diff --git a/docs/guide.rst b/docs/guide.rst index 1e71c6f2..17826ab4 100644 --- a/docs/guide.rst +++ b/docs/guide.rst @@ -99,5 +99,5 @@ SLEIGH & P-Code References -------------------------- Extensive documentation covering SLEIGH and P-Code is available online: -* `SLEIGH, P-Code Introduction `_ -* `P-Code Reference Manual `_ \ No newline at end of file +* `SLEIGH, P-Code Introduction `_ +* `P-Code Reference Manual `_ \ No newline at end of file diff --git a/docs/index.rst b/docs/index.rst index d7ff7dc1..aa093e84 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,7 +1,7 @@ pypcode documentation ===================== pypcode is a machine code disassembly and IR translation library for Python using the -excellent `SLEIGH `__ library from the `Ghidra `__ framework (version 12.0.2). +excellent `SLEIGH `__ library from the `Ghidra `__ framework (version 12.1). This library was created primarily for use with `angr `__, which provides analyses and symbolic execution of p-code. diff --git a/pypcode/processors/68000/data/languages/68000.pspec b/pypcode/processors/68000/data/languages/68000.pspec index 14df2cbd..6bb45ee4 100644 --- a/pypcode/processors/68000/data/languages/68000.pspec +++ b/pypcode/processors/68000/data/languages/68000.pspec @@ -3,6 +3,7 @@ + diff --git a/pypcode/processors/8051/data/languages/80251.sinc b/pypcode/processors/8051/data/languages/80251.sinc index 2658335a..97662df2 100644 --- a/pypcode/processors/8051/data/languages/80251.sinc +++ b/pypcode/processors/8051/data/languages/80251.sinc @@ -15,6 +15,7 @@ define token srcDestByte (8) drk03 = (0,3) # constraint bits d7 = (7,7) + d67 = (6,7) d57 = (5,7) d47 = (4,7) s3 = (3,3) @@ -36,6 +37,7 @@ define token srcDestByte2 (8) drk03_ = (0,3) # constraint bits d7_ = (7,7) + d67_ = (6,7) d57_ = (5,7) s3_ = (3,3) s13_ = (1,3) @@ -85,13 +87,13 @@ attach variables [ wrj47_d2 ] [ # NOTE: must use constraints DRK, DRKD and DRKS attach variables [ drk47 drk03 drk47_ drk03_ ] [ DR0 DR4 DR8 DR12 DR16 DR20 DR24 DR28 - DPX SPX _ _ _ _ _ _ + _ _ _ _ _ _ DPX SPX ]; -@define DRK47 "drk47 & (d7=0 | d57=4)" # constraint for using drk47 -@define DRK03 "drk03 & (s3=0 | s13=4)" # constraint for using drk03 -@define DRK47_ "drk47_ & (d7_=0 | d57_=4)" # constraint for using drk47_ - +@define DRK47 "drk47 & (d7=0 | d67=3)" # constraint for using drk47 +@define DRK03 "drk03 & (s3=0 | s23=3)" # constraint for using drk03 +@define DRK47_ "drk47_ & (d7_=0 | d67_=3)" # constraint for using drk47_ + AtWRjb: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:1 ptr; } AtWRjw: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:2 ptr; } @@ -497,7 +499,7 @@ macro pop24(val) { # MOVH DRk,#data16 -:MOVH drk47,Data16x0 is $(GROUP3) & ophi=7 & oplo=14; $(DRK47) & s03=12; Data16x0 { drk47 = (drk47 & 0xffff0000) | (Data16x0 << 16); } +:MOVH drk47,Data16x0 is $(GROUP3) & ophi=7 & oplo=0xa; $(DRK47) & s03=0xc; Data16x0 { drk47 = (drk47 & 0xffff) | (Data16x0 << 16); } # MOVS WRj,Rm :MOVZ wrj47,rm03 is $(GROUP3) & ophi=1 & oplo=10; wrj47 & rm03 { wrj47 = sext(rm03); } diff --git a/pypcode/processors/8051/data/languages/8051_main.sinc b/pypcode/processors/8051/data/languages/8051_main.sinc index 22700c13..219a9760 100644 --- a/pypcode/processors/8051/data/languages/8051_main.sinc +++ b/pypcode/processors/8051/data/languages/8051_main.sinc @@ -34,7 +34,7 @@ define space BITS type=ram_space size=2; # EXTERNAL - 0x010000-0x01ffff # INTERNAL - 0x000000-0x0000ff -@elif defined(MCS51) +@elif defined(MCS51) || defined(CIP51) @if defined(PTRSIZE) @else @@ -47,12 +47,64 @@ define space BITS type=ram_space size=2; # @define SP_SIZE 1 +define space RAM type=ram_space size=1; define space CODE type=ram_space size=$(PTRSIZE) default; define space INTMEM type=ram_space size=1; define space EXTMEM type=ram_space size=2; +@if defined(CIP51) +# +# CIP-51 allows up to 256 128-byte pages of these, or 32768 bytes, so two address bytes +# are needed for SFR space. +# +# At execution, SFR page selection uses the 8-bit SFRPAGE SFR to provide the page number, +# which effectively is the upper byte of SFR's full address. +# +# The devices covered in the F12x/13x datasheet only have 5 SFR pages and numbers them 0, +# 1, 2, 3, and F. The datasheet doesn't go into detail about SFRPAGE bits 2 to 6, but +# I suppose that for Ghidra instruction decoding it would suffice to just decode the full +# byte. A custom analyzer or script could check for the use of undefined SFRPAGEs. +# +define space SFR type=ram_space size=2; +@else +# +# Intel MCS-51 devices have a maximum of 128 SFRs and a byte-wide address suffices +# define space SFR type=ram_space size=1; +@endif define space BITS type=ram_space size=1; +@if defined(CIP51) +# Per the datasheet https://www.silabs.com/documents/public/data-sheets/C8051F12x-13x.pdf +# (rev 1.4) +# on-chip (internal) flash program/data memory addresses are +# 00000 - 1fbff F120/1/2/3/4/5/6/7, F130/1 +# 00000 - 0ffff F132/3 +# All of the 12x/13x chips covered by the datasheet have +# on-chip scratchpad (i.e. data only) flash: +# 20000 - 200FF +# So allowing 3 address bytes for CIP51 will cover the entire address range for the +# on-chip (internal) flash +define space IFLASH type=ram_space size=3; +# +# As with Intel's original MCS-51 architecture, CIP-51 "internal" ordinary RAM resides on +# the processor chip and uses single-byte addressing. +# +# The lower half of internal RAM can be accessed either directly (by encoding an 8 bit +# address in the opcode) or indirectly (via an address stored in R0 or R1). +# +# The upper half of internal RAM can be accessed only indirectly, again via R0 or R1. +# +# 00 - 7f directly and indirectly addressable +# 80 - ff indirectly addressable only (via R0 or R1) +# +# In CIP51 chips, addresses in the upper half of the range (that is, 80 - FF), when used +# directly, rather than accessing ordinary RAM get mapped to the chip's special function +# register RAM. +# + +define space XRAM type=ram_space size=2; +@endif + @elif defined(MCS80390) @define PTRSIZE 3 @@ -117,7 +169,7 @@ define register offset=0x38 size=1 [ R56 DPXL DPH DPL R60 R61 SPH ]; define register offset=0x3A size=2 [ DPTR ]; define register offset=0x38 size=4 [ DPX SPX ]; -@elif defined(MCS51) || defined(MCS80390) || defined(MX51) +@elif defined(MCS51) || defined(MCS80390) || defined(MX51) || defined(CIP51) define register offset=0x00 size=4 [ R0R1R2R3 ]; define register offset=0x01 size=3 [ R1R2R3 ]; # Used as R3R2R1 @@ -129,7 +181,7 @@ define register offset=0x05 size=3 [ R5R6R7 ]; define register offset=0x0A size=1 [ B ACC ]; # relocated to facilitate AB 16-bit access define register offset=0x0A size=2 [ AB ]; -@if defined(MCS51) || defined(MX51) +@if defined(MCS51) || defined(MX51) || defined(CIP51) define register offset=0x82 size=2 [ DPTR ]; define register offset=0x82 size=1 [ DPH DPL ]; # relocated to facilitate DPTR 16-bit access @elif defined(MCS80390) @@ -192,7 +244,7 @@ define context contextReg # GROUP3 - MCS251 instructions in 0x60-0xff range @define GROUP3 "((srcMode=0 & A5Prefix=1) | (srcMode=1 & A5Prefix=0))" -@elif defined(MCS51) || defined(MCS80390) || defined(MX51) +@elif defined(MCS51) || defined(MCS80390) || defined(MX51) || defined(CIP51) @define GROUP1 "epsilon" @define GROUP2 "epsilon" @@ -352,7 +404,7 @@ macro push8(val) { SPX = SPX + 1; ptr:3 = SPX:3; *[RAM]:1 ptr = val; -@elif defined(MCS51) || defined(MCS80390) +@elif defined(MCS51) || defined(MCS80390) || defined(CIP51) SP = SP + 1; *[INTMEM]:1 SP = val; @elif defined(MX51) @@ -384,16 +436,16 @@ macro push16(val) { *[RAM]:1 SPX:3 = al; SPX = SPX + 1; *[RAM]:1 SPX:3 = ah; - -@elif defined(MCS51) + +@elif defined(MCS51) || defined(CIP51) al:1 = val:1; ah:1 = val(1); - + SP = SP + 1; *[INTMEM]:1 SP = al; - SP = SP + 1; + SP = SP + 1; *[INTMEM]:1 SP = ah; - + @elif defined(MX51) # dptr push #ptr:1 = SP + 1; @@ -432,7 +484,7 @@ macro pop8(val) { ptr:3 = SPX:3; val = *[RAM]:1 ptr; SPX = SPX - 1; -@elif defined(MCS51) || defined(MCS80390) +@elif defined(MCS51) || defined(MCS80390) || defined(CIP51) val = *[INTMEM]:1 SP; SP = SP - 1; @elif defined(MX51) @@ -477,9 +529,9 @@ macro pop16(val) { SPX = SPX - 1; val = (zext(ah) << 8) | zext(al); - -@elif defined(MCS51) - + +@elif defined(MCS51) || defined(CIP51) + ah:1 = *[INTMEM]:1 SP; SP = SP - 1; al:1 = *[INTMEM]:1 SP; @@ -512,7 +564,7 @@ DPTRreg: DPTR is ophi & DPTR { export DPTR; } @if defined(MCS251) ADPTR: "@A+"^DPTR is ophi & DPTR { ptr:3 = 0xff0000 + zext(DPTR) + zext(ACC); export ptr; } -@elif defined(MCS51) +@elif defined(MCS51) || defined(CIP51) ADPTR: "@A+"^DPTR is ophi & DPTR { ptr:$(PTRSIZE) = zext(DPTR) + zext(ACC); export ptr; } @elif defined(MCS80390) ADPTR: "@A+"^DPTR is ophi & DPTR { ptr:3 = zext(DPTR) + zext(ACC); export ptr; } @@ -524,7 +576,7 @@ APC: "@A+PC" is epsilon { tmp:$(PTRSIZE) = inst_next + zext(ACC); expor @if defined(MCS251) ATDPTR: "@"^DPTR is ophi & DPTR { ptr:3 = 0x010000 + zext(DPTR); export *:1 ptr; } # 8051 External data address mapped into RAM space -@elif defined(MCS51) +@elif defined(MCS51) || defined(CIP51) ATDPTR: "@"^DPTR is ophi & DPTR { ptr:2 = DPTR; export *[EXTMEM]:1 ptr; } @elif defined(MCS80390) ATDPTR: "@"^DPTR is ophi & DPTR { ptr:3 = zext(DPTR); export *[EXTMEM]:1 ptr; } @@ -536,13 +588,13 @@ ATDPTR: "@"^DPTR is ophi & DPTR { ptr:3 = zext(DPTR); export *[RAM]:1 ptr; } Ri: @ri is ri { ptr:3 = zext(ri); export *[RAM]:1 ptr; } @elif defined(MX51) Ri: @ri is ri { ptr:3 = zext(ri) + 0x7f0000; export *[RAM]:1 ptr; } -@elif defined(MCS51) || defined(MCS80390) +@elif defined(MCS51) || defined(MCS80390) || defined(CIP51) Ri: @ri is ri { export *[INTMEM]:1 ri; } @endif @if defined(MCS251) RiX: @ri is ri { ptr:3 = 0x010000 + zext(ri); export *:1 ptr; } # 8051 8-bit External data address mapped into RAM space -@elif defined(MCS51) +@elif defined(MCS51) || defined(CIP51) RiX: @ri is ri { ptr:2 = zext(ri); export *[EXTMEM]:1 ptr; } # limited to 8-bit external data address (I/O state can be used to produce 16-bit addr) @elif defined(MCS80390) RiX: @ri is ri { ptr:3 = zext(ri); export *[EXTMEM]:1 ptr; } # tocheck @@ -560,7 +612,7 @@ Data24: "#"data24 is data24 { export *[const]:3 data24; } Direct: mainreg is bank=0 & mainreg { export *[RAM]:1 mainreg; } @elif defined(MX51) Direct: mainreg is bank=0 & mainreg { tmp:3 = mainreg + 0x7f0000; export *[RAM]:1 tmp; } -@elif defined(MCS51) || defined(MCS80390) +@elif defined(MCS51) || defined(MCS80390) || defined(CIP51) Direct: mainreg is bank=0 & mainreg { export *[INTMEM]:1 mainreg; } @endif Direct: direct is bank=1 & direct { export *[SFR]:1 direct; } @@ -580,7 +632,7 @@ Direct: DPXL is bank=1 & direct=0x84 & DPXL { export DPXL; } Direct2: mainreg2 is bank2=0 & mainreg2 { export *[RAM]:1 mainreg2; } @elif defined(MX51) Direct2: mainreg2 is bank2=0 & mainreg2 { tmp:3 = mainreg2 + 0x7f0000; export *[RAM]:1 tmp; } -@elif defined(MCS51) || defined(MCS80390) +@elif defined(MCS51) || defined(MCS80390) || defined(CIP51) Direct2: mainreg2 is bank2=0 & mainreg2 { export *[INTMEM]:1 mainreg2; } @endif Direct2: direct2 is bank2=1 & direct2 { export *[SFR]:1 direct2; } @@ -601,7 +653,7 @@ BitAddr: bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 6)+sfrb BitAddr: bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[BITS]:1 bitaddr; } BitAddr2: "/"bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 6)+sfrbit; ] { export *[BITS]:1 bitaddr; } BitAddr2: "/"bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[BITS]:1 bitaddr; } -@elif defined(MCS51) || defined(MCS80390) || defined(MX51) +@elif defined(MCS51) || defined(MCS80390) || defined(MX51) || defined(CIP51) ## ##TODO !!! 8051 SFRBITS bit overlay block is probably incorrect since there is not a 1:1 mapping to the SFR space ## While the BitAddr is only used for disassembly markup, and labels come from pspec, the underlying data will @@ -622,11 +674,11 @@ BitByteAddr: PSW is bitbank=1 & sfrbyte=0x1A & sfrbit & PSW { export PSW; } BitByteAddr: byteaddr is bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0x20; ] { export *[RAM]:1 byteaddr; } @elif defined(MX51) BitByteAddr: byteaddr is bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0x20; ] { tmp:3 = byteaddr + 0x7f0000; export *[RAM]:1 tmp; } -@elif defined(MCS51) || defined(MCS80390) +@elif defined(MCS51) || defined(MCS80390) || defined(CIP51) BitByteAddr: byteaddr is bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0x20; ] { export *[INTMEM]:1 byteaddr; } @endif -@if defined(MCS251) || defined(MX51) +@if defined(MCS251) || defined(MX51) || defined(CIP51) Addr11: relAddr is aopaddr & adata [ relAddr = (inst_next $and 0xfff800)+(aopaddr*256)+adata; ] { export *:1 relAddr; } Addr16: addr is addr16 [ addr = (inst_next $and 0xff0000) + addr16; ] { export *:1 addr; } @elif defined(MCS51) @@ -856,21 +908,21 @@ Rel16: relAddr is rel16 [ relAddr=inst_next+rel16; ] { export *:1 relAdd :PUSH Direct is $(GROUP1) & ophi=12 & oplo=0; Direct { push8(Direct); } -:RET is $(GROUP1) & ophi=2 & oplo=2 { +:RET is $(GROUP1) & ophi=2 & oplo=2 { @if defined(MCS251) || defined(MX51) -pc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3]; -@elif defined(MCS51) -pc:2 = 0; pop16(pc); return[pc]; +pc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3]; +@elif defined(MCS51) || defined(CIP51) +pc:2 = 0; pop16(pc); return[pc]; @elif defined(MCS80390) pc:3 = 0; pop24(pc); return[pc]; @endif } -:RETI is $(GROUP1) & ophi=3 & oplo=2 { +:RETI is $(GROUP1) & ophi=3 & oplo=2 { @if defined(MCS251) || defined(MX51) -pc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3]; -@elif defined(MCS51) -pc:2 = 0; pop16(pc); return[pc]; +pc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3]; +@elif defined(MCS51) || defined(CIP51) +pc:2 = 0; pop16(pc); return[pc]; @elif defined(MCS80390) pc:3 = 0; pop24(pc); return[pc]; @endif diff --git a/pypcode/processors/8051/data/languages/cip-51.slaspec b/pypcode/processors/8051/data/languages/cip-51.slaspec new file mode 100644 index 00000000..737aaf74 --- /dev/null +++ b/pypcode/processors/8051/data/languages/cip-51.slaspec @@ -0,0 +1,4 @@ +@define CIP51 "" + +@include "8051_main.sinc" + diff --git a/pypcode/processors/8051/data/languages/keil-cx51.cspec b/pypcode/processors/8051/data/languages/keil-cx51.cspec new file mode 100644 index 00000000..14efe890 --- /dev/null +++ b/pypcode/processors/8051/data/languages/keil-cx51.cspec @@ -0,0 +1,118 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pypcode/processors/AARCH64/data/extensions/objc/chkstk_darwin_fixup.xml b/pypcode/processors/AARCH64/data/extensions/objc/chkstk_darwin_fixup.xml new file mode 100644 index 00000000..75f2847b --- /dev/null +++ b/pypcode/processors/AARCH64/data/extensions/objc/chkstk_darwin_fixup.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/pypcode/processors/AARCH64/data/extensions/objc/objc_getProperty_fixup.xml b/pypcode/processors/AARCH64/data/extensions/objc/objc_getProperty_fixup.xml new file mode 100644 index 00000000..1462b86f --- /dev/null +++ b/pypcode/processors/AARCH64/data/extensions/objc/objc_getProperty_fixup.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/pypcode/processors/AARCH64/data/extensions/objc/objc_load_fixup.xml b/pypcode/processors/AARCH64/data/extensions/objc/objc_load_fixup.xml new file mode 100644 index 00000000..b199fb70 --- /dev/null +++ b/pypcode/processors/AARCH64/data/extensions/objc/objc_load_fixup.xml @@ -0,0 +1,9 @@ + + + + + + + diff --git a/pypcode/processors/AARCH64/data/extensions/objc/objc_msgSend_stub.xml b/pypcode/processors/AARCH64/data/extensions/objc/objc_msgSend_stub.xml new file mode 100644 index 00000000..139b600c --- /dev/null +++ b/pypcode/processors/AARCH64/data/extensions/objc/objc_msgSend_stub.xml @@ -0,0 +1,187 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pypcode/processors/AARCH64/data/extensions/objc/objc_release_fixup.xml b/pypcode/processors/AARCH64/data/extensions/objc/objc_release_fixup.xml new file mode 100644 index 00000000..997f1cb1 --- /dev/null +++ b/pypcode/processors/AARCH64/data/extensions/objc/objc_release_fixup.xml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/AARCH64/data/extensions/objc/objc_retain_fixup.xml b/pypcode/processors/AARCH64/data/extensions/objc/objc_retain_fixup.xml new file mode 100644 index 00000000..81a4cc99 --- /dev/null +++ b/pypcode/processors/AARCH64/data/extensions/objc/objc_retain_fixup.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/AARCH64/data/extensions/objc/objc_setProperty_fixup.xml b/pypcode/processors/AARCH64/data/extensions/objc/objc_setProperty_fixup.xml new file mode 100644 index 00000000..e26655ea --- /dev/null +++ b/pypcode/processors/AARCH64/data/extensions/objc/objc_setProperty_fixup.xml @@ -0,0 +1,12 @@ + + + + + + + + + + diff --git a/pypcode/processors/AARCH64/data/extensions/objc/objc_store_fixup.xml b/pypcode/processors/AARCH64/data/extensions/objc/objc_store_fixup.xml new file mode 100644 index 00000000..7c72808a --- /dev/null +++ b/pypcode/processors/AARCH64/data/extensions/objc/objc_store_fixup.xml @@ -0,0 +1,9 @@ + + + + + + + diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64.ldefs b/pypcode/processors/AARCH64/data/languages/AARCH64.ldefs index 58bb4410..633ec3d4 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64.ldefs +++ b/pypcode/processors/AARCH64/data/languages/AARCH64.ldefs @@ -13,6 +13,7 @@ + diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64.opinion b/pypcode/processors/AARCH64/data/languages/AARCH64.opinion index 6d130007..2655181d 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64.opinion +++ b/pypcode/processors/AARCH64/data/languages/AARCH64.opinion @@ -5,6 +5,12 @@ + + + + + + diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64.pspec b/pypcode/processors/AARCH64/data/languages/AARCH64.pspec index 0a17d5c1..abd08719 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64.pspec +++ b/pypcode/processors/AARCH64/data/languages/AARCH64.pspec @@ -7,6 +7,7 @@ + diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc b/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc index 35ada38a..2811de5d 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc +++ b/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc @@ -2841,7 +2841,7 @@ is size.ldstr=3 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR :ldar Rt_GPR32, addrReg is size.ldstr=2 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_1620=0b11111 & b_15=1 & b_1014=0b11111 & addrReg & Rt_GPR32 & Rt_GPR64 { - Rt_GPR64 = *addrReg; + Rt_GPR64 = zext(*:4 addrReg); } # C6.2.146 LDARB page C6-1516 line 89986 MATCH x08c08000/mask=xffe08000 @@ -3049,7 +3049,7 @@ is b_3031=0b10 & b_2529=0b10100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR64 & addrP is b_2531=0b0110100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64 { local addrval1:8 = sext(*:4 addrPairIndexed); - local addrval2:8 = sext(*:4 (addrPairIndexed + 8)); + local addrval2:8 = sext(*:4 (addrPairIndexed + 4)); Rt_GPR64 = addrval1; Rt2_GPR64 = addrval2; } @@ -8366,4 +8366,211 @@ is b_1231=0b11010101000000000100 & b_0007=0b00111111 OV = tmpOV; } +# FEAT_CSSC +:abs Rd_GPR32, Rn_GPR32 +is sf=0 & b_30=1 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1620=0x0 & b_1015=0x8 & Rd_GPR32 & Rn_GPR32 +{ + local tmp = Rn_GPR32; + local test = tmp s< 0; + Rd_GPR32 = (zext(!test)*tmp) + (zext(test)*(-tmp)); +} +:abs Rd_GPR64, Rn_GPR64 +is sf=1 & b_30=1 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1620=0x0 & b_1015=0x8 & Rd_GPR64 & Rn_GPR64 +{ + local tmp = Rn_GPR64; + local test = tmp s< 0; + Rd_GPR64 = (zext(!test)*tmp) + (zext(test)*(-tmp)); +} + +:cnt Rd_GPR32, Rn_GPR32 +is sf=0 & b_30=1 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1620=0x0 & b_1015=0x7 & Rd_GPR32 & Rn_GPR32 +{ + local tmp = Rn_GPR32; + Rd_GPR32 = popcount(tmp); +} + +:cnt Rd_GPR64, Rn_GPR64 +is sf=1 & b_30=1 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1620=0x0 & b_1015=0x7 & Rd_GPR64 & Rn_GPR64 +{ + local tmp = Rn_GPR64; + Rd_GPR64 = popcount(tmp); +} + +:ctz Rd_GPR32, Rn_GPR32 +is sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x6 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + # equivalent to RBIT; CLZ + local tmp = Rn_GPR32; + tmp = (((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1)); + tmp = (((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2)); + tmp = (((tmp & 0xf0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f) << 4)); + tmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8)); + tmp = ((tmp >> 16) | (tmp << 16)); + Rd_GPR64 = lzcount(tmp); +} + +:ctz Rd_GPR64, Rn_GPR64 +is sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x6 & Rn_GPR64 & Rd_GPR64 +{ + # equivalent to RBIT; CLZ + local tmp = Rn_GPR64; + tmp = (((tmp & 0xaaaaaaaaaaaaaaaa) >> 1) | ((tmp & 0x5555555555555555) << 1)); + tmp = (((tmp & 0xcccccccccccccccc) >> 2) | ((tmp & 0x3333333333333333) << 2)); + tmp = (((tmp & 0xf0f0f0f0f0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f0f0f0f0f) << 4)); + tmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8)); + tmp = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16)); + tmp = ((tmp >> 32) | (tmp << 32)); + Rd_GPR64 = lzcount(tmp); +} + +cssc_simm32: "#"^val is simm8 [ val = simm8 * 1; ] { export *[const]:4 val; } +cssc_simm64: "#"^val is simm8 [ val = simm8 * 1; ] { export *[const]:8 val; } + +cssc_imm32: "#"^val is imm8 [ val = imm8 * 1; ] { export *[const]:4 val; } +cssc_imm64: "#"^val is imm8 [ val = imm8 * 1; ] { export *[const]:8 val; } + + +:smax Rd_GPR32, Rn_GPR32, cssc_simm32 +is sf=0 & b_30=0 & S=0 & b_2428=0x11 & b_2123=0x6 & b_1820=0x0 & Rd_GPR32 & Rn_GPR32 & cssc_simm32 +{ + local tmp = Rn_GPR32; + local tmp2 = cssc_simm32; + local test:1 = tmp s>= tmp2; + Rd_GPR32 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:smax Rd_GPR64, Rn_GPR64, cssc_simm64 +is sf=1 & b_30=0 & S=0 & b_2428=0x11 & b_2123=0x6 & b_1820=0x0 & Rd_GPR64 & Rn_GPR64 & cssc_simm64 +{ + local tmp = Rn_GPR64; + local tmp2 = cssc_simm64; + local test = tmp s>= tmp2; + Rd_GPR64 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:smax Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_30=0 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1015=0x18 & Rd_GPR32 & Rn_GPR32 & Rm_GPR32 +{ + local tmp = Rn_GPR32; + local tmp2 = Rm_GPR32; + local test = tmp s>= tmp2; + Rd_GPR32 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:smax Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_30=0 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1015=0x18 & Rd_GPR64 & Rn_GPR64 & Rm_GPR64 +{ + local tmp = Rn_GPR64; + local tmp2 = Rm_GPR64; + local test = tmp s>= tmp2; + Rd_GPR64 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:smin Rd_GPR32, Rn_GPR32, cssc_simm32 +is sf=0 & b_30=0 & S=0 & b_2428=0x11 & b_2123=0x6 & b_1820=0x2 & Rd_GPR32 & Rn_GPR32 & cssc_simm32 +{ + local tmp = Rn_GPR32; + local tmp2 = cssc_simm32; + local test:1 = tmp s<= tmp2; + Rd_GPR32 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:smin Rd_GPR64, Rn_GPR64, cssc_simm64 +is sf=1 & b_30=0 & S=0 & b_2428=0x11 & b_2123=0x6 & b_1820=0x2 & Rd_GPR64 & Rn_GPR64 & cssc_simm64 +{ + local tmp = Rn_GPR64; + local tmp2 = cssc_simm64; + local test = tmp s<= tmp2; + Rd_GPR64 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:smin Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_30=0 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1015=0x1a & Rd_GPR32 & Rn_GPR32 & Rm_GPR32 +{ + local tmp = Rn_GPR32; + local tmp2 = Rm_GPR32; + local test = tmp s<= tmp2; + Rd_GPR32 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:smin Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_30=0 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1015=0x1a & Rd_GPR64 & Rn_GPR64 & Rm_GPR64 +{ + local tmp = Rn_GPR64; + local tmp2 = Rm_GPR64; + local test = tmp s<= tmp2; + Rd_GPR64 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:umax Rd_GPR32, Rn_GPR32, cssc_imm32 +is sf=0 & b_30=0 & S=0 & b_2428=0x11 & b_2123=0x6 & b_1820=0x1 & Rd_GPR32 & Rn_GPR32 & cssc_imm32 +{ + local tmp = Rn_GPR32; + local tmp2 = cssc_imm32; + local test:1 = tmp >= tmp2; + Rd_GPR32 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:umax Rd_GPR64, Rn_GPR64, cssc_imm64 +is sf=1 & b_30=0 & S=0 & b_2428=0x11 & b_2123=0x6 & b_1820=0x1 & Rd_GPR64 & Rn_GPR64 & cssc_imm64 +{ + local tmp = Rn_GPR64; + local tmp2 = cssc_imm64; + local test = tmp >= tmp2; + Rd_GPR64 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:umax Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_30=0 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1015=0x19 & Rd_GPR32 & Rn_GPR32 & Rm_GPR32 +{ + local tmp = Rn_GPR32; + local tmp2 = Rm_GPR32; + local test = tmp >= tmp2; + Rd_GPR32 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:umax Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_30=0 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1015=0x19 & Rd_GPR64 & Rn_GPR64 & Rm_GPR64 +{ + local tmp = Rn_GPR64; + local tmp2 = Rm_GPR64; + local test = tmp >= tmp2; + Rd_GPR64 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:umin Rd_GPR32, Rn_GPR32, cssc_imm32 +is sf=0 & b_30=0 & S=0 & b_2428=0x11 & b_2123=0x6 & b_1820=0x3 & Rd_GPR32 & Rn_GPR32 & cssc_imm32 +{ + local tmp = Rn_GPR32; + local tmp2 = cssc_imm32; + local test:1 = tmp <= tmp2; + Rd_GPR32 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:umin Rd_GPR64, Rn_GPR64, cssc_imm64 +is sf=1 & b_30=0 & S=0 & b_2428=0x11 & b_2123=0x6 & b_1820=0x3 & Rd_GPR64 & Rn_GPR64 & cssc_imm64 +{ + local tmp = Rn_GPR64; + local tmp2 = cssc_imm64; + local test = tmp <= tmp2; + Rd_GPR64 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:umin Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_30=0 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1015=0x1b & Rd_GPR32 & Rn_GPR32 & Rm_GPR32 +{ + local tmp = Rn_GPR32; + local tmp2 = Rm_GPR32; + local test = tmp <= tmp2; + Rd_GPR32 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} + +:umin Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_30=0 & S=0 & b_2428=0x1a & b_2123=0x6 & b_1015=0x1b & Rd_GPR64 & Rn_GPR64 & Rm_GPR64 +{ + local tmp = Rn_GPR64; + local tmp2 = Rm_GPR64; + local test = tmp <= tmp2; + Rd_GPR64 = (zext(test)*tmp) + (zext(!test)*(tmp2)); +} diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64instructions.sinc b/pypcode/processors/AARCH64/data/languages/AARCH64instructions.sinc index f4eea848..03afdd10 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64instructions.sinc +++ b/pypcode/processors/AARCH64/data/languages/AARCH64instructions.sinc @@ -1131,10 +1131,12 @@ define token instrAARCH64 (32) endian = little imm6 = (10,15) aa_imm7 = (15,21) + imm8 = (10,17) imm12 = (10,21) imm16 = (5,20) simm7 = (15,21) signed + simm8 = (10,17) signed simm9 = (12,20) signed simm14 = (5,18) signed simm19 = (5,23) signed diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc b/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc index af8ccb22..4ff3386c 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc +++ b/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc @@ -16042,7 +16042,7 @@ is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b000000 & :sha1h Rd_FPR32, Rn_FPR32 is b_2431=0b01011110 & b_2223=0b00 & b_1721=0b10100 & b_1216=0b00000 & b_1011=0b10 & Rn_FPR32 & Rd_FPR32 & Zd { - Rd_FPR32 = Rn_FPR32 << 30:1; + Rd_FPR32 = Rn_FPR32 << 30:1 | (Rn_FPR32 >> 2:1); zext_zs(Zd); # zero upper 28 bytes of Zd } diff --git a/pypcode/processors/ARM/data/languages/ARM.cspec b/pypcode/processors/ARM/data/languages/ARM.cspec index c116a64d..4eb46f58 100644 --- a/pypcode/processors/ARM/data/languages/ARM.cspec +++ b/pypcode/processors/ARM/data/languages/ARM.cspec @@ -293,19 +293,20 @@ - - - - - - - - - - + + + + + + + + + + + @@ -356,8 +356,7 @@ offset = *:1 (tmpptr + r0); lr = lr + 2 * zext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -374,8 +373,7 @@ offset = *:1 (tmpptr + r0); lr = lr + 2 * sext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -393,8 +391,7 @@ offset = *:2 (tmpptr + index); lr = lr + 2 * sext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -412,8 +409,7 @@ offset = *:2 (tmpptr + index); lr = lr + 2 * zext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -432,8 +428,7 @@ offset = offset * 4; lr = lr + offset; - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> diff --git a/pypcode/processors/ARM/data/languages/ARM.sinc b/pypcode/processors/ARM/data/languages/ARM.sinc index 9bdd8234..0f3b5806 100644 --- a/pypcode/processors/ARM/data/languages/ARM.sinc +++ b/pypcode/processors/ARM/data/languages/ARM.sinc @@ -15,7 +15,6 @@ define register offset=0x0084 size=4 [ r14_svc r13_svc spsr_svc ]; define register offset=0x0090 size=8 [ mult_dat8 ]; # Special internal register for dealing with multiple stores/loads define register offset=0x0090 size=16 [ mult_dat16 ]; # Special internal register for dealing with multiple stores/loads define register offset=0x00A0 size=4 [ fpsr ]; # floating point state register (for FPA10 floating-point accelerator) -define register offset=0x0078 size=1 [ ISAModeSwitch ]; # generic name for TB ThumbBit - set same as TB @define FPSCR_N "fpscr[31,1]" @define FPSCR_Z "fpscr[30,1]" @@ -75,8 +74,10 @@ define register offset=0x0200 size=4 [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 c @endif # SIMD -@if defined(CORTEX) - define register offset=0x400 size=4 [ msplim psplim ]; +@if defined(VERSION_8M) + define register offset=0x400 size=4 [ msplim psplim vpr fpccr ]; + define register offset=0x420 size=2 [ vpr_p0]; # shadow register used with VPT +@define VPR_P0 "vpr[0,16]" @endif # Define context bits @@ -103,17 +104,17 @@ define context contextreg cond_base = (6,8) # shift mask for controlling shift cond_shft = (9,13) # mask and lower bit of it condition field itmode = (5,5) # true if in ITBlock mode - @endif # Transient context bits - counter = (14,18) # 0 to 7 counter (for building variable length register lists) -# dreg = (17,21) # D register (attached, for building register lists) -# sreg = (17,21) # S register (attached, for building register lists) + counter = (14,18) # 0 to 31 counter (for building variable length register lists) +# dreg = (19,23) # D register (attached, for building register lists) +# sreg = (19,23) # S register (attached, for building register lists) regNum = (19,23) # D register number (see dreg) + sdOv = (24,24) counter2 = (24,26) # 0 to 7 counter (for building variable length register lists) -# dreg2 = (25,29) # 2nd D register (attached, for building register lists) -# sreg2 = (25,29) # 2nd S register (attached, for building register lists) +# dreg2 = (27,31) # 2nd D register (attached, for building register lists) +# sreg2 = (27,31) # 2nd S register (attached, for building register lists) reg2Num = (27,31) # 2nd D register number (see dreg2) # --- do not allow any field to span 32-bit boundary --- regInc = (32,33) # Pair register increment @@ -193,7 +194,7 @@ define pcodeop ReverseBitOrder; define pcodeop SendEvent; define pcodeop setEndianState; -# Copies ISAModeSwitch to TMode +# Copies TB to TMode define pcodeop setISAMode; macro affectflags() { @@ -204,14 +205,9 @@ macro affect_resflags() { ZR = tmpZR; NG = tmpNG; } -macro SetISAModeSwitch(value) { - ISAModeSwitch = value; - TB = ISAModeSwitch; -} - macro SetThumbMode(value) { - SetISAModeSwitch(value); - setISAMode(); + TB = value; + setISAMode(TB); } # @@ -239,11 +235,12 @@ macro LoadWritePC(addr) { } # Branch depends on version +# ONLY USED IN ARMinstructions.sinc for thumb use BranchWritePC macro ALUWritePC(addr) { @if defined(VERSION_7) BXWritePC(addr); @else - BranchWritePC(addr); + BranchWritePC(addr & 0xfffffffc); @endif } diff --git a/pypcode/processors/ARM/data/languages/ARM8m_be.slaspec b/pypcode/processors/ARM/data/languages/ARM8m_be.slaspec index 5f551fc7..6eebf98c 100644 --- a/pypcode/processors/ARM/data/languages/ARM8m_be.slaspec +++ b/pypcode/processors/ARM/data/languages/ARM8m_be.slaspec @@ -11,7 +11,7 @@ @define VERSION_8 "" @define SIMD "" @define CDE "" -@define CORTEX "" +@define VERSION_8M "" @define VFPv3 "" @define VFPv4 "" diff --git a/pypcode/processors/ARM/data/languages/ARM8m_le.slaspec b/pypcode/processors/ARM/data/languages/ARM8m_le.slaspec index fb178aa8..e278c618 100644 --- a/pypcode/processors/ARM/data/languages/ARM8m_le.slaspec +++ b/pypcode/processors/ARM/data/languages/ARM8m_le.slaspec @@ -11,7 +11,7 @@ @define VERSION_8 "" @define SIMD "" @define CDE "" -@define CORTEX "" +@define VERSION_8M "" @define VFPv3 "" @define VFPv4 "" diff --git a/pypcode/processors/ARM/data/languages/ARMCortex.pspec b/pypcode/processors/ARM/data/languages/ARMCortex.pspec index e6bf29b3..3c0205a1 100644 --- a/pypcode/processors/ARM/data/languages/ARMCortex.pspec +++ b/pypcode/processors/ARM/data/languages/ARMCortex.pspec @@ -7,6 +7,7 @@ + @@ -18,7 +19,11 @@ - + + + + + diff --git a/pypcode/processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/pypcode/processors/ARM/data/languages/ARMTHUMBinstructions.sinc index 0f46b8f4..1f6b9f8c 100644 --- a/pypcode/processors/ARM/data/languages/ARMTHUMBinstructions.sinc +++ b/pypcode/processors/ARM/data/languages/ARMTHUMBinstructions.sinc @@ -237,7 +237,7 @@ macro th_add_with_carry_flags(op1,op2){ macro th_sub_with_carry_flags(op1, op2){ local result = op1 - op2; tmpCY = (op1 > op2) || (result < zext(CY)); - tmpOV = sborrow(op1,op2) ^^ sborrow(result,zext(!CY)); + tmpOV = sborrow(op1,op2) ^^ sborrow(result,zext(!CY)); } @@ -516,6 +516,15 @@ thBitWidth: "#"^w is imm3_shft & imm2_shft & thc0004 [ w = thc0004 - ((imm3_shft @endif # VERSION_6T2 || VERSION_7 +thAddrShift:[Rn0003,Rm0003] is Rn0003; thc0405=0 & Rm0003 { + local addr = Rn0003 + Rm0003; + export addr; +} + +thAddrShift: [Rn0003,Rm0003,"lsl #"^thc0405] is Rn0003; thc0405 & Rm0003 { + local addr = Rn0003 + (Rm0003 << thc0405); + export addr; +} ##################### ###### thshift2 ###### @@ -523,7 +532,7 @@ thBitWidth: "#"^w is imm3_shft & imm2_shft & thc0004 [ w = thc0004 - ((imm3_shft @if defined(VERSION_6T2) || defined(VERSION_7) -thshift2: Rm0003 is imm3_shft=0 & imm2_shft=0 & thc0405=0 & Rm0003 +thshift2: Rm0003 is imm3_shft=0 & imm2_shft=0 & thc0405=0 & Rm0003 { shift_carry = CY; export Rm0003; } @@ -1193,10 +1202,11 @@ with : ARMcondCk=1 { Hrd0002 = Hrd0002 + Hrm0305; } +# Destination is PC :add^ItCond Hrd0002,Hrm0305 is TMode=1 & ItCond & op8=0x44 & Hrd0002 & Hrm0305 & hrd0002=7 & h1=1 { build ItCond; - dest:4 = Hrd0002 + Hrm0305; + dest:4 = (Hrd0002 + Hrm0305) & 0xfffffffe; # Simple branch, mask off the last bit BranchWritePC(dest); goto [pc]; } @@ -2215,10 +2225,10 @@ define pcodeop ExclusiveAccess; build RtGotoCheck; } -:ldr^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf85 & Rn0003; Rt1215 & RtGotoCheck & thc1111=0 & sop0610=0 & thc0405 & Rm0003 -{ +:ldr^ItCond^".w" Rt1215,thAddrShift is TMode=1 & ItCond & (op4=0xf85; Rt1215 & RtGotoCheck & thc1111=0 & sop0610=0) & thAddrShift { build ItCond; - local tmp = Rn0003 + (Rm0003 << thc0405); + build thAddrShift; + local tmp = thAddrShift; Rt1215 = *tmp; build RtGotoCheck; } @@ -2256,10 +2266,10 @@ define pcodeop ExclusiveAccess; Rt1215 = zext(tmp); } -:ldrb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf81 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 -{ - build ItCond; - local tmp = Rn0003 + (Rm0003 << thc0405); +:ldrb^ItCond^".w" Rt1215,thAddrShift is TMode=1 & ItCond & (op4=0xf81; Rt1215 & thc1111=0 & sop0610=0) & thAddrShift { + build ItCond; + build thAddrShift; + local tmp = thAddrShift; val:1 = *tmp; Rt1215 = zext(val); } @@ -2305,14 +2315,14 @@ define pcodeop ExclusiveAccess; { build ItCond; addr:4 = Rn0003 - immed8; - HintPreloadDataForWrite(addr); + HintPreloadDataForWrite(addr); } -:pldw^ItCond Rn0003,Rm0003,"lsl #"^thc0405 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003 -{ +:pldw^ItCond thAddrShift is TMode=1 & ItCond & (op6=0x3e0 & thwbit=1 & thc0404=1; op8=0xf0 & thc0607=0) & thAddrShift { build ItCond; - addr:4 = Rn0003 + (Rm0003 << thc0405); - HintPreloadDataForWrite(addr); + build thAddrShift; + addr:4 = thAddrShift; + HintPreloadDataForWrite(addr); } @@ -2320,12 +2330,14 @@ define pcodeop ExclusiveAccess; :ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf83 & sop0003=15; Rt1215) & PcrelOffset12 { build ItCond; + build PcrelOffset12; local tmp = PcrelOffset12:2; Rt1215 = zext(tmp); } :ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8b & sop0003=15; Rt1215) & PcrelOffset12 { build ItCond; + build PcrelOffset12; tmp:2 = PcrelOffset12:2; Rt1215 = zext(tmp); } @@ -2346,11 +2358,11 @@ define pcodeop ExclusiveAccess; Rt1215 = zext(tmp); } -:ldrh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf83 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 -{ +:ldrh^ItCond^".w" Rt1215,thAddrShift is TMode=1 & ItCond & (op4=0xf83 ; Rt1215 & thc1111=0 & sop0610=0) & thAddrShift { build ItCond; - local tmp = Rn0003 + (Rm0003 << thc0405); - val:2 = *tmp; + build thAddrShift; + local addr = thAddrShift; + val:2 = *addr; Rt1215 = zext(val); } @@ -2364,7 +2376,7 @@ define pcodeop ExclusiveAccess; # pli moevd above ldrsb to avoid conflict for ldrsb when Rt == 1111 -:pli^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op4=0xf99 & Rn0003; op12=0xf & offset12 +:pli^ItCond [Rn0003,"#"^offset12] is TMode=1 & ItCond & op4=0xf99 & Rn0003; op12=0xf & offset12 { build ItCond; addr:4 = Rn0003 + offset12; @@ -2381,13 +2393,14 @@ define pcodeop ExclusiveAccess; :pli^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12 { build ItCond; + build PcrelOffset12; HintPreloadInstruction(PcrelOffset12); } -:pli^ItCond Rn0003,Rm0003"lsl #"^thc0405 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op6=0x3c0 & thc0405 & Rm0003 -{ +:pli^ItCond thAddrShift is TMode=1 & ItCond & (op4=0xf91; op6=0x3c0) & thAddrShift { build ItCond; - addr:4 = Rn0003 + (Rm0003 << thc0405); + build thAddrShift; + addr:4 = thAddrShift; HintPreloadInstruction(addr); } @@ -2395,16 +2408,17 @@ define pcodeop ExclusiveAccess; # overlaps patterns with the other ldrsb intructions when Rn==1111, therefore it must occur first :ldrsb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12 { - build ItCond; - tmp:1 = *PcrelOffset12; - Rt1215 = sext(tmp); + build ItCond; + build PcrelOffset12; + tmp:1 = *PcrelOffset12; + Rt1215 = sext(tmp); } -:ldrsb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12 -{ - build ItCond; - tmp:1 = *RnIndirect12; - Rt1215 = sext(tmp); +:ldrsb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12 { + build ItCond; + build RnIndirect12; + tmp:1 = *RnIndirect12; + Rt1215 = sext(tmp); } :ldrsb^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf91; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) @@ -2415,10 +2429,10 @@ define pcodeop ExclusiveAccess; Rt1215 = sext(tmp); } -:ldrsb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf91 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 -{ +:ldrsb^ItCond^".w" Rt1215,thAddrShift is TMode=1 & ItCond & (op4=0xf91; Rt1215 & thc1111=0 & sop0610=0) & thAddrShift { build ItCond; - local tmp = Rn0003 + (Rm0003 << thc0405); + build thAddrShift; + local tmp = thAddrShift; val:1 = *tmp; Rt1215 = sext(val); } @@ -2437,15 +2451,15 @@ define pcodeop ExclusiveAccess; { build ItCond; build PcrelOffset12; - tmp:2 = *PcrelOffset12; + tmp:2 = PcrelOffset12:2; Rt1215 = sext(tmp); } -:ldrsh^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf9B; Rt1215) & RnIndirect12 -{ - build ItCond; - tmp:2 = *RnIndirect12; - Rt1215 = sext(tmp); +:ldrsh^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf9B; Rt1215) & RnIndirect12 { + build ItCond; + build RnIndirect12; + tmp:2 = *RnIndirect12; + Rt1215 = sext(tmp); } :ldrsh^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf93; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) @@ -2456,11 +2470,11 @@ define pcodeop ExclusiveAccess; Rt1215 = sext(tmp); } -:ldrsh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf93 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 -{ +:ldrsh^ItCond^".w" Rt1215,thAddrShift is TMode=1 & ItCond & (op4=0xf93; Rt1215 & thc1111=0 & sop0610=0) & thAddrShift { build ItCond; - local tmp = Rn0003 + (Rm0003 << thc0405); - val:2 = *tmp; + build thAddrShift; + local addr = thAddrShift; + val:2 = *addr; Rt1215 = sext(val); } @@ -2542,9 +2556,9 @@ macro th_set_carry_for_lsr(op1,shift_count) { @if defined(VERSION_6T2) || defined(VERSION_7) -:lsl^thSBIT_CZN^ItCond^".w" Rd0811,Rm0003,thLsbImm is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=15; thc1515=0 & Rd0811 & thc0405=0 & Rm0003 & thLsbImm -{ +:lsl^thSBIT_CZN^ItCond^".w" Rd0811,Rm0003,thLsbImm is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=15; thc1515=0 & Rd0811 & thc0405=0 & Rm0003 & thLsbImm { build ItCond; + build thLsbImm; th_set_carry_for_lsl(Rm0003,thLsbImm); Rd0811 = Rm0003 << thLsbImm; resflags(Rd0811); @@ -2561,9 +2575,9 @@ macro th_set_carry_for_lsr(op1,shift_count) { build thSBIT_CZN; } -:lsr^thSBIT_CZN^ItCond^".w" Rd0811,Rm0003,thLsbImm is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=15; thc1515=0 & Rd0811 & thc0405=1 & Rm0003 & thLsbImm -{ +:lsr^thSBIT_CZN^ItCond^".w" Rd0811,Rm0003,thLsbImm is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=15; thc1515=0 & Rd0811 & thc0405=1 & Rm0003 & thLsbImm { build ItCond; + build thLsbImm; th_set_carry_for_lsr(Rm0003,thLsbImm); Rd0811 = Rm0003 >> thLsbImm; resflags(Rd0811); @@ -2640,18 +2654,20 @@ macro th_set_carry_for_lsr(op1,shift_count) { Hrd0002 = Hrm0305; } +# Destination is PC :mov^ItCond Hrd0002,Hrm0305 is TMode=1 & ItCond & op8=0x46 & Hrm0305 & Hrd0002 & hrd0002=7 & h1=1 { build ItCond; - dest:4 = Hrm0305; + dest:4 = Hrm0305 & 0xfffffffe; # Simple branch, mask off the last bit BranchWritePC(dest); goto [pc]; } +# Destination is PC :mov^ItCond Hrd0002,Hrm0305 is TMode=1 & ItCond & op8=0x46 & Hrm0305 & rm0306=14 & Hrd0002 & hrd0002=7 & h1=1 { build ItCond; - dest:4 = Hrm0305; + dest:4 = Hrm0305 & 0xfffffffe; # Simple branch, mask off the last bit BranchWritePC(dest); return [pc]; } @@ -2664,9 +2680,9 @@ macro th_set_carry_for_lsr(op1,shift_count) { @if defined(VERSION_6T2) || defined(VERSION_7) -:mov^thSBIT_ZN^ItCond^".w" Rd0811,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=2 & thSBIT_ZN & sop0003=15; thc1515=0 & Rd0811) & ThumbExpandImm12 -{ +:mov^thSBIT_ZN^ItCond^".w" Rd0811,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=2 & thSBIT_ZN & sop0003=15; thc1515=0 & Rd0811) & ThumbExpandImm12 { build ItCond; + build ThumbExpandImm12; Rd0811 = ThumbExpandImm12; resflags(Rd0811); build thSBIT_ZN; @@ -2817,6 +2833,7 @@ basepri: "basepri" is epsilon {} :mrs^ItCond Rd0811,basepri is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=17 & basepri { build ItCond; + build basepri; Rd0811 = 0; b:1 = isCurrentModePrivileged(); if (!b) goto inst_next; @@ -2828,6 +2845,7 @@ basepri_max: "basepri_max" is epsilon {} :mrs^ItCond Rd0811,basepri_max is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=18 & basepri_max { build ItCond; + build basepri_max; Rd0811 = 0; b:1 = isCurrentModePrivileged(); if (!b) goto inst_next; @@ -2860,7 +2878,7 @@ control: "control" is epsilon {} @endif -@if defined(CORTEX) +@if defined(VERSION_8M) define pcodeop setMainStackPointerLimit; @@ -2894,7 +2912,7 @@ define pcodeop getProcessStackPointerLimit; Rd0811 = getProcessStackPointerLimit(); } -@endif #CORTEX +@endif #VERSION_8M :mrs^ItCond Rd0811,cpsr is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=0 & cpsr { @@ -3047,17 +3065,18 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } spsr = (spsr& ~thspsrmask) | (Rn0003 & thspsrmask); } -:mvn^thSBIT_ZN^ItCond Rd0811,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=3 & thSBIT_ZN & thc0003=15; thc1515=0 & Rd0811) & ThumbExpandImm12 -{ - build ItCond; - Rd0811 = ~ThumbExpandImm12; - resflags(Rd0811); - build thSBIT_ZN; +:mvn^thSBIT_ZN^ItCond Rd0811,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=3 & thSBIT_ZN & thc0003=15; thc1515=0 & Rd0811) & ThumbExpandImm12 { + build ItCond; + build ThumbExpandImm12; + Rd0811 = ~ThumbExpandImm12; + resflags(Rd0811); + build thSBIT_ZN; } :mvn^thSBIT_ZN^ItCond^".w" Rd0811,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=3 & thSBIT_ZN & thc0003=15; thc1515=0 & Rd0811 & thshift2 { build ItCond; + build thshift2; Rd0811 = ~thshift2; resflags(Rd0811); build thSBIT_ZN; @@ -3128,6 +3147,7 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } :orn^thSBIT_CZNO^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=3 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 { build ItCond; + build ThumbExpandImm12; Rd0811 = Rn0003 | ~(ThumbExpandImm12); th_logicflags(); resflags(Rd0811); @@ -3137,6 +3157,7 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } :orn^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=3 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 { build ItCond; + build thshift2; Rd0811 = Rn0003 | ~(thshift2); th_logicflags(); resflags(Rd0811); @@ -3146,6 +3167,7 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } :orr^thSBIT_CZNO^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=2 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 { build ItCond; + build ThumbExpandImm12; Rd0811 = Rn0003 | ThumbExpandImm12; th_logicflags(); resflags(Rd0811); @@ -3155,6 +3177,7 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } :orr^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 { build ItCond; + build thshift2; Rd0811 = Rn0003 | thshift2; th_logicflags(); resflags(Rd0811); @@ -3164,6 +3187,7 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } :pkhbt^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op4=0xeac & Rn0003; thc1515=0 & Rd0811 & thc0505=0 & thc0404=0 & thshift2 { build ItCond; + build thshift2; Rd0811 = (Rn0003 & 0x0000ffff) | (thshift2 & 0xffff0000); th_logicflags(); resflags(Rd0811); @@ -3172,6 +3196,7 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } :pkhtb^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op4=0xeac & Rn0003; thc1515=0 & Rd0811 & thc0505=1 & thc0404=0 & thshift2 { build ItCond; + build thshift2; Rd0811 = (Rn0003 & 0xffff0000) | (thshift2 & 0x0000ffff); th_logicflags(); resflags(Rd0811); @@ -3195,13 +3220,14 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } :pld^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf8 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12 { build ItCond; + build PcrelOffset12; HintPreloadData(PcrelOffset12); } -:pld^ItCond Rn0003,Rm0003"lsl #"^thc0405 is TMode=1 & ItCond & op6=0x3e0 & thwbit=0 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003 -{ +:pld^ItCond thAddrShift is TMode=1 & ItCond & (op6=0x3e0 & thwbit=0 & thc0404=1; op8=0xf0 & thc0607=0) & thAddrShift { build ItCond; - addr:4 = Rn0003 + (Rm0003 << thc0405); + build thAddrShift; + addr:4 = thAddrShift; HintPreloadData(addr); } @@ -3248,9 +3274,9 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } :pop^ItCond thldrlist_inc is TMode=1 & ItCond & op0=0xe8bd; thldrlist_inc & thc1515=1 { - build ItCond; + build ItCond; # mult_addr = sp & 0xfffffffc; - mult_addr = sp; + mult_addr = sp; build thldrlist_inc; sp = mult_addr; LoadWritePC(pc); @@ -3641,7 +3667,7 @@ macro BitReverse(val) { cpsr = *ptr; ptr = ptr - 4; dest:4 = *ptr; - BranchWritePC(dest); + BranchWritePC(dest & 0xfffffffe); # Simple branch, mask off the last bit return [pc]; } @@ -3653,7 +3679,7 @@ macro BitReverse(val) { ptr = ptr - 4; dest:4 = *ptr; part2Rd0003 = ptr; - BranchWritePC(dest); + BranchWritePC(dest & 0xfffffffe); # Simple branch, mask off the last bit return [pc]; } @@ -3664,7 +3690,7 @@ macro BitReverse(val) { cpsr = *ptr; ptr = ptr + 4; dest:4 = *ptr; - BranchWritePC(dest); + BranchWritePC(dest & 0xfffffffe); # Simple branch, mask off the last bit return [pc]; } @@ -3676,7 +3702,7 @@ macro BitReverse(val) { ptr = ptr + 4; dest:4 = *ptr; part2Rd0003 = ptr + 4; - BranchWritePC(dest); + BranchWritePC(dest & 0xfffffffe); # Simple branch, mask off the last bit return [pc]; } @@ -3686,6 +3712,7 @@ macro BitReverse(val) { :rsb^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=14 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 { build ItCond; + build ThumbExpandImm12; th_subflags(ThumbExpandImm12,Rn0003); Rd0811 = ThumbExpandImm12 - Rn0003; resflags(Rd0811); @@ -3695,6 +3722,7 @@ macro BitReverse(val) { :rsb^thSBIT_CZNO^ItCond Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=14 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 { build ItCond; + build thshift2; th_subflags(thshift2,Rn0003); Rd0811 = thshift2 - Rn0003; resflags(Rd0811); @@ -3724,6 +3752,7 @@ macro th_set_carry_for_ror(result, count) { :ror^thSBIT_CZN^ItCond Rd0811,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & thc0003=0xf; thc1515=0 & Rd0811 & thc0405=3 & thshift2 { build ItCond; + build thshift2; Rd0811 = thshift2; tmpCY = shift_carry; resflags(Rd0811); @@ -3929,9 +3958,8 @@ macro th_set_carry_for_ror(result, count) { } @endif # defined(VERSION_6T2) || defined(VERSION_7) - -thXBIT: "b" is Rn0003 ; thc0505=0 { local tmpRn0003 = Rn0003; tmp_x:2 = tmpRn0003:2; export tmp_x; } -thXBIT: "t" is Rn0003 ; thc0505=1 { local tmpRn0003 = Rn0003; tmp_x:2 = tmpRn0003(2); export tmp_x; } +thXBIT: "b" is Rn0003 ; thc0505=0 { local tmpRn0003 = Rn0003; tmp_x:2 = tmpRn0003:2; export tmp_x; } +thXBIT: "t" is Rn0003 ; thc0505=1 { local tmpRn0003 = Rn0003; tmp_x:2 = tmpRn0003(2); export tmp_x; } thYBIT: "b" is thc0404=0 & Rm0003 { local tmpRm0003 = Rm0003; tmp_y:2 = tmpRm0003:2; export tmp_y; } thYBIT: "t" is thc0404=1 & Rm0003 { local tmpRm0003 = Rm0003; tmp_y:2 = tmpRm0003(2); export tmp_y; } @@ -4196,14 +4224,13 @@ thdXtop: "X" is thc0404=1 & Rm0003 { local tmpRm0003 = Rm0003; tmp:2 = tmp sp = ptr; } -:srsia^ItCond sp,thSRSMode is TMode=1 & ItCond & op6=0x3a6 & sp & thc0505=0 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode -{ - build ItCond; - # register list is always: r14, spsr - ptr:4 = sp + 4; - *ptr = lr; - ptr = ptr + 4; - *ptr = spsr; +:srsia^ItCond sp,thSRSMode is TMode=1 & ItCond & op6=0x3a6 & sp & thc0505=0 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode { + build ItCond; + # register list is always: r14, spsr + ptr:4 = sp + 4; + *ptr = lr; + ptr = ptr + 4; + *ptr = spsr; } @if defined(VERSION_6T2) || defined(VERSION_7) @@ -4472,6 +4499,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :str.w^ItCond Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf8c; Rt1215) & RnIndirect12 { build ItCond; + build RnIndirect12; *RnIndirect12 = Rt1215; } @@ -4489,10 +4517,10 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } *tmp = Rt1215; } -:str^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf84 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 -{ +:str^ItCond^".w" Rt1215,thAddrShift is TMode=1 & ItCond & (op4=0xf84; Rt1215 & thc1111=0 & sop0610=0) & thAddrShift { build ItCond; - local tmp = Rn0003 + (Rm0003 << thc0405); + build thAddrShift; + local tmp = thAddrShift; *tmp = Rt1215; } @@ -4512,12 +4540,12 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } *RnIndirectPUW = tmpRt1215:1; } -:strb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf80 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 -{ +:strb^ItCond^".w" Rt1215,thAddrShift is TMode=1 & ItCond & (op4=0xf80; Rt1215 & thc1111=0 & sop0610=0) & thAddrShift { build ItCond; - local tmp = Rn0003 + (Rm0003 << thc0405); + build thAddrShift; + local addr = thAddrShift; local tmpRt1215 = Rt1215; - *tmp = tmpRt1215:1; + *addr = tmpRt1215:1; } :strbt^ItCond Rt1215,[Rn0003,Immed8] is TMode=1 & ItCond & op4=0xf80 & Rn0003; Rt1215 & thc0811=14 & Immed8 @@ -4553,12 +4581,12 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } *RnIndirectPUW = tmpRt1215:2; } -:strh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf82 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 -{ +:strh^ItCond^".w" Rt1215,thAddrShift is TMode=1 & ItCond & (op4=0xf82; Rt1215 & thc1111=0 & sop0610=0) & thAddrShift { build ItCond; - local tmp = Rn0003 + (Rm0003 << thc0405); + build thAddrShift; + local addr = thAddrShift; local tmpRt1215 = Rt1215; - *tmp = tmpRt1215:2; + *addr = tmpRt1215:2; } :strht^ItCond Rt1215,[Rn0003,Immed8] is TMode=1 & ItCond & op4=0xf82 & Rn0003; Rt1215 & thc0811=14 & Immed8 @@ -4681,7 +4709,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sub^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=13 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 { - build ItCond; + build ItCond; build thshift2; local tmp = thshift2; th_subflags(Rn0003,tmp); @@ -4692,7 +4720,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sub^thSBIT_CZNO^ItCond^".w" Rd0811,sp,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=13 & thSBIT_CZNO & sp & sop0003=0xd; thc1515=0 & Rd0811) & ThumbExpandImm12 { - build ItCond; + build ItCond; build ThumbExpandImm12; th_subflags(sp,ThumbExpandImm12); Rd0811 = sp-ThumbExpandImm12; @@ -4702,7 +4730,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sub^ItCond pc,lr,Immed8 is TMode=1 & ItCond & op4=0xf3d & pc & sop0003=0xe; op8=0x8f & lr & Immed8 { - build ItCond; + build ItCond; build Immed8; th_subflags(lr,Immed8); dest:4 = lr-Immed8; @@ -4715,7 +4743,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :subw^ItCond Rd0811,sp,Immed12 is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=5 & thc0404=0 & sop0003=0xd & sp; thc1515=0 & Rd0811) & Immed12 { - build ItCond; + build ItCond; th_subflags(sp,Immed12); Rd0811 = sp-Immed12; resflags(Rd0811); @@ -4723,7 +4751,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sub^thSBIT_CZNO^ItCond^".w" Rd0811,sp,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=13 & thSBIT_CZNO & sop0003=0xd & sp; thc1515=0 & Rd0811 & thshift2 { - build ItCond; + build ItCond; build thshift2; local tmp = thshift2; th_subflags(sp,tmp); @@ -4736,7 +4764,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :svc^ItCond immed8 is TMode=1 & ItCond & op8=0xdf & immed8 { - build ItCond; + build ItCond; tmp:4 = immed8; software_interrupt(tmp); } @@ -4745,7 +4773,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sxtab^ItCond Rd0811, Rn0003, Rm0003, ByteRotate is TMode=1 & ItCond & op4=0xfa4 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 { - build ItCond; + build ItCond; tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); Rd0811 = sext(tmp:1) + Rn0003; } @@ -4759,7 +4787,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sxtab16^ItCond Rd0811, Rn0003, Rm0003, ByteRotate is TMode=1 & ItCond & op4=0xfa2 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 { - build ItCond; + build ItCond; tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); local tmpRn0003 = Rn0003; tmpL:2 = sext(tmp:1) + tmpRn0003:2; @@ -4770,7 +4798,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sxtab16^ItCond Rd0811, Rn0003, Rm0003 is TMode=1 & ItCond & op4=0xfa2 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 { - build ItCond; + build ItCond; local tmpRn0003 = Rn0003; local tmpRm0003 = Rm0003; tmpL:2 = sext(tmpRm0003:1) + tmpRn0003:2; @@ -4781,15 +4809,15 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sxtah^ItCond Rd0811, Rn0003, Rm0003, ByteRotate is TMode=1 & ItCond & op4=0xfa0 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 { - build ItCond; + build ItCond; tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); Rd0811 = sext(tmp:2) + Rn0003; } :sxtah^ItCond Rd0811, Rn0003, Rm0003 is TMode=1 & ItCond & op4=0xfa0 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 { - build ItCond; - local tmpRm0003 = Rm0003; + build ItCond; + local tmpRm0003 = Rm0003; Rd0811 = sext(tmpRm0003:2) + Rn0003; } @@ -4799,22 +4827,22 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sxtb^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=0 & thc0606=1 & Rm0305 & Rd0002 { - build ItCond; - local tmpRm0305 = Rm0305; + build ItCond; + local tmpRm0305 = Rm0305; Rd0002 = sext(tmpRm0305:1); } :sxtb^ItCond^".w" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa4f; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 { - build ItCond; + build ItCond; tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); Rd0811 = sext(tmp:1); } :sxtb^ItCond^".w" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa4f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 { - build ItCond; - local tmpRm0003 = Rm0003; + build ItCond; + local tmpRm0003 = Rm0003; Rd0811 = sext(tmpRm0003:1); } @@ -4823,9 +4851,8 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } @if defined(VERSION_6T2) || defined(VERSION_7) :sxtb16^ItCond Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa2f; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 - { - build ItCond; + build ItCond; tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); tmpL:2 = sext(tmp:1); tmp = tmp >> 16; @@ -4835,8 +4862,8 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sxtb16^ItCond Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa2f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 { - build ItCond; - local tmpRm0003 = Rm0003; + build ItCond; + local tmpRm0003 = Rm0003; tmpL:2 = sext(tmpRm0003:1); tmp:4 = tmpRm0003 >> 16; tmpH:2 = sext(tmp:1); @@ -4849,22 +4876,22 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } :sxth^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=0 & thc0606=0 & Rm0305 & Rd0002 { - build ItCond; - local tmpRm0305 = Rm0305; + build ItCond; + local tmpRm0305 = Rm0305; Rd0002 = sext(tmpRm0305:2); } :sxth^ItCond^".w" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa0f; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 { - build ItCond; - tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); Rd0811 = sext(tmp:2); } :sxth^ItCond^".w" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa0f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 { - build ItCond; - local tmpRm0003 = Rm0003; + build ItCond; + local tmpRm0003 = Rm0003; Rd0811 = sext(tmpRm0003:2); } diff --git a/pypcode/processors/ARM/data/languages/ARM_apcs.cspec b/pypcode/processors/ARM/data/languages/ARM_apcs.cspec index 406734fa..3f21f334 100644 --- a/pypcode/processors/ARM/data/languages/ARM_apcs.cspec +++ b/pypcode/processors/ARM/data/languages/ARM_apcs.cspec @@ -162,6 +162,7 @@ + @@ -212,8 +212,7 @@ offset = *:1 (tmpptr + r0); lr = lr + 2 * zext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -230,8 +229,7 @@ offset = *:1 (tmpptr + r0); lr = lr + 2 * sext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -249,8 +247,7 @@ offset = *:2 (tmpptr + index); lr = lr + 2 * sext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -268,8 +265,7 @@ offset = *:2 (tmpptr + index); lr = lr + 2 * zext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -288,8 +284,7 @@ offset = offset * 4; lr = lr + offset; - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> diff --git a/pypcode/processors/ARM/data/languages/ARM_v45.cspec b/pypcode/processors/ARM/data/languages/ARM_v45.cspec index a6b7a3bd..e53aac6b 100644 --- a/pypcode/processors/ARM/data/languages/ARM_v45.cspec +++ b/pypcode/processors/ARM/data/languages/ARM_v45.cspec @@ -82,6 +82,7 @@ + @@ -131,8 +131,7 @@ offset = *:1 (tmpptr + r0); lr = lr + 2 * zext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -149,8 +148,7 @@ offset = *:1 (tmpptr + r0); lr = lr + 2 * sext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -168,8 +166,7 @@ offset = *:2 (tmpptr + index); lr = lr + 2 * sext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -187,8 +184,7 @@ offset = *:2 (tmpptr + index); lr = lr + 2 * zext(offset); - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> @@ -207,8 +203,7 @@ offset = offset * 4; lr = lr + offset; - ISAModeSwitch = (lr & 1) != 0; - TB = ISAModeSwitch; + TB = (lr & 1) != 0; pc = lr & 0xfffffffe; goto [pc]; ]]> diff --git a/pypcode/processors/ARM/data/languages/ARM_v45.pspec b/pypcode/processors/ARM/data/languages/ARM_v45.pspec index b7cd9524..d28bdb6a 100644 --- a/pypcode/processors/ARM/data/languages/ARM_v45.pspec +++ b/pypcode/processors/ARM/data/languages/ARM_v45.pspec @@ -8,6 +8,7 @@ + @@ -18,7 +19,11 @@ - + + + + + diff --git a/pypcode/processors/ARM/data/languages/ARM_win.cspec b/pypcode/processors/ARM/data/languages/ARM_win.cspec index c9e0c331..117cbe2b 100644 --- a/pypcode/processors/ARM/data/languages/ARM_win.cspec +++ b/pypcode/processors/ARM/data/languages/ARM_win.cspec @@ -228,6 +228,7 @@ + >1; ] { } :vldmia^COND vldmRn,vldmDdList is ( ($(AMODE) & c2327=0x19 & c2121 & c2020=1 & c0811=11 & c0000=0) | - ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0) ) & COND & vldmRn & vldmDdList & vldmOffset & vldmUpdate + ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=1 & thv_c1619 != 0xf & thv_c0811=11 & thv_c0000=0) ) & COND & vldmRn & vldmDdList & vldmOffset & vldmUpdate { mult_addr = vldmRn; build vldmDdList; @@ -3791,7 +4055,7 @@ vldmDdList: "{"^buildVldmDdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 } :vldmdb^COND vldmRn,vldmDdList is ( ($(AMODE) & c2327=0x1a & c2121=1 & c2020=1 & c0811=11 & c0000=0) | - ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0 ) ) & COND & vldmRn & vldmDdList & vldmOffset + ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c1619 != 0xf & thv_c0811=11 & thv_c0000=0 ) ) & COND & vldmRn & vldmDdList & vldmOffset { local start_addr = vldmRn - vldmOffset; mult_addr = start_addr; @@ -4040,7 +4304,7 @@ vldmSdList: "{"^buildVldmSdList^"}" is TMode=0 & D22 & c1215 & c0007 & buildVl vldmSdList: "{"^buildVldmSdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVldmSdList [ regNum=(thv_c1215<<1) + thv_D22 - 1; counter=thv_c0007; ] { } :vldmia^COND vldmRn,vldmSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c2020=1 & c0811=10 ) | - ($(TMODE_E) & thv_c2327=0x19 & thv_c2020=1 & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset & vldmUpdate + ($(TMODE_E) & thv_c2327=0x19 & thv_c2020=1 & thv_c1619 != 0xf & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset & vldmUpdate { mult_addr = vldmRn; build vldmSdList; @@ -4048,7 +4312,7 @@ vldmSdList: "{"^buildVldmSdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 } :vldmdb^COND vldmRn,vldmSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c2121=1 & c2020=1 & c0811=10 ) | - ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset + ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c1619 != 0xf & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset { local start_addr = vldmRn - vldmOffset; mult_addr = start_addr; @@ -4060,22 +4324,22 @@ vldmSdList: "{"^buildVldmSdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 # VLDR # -vldrRn: "["^Rn^"]" is TMode=0 & Rn & immed=0 & c2323=0 { ptr:4 = Rn; export ptr; } -vldrRn: "["^Rn^"]" is TMode=0 & Rn & immed=0 & c2323=1 { ptr:4 = Rn; export ptr; } -vldrRn: "["^Rn^",#-"^vldrImm^"]" is TMode=0 & Rn & immed & c2323=0 [ vldrImm = immed * 4; ] { ptr:4 = Rn - vldrImm; export ptr; } -vldrRn: "["^Rn^",#"^vldrImm^"]" is TMode=0 & Rn & immed & c2323=1 [ vldrImm = immed * 4; ] { ptr:4 = Rn + vldrImm; export ptr; } -vldrRn: "["^pc^"]" is TMode=0 & Rn=15 & pc & immed=0 & c2323=0 { ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; } -vldrRn: "["^pc^"]" is TMode=0 & Rn=15 & pc & immed=0 & c2323=1 { ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; } -vldrRn: "["^pc^",#-"^vldrImm^"]" is TMode=0 & Rn=15 & pc & immed & c2323=0 [ vldrImm = immed * 4; ] { ptr:4 = ((inst_start + 8) & 0xfffffffc) - vldrImm; export ptr; } -vldrRn: "["^pc^",#"^vldrImm^"]" is TMode=0 & Rn=15 & pc & immed & c2323=1 [ vldrImm = immed * 4; ] { ptr:4 = ((inst_start + 8) & 0xfffffffc) + vldrImm; export ptr; } +vldrRn: "["^Rn^"]" is TMode=0 & Rn & immed=0 & c2323=0 { ptr:4 = Rn; export ptr; } +vldrRn: "["^Rn^"]" is TMode=0 & Rn & immed=0 & c2323=1 { ptr:4 = Rn; export ptr; } +vldrRn: "["^Rn^",#-"^vldrImm^"]" is TMode=0 & Rn & immed & c2323=0 [ vldrImm = immed * 4; ] { ptr:4 = Rn - vldrImm; export ptr; } +vldrRn: "["^Rn^",#"^vldrImm^"]" is TMode=0 & Rn & immed & c2323=1 [ vldrImm = immed * 4; ] { ptr:4 = Rn + vldrImm; export ptr; } +vldrRn: "["^pc^"]" is TMode=0 & Rn=15 & pc & immed=0 & c2323=0 { ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; } +vldrRn: "["^pc^"]" is TMode=0 & Rn=15 & pc & immed=0 & c2323=1 { ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; } +vldrRn: "["^pc^",#-"^vldrImm^"]" is TMode=0 & Rn=15 & pc & immed & c2323=0 [ vldrImm = immed * 4; ] { ptr:4 = ((inst_start + 8) & 0xfffffffc) - vldrImm; export ptr; } +vldrRn: "["^pc^",#"^vldrImm^"]" is TMode=0 & Rn=15 & pc & immed & c2323=1 [ vldrImm = immed * 4; ] { ptr:4 = ((inst_start + 8) & 0xfffffffc) + vldrImm; export ptr; } vldrRn: "["^VRn^"]" is TMode=1 & VRn & thv_immed=0 & thv_c2323=0 { ptr:4 = VRn; export ptr; } vldrRn: "["^VRn^"]" is TMode=1 & VRn & thv_immed=0 & thv_c2323=1 { ptr:4 = VRn; export ptr; } vldrRn: "["^VRn^",#-"^vldrImm^"]" is TMode=1 & VRn & thv_immed & thv_c2323=0 [ vldrImm = thv_immed * 4; ] { ptr:4 = VRn - vldrImm; export ptr; } vldrRn: "["^VRn^",#"^vldrImm^"]" is TMode=1 & VRn & thv_immed & thv_c2323=1 [ vldrImm = thv_immed * 4; ] { ptr:4 = VRn + vldrImm; export ptr; } -vldrRn: "["^pc^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=0 { ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; } -vldrRn: "["^pc^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=1 { ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; } +vldrRn: "["^pc^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=0 { ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; } +vldrRn: "["^pc^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=1 { ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; } vldrRn: "["^pc^",#-"^vldrImm^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2323=0 [ vldrImm = thv_immed * 4; ] { ptr:4 = ((inst_start + 4) & 0xfffffffc) - vldrImm; export ptr; } -vldrRn: "["^pc^",#"^vldrImm^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2323=1 [ vldrImm = thv_immed * 4; ] { ptr:4 = ((inst_start + 4) & 0xfffffffc) + vldrImm; export ptr; } +vldrRn: "["^pc^",#"^vldrImm^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2323=1 [ vldrImm = thv_immed * 4; ] { ptr:4 = ((inst_start + 4) & 0xfffffffc) + vldrImm; export ptr; } :vldr^COND^".64" Dd,vldrRn is COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=1 & c0811=11) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=1 & thv_c0811=11)) & Dd & vldrRn { @@ -4087,6 +4351,29 @@ vldrRn: "["^pc^",#"^vldrImm^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2 Sd = *:4 vldrRn; } +vldrRn16: "["^Rn^"]" is TMode=0 & Rn & immed=0 & c2323=0 { ptr:4 = Rn; export ptr; } +vldrRn16: "["^Rn^"]" is TMode=0 & Rn & immed=0 & c2323=1 { ptr:4 = Rn; export ptr; } +vldrRn16: "["^Rn^",#-"^vldrImm^"]" is TMode=0 & Rn & immed & c2323=0 [ vldrImm = immed * 2; ] { ptr:4 = Rn - vldrImm; export ptr; } +vldrRn16: "["^Rn^",#"^vldrImm^"]" is TMode=0 & Rn & immed & c2323=1 [ vldrImm = immed * 2; ] { ptr:4 = Rn + vldrImm; export ptr; } +vldrRn16: "["^pc^"]" is TMode=0 & Rn=15 & pc & immed=0 & c2323=0 { ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; } +vldrRn16: "["^pc^"]" is TMode=0 & Rn=15 & pc & immed=0 & c2323=1 { ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; } +vldrRn16: "["^pc^",#-"^vldrImm^"]" is TMode=0 & Rn=15 & pc & immed & c2323=0 [ vldrImm = immed * 2; ] { ptr:4 = ((inst_start + 8) & 0xfffffffc) - vldrImm; export ptr; } +vldrRn16: "["^pc^",#"^vldrImm^"]" is TMode=0 & Rn=15 & pc & immed & c2323=1 [ vldrImm = immed * 2; ] { ptr:4 = ((inst_start + 8) & 0xfffffffc) + vldrImm; export ptr; } +vldrRn16: "["^VRn^"]" is TMode=1 & VRn & thv_immed=0 & thv_c2323=0 { ptr:4 = VRn; export ptr; } +vldrRn16: "["^VRn^"]" is TMode=1 & VRn & thv_immed=0 & thv_c2323=1 { ptr:4 = VRn; export ptr; } +vldrRn16: "["^VRn^",#-"^vldrImm^"]" is TMode=1 & VRn & thv_immed & thv_c2323=0 [ vldrImm = thv_immed * 2; ] { ptr:4 = VRn - vldrImm; export ptr; } +vldrRn16: "["^VRn^",#"^vldrImm^"]" is TMode=1 & VRn & thv_immed & thv_c2323=1 [ vldrImm = thv_immed * 2; ] { ptr:4 = VRn + vldrImm; export ptr; } +vldrRn16: "["^pc^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=0 { ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; } +vldrRn16: "["^pc^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=1 { ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; } +vldrRn16: "["^pc^",#-"^vldrImm^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2323=0 [ vldrImm = thv_immed * 2; ] { ptr:4 = ((inst_start + 4) & 0xfffffffc) - vldrImm; export ptr; } +vldrRn16: "["^pc^",#"^vldrImm^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2323=1 [ vldrImm = thv_immed * 2; ] { ptr:4 = ((inst_start + 4) & 0xfffffffc) + vldrImm; export ptr; } + + +:vldr^COND^".16" Sd,vldrRn16 is COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=1 & c0811=9) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=1 & thv_c0811=9)) & Sd & vldrRn16 +{ + Sd = *:2 vldrRn16; +} + @endif # VFPv2 | VFPv3 define pcodeop VectorMin; @@ -4107,13 +4394,13 @@ define pcodeop FloatVectorMultiplySubtract; @if defined(SIMD) :vmax.^udt^esize2021 Dd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=0 & c0404=0 ) | - ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=0 & thv_c0404=0 ) ) & esize2021 & udt & Dm & Dn & Dd + ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=6 & thv_Q6=0 & thv_c0404=0 ) ) & esize2021 & udt & Dm & Dn & Dd { Dd = VectorMax(Dn,Dm,esize2021,udt); } :vmax.^udt^esize2021 Qd, Qn, Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=1 & c0404=0 ) | - ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & udt & Qm & Qn & Qd + ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=6 & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & udt & Qm & Qn & Qd { Qd = VectorMax(Qn,Qm,esize2021,udt); } @@ -4131,14 +4418,14 @@ define pcodeop FloatVectorMultiplySubtract; } :vmin.^udt^esize2021 Dd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=0 & c0404=1 ) | - ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=0 & thv_c0404=1 ) ) & esize2021 & udt & Dm & Dn & Dd + ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=6 & thv_Q6=0 & thv_c0404=1 ) ) & esize2021 & udt & Dm & Dn & Dd { Dd = VectorMin(Dn,Dm,esize2021,udt); } :vmin.^udt^esize2021 Qd, Qn, Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=1 & c0404=1 ) | - ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=1 & thv_c0404=1 ) ) & esize2021 & udt & Qm & Qn & Qd + ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=6 & thv_Q6=1 & thv_c0404=1 ) ) & esize2021 & udt & Qm & Qn & Qd { Qd = VectorMin(Qn,Qm,esize2021,udt); @@ -4324,16 +4611,31 @@ vmlDm: thv_Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5 Qd = VectorMultiplySubtract(Dn,vmlDm,esize2021,udt); } -# Addresses all versions of F6.1.134 except A2/T2 with Q=0 -:vmov.^simdExpImmDT Dd,simdExpImm_8 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=0 & c0404=1 ) | - ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=0 & thv_c0404=1 )) & Dd & simdExpImmDT & simdExpImm_8 +# Addresses all versions of F6.1.134 except A2/T2/A5/T5 with Q=0 +:vmov.^simdExpImmDT Dd,simdExpImm_8 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=0 & c0505=0 & c0404=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=0 & thv_c0505=0 & thv_c0404=1 )) & Dd & simdExpImmDT & simdExpImm_8 +{ + Dd = simdExpImm_8; +} + +# F6.1.134 A5/T5 with Q=0 +:vmov.^simdExpImmDT Dd,simdExpImm_8 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0811=0xe & c0707=0 & Q6=0 & c0505=1 & c0404=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0811=0xe & thv_c0707=0 & thv_Q6=0 & thv_c0505=1 & thv_c0404=1 )) & Dd & simdExpImmDT & simdExpImm_8 { Dd = simdExpImm_8; } -# Addresses all versions of F6.1.134 except At/T2 with Q=1 -:vmov.^simdExpImmDT Qd,simdExpImm_16 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=1 & c0404=1 ) | - ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=1 & thv_c0404=1 )) & Qd & simdExpImmDT & simdExpImm_16 + +# Addresses all versions of F6.1.134 except A2/T2/A5/T5 with Q=1 +:vmov.^simdExpImmDT Qd,simdExpImm_16 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=1 & c0505=0 & c0404=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=1 & thv_c0505=0 & thv_c0404=1 )) & Qd & simdExpImmDT & simdExpImm_16 +{ + Qd = simdExpImm_16; +} + +# F6.1.134 A5/T5 with Q=1 +:vmov.^simdExpImmDT Qd,simdExpImm_16 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0811=0xe & c0707=0 & Q6=1 & c0505=1 & c0404=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0811=0xe & thv_c0707=0 & thv_Q6=1 & thv_c0505=1 & thv_c0404=1 )) & Qd & simdExpImmDT & simdExpImm_16 { Qd = simdExpImm_16; } @@ -4420,7 +4722,7 @@ vmovIndex: thv_c2121 is TMode=1 & thv_c2222=0 & thv_c2121 & thv_c0506=0 { tmp dNvmovIndex: Dn^"["^vmovIndex^"]" is Dn & vmovIndex { } - +@ifndef VERSION_8M :vmov^COND^".8" dNvmovIndex,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=1 & c2020=0 & c0811=11 & c0404=1 & c0003=0 ) | ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=1 & thv_c2020=0 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex { @@ -4449,7 +4751,6 @@ dNvmovIndex: Dn^"["^vmovIndex^"]" is Dn & vmovIndex { } #VectorSetElement(VRd,Dn,vmovIndex,vmovSize); } - :vmov^COND^".u8" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=1 & c2020=1 & c0811=11 & c0404=1 & c0003=0 ) | ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=1 & thv_c2020=1 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex { @@ -4503,7 +4804,7 @@ dNvmovIndex: Dn^"["^vmovIndex^"]" is Dn & vmovIndex { } VRd = sext(result); #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); } - +@endif #ndef VERSION_8M @endif # SIMD @@ -4588,10 +4889,39 @@ vmrsReg: mvfr0 is (($(AMODE) & c1619=7) | (TMode=1 & thv_c1619=7)) & mvfr0 { exp vmrsReg: fpexc is (($(AMODE) & c1619=8) | (TMode=1 & thv_c1619=8)) & fpexc { export fpexc; } vmrsReg: fpinst is (($(AMODE) & c1619=9) | (TMode=1 & thv_c1619=9)) & fpinst { export mvfr1; } vmrsReg: fpinst2 is (($(AMODE) & c1619=0xa) | (TMode=1 & thv_c1619=0xa)) & fpinst2 { export mvfr0; } +@if defined(VERSION_8M) +vmrsReg: vpr is TMode=1 & thv_c1619=0xc & vpr { export vpr; } +define pcodeop SaveFloatingPointContext; # contedxt register, + +:vmrs^COND VRd,fpscr^"_nzcvq" is $(TMODE_E) & thv_c1627=0xef2 & VRd & thv_c0011=0xa10 & COND & fpscr +{ + build COND; + VRd = zext((fpscr[27,5] << 27)); +} + +:vmrs^COND VRd,"p0" is $(TMODE_E) & thv_c1627=0xefd & VRd & thv_c0011=0xa10 & COND +{ + build COND; + VRd = zext($(VPR_P0)); +} + +:vmrs^COND VRd,fpccr^"_ns" is $(TMODE_E) & thv_c1627=0xefe & VRd & thv_c0011=0xa10 & COND & fpccr +{ + build COND; + VRd = SaveFloatingPointContext(fpscr, 1:1); +} + +:vmrs^COND VRd,"fpcxt_s" is $(TMODE_E) & thv_c1627=0xeff & VRd & thv_c0011=0xa10 & COND +{ + build COND; + VRd = SaveFloatingPointContext(fpscr, 1:1); +} +@endif # VERSION_8M :vmrs^COND VRd,vmrsReg is COND & ( ($(AMODE) & ARMcond=1 & c2027=0xef & c0011=0xa10) | ($(TMODE_E) & thv_c2027=0xef & thv_c0011=0xa10)) & vmrsReg & VRd { + build COND; VRd = vmrsReg; } @@ -4601,18 +4931,45 @@ apsr: "apsr" is epsilon {} ($(TMODE_E) & thv_c1627=0xef1 & thv_c1215=15 & thv_c0011=0xa10) ) & COND & apsr & fpscr { + build COND; NG = $(FPSCR_N); ZR = $(FPSCR_Z); CY = $(FPSCR_C); OV = $(FPSCR_V); } +@if defined(VERSION_8M) +:vmsr^COND fpscr^"_nzcvq",VRd is $(TMODE_E) & thv_c1627=0xee2 & thv_c0011=0xa10 & COND & VRd & fpscr +{ + build COND; + fpscr[27,5] = VRd[27,5]; +} + +:vmsr^COND "p0",VRd is $(TMODE_E) & thv_c1627=0xeed & thv_c0011=0xa10 & COND & VRd +{ + build COND; + $(VPR_P0) = VRd[0,16]; +} +define pcodeop LoadFloatingPointContext; +:vmsr^COND fpccr^"_ns",VRd is $(TMODE_E) & thv_c1627=0xeee & thv_c0011=0xa10 & COND & VRd & fpccr +{ + build COND; + fpscr = LoadFloatingPointContext(VRd, 0:1); +} + +:vmsr^COND "fpcxt_s",VRd is $(TMODE_E) & thv_c1627=0xeef & thv_c0011=0xa10 & COND & VRd +{ + build COND; + fpscr = LoadFloatingPointContext(VRd, 1:1); +} +@endif # VERSION_8M :vmsr^COND vmrsReg,VRd is ( ($(AMODE) & ARMcond=1 & c2027=0xee & c0011=0xa10) | ($(TMODE_E) & thv_c2027=0xee & thv_c0011=0xa10) ) & COND & VRd & vmrsReg { + build COND; vmrsReg = VRd; } @@ -4707,6 +5064,10 @@ define pcodeop PolynomialMultiply; Qd = PolynomialMultiply(Qn,Qm,1:1); } +### +# VMULL (Integer and polynomial) +# + :vmull.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=0xc & Q6=0 & c0404=0) | ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0xc & thv_Q6=0 & thv_c0404=0) ) & esize2021 & Dm & Dn & Qd & udt { @@ -4714,7 +5075,7 @@ define pcodeop PolynomialMultiply; } :vmull.p8 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x5 & c2021=0 & c0811=0xe & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=0 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=0 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd { Qd = PolynomialMultiply(Dn,Dm,1:1); } @@ -4763,41 +5124,18 @@ vmlDmA: Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & Dm_4 & thv_M5 { # VMVN (immediate) # -:vmvn.i32 Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=0 & c0808=0 & c0407=3 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=0 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8 +:vmvn.^simdExpImmDT Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0407=3) ) & Dd & simdExpImmDT & simdExpImm_8 { Dd = ~simdExpImm_8; } -:vmvn.i32 Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=0 & c0808=0 & c0407=7 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=0 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16 +:vmvn.^simdExpImmDT Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0407=7) ) & Qd & simdExpImmDT & simdExpImm_16 { Qd = ~simdExpImm_16; } -:vmvn.i16 Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=0 & c0407=3 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8 -{ - Dd = ~simdExpImm_8; -} - -:vmvn.i16 Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=0 & c0407=7 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16 -{ - Qd = ~simdExpImm_16; -} - -:vmvn.i32 Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0911=6 & c0808=0 & c0407=3 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0911=6 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8 -{ - Dd = ~simdExpImm_8; -} - -:vmvn.i32 Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0911=6 & c0808=0 & c0407=7 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0911=6 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16 -{ - Qd = ~simdExpImm_16; -} ### # VMVN (register) diff --git a/pypcode/processors/ARM/data/languages/ARMt.pspec b/pypcode/processors/ARM/data/languages/ARMt.pspec index ff62a392..bbc92d2c 100644 --- a/pypcode/processors/ARM/data/languages/ARMt.pspec +++ b/pypcode/processors/ARM/data/languages/ARMt.pspec @@ -7,6 +7,7 @@ + @@ -42,6 +43,8 @@ + + diff --git a/pypcode/processors/ARM/data/languages/ARMtTHUMB.pspec b/pypcode/processors/ARM/data/languages/ARMtTHUMB.pspec index 58b125c9..c390c826 100644 --- a/pypcode/processors/ARM/data/languages/ARMtTHUMB.pspec +++ b/pypcode/processors/ARM/data/languages/ARMtTHUMB.pspec @@ -8,6 +8,7 @@ + @@ -43,6 +44,8 @@ + + diff --git a/pypcode/processors/ARM/data/languages/ARMt_v45.pspec b/pypcode/processors/ARM/data/languages/ARMt_v45.pspec index a8fe2ee8..26caefdd 100644 --- a/pypcode/processors/ARM/data/languages/ARMt_v45.pspec +++ b/pypcode/processors/ARM/data/languages/ARMt_v45.pspec @@ -8,6 +8,7 @@ + @@ -19,7 +20,11 @@ - + + + + + diff --git a/pypcode/processors/ARM/data/languages/ARMt_v6.pspec b/pypcode/processors/ARM/data/languages/ARMt_v6.pspec index a10848d1..bb89c424 100644 --- a/pypcode/processors/ARM/data/languages/ARMt_v6.pspec +++ b/pypcode/processors/ARM/data/languages/ARMt_v6.pspec @@ -7,6 +7,7 @@ + @@ -20,7 +21,11 @@ - + + + + + diff --git a/pypcode/processors/ARM/data/languages/ARMv8.sinc b/pypcode/processors/ARM/data/languages/ARMv8.sinc index ab4d26b3..5bbbd871 100644 --- a/pypcode/processors/ARM/data/languages/ARMv8.sinc +++ b/pypcode/processors/ARM/data/languages/ARMv8.sinc @@ -1,346 +1,825 @@ +@if defined(VERSION_8M) +#Cortex NEON only has q0-q7, no q8-q15, and the spacing is different from NEON +attach variables [ cor_Qn0 cor_Qd0 cor_Qm0 ] [ q0 q1 q2 q3 q4 q5 q6 q7 ]; +attach variables [ cor_Qd1 ] [ q1 q2 q3 q4 q5 q6 q7 _ ]; +attach variables [ cor_Qd2 ] [ q2 q3 q4 q5 q6 q7 _ _ ]; +attach variables [ cor_Qd3 ] [ q3 q4 q5 q6 q7 _ _ _ ]; + +attach variables [ cor_Rn ] [r0 r2 r4 r6 r8 r10 r12 lr ]; +attach variables [ cor_Rm ] [ r1 r3 r5 r7 r9 r11 sp _]; + +accum0505: "" is thv_c0505=0 { tmp:1 = 0; export *[const]:1 tmp; } +accum0505: "a" is thv_c0505=1 { tmp:1 = 1; export *[const]:1 tmp; } +exch1212: "" is thv_c1212=0 { tmp:1 = 0; export *[const]:1 tmp; } +exch1212: "x" is thv_c1212=1 { tmp:1 = 1; export *[const]:1 tmp; } + +# All v8m instructions currently state that +cor_Qd: cor_Qd0 is thv_D22=0 & cor_Qd0 { export cor_Qd0; } +cor_Qn: cor_Qn0 is thv_N7=0 & cor_Qn0 { export cor_Qn0; } +cor_Qm: cor_Qm0 is thv_M5=0 & cor_Qm0 { export cor_Qm0; } + +cor_Qdm: cor_Qd0 is thv_N7=0 & cor_Qd0 { export cor_Qd0; } + +RZn: thv_Rn is thv_Rn { export thv_Rn; } +RZn: 0 is thv_Rn=0 { local tmp:4 = 0; export *[const]:4 tmp; } + +RZm: thv_Rm is thv_Rm { export thv_Rm; } +RZm: 0 is thv_Rm=0 { local tmp:4 = 0; export *[const]:4 tmp; } + +cor_immShiftSR: "#"^immval is thv_c1214 & thv_c0607 [immval = (thv_c1214 << 2) | thv_c0607; ] { export *[const]:1 immval; } +cor_immShiftSR: "#"^immval is thv_c1214=0 & thv_c0607=0 [immval = 32 + 0; ] { export *[const]:1 immval; } + +cor_immBF: reloc is cor_immA & cor_immC & cor_immB [ reloc = (inst_start + 4) + ((cor_immA << 12) | (cor_immB << 2) | (cor_immC) | 1); ] { export *[ram]:4 reloc; } + +cor_bLabel: reloc is cor_boff [ reloc = inst_next + 4 + (cor_boff << 1); ] { export *[ram]:4 reloc; } + +cor_immBFC:reloc is thv_c1616 & cor_immC & cor_immB [ reloc = (inst_start + 4) + ((thv_c1616 << 12) | (cor_immB << 2) | (cor_immC) | 1); ] { export *[ram]:4 reloc; } + +cor_baLabel: reloc is cor_boff & thv_c1717=0 [ reloc = inst_next + 4 + (cor_boff << 1) + 3; ] { export *[ram]:4 reloc; } +cor_baLabel: reloc is cor_boff & thv_c1717=1 [ reloc = inst_next + 4 + (cor_boff << 1) + 5; ] { export *[ram]:4 reloc; } + +cor_cc: "eq" is cor_bcond=0 { export ZR; } +cor_cc: "ne" is cor_bcond=1 { tmp:1 = !ZR; export tmp; } +cor_cc: "cs" is cor_bcond=2 { export CY; } +cor_cc: "cc" is cor_bcond=3 { tmp:1 = !CY; export tmp; } +cor_cc: "mi" is cor_bcond=4 { export NG; } +cor_cc: "pl" is cor_bcond=5 { tmp:1 = !NG; export tmp; } +cor_cc: "vs" is cor_bcond=6 { export OV; } +cor_cc: "vc" is cor_bcond=7 { tmp:1 = !OV; export tmp; } +cor_cc: "hi" is cor_bcond=8 { tmp:1 = CY && (!ZR); export tmp; } +cor_cc: "ls" is cor_bcond=9 { tmp:1 = (!CY) || ZR; export tmp; } +cor_cc: "ge" is cor_bcond=10 { tmp:1 = (NG==OV); export tmp; } +cor_cc: "lt" is cor_bcond=11 { tmp:1 = (NG!=OV); export tmp; } +cor_cc: "gt" is cor_bcond=12 { tmp:1 = (!ZR) && (NG==OV); export tmp; } +cor_cc: "le" is cor_bcond=13 { tmp:1 = ZR || (NG!=OV); export tmp; } + +cor_fcc: "eq" is cor_fcond=0 { tmp:1 = (ZR==0); export tmp; } +cor_fcc: "ne" is cor_fcond=1 { tmp:1 = (ZR!=0); export tmp; } +cor_fcc: "cs" is cor_fcond=2 { tmp:1 = (CY==0); export tmp; } +cor_fcc: "cc" is cor_fcond=3 { tmp:1 = (CY!=0); export tmp; } +cor_fcc: "mi" is cor_fcond=4 { tmp:1 = (NG==0); export tmp; } +cor_fcc: "pl" is cor_fcond=5 { tmp:1 = (NG!=0); export tmp; } +cor_fcc: "vs" is cor_fcond=6 { tmp:1 = (OV==0); export tmp; } +cor_fcc: "vc" is cor_fcond=7 { tmp:1 = (OV!=0); export tmp; } +cor_fcc: "hi" is cor_fcond=8 { tmp:1 = CY && !ZR; export tmp; } +cor_fcc: "ls" is cor_fcond=9 { tmp:1 = (!CY) || (ZR); export tmp; } +cor_fcc: "ge" is cor_fcond=10 { tmp:1 = (NG == OV); export tmp; } +cor_fcc: "lt" is cor_fcond=11 { tmp:1 = (NG != OV); export tmp; } +cor_fcc: "gt" is cor_fcond=12 { tmp:1 = !ZR && (NG == OV); export tmp; } +cor_fcc: "le" is cor_fcond=13 { tmp:1 = ZR || (NG != OV); export tmp; } + +# A handful of instructions use inverted conditions +cor_ifcc: "eq" is cor_fcond=1 { tmp:1 = (ZR==0); export tmp; } +cor_ifcc: "ne" is cor_fcond=0 { tmp:1 = (ZR!=0); export tmp; } +cor_ifcc: "cs" is cor_fcond=3 { tmp:1 = (CY==0); export tmp; } +cor_ifcc: "cc" is cor_fcond=2 { tmp:1 = (CY!=0); export tmp; } +cor_ifcc: "mi" is cor_fcond=5 { tmp:1 = (NG==0); export tmp; } +cor_ifcc: "pl" is cor_fcond=4 { tmp:1 = (NG!=0); export tmp; } +cor_ifcc: "vs" is cor_fcond=7 { tmp:1 = (OV==0); export tmp; } +cor_ifcc: "vc" is cor_fcond=6 { tmp:1 = (OV!=0); export tmp; } +cor_ifcc: "hi" is cor_fcond=9 { tmp:1 = CY && !ZR; export tmp; } +cor_ifcc: "ls" is cor_fcond=8 { tmp:1 = (!CY) || (ZR); export tmp; } +cor_ifcc: "ge" is cor_fcond=11 { tmp:1 = (NG == OV); export tmp; } +cor_ifcc: "lt" is cor_fcond=10 { tmp:1 = (NG != OV); export tmp; } +cor_ifcc: "gt" is cor_fcond=13 { tmp:1 = !ZR && (NG == OV); export tmp; } +cor_ifcc: "le" is cor_fcond=12 { tmp:1 = ZR || (NG != OV); export tmp; } + +VP_fc000712: "eq" is thv_c1212=0 & thv_c0000=0 & thv_c0707=0 { local tmp:1 = 0; export *[const]:1 tmp; } +VP_fc000712: "ne" is thv_c1212=0 & thv_c0000=0 & thv_c0707=1 { local tmp:1 = 1; export *[const]:1 tmp; } +VP_fc000712: "cs" is thv_c1212=0 & thv_c0000=1 & thv_c0707=0 { local tmp:1 = 2; export *[const]:1 tmp; } +VP_fc000712: "hi" is thv_c1212=0 & thv_c0000=1 & thv_c0707=1 { local tmp:1 = 3; export *[const]:1 tmp; } +VP_fc000712: "ge" is thv_c1212=1 & thv_c0000=0 & thv_c0707=0 { local tmp:1 = 4; export *[const]:1 tmp; } +VP_fc000712: "lt" is thv_c1212=1 & thv_c0000=0 & thv_c0707=1 { local tmp:1 = 5; export *[const]:1 tmp; } +VP_fc000712: "gt" is thv_c1212=1 & thv_c0000=1 & thv_c0707=0 { local tmp:1 = 6; export *[const]:1 tmp; } +VP_fc000712: "le" is thv_c1212=1 & thv_c0000=1 & thv_c0707=1 { local tmp:1 = 7; export *[const]:1 tmp; } + +VP_fc050712: "eq" is thv_c1212=0 & thv_c0505=0 & thv_c0707=0 { local tmp:1 = 0; export *[const]:1 tmp; } +VP_fc050712: "ne" is thv_c1212=0 & thv_c0505=0 & thv_c0707=1 { local tmp:1 = 1; export *[const]:1 tmp; } +VP_fc050712: "cs" is thv_c1212=0 & thv_c0505=1 & thv_c0707=0 { local tmp:1 = 2; export *[const]:1 tmp; } +VP_fc050712: "hi" is thv_c1212=0 & thv_c0505=1 & thv_c0707=1 { local tmp:1 = 3; export *[const]:1 tmp; } +VP_fc050712: "ge" is thv_c1212=1 & thv_c0505=0 & thv_c0707=0 { local tmp:1 = 4; export *[const]:1 tmp; } +VP_fc050712: "lt" is thv_c1212=1 & thv_c0505=0 & thv_c0707=1 { local tmp:1 = 5; export *[const]:1 tmp; } +VP_fc050712: "gt" is thv_c1212=1 & thv_c0505=1 & thv_c0707=0 { local tmp:1 = 6; export *[const]:1 tmp; } +VP_fc050712: "le" is thv_c1212=1 & thv_c0505=1 & thv_c0707=1 { local tmp:1 = 7; export *[const]:1 tmp; } + +clrmlist15: r0 is thv_c0000=1 & r0 & thv_c0115=0 { r0 = 0; } +clrmlist15: r0, is thv_c0000=1 & r0 { r0 = 0; } +clrmlist15: is thv_c0000=0 { } +clrmlist14: clrmlist15^r1 is thv_c0101=1 & clrmlist15 & r1 & thv_c0215=0 { r1 = 0; } +clrmlist14: clrmlist15^r1, is thv_c0101=1 & clrmlist15 & r1 { r1 = 0; } +clrmlist14: clrmlist15 is thv_c0101=0 & clrmlist15 { } +clrmlist13: clrmlist14^r2 is thv_c0202=1 & clrmlist14 & r2 & thv_c0315=0 { r2 = 0; } +clrmlist13: clrmlist14^r2, is thv_c0202=1 & clrmlist14 & r2 { r2 = 0; } +clrmlist13: clrmlist14 is thv_c0202=0 & clrmlist14 { } +clrmlist12: clrmlist13^r3 is thv_c0303=1 & clrmlist13 & r3 & thv_c0415=0 { r3 = 0; } +clrmlist12: clrmlist13^r3, is thv_c0303=1 & clrmlist13 & r3 { r3 = 0; } +clrmlist12: clrmlist13 is thv_c0303=0 & clrmlist13 { } +clrmlist11: clrmlist12^r4 is thv_c0404=1 & clrmlist12 & r4 & thv_c0515=0 { r4 = 0; } +clrmlist11: clrmlist12^r4, is thv_c0404=1 & clrmlist12 & r4 { r4 = 0; } +clrmlist11: clrmlist12 is thv_c0404=0 & clrmlist12 { } +clrmlist10: clrmlist11^r5 is thv_c0505=1 & clrmlist11 & r5 & thv_c0615=0 { r5 = 0; } +clrmlist10: clrmlist11^r5, is thv_c0505=1 & clrmlist11 & r5 { r5 = 0; } +clrmlist10: clrmlist11 is thv_c0505=0 & clrmlist11 { } +clrmlist9: clrmlist10^r6 is thv_c0606=1 & clrmlist10 & r6 & thv_c0715=0 { r6 = 0; } +clrmlist9: clrmlist10^r6, is thv_c0606=1 & clrmlist10 & r6 { r6 = 0; } +clrmlist9: clrmlist10 is thv_c0606=0 & clrmlist10 { } +clrmlist8: clrmlist9^r7 is thv_c0707=1 & clrmlist9 & r7 & thv_c0815=0 { r7 = 0; } +clrmlist8: clrmlist9^r7, is thv_c0707=1 & clrmlist9 & r7 { r7 = 0; } +clrmlist8: clrmlist9 is thv_c0707=0 & clrmlist9 { } +clrmlist7: clrmlist8^r8 is thv_c0808=1 & clrmlist8 & r8 & thv_c0915=0 { r8 = 0; } +clrmlist7: clrmlist8^r8, is thv_c0808=1 & clrmlist8 & r8 { r8 = 0; } +clrmlist7: clrmlist8 is thv_c0808=0 & clrmlist8 { } +clrmlist6: clrmlist7^r9 is thv_c0909=1 & clrmlist7 & r9 & thv_c1015=0 { r9 = 0; } +clrmlist6: clrmlist7^r9, is thv_c0909=1 & clrmlist7 & r9 { r9 = 0; } +clrmlist6: clrmlist7 is thv_c0909=0 & clrmlist7 { } +clrmlist5: clrmlist6^r10 is thv_c1010=1 & clrmlist6 & r10 & thv_c1115=0 { r10 = 0; } +clrmlist5: clrmlist6^r10, is thv_c1010=1 & clrmlist6 & r10 { r10 = 0; } +clrmlist5: clrmlist6 is thv_c1010=0 & clrmlist6 { } +clrmlist4: clrmlist5^r11 is thv_c1111=1 & clrmlist5 & r11 & thv_c1215=0 { r11 = 0; } +clrmlist4: clrmlist5^r11, is thv_c1111=1 & clrmlist5 & r11 { r11 = 0; } +clrmlist4: clrmlist5 is thv_c1111=0 & clrmlist5 { } +clrmlist3: clrmlist4^r12 is thv_c1212=1 & clrmlist4 & r12 & thv_c1315=0 { r12 = 0; } +clrmlist3: clrmlist4^r12, is thv_c1212=1 & clrmlist4 & r12 { r12 = 0; } +clrmlist3: clrmlist4 is thv_c1212=0 & clrmlist4 { } +#clrmlist2 is impossible since sp (r13) is not allowed +clrmlist1: clrmlist3^lr is thv_c1414=1 & clrmlist3 & lr & thv_c1515=0 { lr = 0; } +clrmlist1: clrmlist3^lr, is thv_c1414=1 & clrmlist3 & lr { lr = 0; } +clrmlist1: clrmlist3 is thv_c1414=0 & clrmlist3 { } +clrmlist: {clrmlist1^"apsr"} is thv_c1515=1 & clrmlist1 { + Q = 0; + OV = 0; + CY = 0; + ZR = 0; + NG = 0; +} +clrmlist: {clrmlist1} is thv_c1515=0 & clrmlist1 { } + +crot0012: "#"^0 is thv_c0000=0 & thv_c1212=0 { local tmp:4 = 0; export *[const]:4 tmp; } +crot0012: "#"^90 is thv_c0000=0 & thv_c1212=1 { local tmp:4 = 90; export *[const]:4 tmp; } +crot0012: "#"^180 is thv_c0000=1 & thv_c1212=0 { local tmp:4 = 180; export *[const]:4 tmp; } +crot0012: "#"^270 is thv_c0000=1 & thv_c1212=1 { local tmp:4 = 270; export *[const]:4 tmp; } + +esize0708: "8" is thv_c0708=0 { tmp:1 = 1; export *[const]:1 tmp; } +esize0708: "16" is thv_c0708=1 { tmp:1 = 2; export *[const]:1 tmp; } +esize0708: "32" is thv_c0708=2 { tmp:1 = 4; export *[const]:1 tmp; } +esize0708: "64" is thv_c0708=3 { tmp:1 = 8; export *[const]:1 tmp; } + +esize1616: "16" is thv_c1616=0 { tmp:1 = 1; export *[const]:1 tmp; } +esize1616: "32" is thv_c1616=1 { tmp:1 = 2; export *[const]:1 tmp; } + +esize1920x2: val is thv_c1920 [ val = 16 << thv_c1920; ] { export *[const]:1 val; } + +esize2828: "32" is thv_c2828=0 { tmp:1 = 2; export *[const]:1 tmp; } +esize2828: "16" is thv_c2828=1 { tmp:1 = 1; export *[const]:1 tmp; } + +@endif #VERSION_8M + + +@if defined(VERSION_8M) +# (DDI0553B) C2.4.13 p. 555 ASRL (immediate) +:asrl^ItCond thv_Rn, thv_Rt2, cor_immShiftSR is $(TMODE_E) & ItCond & thv_c2327=0b10100 & thv_c2022=0b101 & thv_c1616=0 & thv_c1515=0 & thv_c0808=1 & thv_c0405=0b10 & thv_c0003=0b1111 & thv_Rn & thv_Rt2 &cor_immShiftSR { + build ItCond; + local tmp:8 = sext(thv_Rt2) << 32 | sext(thv_Rn); + tmp = tmp s>> cor_immShiftSR; + thv_Rn = tmp[0,32]; + thv_Rt2 = tmp[32,32]; +} + +# (DDI0553B) C2.4.14 p. 556 ASRL (register) +:asrl^ItCond thv_Rn, thv_Rt2, thv_Rd is $(TMODE_E) & ItCond & thv_c2327=0b10100 & thv_c2022=0b101 & thv_c1616=0 & thv_c1515=0 & thv_c0808=1 & thv_c0405=0b10 & thv_c0003=0b1101 & thv_Rn & thv_Rt2 & thv_Rd { + build ItCond; + local shiftAmount:1 = thv_Rd[0,8]; + local tmp:8 = sext(thv_Rt2) << 32 | sext(thv_Rn); + tmp = tmp s>> shiftAmount; + thv_Rn = tmp[0,32]; + thv_Rt2 = tmp[32,32]; +} + +# (DDI0553B) C2.4.17 p. 561 AUT +define pcodeop ValidatePAC; +:aut r12, lr, sp is thv_c1631=0xf3af & thv_c0015=0x802d & lr & sp & r12 { + ValidatePAC(lr, sp, r12); +} + +# (DDI0553B) C2.4.18 p. 563 AUTG +:autg^ItCond thv_Rt, thv_Rn, thv_Rm is ItCond & thv_c2031=0xfb5 & thv_c0811=0xf & thv_c0407=0 & thv_Rm & thv_Rn & thv_Rt { + build ItCond; + ValidatePAC(thv_Rn, thv_Rm, thv_Rt); +} + +# (DDI0553B) C2.4.20 p. 567 BF, BFX, BFL, BFLX, BFCSEL +define pcodeop BranchFuture; +:bf^ItCond cor_bLabel, cor_immBF is $(TMODE_F) & ItCond & thv_c2727=0 & thv_c2122=0b10 & thv_c1215=0xe & thv_bit00=1 & cor_bLabel & cor_immBF { + build ItCond; + BranchFuture(cor_bLabel, cor_immBF, 0x0:1, 0xe:1); +} + +:bfcsel^ItCond cor_bLabel, cor_immBFC, cor_baLabel, cor_cc is $(TMODE_F) & ItCond & thv_c2727=0 & thv_c2222=0b0 & thv_c1215=0xe & thv_bit00=1 & cor_bLabel & cor_immBFC & cor_baLabel & cor_cc { + build ItCond; + BranchFuture(cor_bLabel, cor_immBFC, cor_baLabel, cor_cc); +} + +:bfx^ItCond cor_bLabel, thv_Rn is $(TMODE_F) & ItCond & thv_c2727=0 & thv_c2022=0b110 & thv_c1215=0xe & cor_immC=0 & cor_immB=0 & thv_bit00=1 & cor_bLabel & thv_Rn { + build ItCond; + BranchFuture(cor_bLabel, thv_Rn, 0x0:1, 0xe:1); +} + +:bfl^ItCond cor_bLabel, cor_immBF is $(TMODE_F) & ItCond & thv_c2727=0 & thv_c2122=0b10 & thv_c1215=0xc & thv_bit00=1 & cor_bLabel & cor_immBF { + build ItCond; + BranchFuture(cor_bLabel, cor_immBF, 0x0:1, 0xe:1); +} + +:bflx^ItCond cor_bLabel, thv_Rn is $(TMODE_F) & ItCond & thv_c2727=0 & thv_c2022=0b111 & thv_c1215=0xc & cor_immC=0 & cor_immB=0 & thv_bit00=1 & cor_bLabel & thv_Rn { + build ItCond; + BranchFuture(cor_bLabel, thv_Rn, 0x0:1, 0xe:1); +} + +# (DDI0553B) C2.4.28 p. 583 BTI +define pcodeop BranchTargetID; +:bti is $(TMODE_F) & thv_c1627=0x3af & thv_c0015=0xf00f { + BranchTargetID(); +} + +# (DDI0553B) C2.4.30 p. 586 BXAUT +:bxaut^ItCond thv_Rt, thv_Rn, thv_Rm is $(TMODE_F) & ItCond & thv_c2427=0xb & thv_c2023=0x5 & thv_Rn & thv_Rt & thv_c0811=0xf & thv_c0407=0x1 & thv_Rm { + build ItCond; + ValidatePAC(thv_Rn, thv_Rm, thv_Rt); + BXWritePC(thv_Rn); + return [pc]; +} + +# (DDI0553B) C2.4.33 p. 591 CINC +:cinc thv_Rt2, RZn, cor_ifcc is $(TMODE_E) & thv_c2427=0xa & thv_c2023=0x5 & RZn & thv_c1215=0x9 & thv_Rt2 & cor_ifcc & (thv_c1619 < 15 & thv_c0003 < 15 & thv_c1619=thv_c0003) { + thv_Rt2 = (zext(cor_ifcc) * RZn + 1) + (zext(!cor_ifcc) * RZn); +} + +# (DDI0553B) C2.4.34 p. 592 CINV +:cinv thv_Rt2, RZn, cor_ifcc is $(TMODE_E) & thv_c2427=0xa & thv_c2023=0x5 & thv_c1215=0x8 & RZn & thv_Rt2 & cor_ifcc & (thv_c1619 < 15 & thv_c0003 < 15 & thv_c1619=thv_c0003) { + thv_Rt2 = (zext(cor_ifcc) * ~RZn) + (zext(!cor_ifcc) * RZn); +} + +# (DDI0553B) C2.4.36 p. 594 CLRM +:clrm^ItCond clrmlist is $(TMODE_E) & ItCond & thv_c2427=0x8 & thv_c2023=0x9 & thv_c1619=0xf & clrmlist { + build ItCond; + build clrmlist; +} + +# (DDI0553B) C2.4.42 p. 605 CNEG +:cneg thv_Rt2, RZn, cor_ifcc is $(TMODE_E) & thv_c2427=0xa & thv_c2023=0x5 & thv_c1215=0xb & RZn & thv_Rt2 & cor_ifcc & (thv_c1619=thv_c0003) { + thv_Rt2 = (zext(cor_ifcc) * RZn) + (zext(!cor_ifcc) * -RZn); +} + +# (DDI0553B) C2.4.45 p. 609 CSEL +:csel thv_Rt2, RZn, RZm, cor_fcc is $(TMODE_E) & thv_c2427=0xa & thv_c2023=0x5 & thv_c1215=0x8 & RZn & thv_Rt2 & cor_fcc & RZm { + thv_Rt2 = (zext(cor_fcc) * RZn) + (zext(!cor_fcc) * RZm); +} + +# (DDI0553B) C2.4.46 p. 611 CSET +:cset thv_Rt2, cor_ifcc is $(TMODE_E) & thv_c2427=0xa & thv_c2023=0x5 & thv_c1215=0x9 & thv_Rt2 & cor_ifcc & (thv_c1619=0xf & thv_c0003=0xf) { + thv_Rt2 = zext(cor_ifcc); +} + +# (DDI0553B) C2.4.37 p. 612 CSETM +:csetm thv_Rt2, cor_ifcc is $(TMODE_E) & thv_c2427=0xa & thv_c2023=0x5 & thv_c1215=0xa & thv_Rt2 & cor_ifcc & (thv_c1619=0xf & thv_c0003=0xf) { + thv_Rt2 = (zext(cor_ifcc) * ~0) + (zext(!cor_ifcc) * 0); +} + +# (DDI0553B) C2.4.48 p. 613 CSINC +:csinc thv_Rt2, RZn, RZm, cor_fcc is $(TMODE_E) & thv_c2427=0xa & thv_c2023=0x5 & thv_c1215=0x9 & RZn & thv_Rt2 & cor_fcc & RZm { + thv_Rt2 = (zext(cor_fcc) * RZn) + (zext(!cor_fcc) * RZm + 1); +} + +# (DDI0553B) C2.4.49 p. 615 CSINV +:csinv thv_Rt2, RZn, RZm, cor_fcc is $(TMODE_E) & thv_c2427=0xa & thv_c2023=0xa & thv_c1215=0xa & RZn & thv_Rt2 & cor_fcc & RZm { + thv_Rt2 = (zext(cor_fcc) * RZn) + (zext(!cor_fcc) * ~RZm); +} + +# (DDI0553B) C2.4.50 p. 617 CSNEG +:csneg thv_Rt2, RZn, RZm, cor_fcc is $(TMODE_E) & thv_c2427=0xa & thv_c2023=0x5 & thv_c1215=0xb & RZn & thv_Rt2 & cor_fcc & RZm { + thv_Rt2 = (zext(cor_fcc) * RZn) + (zext(!cor_fcc) * -RZm); +} + +@endif + # This macro is always defined in this file, but the ifdef may be # useful if it is moved to ARMinstructions.sinc. - -crc32_type: "b" is TMode=0 & c2122=0b00 & c0909=0 { } -crc32_type: "h" is TMode=0 & c2122=0b01 & c0909=0 { } -crc32_type: "w" is TMode=0 & c2122=0b10 & c0909=0 { } -crc32_type: "cb" is TMode=0 & c2122=0b00 & c0909=1 { } -crc32_type: "ch" is TMode=0 & c2122=0b01 & c0909=1 { } -crc32_type: "cw" is TMode=0 & c2122=0b10 & c0909=1 { } -crc32_type: "b" is TMode=1 & thv_c0405=0b00 { } -crc32_type: "h" is TMode=1 & thv_c0405=0b01 { } -crc32_type: "w" is TMode=1 & thv_c0405=0b10 { } +crc32_type: "b" is TMode=0 & c2122=0b00 & c0909=0 { } +crc32_type: "h" is TMode=0 & c2122=0b01 & c0909=0 { } +crc32_type: "w" is TMode=0 & c2122=0b10 & c0909=0 { } +crc32_type: "cb" is TMode=0 & c2122=0b00 & c0909=1 { } +crc32_type: "ch" is TMode=0 & c2122=0b01 & c0909=1 { } +crc32_type: "cw" is TMode=0 & c2122=0b10 & c0909=1 { } +crc32_type: "b" is TMode=1 & thv_c0405=0b00 { } +crc32_type: "h" is TMode=1 & thv_c0405=0b01 { } +crc32_type: "w" is TMode=1 & thv_c0405=0b10 { } define pcodeop Crc32Calc; # F5.1.39,40 p7226,7229 CRC32,CRC32C A1 -:crc32^crc32_type Rd,Rn,Rm - is TMode=0 & c2831=0b1110 & c2327=0b00010 & c2020=0 & c0407=0b0100 & c1011=0b00 & c0808=0 - & crc32_type & Rn & Rd & Rm - { Rd = Crc32Calc(Rn,Rm); } +:crc32^crc32_type Rd,Rn,Rm is TMode=0 & c2831=0b1110 & c2327=0b00010 & c2020=0 & c0407=0b0100 & c1011=0b00 & c0808=0 & crc32_type & Rn & Rd & Rm { + Rd = Crc32Calc(Rn,Rm); +} # F5.1.39 p7226 CRC32 T1 -:crc32^crc32_type thv_Rt2,thv_Rn,thv_Rm - is TMode=1 & thv_c2031=0b111110101100 & thv_c1215=0b1111 & thv_c0607=0b10 - & crc32_type & thv_Rn & thv_Rt2 & thv_Rm - { thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); } +:crc32^crc32_type thv_Rt2,thv_Rn,thv_Rm is TMode=1 & thv_c2031=0b111110101100 & thv_c1215=0b1111 & thv_c0607=0b10 & crc32_type & thv_Rn & thv_Rt2 & thv_Rm { + thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); +} # F5.1.40 p7229 CRC32C T1 -:crc32c^crc32_type thv_Rt2,thv_Rn,thv_Rm - is TMode=1 & thv_c2031=0b111110101101 & thv_c1215=0b1111 & thv_c0607=0b10 - & crc32_type & thv_Rn & thv_Rt2 & thv_Rm - { thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); } +:crc32c^crc32_type thv_Rt2,thv_Rn,thv_Rm is TMode=1 & thv_c2031=0b111110101101 & thv_c1215=0b1111 & thv_c0607=0b10 & crc32_type & thv_Rn & thv_Rt2 & thv_Rm { + thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); +} + +# F5.1.41 +define pcodeop consumptionOfSpeculativeDataBarrier; + +:csdb^COND is $(AMODE) & COND & c0027=0x320f014 { + build COND; + consumptionOfSpeculativeDataBarrier(); +} + +:csdb^ItCond is TMode=1 & ItCond & thv_c1631=0xf3bf & thv_c0015=0x8014 { + build ItCond; + consumptionOfSpeculativeDataBarrier(); +} define pcodeop DCPSInstruction; -dcps_lev:1 is TMode=1 & thv_c0001=0b01 { export 1:1; } -dcps_lev:2 is TMode=1 & thv_c0001=0b10 { export 2:1; } -dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } +dcps_lev:1 is TMode=1 & thv_c0001=0b01 { export 1:1; } +dcps_lev:2 is TMode=1 & thv_c0001=0b10 { export 2:1; } +dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } # F5.1.43 p7235 DCPS1,DCPS2,DCPS3 DSPS1 variant -:dcps^dcps_lev - is TMode=1 & thv_c1631=0b1111011110001111 & thv_c0215=0b10000000000000 & (thv_c0101=1 | thv_c0000=1) & dcps_lev +:dcps^dcps_lev is TMode=1 & thv_c1631=0b1111011110001111 & thv_c0215=0b10000000000000 & (thv_c0101=1 | thv_c0000=1) & dcps_lev { DCPSInstruction(dcps_lev:1); } +# F5.1.52 +define pcodeop ErrorSynchronizationBarrier; + +:esb^COND is $(AMODE) & COND & c0027=0x320f010 { + build COND; + ErrorSynchronizationBarrier(); +} + +:esb^ItCond is TMode=1 & ItCond & thv_c1631=0xf3af & thv_c0015=0x8010 { + build ItCond; + ErrorSynchronizationBarrier(); +} + +@if defined(VERSION_8M) +define pcodeop loopClearTailPredication; + +loopAddr: reloc is cor_immB & thv_c1111 [ reloc = inst_next - (cor_immB <<2) | (thv_c1111 << 1); ] { export *[ram]:4 reloc; } + +# (DDI0553B) C2.4.67 p. 646 LCTP +:lctp is TMode=1 & thv_c1631=0xf00f & thv_c0015=0xe001 { + fpscr[16,3] = 4; +} + +define pcodeop loopEnd; + +# (DDI0553B) C2.4.103 p. 713 LE, LETP +:le lr, loopAddr is TMode=1 & thv_c1631=0xf00f & thv_c1215=0b1100 & thv_c0000=1 & loopAddr & lr { + lr = lr - 1; + loopEnd(); + goto loopAddr; +} + +# T2 == forever variant +:le loopAddr is TMode=1 & thv_c1631=0xf02f & thv_c1215=0b1100 & thv_c0000=1 & loopAddr { + goto loopAddr; +} + +:letp lr, loopAddr is TMode=1 & thv_c1631=0xf01f & thv_c1215=0b1100 & thv_c0000=1 & loopAddr & lr { + ltpsize:1 = fpscr[16,3]; + if (lr <= (1 << (4-ltpsize))) goto ; + lr = lr - (1 << (4-ltpsize)); + goto ; + + fpscr[16,3] = 4; + + goto loopAddr; +} + +@endif # VERSION_8M + # F5.1.57 p7268 LDA -:lda^COND Rd,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xc9f - { - build COND; - Rd = *Rn; - } +:lda^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xc9f { + build COND; + Rd = *Rn; +} # F5.1.57 p7268 LDA -:lda thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1010 - & ItCond & thv_Rn & thv_Rt - { - build ItCond; - thv_Rt = *thv_Rn; - } +:lda thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1010 + & ItCond & thv_Rn & thv_Rt { + build ItCond; + thv_Rt = *thv_Rn; +} # F5.1.58 p7270 LDAB -:ldab^COND Rd,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xc9f - { - build COND; - val:1 = *Rn; - Rd = zext(val); - } +:ldab^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xc9f { + build COND; + val:1 = *Rn; + Rd = zext(val); +} # F5.1.58 p7270 LDAB -:ldab thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1000 - & ItCond & thv_Rt & thv_Rn - { - build ItCond; - val:1 = *thv_Rn; - thv_Rt = zext(val); - } +:ldab thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1000 + & ItCond & thv_Rt & thv_Rn { + build ItCond; + val:1 = *thv_Rn; + thv_Rt = zext(val); +} # F5.1.59 p7272 LDAEX -:ldaex^COND Rd,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xe9f - { - build COND; - Rd = *Rn; - } +:ldaex^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xe9f { + build COND; + Rd = *Rn; +} # F5.1.59 p7272 LDAEX -:ldaex thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1110 - & ItCond & thv_Rt & thv_Rn - { - build ItCond; - thv_Rt = *thv_Rn; - } +:ldaex thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1110 + & ItCond & thv_Rt & thv_Rn { + build ItCond; + thv_Rt = *thv_Rn; +} # F5.1.60 p7274 LDAEXB -:ldaexb^COND Rd,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xe9f - { - build COND; - val:1 = *Rn; - Rd = zext(val); - } +:ldaexb^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xe9f { + build COND; + val:1 = *Rn; + Rd = zext(val); +} # F5.1.60 p7274 LDAEXB -:ldaexb thv_Rt,thv_Rn - is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1100 - & ItCond & thv_Rt & thv_Rn - { - build ItCond; - val:1 = *thv_Rn; - thv_Rt = zext(val); - } +:ldaexb thv_Rt,thv_Rn is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1100 + & ItCond & thv_Rt & thv_Rn { + build ItCond; + val:1 = *thv_Rn; + thv_Rt = zext(val); +} # F5.1.61 p7274 LDAEXD -:ldaexd^COND Rd,Rd2,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xe9f - { - local addr:4 = Rn; - build COND; +:ldaexd^COND Rd,Rd2,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xe9f { + local addr:4 = Rn; + build COND; @if ENDIAN == "big" - Rd = *(addr + 4); - Rd2 = *(addr); -@else # ENDIAN == "little" - Rd = *(addr); - Rd2 = *(addr + 4); -@endif # ENDIAN == "little" - } + Rd = *(addr + 4); + Rd2 = *(addr); +@else # ENDIAN == "little" + Rd = *(addr); + Rd2 = *(addr + 4); +@endif # ENDIAN == "little" +} # F5.1.61 p7274 LDAEXD -:ldaexd thv_Rt,thv_Rt2,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1111 - & ItCond & thv_Rt & thv_Rt2 & thv_Rn - { - local addr:4 = thv_Rn; - build ItCond; +:ldaexd thv_Rt,thv_Rt2,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1111 + & ItCond & thv_Rt & thv_Rt2 & thv_Rn { + local addr:4 = thv_Rn; + build ItCond; @if ENDIAN == "big" - thv_Rt = *(addr + 4); - thv_Rt2 = *(addr); -@else # ENDIAN == "little" - thv_Rt = *(addr); - thv_Rt2 = *(addr + 4); -@endif # ENDIAN == "little" - } + thv_Rt = *(addr + 4); + thv_Rt2 = *(addr); +@else # ENDIAN == "little" + thv_Rt = *(addr); + thv_Rt2 = *(addr + 4); +@endif # ENDIAN == "little" +} # F5.1.62 p7278 LDAEXH -:ldaexh^COND Rd,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xe9f - { - build COND; - val:2 = *Rn; - Rd = zext(val); - } +:ldaexh^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xe9f { + build COND; + val:2 = *Rn; + Rd = zext(val); +} # F5.1.62 p7278 LDAEXH -:ldaexh thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1101 - & ItCond & thv_Rt & thv_Rn - { - build ItCond; - val:2 = *thv_Rn; - thv_Rt = zext(val); - } +:ldaexh thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1101 + & ItCond & thv_Rt & thv_Rn { + build ItCond; + val:2 = *thv_Rn; + thv_Rt = zext(val); +} # F5.1.63 p7280 LDAH -:ldah^COND Rd,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xc9f - { - build COND; - val:2 = *Rn; - Rd = zext(val); - } +:ldah^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xc9f { + build COND; + val:2 = *Rn; + Rd = zext(val); +} # F5.1.63 p7280 LDAH -:ldah thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1001 - & ItCond & thv_Rt & thv_Rn - { - build ItCond; - val:2 = *thv_Rn; - thv_Rt = zext(val); - } +:ldah thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1001 + & ItCond & thv_Rt & thv_Rn { + build ItCond; + val:2 = *thv_Rn; + thv_Rt = zext(val); +} + +@if defined(VERSION_8M) +# (DDI0553B) C2.4.106 p. 719 LSLL (immediate) +:lsll^ItCond thv_Rn, thv_Rt2, cor_immShiftSR is $(TMODE_E) & ItCond & thv_c2327=0b10100 & thv_c2022=0b101 & thv_c1616=0 & thv_c1515=0 & thv_c0808=1 & thv_c0405=0b00 & thv_c0003=0b1111 & thv_Rn & thv_Rt2 &cor_immShiftSR { + build ItCond; + local tmp:8 = sext(thv_Rt2) << 32 | sext(thv_Rn); + tmp = tmp << cor_immShiftSR; + thv_Rn = tmp[0,32]; + thv_Rt2 = tmp[32,32]; +} + +# (DDI0553B) C2.4.107 p. 720 LSLL (register) +:lsll^ItCond thv_Rn, thv_Rt2, thv_Rd is $(TMODE_E) & ItCond & thv_c2327=0b10100 & thv_c2022=0b101 & thv_c1616=0 & thv_c1515=0 & thv_c0808=1 & thv_c0405=0b00 & thv_c0003=0b1101 & thv_Rn & thv_Rt2 & thv_Rd { + build ItCond; + local shiftAmount:1 = thv_Rd[0,8]; + local tmp:8 = sext(thv_Rt2) << 32 | sext(thv_Rn); + tmp = tmp << shiftAmount; + thv_Rn = tmp[0,32]; + thv_Rt2 = tmp[32,32]; +} + +# (DDI0553B) C2.4.112 p. 729 LSRL (immediate) +:lsrl^ItCond thv_Rn, thv_Rt2, cor_immShiftSR is $(TMODE_E) & ItCond & thv_c2327=0b10100 & thv_c2022=0b101 & thv_c1616=0 & thv_c1515=0 & thv_c0808=1 & thv_c0405=0b01 & thv_c0003=0b1111 & thv_Rn & thv_Rt2 &cor_immShiftSR { + build ItCond; + local tmp:8 = sext(thv_Rt2) << 32 | sext(thv_Rn); + tmp = tmp >> cor_immShiftSR; + thv_Rn = tmp[0,32]; + thv_Rt2 = tmp[32,32]; +} + +define pcodeop createPAC; + +:pac r12, lr, sp is thv_c1631=0xf3af & thv_c0015=0x801d & lr & sp & r12 { + createPAC(lr, sp, r12, 0:1); +} + +:pacbti r12, lr, sp is thv_c1631=0xf3af & thv_c0015=0x800d & lr & sp & r12 { + createPAC(lr, sp, r12, 1:1); # clear BTI +} + +:pacg^ItCond thv_Rt, thv_Rn, thv_Rm is ItCond & thv_c2031=0xf66 & thv_c0811=0xf & thv_c0407=0 & thv_Rm & thv_Rn & thv_Rt { + build ItCond; + createPAC(thv_Rn, thv_Rm, thv_Rt, 0:1); +} + +@endif # VERSION_8M + +# F5.1.141 p7795 PSSBB A1 variant +define pcodeop physicalSpeculativeStoreBypassBarrier; +:pssbb is $(AMODE) & c0031=0xf57ff044 { + physicalSpeculativeStoreBypassBarrier(); +} + +# F5.1.141 p7795 PSSBB T1 variant +:pssbb is TMode=1 & thv_c1631=0xf3bf & thv_c0015=0x8f44 { + physicalSpeculativeStoreBypassBarrier(); +} # F5.1.185 p7573 SEVL A1 variant -:sevl^COND - is TMode=0 & ARMcond=1 & COND & c1627=0b001100100000 & c0007=0b00000101 - { - build COND; - SendEvent(); - } +:sevl^COND is TMode=0 & ARMcond=1 & COND & c1627=0b001100100000 & c0007=0b00000101 { + build COND; + SendEvent(); +} # F5.1.185 p7573 SEVL T2 variant -:sevl.w - is TMode=1 & thv_c2031=0b111100111010 & thv_c1415=0b10 & thv_c1212=0 & thv_c0010=0b00000000101 - & ItCond - { - build ItCond; - SendEvent(); - } +:sevl.w is TMode=1 & thv_c0015=0x8005 & thv_c1631=0xf3af#thv_c2031=0b111100111010 & thv_c1415=0b10 & thv_c1212=0 & thv_c0010=0b00000000101 + & ItCond { + build ItCond; + SendEvent(); +} + +@if defined(VERSION_8M) +:sqrshr^ItCond thv_Rn, thv_Rt is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_Rn & thv_Rt & thv_c0811=0xf & thv_c0407=2 & thv_c0003=0xd { + build ItCond; + local amount = thv_Rt[0,8]; + local left = amount s< 0; + local sum = thv_Rn; + sum = (zext(left) * (1 s>> (amount-1))) + (zext(!left) * (1 << (amount-1))); + sum = (zext(left) * (1 << amount)) + (zext(!left) * (1 s>> amount)); + thv_Rn = SignedSaturate(sum,32:2); +} + +qSat: "#"^satAmount is thv_c0707 [ satAmount = 48 << (thv_c0707 * 16); ] { export *[const]:2 satAmount; } + +:sqrshrl^ItCond thv_RdaLo, thv_RdaHi, qSat, thv_Rt is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_RdaLo & thv_c1616=1 & thv_RdaHi & thv_c0808=1 & thv_Rt & qSat & thv_c0406=2 & thv_c0003=0xd { + build ItCond; + local amount = thv_Rt[0,8]; + local left = amount s< 0; + local sum:8 = zext(thv_RdaHi) << 32 | zext(thv_RdaLo); + sum = (zext(left) * (1 s>> (amount-1))) + (zext(!left) * (1 << (amount-1))); + sum = (zext(left) * (1 << amount)) + (zext(!left) * (1 s>> amount)); + sum = SignedSaturate(sum,qSat); + thv_RdaLo = sum[0,32]; + thv_RdaHi = sum[32,32]; +} + +qShift: "#"^shAmount is thv_c0607 & thv_c1214 [ shAmount = (thv_c1214 << 2) + thv_c0607; ] { export *[const]:1 shAmount; } +qShift: "#"^0 is thv_c0607=0 & thv_c1214=0 { tmp:1 = 0; export *[const]:1 tmp; } + +:sqshl^ItCond thv_Rn, qShift is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_Rn & qShift & thv_c1515=0 & thv_c0811=0xf & thv_c0405=3 & thv_c0003=0xf { + local amount = qShift; + local result = thv_Rn << amount; + thv_Rn = SignedSaturate(result,32:2); +} + +:sqshll^ItCond thv_RdaLo, thv_RdaHi, qShift is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_RdaLo & thv_c1616=1 & thv_RdaHi & thv_c0808=1 & thv_c1515=0 & qShift & thv_c0405=3 & thv_c0003=0xf { + build ItCond; + local amount = qShift; + local result:8 = zext(thv_RdaHi) << 32 | zext(thv_RdaLo); + result = result << amount; + result = SignedSaturate(result,64:2); + thv_RdaLo = result[0,32]; + thv_RdaHi = result[32,32]; +} + + +:sqshr^ItCond thv_Rn, qShift is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_Rn & qShift & thv_c1515=0 & thv_c0811=0xf & thv_c0405=2 & thv_c0003=0xf { + local amount = qShift; + local result = thv_Rn << (amount-1); + result = result s>> amount; + thv_Rn = SignedSaturate(result,32:2); +} + +:sqshrl^ItCond thv_RdaLo, thv_RdaHi, qShift is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_RdaLo & thv_c1616=1 & thv_RdaHi & thv_c0808=1 & thv_c1515=0 & qShift & thv_c0405=2 & thv_c0003=0xf { + build ItCond; + local amount = qShift; + local result:8 = zext(thv_RdaHi) << 32 | zext(thv_RdaLo); + result = result s>> amount; + result = SignedSaturate(result,64:2); + thv_RdaLo = result[0,32]; + thv_RdaHi = result[32,32]; +} + +@endif #VERSION_8M # F5.1.217 p7642 STL -:stl^COND Rm,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & c0415=0xfc9 & Rm - { - build COND; - *Rn = Rm; - } +:stl^COND Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & c0415=0xfc9 & Rm { + build COND; + *Rn = Rm; +} # F5.1.217 p7642 STL -:stl thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1010 - & ItCond & thv_Rt & thv_Rn - { - build ItCond; - *thv_Rn = thv_Rt; - } +:stl thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1010 + & ItCond & thv_Rt & thv_Rn { + build ItCond; + *thv_Rn = thv_Rt; +} # F5.1.218 p7644 STLB -:stlb^COND Rm,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & c0415=0xfc9 & Rm - { - build COND; - *:1 Rn = Rm[0,8]; - } +:stlb^COND Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & c0415=0xfc9 & Rm { + build COND; + *:1 Rn = Rm[0,8]; +} # F5.1.218 p7644 STLB -:stlb thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1000 - & ItCond & thv_Rt & thv_Rn - { - build ItCond; - *:1 thv_Rn = thv_Rt[0,8]; - } +:stlb thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1000 + & ItCond & thv_Rt & thv_Rn { + build ItCond; + *:1 thv_Rn = thv_Rt[0,8]; +} # F5.1.219 p7646 STLEX -:stlex^COND Rd,Rm,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & Rd & c0411=0xe9 & Rm - { - build COND; - *Rn = Rm; - Rd = 0; - } +:stlex^COND Rd,Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & Rd & c0411=0xe9 & Rm { + build COND; + *Rn = Rm; + Rd = 0; +} # F5.1.219 p7646 STLEX -:stlex thv_Rm,thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1110 - & ItCond & thv_Rm & thv_Rt & thv_Rn - { - build ItCond; - *thv_Rn = thv_Rt; - thv_Rm = 0; - } +:stlex thv_Rm,thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1110 + & ItCond & thv_Rm & thv_Rt & thv_Rn { + build ItCond; + *thv_Rn = thv_Rt; + thv_Rm = 0; +} # F5.1.220 p7649 STLEXB -:stlexb^COND Rd,Rm,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & Rd & c0411=0xe9 & Rm - { - build COND; - *:1 Rn = Rm[0,8]; - Rd = 0; - } +:stlexb^COND Rd,Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & Rd & c0411=0xe9 & Rm { + build COND; + *:1 Rn = Rm[0,8]; + Rd = 0; +} # F5.1.220 p7649 STLEXB -:stlexb thv_Rm,thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1100 - & ItCond & thv_Rm & thv_Rt & thv_Rn - { - build ItCond; - *:1 thv_Rn = thv_Rt[0,8]; - thv_Rm = 0; - } +:stlexb thv_Rm,thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1100 + & ItCond & thv_Rm & thv_Rt & thv_Rn { + build ItCond; + *:1 thv_Rn = thv_Rt[0,8]; + thv_Rm = 0; +} # F5.1.221 p7651 STLEXD -:stlexd^COND Rd,Rm,Rm2,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1a & Rn & Rd & c0411=0xe9 & Rm & Rm2 - { - build COND; +:stlexd^COND Rd,Rm,Rm2,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1a & Rn & Rd & c0411=0xe9 & Rm & Rm2 { + build COND; @if ENDIAN == "big" - *Rn = Rm; - *(Rn + 4) = Rm2; -@else # ENDIAN == "little" - *Rn = Rm2; - *(Rn + 4) = Rm; -@endif # ENDIAN == "little" - Rd = 0; - } + *Rn = Rm; + *(Rn + 4) = Rm2; +@else # ENDIAN == "little" + *Rn = Rm2; + *(Rn + 4) = Rm; +@endif # ENDIAN == "little" + Rd = 0; +} # F5.1.221 p7651 STLEXD -:stlexd thv_Rm,thv_Rt,thv_Rt2,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1111 - & ItCond & thv_Rm & thv_Rt & thv_Rt2 & thv_Rn - { - build ItCond; +:stlexd thv_Rm,thv_Rt,thv_Rt2,[thv_Rn] is TMode=1 & ItCond & thv_c2031=0b111010001100 & thv_c0407=0b1111 & thv_Rm & thv_Rt & thv_Rt2 & thv_Rn { + build ItCond; @if ENDIAN == "big" - *thv_Rn = thv_Rt; - *(thv_Rn + 4) = thv_Rt2; -@else # ENDIAN == "little" - *thv_Rn = thv_Rt2; - *(thv_Rn + 4) = thv_Rt; -@endif # ENDIAN == "little" - thv_Rm = 0; - } + *thv_Rn = thv_Rt; + *(thv_Rn + 4) = thv_Rt2; +@else # ENDIAN == "little" + *thv_Rn = thv_Rt2; + *(thv_Rn + 4) = thv_Rt; +@endif # ENDIAN == "little" + thv_Rm = 0; +} # F5.1.222 p7654 STLEXH -:stlexh^COND Rd,Rm,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & Rd & c0411=0xe9 & Rm - { - build COND; - *:2 Rn = Rm[0,16]; - Rd = 0; - } +:stlexh^COND Rd,Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & Rd & c0411=0xe9 & Rm { + build COND; + *:2 Rn = Rm[0,16]; + Rd = 0; +} # F5.1.222 p7654 STLEXH -:stlexh thv_Rm,thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1101 - & ItCond & thv_Rm & thv_Rt & thv_Rn - { - build ItCond; - *:2 thv_Rn = thv_Rt[0,16]; - thv_Rm = 0; - } +:stlexh thv_Rm,thv_Rt,[thv_Rn] is TMode=1 & ItCond & thv_c2031=0b111010001100 & thv_c0407=0b1101 & thv_Rm & thv_Rt & thv_Rn { + build ItCond; + *:2 thv_Rn = thv_Rt[0,16]; + thv_Rm = 0; +} # F5.1.223 p7657 STLH -:stlh^COND Rm,[Rn] - is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & c0415=0xfc9 & Rm - { - build COND; - *:2 Rn = Rm[0,16]; - } +:stlh^COND Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & c0415=0xfc9 & Rm { + build COND; + *:2 Rn = Rm[0,16]; +} # F5.1.223 p7657 STLH -:stlh thv_Rt,[thv_Rn] - is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1001 - & ItCond & thv_Rt & thv_Rn - { - build ItCond; - *:2 thv_Rn = thv_Rt[0,16]; - } +:stlh thv_Rt,[thv_Rn] is TMode=1 & ItCond & thv_c2031=0b111010001100 & thv_c0407=0b1001 & thv_Rt & thv_Rn { + build ItCond; + *:2 thv_Rn = thv_Rt[0,16]; +} + +@if defined(VERSION_8M) +:uqrshr^ItCond thv_Rn, thv_Rt is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_Rn & thv_Rt & thv_c0811=0xf & thv_c0407=0 & thv_c0003=0xd { + build ItCond; + local amount = thv_Rt[0,8]; + local left = amount s< 0; + local sum = thv_Rn; + sum = (zext(left) * (1 >> (amount-1))) + (zext(!left) * (1 << (amount-1))); + sum = (zext(left) * (1 << amount)) + (zext(!left) * (1 >> amount)); + thv_Rn = UnsignedSaturate(sum,32:2); +} + +:uqrshrl^ItCond thv_RdaLo, thv_RdaHi, qSat, thv_Rt is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_RdaLo & thv_c1616=1 & thv_RdaHi & thv_c0808=1 & thv_Rt & qSat & thv_c0406=0 & thv_c0003=0xd { + build ItCond; + local amount = thv_Rt[0,8]; + local left = amount s< 0; + local sum:8 = zext(thv_RdaHi) << 32 | zext(thv_RdaLo); + sum = (zext(left) * (1 >> (amount-1))) + (zext(!left) * (1 << (amount-1))); + sum = (zext(left) * (1 << amount)) + (zext(!left) * (1 >> amount)); + sum = UnsignedSaturate(sum,qSat); + thv_RdaLo = sum[0,32]; + thv_RdaHi = sum[32,32]; +} + +:uqshl^ItCond thv_Rn, qShift is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_Rn & qShift & thv_c1515=0 & thv_c0811=0xf & thv_c0405=0 & thv_c0003=0xf { + local amount = qShift; + local result = thv_Rn << amount; + thv_Rn = UnsignedSaturate(result,32:2); +} + +:uqshll^ItCond thv_RdaLo, thv_RdaHi, qShift is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_RdaLo & thv_c1616=1 & thv_RdaHi & thv_c0808=1 & thv_c1515=0 & qShift & thv_c0405=0 & thv_c0003=0xf { + build ItCond; + local amount = qShift; + local result:8 = zext(thv_RdaHi) << 32 | zext(thv_RdaLo); + result = result << amount; + result = UnsignedSaturate(result,64:2); + thv_RdaLo = result[0,32]; + thv_RdaHi = result[32,32]; +} + + +:uqshr^ItCond thv_Rn, qShift is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_Rn & qShift & thv_c1515=0 & thv_c0811=0xf & thv_c0405=1 & thv_c0003=0xf { + build ItCond; + local amount = qShift; + local result = thv_Rn << (amount-1); + result = result >> amount; + thv_Rn = UnsignedSaturate(result,32:2); +} + +:uqshrl^ItCond thv_RdaLo, thv_RdaHi, qShift is $(TMODE_E) & ItCond & thv_c2427=0xa & thv_c2023=0x5 & thv_RdaLo & thv_c1616=1 & thv_RdaHi & thv_c0808=1 & thv_c1515=0 & qShift & thv_c0405=1 & thv_c0003=0xf { + build ItCond; + local amount = qShift; + local result:8 = zext(thv_RdaHi) << 32 | zext(thv_RdaLo); + result = result >> amount; + result = UnsignedSaturate(result,64:2); + thv_RdaLo = result[0,32]; + thv_RdaHi = result[32,32]; +} + +@endif #VERSION_8M + -@ifdef INCLUDE_NEON # Advanced SIMD support / NEON in ARMv8 @@ -367,13 +846,6 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } -# FixedToFP(fp, M, N, fbits, unsigned, rounding) -# Convert M-bit fixed point with fbits fractional bits to N-bit -# floating point, controlled by unsigned flag and rounding. Can -# also be used with packed "SIMD" floats. - -define pcodeop FixedToFP; - # FPConvert(fp, M, N [, rounding]) # Convert floating point between from M-bit to N-bit precision. # Can also be used with packed "SIMD" floats. Sometimes @@ -395,13 +867,6 @@ define pcodeop FPConvert; define pcodeop FPConvertInexact; -# FPToFixed(fp, M, N, fbits, unsigned, rounding) -# Convert M-bit floating point to N-bit fixed point with fbits -# fractional bits, controlled by unsigned flag and rounding. -# between different precisions. Can also be used with packed -# "SIMD" floats. - -define pcodeop FPToFixed; # FPRoundInt(fp, N, rounding, exact) # Round fp to nearest integral floating point, controlled by @@ -414,744 +879,1597 @@ define pcodeop FPRoundInt; define pcodeop PolynomialMult; - - +@if defined(VERSION_8M) +# (DDI0553B) C2.4.295 p. 1013 VABAV +define pcodeop VectorAbsoluteDifferenceAndAccumulateAcrossVector; +:vabav.^udt^esize2021 cor_Qn0, cor_Qm0 is $(TMODE_EorF) & udt & thv_c2427=0xe & thv_c2223=2 & esize2021 & thv_c1616=0 & thv_c0811=0xf & thv_c0606=0 & thv_c0404=0 & thv_c0000=1 & thv_Rd & cor_Qn0 & cor_Qm0 { + thv_Rd = VectorAbsoluteDifferenceAndAccumulateAcrossVector(thv_Rd, cor_Qn0, cor_Qm0, esize2021, udt); +} + +carryInit1212: "" is thv_c1212=0 { tmp:1 = $(FPSCR_C); export *[const]:1 tmp; } +carryInit1212: "i" is thv_c1212=1 { tmp:1 = 1; export *[const]:1 tmp; } + +# (DDI0553B) C2.4.301 p. 1025 VADC +define pcodeop WholeVectorAddWithCarry; +:vadc^carryInit1212^".i32" cor_Qd, cor_Qn, cor_Qm is $(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c1616=0 & thv_c0811=0xf & thv_c0606=0 & thv_c0404=0 & thv_c0000=0 & carryInit1212 & cor_Qd & cor_Qn & cor_Qm { + cor_Qd = WholeVectorAddWithCarry(cor_Qn, cor_Qm, carryInit1212); +} + +fesize2828: "f16" is TMode=1 & thv_c2828=1 { export 4:4; } +fesize2828: "f32" is TMode=1 & thv_c2828=0 { export 2:4; } + +# (DDI0553B) C2.4.303 T2 p. 1029 VADD (floating-point) +:vadd.^fesize2828 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c2021=3 & thv_c1616=0 & thv_c1212=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=0 & fesize2828 & cor_Qn & cor_Qd & thv_Rm +{ + cor_Qd = FloatVectorAdd(cor_Qn,thv_Rm,fesize2828); +} + +# (DDI0553B) C2.4.304 p. 1031 VADD (vector) T2 +:vadd.i^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=1 & thv_c1212=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=0 & esize2021 & thv_Rm & cor_Qn & cor_Qd +{ + cor_Qd = VectorAdd(cor_Qn,thv_Rm,esize2021); +} + + + +# (DDI0553B) C2.4.305 p. 1033 VADDLV +define pcodeop VectorAddLongAcrossVector; +:vaddvl^accum0505^"."^udt^"32" thv_RdaLo,thv_RdaHi,cor_Qm is $(TMODE_EorF) & thv_c2327=0x1d & thv_c1619=9 & thv_c1212=0 & thv_c0811=0xf & thv_c0607=0 & thv_c0404=0 & thv_c0000=0 & accum0505 & udt & thv_RdaLo & thv_RdaHi & cor_Qm { + local result:8 = VectorAddLongAcrossVector(cor_Qm, thv_RdaLo, thv_RdaHi, accum0505, udt); + thv_RdaLo = result(0); + thv_RdaHi = result(4); +} + +# (DDI0553B) C2.4.306 p. 1035 VADDV +define pcodeop VectorAddAcrossVector; +:vaddvl^accum0505^"."^udt^esize1819 thv_RdaLo,cor_Qm is $(TMODE_EorF) & thv_c2327=0x1d & thv_c2022=7 & thv_c1617=1 & thv_c1212=0 & thv_c0811=0xf & thv_c0607=0 & thv_c0404=0 & thv_c0000=0 & accum0505 & udt & esize1819 & thv_RdaLo & cor_Qm { + local result:4 = VectorAddAcrossVector(cor_Qm, thv_RdaLo, accum0505, udt, esize1819); + thv_RdaLo = result(0); +} + +# (DDI0553B) C2.4.311 p. 1044 VBRSR +define pcodeop VectorBitReverseAndShiftRight; +:vbsr.^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_F) & thv_c2327=0x1c & thv_c1616=1 & thv_c1212=1 & thv_c0811=0xe & thv_Q6=1 & thv_c0405=2 & esize2021 & thv_Rm & cor_Qn & cor_Qd +{ + cor_Qd = VectorBitReverseAndShiftRight(cor_Qn,thv_Rm,esize2021); +} + +crot1212: "#"^90 is thv_c1212=0 { local tmp:4 = 90; export tmp; } +crot1212: "#"^270 is TMode=1 & thv_c1212=1 { local tmp:4 = 270; export tmp; } + +# (DDI0553B) C2.4.312 p. 1046 VCADD +define pcodeop VectorComplexAdd; +:vcadd.i^esize2021 cor_Qd,cor_Qn,cor_Qm,crot1212 is $(TMODE_F) & thv_c2327=0x1c & thv_c1616=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & thv_c0000=0 & crot1212 & esize2021 & cor_Qm & cor_Qn & cor_Qd +{ + cor_Qd = VectorComplexAdd(cor_Qn,cor_Qm,crot1212,esize2021); +} +# (DDI0553B) C2.4.318 p. 1060 VCMP (floating-point) +define pcodeop FloatVectorCompareByLane; # FloatVectorCompareByLane(param1, param2, conditional) +:vcmp.^fesize2828 VP_fc000712,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2427=0xe & thv_c2023=3 & thv_c1616=1 & thv_c1315=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & fesize2828 & VP_fc000712 & cor_Qn & cor_Qm { + $(VPR_P0) = FloatVectorCompareByLane(cor_Qn, cor_Qm, VP_fc000712); +} + +:vcmp.^fesize2828 VP_fc050712,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2427=0xe & thv_c2023=3 & thv_c1616=1 & thv_c1315=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0404=0 & fesize2828 & VP_fc050712 & cor_Qn & thv_Rm { + $(VPR_P0) = FloatVectorCompareByLane(cor_Qn, thv_Rm, VP_fc050712); +} + + +# (DDI0553B) C2.4.319 p. 1062 VCMP (vector) +define pcodeop VectorCompareByLane; # VectorCompareByLane(param1, param2, mask, withScalar, elementType, size, conditional) +# T1 +:vcmp.i^esize2021 VP_fc000712,cor_Qn,cor_Qm is $(TMODE_F) & thv_c2427=0xe & thv_c2223=0 & thv_c1616=1 & thv_c1215=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & thv_c0000=0 & esize2021 & VP_fc000712 & cor_Qn & cor_Qm { + $(VPR_P0) = VectorCompareByLane(cor_Qn, cor_Qm, 0:1, 0:1, VP_fc000712); +} + +# T2 +:vcmp.uesize2021 VP_fc000712,cor_Qn,cor_Qm is $(TMODE_F) & thv_c2427=0xe & thv_c2223=0 & thv_c1616=1 & thv_c1215=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & thv_c0000=1 & esize2021 & VP_fc000712 & cor_Qn & cor_Qm { + $(VPR_P0) = VectorCompareByLane(cor_Qn, cor_Qm, 0:1, 1:1, VP_fc000712); +} + +# T3 +:vcmp.s^esize2021 VP_fc000712,cor_Qn,cor_Qm is $(TMODE_F) & thv_c2427=0xe & thv_c2223=0 & thv_c1616=1 & thv_c1215=1 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & esize2021 & VP_fc000712 & cor_Qn & cor_Qm { + $(VPR_P0) = VectorCompareByLane(cor_Qn, cor_Qm, 0:1, 2:1, VP_fc000712); +} + +# T4 +:vcmp.i^esize2021 VP_fc050712,cor_Qn,thv_Rm is $(TMODE_F) & thv_c2427=0xe & thv_c2023=0 & thv_c1616=1 & thv_c1215=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=0 & esize2021 & VP_fc050712 & cor_Qn & thv_Rm { + $(VPR_P0) = VectorCompareByLane(cor_Qn, thv_Rm, 1:1, 0:1, VP_fc050712); +} + +# T5 +:vcmp.u^esize2021 VP_fc050712,cor_Qn,thv_Rm is $(TMODE_F) & thv_c2427=0xe & thv_c2023=0 & thv_c1616=1 & thv_c1215=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=1 & esize2021 & VP_fc050712 & cor_Qn & thv_Rm { + $(VPR_P0) = VectorCompareByLane(cor_Qn, thv_Rm, 1:1, 1:1, VP_fc050712); +} + +# T6 +:vcmp.s^esize2021 VP_fc050712,cor_Qn,thv_Rm is $(TMODE_F) & thv_c2427=0xe & thv_c2023=0 & thv_c1616=1 & thv_c1215=1 & thv_c0811=0xf & thv_Q6=1 & thv_c0404=0 & esize2021 & VP_fc050712 & cor_Qn & thv_Rm { + $(VPR_P0) = VectorCompareByLane(cor_Qn, thv_Rm, 1:1, 2:1, VP_fc050712); +} + + + + +# (DDI0553B) C2.4.321 p. 1070 VCMUL (floating-point) +define pcodeop FloatVectorComplexMultiply; +:vcmul.^fesize2828 cor_Qd,cor_Qn,cor_Qm,crot0012 is $(TMODE_EorF) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0 & fesize2828 & crot0012 & cor_Qd & cor_Qn & cor_Qm { + cor_Qd = FloatVectorComplexMultiply(cor_Qn, cor_Qm, crot0012, fesize2828); +} +# (DDI0553B) C2.4.322 p. 1073 VCTP +define pcodeop CreateTailPredicate; +:vctp.^esize2021 thv_Rn is $(TMODE_F) & thv_c2427=0 & thv_c2223=0 & thv_c1215=0xe & thv_c0811=8 & thv_c0407=0 & thv_c0003=1 & esize2021 & thv_Rn { + $(VPR_P0) = CreateTailPredicate(thv_Rn,esize2021); +} + +bort1212: "b" is TMode=1 & thv_c1212=1 { local tmp:1 = 0; export *[const]:1 tmp; } +bort1212: "t" is TMode=1 & thv_c1212=0 { local tmp:1 = 1; export *[const]:1 tmp; } + +# (DDI0553B) C2.4.327 p. 1082 VCVT (between single and half-precision floating-point) +define pcodeop FloatVectorConvertSingleToHalf; +define pcodeop FloatVectorConvertHalfToSingle; +:vcvt^bort1212^".f16.f32" cor_Qd,cor_Qm is $(TMODE_E) & thv_c2327=0x1c & thv_c2021=0x3 & thv_c1619=0xf & thv_c0811=0xe & thv_c0607=0 & thv_c0404=0 & thv_c0000=1 & bort1212 & cor_Qd & cor_Qm { + cor_Qd = FloatVectorConvertSingleToHalf(cor_Qd, cor_Qm, bort1212); +} + +:vcvt^bort1212^".f32.f16" cor_Qd,cor_Qm is $(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x3 & thv_c1619=0xf & thv_c0811=0xe & thv_c0607=0 & thv_c0404=0 & thv_c0000=1 & bort1212 & cor_Qd & cor_Qm { + cor_Qd = FloatVectorConvertHalfToSingle(cor_Qm, bort1212); +} + +@endif # VERSION_8M ####### # The VCVT instructions are a large family for converting between # floating point numbers and integers, of all sizes and combinations -# F6.1.58 p7998 A1 cases size = 10 (c0809) -:vcvt^COND^".f64.f32" Dd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b10) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) - & COND & Dd & Sm - { build COND; Dd = float2float(Sm); } - -# F6.1.58 p7998 A1 cases size = 11 (c0809) -:vcvt^COND^".f32.f64" Sd,Dm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b11) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) - & COND & Sd & Dm - { build COND; Sd = float2float(Dm); } - -# F6.1.59 p8000 A1 op == 1 (c0808) -:vcvt.f32.f16 Qd,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=1) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=1)) - & Qd & Dm - { - Qd = float2float(Dm:2); - } - -# F6.1.59 p8000 A1 op == 0 (c0808) -:vcvt.f16.f32 Dd,Qm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=0)) - & Dd & Qm - { Dd = float2float(Qm); } - -vcvt_56_64_dt: ".f32.s32" - is ((TMode=0 & c0708=0b00) - | (TMode=1 & thv_c0708=0b00)) - & Dd & Dm - { Dd = FixedToFP(Dm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_56_64_dt: ".f32.u32" - is ((TMode=0 & c0708=0b01) - | (TMode=1 & thv_c0708=0b01)) - & Dd & Dm - { Dd = FixedToFP(Dm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_56_64_dt: ".s32.f32" - is ((TMode=0 & c0708=0b10) - | (TMode=1 & thv_c0708=0b10)) - & Dd & Dm - { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_ZERO)); } -vcvt_56_64_dt: ".u32.f32" - is ((TMode=0 & c0708=0b11) - | (TMode=1 & thv_c0708=0b11)) - & Dd & Dm - { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); } - -vcvt_56_128_dt: ".f32.s32" - is ((TMode=0 & c0708=0b00) - | (TMode=1 & thv_c0708=0b00)) - & Qd & Qm - { Qd = FixedToFP(Qm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_56_128_dt: ".f32.u32" - is ((TMode=0 & c0708=0b01) - | (TMode=1 & thv_c0708=0b01)) - & Qd & Qm - { Qd = FixedToFP(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_56_128_dt: ".s32.f32" - is ((TMode=0 & c0708=0b10) - | (TMode=1 & thv_c0708=0b10)) - & Qd & Qm - { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_ZERO)); } -vcvt_56_128_dt: ".u32.f32" - is ((TMode=0 & c0708=0b11) - | (TMode=1 & thv_c0708=0b11)) - & Qd & Qm - { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); } + +vcvt_56_64_dt: ".f32.s32" is ((TMode=0 & c0708=0b00) | (TMode=1 & thv_c0708=0b00)) & Dd & Dm { Dd = FixedToFP(Dm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_56_64_dt: ".f32.u32" is ((TMode=0 & c0708=0b01) | (TMode=1 & thv_c0708=0b01)) & Dd & Dm { Dd = FixedToFP(Dm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_56_64_dt: ".s32.f32" is ((TMode=0 & c0708=0b10) | (TMode=1 & thv_c0708=0b10)) & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_ZERO)); } +vcvt_56_64_dt: ".u32.f32" is ((TMode=0 & c0708=0b11) | (TMode=1 & thv_c0708=0b11)) & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); } + +vcvt_56_128_dt: ".f32.s32" is ((TMode=0 & c0708=0b00) | (TMode=1 & thv_c0708=0b00)) & Qd & Qm { Qd = FixedToFP(Qm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_56_128_dt: ".f32.u32" is ((TMode=0 & c0708=0b01) | (TMode=1 & thv_c0708=0b01)) & Qd & Qm { Qd = FixedToFP(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_56_128_dt: ".s32.f32" is ((TMode=0 & c0708=0b10) | (TMode=1 & thv_c0708=0b10)) & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_ZERO)); } +vcvt_56_128_dt: ".u32.f32" is ((TMode=0 & c0708=0b11) | (TMode=1 & thv_c0708=0b11)) & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); } # F6.1.60 p8002 A1 Q == 0 (c0606) -:vcvt^vcvt_56_64_dt Dd,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0) +:vcvt^vcvt_56_64_dt Dd,Dm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=0)) & vcvt_56_64_dt & Dd & Dm { } # F6.1.60 p8002 A1 Q == 1 (c0606) -:vcvt^vcvt_56_128_dt Qd,Qm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1) +:vcvt^vcvt_56_128_dt Qd,Qm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=1)) & vcvt_56_128_dt & Qd & Qm { } # F6.1.61 p8005 A1 opc2==100 && size==10 (c1618, c0809) -:vcvt^COND^".u32.f32" Sd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b10) +:vcvt^COND^".u32.f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10)) & COND & Sd & Sm { build COND; Sd = zext(Sm f> 0) * (trunc(Sm)); } # F6.1.61 p8005 A1 opc2==101 && size==10 (c1618, c0809) -:vcvt^COND^".s32.f32" Sd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b10) +:vcvt^COND^".s32.f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10)) & COND & Sd & Sm { build COND; Sd = trunc(Sm); } # F6.1.61 p8005 A1 opc2==100 && size==11 (c1618, c0809) -:vcvt^COND^".u32.f64" Sd,Dm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b11) +:vcvt^COND^".u32.f64" Sd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11)) & COND & Sd & Dm { build COND; local tmp:8 = zext(Dm f> 0) * (trunc(Dm)); Sd = tmp:4; } # F6.1.61 p8005 A1 opc2==101 && size==11 (c1618, c0809) -:vcvt^COND^".s32.f64" Sd,Dm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b11) +:vcvt^COND^".s32.f64" Sd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11)) & COND & Sd & Dm { build COND; local tmp:8 = trunc(Dm); Sd = tmp:4; } # The rounding mode depends on c0707=0 => FPSCR else ZERO - -vcvt_58_3232_dt: ".f32.u32" - is ((TMode=0 & c0708=0b00) +vcvt_58_3232_dt: ".f32.u32" is ((TMode=0 & c0708=0b00) | (TMode=1 & thv_c0708=0b00)) - & Sd & Sm - { local tmp:8 = zext(Sm); Sd = int2float(tmp); } -vcvt_58_3232_dt: ".f32.s32" - is ((TMode=0 & c0708=0b01) + & Sd & Sm { local tmp:8 = zext(Sm); Sd = int2float(tmp); } +vcvt_58_3232_dt: ".f32.s32" is ((TMode=0 & c0708=0b01) | (TMode=1 & thv_c0708=0b01)) - & Sd & Sm - { local tmp:8 = sext(Sm); Sd = int2float(tmp); } + & Sd & Sm { local tmp:8 = sext(Sm); Sd = int2float(tmp); } -vcvt_58_6432_dt: ".f64.u32" - is ((TMode=0 & c0708=0b10) +vcvt_58_6432_dt: ".f64.u32" is ((TMode=0 & c0708=0b10) | (TMode=1 & thv_c0708=0b10)) - & Dd & Sm - { local tmp:8 = zext(Sm); Dd = int2float(tmp); } -vcvt_58_6432_dt: ".f64.s32" - is ((TMode=0 & c0708=0b11) + & Dd & Sm { local tmp:8 = zext(Sm); Dd = int2float(tmp); } +vcvt_58_6432_dt: ".f64.s32" is ((TMode=0 & c0708=0b11) | (TMode=1 & thv_c0708=0b11)) - & Dd & Sm - { local tmp:8 = sext(Sm); Dd = int2float(tmp); } + & Dd & Sm { local tmp:8 = sext(Sm); Dd = int2float(tmp); } # F6.1.62 p8009 A1 size == 10 (c0809) -:vcvt^COND^vcvt_58_3232_dt Sd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) +:vcvt^COND^vcvt_58_3232_dt Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) & COND & vcvt_58_3232_dt & Sd & Sm { build COND; build vcvt_58_3232_dt; } # F6.1.62 p8009 A1 size == 11 (c0809) -:vcvt^COND^vcvt_58_6432_dt Dd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) +:vcvt^COND^vcvt_58_6432_dt Dd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) & COND & vcvt_58_6432_dt & Dd & Sm { build COND; build vcvt_58_6432_dt; } -vcvt_59_fbits_built: fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] { export * [const]:1 fbits; } -vcvt_59_fbits_built: fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { export * [const]:1 fbits; } -vcvt_59_fbits: "#"^fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] { } -vcvt_59_fbits: "#"^fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { } +vcvt_59_fbits_built: fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] { export * [const]:1 fbits; } +vcvt_59_fbits_built: fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { export * [const]:1 fbits; } + +vcvt_59_fbits: "#"^fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] { } +vcvt_59_fbits: "#"^fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { } -vcvt_59_32_dt: ".f32.s32" - is ((TMode=0 & c0809=2 & c2424=0) +vcvt_59_32_dt: ".f32.s32" is ((TMode=0 & c0809=2 & c2424=0) | (TMode=1 & thv_c0809=2 & thv_c2828=0)) - & Dd & Dm & vcvt_59_fbits_built - { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_59_32_dt: ".f32.u32" - is ((TMode=0 & c0809=2 & c2424=1) + & Dd & Dm & vcvt_59_fbits_built { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_59_32_dt: ".f32.u32" is ((TMode=0 & c0809=2 & c2424=1) | (TMode=1 & thv_c0809=2 & thv_c2828=1)) - & Dd & Dm & vcvt_59_fbits_built - { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_59_32_dt: ".s32.f32" - is ((TMode=0 & c0809=3 & c2424=0) + & Dd & Dm & vcvt_59_fbits_built { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_59_32_dt: ".s32.f32" is ((TMode=0 & c0809=3 & c2424=0) | (TMode=1 & thv_c0809=3 & thv_c2828=0)) - & Dd & Dm & vcvt_59_fbits_built - { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } -vcvt_59_32_dt: ".u32.f32" - is ((TMode=0 & c0809=3 & c2424=1) + & Dd & Dm & vcvt_59_fbits_built { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_59_32_dt: ".u32.f32" is ((TMode=0 & c0809=3 & c2424=1) | (TMode=1 & thv_c0809=3 & thv_c2828=1)) - & Dd & Dm & vcvt_59_fbits_built - { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } -vcvt_59_32_dt: ".f16.s16" - is ((TMode=0 & c0809=0 & c2424=0) + & Dd & Dm & vcvt_59_fbits_built { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } +vcvt_59_32_dt: ".f16.s16" is ((TMode=0 & c0809=0 & c2424=0) | (TMode=1 & thv_c0809=0 & thv_c2828=0)) - & Dd & Dm & vcvt_59_fbits_built - { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_59_32_dt: ".f16.u16" - is ((TMode=0 & c0809=0 & c2424=1) + & Dd & Dm & vcvt_59_fbits_built { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_59_32_dt: ".f16.u16" is ((TMode=0 & c0809=0 & c2424=1) | (TMode=1 & thv_c0809=0 & thv_c2828=1)) - & Dd & Dm & vcvt_59_fbits_built - { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_59_32_dt: ".s16.f16" - is ((TMode=0 & c0809=1 & c2424=0) + & Dd & Dm & vcvt_59_fbits_built { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_59_32_dt: ".s16.f16" is ((TMode=0 & c0809=1 & c2424=0) | (TMode=1 & thv_c0809=1 & thv_c2828=0)) - & Dd & Dm & vcvt_59_fbits_built - { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } -vcvt_59_32_dt: ".u16.f16" - is ((TMode=0 & c0809=1 & c2424=1) + & Dd & Dm & vcvt_59_fbits_built { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_59_32_dt: ".u16.f16" is ((TMode=0 & c0809=1 & c2424=1) | (TMode=1 & thv_c0809=1 & thv_c2828=1)) - & Dd & Dm & vcvt_59_fbits_built - { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } - -vcvt_59_64_dt: ".f32.s32" - is ((TMode=0 & c0809=2 & c2424=0) + & Dd & Dm & vcvt_59_fbits_built { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } + +vcvt_59_64_dt: ".f32.s32" is ((TMode=0 & c0809=2 & c2424=0) | (TMode=1 & thv_c0809=2 & thv_c2828=0)) - & Qd & Qm & vcvt_59_fbits_built - { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_59_64_dt: ".f32.u32" - is ((TMode=0 & c0809=2 & c2424=1) + & Qd & Qm & vcvt_59_fbits_built { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_59_64_dt: ".f32.u32" is ((TMode=0 & c0809=2 & c2424=1) | (TMode=1 & thv_c0809=2 & thv_c2828=1)) - & Qd & Qm & vcvt_59_fbits_built - { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_59_64_dt: ".s32.f32" - is ((TMode=0 & c0809=3 & c2424=0) + & Qd & Qm & vcvt_59_fbits_built { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_59_64_dt: ".s32.f32" is ((TMode=0 & c0809=3 & c2424=0) | (TMode=1 & thv_c0809=3 & thv_c2828=0)) - & Qd & Qm & vcvt_59_fbits_built - { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } -vcvt_59_64_dt: ".u32.f32" - is ((TMode=0 & c0809=3 & c2424=1) + & Qd & Qm & vcvt_59_fbits_built { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_59_64_dt: ".u32.f32" is ((TMode=0 & c0809=3 & c2424=1) | (TMode=1 & thv_c0809=3 & thv_c2828=1)) - & Qd & Qm & vcvt_59_fbits_built - { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } -vcvt_59_64_dt: ".f16.s16" - is ((TMode=0 & c0809=0 & c2424=0) + & Qd & Qm & vcvt_59_fbits_built { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } +vcvt_59_64_dt: ".f16.s16" is ((TMode=0 & c0809=0 & c2424=0) | (TMode=1 & thv_c0809=0 & thv_c2828=0)) - & Qd & Qm & vcvt_59_fbits_built - { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_59_64_dt: ".f16.u16" - is ((TMode=0 & c0809=0 & c2424=1) + & Qd & Qm & vcvt_59_fbits_built { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_59_64_dt: ".f16.u16" is ((TMode=0 & c0809=0 & c2424=1) | (TMode=1 & thv_c0809=0 & thv_c2828=1)) - & Qd & Qm & vcvt_59_fbits_built - { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_59_64_dt: ".s16.f16" - is ((TMode=0 & c0809=1 & c2424=0) + & Qd & Qm & vcvt_59_fbits_built { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_59_64_dt: ".s16.f16" is ((TMode=0 & c0809=1 & c2424=0) | (TMode=1 & thv_c0809=1 & thv_c2828=0)) - & Qd & Qm & vcvt_59_fbits_built - { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } -vcvt_59_64_dt: ".u16.f16" - is ((TMode=0 & c0809=1 & c2424=1) + & Qd & Qm & vcvt_59_fbits_built { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_59_64_dt: ".u16.f16" is ((TMode=0 & c0809=1 & c2424=1) | (TMode=1 & thv_c0809=1 & thv_c2828=1)) - & Qd & Qm & vcvt_59_fbits_built - { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } + & Qd & Qm & vcvt_59_fbits_built { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } # Should add rounding here, if dt2 is s32 or u32 then rounding is # FPRounding_ZERO otherwise FPROunding_TIEEVEN - # F6.1.63 p8012 A1 Q = 0 (c0606) -:vcvt^vcvt_59_32_dt Dd,Dm,vcvt_59_fbits - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=0) +:vcvt^vcvt_59_32_dt Dd,Dm,vcvt_59_fbits is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=0) | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=0)) & vcvt_59_32_dt & vcvt_59_fbits & Dd & Dm { } # F6.1.63 p8012 A1 Q = 1 (c0606) -:vcvt^vcvt_59_64_dt Qd,Qm,vcvt_59_fbits - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=1) +:vcvt^vcvt_59_64_dt Qd,Qm,vcvt_59_fbits is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=1) | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=1)) & vcvt_59_64_dt & vcvt_59_fbits & Qd & Qm { } -vcvt_60_fbits_built: fbits is TMode=0 & c0707=0 & c0505 & c0003 [fbits = 16 - ( c0003 * 2 + c0505); ] { export * [const]:1 fbits; } -vcvt_60_fbits_built: fbits is TMode=1 & thv_c0707=0 & thv_c0505 & thv_c0003 [fbits = 16 - (thv_c0003 * 2 + thv_c0505); ] { export * [const]:1 fbits; } -vcvt_60_fbits_built: fbits is TMode=0 & c0707=1 & c0505 & c0003 [fbits = 32 - ( c0003 * 2 + c0505); ] { export * [const]:1 fbits; } -vcvt_60_fbits_built: fbits is TMode=1 & thv_c0707=1 & thv_c0505 & thv_c0003 [fbits = 32 - (thv_c0003 * 2 + thv_c0505); ] { export * [const]:1 fbits; } -vcvt_60_fbits: "#"^fbits is TMode=0 & c0707=0 & c0505 & c0003 [fbits = 16 - ( c0003 * 2 + c0505); ] { } -vcvt_60_fbits: "#"^fbits is TMode=1 & thv_c0707=0 & thv_c0505 & thv_c0003 [fbits = 16 - (thv_c0003 * 2 + thv_c0505); ] { } -vcvt_60_fbits: "#"^fbits is TMode=0 & c0707=1 & c0505 & c0003 [fbits = 32 - ( c0003 * 2 + c0505); ] { } -vcvt_60_fbits: "#"^fbits is TMode=1 & thv_c0707=1 & thv_c0505 & thv_c0003 [fbits = 32 - (thv_c0003 * 2 + thv_c0505); ] { } - -vcvt_60_32_dt: ".f32.s16" - is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b10 & c0707=0) +vcvt_60_fbits_built: fbits is TMode=0 & c0707=0 & c0505 & c0003 [fbits = 16 - ( c0003 * 2 + c0505); ] { export * [const]:1 fbits; } +vcvt_60_fbits_built: fbits is TMode=1 & thv_c0707=0 & thv_c0505 & thv_c0003 [fbits = 16 - (thv_c0003 * 2 + thv_c0505); ] { export * [const]:1 fbits; } +vcvt_60_fbits_built: fbits is TMode=0 & c0707=1 & c0505 & c0003 [fbits = 32 - ( c0003 * 2 + c0505); ] { export * [const]:1 fbits; } +vcvt_60_fbits_built: fbits is TMode=1 & thv_c0707=1 & thv_c0505 & thv_c0003 [fbits = 32 - (thv_c0003 * 2 + thv_c0505); ] { export * [const]:1 fbits; } + +vcvt_60_fbits: "#"^fbits is TMode=0 & c0707=0 & c0505 & c0003 [fbits = 16 - ( c0003 * 2 + c0505); ] { } +vcvt_60_fbits: "#"^fbits is TMode=1 & thv_c0707=0 & thv_c0505 & thv_c0003 [fbits = 16 - (thv_c0003 * 2 + thv_c0505); ] { } +vcvt_60_fbits: "#"^fbits is TMode=0 & c0707=1 & c0505 & c0003 [fbits = 32 - ( c0003 * 2 + c0505); ] { } +vcvt_60_fbits: "#"^fbits is TMode=1 & thv_c0707=1 & thv_c0505 & thv_c0003 [fbits = 32 - (thv_c0003 * 2 + thv_c0505); ] { } + +vcvt_60_32_dt: ".f32.s16" is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b10 & c0707=0) | (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=0)) - & Sd & Sd2 & vcvt_60_fbits_built - { Sd = FixedToFP(Sd2, 16:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_60_32_dt: ".f32.s32" - is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b10 & c0707=1) + & Sd & Sd2 & vcvt_60_fbits_built { Sd = FixedToFP(Sd2, 16:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_60_32_dt: ".f32.s32" is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b10 & c0707=1) | (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=1)) - & Sd & Sd2 & vcvt_60_fbits_built - { Sd = FixedToFP(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_60_32_dt: ".f32.u16" - is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b10 & c0707=0) + & Sd & Sd2 & vcvt_60_fbits_built { Sd = FixedToFP(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_60_32_dt: ".f32.u16" is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b10 & c0707=0) | (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=0)) - & Sd & Sd2 & vcvt_60_fbits_built - { Sd = FixedToFP(Sd2, 16:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_60_32_dt: ".f32.u32" - is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b10 & c0707=1) + & Sd & Sd2 & vcvt_60_fbits_built { Sd = FixedToFP(Sd2, 16:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_60_32_dt: ".f32.u32" is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b10 & c0707=1) | (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=1)) - & Sd & Sd2 & vcvt_60_fbits_built - { Sd = FixedToFP(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_60_32_dt: ".s16.f32" - is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b10 & c0707=0) + & Sd & Sd2 & vcvt_60_fbits_built { Sd = FixedToFP(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_60_32_dt: ".s16.f32" is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b10 & c0707=0) | (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=0)) - & Sd & Sd2 & vcvt_60_fbits_built - { Sd = FPToFixed(Sd2, 32:1, 16:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } -vcvt_60_32_dt: ".s32.f32" - is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b10 & c0707=1) + & Sd & Sd2 & vcvt_60_fbits_built { Sd = FPToFixed(Sd2, 32:1, 16:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_60_32_dt: ".s32.f32" is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b10 & c0707=1) | (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=1)) - & Sd & Sd2 & vcvt_60_fbits_built - { Sd = FPToFixed(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } -vcvt_60_32_dt: ".u16.f32" - is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b10 & c0707=0) + & Sd & Sd2 & vcvt_60_fbits_built { Sd = FPToFixed(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_60_32_dt: ".u16.f32" is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b10 & c0707=0) | (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=0)) - & Sd & Sd2 & vcvt_60_fbits_built - { Sd = FPToFixed(Sd2, 32:1, 16:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } -vcvt_60_32_dt: ".u32.f32" - is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b10 & c0707=1) + & Sd & Sd2 & vcvt_60_fbits_built { Sd = FPToFixed(Sd2, 32:1, 16:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } +vcvt_60_32_dt: ".u32.f32" is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b10 & c0707=1) | (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=1)) - & Sd & Sd2 & vcvt_60_fbits_built - { Sd = FPToFixed(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } + & Sd & Sd2 & vcvt_60_fbits_built { Sd = FPToFixed(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } -vcvt_60_64_dt: ".f64.s16" - is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b11 & c0707=0) +vcvt_60_64_dt: ".f64.s16" is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b11 & c0707=0) | (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=0)) - & Dd & Dd2 & vcvt_60_fbits_built - { Dd = FixedToFP(Dd2, 16:1, 64:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_60_64_dt: ".f64.s32" - is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b11 & c0707=1) + & Dd & Dd2 & vcvt_60_fbits_built { Dd = FixedToFP(Dd2, 16:1, 64:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_60_64_dt: ".f64.s32" is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b11 & c0707=1) | (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=1)) - & Dd & Dd2 & vcvt_60_fbits_built - { Dd = FixedToFP(Dd2, 32:1, 64:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } -vcvt_60_64_dt: ".f64.u16" - is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b11 & c0707=0) + & Dd & Dd2 & vcvt_60_fbits_built { Dd = FixedToFP(Dd2, 32:1, 64:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_60_64_dt: ".f64.u16" is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b11 & c0707=0) | (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=0)) - & Dd & Dd2 & vcvt_60_fbits_built - { Dd = FixedToFP(Dd2, 16:1, 64:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_60_64_dt: ".f64.u32" - is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b11 & c0707=1) + & Dd & Dd2 & vcvt_60_fbits_built { Dd = FixedToFP(Dd2, 16:1, 64:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_60_64_dt: ".f64.u32" is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b11 & c0707=1) | (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=1)) - & Dd & Dd2 & vcvt_60_fbits_built - { Dd = FixedToFP(Dd2, 32:1, 64:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } -vcvt_60_64_dt: ".s16.f64" - is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b11 & c0707=0) + & Dd & Dd2 & vcvt_60_fbits_built { Dd = FixedToFP(Dd2, 32:1, 64:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_60_64_dt: ".s16.f64" is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b11 & c0707=0) | (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=0)) - & Dd & Dd2 & vcvt_60_fbits_built - { Dd = FPToFixed(Dd2, 64:1, 16:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } -vcvt_60_64_dt: ".s32.f64" - is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b11 & c0707=1) + & Dd & Dd2 & vcvt_60_fbits_built { Dd = FPToFixed(Dd2, 64:1, 16:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_60_64_dt: ".s32.f64" is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b11 & c0707=1) | (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=1)) - & Dd & Dd2 & vcvt_60_fbits_built - { Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } -vcvt_60_64_dt: ".u16.f64" - is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b11 & c0707=0) + & Dd & Dd2 & vcvt_60_fbits_built { Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_60_64_dt: ".u16.f64" is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b11 & c0707=0) | (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=0)) - & Dd & Dd2 & vcvt_60_fbits_built - { Dd = FPToFixed(Dd2, 64:1, 16:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } -vcvt_60_64_dt: ".u32.f64" - is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b11 & c0707=1) + & Dd & Dd2 & vcvt_60_fbits_built { Dd = FPToFixed(Dd2, 64:1, 16:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } +vcvt_60_64_dt: ".u32.f64" is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b11 & c0707=1) | (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=1)) - & Dd & Dd2 & vcvt_60_fbits_built - { Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } + & Dd & Dd2 & vcvt_60_fbits_built { Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } # F6.1.63 p8012 A1 op=0/1 sf=10 (c1818, c0809) -:vcvt^COND^vcvt_60_32_dt Sd,Sd2,vcvt_60_fbits - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b10) +:vcvt^COND^vcvt_60_32_dt Sd,Sd2,vcvt_60_fbits is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b10)) & COND & vcvt_60_fbits & vcvt_60_32_dt & Sd & Sd2 { build COND; build vcvt_60_32_dt; } # F6.1.63 p8012 A1 op=0/1 sf=11 (c1818, c0809) -:vcvt^COND^vcvt_60_64_dt Dd,Dd2,vcvt_60_fbits - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b11) +:vcvt^COND^vcvt_60_64_dt Dd,Dd2,vcvt_60_fbits is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b11)) & COND & vcvt_60_fbits & vcvt_60_64_dt & Dd & Dd2 { build COND; build vcvt_60_64_dt; } -# vcvta, vcvtm, vcvtn, and vcvtp - -vcvt_amnp_simd_RM: "a" - is ((TMode=0 & c0809=0b00) - | (TMode=1 & thv_c0809=0b00)) - { export $(FPRounding_TIEAWAY); } -vcvt_amnp_simd_RM: "n" - is ((TMode=0 & c0809=0b01) - | (TMode=1 & thv_c0809=0b01)) - { export $(FPRounding_TIEEVEN); } -vcvt_amnp_simd_RM: "p" - is ((TMode=0 & c0809=0b10) - | (TMode=1 & thv_c0809=0b10)) - { export $(FPRounding_POSINF); } -vcvt_amnp_simd_RM: "m" - is ((TMode=0 & c0809=0b11) - | (TMode=1 & thv_c0809=0b11)) - { export $(FPRounding_NEGINF); } - -# These RM values need to be converted properly -vcvt_amnp_simd_64_dt: ".s32" is TMode=0 & c0707=0 & c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); } -vcvt_amnp_simd_64_dt: ".s32" is TMode=1 & thv_c0707=0 & thv_c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); } -vcvt_amnp_simd_64_dt: ".u32" is TMode=0 & c0707=1 & c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } -vcvt_amnp_simd_64_dt: ".u32" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } - -vcvt_amnp_simd_128_dt: ".s32" is TMode=0 & c0707=0 & c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); } -vcvt_amnp_simd_128_dt: ".s32" is TMode=1 & thv_c0707=0 & thv_c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); } -vcvt_amnp_simd_128_dt: ".u32" is TMode=0 & c0707=1 & c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } -vcvt_amnp_simd_128_dt: ".u32" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } - -# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 64-bit SIMD vector variant Q = 0 (c0606) -:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_64_dt^".f32" Dd,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=0)) - & vcvt_amnp_simd_RM & vcvt_amnp_simd_64_dt & Dd & Dm - { } - -# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 128-bit SIMD vector variant Q = 1(c0606) -:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_128_dt^".f32" Qd,Qm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=1) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=1)) - & vcvt_amnp_simd_RM & vcvt_amnp_simd_128_dt & Qd & Qm - { } - -vcvt_amnp_fp_RM: "a" - is ((TMode=0 & c1617=0b00) - | (TMode=1 & thv_c1617=0b00)) - { export $(FPRounding_TIEAWAY); } -vcvt_amnp_fp_RM: "n" - is ((TMode=0 & c1617=0b01) - | (TMode=1 & thv_c1617=0b01)) - { export $(FPRounding_TIEEVEN); } -vcvt_amnp_fp_RM: "p" - is ((TMode=0 & c1617=0b10) - | (TMode=1 & thv_c1617=0b10)) - { export $(FPRounding_POSINF); } -vcvt_amnp_fp_RM: "m" - is ((TMode=0 & c1617=0b11) - | (TMode=1 & thv_c1617=0b11)) - { export $(FPRounding_NEGINF); } - -vcvt_amnp_fp_s_dt: ".u32" is TMode=0 & c0707=0 & c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); } -vcvt_amnp_fp_s_dt: ".u32" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); } -vcvt_amnp_fp_s_dt: ".s32" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } -vcvt_amnp_fp_s_dt: ".s32" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } - -vcvt_amnp_fp_d_dt: ".u32" is TMode=0 & c0707=0 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); } -vcvt_amnp_fp_d_dt: ".u32" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); } -vcvt_amnp_fp_d_dt: ".s32" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } -vcvt_amnp_fp_d_dt: ".s32" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } - -# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 01 (c0809) -:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f16" Sd,Sm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01)) - & vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm - unimpl - -# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 11 (c0809) -:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f32" Sd,Sm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) - & vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm - { } - -# F6.1.66,70,72,74 p8021,8030,8034,8038 Double-precision scalar variant size = 11 (c0809) -:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_d_dt^".f64" Sd,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) - & vcvt_amnp_fp_RM & vcvt_amnp_fp_d_dt & Sd & Dm - { } - # vcvtb and vcvtt - -vcvt_bt3216_op: "b" - is ((TMode=0 & c0707=0) +vcvt_bt3216_op: "b" is ((TMode=0 & c0707=0) | (TMode=1 & thv_c0707=0)) - & Sd & Sm - { Sd = float2float(Sm:2); } -vcvt_bt3216_op: "t" - is ((TMode=0 & c0707=1) + & Sd & Sm { Sd = float2float(Sm:2); } +vcvt_bt3216_op: "t" is ((TMode=0 & c0707=1) | (TMode=1 & thv_c0707=1)) - & Sd & Sm - { w:2 = Sm(2); Sd = float2float(w); } + & Sd & Sm { w:2 = Sm(2); Sd = float2float(w); } -vcvt_bt6416_op: "b" - is ((TMode=0 & c0707=0) +vcvt_bt6416_op: "b" is ((TMode=0 & c0707=0) | (TMode=1 & thv_c0707=0)) - & Dd & Sm - { Dd = float2float(Sm:2); } -vcvt_bt6416_op: "t" - is ((TMode=0 & c0707=1) + & Dd & Sm { Dd = float2float(Sm:2); } +vcvt_bt6416_op: "t" is ((TMode=0 & c0707=1) | (TMode=1 & thv_c0707=1)) - & Dd & Sm - { w:2 = Sm(2); Dd = float2float(w); } + & Dd & Sm { w:2 = Sm(2); Dd = float2float(w); } -vcvt_bt1632_op: "b" - is ((TMode=0 & c0707=0) +vcvt_bt1632_op: "b" is ((TMode=0 & c0707=0) | (TMode=1 & thv_c0707=0)) - & Sd & Sm - { Sd[0,16] = float2float(Sm); } -vcvt_bt1632_op: "t" - is ((TMode=0 & c0707=1) + & Sd & Sm { Sd[0,16] = float2float(Sm); } +vcvt_bt1632_op: "t" is ((TMode=0 & c0707=1) | (TMode=1 & thv_c0707=1)) - & Sd & Sm - { tmp:2 = float2float(Sm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); } + & Sd & Sm { tmp:2 = float2float(Sm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); } -vcvt_bt1664_op: "b" - is ((TMode=0 & c0707=0) +vcvt_bt1664_op: "b" is ((TMode=0 & c0707=0) | (TMode=1 & thv_c0707=0)) - & Sd & Dm - { Sd[0,16] = float2float(Dm); } -vcvt_bt1664_op: "t" - is ((TMode=0 & c0707=1) + & Sd & Dm { Sd[0,16] = float2float(Dm); } +vcvt_bt1664_op: "t" is ((TMode=0 & c0707=1) | (TMode=1 & thv_c0707=1)) - & Sd & Dm - { tmp:2 = float2float(Dm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); } + & Sd & Dm { tmp:2 = float2float(Dm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); } # F6.1.67 p8023 A1 cases op:sz = 00 (c1616, c0808) # F6.1.76 p8044 A1 cases op:sz = 00 (c1616, c0808) -:vcvt^vcvt_bt3216_op^COND^".f32.f16" Sd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=0) +:vcvt^vcvt_bt3216_op^COND^".f32.f16" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=0) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=0)) & COND & vcvt_bt3216_op & Sd & Sm { build COND; build vcvt_bt3216_op; } # F6.1.67 p8023 A1 cases op:sz = 01 (c1616, c0808) # F6.1.76 p8044 A1 cases op:sz = 01 (c1616, c0808) -:vcvt^vcvt_bt6416_op^COND^".f64.f16" Dd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=1) +:vcvt^vcvt_bt6416_op^COND^".f64.f16" Dd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=1) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=1)) & COND & vcvt_bt6416_op & Dd & Sm { build COND; build vcvt_bt6416_op; } # F6.1.67 p8023 A1 cases op:sz = 10 (c1616, c0808) # F6.1.76 p8044 A1 cases op:sz = 10 (c1616, c0808) -:vcvt^vcvt_bt1632_op^COND^".f16.f32" Sd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=0) +:vcvt^vcvt_bt1632_op^COND^".f16.f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=0) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=0)) & COND & vcvt_bt1632_op & Sd & Sm { build COND; build vcvt_bt1632_op; } # F6.1.67 p8023 A1 cases op:sz = 11 (c1616, c0808) # F6.1.76 p8044 A1 cases op:sz = 11 (c1616, c0808) -:vcvt^vcvt_bt1664_op^COND^".f16.f64" Sd,Dm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=1) +:vcvt^vcvt_bt1664_op^COND^".f16.f64" Sd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=1) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=1)) & COND & vcvt_bt1664_op & Sd & Dm { build COND; build vcvt_bt1664_op; } -# vcvtr - -# F6.1.75 p8040 A1 case opc2=100 size=10 (c1618, c0809) -:vcvtr^COND^".u32.f32" Sd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b10) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10)) - & COND & Sd & Sm - { build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); } - -# F6.1.75 p8040 A1 case opc2=101 size=10 -:vcvtr^COND^".s32.f32" Sd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b10) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10)) - & COND & Sd & Sm - { build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, $(FPSCR_RMODE)); } -# F6.1.75 p8040 A1 case opc2=100 size=11 -:vcvtr^COND^".u32.f64" Sd,Dm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b11) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11)) - & COND & Sd & Dm - { build COND; Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); } -# F6.1.75 p8040 A1 case opc2=101 size=11 -:vcvtr^COND^".s32.f64" Sd,Dm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b11) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11)) - & COND & Sd & Dm - { build COND; Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, $(FPSCR_RMODE)); } +@if defined(VERSION_8M) +dupImm: "#"^val is thv_c0707 & thv_c0000 [ val = 1 << (thv_c0707 << 1 + thv_c0000);] { export *[const]:1 val; } + +# (DDI0553B) C2.4.344 p. 1116 VDDUP, VDWDUP +define pcodeop VectorDecrementAndDuplicate; +:vdwdup.u^esize2021 cor_Qd,cor_Rn,cor_Rm,dupImm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=1 & thv_c1212=1 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=2 & esize2021 & cor_Qd & cor_Rn & cor_Rm & dupImm { + cor_Qd = VectorDecrementAndDuplicate(cor_Rn, cor_Rm, dupImm); +} + +:vddup.u^esize2021 cor_Qd,cor_Rn,dupImm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=1 & thv_c1212=1 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=2 & thv_c0103=7 & esize2021 & cor_Qd & cor_Rn & dupImm { + cor_Qd = VectorDecrementAndDuplicate(cor_Rn, 0:1, dupImm); +} + +# (DDI0553B) C2.4.349 p. 1127 VFMA (vector by scalar plus vector, floating-point) +define pcodeop VectorFusedMultiplyAccumulateVbSpV; +define pcodeop VectorFusedMultiplyAccumulateVbVpS; +:vfma.^fesize2828 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c1616=1 & thv_c1212=0 & thv_c0811=0xe & thv_Q6=1 & thv_c0405=0 & fesize2828 & cor_Qd & cor_Qn & thv_Rm { + cor_Qd = VectorFusedMultiplyAccumulateVbSpV(cor_Qd, cor_Qn, thv_Rm, fesize2828); +} + +# (DDI0553B) C2.4.351 p. 1131 VFMAS (vector by vector plus scalar, floating-point) + +:vfmas.^fesize2828 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1e & thv_c1616=1 & thv_c1212=1 & thv_c0811=0xe & thv_Q6=1 & thv_c0405=0 & fesize2828 & cor_Qd & cor_Qn & thv_Rm { + cor_Qd = VectorFusedMultiplyAccumulateVbVpS(cor_Qd, cor_Qn, thv_Rm, fesize2828); +} + +# (DDI0553B) C2.4.355 T2 p. 1139 VHADD +:vhadd.^udt^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c &thv_c1616=0 & thv_c1212=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=0 & udt & esize2021 & cor_Qd & cor_Qn & thv_Rm { + cor_Qd = VectorHalvingAdd(cor_Qn,thv_Rm,esize2021,udt); +} + +# (DDI0553B) C2.4.356 p. 1141 VHCADD +define pcodeop VectorHavingComplexAdd; +:vhcadd.s^esize2021 cor_Qd,cor_Qn,cor_Qm,crot1212 is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & thv_c0000=0 & esize2021 & cor_Qd & cor_Qn & cor_Qm & crot1212 { + cor_Qd = VectorHavingComplexAdd(cor_Qn, cor_Qm, crot1212); +} + +# (DDI0553B) C2.4.357 T2 p. 1143 VHSUB +:vhsub.^udt^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c &thv_c1616=0 & thv_c1212=1 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=0 & udt & esize2021 & cor_Qd & cor_Qn & thv_Rm { + cor_Qd = VectorHalvingSubtract(cor_Qn,thv_Rm,esize2021,udt); +} + +# (DDI0553B) C2.4.358 p. 1145 VIDUP, VIWDUP +define pcodeop VectorIncrementAndDuplicate; +:viwdup.u^esize2021 cor_Qd,cor_Rn,cor_Rm,dupImm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=1 & thv_c1212=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=2 & esize2021 & cor_Qd & cor_Rn & cor_Rm & dupImm { + cor_Qd = VectorIncrementAndDuplicate(cor_Rn, cor_Rm, dupImm); +} + +:vidup.u^esize2021 cor_Qd,cor_Rn,dupImm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=1 & thv_c1212=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0405=2 & thv_c0103=7 & esize2021 & cor_Qd & cor_Rn & dupImm { + cor_Qd = VectorIncrementAndDuplicate(cor_Rn, 0:1, dupImm); +} + +pat0506: val is thv_c0506 [ val = thv_c0506 * 1; ] { export *[const]:4 val; } + +# (DDI0553B) C2.4.360 p. 1149 VLD2 +RnAddrPat: [thv_Rn] is thv_Rn & pat0506 { local baseAddr = thv_Rn + (pat0506 << 2); export baseAddr; } +wbackRn2: "" is thv_Rn & thv_c2121=0 { } +wbackRn2: "!" is thv_Rn & thv_c2121=1 { thv_Rn = thv_Rn + 32; } + +vld2List: {cor_Qd0,cor_Qd1} is cor_Qd0 & cor_Qd1 & thv_c0708=0 & pat0506 { + local count:1 = 0; + local ptr0 = &cor_Qd0 + 16*pat0506; + local ptr1 = &cor_Qd1 + 16*pat0506; + + *[register]:1 ptr0 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr1 = *:1 mult_addr; + mult_addr = mult_addr + 1; + count = count + 1; + ptr0 = ptr0 + 1; + ptr1 = ptr1 + 1; + if count == 16 goto ; + goto ; + +} + +vld2List: {cor_Qd0,cor_Qd1} is cor_Qd0 & cor_Qd1 & thv_c0708=1 & pat0506 { + local count:1 = 0; + local ptr0 = &cor_Qd0 + 16*pat0506; + local ptr1 = &cor_Qd1 + 16*pat0506; + + *[register]:2 ptr0 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr1 = *:2 mult_addr; + mult_addr = mult_addr + 2; + count = count + 1; + ptr0 = ptr0 + 2; + ptr1 = ptr1 + 2; + if count == 8 goto ; + goto ; + +} + +vld2List: {cor_Qd0,cor_Qd1} is cor_Qd0 & cor_Qd1 & thv_c0708=2 & pat0506 { + local count :1= 0; + local ptr0 = &cor_Qd0 + 16*pat0506; + local ptr1 = &cor_Qd1 + 16*pat0506; + + *[register]:4 ptr0 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr1 = *:4 mult_addr; + mult_addr = mult_addr + 4; + count = count + 1; + ptr0 = ptr0 + 4; + ptr1 = ptr1 + 4; + if count == 4 goto ; + goto ; + +} + +:vld2^pat0506^"."^esize0708 vld2List, RnAddrPat^wbackRn2 is $(TMODE_F) & thv_c2327=0x19 & thv_c2020=1 & thv_c1212=1 & thv_c0911=7 & thv_Q6=0 & thv_c0004=0 & esize0708 & pat0506 & RnAddrPat & vld2List & wbackRn2 { + mult_addr = RnAddrPat; + build vld2List; + build wbackRn2; +} + +# (DDI0553B) C2.4.361 p. 1151 VLD4 +wbackRn4: "" is thv_Rn & thv_c2121=0 { } +wbackRn4: "!" is thv_Rn & thv_c2121=1 { thv_Rn = thv_Rn + 64; } + +vld4List: {cor_Qd0,cor_Qd1,cor_Qd2,cor_Qd3} is cor_Qd0 & cor_Qd1 & cor_Qd2 & cor_Qd3 & thv_c0708=0 & pat0506 { + local count:1 = 0; + local ptr0 = &cor_Qd0 + 8*pat0506; + local ptr1 = &cor_Qd1 + 8*pat0506; + local ptr2 = &cor_Qd2 + 8*pat0506; + local ptr3 = &cor_Qd3 + 8*pat0506; + + *[register]:1 ptr0 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr1 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr2 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr3 = *:1 mult_addr; + mult_addr = mult_addr + 1; + count = count + 1; + ptr0 = ptr0 + 1; + ptr1 = ptr1 + 1; + ptr2 = ptr2 + 1; + ptr3 = ptr3 + 1; + if count == 16 goto ; + goto ; + +} + +vld4List: {cor_Qd0,cor_Qd1,cor_Qd2,cor_Qd3} is cor_Qd0 & cor_Qd1 & cor_Qd2 & cor_Qd3 & thv_c0708=1 & pat0506 { + local count:1 = 0; + local ptr0 = &cor_Qd0 + 8*pat0506; + local ptr1 = &cor_Qd1 + 8*pat0506; + local ptr2 = &cor_Qd2 + 8*pat0506; + local ptr3 = &cor_Qd3 + 8*pat0506; + + *[register]:2 ptr0 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr1 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr2 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr3 = *:2 mult_addr; + mult_addr = mult_addr + 2; + count = count + 1; + ptr0 = ptr0 + 2; + ptr1 = ptr1 + 2; + ptr2 = ptr2 + 2; + ptr3 = ptr3 + 2; + if count == 8 goto ; + goto ; + +} + +vld4List: {cor_Qd0,cor_Qd1,cor_Qd2,cor_Qd3} is cor_Qd0 & cor_Qd1 & cor_Qd2 & cor_Qd3 & thv_c0708=2 & pat0506 { + local count :1= 0; + local ptr0 = &cor_Qd0 + 8*pat0506; + local ptr1 = &cor_Qd1 + 8*pat0506; + local ptr2 = &cor_Qd2 + 8*pat0506; + local ptr3 = &cor_Qd3 + 8*pat0506; + + *[register]:4 ptr0 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr1 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr2 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr3 = *:4 mult_addr; + mult_addr = mult_addr + 4; + count = count + 1; + ptr0 = ptr0 + 4; + ptr1 = ptr1 + 4; + ptr2 = ptr2 + 4; + ptr3 = ptr3 + 4; + if count == 4 goto ; + goto ; + +} + +:vld4^pat0506^"."^esize0708 vld4List, RnAddrPat^wbackRn4 is $(TMODE_F) & thv_c2327=0x19 & thv_c2020=1 & thv_c1212=1 & thv_c0911=7 & thv_Q6=0 & thv_c0004=1 & esize0708 & pat0506 & RnAddrPat & vld4List & wbackRn4 { + mult_addr = RnAddrPat; + build vld4List; + build wbackRn4; +} + +# (DDI0553B) C2.4.364 p. 1160 VLDR (System Register) +vldrSimm: "#"^val is thv_c2323=0 & cor_imm7 [ val = cor_imm7 * 4; ] { export *[const]:4 val; } +vldrSimm: "#"^val is thv_c2323=1 & cor_imm7 [ val = cor_imm7 * (-4); ] { export *[const]:4 val; } + +vldrRnc: "["^thv_Rn^"]" is thv_Rn & thv_c2424=1 & cor_imm7=0 { ptr:4 = thv_Rn; export ptr; } +vldrRnc: "["^thv_Rn,vldrSimm^"]" is thv_Rn & thv_c2424=1 & thv_c2121=0 & vldrSimm { ptr:4 = thv_Rn + vldrSimm; export ptr; } +vldrRnc: "["^thv_Rn,vldrSimm^"]!" is thv_Rn & thv_c2424=1 & thv_c2121=1 & vldrSimm { ptr:4 = thv_Rn + vldrSimm; thv_Rn = ptr; export ptr; } +vldrRnc: "["^thv_Rn^"]",vldrSimm is thv_Rn & thv_c2424=0 & thv_c2121=1 & vldrSimm { ptr:4 = thv_Rn; thv_Rn = thv_Rn + vldrSimm; export ptr; } + +define pcodeop fpActiveCheck; +:vldr fpscr, vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=1 & thv_c1212=0 & thv_c0711=0x1f & vldrRnc & thv_c2222=0 & thv_c1315=1 & fpscr { + fpscr = *:4 vldrRnc; +} + +:vldr "fpscr_nzcvqc", vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=1 & thv_c1212=0 & thv_c0711=0x1f & vldrRnc & thv_c2222=0 & thv_c1315=2 { + local result:4 = *:4 vldrRnc; + fpscr[27,5] = result[27,5]; +} + +:vldr vpr, vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=1 & thv_c1212=0 & thv_c0711=0x1f & vldrRnc & thv_c2222=1 & thv_c1315=4 & vpr { + vpr = *:4 vldrRnc; +} + +:vldr "p0", vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=1 & thv_c1212=0 & thv_c0711=0x1f & vldrRnc & thv_c2222=1 & thv_c1315=5 { + local result:4 = *:4 vldrRnc; + vpr[0,16] = result[0,16]; +} + +:vldr "fpcxt_ns", vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=1 & thv_c1212=0 & thv_c0711=0x1f & vldrRnc & thv_c2222=1 & thv_c1315=6 { + local result:4 = *:4 vldrRnc; + fpActive:1 = fpActiveCheck(); + if fpActive == 0 goto ; + fpscr = zext(result[0,28]); + +} + +:vldr "fpcxt_s", vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=1 & thv_c1212=0 & thv_c0711=0x1f & vldrRnc & thv_c2222=1 & thv_c1315=7 { + local result:4 = *:4 vldrRnc; + fpscr = zext(result[0,28]); +} + + +# (DDI0553B) C2.4.365 p. 1163 VLDRB, VLDRH, VLDRW +define pcodeop VectorLoadRegister; +:vldrb.^udt^esize0708 cor_Qd,vldrRnc is $(TMODE_EorF) & thv_c2527=6 & thv_c2222=0 & thv_c2020=1 & thv_c1919=0 & thv_c1212=0 & thv_c0911=7 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorLoadRegister(vldrRnc, 0:1, esize0708, udt); +} + +:vldrh.^udt^esize0708 cor_Qd,vldrRnc is $(TMODE_EorF) & thv_c2527=6 & thv_c2222=0 & thv_c2020=1 & thv_c1919=1 & thv_c1212=0 & thv_c0911=7 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorLoadRegister(vldrRnc, 1:1, esize0708, udt); +} + +:vldrb.8 cor_Qd,vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=1 & thv_c1212=1 & thv_c0811=0xe & thv_c0707=0 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorLoadRegister(vldrRnc, 0:1, esize0708, udt); +} + +:vldrh.16 cor_Qd,vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=1 & thv_c1212=1 & thv_c0811=0xe & thv_c0707=1 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorLoadRegister(vldrRnc, 1:1, esize0708, udt); +} + +:vldrw.32 cor_Qd,vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=1 & thv_c1212=1 & thv_c0811=0xf & thv_c0707=0 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorLoadRegister(vldrRnc, 2:1, esize0708, udt); +} + +# Display for address vector, exports offset +vldrRnQm: [thv_Rn,cor_Qm] is thv_Rn & cor_Qm & thv_c0000=0 {tmp:1 = 0; export *[const]:1 tmp; } +vldrRnQm: [thv_Rn,cor_Qm,"UXTW #"^os] is thv_Rn & cor_Qm & thv_Q6 & thv_c0404 & thv_c0000=1 [os = (thv_Q6 << 1) + thv_c0404; ] {export *[const]:1 os; } + +# (DDI0553B) C2.4.366 p. 1168 VLDRB, VLDRH, VLDRW, VLDRD (vector) +define pcodeop VectorGatherLoad; # output = VectorGatherLoad(base address, offset vector, immediate, shift, esize, msize, signed) +:vldrb.^udt^esize0708 cor_Qd,vldrRnQm is $(TMODE_EorF) & thv_c2327=0x19 & thv_c2021=1 & thv_c1212=0 & thv_c0911=7 & thv_Q6=0 & thv_c0404=0 & thv_c0000 & udt & esize0708 & cor_Qd & vldrRnQm & thv_Rn & cor_Qm { + cor_Qd = VectorGatherLoad(thv_Rn, cor_Qm, 0:1, 0:1, esize0708, vldrRnQm, udt); +} + +:vldrh.^udt^esize0708 cor_Qd,vldrRnQm is $(TMODE_EorF) & thv_c2327=0x19 & thv_c2021=1 & thv_c1212=0 & thv_c0911=7 & thv_Q6=0 & thv_c0404=1 & thv_c0000 & udt & esize0708 & cor_Qd & vldrRnQm & thv_Rn & cor_Qm { + cor_Qd = VectorGatherLoad(thv_Rn, cor_Qm, 0:1, thv_c0000:1, esize0708, vldrRnQm, udt); +} + +:vldrw.^udt^esize0708 cor_Qd,vldrRnQm is $(TMODE_EorF) & thv_c2327=0x19 & thv_c2021=1 & thv_c1212=0 & thv_c0911=7 & thv_Q6=1 & thv_c0404=0 & thv_c0000 & udt & esize0708 & cor_Qd & vldrRnQm & thv_Rn & cor_Qm { + cor_Qd = VectorGatherLoad(thv_Rn, cor_Qm, 0:1, thv_c0000:1, esize0708, vldrRnQm, udt); +} + +:vldrd.^udt^esize0708 cor_Qd,vldrRnQm is $(TMODE_EorF) & thv_c2327=0x19 & thv_c2021=1 & thv_c1212=0 & thv_c0911=7 & thv_Q6=1 & thv_c0404=1 & thv_c0000 & udt & esize0708 & cor_Qd & vldrRnQm & thv_Rn & cor_Qm { + cor_Qd = VectorGatherLoad(thv_Rn, cor_Qm, 0:1, thv_c0000:1, esize0708, vldrRnQm, udt); +} + +# Display for address vector, exports writeback +vldrQmImm: "["^cor_Qn^"]" is cor_Qn & thv_c2121 & cor_imm7=0 { tmp:1 = 0; export *[const]:1 tmp; } +vldrQmImm: "["^cor_Qn,vldrSimm^"]" is cor_Qn & thv_c2121=0 & vldrSimm { tmp:1 = 0; export *[const]:1 tmp; } +vldrQmImm: "["^cor_Qn,vldrSimm^"]!" is cor_Qn & thv_c2121=1 & vldrSimm { tmp:1 = 1; export *[const]:1 tmp; } + +:vldrw.32 cor_Qd,vldrQmImm is $(TMODE_F) & thv_c2327=0x1d & thv_c2020=1 & thv_c1616=0 & thv_c1212=1 & thv_c0811=0xe & cor_Qd & vldrQmImm & vldrSimm & cor_Qn { + cor_Qd = VectorGatherLoad(0:4, cor_Qn, vldrSimm, 0:1, 2:1, 2:1, vldrQmImm); +} + +:vldrd.64 cor_Qd,vldrQmImm is $(TMODE_F) & thv_c2327=0x1d & thv_c2020=1 & thv_c1616=0 & thv_c1212=1 & thv_c0811=0xf & cor_Qd & vldrQmImm & vldrSimm & cor_Qn { + cor_Qd = VectorGatherLoad(0:4, cor_Qn, vldrSimm, 0:1, 3:1, 3:1, vldrQmImm); +} + +macro vlldm_load(reg, ptr) { + reg = *:4 ptr; + ptr = ptr + 4; +} + +# (DDI0553B) C2.4.367 p. 1174 VLLDM +:vlldm thv_Rn,"{d0-d15}" is $(TMODE_E) & thv_c2427=0xc & thv_c2023=3 & thv_c1215=0 & thv_c0811=0xa & thv_c0007=0 & thv_Rn { + local ptr:4 = thv_Rn; + vlldm_load(s0, ptr); + vlldm_load(s1, ptr); + vlldm_load(s2, ptr); + vlldm_load(s3, ptr); + vlldm_load(s4, ptr); + vlldm_load(s5, ptr); + vlldm_load(s6, ptr); + vlldm_load(s7, ptr); + vlldm_load(s8, ptr); + vlldm_load(s9, ptr); + vlldm_load(s10, ptr); + vlldm_load(s11, ptr); + vlldm_load(s12, ptr); + vlldm_load(s13, ptr); + vlldm_load(s14, ptr); + vlldm_load(s15, ptr); + vlldm_load(fpscr, ptr); + vlldm_load(vpr, ptr); + vlldm_load(s16, ptr); + vlldm_load(s17, ptr); + vlldm_load(s18, ptr); + vlldm_load(s19, ptr); + vlldm_load(s20, ptr); + vlldm_load(s21, ptr); + vlldm_load(s22, ptr); + vlldm_load(s23, ptr); + vlldm_load(s24, ptr); + vlldm_load(s25, ptr); + vlldm_load(s26, ptr); + vlldm_load(s27, ptr); + vlldm_load(s28, ptr); + vlldm_load(s29, ptr); + vlldm_load(s30, ptr); + vlldm_load(s31, ptr); +} + +# Behaves identically to the above variant in practice +:vlldm thv_Rn,"{d0-d31}" is $(TMODE_E) & thv_c2427=0xc & thv_c2023=3 & thv_c1215=0 & thv_c0811=0xa & thv_c0007=0x80 & thv_Rn { + local ptr:4 = thv_Rn; + vlldm_load(s0, ptr); + vlldm_load(s1, ptr); + vlldm_load(s2, ptr); + vlldm_load(s3, ptr); + vlldm_load(s4, ptr); + vlldm_load(s5, ptr); + vlldm_load(s6, ptr); + vlldm_load(s7, ptr); + vlldm_load(s8, ptr); + vlldm_load(s9, ptr); + vlldm_load(s10, ptr); + vlldm_load(s11, ptr); + vlldm_load(s12, ptr); + vlldm_load(s13, ptr); + vlldm_load(s14, ptr); + vlldm_load(s15, ptr); + vlldm_load(fpscr, ptr); + vlldm_load(vpr, ptr); + vlldm_load(s16, ptr); + vlldm_load(s17, ptr); + vlldm_load(s18, ptr); + vlldm_load(s19, ptr); + vlldm_load(s20, ptr); + vlldm_load(s21, ptr); + vlldm_load(s22, ptr); + vlldm_load(s23, ptr); + vlldm_load(s24, ptr); + vlldm_load(s25, ptr); + vlldm_load(s26, ptr); + vlldm_load(s27, ptr); + vlldm_load(s28, ptr); + vlldm_load(s29, ptr); + vlldm_load(s30, ptr); + vlldm_load(s31, ptr); +} + +macro vlstm_store(reg, ptr) { + *:4 ptr = reg; + ptr = ptr + 4; +} +# (DDI0553B) C2.4.368 p. 1177 VLSTM +:vlstm thv_Rn,"{d0-d15}" is $(TMODE_E) & thv_c2427=0xc & thv_c2023=2 & thv_c1215=0 & thv_c0811=0xa & thv_c0007=0 & thv_Rn { + local ptr:4 = thv_Rn; + vlstm_store(s0, ptr); + vlstm_store(s1, ptr); + vlstm_store(s2, ptr); + vlstm_store(s3, ptr); + vlstm_store(s4, ptr); + vlstm_store(s5, ptr); + vlstm_store(s6, ptr); + vlstm_store(s7, ptr); + vlstm_store(s8, ptr); + vlstm_store(s9, ptr); + vlstm_store(s10, ptr); + vlstm_store(s11, ptr); + vlstm_store(s12, ptr); + vlstm_store(s13, ptr); + vlstm_store(s14, ptr); + vlstm_store(s15, ptr); + vlstm_store(fpscr, ptr); + vlstm_store(vpr, ptr); + vlstm_store(s16, ptr); + vlstm_store(s17, ptr); + vlstm_store(s18, ptr); + vlstm_store(s19, ptr); + vlstm_store(s20, ptr); + vlstm_store(s21, ptr); + vlstm_store(s22, ptr); + vlstm_store(s23, ptr); + vlstm_store(s24, ptr); + vlstm_store(s25, ptr); + vlstm_store(s26, ptr); + vlstm_store(s27, ptr); + vlstm_store(s28, ptr); + vlstm_store(s29, ptr); + vlstm_store(s30, ptr); + vlstm_store(s31, ptr); +} + +# Behaves identically to the above variant in practice +:vlstm thv_Rn,"{d0-d31}" is $(TMODE_E) & thv_c2427=0xc & thv_c2023=2 & thv_c1215=0 & thv_c0811=0xa & thv_c0007=0x80 & thv_Rn { + local ptr:4 = thv_Rn; + vlstm_store(s0, ptr); + vlstm_store(s1, ptr); + vlstm_store(s2, ptr); + vlstm_store(s3, ptr); + vlstm_store(s4, ptr); + vlstm_store(s5, ptr); + vlstm_store(s6, ptr); + vlstm_store(s7, ptr); + vlstm_store(s8, ptr); + vlstm_store(s9, ptr); + vlstm_store(s10, ptr); + vlstm_store(s11, ptr); + vlstm_store(s12, ptr); + vlstm_store(s13, ptr); + vlstm_store(s14, ptr); + vlstm_store(s15, ptr); + vlstm_store(fpscr, ptr); + vlstm_store(vpr, ptr); + vlstm_store(s16, ptr); + vlstm_store(s17, ptr); + vlstm_store(s18, ptr); + vlstm_store(s19, ptr); + vlstm_store(s20, ptr); + vlstm_store(s21, ptr); + vlstm_store(s22, ptr); + vlstm_store(s23, ptr); + vlstm_store(s24, ptr); + vlstm_store(s25, ptr); + vlstm_store(s26, ptr); + vlstm_store(s27, ptr); + vlstm_store(s28, ptr); + vlstm_store(s29, ptr); + vlstm_store(s30, ptr); + vlstm_store(s31, ptr); +} +# (DDI0553B) C2.4.369 p. 1180 VMAX, VMAXA T2 +define pcodeop VectorMaxAbsolute; +:vmaxa.s^esize1819 cor_Qd, cor_Qm is $(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=3 & thv_c1212=0 & thv_c0811=0xe & thv_c0607=2 & thv_c0404=0 & thv_c0000=1 & esize1819 & cor_Qm & cor_Qd { + cor_Qd = VectorMaxAbsolute(cor_Qd,cor_Qm,esize1819); +} + +@endif # VERSION_8M ####### # VMAXNM/VMINNM - - -# FPMaxNum(Vn, Vm) +# FPMaxNum(Vn, Vm, size, abs) # Return the maximum of two floating point numbers. # Includes FP and SIMD variants of all lane sizes. - define pcodeop FPMaxNum; -# FPMinNum(Vn, Vm) +# FPMinNum(Vn, Vm, size, abs) # Return the minimum of two floating point numbers. # Includes FP and SIMD variants of all lane sizes. define pcodeop FPMinNum; # F6.1.117 p8178 A1/T1 Q = 0 (c0606) -:vmaxnm^".f32" Dd,Dn,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0) +:vmaxnm^".f32" Dd,Dn,Dm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) & Dd & Dn & Dm { Dd = FPMaxNum(Dn, Dm); } # F6.1.117 p8178 A1/T1 Q = 1 (c0606) -:vmaxnm^".f32" Qd,Qn,Qm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1) +:vmaxnm^".f32" Qd,Qn,Qm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) & Qd & Qn & Qm { Qd = FPMaxNum(Qn, Qm); } # F6.1.117 p8178 A1/T1 Q = 0 (c0606) -:vmaxnm^".f16" Dd,Dn,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0) +:vmaxnm^".f16" Dd,Dn,Dm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) & Dd & Dn & Dm { Dd = FPMaxNum(Dn, Dm); } # F6.1.117 p8178 A1/T1 Q = 1 (c0606) -:vmaxnm^".f16" Qd,Qn,Qm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1) +:vmaxnm^".f16" Qd,Qn,Qm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) & Qd & Qn & Qm { Qd = FPMaxNum(Qn, Qm); } # F6.1.117 p8178 A2/T2 size = 01 (c0809) -:vmaxnm^".f16" Sd,Sn,Sm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01) +:vmaxnm^".f16" Sd,Sn,Sm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b01)) & Sd & Sn & Sm { Sd = FPMaxNum(Sn, Sm); } # F6.1.117 p8178 A2/T2 size = 10 (c0809) -:vmaxnm^".f32" Sd,Sn,Sm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) +:vmaxnm^".f32" Sd,Sn,Sm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10)) & Sd & Sn & Sm { Sd = FPMaxNum(Sn, Sm); } # F6.1.117 p8178 A2/T2 size = 11 (c0809) -:vmaxnm^".f64" Dd,Dn,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) +:vmaxnm^".f64" Dd,Dn,Dm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11)) & Dd & Dn & Dm { Dd = FPMaxNum(Dn, Dm); } +@if defined(VERSION_8M) +# (DDI0553B) C2.4.371 p. 1185 VMAXNM, VMAXNMA (floating-point) T2 +define pcodeop FloatVectorMaxAbsolute; +:vmaxnma.f16 is $(TMODE_F) & thv_c2327=0x1c & thv_c2021=3 & thv_c1619=0xf & thv_c1212=0 & thv_c0811=0xe & thv_c0607=2 & thv_c0404=0 & thv_c0000=1 & cor_Qm & cor_Qd { + cor_Qd = FloatVectorMaxAbsolute(cor_Qd, cor_Qm, 1:1); +} + +:vmaxnma.f32 is $(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c1619=0xf & thv_c1212=0 & thv_c0811=0xe & thv_c0607=2 & thv_c0404=0 & thv_c0000=1 & cor_Qm & cor_Qd { + cor_Qd = FloatVectorMaxAbsolute(cor_Qd, cor_Qm, 2:1); +} + +# (DDI0553B) C2.4.372 p. 1187 VMAXNMV, VMAXNMAV (floating-point) +define pcodeop FloatVectorMaxAcrossVector; +define pcodeop FloatVectorMaxAcrossVectorAbsolute; +:vmaxnmv.f16 thv_Rd,cor_Qm is $(TMODE_F) & thv_c1631=0xfeee & thv_c0811=0xf & thv_c0607=0 & thv_c0404=0 & thv_c0000=0 & thv_Rd & cor_Qm { + thv_Rd = FloatVectorMaxAcrossVector(cor_Qm, 1:1); +} + +:vmaxnmv.f32 thv_Rd,cor_Qm is $(TMODE_E) & thv_c1631=0xeeee & thv_c0811=0xf & thv_c0607=0 & thv_c0404=0 & thv_c0000=0 & thv_Rd & cor_Qm { + thv_Rd = FloatVectorMaxAcrossVector(cor_Qm, 2:1); +} + +:vmaxnmva.f16 thv_Rd,cor_Qm is $(TMODE_F) & thv_c1631=0xfeec & thv_c0811=0xf & thv_c0607=0 & thv_c0404=0 & thv_c0000=0 & thv_Rd & cor_Qm { + thv_Rd = FloatVectorMaxAcrossVectorAbsolute(cor_Qm, 1:1); +} + +:vmaxnmva.f32 thv_Rd,cor_Qm is $(TMODE_E) & thv_c1631=0xeeec & thv_c0811=0xf & thv_c0607=0 & thv_c0404=0 & thv_c0000=0 & thv_Rd & cor_Qm { + thv_Rd = FloatVectorMaxAcrossVectorAbsolute(cor_Qm, 2:1); +} + +# (DDI0553B) C2.4.373 p. 1189 VMAXV, VMAXAV +define pcodeop VectorMaxAcrossVector; +define pcodeop VectorMaxAcrossVectorAbsolute; +:vmaxv.^udt^esize1819 thv_Rd,cor_Qm is $(TMODE_EorF) & thv_c2427=0xe & thv_c2023=0xe & thv_c1617=2 & thv_c0811=0xf & thv_c0607=0 & thv_c0404=0 & thv_c0000=0 & udt & esize1819 & cor_Qm & thv_Rd { + thv_Rd = VectorMaxAcrossVector(thv_Rd,cor_Qm,esize1819); +} +:vmaxav.s^esize1819 thv_Rd,cor_Qm is $(TMODE_E) & thv_c2427=0xe & thv_c2023=0xe & thv_c1617=0 & thv_c0811=0xf & thv_c0607=0 & thv_c0404=0 & thv_c0000=0 & esize1819 & cor_Qm & thv_Rd { + thv_Rd = VectorMaxAcrossVectorAbsolute(thv_Rd,cor_Qm,esize1819); +} + +# (DDI0553B) C2.4.374 p. 1191 VMIN, VMINA T2 +define pcodeop VectorMinAbsolute; +:vmina.s^esize1819 cor_Qd, cor_Qm is $(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=3 & thv_c1212=1 & thv_c0811=0xe & thv_c0607=2 & thv_c0404=0 & thv_c0000=1 & esize1819 & cor_Qm & cor_Qd { + cor_Qd = VectorMinAbsolute(cor_Qd,cor_Qm,esize1819); +} +@endif # VERSION_8M + # F6.1.120 p8178 A1/T1 Q = 0 (c0606) -:vminnm^".f32" Dd,Dn,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0) +:vminnm^".f32" Dd,Dn,Dm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) & Dd & Dn & Dm { Dd = FPMinNum(Dn, Dm); } # F6.1.120 p8178 A1/T1 Q = 1 (c0606) -:vminnm^".f32" Qd,Qn,Qm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1) +:vminnm^".f32" Qd,Qn,Qm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) & Qd & Qn & Qm { Qd = FPMinNum(Qn, Qm); } # F6.1.120 p8178 A1/T1 Q = 0 (c0606) -:vminnm^".f16" Dd,Dn,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0) +:vminnm^".f16" Dd,Dn,Dm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) & Dd & Dn & Dm { Dd = FPMinNum(Dn, Dm); } # F6.1.120 p8178 A1/T1 Q = 1 (c0606) -:vminnm^".f16" Qd,Qn,Qm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1) +:vminnm^".f16" Qd,Qn,Qm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) & Qd & Qn & Qm { Qd = FPMinNum(Qn, Qm); } # F6.1.120 p8178 A2/T2 size = 01 (c0809) -:vminnm^".f16" Sd,Sn,Sm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01) +:vminnm^".f16" Sd,Sn,Sm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01)) & Sd & Sn & Sm { Sd = FPMinNum(Sn, Sm); } # F6.1.120 p8178 A2/T2 size = 10 (c0809) -:vminnm^".f32" Sd,Sn,Sm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) +:vminnm^".f32" Sd,Sn,Sm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) & Sd & Sn & Sm { Sd = FPMinNum(Sn, Sm); } # F6.1.120 p8178 A2/T2 size = 11 (c0809) -:vminnm^".f64" Dd,Dn,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) +:vminnm^".f64" Dd,Dn,Dm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) & Dd & Dn & Dm { Dd = FPMinNum(Dn, Dm); } +@if defined(VERSION_8M) +# (DDI0553B) C2.4.376 p. 1196 VMINNM, VMINNMA (floating-point) T2 +define pcodeop FloatVectorMinAbsolute; +:vminnma.f16 is $(TMODE_F) & thv_c2327=0x1c & thv_c2021=3 & thv_c1619=0xf & thv_c1212=1 & thv_c0811=0xe & thv_c0607=2 & thv_c0404=0 & thv_c0000=1 & cor_Qm & cor_Qd { + cor_Qd = FloatVectorMinAbsolute(cor_Qd, cor_Qm, 1:1); +} + +:vminnma.f32 is $(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c1619=0xf & thv_c1212=1 & thv_c0811=0xe & thv_c0607=2 & thv_c0404=0 & thv_c0000=1 & cor_Qm & cor_Qd { + cor_Qd = FloatVectorMinAbsolute(cor_Qd, cor_Qm, 2:1); +} + +# (DDI0553B) C2.4.377 p. 1198 VMINNMV, VMINNMAV (floating-point) +define pcodeop FloatVectorMinAcrossVector; +define pcodeop FloatVectorMinAcrossVectorAbsolute; +:vminnmv.f16 thv_Rd,cor_Qm is $(TMODE_F) & thv_c1631=0xfeee & thv_c0811=0xf & thv_c0607=2 & thv_c0404=0 & thv_c0000=0 & thv_Rd & cor_Qm { + thv_Rd = FloatVectorMinAcrossVector(cor_Qm, 1:1); +} + +:vminnmv.f32 thv_Rd,cor_Qm is $(TMODE_E) & thv_c1631=0xeeee & thv_c0811=0xf & thv_c0607=2 & thv_c0404=0 & thv_c0000=0 & thv_Rd & cor_Qm { + thv_Rd = FloatVectorMinAcrossVector(cor_Qm, 2:1); +} + +:vminnmva.f16 thv_Rd,cor_Qm is $(TMODE_F) & thv_c1631=0xfeec & thv_c0811=0xf & thv_c0607=2 & thv_c0404=0 & thv_c0000=0 & thv_Rd & cor_Qm { + thv_Rd = FloatVectorMinAcrossVectorAbsolute(cor_Qm, 1:1); +} + +:vminnmva.f32 thv_Rd,cor_Qm is $(TMODE_E) & thv_c1631=0xeeec & thv_c0811=0xf & thv_c0607=2 & thv_c0404=0 & thv_c0000=0 & thv_Rd & cor_Qm { + thv_Rd = FloatVectorMinAcrossVectorAbsolute(cor_Qm, 2:1); +} + +# (DDI0553B) C2.4.378 p. 1200 VMINV, VMINAV +define pcodeop VectorMinAcrossVector; +define pcodeop VectorMinAcrossVectorAbsolute; +:vminv.^udt^esize1819 thv_Rd,cor_Qm is $(TMODE_EorF) & thv_c2427=0xe & thv_c2023=0xe & thv_c1617=2 & thv_c0811=0xf & thv_c0607=2 & thv_c0404=0 & thv_c0000=0 & udt & esize1819 & cor_Qm & thv_Rd { + thv_Rd = VectorMinAcrossVector(thv_Rd,cor_Qm,esize1819); +} +:vminav.s^esize1819 thv_Rd,cor_Qm is $(TMODE_E) & thv_c2427=0xe & thv_c2023=0xe & thv_c1617=0 & thv_c0811=0xf & thv_c0607=2 & thv_c0404=0 & thv_c0000=0 & esize1819 & cor_Qm & thv_Rd { + thv_Rd = VectorMinAcrossVectorAbsolute(thv_Rd,cor_Qm,esize1819); +} + +# (DDI0553B) C2.4.380 p. 1204 VMLA (vector by scalar plus vector) +define pcodeop VectorMultiplyAccumulateVectorByScalar; +# Qd[e] = Qd[e] + Qn[e]*Rm +:vmla.i^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=1 & thv_c1212=0 & thv_c0811=0xe & thv_c0406=4 & esize2021 & cor_Qd & cor_Qn & thv_Rm { + cor_Qd = VectorMultiplyAccumulateVectorByScalar(cor_Qd, cor_Qn, thv_Rm, esize2021); +} + +# (DDI0553B) C2.4.381 1206 VMLADAV +define pcodeop VectorMultiplyAddDualAccumulate; +:vmladav^accum0505^"x."^udt^esize1616 thv_Rda,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2427=0xe & thv_c2023=0xf & thv_c1212=1 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0 & thv_c0000=0 & accum0505 & udt & esize1616 & thv_Rda & cor_Qn & cor_Qm { + thv_Rda = VectorMultiplyAddDualAccumulate(thv_Rda, cor_Qn, cor_Qm, accum0505, 1:1, esize1616, udt); +} + +# Alias when X == 0 +:vmlav^accum0505^"."^udt^esize1616 thv_Rda,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2427=0xe & thv_c2023=0xf & thv_c1212=0 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0 & thv_c0000=0 & accum0505 & udt & esize1616 & thv_Rda & cor_Qn & cor_Qm { + thv_Rda = VectorMultiplyAddDualAccumulate(thv_Rda, cor_Qn, cor_Qm, accum0505, 0:1, esize1616, udt); +} + +:vmladav^accum0505^exch1212^"."^udt^"8" thv_Rda,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2427=0xe & thv_c2023=0xf & thv_c1616=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & thv_c0000=0 & accum0505 & exch1212 & udt & thv_Rda & cor_Qn & cor_Qm { + thv_Rda = VectorMultiplyAddDualAccumulate(thv_Rda, cor_Qn, cor_Qm, accum0505, exch1212, 0:1, udt); +} + +# (DDI0553B) C2.4.382 p. 1209 VMLALDAV +define pcodeop VectorMultiplyAddLongDualAccumulate; +:vmlaldav^accum0505^exch1212^"."^udt^esize1616 thv_Rda,thv_RdaHi2,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2327=0x1d & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & thv_c0000=0 & accum0505 & exch1212 & udt & esize1616 & thv_Rda & thv_RdaHi2 & cor_Qn & cor_Qm { + thv_Rda = VectorMultiplyAddLongDualAccumulate(thv_Rda, thv_RdaHi2, cor_Qn, cor_Qm, accum0505, exch1212, esize1616, udt); +} + +# Alias when X == 0 +:vmlalv^accum0505^"."^udt^esize1616 thv_Rda,thv_RdaHi2,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2327=0x1d & thv_c1212=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & thv_c0000=0 & accum0505 & udt & esize1616 & thv_Rda & thv_RdaHi2 & cor_Qn & cor_Qm { + thv_Rda = VectorMultiplyAddLongDualAccumulate(thv_Rda, thv_RdaHi2, cor_Qn, cor_Qm, accum0505, 0:1, esize1616, udt); +} + + +# (DDI0553B) C2.4.384 p. 1212 VMLAS (vector by vector plus scalar) +define pcodeop VectorMultiplyAccumulateVectorPlusScalar; +# Qd[e] = Qd[e]*Qn[e] + Rm +:vmlas.i^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=0 & thv_c1212=0 & thv_c0811=0xe & thv_c0406=4 & esize2021 & cor_Qd & cor_Qn & thv_Rm { + cor_Qd = VectorMultiplyAccumulateVectorPlusScalar(cor_Qd, cor_Qn, thv_Rm, esize2021); +} + +# (DDI0553B) C2.4.387 p. 1217 VMLSDAV +define pcodeop VectorMultiplySubtractDualAccumulate; +:vmlsdav^accum0505^exch1212^".s"^esize1616 thv_Rda,cor_Qn,cor_Qm is $(TMODE_E) & thv_c2427=0xe & thv_c2023=0xf & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0 & thv_c0000=1 & accum0505 & exch1212 & esize1616 & thv_Rda & cor_Qn & cor_Qm { + thv_Rda = VectorMultiplySubtractDualAccumulate(thv_Rda, cor_Qn, cor_Qm, accum0505, exch1212, esize1616); +} + +:vmlsdav^accum0505^exch1212^".s8" thv_Rda,cor_Qn,cor_Qm is $(TMODE_F) & thv_c2427=0xe & thv_c2023=0xf & thv_c1616=0 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0 & thv_c0000=1 & accum0505 & exch1212 & thv_Rda & cor_Qn & cor_Qm { + thv_Rda = VectorMultiplySubtractDualAccumulate(thv_Rda, cor_Qn, cor_Qm, accum0505, exch1212, 0:1); +} + +# (DDI0553B) C2.4.388 p. 1220 VMLSLDAV +define pcodeop VectorMultiplySubtractLongDualAccumulate; +:vmlsldav^accum0505^exch1212^".s"^esize1616 thv_Rda,thv_RdaHi2,cor_Qn,cor_Qm is $(TMODE_E) & thv_c2327=0x1d & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0 & thv_c0000=1 & accum0505 & exch1212 & udt & esize1616 & thv_Rda & thv_RdaHi2 & cor_Qn & cor_Qm { + thv_Rda = VectorMultiplySubtractLongDualAccumulate(thv_Rda, thv_RdaHi2, cor_Qn, cor_Qm, accum0505, exch1212, esize1616); +} + + +# (DDI0553B) C2.4.393 p. 1228 VMOV (general-purpose register to vector lane) (VERY similar to F6.1.137 VMOV (general-purpose register to scalar) ) +vmov32Idx: val is thv_c1616 & thv_c2121 [ val = (thv_c1616 << 1) + thv_c2121; ] { export *[const]:1 val; } +:vmov^ItCond^".32" cor_Qdm^"["^vmov32Idx^"]", thv_Rt is $(TMODE_E) & ItCond & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=0 & thv_c0811=0xb & thv_c0406=1 & thv_c0003=0 & vmov32Idx & cor_Qdm & thv_Rt { + build ItCond; + vmask:4 = 0xffff; + invMask:16 = ~(zext(vmask) << (vmov32Idx * 32)); + cor_Qdm = (cor_Qdm & invMask) + (zext(thv_Rt) << (vmov32Idx * 32)); +} + +vmov16Idx: val is thv_c1616 & thv_c2121 & thv_c0606 [ val = (thv_c1616 << 2) + (thv_c2121 << 1) + thv_c0606; ] { export *[const]:1 val; } +:vmov^ItCond^".16" cor_Qdm^"["^vmov16Idx^"]", thv_Rt is $(TMODE_E) & ItCond & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=0 & thv_c0811=0xb & thv_c0405=3 & thv_c0003=0 & vmov16Idx & cor_Qdm & thv_Rt { + build ItCond; + vmask:2 = 0xff; + invMask:16 = ~(zext(vmask) << (vmov16Idx * 16)); + cor_Qdm = (cor_Qdm & invMask) + (zext(thv_Rt[0,16]) << (vmov16Idx * 16)); +} + +vmov8Idx: val is thv_c1616 & thv_c2121 & thv_c0506 [ val = (thv_c1616 << 3) + (thv_c2121 << 2) + thv_c0506; ] { export *[const]:1 val; } +:vmov^ItCond^".8" cor_Qdm^"["^vmov8Idx^"]", thv_Rt is $(TMODE_E) & ItCond & thv_c2327=0x1c & thv_c2222=1 & thv_c2020=0 & thv_c0811=0xb & thv_c0404=1 & thv_c0003=0 & vmov8Idx & cor_Qdm & thv_Rt { + build ItCond; + vmask:1 = 0xf; + invMask:16 = ~(zext(vmask) << (vmov8Idx*8)); + cor_Qdm = (cor_Qdm & invMask) | (zext(thv_Rt[0,8]) << (vmov8Idx*8)); +} + +# (DDI0553B) C2.4.400 p. 1239 VMOV (two 32-bit vector lanes to two general-purpose registers) +idx1: cor_Qd^"[^"idxVal^"]" is cor_Qd & thv_c0404 [ idxVal = thv_c0404 + 2; ] { tmp:1 = (thv_c0404:1==1); export *[const]:1 tmp; } +idx2: cor_Qd^"[^"idxVal^"]" is cor_Qd & thv_c0404 [ idxVal = thv_c0404 + 0; ] { tmp:1 = (thv_c0404:1==1); export *[const]:1 tmp; } + +:vmov^ItCond thv_Rm,thv_Rn,idx1,idx2 is $(TMODE_E) & ItCond & thv_c2327=0x18 & thv_c2021=0 & thv_c1212=0 & thv_c0811=0xf & thv_c0507=0 & thv_Rm & thv_Rn & cor_Qd & idx1 & idx2 { + build ItCond; + local w0:4 = cor_Qd[0,32]; + local w1:4 = cor_Qd[32,32]; + local w2:4 = cor_Qd[64,32]; + local w3:4 = cor_Qd[96,32]; + thv_Rm = (zext(!idx1) * w2) + (zext(idx1) * w3); + thv_Rn = (zext(!idx2) * w0) + (zext(idx2) * w1); +} +# (DDI0553B) C2.4.401 p. 1241 VMOV (two general-purpose registers to two 32-bit vector lanes) +:vmov^ItCond idx1,idx2,thv_Rm,thv_Rn is $(TMODE_E) & ItCond & thv_c2327=0x18 & thv_c2021=1 & thv_c1212=0 & thv_c0811=0xf & thv_c0507=0 & thv_Rm & thv_Rn & cor_Qd & idx1 & idx2 { + build ItCond; + cor_Qd[64,32] = (zext(!idx2) * thv_Rm) + (zext(idx2) * cor_Qd[64,32]); + cor_Qd[96,32] = (zext(!idx2) * cor_Qd[64,32]) + (zext(idx2) * thv_Rm); + cor_Qd[0,32] = (zext(!idx2) * thv_Rn) + (zext(idx2) * cor_Qd[0,32]); + cor_Qd[32,32] = (zext(!idx2) * cor_Qd[32,32]) + (zext(idx2) * thv_Rn); +} + +# (DDI0553B) C2.4.402 p. 1243 VMOV (vector lane to general-purpose register) +:vmov^ItCond^".32" cor_Qn^"["^vmov32Idx^"]", thv_Rt is $(TMODE_E) & ItCond & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=1 & thv_c0811=0xb & thv_c0406=1 & thv_c0003=0 & vmov32Idx & cor_Qn & thv_Rt { + build ItCond; + vmask:4 = 0xffff; + local val:16 = (cor_Qn >> (vmov32Idx * 32)) & zext(vmask); + thv_Rt = val:4; +} + +:vmov^ItCond^".s16" cor_Qn^"["^vmov16Idx^"]", thv_Rt is $(TMODE_E) & ItCond & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=1 & thv_c0811=0xb & thv_c0405=3 & thv_c0003=0 & vmov16Idx & cor_Qn & thv_Rt { + build ItCond; + vmask:2 = 0xff; + local val:16 = (cor_Qn >> (vmov16Idx * 16)) & zext(vmask); + thv_Rt = sext(val:2); +} + +:vmov^ItCond^".u16" cor_Qn^"["^vmov16Idx^"]", thv_Rt is $(TMODE_E) & ItCond & thv_c2327=0x1d & thv_c2222=0 & thv_c2020=1 & thv_c0811=0xb & thv_c0405=3 & thv_c0003=0 & vmov16Idx & cor_Qn & thv_Rt { + build ItCond; + vmask:2 = 0xff; + local val:16 = (cor_Qn >> (vmov16Idx * 16)) & zext(vmask); + thv_Rt = zext(val:2); +} + +:vmov^ItCond^".s8" cor_Qn^"["^vmov8Idx^"]", thv_Rt is $(TMODE_E) & ItCond & thv_c2327=0x1c & thv_c2222=1 & thv_c2020=1 & thv_c0811=0xb & thv_c0404=1 & thv_c0003=0 & vmov8Idx & cor_Qn & thv_Rt { + build ItCond; + vmask:1 = 0xf; + local val:16 = (cor_Qn >> (vmov8Idx*8)) & zext(vmask); + thv_Rt = sext(val:1); +} + +:vmov^ItCond^".u8" cor_Qn^"["^vmov8Idx^"]", thv_Rt is $(TMODE_E) & ItCond & thv_c2327=0x1d & thv_c2222=1 & thv_c2020=1 & thv_c0811=0xb & thv_c0404=1 & thv_c0003=0 & vmov8Idx & cor_Qn & thv_Rt { + build ItCond; + vmask:1 = 0xf; + local val:16 = (cor_Qn >> (vmov8Idx*8)) & zext(vmask); + thv_Rt = zext(val:1); +} + +# (DDI0553B) C2.4.403 p. 1245 VMOVL (nothing like F6.1.141) +esize1920: "8" is thv_c1920=0 { export 1:4; } +esize1920: "8" is thv_c1920=1 { export 1:4; } +esize1920: "16" is thv_c1920=2 { export 2:4; } +esize1920: "16" is thv_c1920=3 { export 2:4; } + +define pcodeop VectorMoveLong; +:vmovl^bort1212^"."^udt^esize1920 cor_Qd,cor_Qm is $(TMODE_EorF) & thv_c2327=0x1d & thv_c2121=1 & thv_c1618=0 & thv_c0811=0xf & thv_c0607=1 & thv_c0404=0 & thv_c0000=0 & bort1212 & udt & esize1920 & cor_Qd & cor_Qm { + cor_Qd = VectorMoveLong(cor_Qm,bort1212,esize1920); +} + +# (DDI0553B) C2.4.404 p. 1247 VMOVN +define pcodeop VectorMoveNarrow; +:vmovn^bort1212^".i"^esize1819x2 cor_Qd,cor_Qm is $(TMODE_F) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=1 & thv_c0811=0xe & thv_c0607=2 & thv_c0404=0 & thv_c0000=1 & bort1212 & esize1819x2 & cor_Qd & cor_Qm { + cor_Qd = VectorMoveNarrow(cor_Qm,bort1212,1:1,esize1819x2); +} + +# (DDI0553B) C2.4.406 VMRS and C2.4.407 VMSR p. 1250/1253 have additional status register decodes (see ARMneon.sinc) + +# (DDI0553B) C2.4.410 p. 1260 VMUL (vector) T2 +:vmul.i^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_E) & thv_c2327=0x1c & thv_c1212=1 & thv_c0811=0xe & thv_c0406=6 & esize2021 & thv_Rm & cor_Qn & cor_Qd +{ + cor_Qd = VectorMultiply(cor_Qn,thv_Rm,esize2021); +} + +# (DDI0553B) C2.4.411 p. 1262 VMULH, VRMULH +rm1212: "" is thv_c1212=0 { tmp:1 = 0; export *[const]:1 tmp; } +rm1212: "r" is thv_c1212=1 { tmp:1 = 1; export *[const]:1 tmp; } +define pcodeop VectorMultiplyReturningHighHalf; +:v^rm1212^"mulh."^udt^esize2021 is $(TMODE_EorF) & thv_c2327=0x1c & thv_c1616=1 & thv_c0811=0xe & thv_c0606=0 & thv_c0404=0 & thv_c0000=1 & udt & rm1212 & esize2021 & cor_Qd & cor_Qm & cor_Qn { + cor_Qd = VectorMultiplyReturningHighHalf(cor_Qn, cor_Qm, udt, esize2021, rm1212); +} + +@endif # VERSION_8M ####### # VMULL instructions vector/polynomial multiplication +vmull_dt: ".s8" is ((TMode=0 & c0909=0 & c2424=0 & c2021=0b00) + | (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b00)) { } -vmull_dt: ".s8" - is ((TMode=0 & c0909=0 & c2424=0 & c2021=0b00) - | (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b00)) - { } +vmull_dt: ".s16" is ((TMode=0 & c0909=0 & c2424=0 & c2021=0b01) + | (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b01)) { } -vmull_dt: ".s16" - is ((TMode=0 & c0909=0 & c2424=0 & c2021=0b01) - | (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b01)) - { } +vmull_dt: ".s32" is ((TMode=0 & c0909=0 & c2424=0 & c2021=0b10) + | (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b10)) { } -vmull_dt: ".s32" - is ((TMode=0 & c0909=0 & c2424=0 & c2021=0b10) - | (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b10)) - { } +vmull_dt: ".u8" is ((TMode=0 & c0909=0 & c2424=1 & c2021=0b00) + | (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b00)) { } -vmull_dt: ".u8" - is ((TMode=0 & c0909=0 & c2424=1 & c2021=0b00) - | (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b00)) - { } +vmull_dt: ".u16" is ((TMode=0 & c0909=0 & c2424=1 & c2021=0b01) + | (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b01)) { } -vmull_dt: ".u16" - is ((TMode=0 & c0909=0 & c2424=1 & c2021=0b01) - | (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b01)) - { } +vmull_dt: ".u32" is ((TMode=0 & c0909=0 & c2424=1 & c2021=0b10) + | (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b10)) { } -vmull_dt: ".u32" - is ((TMode=0 & c0909=0 & c2424=1 & c2021=0b10) - | (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b10)) - { } +vmull_dt: ".p8" is ((TMode=0 & c0909=1 & c2424=0 & c2021=0b00) + | (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b00)) { } -vmull_dt: ".p8" - is ((TMode=0 & c0909=1 & c2424=0 & c2021=0b00) - | (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b00)) - { } - -vmull_dt: ".p64" - is ((TMode=0 & c0909=1 & c2424=0 & c2021=0b10) - | (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b10)) - { } +vmull_dt: ".p64" is ((TMode=0 & c0909=1 & c2424=0 & c2021=0b10) + | (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b10)) { } # F6.1.149 p8266 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01) -:vmull^vmull_dt Qd,Dn,Dm - is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1) +:vmull^vmull_dt Qd,Dn,Dm is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1) | (TMode=1 & thv_c2931=0b111 & thv_c2828=0 & thv_c2327=0b11111 & (thv_c2121 & thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=1)) & vmull_dt & Qd & Dn & Dm { Qd = PolynomialMult(Dn, Dm); } # F6.1.149 p8266 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11) -:vmull^vmull_dt Qd,Dn,Dm - is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0) +:vmull^vmull_dt Qd,Dn,Dm is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0) | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & (thv_c2121=0 | thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=0)) & vmull_dt & Qd & Dn & Dm { Qd = VectorMultiply(Dn, Dm); } +@if defined(VERSION_8M) + +psize28: val is thv_c2828 [ val = 8 << thv_c2828;] { export *[const]:1 val; } + +# (DDI0553B) C2.4.412 p. 1264 VMULL (integer) +:vmull^bort1212^"."^udt^esize2021 cor_Qd, cor_Qn, cor_Qm is ($(TMODE_EorF) & thv_c2327=0x1c & thv_c2021<3 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) & esize2021 & cor_Qm & cor_Qn & cor_Qd & udt & bort1212 { + cor_Qd = VectorMultiply(cor_Qn,cor_Qm,bort1212,esize2021,udt); +} + +# (DDI0553B) C2.4.413 p. 1266 VMULL (polynomial) +:vmull^bort1212^"."^psize28 cor_Qd, cor_Qn, cor_Qm is ($(TMODE_EorF) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) & cor_Qm & cor_Qn & cor_Qd & psize28 & bort1212 { + cor_Qd = PolynomialMultiply(cor_Qn,cor_Qm,bort1212,psize28); +} + + + +@if defined(VERSION_8M) + +# C2.4.426 VPNOT +:vpnot is $(TMODE_F) & thv_c1627=0xe31 & thv_c0015=0x0f4d { + local p0:2 = $(VPR_P0); + p0 = ~(p0); + $(VPR_P0) = p0; +} +# C2.4.428 VPSEL +:vpsel is $(TMODE_F) & thv_c2327=0x1c & thv_c2021=3 & thv_c1616=1 & thv_c1212=0 & thv_c0811=0xf & thv_c0606=0 & thv_c0404=0 & thv_c0000=1 & cor_Qd & cor_Qn & cor_Qm { + local vp:2 = $(VPR_P0); + local result:16 = 0; + vptest:1 = vp[0,1] == 0; + result[0,8] = (zext(vptest) * cor_Qn[0,8]) + (zext(vptest) * cor_Qm[0,8]); + vptest = vp[1,1] == 0; + result[8,8] = (zext(vptest) * cor_Qn[8,8]) + (zext(vptest) * cor_Qm[8,8]); + vptest = vp[2,1] == 0; + result[16,8] = (zext(vptest) * cor_Qn[16,8]) + (zext(vptest) * cor_Qm[16,8]); + vptest = vp[3,1] == 0; + result[24,8] = (zext(vptest) * cor_Qn[24,8]) + (zext(vptest) * cor_Qm[24,8]); + vptest = vp[4,1] == 0; + result[32,8] = (zext(vptest) * cor_Qn[32,8]) + (zext(vptest) * cor_Qm[32,8]); + vptest = vp[5,1] == 0; + result[40,8] = (zext(vptest) * cor_Qn[40,8]) + (zext(vptest) * cor_Qm[40,8]); + vptest = vp[6,1] == 0; + result[48,8] = (zext(vptest) * cor_Qn[48,8]) + (zext(vptest) * cor_Qm[48,8]); + vptest = vp[7,1] == 0; + result[56,8] = (zext(vptest) * cor_Qn[56,8]) + (zext(vptest) * cor_Qm[56,8]); + vptest = vp[8,1] == 0; + result[64,8] = (zext(vptest) * cor_Qn[64,8]) + (zext(vptest) * cor_Qm[64,8]); + vptest = vp[9,1] == 0; + result[72,8] = (zext(vptest) * cor_Qn[72,8]) + (zext(vptest) * cor_Qm[72,8]); + vptest = vp[10,1] == 0; + result[80,8] = (zext(vptest) * cor_Qn[80,8]) + (zext(vptest) * cor_Qm[80,8]); + vptest = vp[11,1] == 0; + result[88,8] = (zext(vptest) * cor_Qn[88,8]) + (zext(vptest) * cor_Qm[88,8]); + vptest = vp[12,1] == 0; + result[96,8] = (zext(vptest) * cor_Qn[96,8]) + (zext(vptest) * cor_Qm[96,8]); + vptest = vp[13,1] == 0; + result[104,8] = (zext(vptest) * cor_Qn[104,8]) + (zext(vptest) * cor_Qm[104,8]); + vptest = vp[14,1] == 0; + result[112,8] = (zext(vptest) * cor_Qn[112,8]) + (zext(vptest) * cor_Qm[112,8]); + vptest = vp[15,1] == 0; + result[120,8] = (zext(vptest) * cor_Qn[120,8]) + (zext(vptest) * cor_Qm[120,8]); + cor_Qd = result; +} + +vX: "t" is TMode=1 & (thv_c2222=0) { } +vX: "e" is TMode=1 & (thv_c2222=1) { } + +vY: "t" is TMode=1 & ((thv_c2222=0 & thv_c1515=0) | (thv_c2222=1 & thv_c1515=1)) & thv_c1314 != 0 { } +vY: "e" is TMode=1 & ((thv_c2222=0 & thv_c1515=1) | (thv_c2222=1 & thv_c1515=0)) & thv_c1314 != 0 { } +vY: "" is TMode=1 & thv_c1314=0 { } + +vZ: "t" is TMode=1 & ((thv_c2222=0 & (thv_c1515 = thv_c1414)) | (thv_c2222=1 & (thv_c1515 != thv_c1414))) & (thv_c1313=1) { } +vZ: "e" is TMode=1 & ((thv_c2222=0 & (thv_c1515 != thv_c1414)) | (thv_c2222=1 & (thv_c1515 = thv_c1414))) & (thv_c1313=1) { } +vZ: "" is TMode=1 & thv_c1313=0 { } + +VPmask: is TMode=1 & thv_c2222=1 & thv_c1315=0 { } +VPmask: vX^vY^vZ is TMode=1 & vX & vY & vZ { } + + +###### +# (DDI0553B) C2.4.429 p. 1295 VPST +# + +define pcodeop VectorPredicateSetThen; +:vpst^VPmask is $(TMODE_F) & thv_c2327=0x1c & thv_c2021=3 & thv_c1619=1 & thv_c1212=0 & thv_c0011=0xf4d & VPmask { + p0:2 = $(VPR_P0); + $(VPR_P0) = VectorPredicateSetThen(p0, VPmask); +} + + +VPsz:vpsz is thv_c2021 [ vpsz = 8 << thv_c2021; ] { local tmp:1 = vpsz; export *[const]:1 tmp; } + + +###### +# (DDI0553B) C2.4.430 p. 1296 VPT +# + +define pcodeop VectorPredicateThen; # VectorPredicateThen(param1, param2, mask, withScalar, elementType, size, conditional) +# T1 +:vpt^VPmask^".i"^VPsz VP_fc000712,cor_Qn,cor_Qm is $(TMODE_F) & thv_c2327=0x1c & thv_c1616=1 & VPsz & thv_c1212=0 & thv_c0811=0xf & thv_c0606=0 & thv_c0404=0 & thv_c0000=0 & cor_Qn & cor_Qm & VPmask & VP_fc000712 { + # TODO: implement predication + $(VPR_P0) = VectorPredicateThen(cor_Qn,cor_Qm, VPmask, 0:1, 0:1, VPsz, VP_fc000712); +} + +# T2 +:vpt^VPmask^".u"^VPsz VP_fc000712,cor_Qn,cor_Qm is $(TMODE_F) & thv_c2327=0x1c & thv_c1616=1 & VPsz & thv_c1212=0 & thv_c0811=0xf & thv_c0606=0 & thv_c0404=0 & thv_c0000=1 & cor_Qn & cor_Qm & VPmask & VP_fc000712 { + # TODO: implement predication + $(VPR_P0) = VectorPredicateThen(cor_Qn,cor_Qm, VPmask, 0:1, 1:1, VPsz, VP_fc000712); +} + +# T3 +:vpt^VPmask^".s"^VPsz VP_fc000712,cor_Qn,cor_Qm is $(TMODE_F) & thv_c2327=0x1c & thv_c1616=1 & VPsz & thv_c1212=1 & thv_c0811=0xf & thv_c0404=0 & thv_c0000=1 & cor_Qn & cor_Qm & VPmask & VP_fc000712 { + # TODO: implement predication + $(VPR_P0) = VectorPredicateThen(cor_Qn,cor_Qm, VPmask, 0:1, 2:1, VPsz, VP_fc000712); +} + +# T4 +:vpt^VPmask^".i"^VPsz VP_fc050712,cor_Qn,thv_Rm is $(TMODE_F) & thv_c2327=0x1c & thv_c1616=1 & VPsz & thv_c1212=0 & thv_c0811=0xf & thv_c0606=1 & thv_c0405=0 & thv_c0000=0 & cor_Qn & thv_Rm & VPmask & VP_fc050712 { + # TODO: implement predication + $(VPR_P0) = VectorPredicateThen(cor_Qn,thv_Rm, VPmask, 1:1, 0:1, VPsz, VP_fc050712); +} + +# T5 +:vpt^VPmask^".u"^VPsz VP_fc050712,cor_Qn,thv_Rm is $(TMODE_F) & thv_c2327=0x1c & thv_c1616=1 & VPsz & thv_c1212=0 & thv_c0811=0xf & thv_c0606=1 & thv_c0405=2 & thv_c0000=0 & cor_Qn & thv_Rm & VPmask & VP_fc050712 { + # TODO: implement predication + $(VPR_P0) = VectorPredicateThen(cor_Qn,thv_Rm, VPmask, 1:1, 1:1, VPsz, VP_fc050712); +} + +# T6 +:vpt^VPmask^".s"^VPsz VP_fc050712,cor_Qn,thv_Rm is $(TMODE_F) & thv_c2327=0x1c & thv_c1616=1 & VPsz & thv_c1212=1 & thv_c0811=0xf & thv_c0606=1 & thv_c0404=0 & thv_c0000=0 & cor_Qn & thv_Rm & VPmask & VP_fc050712 { + # TODO: implement predication + $(VPR_P0) = VectorPredicateThen(cor_Qn,thv_Rm, VPmask, 1:1, 2:1, VPsz, VP_fc050712); +} + + + +# C2.4.431 VPT (floating-point) +:vpt^VPmask^".f"^esize2828 VP_fc000712,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c2021=3 & thv_c1616=1 & thv_c0811=0xf & thv_c0606=0 & thv_c0404=0 & cor_Qn & cor_Qm & VPmask & esize2828 & VP_fc000712 { + # TODO: implement predication + $(VPR_P0) = VectorPredicateThen(cor_Qn,cor_Qm, VPmask, 0:1, 3:1, esize2828, VP_fc000712); +} + +:vpt^VPmask^".f"^esize2828 VP_fc050712,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c2021=3 & thv_c1616=1 & thv_c0811=0xf & thv_c0606=1 & thv_c0404=0 & cor_Qn & thv_Rm & VPmask & esize2828 & VP_fc050712 { + # TODO: implement predication + $(VPR_P0) = VectorPredicateThen(cor_Qn,thv_Rm, VPmask, 1:1, 3:1, esize2828, VP_fc050712); +} + +# (DDI0553B) C2.4.434 p. 1307 VQADD T2 +:vqadd.^udt^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c1616=0 & thv_c1212=0 & thv_c0811=0xf & thv_c0406=6 & udt & esize2021 & thv_Rm & cor_Qn & cor_Qd +{ + cor_Qd = VectorAdd(cor_Qn,thv_Rm,esize2021,udt); + cor_Qd = SatQ(cor_Qd, esize2021, udt); +} + +# (DDI0553B) C2.4.435 p. 1309 VQDMLADH, VQRDMLADH +rm0000: "" is thv_c0000=0 { tmp:1 = 0; export *[const]:1 tmp; } +rm0000: "r" is thv_c0000=1 { tmp:1 = 1; export *[const]:1 tmp; } +ex1212: "" is thv_c1212=0 { tmp:1 = 0; export *[const]:1 tmp; } +ex1212: "x" is thv_c1212=1 { tmp:1 = 1; export *[const]:1 tmp; } +define pcodeop vqdmladh; +:vq^rm0000^"dmladh"^ex1212^".s"^esize2021 cor_Qd,cor_Qn,cor_Qm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=0 & thv_c0811=0xe & thv_c0606=0 & thv_c0404=0 & rm0000 & ex1212 & esize2021 & cor_Qd & cor_Qn & cor_Qm { + cor_Qd = vqdmladh(cor_Qn,cor_Qm,esize2021,rm0000,ex1212); +} + +# (DDI0553B) C2.4.436 p. 1312 VQDMLAH, VQRDMLAH (vector by scalar plus vector) +rm0505: "" is thv_c0505=0 { tmp:1 = 0; export *[const]:1 tmp; } +rm0505: "r" is thv_c0505=1 { tmp:1 = 1; export *[const]:1 tmp; } +define pcodeop vqdmlah; +:vq^rm0505^"dmlah.s"^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=0 & thv_c1212=1 & thv_c0811=0xe & thv_c0606=1 & thv_c0404=0 & rm0505 & esize2021 & cor_Qd & cor_Qn & thv_Rm { + cor_Qd = vqdmlah(cor_Qn,thv_Rm,esize2021,rm0505); + +} + +# (DDI0553B) C2.4.437 p. 1314 VQDMLASH, VQRDMLASH (vector by vector plus scalar) +define pcodeop vqdmlash; +:vq^rm0505^"dmlash.s"^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_E) & thv_c2327=0x1c & thv_c1616=0 & thv_c1212=0 & thv_c0811=0xe & thv_c0606=1 & thv_c0404=0 & rm0505 & esize2021 & cor_Qd & cor_Qn & thv_Rm { + cor_Qd = vqdmlash(cor_Qn,thv_Rm,esize2021,rm0505); + +} +# (DDI0553B) C2.4.438 p. 1316 VQDMLSDH, VQRDMLSDH +define pcodeop vqdmlsdh; +:vq^rm0000^"dmlsdh"^ex1212^".s"^esize2021 cor_Qd,cor_Qn,cor_Qm is $(TMODE_F) & thv_c2327=0x1c & thv_c1616=0 & thv_c0811=0xe & thv_c0606=0 & thv_c0404=0 & rm0000 & ex1212 & esize2021 & cor_Qd & cor_Qn & cor_Qm { + cor_Qd = vqdmlsdh(cor_Qn,cor_Qm,esize2021,rm0000,ex1212); +} + +# (DDI0553B) C2.4.439 p. 1319 VQDMULH, VQRDMULH +rm2727: "" is thv_c2727=0 { tmp:1 = 0; export *[const]:1 tmp; } +rm2727: "r" is thv_c2727=1 { tmp:1 = 1; export *[const]:1 tmp; } +define pcodeop vqdmulh; +:vq^rm2727^"dmulh.s"^esize2021 cor_Qd,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2327=0x1e & thv_c1616=0 & thv_c1212=0 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0 & thv_c0000=0 & rm2727 & esize2021 & cor_Qd & cor_Qn & cor_Qm { + cor_Qd = vqdmulh(cor_Qn,cor_Qm,esize2021,rm2727); + +} + +:vq^rm2727^"dmulh.s"^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c1616=1 & thv_c1212=0 & thv_c0811=0xe & thv_c0406=6 & rm2727 & esize2021 & cor_Qd & cor_Qn & thv_Rm { + cor_Qd = vqdmulh(cor_Qn,thv_Rm,esize2021,rm2727); +} + +# C2.4.440 VQDMULL +qdsize28: val is thv_c2828 [ val = 8 << (thv_c2828+1);] { export *[const]:1 val; } +define pcodeop VectorMultiplyLong; +:vqdmull^bort1212^".s"^qdsize28 cor_Qd, cor_Qn, cor_Qm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c2021=3 & thv_c1616=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=0 & thv_c0000=0 & cor_Qm & cor_Qn & cor_Qd & qdsize28 & bort1212 { + cor_Qd = VectorMultiplyLong(cor_Qn,cor_Qm,bort1212,qdsize28); +} + +:vqdmull^bort1212^".s"^qdsize28 cor_Qd, cor_Qn, thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c2021=3 & thv_c1616=0 & thv_c0811=0xf & thv_c0406=6 & thv_Rm & cor_Qn & cor_Qd & qdsize28 & bort1212 { + cor_Qd = VectorMultiplyLong(cor_Qn,thv_Rm,bort1212,qdsize28); +} + +# C2.4.441 VQMOVN +:vqmovn^bort1212^".s"^esize1819x2 cor_Qd,cor_Qm is $(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=3 & thv_c0811=0xe & thv_c0607=0 & thv_c0404=0 & thv_c0000=1 & bort1212 & esize1819x2 & cor_Qd & cor_Qm { + cor_Qd = VectorMoveNarrow(cor_Qm,bort1212,0:1,esize1819x2); + cor_Qd = SignedSaturate(cor_Qd,esize1819x2); +} + +:vqmovn^bort1212^".u"^esize1819x2 cor_Qd,cor_Qm is $(TMODE_F) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=3 & thv_c0811=0xe & thv_c0607=0 & thv_c0404=0 & thv_c0000=1 & bort1212 & esize1819x2 & cor_Qd & cor_Qm { + cor_Qd = VectorMoveNarrow(cor_Qm,bort1212,1:1,esize1819x2); + cor_Qd = UnsignedSaturate(cor_Qd,esize1819x2); +} + +# C2.4.442 VQMOVUN +:vqmovun^bort1212^".s"^esize1819x2 cor_Qd,cor_Qm is $(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=3 & thv_c0811=0xe & thv_c0607=2 & thv_c0404=0 & thv_c0000=1 & bort1212 & esize1819x2 & cor_Qd & cor_Qm { + cor_Qd = VectorMoveNarrow(cor_Qm,bort1212,0:1,esize1819x2); + cor_Qd = UnsignedSaturate(cor_Qd,esize1819x2); +} + +# C2.4.445 VQRSHRN +esize1920x: "#"^val is thv_c2020=0 & thv_c1919=1 [ val = 16 << 0; ] { export *[const]:1 val; } +esize1920x: "#"^val is thv_c2020=1 [ val = 32 << 0; ] { export *[const]:1 val; } +cor_shImm: "#"^val is thv_c1618 [ val = thv_c1618 << 0; ] { export *[const]:1 val; } + +:vqrshrn^bort1212^".s"^esize1920x cor_Qd,cor_Qm,cor_shImm is $(TMODE_E) & thv_c2327=0x1d & thv_c2121=0 & thv_c0811=0xf & thv_c0607=1 & thv_c0404=0 & thv_c0000=1 & bort1212 & esize1920x & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorRoundShiftRightNarrow(cor_Qm,cor_shImm,bort1212,0:1,esize1920x); + cor_Qd = SignedSaturate(cor_Qd,esize1920x); +} + +:vqrshrn^bort1212^".u"^esize1920x cor_Qd,cor_Qm,cor_shImm is $(TMODE_F) & thv_c2327=0x1d & thv_c2121=0 & thv_c0811=0xf & thv_c0607=1 & thv_c0404=0 & thv_c0000=1 & bort1212 & esize1920x & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorRoundShiftRightNarrow(cor_Qm,cor_shImm,bort1212,1:1,esize1920x); + cor_Qd = UnsignedSaturate(cor_Qd,esize1920x); +} + +# C2.4.446 VQRSHRUN +:vqrshrun^bort1212^".s"^esize1920x cor_Qd,cor_Qm,cor_shImm is $(TMODE_F) & thv_c2327=0x1d & thv_c2121=0 & thv_c0811=0xf & thv_c0607=3 & thv_c0404=0 & thv_c0000=0 & bort1212 & esize1920x & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorRoundShiftRightNarrow(cor_Qm,cor_shImm,bort1212,0:1,esize1920x); + cor_Qd = UnsignedSaturate(cor_Qd,esize1920x); +} + +# C2.4.447 VQSHL, VQSHLU +esize1921: "#"^val is thv_c2021=0 & thv_c1919=1 [ val = 8 << 0; ] { export *[const]:1 val; } +esize1921: "#"^val is thv_c2121=0 & thv_c2020=1 [ val = 16 << 0; ] { export *[const]:1 val; } +esize1921: "#"^val is thv_c2121=1 [ val = 32 << 0; ] { export *[const]:1 val; } + +# T1 +:vqshl.s^esize1819 cor_Qd,thv_Rm is $(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=1 & thv_c1212=1 & thv_c0811=0xe & thv_c0407=0xe & esize1819 & cor_Qd & thv_Rm { + cor_Qd = VectorShiftLeft(cor_Qd, thv_Rm, esize1819, 0:1); + cor_Qd = SignedSaturate(cor_Qd,esize1819); +} + +:vqshl.u^esize1819 cor_Qd,thv_Rm is $(TMODE_F) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=1 & thv_c1212=1 & thv_c0811=0xe & thv_c0407=0xe & esize1819 & cor_Qd & thv_Rm { + cor_Qd = VectorShiftLeft(cor_Qd, thv_Rm, esize1819, 1:1); + cor_Qd = UnsignedSaturate(cor_Qd,esize1819); +} + +# T2 +:vqshl.s^esize1921 cor_Qd,cor_Qm,cor_shImm is $(TMODE_E) & thv_c2327=0x1f & thv_c1212=0 & thv_c0811=0x7 & thv_c0607=0x1 & thv_c0404=1 & thv_c0000=0 & esize1921 & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorShiftLeft(cor_Qm, cor_shImm, esize1921, 0:1); + cor_Qd = SignedSaturate(cor_Qd,esize1921); +} + +:vqshl.u^esize1921 cor_Qd,cor_Qm,cor_shImm is $(TMODE_F) & thv_c2327=0x1f & thv_c1212=0 & thv_c0811=0x7 & thv_c0607=0x1 & thv_c0404=1 & thv_c0000=0 & esize1921 & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorShiftLeft(cor_Qm, cor_shImm, esize1921, 1:1); + cor_Qd = UnsignedSaturate(cor_Qd,esize1921); +} + +# T3 +:vqshlu.s^esize1921 cor_Qd,cor_Qm,cor_shImm is $(TMODE_F) & thv_c2327=0x1f & thv_c1212=0 & thv_c0811=0x6 & thv_c0607=0x1 & thv_c0404=1 & thv_c0000=0 & esize1921 & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorShiftLeft(cor_Qm, cor_shImm, esize1921, 0:1); + cor_Qd = UnsignedSaturate(cor_Qd,esize1921); +} + +# T4 see F6.1.187 + +# C2.4.448 VQSHRN +:vqshrn^bort1212^".s"^esize1920x cor_Qd,cor_Qm,cor_shImm is $(TMODE_E) & thv_c2327=0x1d & thv_c2121=0 & thv_c0811=0xf & thv_c0607=1 & thv_c0404=0 & thv_c0000=0 & bort1212 & esize1920x & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorShiftRightNarrow(cor_Qm,cor_shImm,bort1212,0:1,esize1920x); + cor_Qd = SignedSaturate(cor_Qd,esize1920x); +} + +:vqrhrn^bort1212^".u"^esize1920x cor_Qd,cor_Qm,cor_shImm is $(TMODE_F) & thv_c2327=0x1d & thv_c2121=0 & thv_c0811=0xf & thv_c0607=1 & thv_c0404=0 & thv_c0000=0 & bort1212 & esize1920x & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorShiftRightNarrow(cor_Qm,cor_shImm,bort1212,1:1,esize1920x); + cor_Qd = UnsignedSaturate(cor_Qd,esize1920x); +} + +# C2.4.449 VQSHRUN +:vqshrun^bort1212^".s"^esize1920x2 cor_Qd,cor_Qm,cor_shImm is $(TMODE_E) & thv_c2327=0x1d & thv_c2121=0 & thv_c0811=0xf & thv_c0607=3 & thv_c0404=0 & thv_c0000=0 & bort1212 & esize1920x2 & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorShiftRightNarrow(cor_Qm,cor_shImm,bort1212,0:1,esize1920x2); + cor_Qd = UnsignedSaturate(cor_Qd,esize1920x2); +} + +# C2.4.450 VQSUB T2 +:vqsub.^udt^esize2021 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c1616=0 & thv_c1212=1 & thv_c0811=0xf & thv_c0406=6 & udt & esize2021 & thv_Rm & cor_Qn & cor_Qd +{ + cor_Qd = VectorSub(cor_Qn,thv_Rm,esize2021,udt); + cor_Qd = SatQ(cor_Qd, esize2021, udt); +} +@endif #VERSION_8M + +@ifdef INCLUDE_NEON ####### # The VRINT instructions round a "floating-point to an integral # floating point value of the same size", i.e. trunc. @@ -1160,191 +2478,533 @@ vmull_dt: ".p64" # 2: rounding mode # 3: boolean exact, if true then raise the Inexact exception if the # result differs from the original +vrint_simd_RM: "a" is ((TMode=0 & c0709=0b010) + | (TMode=1 & thv_c0709=0b010)) { export $(FPRounding_TIEAWAY); } -vrint_simd_RM: "a" - is ((TMode=0 & c0709=0b010) - | (TMode=1 & thv_c0709=0b010)) - { export $(FPRounding_TIEAWAY); } - -vrint_simd_RM: "m" - is ((TMode=0 & c0709=0b101) - | (TMode=1 & thv_c0709=0b101)) - { export $(FPRounding_NEGINF); } +vrint_simd_RM: "m" is ((TMode=0 & c0709=0b101) + | (TMode=1 & thv_c0709=0b101)) { export $(FPRounding_NEGINF); } -vrint_simd_RM: "n" - is ((TMode=0 & c0709=0b000) - | (TMode=1 & thv_c0709=0b000)) - { export $(FPRounding_TIEEVEN); } +vrint_simd_RM: "n" is ((TMode=0 & c0709=0b000) + | (TMode=1 & thv_c0709=0b000)) { export $(FPRounding_TIEEVEN); } -vrint_simd_RM: "p" - is ((TMode=0 & c0709=0b111) - | (TMode=1 & thv_c0709=0b111)) - { export $(FPRounding_POSINF); } +vrint_simd_RM: "p" is ((TMode=0 & c0709=0b111) + | (TMode=1 & thv_c0709=0b111)) { export $(FPRounding_POSINF); } -vrint_simd_RM: "x" - is ((TMode=0 & c0709=0b001) - | (TMode=1 & thv_c0709=0b001)) - { export $(FPRounding_TIEEVEN); } +vrint_simd_RM: "x" is ((TMode=0 & c0709=0b001) + | (TMode=1 & thv_c0709=0b001)) { export $(FPRounding_TIEEVEN); } -vrint_simd_RM: "z" - is ((TMode=0 & c0709=0b011) - | (TMode=1 & thv_c0709=0b011)) - { export $(FPRounding_ZERO); } +vrint_simd_RM: "z" is ((TMode=0 & c0709=0b011) + | (TMode=1 & thv_c0709=0b011)) { export $(FPRounding_ZERO); } # For vrintx, the exact flag is 1, and the IXF flag is set (inexact) +vrint_simd_exact: "x" is ((TMode=0 & c0709=0b001) + | (TMode=1 & thv_c0709=0b001)) { export 1:1; } -vrint_simd_exact: "x" - is ((TMode=0 & c0709=0b001) - | (TMode=1 & thv_c0709=0b001)) - { export 1:1; } +vrint_simd_exact: is ((TMode=0 & ( c0707=1 | c0808=1 | c0909=0)) + | (TMode=1 & ( thv_c0707=1 | thv_c0808=1 | thv_c0909=0))) { export 0:1; } -vrint_simd_exact: - is ((TMode=0 & ( c0707=1 | c0808=1 | c0909=0)) - | (TMode=1 & ( thv_c0707=1 | thv_c0808=1 | thv_c0909=0))) - { export 0:1; } - -vrint_simd_ixf: - is ((TMode=0 & c0709=0b001) - | (TMode=1 & thv_c0709=0b001)) - { $(FPEXC_IXF) = FPConvertInexact(); } - -vrint_simd_ixf: - is ((TMode=0 & ( c0707=1 | c0808=1 | c0909=0)) - | (TMode=1 & ( thv_c0707=1 | thv_c0808=1 | thv_c0909=0))) - { } +vrint_simd_ixf: is ((TMode=0 & c0709=0b001) + | (TMode=1 & thv_c0709=0b001)) { $(FPEXC_IXF) = FPConvertInexact(); } +vrint_simd_ixf: is ((TMode=0 & ( c0707=1 | c0808=1 | c0909=0)) + | (TMode=1 & ( thv_c0707=1 | thv_c0808=1 | thv_c0909=0))) { } # F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 0 (c0606) -:vrint^vrint_simd_RM^".f32" Dd,Dm - is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & (( c0707=0 & c0909=0) | ( c0707=1 & c0909=1) | ( c0707=1 & c0909=0)) & c0404=0 & c0606=0) +:vrint^vrint_simd_RM^".f32" Dd,Dm is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & (( c0707=0 & c0909=0) | ( c0707=1 & c0909=1) | ( c0707=1 & c0909=0)) & c0404=0 & c0606=0) | (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & ((thv_c0707=0 & thv_c0909=0) | (thv_c0707=1 & thv_c0909=1) | (thv_c0707=1 & thv_c0909=0)) & thv_c0404=0 & thv_c0606=0)) & vrint_simd_RM & vrint_simd_exact & vrint_simd_ixf & Dd & Dm { Dd = FPRoundInt(Dm, 32:1, vrint_simd_RM, 0:1); build vrint_simd_ixf; } # F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 1 (c0606) -:vrint^vrint_simd_RM^".f32" Qd,Qm - is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & c0404=0 & c0606=1) +:vrint^vrint_simd_RM^".f32" Qd,Qm is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & c0404=0 & c0606=1) | (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & thv_c0404=0 & thv_c0606=1)) & vrint_simd_RM & vrint_simd_exact & vrint_simd_ixf & Qd & Qm { Qd = FPRoundInt(Qm, 32:1, vrint_simd_RM, 0:1); build vrint_simd_ixf; } -vrint_fp_RM: "a" - is ((TMode=0 & c1617=0b00) - | (TMode=1 & thv_c1617=0b00)) - { export $(FPRounding_TIEAWAY); } +vrint_fp_RM: "a" is ((TMode=0 & c1617=0b00) + | (TMode=1 & thv_c1617=0b00)) { export $(FPRounding_TIEAWAY); } -vrint_fp_RM: "m" - is ((TMode=0 & c1617=0b11) - | (TMode=1 & thv_c1617=0b11)) - { export $(FPRounding_NEGINF); } +vrint_fp_RM: "m" is ((TMode=0 & c1617=0b11) + | (TMode=1 & thv_c1617=0b11)) { export $(FPRounding_NEGINF); } -vrint_fp_RM: "n" - is ((TMode=0 & c1617=0b01) - | (TMode=1 & thv_c1617=0b01)) - { export $(FPRounding_TIEEVEN); } +vrint_fp_RM: "n" is ((TMode=0 & c1617=0b01) + | (TMode=1 & thv_c1617=0b01)) { export $(FPRounding_TIEEVEN); } -vrint_fp_RM: "p" - is ((TMode=0 & c1617=0b10) - | (TMode=1 & thv_c1617=0b10)) - { export $(FPRounding_POSINF); } +vrint_fp_RM: "p" is ((TMode=0 & c1617=0b10) + | (TMode=1 & thv_c1617=0b10)) { export $(FPRounding_POSINF); } # F6.1.200,202,204,206 p8398,8402,8406,8410 size = 10 (c0809) -:vrint^vrint_fp_RM^".f32" Sd,Sm - is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10) +:vrint^vrint_fp_RM^".f32" Sd,Sm is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b10)) & vrint_fp_RM & Sd & Sm { Sd = FPRoundInt(Sm, 32:1, vrint_fp_RM, 0:1); } # F6.1.200,202,204,206 p8398,8402,8406,8410 size = 11 (c0809) -:vrint^vrint_fp_RM^".f64" Dd,Dm - is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11) +:vrint^vrint_fp_RM^".f64" Dd,Dm is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b11)) & vrint_fp_RM & Dd & Dm { Dd = FPRoundInt(Dm, 32:1, vrint_fp_RM, 0:1); } -vrint_rxz_RM: "r" - is ((TMode=0 & c1616=0 & c0707=0) - | (TMode=1 & thv_c1616=0 & thv_c0707=0)) - { tmp:1 = $(FPSCR_RMODE); export tmp; } +vrint_rxz_RM: "r" is ((TMode=0 & c1616=0 & c0707=0) + | (TMode=1 & thv_c1616=0 & thv_c0707=0)) { tmp:1 = $(FPSCR_RMODE); export tmp; } -vrint_rxz_RM: "x" - is ((TMode=0 & c1616=1 & c0707=0) - | (TMode=1 & thv_c1616=1 & thv_c0707=0)) - { tmp:1 = $(FPSCR_RMODE); export tmp; } +vrint_rxz_RM: "x" is ((TMode=0 & c1616=1 & c0707=0) + | (TMode=1 & thv_c1616=1 & thv_c0707=0)) { tmp:1 = $(FPSCR_RMODE); export tmp; } -vrint_rxz_RM: "z" - is ((TMode=0 & c1616=0 & c0707=1) - | (TMode=1 & thv_c1616=0 & thv_c0707=1)) - { export $(FPRounding_ZERO); } +vrint_rxz_RM: "z" is ((TMode=0 & c1616=0 & c0707=1) + | (TMode=1 & thv_c1616=0 & thv_c0707=1)) { export $(FPRounding_ZERO); } # For vrintx, the exact flag is 1, and the IXF flag is set (inexact) +vrint_rxz_exact: "x" is ((TMode=0 & c1616=1 & c0707=0) + | (TMode=1 & thv_c1616=1 & thv_c0707=0)) { export 1:1; } -vrint_rxz_exact: "x" - is ((TMode=0 & c1616=1 & c0707=0) - | (TMode=1 & thv_c1616=1 & thv_c0707=0)) - { export 1:1; } +vrint_rxz_exact: is ((TMode=0 & ( c1616=0 | c0707=1)) + | (TMode=1 & (thv_c1616=0 | thv_c0707=1))) { export 0:1; } -vrint_rxz_exact: - is ((TMode=0 & ( c1616=0 | c0707=1)) - | (TMode=1 & (thv_c1616=0 | thv_c0707=1))) - { export 0:1; } +vrint_rxz_ixf: is ((TMode=0 & c1616=1 & c0707=0) + | (TMode=1 & thv_c1616=1 & thv_c0707=0)) { $(FPEXC_IXF) = FPConvertInexact(); } -vrint_rxz_ixf: - is ((TMode=0 & c1616=1 & c0707=0) - | (TMode=1 & thv_c1616=1 & thv_c0707=0)) - { $(FPEXC_IXF) = FPConvertInexact(); } - -vrint_rxz_ixf: - is ((TMode=0 & ( c1616=0 | c0707=1)) - | (TMode=1 & (thv_c1616=0 | thv_c0707=1))) - { } +vrint_rxz_ixf: is ((TMode=0 & ( c1616=0 | c0707=1)) + | (TMode=1 & (thv_c1616=0 | thv_c0707=1))) { } # F6.1.207,209,211 p8412,8416,8420 A1 size = 10 (c0809) -:vrint^vrint_rxz_RM^COND^".f32" Sd,Sm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b10) +:vrint^vrint_rxz_RM^COND^".f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b10)) & vrint_rxz_RM & vrint_rxz_exact & vrint_rxz_ixf & COND & Sd & Sm { build COND; Sd = FPRoundInt(Sm, 32:1, vrint_rxz_RM, vrint_rxz_exact); build vrint_rxz_ixf; } # F6.1.207,209,211 p8412,8416,8420 A1 size = 11 (c0809) -:vrint^vrint_rxz_RM^COND^".f64" Dd,Dm - is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b11) +:vrint^vrint_rxz_RM^COND^".f64" Dd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b11)) & vrint_rxz_RM & vrint_rxz_exact & vrint_rxz_ixf & COND & Dd & Dm { build COND; Dd = FPRoundInt(Dm, 32:1, vrint_rxz_RM, vrint_rxz_exact); build vrint_rxz_ixf; } +@if defined(VERSION_8M) +# C2.4.463 VRMLALDAVH +define pcodeop vrmlaldavh; +:vrmlaldavh^accum0505^exch1212^"."^udt^"32" thv_RdaLo,thv_RdaHi,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2327=0x1d & thv_c1616=0 & thv_c0811=0xf & thv_c0606=0 & thv_c0404=0 & thv_c0000=0 & accum0505 & exch1212 & udt & thv_RdaLo & thv_RdaHi & cor_Qn & cor_Qm { + local accum:8 = zext(accum0505)*(zext(thv_RdaLo) + (zext(thv_RdaHi) << 32)); + local result:9 = vrmlaldavh(accum,cor_Qn,cor_Qm,udt,exch1212); + thv_RdaLo = result[8,32]; + thv_RdaHi = result[40,32]; +} + +# C2.4.464 VRMLALVH (alias of VRMLALDAVH with X == 0) +:vrmlalvh^accum0505^"."^udt^"32" thv_RdaLo,thv_RdaHi,cor_Qn,cor_Qm is $(TMODE_EorF) & thv_c2327=0x1d & thv_c1616=0 & thv_c1212=0 & thv_c0811=0xf & thv_c0606=0 & thv_c0404=0 & thv_c0000=0 & accum0505 & udt & thv_RdaLo & thv_RdaHi & cor_Qn & cor_Qm { + local accum:8 = zext(accum0505)*(zext(thv_RdaLo) + (zext(thv_RdaHi) << 32)); + local result:9 = vrmlaldavh(accum,cor_Qn,cor_Qm,udt,0:1); + thv_RdaLo = result[8,32]; + thv_RdaHi = result[40,32]; +} + +# C2.4.465 VRMLSLDAVH +define pcodeop vrmlsldavh; +:vrmlsldavh^accum0505^exch1212^".s32" thv_RdaLo,thv_RdaHi,cor_Qn,cor_Qm is $(TMODE_F) & thv_c2327=0x1d & thv_c1616=0 & thv_c0811=0xe & thv_c0606=0 & thv_c0404=0 & thv_c0000=1 & accum0505 & exch1212 & thv_RdaLo & thv_RdaHi & cor_Qn & cor_Qm { + local accum:8 = zext(accum0505)*(zext(thv_RdaLo) + (zext(thv_RdaHi) << 32)); + local result:9 = vrmlsldavh(accum,cor_Qn,cor_Qm,0:1,exch1212); + thv_RdaLo = result[8,32]; + thv_RdaHi = result[40,32]; +} + +# C2.4.466 VRSHL T2 +:vrshl.^udt^esize1819 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=3 & thv_c1212=1 & thv_c0811=0xe & thv_c0407=6 & udt & esize1819 & thv_Rm & cor_Qn & cor_Qd +{ + cor_Qd = VectorRoundShiftLeft(cor_Qn,thv_Rm,esize1819,udt); +} + +# C2.4.468 VRSHRN +:vqrshrn^bort1212^".i"^esize1920x cor_Qd,cor_Qm,cor_shImm is $(TMODE_F) & thv_c2327=0x1d & thv_c2121=0 & thv_c0811=0xf & thv_c0607=3 & thv_c0404=0 & thv_c0000=1 & bort1212 & esize1920x & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorRoundShiftRightNarrow(cor_Qm,cor_shImm,bort1212,1:1,esize1920x); +} + +# C2.4.469 VSBC +define pcodeop WholeVectorSubWithCarry; +:vsbc^carryInit1212^".i32" cor_Qd, cor_Qn, cor_Qm is $(TMODE_F) & thv_c2327=0x1c & thv_c2021=3 & thv_c1616=0 & thv_c0811=0xf & thv_c0606=0 & thv_c0404=0 & thv_c0000=0 & carryInit1212 & cor_Qd & cor_Qn & cor_Qm { + cor_Qd = WholeVectorSubWithCarry(cor_Qn, cor_Qm, carryInit1212); +} + +# C2.4.470 VSCCLRM +buildClrmDdList: Dreg is Dreg & counter=1 [ counter=0; regNum=regNum+1; ] +{ + Dreg = 0; +} +buildClrmDdList: Dreg,buildClrmDdList is Dreg & buildClrmDdList [ counter=counter-1; regNum=regNum+1; ] +{ + build Dreg; + Dreg = 0; + build buildClrmDdList; +} + +clrmDdList: "{"^buildClrmDdList^","vpr^"}" is thv_D22 & thv_c1215 & thv_c0107 & buildClrmDdList & vpr [ regNum=(thv_D22<<4)+thv_c1215-1; counter=thv_c0107; ] { } + +:vscclrm^ItCond clrmDdList is $(TMODE_E) & ItCond & thv_c2327=0x19 & thv_c2021=1 & thv_c1619=0xf & thv_c0811=0xb & thv_c0000=0 & clrmDdList { + build ItCond; + build clrmDdList; + vpr = 0; +} + +:vscclrm^ItCond "{"^vpr^"}" is $(TMODE_E) & ItCond & thv_c2327=0x19 & thv_c2021=1 & thv_c1619=0xf & thv_c0811=0xb & thv_c0007=0 & vpr { + build ItCond; + vpr = 0; +} + +# End of Single Regs list +buildClrmSdList: Sreg is Sreg & counter=1 & sdOv=0 [ counter=0; regNum=regNum+1; ] +{ + Sreg = 0; +} + +# edge case for a length multiple of 32, transition to regs +buildClrmSdList: Sreg, is Sreg & counter=0 & sdOv=1 [ regNum=regNum+1; ] +{ + Sreg = 0; +} + +# End of sregs list, transition to dregs +buildClrmSdList: Sreg, is Sreg & regNum=30 & counter > 1 [ regNum=regNum+1; ] +{ + Sreg = 0; +} + +buildClrmSdList: Sreg,buildClrmSdList is Sreg & buildClrmSdList [ counter=counter-1; regNum=regNum+1; ] +{ + build Sreg; + Sreg = 0; + build buildClrmSdList; +} + +clrmSdDdList: is thv_D22 & thv_c1215 & thv_c0007 & sdOv=0 & counter=0 {} +clrmSdDdList: buildClrmDdList is thv_D22 & thv_c1215 & thv_c0007 & buildClrmDdList [regNum=15; counter=(thv_c0007-(32-(thv_c1215 << 1)+thv_D22-1)) >> 1;] { +} + +clrmSdList: "{"^buildClrmSdList^clrmSdDdList^","vpr^"}" is thv_D22 & thv_c1215 & thv_c0007 & buildClrmSdList & clrmSdDdList & vpr [ regNum=(thv_c1215 << 1)+thv_D22-1; counter=thv_c0007; ] { + build buildClrmSdList; + build clrmSdDdList; +} + +clrmSdList: "{"^buildClrmSdList^clrmSdDdList^","vpr^"}" is thv_D22 & thv_c1215 & thv_c0507 !=0 & thv_c0007 & buildClrmSdList & clrmSdDdList & vpr [ regNum=(thv_c1215 << 1)+thv_D22-1; counter=31; sdOv=1; ] { + build buildClrmSdList; + build clrmSdDdList; +} + +:vscclrm^ItCond clrmSdList is $(TMODE_E) & ItCond & thv_c2327=0x19 & thv_c2021=1 & thv_c1619=0xf & thv_c0811=0xa & clrmSdList { + build ItCond; + build clrmSdList; + vpr = 0; +} + +:vscclrm^ItCond "{"^vpr^"}" is $(TMODE_E) & ItCond & thv_c2327=0x19 & thv_c2021=1 & thv_c1619=0xf & thv_c0811=0xa & thv_c0007=0 & vpr { + build ItCond; + vpr = 0; +} + +@endif # VERSION_8M + ####### # VSEL - -vselcond: "eq" - is ((TMode=0 & c2021=0b00) - | (TMode=1 & thv_c2021=0b00)) - { tmp:1 = ZR; export tmp; } -vselcond: "ge" - is ((TMode=0 & c2021=0b10) - | (TMode=1 & thv_c2021=0b10)) - { tmp:1 = (NG==OV); export tmp; } -vselcond: "gt" - is ((TMode=0 & c2021=0b11) - | (TMode=1 & thv_c2021=0b11)) - { tmp:1 = (!ZR && NG==OV); export tmp; } -vselcond: "vs" - is ((TMode=0 & c2021=0b01) - | (TMode=1 & thv_c2021=0b01)) - { tmp:1 = OV; export tmp; } +vselcond: "eq" is ((TMode=0 & c2021=0b00) + | (TMode=1 & thv_c2021=0b00)) { tmp:1 = ZR; export tmp; } +vselcond: "ge" is ((TMode=0 & c2021=0b10) + | (TMode=1 & thv_c2021=0b10)) { tmp:1 = (NG==OV); export tmp; } +vselcond: "gt" is ((TMode=0 & c2021=0b11) + | (TMode=1 & thv_c2021=0b11)) { tmp:1 = (!ZR && NG==OV); export tmp; } +vselcond: "vs" is ((TMode=0 & c2021=0b01) + | (TMode=1 & thv_c2021=0b01)) { tmp:1 = OV; export tmp; } # F6.1.223 p8447 A1/T1 size = 11 doubleprec (c0809) -:vsel^vselcond^".f64" Dd,Dn,Dm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) +:vsel^vselcond^".f64" Dd,Dn,Dm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11)) & vselcond & Dn & Dd & Dm { Dd = zext(vselcond != 0) * Dn + zext(vselcond == 0) * Dm; } # F6.1.223 p8447 A1/T1 size = 10 singleprec (c0809) -:vsel^vselcond".f32" Sd,Sn,Sm - is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) +:vsel^vselcond".f32" Sd,Sn,Sm is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10)) & vselcond & Sn & Sd & Sm { Sd = zext(vselcond != 0) * Sn + zext(vselcond == 0) * Sm; } +@if defined(VERSION_8M) +# C2.4.472 VSHL T2 +:vshl.^udt^esize1819 cor_Qd,cor_Qn,thv_Rm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=1 & thv_c1212=1 & thv_c0811=0xe & thv_c0407=6 & udt & esize1819 & thv_Rm & cor_Qn & cor_Qd +{ + cor_Qd = VectorShiftLeft(cor_Qn,thv_Rm,esize1819,udt); +} +# C2.4.473 VSHLC +shImm5: "#"^32 is thv_c1620=0 { tmp:1 = 32; export *[const]:1 tmp; } +shImm5: "#"^thv_c1620 is thv_c1620 { tmp:1 = thv_c1620; export *[const]:1 tmp; } + +define pcodeop VectorWholeShiftLeftCarry; +:vshlc cor_Qd,thv_Rm,shImm5 is $(TMODE_E) & thv_c2327=0x1d & thv_c2121=1 & thv_c1212=0 & thv_c0811=0xf & thv_c0407=0xc & cor_Qd & thv_Rm & shImm5 { + cor_Qd = VectorWholeShiftLeftCarry(cor_Qd,thv_Rm,shImm5); +} +# C2.4.474 VSHLL +define pcodeop VectorShiftLeftLong; +:vshll^bort1212^"."^udt^esize1920 cor_Qd,cor_Qm,cor_shImm is $(TMODE_EorF) & thv_c2327=0x1d & thv_c2121=1 & thv_c0811=0xf & thv_c0607=1 & thv_c0404=0 & thv_c0000=0 & bort1212 & udt & esize1920 & cor_Qd & cor_Qm & cor_shImm { + cor_Qd = VectorShiftLeftLong(cor_Qm,cor_shImm,bort1212,udt,esize1920); +} + +szShImm: "#"^8 is thv_c1819=0 { tmp:1 = 8; export *[const]:1 tmp; } +szShImm: "#"^16 is thv_c1819=1 { tmp:1 = 16; export *[const]:1 tmp; } + +:vshll^bort1212^"."^udt^esize1819 cor_Qd,cor_Qm,szShImm is $(TMODE_EorF) & thv_c2327=0x1c & thv_c2021=3 & thv_c1617=1 & thv_c0811=0xe & thv_c0607=0 & thv_c0404=0 & thv_c0000=1 & bort1212 & udt & esize1819 & cor_Qd & cor_Qm & szShImm { + cor_Qd = VectorShiftLeftLong(cor_Qm,szShImm,bort1212,udt,esize1819); +} + +# C2.4.476 VSHRN +:vshrn^bort1212^".i"^esize1920x2 cor_Qd, cor_Qm, cor_shImm is $(TMODE_E) & thv_c2327=0x1d & thv_c2121=0 & thv_c0811=0xf & thv_c0607=3 & thv_c0404=0 & thv_c0000=1 & bort1212 & esize1920x2 & cor_Qd & cor_Qm & cor_shImm{ + cor_Qd = VectorShiftRightNarrow(cor_Qm, cor_shImm, bort1212, esize1920x2); +} +# C2.4.480 VST2 +vst2List: {cor_Qd0,cor_Qd1} is cor_Qd0 & cor_Qd1 & thv_c0708=0 & pat0506 { + local count:1 = 0; + local ptr0 = &cor_Qd0 + 16*pat0506; + local ptr1 = &cor_Qd1 + 16*pat0506; + + *:1 mult_addr = *[register]:1 ptr0; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr0; + mult_addr = mult_addr + 1; + count = count + 1; + ptr0 = ptr0 + 1; + ptr1 = ptr1 + 1; + if count == 16 goto ; + goto ; + +} + +vst2List: {cor_Qd0,cor_Qd1} is cor_Qd0 & cor_Qd1 & thv_c0708=1 & pat0506 { + local count:1 = 0; + local ptr0 = &cor_Qd0 + 16*pat0506; + local ptr1 = &cor_Qd1 + 16*pat0506; + + *:2 mult_addr = *[register]:2 ptr0; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr1; + mult_addr = mult_addr + 2; + count = count + 1; + ptr0 = ptr0 + 2; + ptr1 = ptr1 + 2; + if count == 8 goto ; + goto ; + +} + +vst2List: {cor_Qd0,cor_Qd1} is cor_Qd0 & cor_Qd1 & thv_c0708=2 & pat0506 { + local count :1= 0; + local ptr0 = &cor_Qd0 + 16*pat0506; + local ptr1 = &cor_Qd1 + 16*pat0506; + + *:4 mult_addr = *[register]:4 ptr0; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr1; + mult_addr = mult_addr + 4; + count = count + 1; + ptr0 = ptr0 + 4; + ptr1 = ptr1 + 4; + if count == 4 goto ; + goto ; + +} + +:vst2^pat0506^"."^esize0708 vst2List, RnAddrPat^wbackRn2 is $(TMODE_F) & thv_c2327=0x19 & thv_c2020=0 & thv_c1212=1 & thv_c0911=7 & thv_c0606=0 & thv_c0004=0 & pat0506 & esize0708 & vst2List & RnAddrPat & wbackRn2 { + mult_addr = RnAddrPat; + build vst2List; + build wbackRn2; +} + +# C2.4.481 VST4 +vst4List: {cor_Qd0,cor_Qd1,cor_Qd2,cor_Qd3} is cor_Qd0 & cor_Qd1 & cor_Qd2 & cor_Qd3 & thv_c0708=0 & pat0506 { + local count:1 = 0; + local ptr0 = &cor_Qd0 + 8*pat0506; + local ptr1 = &cor_Qd1 + 8*pat0506; + local ptr2 = &cor_Qd2 + 8*pat0506; + local ptr3 = &cor_Qd3 + 8*pat0506; + + *:1 mult_addr = *[register]:1 ptr0; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr1; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr2; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr3; + mult_addr = mult_addr + 1; + count = count + 1; + ptr0 = ptr0 + 1; + ptr1 = ptr1 + 1; + ptr2 = ptr2 + 1; + ptr3 = ptr3 + 1; + if count == 16 goto ; + goto ; + +} + +vst4List: {cor_Qd0,cor_Qd1,cor_Qd2,cor_Qd3} is cor_Qd0 & cor_Qd1 & cor_Qd2 & cor_Qd3 & thv_c0708=1 & pat0506 { + local count:1 = 0; + local ptr0 = &cor_Qd0 + 8*pat0506; + local ptr1 = &cor_Qd1 + 8*pat0506; + local ptr2 = &cor_Qd2 + 8*pat0506; + local ptr3 = &cor_Qd3 + 8*pat0506; + + *:2 mult_addr = *[register]:2 ptr0; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr1; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr2; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr3; + mult_addr = mult_addr + 2; + count = count + 1; + ptr0 = ptr0 + 2; + ptr1 = ptr1 + 2; + ptr2 = ptr2 + 2; + ptr3 = ptr3 + 2; + if count == 8 goto ; + goto ; + +} + +vst4List: {cor_Qd0,cor_Qd1,cor_Qd2,cor_Qd3} is cor_Qd0 & cor_Qd1 & cor_Qd2 & cor_Qd3 & thv_c0708=2 & pat0506 { + local count :1= 0; + local ptr0 = &cor_Qd0 + 8*pat0506; + local ptr1 = &cor_Qd1 + 8*pat0506; + local ptr2 = &cor_Qd2 + 8*pat0506; + local ptr3 = &cor_Qd3 + 8*pat0506; + + *:4 mult_addr = *[register]:4 ptr0; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr1; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr2; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr3; + mult_addr = mult_addr + 4; + count = count + 1; + ptr0 = ptr0 + 4; + ptr1 = ptr1 + 4; + ptr2 = ptr2 + 4; + ptr3 = ptr3 + 4; + if count == 4 goto ; + goto ; + +} + +:vst4^pat0506^"."^esize0708 vst4List, RnAddrPat^wbackRn4 is $(TMODE_F) & thv_c2327=0x19 & thv_c2020=0 & thv_c1212=1 & thv_c0911=7 & thv_Q6=0 & thv_c0004=1 & esize0708 & pat0506 & RnAddrPat & vst4List & wbackRn4 { + mult_addr = RnAddrPat; + build vst4List; + build wbackRn4; +} +# C2.4.484 VSTR (System Register) +vstrSimm: "#"^val is thv_c2323=0 & cor_imm7 [ val = cor_imm7 * 4; ] { export *[const]:4 val; } +vstrSimm: "#"^val is thv_c2323=1 & cor_imm7 [ val = cor_imm7 * (-4); ] { export *[const]:4 val; } + +vstrRnc: "["^thv_Rn^"]" is thv_Rn & thv_c2424=1 & cor_imm7=0 { ptr:4 = thv_Rn; export ptr; } +vstrRnc: "["^thv_Rn,vstrSimm^"]" is thv_Rn & thv_c2424=1 & thv_c2121=0 & vstrSimm { ptr:4 = thv_Rn + vstrSimm; export ptr; } +vstrRnc: "["^thv_Rn,vstrSimm^"]!" is thv_Rn & thv_c2424=1 & thv_c2121=1 & vstrSimm { ptr:4 = thv_Rn + vstrSimm; thv_Rn = ptr; export ptr; } +vstrRnc: "["^thv_Rn^"]",vstrSimm is thv_Rn & thv_c2424=0 & thv_c2121=1 & vstrSimm { ptr:4 = thv_Rn; thv_Rn = thv_Rn + vstrSimm; export ptr; } + +:vstr fpscr, vstrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=0 & thv_c1212=0 & thv_c0711=0x1f & vstrRnc & thv_c2222=0 & thv_c1315=1 & fpscr { + *:4 vstrRnc = fpscr; +} + +:vstr "fpscr_nzcvqc", vstrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=0 & thv_c1212=0 & thv_c0711=0x1f & vstrRnc & thv_c2222=0 & thv_c1315=2 { + local result:4 = 0; + result[27,5] = fpscr[27,5]; + *:4 vstrRnc = result; +} + +:vstr vpr, vstrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=0 & thv_c1212=0 & thv_c0711=0x1f & vstrRnc & thv_c2222=1 & thv_c1315=4 & vpr { + *:4 vstrRnc = vpr; +} + +:vstr "p0", vstrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=0 & thv_c1212=0 & thv_c0711=0x1f & vstrRnc & thv_c2222=1 & thv_c1315=5 { + local result:2 = vpr[0,16]; + *:4 vstrRnc = zext(result); +} + +:vstr "fpcxt_ns", vstrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=0 & thv_c1212=0 & thv_c0711=0x1f & vstrRnc & thv_c2222=1 & thv_c1315=6 { + *:4 vstrRnc = fpscr; +} + +:vstr "fpcxt_s", vstrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=0 & thv_c1212=0 & thv_c0711=0x1f & vstrRnc & thv_c2222=1 & thv_c1315=7 { + *:4 vstrRnc = fpscr; +} +# C2.4.485 VSTRB, VSTRH, VSTRW +define pcodeop VectorStoreRegister; +:vstrb.^udt^esize0708 cor_Qd,vldrRnc is $(TMODE_EorF) & thv_c2527=6 & thv_c2222=0 & thv_c1920=0 & thv_c1212=0 & thv_c0911=7 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorStoreRegister(vldrRnc, 0:1, esize0708, udt); +} + +:vstrh.^udt^esize0708 cor_Qd,vldrRnc is $(TMODE_EorF) & thv_c2527=6 & thv_c2222=0 & thv_c1920=1 & thv_c1212=0 & thv_c0911=7 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorStoreRegister(vldrRnc, 1:1, esize0708, udt); +} + +:vstrb.8 cor_Qd,vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=0 & thv_c1212=1 & thv_c0811=0xe & thv_c0707=0 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorStoreRegister(vldrRnc, 0:1, esize0708, udt); +} + +:vstrh.16 cor_Qd,vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=0 & thv_c1212=1 & thv_c0811=0xe & thv_c0707=1 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorStoreRegister(vldrRnc, 1:1, esize0708, udt); +} + +:vstrw.32 cor_Qd,vldrRnc is $(TMODE_E) & thv_c2527=6 & thv_c2020=0 & thv_c1212=1 & thv_c0811=0xf & thv_c0707=0 & cor_Qd & vldrRnc & udt & esize0708 { + cor_Qd = VectorStoreRegister(vldrRnc, 2:1, esize0708, udt); +} +# C2.4.486 VSTRB, VSTRH, VSTRW, VSTRD (vector) +define pcodeop VectorScatterStore; # VectorScatterStore(base address, element vector, offset vector, immediate, shift, esize, msize, signed) +:vldrb.^esize0708 cor_Qd,vldrRnQm is $(TMODE_E) & thv_c2327=0x19 & thv_c2021=0 & thv_c1212=0 & thv_c0911=7 & thv_Q6=0 & thv_c0404=0 & thv_c0000 & esize0708 & cor_Qd & vldrRnQm & thv_Rn & cor_Qm { + VectorScatterStore(thv_Rn, cor_Qd, cor_Qm, 0:1, 0:1, esize0708, vldrRnQm); +} + +:vldrh.^esize0708 cor_Qd,vldrRnQm is $(TMODE_E) & thv_c2327=0x19 & thv_c2021=0 & thv_c1212=0 & thv_c0911=7 & thv_Q6=0 & thv_c0404=1 & thv_c0000 & esize0708 & cor_Qd & vldrRnQm & thv_Rn & cor_Qm { + VectorScatterStore(thv_Rn, cor_Qd, cor_Qm, 0:1, thv_c0000:1, esize0708, vldrRnQm); +} + +:vldrw.^esize0708 cor_Qd,vldrRnQm is $(TMODE_E) & thv_c2327=0x19 & thv_c2021=0 & thv_c1212=0 & thv_c0911=7 & thv_Q6=1 & thv_c0404=0 & thv_c0000 & esize0708 & cor_Qd & vldrRnQm & thv_Rn & cor_Qm { + VectorScatterStore(thv_Rn, cor_Qd, cor_Qm, 0:1, thv_c0000:1, esize0708, vldrRnQm); +} + +:vldrd.^esize0708 cor_Qd,vldrRnQm is $(TMODE_E) & thv_c2327=0x19 & thv_c2021=0 & thv_c1212=0 & thv_c0911=7 & thv_Q6=1 & thv_c0404=1 & thv_c0000 & esize0708 & cor_Qd & vldrRnQm & thv_Rn & cor_Qm { + VectorScatterStore(thv_Rn, cor_Qd, cor_Qm, 0:1, thv_c0000:1, esize0708, vldrRnQm); +} + + +:vldrw.32 cor_Qd,vldrQmImm is $(TMODE_F) & thv_c2327=0x1d & thv_c2020=0 & thv_c1616=0 & thv_c1212=1 & thv_c0811=0xe & cor_Qd & vldrQmImm & vldrSimm & cor_Qn { + VectorScatterStore(0:4, cor_Qd, cor_Qn, vldrSimm, 0:1, 2:1, 2:1, vldrQmImm); +} + +:vldrd.64 cor_Qd,vldrQmImm is $(TMODE_F) & thv_c2327=0x1d & thv_c2020=0 & thv_c1616=0 & thv_c1212=1 & thv_c0811=0xf & cor_Qd & vldrQmImm & vldrSimm & cor_Qn { + VectorScatterStore(0:4, cor_Qd, cor_Qn, vldrSimm, 0:1, 3:1, 3:1, vldrQmImm); +} + +# C2.4.492 WLS, DLS, WLSTP, DLSTP +wloopEndAddr: reloc is cor_immB & thv_c1111 [ reloc = inst_next + (cor_immB <<2) | (thv_c1111 << 1); ] { export *[ram]:4 reloc; } + +:wls lr,thv_Rn,wloopEndAddr is $(TMODE_F) & thv_c2427=0 & thv_c2023=4 & thv_c1215=0xc & thv_c0000=1 & lr & thv_Rn & wloopEndAddr { + local count = thv_Rn; + if (count != 0) goto ; + goto wloopEndAddr; + + lr = count; +} + +:dls lr, thv_Rn is $(TMODE_F) & thv_c2427=0 & thv_c2023=4 & thv_c1215=0xe & thv_c0811=0 & thv_c0407=0 & thv_c0003=1 & lr & thv_Rn { + lr = thv_Rn; +} + +:wlstp.^esize2021 lr,thv_Rn,wloopEndAddr is $(TMODE_F) & thv_c2427=0 & thv_c2223=0 & thv_c1215=0xc & thv_c0000=1 & esize2021 & lr & thv_Rn & wloopEndAddr { + local count = thv_Rn; + if (count != 0) goto ; + goto wloopEndAddr; + + fpscr[16,3] = esize2021; + lr = count; +} + +:dlstp.^esize2021 lr, thv_Rn is $(TMODE_F) & thv_c2427=0 & thv_c2223=0 & thv_c1215=0xe & thv_c0811=0 & thv_c0407=0 & thv_c0003=1 & esize2021 & lr & thv_Rn { + fpscr[16,3] = esize2021; + lr = thv_Rn; +} + +@endif # VERSION_8M + @endif # INCLUDE_NEON diff --git a/pypcode/processors/Atmel/data/languages/avr32a_instruction_flow.sinc b/pypcode/processors/Atmel/data/languages/avr32a_instruction_flow.sinc index 23970365..bcfa9a24 100644 --- a/pypcode/processors/Atmel/data/languages/avr32a_instruction_flow.sinc +++ b/pypcode/processors/Atmel/data/languages/avr32a_instruction_flow.sinc @@ -154,8 +154,9 @@ RJMPdisp: disp is disp4_8 & sdisp0_2 # 0101 1101 0001 dddd :ICALL rd0 is op4_12=0x5d1 & rd0 { + tmp:4 = rd0; LR = inst_next; - call [rd0]; + call [tmp]; } #--------------------------------------------------------------------- diff --git a/pypcode/processors/CR16/data/languages/CR16C.sinc b/pypcode/processors/CR16/data/languages/CR16C.sinc index f70a4574..51a23c4f 100644 --- a/pypcode/processors/CR16/data/languages/CR16C.sinc +++ b/pypcode/processors/CR16/data/languages/CR16C.sinc @@ -1240,20 +1240,14 @@ macro do_lshb(count, dest) { *:2 tmp = val | mask; # clear bit, store } -# TBIT - test bit +# TBIT - test bit in register :TBIT imm4a, src1 is hi=0x06 & imm4a & src1 { - tmp:4 = zext(src1); - val:2 = *:2 tmp; # load dst operand mask:2 = 1 << imm4a; - bit:2 = (val & mask) >> imm4a; - $(F) = bit:1; # save bit + $(F) = (src1 & mask) != 0; } :TBIT src, src1 is hi=0x07 & src & src1 { - tmp:4 = zext(src1); - val:2 = *:2 tmp; # load dst operand mask:2 = 1 << src; - bit:2 = (val & mask) >> src; - $(F) = bit:1; # save bit + $(F) = (src1 & mask) != 0; } # TBITB - test bit in low-order byte diff --git a/pypcode/processors/Hexagon/data/languages/Hexagon.opinion b/pypcode/processors/Hexagon/data/languages/Hexagon.opinion new file mode 100755 index 00000000..ba3f687b --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/Hexagon.opinion @@ -0,0 +1,5 @@ + + + + + diff --git a/pypcode/processors/Hexagon/data/languages/hexagon.cspec b/pypcode/processors/Hexagon/data/languages/hexagon.cspec new file mode 100755 index 00000000..91e10ecf --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon.cspec @@ -0,0 +1,154 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pypcode/processors/Hexagon/data/languages/hexagon.dwarf b/pypcode/processors/Hexagon/data/languages/hexagon.dwarf new file mode 100644 index 00000000..7420ce37 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon.dwarf @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/Hexagon/data/languages/hexagon.ldefs b/pypcode/processors/Hexagon/data/languages/hexagon.ldefs new file mode 100755 index 00000000..0c21cea5 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon.ldefs @@ -0,0 +1,17 @@ + + + + + Qualcomm Hexagon V69 processor (QDSP6) 32-bit little-endian + + + + + diff --git a/pypcode/processors/Hexagon/data/languages/hexagon.pspec b/pypcode/processors/Hexagon/data/languages/hexagon.pspec new file mode 100755 index 00000000..a2ad8e87 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon.pspec @@ -0,0 +1,439 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pypcode/processors/Hexagon/data/languages/hexagon.sinc b/pypcode/processors/Hexagon/data/languages/hexagon.sinc new file mode 100755 index 00000000..de29be04 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon.sinc @@ -0,0 +1,17384 @@ +# Qualcomm Hexagon (V73) General Instruction Set + +# +# Custom pcode-op +# +define pcodeop lock; +define pcodeop unlock; +define pcodeop lock_valid; +define pcodeop bitReverse; +define pcodeop circularAdd; +define pcodeop countTrailingZeros; +define pcodeop countTrailingOnes; +define pcodeop countLeadingBits; +define pcodeop saturate8; +define pcodeop saturate16; +define pcodeop saturate32; +define pcodeop usaturate8; +define pcodeop usaturate16; +define pcodeop usaturate32; + +# roundArithmetic(v,n) (n==0) ? (v) : round( v + 2**(n-1) )) >> n +# Arithmentic rounding of v to any bit location n (only least significant 5-bits of n are used) +# round: .5 is rounded up +define pcodeop roundArithmetic; +define pcodeop roundArithmeticSaturate; + +# roundConvergent(v,n) (n==0) ? v : convround(v + 2**(n-1)) >> n +# Convergent rounding of v to any bit location n (only least significant 5-bits of n are used) +# convround: .5 is rounded towards even +define pcodeop roundConvergent; +define pcodeop roundConvergentSaturate; + +define pcodeop reciprocal; +define pcodeop reciprocalAdjust; +define pcodeop multiplyAddScale; + +# +# Macros +# + +macro addSat16(dest, src1, src2) { + result:4 = sext(src1) + sext(src2); + dest = saturate16(result); +} + +macro adduSat16(dest, src1, src2) { + result:4 = zext(src1) + zext(src2); + dest = usaturate16(result); +} + +macro subSat16(dest, src1, src2) { + result:4 = sext(src1) - sext(src2); + dest = saturate16(result); +} + +macro subuSat16(dest, src1, src2) { + result:4 = zext(src1) - zext(src2); + dest = usaturate16(result); +} + +macro addSat32(dest, src1, src2) { + result:8 = sext(src1) + sext(src2); + dest = saturate32(result); +} + +macro adduSat32(dest, src1, src2) { + result:8 = zext(src1) + zext(src2); + dest = usaturate32(result); +} + +macro subSat32(dest, src1, src2) { + result:8 = sext(src1) - sext(src2); + dest = saturate32(result); +} + +macro subuSat32(dest, src1, src2) { + result:8 = zext(src1) - zext(src2); + dest = usaturate32(result); +} + +# +# Sub-constructors +# + +Zero: "#"^val is epsilon [ val = 0; ] { export *[const]:1 val; } +MinusOne: "#"^val is epsilon [ val = -1; ] { export *[const]:1 val; } +One: "#"^val is epsilon [ val = 1; ] { export *[const]:1 val; } +FF: "#"^val is epsilon [ val = 0xff; ] { export *[const]:1 val; } + +PCval: val is epsilon [ val = inst_start - (4 * packetOffset); ] { export *[const]:4 val; } +PacketPC: PC is PC & PCval { export PCval; } + +# Source control register (handle PC special) +Cs5: cs5 is cs5 { export cs5; } # Source use only +Cs5: PacketPC is cs5=9 & PacketPC { export PacketPC; } + +# Destination control register (PC assignment not currently handled) +Cd5: cd5 is cd5 & cd5_ { + export cd5_; + <> + cd5 = cd5_; +} +Cdd5: cdd5 is cdd5 & cdd5_ { + export cdd5_; + <> + cdd5 = cdd5_; +} + +# Destination guest register (shadow not currently supported) +Gd5: gd5 is gd5 { export gd5; } +Gdd5: gdd5 is gdd5 { export gdd5; } + +# Destination supervisor register (shadow not currently supported) +Sd6: sd6 is sd6 { export sd6; } +Sdd6: sdd6 is sdd6 { export sdd6; } + +# Destination register (displays reg but exports shadow-reg) +# NOTE: Unconditional auto-commit use only +Rdd5: rdd5 is rdd5 & rdd5_ { # facilitates Nreg use in packet + export rdd5_; + <> + rdd5 = rdd5_; +} +Rd5: rd5 is rd5 & rd5_ & SetNRegRd5 & cond=0 { # facilitates Nreg use in packet + export rd5_; + <> + rd5 = rd5_; +} +Rxx5: rxx5 is rxx5 & rxx5_ { # facilitates Nreg use in packet + export rxx5_; + <> + rxx5 = rxx5_; +} +Rx5: rx5 is rx5 & rx5_ & SetNRegRx5 { # facilitates Nreg use in packet + export rx5_; + <> + rx5 = rx5_; +} +Rd0812: rd0812 is rd0812 & rd0812_ & SetNRegRd0812 { # facilitates Nreg use in packet + export rd0812_; + <> + rd0812 = rd0812_; +} +Rdd0812: rdd0812 is rdd0812 & rdd0812_ & SetNRegRd0812 { # facilitates Nreg use in packet + export rdd0812_; + <> + rdd0812 = rdd0812_; +} +Rx5H: rx5H is rx5H & rx5H_ { # TODO: Do we need to set nreg ? + export rx5H_; + <> + rx5H = rx5H_; +} +Rx5L: rx5L is rx5L & rx5L_ { # TODO: Do we need to set nreg ? + export rx5L_; + <> + rx5L = rx5L_; +} +Rd0811: rd0811 is rd0811 & rd0811_ { # TODO: Do we need to set nreg ? + export rd0811_; + <> + rd0811 = rd0811_; +} +Rd1619: rd1619 is rd1619 & rd1619_ { # TODO: Do we need to set nreg ? + export rd1619_; + <> + rd1619 = rd1619_; +} + +Rdd3l: rdd3l is rdd3l & rdd3l_ { + export rdd3l_; + <> + rdd3l = rdd3l_; +} +Rdd3r: rdd3r is rdd3r & rdd3r_ { + export rdd3r_; + <> + rdd3r = rdd3r_; +} +Rd4l: rd4l is rd4l & rd4l_ { + export rd4l_; + <> + rd4l = rd4l_; +} +Rd4r: rd4r is rd4r & rd4r_ { + export rd4r_; + <> + rd4r = rd4r_; +} + +# Source registers + +Ru5HL21: ru5L is op21=0 & ru5L { export ru5L; } +Ru5HL21: ru5H is op21=1 & ru5H { export ru5H; } + +Rt5HL21: rt5L is op21=0 & rt5L { export rt5L; } +Rt5HL21: rt5H is op21=1 & rt5H { export rt5H; } + +Rt5HL06: rt5L is op6=0 & rt5L { export rt5L; } +Rt5HL06: rt5H is op6=1 & rt5H { export rt5H; } + +Rt5HL05: rt5L is op5=0 & rt5L { export rt5L; } +Rt5HL05: rt5H is op5=1 & rt5H { export rt5H; } + +Rs5HL06: rs5L is op6=0 & rs5L { export rs5L; } +Rs5HL06: rs5H is op6=1 & rs5H { export rs5H; } + +Rs5HL05: rs5L is op5=0 & rs5L { export rs5L; } +Rs5HL05: rs5H is op5=1 & rs5H { export rs5H; } + +OnesCompRs5: "~"^rs5 is rs5 { tmp:4 = ~rs5; export tmp; } +OnesCompRss5: "~"^rss5 is rss5 { tmp:8 = ~rss5; export tmp; } + +OnesCompRt5: "~"^rt5 is rt5 { tmp:4 = ~rt5; export tmp; } + +define pcodeop conjugate; +Rt5Conjugate: rt5^"*" is rt5 { tmp:4 = conjugate(rt5); export tmp; } +Rtt5Conjugate: rtt5^"*" is rtt5 { tmp:8 = conjugate(rtt5); export tmp; } + +# +# P0 - P3 register modes +# +# NOTE: A predicate destination register must be auto-AND'd with it previous .new state +# which is initially set to 0xff to allow for this. +# + +# Destination +# NOTE: Unconditional commit use only +Pd2: pu0001 is pu0001 & pu0001_ { + export pu0001_; + <> + pu0001 = pu0001_; +} +Pd25: pu25 is pu25 & pu25_ { + export pu25_; + <> + pu25 = pu25_; +} +Pd12: pu12 is pu12 & pu12_ { + export pu12_; + <> + pu12 = pu12_; +} +P0dest: P0 is P0 { + export P0.new; + <> + P0 = P0.new; +} + +Pd0506: pu0506 is pu0506 & pu0506_ { + export pu0506_; + <> + pu0506 = pu0506_; +} + +NotPs2: "!"^pu1617 is pu1617 { tmp:1 = !pu1617; export tmp; } + +# Relative Destination Address (relative to start of packet) +# NOTE: All relative addresses support immext (relative offset is not shifted when immext is present and first two bits always cleared) +# NOTE: Use of immext only appends 6 low-order bits to immext, although resulting bit-0 and bit-1 are cleared/ignored by hardware. +@define PKT_START "inst_start - (4 * packetOffset)" + +RelDest22x: val is s1624 & i0113 & immexted=0 [ val = (((s1624 << 13) | i0113) << 2) + $(PKT_START); ] { export *[ram]:4 val; } +RelDest22x: val is i0306 & immexted=1 [ val = ((simmext << 6) | (i0306 << 2)) + $(PKT_START); ] { export *[ram]:4 val; } + +@define r15_2_val "((s2223 << 13) | (i1620 << 8) | (i13 << 7) | i0107)" +RelDest15x: val is i0107 & i13 & i1620 & s2223 & immexted=0 [ val = ($(r15_2_val) << 2) + $(PKT_START); ] { export *[ram]:4 val; } +RelDest15x: val is i0306 & immexted=1 [ val = ((simmext << 6) | (i0306 << 2)) + $(PKT_START); ] { export *[ram]:4 val; } + +@define r13_2_val "((s21 << 12) | (op13 << 11) | i0111)" +RelDest13: val is i0111 & op13 & s21 [ val = ($(r13_2_val) << 2) + $(PKT_START); ] { export *[ram]:4 val; } + +RelDest9x: val is i0107 & s2021 & immexted=0 [ val = (((s2021 << 7) | i0107) << 2) + $(PKT_START); ] { export *[ram]:4 val; } +RelDest9x: val is i0306 & immexted=1 [ val = ((simmext << 6) | (i0306 << 2)) + $(PKT_START); ] { export *[ram]:4 val; } + +# +# Non-extended Immediates +# + +Simm8_0813: "#"^s0813 is s0813 { export *[const]:1 s0813; } +Simm8_0512: "#"^s0512 is s0512 { export *[const]:1 s0512; } +Simm8_0410: "#"^s0410 is s0410 { export *[const]:1 s0410; } +Simm8_1620_05: "#"^val is s1620 & i5 [ val = (s1620 << 1) | i5; ] { export *[const]:1 val; } +Simm8_1622_13: "#"^val is s1622 & i13 [ val = (s1622 << 1) | i13; ] { export *[const]:1 val; } + +Uimm16_21_0513: "#"^val is op21 & i0513 [ val = (op21 << 9) | i0513; ] { export *[const]:2 val; } +Uimm16_2223_0013: "#"^val is i2223 & i0013 [ val = (i2223 << 14) | i0013; ] { export *[const]:2 val; } + +Uimm10_1617_0812_0204: "#"^val is i1617 & i0812 & i0204 [ val = (i1617 << 8) | (i0812 << 3) | i0204; ] { export *[const]:2 val; } + + +Uimm8_2123_0507: "#"^val is i2123 & i0507 [ val = (i2123 << 3) | i0507; ] { export *[const]:1 val; } +Uimm8_2122_0507: "#"^val is i2122 & i0507 [ val = (i2122 << 3) | i0507; ] { export *[const]:1 val; } + +Uimm8_23_0004: "#"^val is op23 & i0004 [ val = (op23 << 5) | i0004; ] { export *[const]:1 val; } +Uimm8_21_0507: "#"^val is op21 & i0507 [ val = (op21 << 3) | i0507; ] { export *[const]:1 val; } +Uimm8_0812_0204: "#"^val is i0812 & i0204 [ val = (i0812 << 3) | i0204; ] { export *[const]:1 val; } +Uimm8_0813: "#"^i0813 is i0813 { export *[const]:1 i0813; } +Uimm8_0812: "#"^i0812 is i0812 { export *[const]:1 i0812; } +Uimm8_0811: "#"^i0811 is i0811 { export *[const]:1 i0811; } +Uimm8_0512: "#"^i0512 is i0512 { export *[const]:1 i0512; } +Uimm8_0511: "#"^i0511 is i0511 { export *[const]:1 i0511; } +Uimm8_0509: "#"^i0509 is i0509 { export *[const]:1 i0509; } +Uimm8_0507: "#"^i0507 is i0507 { export *[const]:1 i0507; } +Uimm8_0409: "#"^i0409 is i0409 { export *[const]:1 i0409; } +Uimm8_0004: "#"^i0004 is i0004 { export *[const]:1 i0004; } +Uimm8_0001: "#"^i0001 is i0001 { export *[const]:1 i0001; } + +Uimm3_0507: "#"^i0507 is i0507 { export *[const]:1 i0507; } + +Uimm2_13_07: "#"^val is op13 & op7 [ val = (op13 << 1) | op7; ] { export *[const]:1 val; } +Uimm2_13_06: "#"^val is op13 & op6 [ val = (op13 << 1) | op6; ] { export *[const]:1 val; } +Uimm2_13_05: "#"^val is op13 & op5 [ val = (op13 << 1) | op5; ] { export *[const]:1 val; } +Uimm2_1617: "#"^op1617 is op1617 { export *[const]:1 op1617; } +Uimm2_2122: "#"^op2122 is op2122 { export *[const]:1 op2122; } +Uimm2_1920: "#"^op1920 is op1920 { export *[const]:1 op1920; } +Uimm2_0304: "#"^i0304 is i0304 { export *[const]:1 i0304; } +Uimm2_0506: "#"^i0506 is i0506 { export *[const]:1 i0506; } + +Uimm1_24: "#"^i24 is i24 { export *[const]:1 i24; } +Uimm1_08: "#"^i8 is i8 { export *[const]:1 i8; } +Uimm1_05: "#"^i5 is i5 { export *[const]:1 i5; } + +# +# Non-extended Immediates with shift factor +# +Uimm8_0408_shift3: "#"^val is i0408 [ val = i0408 << 3; ] { export *[const]:1 val; } +Uimm8_0409_shift2: "#"^val is i0409 [ val = i0409 << 2; ] { export *[const]:1 val; } +Uimm16_0010_shift3: "#"^val is i0010 [ val = i0010 << 3; ] { export *[const]:2 val; } +Uimm8_2025_shift2: "#"^val is i2025 [ val = i2025 << 2; ] { export *[const]:1 val; } +Uimm32_2122_13_0507_shift2: "#"^val is i2122 & i13 & i0507 [ val = ((i2122 << 4) | (i13 << 3) | i0507) << 2; ] { export *[const]:4 val; } + + +# +# Extended Immediates (see immext) +# Double-# indicates use of extended immediate value + +Simm32_13_0006x: "#"^val is s13 & i0006 & immexted=0 [ val = (s13 << 7) | i0006; ] { export *[const]:4 val; } +Simm32_13_0006x: "##"^val is s13 & i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:4 val; } # u32 + +Simm32_13_0004x: "#"^val is s13 & i0004 & immexted=0 [ val = (s13 << 5) | i0004; ] { export *[const]:4 val; } +Simm32_13_0004x: "##"^val is op13 & i0004 & immexted=1 [ val = (immext << 6) | (op13 << 5) | i0004; ] { export *[const]:4 val; } # u32 + +Simm32_0512x: "#"^s0512 is s0512 & immexted=0 { export *[const]:4 s0512; } +Simm32_0512x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32 + +Simm32_2127_0513x: "#"^val is s2127 & i0513 & immexted=0 [ val = (s2127 << 9) | i0513; ] { export *[const]:4 val; } +Simm32_2127_0513x: "##"^val is i0510 & immexted=1 [ val = (simmext << 6) | i0510; ] { export *[const]:4 val; } # s32 + +Simm32_2223_1620_0513x: "#"^val is s2223 & i1620 & i0513 & immexted=0 [ val = (s2223 << 14) | (i1620 << 9) | i0513; ] { export *[const]:4 val; } +Simm32_2223_1620_0513x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32 + +Simm32_2122_13_0507x: "#"^val is s2122 & i13 & i0507 & immexted=0 [ val = (s2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; } +Simm32_2122_13_0507x: "##"^val is i2122 & i13 & i0507 & immexted=1 [ val = (immext << 6) | (i2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; } # u32 + +Simm32_21_0513x: "#"^val is s21 & i0513 & immexted=0 [ val = (s21 << 9) | i0513; ] { export *[const]:4 val; } +Simm32_21_0513x: "##"^val is s21 & i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32 + +Simm32_1619_0512x: "#"^val is s1619 & i0512 & immexted=0 [ val = (s1619 << 8) | i0512; ] { export *[const]:4 val; } +Simm32_1619_0512x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32 + +Simm32_2026x: "#"^s2026 is s2026 & immexted=0 { export *[const]:4 s2026; } +Simm32_2026x: "##"^val is i2025 & immexted=1 [ val = (simmext << 6) | i2025; ] { export *[const]:4 val; } # s32 + +Uimm32_2123_13_0507_03x: "#"^val is i2123 & i13 & i0507 & i3 & immexted=0 [ val = (i2123 << 5) | (i13 << 4) | (i0507 << 1) | i3; ] { export *[const]:4 val; } +Uimm32_2123_13_0507_03x: "##"^val is op21 & i13 & i0507 & i3 & immexted=1 [ val = (immext << 6) | (op21 << 5) | (i13 << 4) | (i0507 << 1) | i3; ] { export *[const]:4 val; } + +Uimm32_2122_13_0507x: "#"^val is i2122 & i13 & i0507 & immexted=0 [ val = (i2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; } +Uimm32_2122_13_0507x: "##"^val is i2122 & i13 & i0507 & immexted=1 [ val = (immext << 6) | (i2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; } + +Uimm32_1620_13x: "#"^val is i1620 & i13 & immexted=0 [ val = (i1620 << 1) | i13; ] { export *[const]:4 val; } +Uimm32_1620_13x: "##"^val is i1620 & i13 & immexted=1 [ val = (immext << 6) | (i1620 << 1) | i13; ] { export *[const]:4 val; } + +Uimm32_1620_08x: "#"^val is i1620 & i8 & immexted=0 [ val = (i1620 << 1) | i8; ] { export *[const]:4 val; } +Uimm32_1620_08x: "##"^val is i1620 & i8 & immexted=1 [ val = (immext << 6) | (i1620 << 1) | i8; ] { export *[const]:4 val; } + +Uimm32_1617_0306x: "#"^val is i1617 & i0306 & immexted=0 [ val = (i1617 << 4) | i0306; ] { export *[const]:4 val; } +Uimm32_1617_0306x: "##"^val is i1617 & i0306 & immexted=1 [ val = (immext << 6) | (i1617 << 4) | i0306; ] { export *[const]:4 val; } + +Uimm32_0811_0506x: "#"^val is i0811 & i0506 & immexted=0 [ val = (i0811 << 2) | i0506; ] { export *[const]:4 val; } +Uimm32_0811_0506x: "##"^val is i0811 & i0506 & immexted=1 [ val = (immext << 6) | (i0811 << 2) | i0506; ] { export *[const]:4 val; } + +Uimm32_0712x: "#"^i0712 is i0712 & immexted=0 { export *[const]:4 i0712; } +Uimm32_0712x: "##"^val is i0712 & immexted=1 [ val = (simmext << 6) | i0712; ] { export *[const]:4 val; } # s32 + +Uimm32_0513x: "#"^i0513 is i0513 & immexted=0 { export *[const]:4 i0513; } +Uimm32_0513x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } + +Uimm32_0512x: "#"^i0512 is i0512 & immexted=0 { export *[const]:4 i0512; } +Uimm32_0512x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } + +Uimm32_2025x: "#"^i2025 is i2025 & immexted=0 { export *[const]:4 i2025; } +Uimm32_2025x: "##"^val is i2025 & immexted=1 [ val = (immext << 6) | i2025; ] { export *[const]:4 val; } + +Uimm32_0005x: "#"^i0005 is i0005 & immexted=0 { export *[const]:4 i0005; } +Uimm32_0005x: "##"^val is i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:4 val; } + +# Truncated Extended Immediates +# TODO: Should we be truncating extended constant values? Maybe not +# Assembler does permit extended immediate +/- values larger than operation size: +# p0 = cmpb.gtu (r1, ##212321) + +Simm16_13_0006x: "#"^val is s13 & i0006 & immexted=0 [ val = (s13 << 7) | i0006; ] { export *[const]:2 val; } +Simm16_13_0006x: "##"^val is i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:2 val; } # u32 + +Simm8_13_0006x: "#"^val is s13 & i0006 & immexted=0 [ val = (s13 << 7) | i0006; ] { export *[const]:1 val; } +Simm8_13_0006x: "##"^val is i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:1 val; } # u32 + +Simm8_13_0004x: "#"^val is s13 & i0004 & immexted=0 [ val = (s13 << 5) | i0004; ] { export *[const]:1 val; } +Simm8_13_0004x: "##"^val is i13 & i0004 & immexted=1 [ val = (immext << 6) | (i13 << 5) | i0004; ] { export *[const]:1 val; } # u32 + +Simm16_13_0004x: "#"^val is s13 & i0004 & immexted=0 [ val = (s13 << 5) | i0004; ] { export *[const]:2 val; } +Simm16_13_0004x: "##"^val is i13 & i0004 & immexted=1 [ val = (immext << 6) | (i13 << 5) | i0004; ] { export *[const]:2 val; } # u32 + +Uimm8_0511x: "#"^i0511 is i0511 & immexted=0 { export *[const]:1 i0511; } +Uimm8_0511x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:1 val; } + +Uimm16_0511x: "#"^i0511 is i0511 & immexted=0 { export *[const]:2 i0511; } +Uimm16_0511x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:2 val; } + +Simm16_0512x: "#"^s0512 is s0512 & immexted=0 { export *[const]:2 s0512; } +Simm16_0512x: "##"^val is i0510 & immexted=1 [ val = (simmext << 6) | i0510; ] { export *[const]:2 val; } + +# Clear mask which can be and-ed with source +ClrBit_0004w: "clrbit("^Uimm8_0004^")" is Uimm8_0004 { mask:4 = ~(1 << Uimm8_0004); export mask; } +ClrBit_0004h: "clrbit("^Uimm8_0004^")" is Uimm8_0004 { mask:2 = ~(1 << Uimm8_0004); export mask; } +ClrBit_0004b: "clrbit("^Uimm8_0004^")" is Uimm8_0004 { mask:1 = ~(1 << Uimm8_0004); export mask; } + +# Set mask which can be or-ed with source +SetBit_0004w: "setbit("^Uimm8_0004^")" is Uimm8_0004 { mask:4 = 1 << Uimm8_0004; export mask; } +SetBit_0004h: "setbit("^Uimm8_0004^")" is Uimm8_0004 { mask:2 = 1 << Uimm8_0004; export mask; } +SetBit_0004b: "setbit("^Uimm8_0004^")" is Uimm8_0004 { mask:1 = 1 << Uimm8_0004; export mask; } + +# embedded shift operand (Class-13): asl(Rx32,#U5) and lsr(Rx32,#U5) +ShiftRx_D04_I0812: "asl("^rx5,Uimm8_0812^")" is op4=0 & rx5 & Uimm8_0812 { tmp:4 = rx5 << Uimm8_0812; export tmp; } +ShiftRx_D04_I0812: "lsr("^rx5,Uimm8_0812^")" is op4=1 & rx5 & Uimm8_0812 { tmp:4 = rx5 >> Uimm8_0812; export tmp; } + +# embedded predicate and/or logic operand (Class-6): and(Pt4,[!]Pu4) and or(Pt4,[!]Pu4 ) +# NOTE: Decided to implement as full byte logic instead of single-bit boolean logic +PredLogic_S23_P0607: pu0607 is op23=0 & pu0607 { export pu0607; } +PredLogic_S23_P0607: "!"^pu0607 is op23=1 & pu0607 { tmp:1 = ~pu0607; export tmp; } +PredLogic_L21_S23_P0809_P0607: "and("^pu0809,PredLogic_S23_P0607^")" is op21=0 & pu0809 & PredLogic_S23_P0607 { tmp:1 = pu0809 & PredLogic_S23_P0607; export tmp; } +PredLogic_L21_S23_P0809_P0607: "or("^pu0809,PredLogic_S23_P0607^")" is op21=1 & pu0809 & PredLogic_S23_P0607 { tmp:1 = pu0809 | PredLogic_S23_P0607; export tmp; } + + +# Taken/Not-Taken (decoration only) + +Taken13: ":t" is op13=1 { } +Taken13: ":nt" is op13=0 { } + +Taken12: ":t" is op12=1 { } +Taken12: ":nt" is op12=0 { } + +NotTaken01: ":nt" is op1=1 { } +NotTaken01: is op1=0 { } + +# Predicate Register Condition for jump/call (least significant bit only) +FlowCondUU: ".if("pu0809name")" is op21=0 & pu0809name & pu0809 { + condition:1 = (pu0809 & 1); + <> + ConditionReg = condition; +} +FlowCondUU: ".if(!"pu0809name")" is op21=1 & pu0809name & pu0809 { + condition:1 = !(pu0809 & 1); + <> + ConditionReg = condition; +} + +# .new Predicate Register Condition for jump/call (least significant bit only) +FlowCondNewUU: ".if("pu0809name".new)" is op21=0 & pu0809name & pu0809 { + <> + ConditionReg = (pu0809 & 1); # predicate will already be comitted +} +FlowCondNewUU: ".if(!"pu0809name".new)" is op21=1 & pu0809name & pu0809 { + <> + ConditionReg = !(pu0809 & 1); # predicate will already be comitted +} + +# Predicate Register Condition for dealloc_return (least significant bit only) + +FlowCond0809_N11_S13: ".if("pu0809name")" is op13=0 & op11=0 & pu0809 & pu0809name { + condition:1 = (pu0809 & 1); + <> + ConditionReg = condition; +} +FlowCond0809_N11_S13: ".if(!"pu0809name")" is op13=1 & op11=0 & pu0809 & pu0809name { + condition:1 = !(pu0809 & 1); + <> + ConditionReg = condition; +} +FlowCond0809_N11_S13: ".if("pu0809name".new)" is op13=0 & op11=1 & pu0809 & pu0809name { + <> + ConditionReg = (pu0809 & 1); # predicate will already be comitted +} +FlowCond0809_N11_S13: ".if(!"pu0809name".new)" is op13=1 & op11=1 & pu0809 & pu0809name { + <> + ConditionReg = !(pu0809 & 1); # predicate will already be comitted +} + + +# Predicate Register Condition for Right Packed EE jumpr (least significant bit only, includes .new handling) + +FlowP0Cond_N01_S00: ".if(P0)" is op0=0 & op1=0 { + condition:1 = (P0 & 1); + <> + ConditionReg = condition; +} +FlowP0Cond_N01_S00: ".if(!P0)" is op0=1 & op1=0 { + condition:1 = !(P0 & 1); + <> + ConditionReg = condition; +} +FlowP0Cond_N01_S00: ".if(P0.new)" is op0=0 & op1=1 { + <> + ConditionReg = (P0 & 1); # P0 will already be comitted +} +FlowP0Cond_N01_S00: ".if(!P0.new)" is op0=1 & op1=1 { + <> + ConditionReg = !(P0 & 1); # P0 will already be comitted +} + + +# Predicate Register Condition for Right Packed EE conditional ops (least significant bit only, includes .new handling) + +P0Cond_N05_S04: ".if(P0)" is op4=0 & op5=1 { + condition:1 = (P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N05_S04: ".if(!P0)" is op4=1 & op5=1 { + condition:1 = !(P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N05_S04: ".if(P0.new)" is op4=0 & op5=0 { + condition:1 = 0; + <> + condition = (P0.new & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N05_S04: ".if(!P0.new)" is op4=1 & op5=0 { + condition:1 = 0; + <> + condition = !(P0.new & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition for Left Packed EE conditional ops (least significant bit only, includes .new handling) + +P0Cond_N21_S20: ".if(P0)" is op20=0 & op21=1 { + condition:1 = (P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N21_S20: ".if(!P0)" is op20=1 & op21=1 { + condition:1 = !(P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N21_S20: ".if(P0.new)" is op20=0 & op21=0 { + condition:1 = 0; + <> + condition = (P0.new & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N21_S20: ".if(!P0.new)" is op20=1 & op21=0 { + condition:1 = 0; + <> + condition = !(P0.new & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory store which must be in last slot. + +PuCond0001_N07_S02: ".if("pu0001name")" is op2=0 & op7=0 & pu0001 & pu0001name { + condition:1 = (pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N07_S02: ".if(!"pu0001name")" is op2=1 & op7=0 & pu0001 & pu0001name { + condition:1 = !(pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N07_S02: ".if("pu0001name".new)" is op2=0 & op7=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = (pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N07_S02: ".if(!"pu0001name".new)" is op2=1 & op7=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = !(pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory store which must be in last slot. + +PuCond0001_N13_S02: ".if("pu0001name")" is op2=0 & op13=0 & pu0001 & pu0001name { + condition:1 = (pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N13_S02: ".if(!"pu0001name")" is op2=1 & op13=0 & pu0001 & pu0001name { + condition:1 = !(pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N13_S02: ".if("pu0001name".new)" is op2=0 & op13=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = (pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N13_S02: ".if(!"pu0001name".new)" is op2=1 & op13=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = !(pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory store which must be in last slot. + +PuCond0001_N25_S26: ".if("pu0001name")" is op26=0 & op25=0 & pu0001 & pu0001name { + condition:1 = (pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N25_S26: ".if(!"pu0001name")" is op26=1 & op25=0 & pu0001 & pu0001name { + condition:1 = !(pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N25_S26: ".if("pu0001name".new)" is op26=0 & op25=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = (pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N25_S26: ".if(!"pu0001name".new)" is op26=1 & op25=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = !(pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) + +PuCond0809_N10_S11: ".if("pu0809name")" is op11=0 & op10=0 & pu0809 & pu0809name { + condition:1 = (pu0809 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0809_N10_S11: ".if(!"pu0809name")" is op11=1 & op10=0 & pu0809 & pu0809name { + condition:1 = !(pu0809 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0809_N10_S11: ".if("pu0809name".new)" is op11=0 & op10=1 & pu0809_ & pu0809name { + condition:1 = 0; + <> + condition = (pu0809_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0809_N10_S11: ".if(!"pu0809name".new)" is op11=1 & op10=1 & pu0809_ & pu0809name { + condition:1 = 0; + <> + condition = !(pu0809_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory load which must be in last slot. + +PuCond0910_N12_S11: ".if("pu0910name")" is op11=0 & op12=0 & pu0910 & pu0910name { + condition:1 = (pu0910 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0910_N12_S11: ".if(!"pu0910name")" is op11=1 & op12=0 & pu0910 & pu0910name { + condition:1 = !(pu0910 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0910_N12_S11: ".if("pu0910name".new)" is op11=0 & op12=1 & pu0910_ & pu0910name { + condition:1 = 0; + <> + condition = (pu0910_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0910_N12_S11: ".if(!"pu0910name".new)" is op11=1 & op12=1 & pu0910_ & pu0910name { + condition:1 = 0; + <> + condition = !(pu0910_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory load which must be in last slot. + +PuCond1112_N25_S26: ".if("pu1112name")" is op26=0 & op25=0 & pu1112 & pu1112name { + condition:1 = (pu1112 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond1112_N25_S26: ".if(!"pu1112name")" is op26=1 & op25=0 & pu1112 & pu1112name { + condition:1 = !(pu1112 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond1112_N25_S26: ".if("pu1112name".new)" is op26=0 & op25=1 & pu1112_ & pu1112name { + condition:1 = 0; + <> + condition = (pu1112_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond1112_N25_S26: ".if(!"pu1112name".new)" is op26=1 & op25=1 & pu1112_ & pu1112name { + condition:1 = 0; + <> + condition = !(pu1112_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) + +PuCond2122_N13_S23: ".if("pu2122name")" is op23=0 & op13=0 & pu2122 & pu2122name { + condition:1 = (pu2122 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond2122_N13_S23: ".if(!"pu2122name")" is op23=1 & op13=0 & pu2122 & pu2122name { + condition:1 = !(pu2122 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond2122_N13_S23: ".if("pu2122name".new)" is op23=0 & op13=1 & pu2122_ & pu2122name { + condition:1 = 0; + <> + condition = (pu2122_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond2122_N13_S23: ".if(!"pu2122name".new)" is op23=1 & op13=1 & pu2122_ & pu2122name { + condition:1 = 0; + <> + condition = !(pu2122_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) + +PuCond0506_N13_S07: ".if("pu0506name")" is op7=0 & op13=0 & pu0506 & pu0506name { + condition:1 = (pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N13_S07: ".if(!"pu0506name")" is op7=1 & op13=0 & pu0506 & pu0506name { + condition:1 = !(pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N13_S07: ".if("pu0506name".new)" is op7=0 & op13=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = (pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N13_S07: ".if(!"pu0506name".new)" is op7=1 & op13=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = !(pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory load/store which must be in last slot. + +PuCond0506_N25_S24: ".if("pu0506name")" is op24=0 & op25=0 & pu0506 & pu0506name { + condition:1 = (pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N25_S24: ".if(!"pu0506name")" is op24=1 & op25=0 & pu0506 & pu0506name { + condition:1 = !(pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N25_S24: ".if("pu0506name".new)" is op24=0 & op25=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = (pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N25_S24: ".if(!"pu0506name".new)" is op24=1 & op25=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = !(pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory store which must be in last slot. + +PuCond0506_N24_S23: ".if("pu0506name")" is op23=0 & op24=0 & pu0506 & pu0506name { + condition:1 = (pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N24_S23: ".if(!"pu0506name")" is op23=1 & op24=0 & pu0506 & pu0506name { + condition:1 = !(pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N24_S23: ".if("pu0506name".new)" is op23=0 & op24=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = (pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N24_S23: ".if(!"pu0506name".new)" is op23=1 & op24=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = !(pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# +# Class-3 Memory Access +# + +# Class-3 Store Memory: Rs+#u6 - (u6 is NOT extended) +StAddrRsRelC3: "("^rs5^")" is rs5 & i0712=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +StAddrRsRelC3: "("^rs5^"+#"^offs^")" is rs5 & i0712 [ offs = i0712 << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +#StMemRsRelC3d: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 3; ] { export *[ram]:8 StAddrRsRelC3; } +StMemRsRelC3w: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 2; ] { export *[ram]:4 StAddrRsRelC3; } +StMemRsRelC3h: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 1; ] { export *[ram]:2 StAddrRsRelC3; } +StMemRsRelC3b: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 0; ] { export *[ram]:1 StAddrRsRelC3; } + +# Class-3 Store Memory: Rs+#u6x - (u6 is extended) +StAddrRsRelxC3: "("^rs5^")" is rs5 & i0712=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +StAddrRsRelxC3: "("^rs5^"+#"^offs^")" is rs5 & i0712 & immexted=0 [ offs = i0712 << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StAddrRsRelxC3: "("^rs5^"+##"^offs^")" is rs5 & i0712 & immexted=1 [ offs = (immext << 6) | i0712; ] { + ptr:4 = rs5 + offs; + export ptr; +} +#StMemRsRelxC3d: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 3; ] { export *[ram]:8 StAddrRsRelxC3; } +StMemRsRelxC3w: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 2; ] { export *[ram]:4 StAddrRsRelxC3; } +StMemRsRelxC3h: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 1; ] { export *[ram]:2 StAddrRsRelxC3; } +StMemRsRelxC3b: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 0; ] { export *[ram]:1 StAddrRsRelxC3; } + + +# Class-3 Memory: Rs+Rt<<#n2 +AddrRsRelShiftC3: "("^rs5^"+"^rt5^")" is rs5 & rt5 & op13=0 & op7=0 { + tmp:4 = rs5 + rt5; + export tmp; +} +AddrRsRelShiftC3: "("^rs5^"+"^rt5^"<<"^Uimm2_13_07^")" is rs5 & rt5 & Uimm2_13_07 { + # TODO: verify order of operation + # TODO: Is there an alignment shift? + tmp:4 = rs5 + (rt5 << Uimm2_13_07); + export tmp; +} +MemRsRelShiftC3d: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:8 AddrRsRelShiftC3; } +MemRsRelShiftC3w: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:4 AddrRsRelShiftC3; } +MemRsRelShiftC3h: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:2 AddrRsRelShiftC3; } +MemRsRelShiftC3b: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:1 AddrRsRelShiftC3; } + + +# +# Class-4 Memory Access +# + +# Class-4 Load Memory: Rs+#u6x +LdAddrRsRelxC4: "("^rs5^")" is rs5 & i0510=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +LdAddrRsRelxC4: "("^rs5^"+#"^offs^")" is rs5 & i0510 & immexted=0 [ offs = i0510 << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +LdAddrRsRelxC4: "("^rs5^"+##"^offs^")" is rs5 & i0510 & immexted=1 [ offs = (immext << 6) | i0510; ] { + ptr:4 = rs5 + offs; + export ptr; +} +LdMemRsRelxC4d: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 3; ] { export *[ram]:8 LdAddrRsRelxC4; } +LdMemRsRelxC4w: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 2; ] { export *[ram]:4 LdAddrRsRelxC4; } +LdMemRsRelxC4h: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 1; ] { export *[ram]:2 LdAddrRsRelxC4; } +LdMemRsRelxC4b: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 0; ] { export *[ram]:1 LdAddrRsRelxC4; } + +# Class-4 Store Memory: Rs+#u6x +StAddrRsRelxC4: "("^rs5^")" is rs5 & i13=0 & i0307=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +StAddrRsRelxC4: "("^rs5^"+#"^offs^")" is rs5 & i13 & i0307 & immexted=0 [ offs = ((i13 << 5) | i0307) << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StAddrRsRelxC4: "("^rs5^"+##"^offs^")" is rs5 & i13 & i0307 & immexted=1 [ offs = (immext << 6) | (i13 << 5) | i0307; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StMemRsRelxC4d: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 3; ] { export *[ram]:8 StAddrRsRelxC4; } +StMemRsRelxC4w: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 2; ] { export *[ram]:4 StAddrRsRelxC4; } +StMemRsRelxC4h: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 1; ] { export *[ram]:2 StAddrRsRelxC4; } +StMemRsRelxC4b: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 0; ] { export *[ram]:1 StAddrRsRelxC4; } + +# Class-4 Load Memory: GP+#u16x +LdAddrGPRelxC4: "("^GP^"+#"^offs^")" is i2526 & i1620 & i0513 & GP & immexted=0 + [ offs = ((i2526 << 14) | (i1620 << 9) | i0513) << shift; ] { + local ptr = GP + offs; + export ptr; +} +LdAddrGPRelxC4: "(##"^offs^")" is i0510 & immexted=1 [ offs = (immext << 6) | i0510; ] { + export *[const]:4 offs; +} +LdMemGPRelxC4d: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 3; ] { export *[ram]:8 LdAddrGPRelxC4; } +LdMemGPRelxC4w: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 2; ] { export *[ram]:4 LdAddrGPRelxC4; } +LdMemGPRelxC4h: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 1; ] { export *[ram]:2 LdAddrGPRelxC4; } +LdMemGPRelxC4b: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 0; ] { export *[ram]:1 LdAddrGPRelxC4; } + +# Class-4 Store Memory: GP+#u16x +StAddrGPRelxC4: "("^GP^"+#"^offs^")" is i2526 & i1620 & i13 & i0007 & GP & immexted=0 + [ offs = ((i2526 << 14) | (i1620 << 9) | (i13 << 8) | i0007) << shift; ] { + local ptr = GP + offs; + export ptr; +} +StAddrGPRelxC4: "(##"^offs^")" is i0005 & immexted=1 [ offs = (immext << 6) | i0005; ] { + export *[const]:4 offs; +} +StMemGPRelxC4d: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 3; ] { export *[ram]:8 StAddrGPRelxC4; } +StMemGPRelxC4w: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 2; ] { export *[ram]:4 StAddrGPRelxC4; } +StMemGPRelxC4h: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 1; ] { export *[ram]:2 StAddrGPRelxC4; } +StMemGPRelxC4b: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 0; ] { export *[ram]:1 StAddrGPRelxC4; } + + +# +# Class-9 Memory Access +# + +# Class-9 Load Memory: (Rs32) +LdAddrRsRelC9: "("^rs5^")" is rs5 { export rs5; } +LdMemRsRelC9d: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:8 LdAddrRsRelC9; } +LdMemRsRelC9w: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:4 LdAddrRsRelC9; } +#LdMemRsRelC9h: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:2 LdAddrRsRelC9; } +#LdMemRsRelC9b: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:1 LdAddrRsRelC9; } + +# Class-9 Load Memory: Rf=#U6x +LdAddrRsAssignxC9: "("^rf5^"="^Uimm32_0811_0506x^")" is rf5 & rf5_ & Uimm32_0811_0506x { + # TODO: Need to verify behavior !! + rf5_ = Uimm32_0811_0506x; + export Uimm32_0811_0506x; + <> + rf5 = rf5_; +} +LdMemRsAssignxC9d: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:8 LdAddrRsAssignxC9; } +LdMemRsAssignxC9w: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:4 LdAddrRsAssignxC9; } +LdMemRsAssignxC9h: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:2 LdAddrRsAssignxC9; } +LdMemRsAssignxC9b: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:1 LdAddrRsAssignxC9; } + +# Class-9 Load Memory: #u6x +LdAddrAbsU6xC9: "("^Uimm32_1620_08x^")" is Uimm32_1620_08x { export Uimm32_1620_08x; } + +LdMemAbsU6xC9d: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:8 LdAddrAbsU6xC9; } +LdMemAbsU6xC9w: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:4 LdAddrAbsU6xC9; } +LdMemAbsU6xC9h: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:2 LdAddrAbsU6xC9; } +LdMemAbsU6xC9b: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:1 LdAddrAbsU6xC9; } + + +# Class-9 Load Memory: ( Rs32 << #n2 + #U6x ) +LdAddrRsRelShiftxC9: "("^rs5^"+"^Uimm32_0811_0506x^")" is rs5 & op13=0 & op7=0 & Uimm32_0811_0506x { + tmp:4 = rs5 + Uimm32_0811_0506x; + export tmp; +} +LdAddrRsRelShiftxC9: "("^rs5^"<<"^Uimm2_13_07^"+"^Uimm32_0811_0506x^")" is rs5 & Uimm2_13_07 & Uimm32_0811_0506x { + # TODO: verify order of operation + # TODO: Is there an alignment shift? + tmp:4 = (rs5 << Uimm2_13_07) + Uimm32_0811_0506x; + export tmp; +} +LdMemRsRelShiftxC9d: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:8 LdAddrRsRelShiftxC9; } +LdMemRsRelShiftxC9w: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:4 LdAddrRsRelShiftxC9; } +LdMemRsRelShiftxC9h: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:2 LdAddrRsRelShiftxC9; } +LdMemRsRelShiftxC9b: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:1 LdAddrRsRelShiftxC9; } + + +# Class-9 Load Memory: Rs+#s11x +LdAddrRsRelxC9: "("^rs5^")" is op27=0 & rs5 & i2526=0 & i0513=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +LdAddrRsRelxC9: "("^rs5^"+#"^offs^")" is op27=0 & rs5 & s2526 & i0513 & immexted=0 + [ offs = ((s2526 << 9) | i0513) << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +LdAddrRsRelxC9: "("^rs5^"+##"^offs^")" is op27=0 & rs5 & i0510 & immexted=1 [ offs = (immext << 6) | i0510; ] { + ptr:4 = rs5 + offs; + export ptr; +} +LdMemRsRelxC9d: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 3; ] { export *[ram]:8 LdAddrRsRelxC9; } +LdMemRsRelxC9w: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 2; ] { export *[ram]:4 LdAddrRsRelxC9; } +LdMemRsRelxC9h: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 1; ] { export *[ram]:2 LdAddrRsRelxC9; } +LdMemRsRelxC9b0: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 0; ] { export *[ram]:1 LdAddrRsRelxC9; } +LdMemRsRelxC9b1: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 1; ] { export *[ram]:1 LdAddrRsRelxC9; } +LdMemRsRelxC9b2: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 2; ] { export *[ram]:1 LdAddrRsRelxC9; } + +# Class-9 Load Memory: Rx++#s4 -- 'cond=1' context must be set by conditional instructions! +LdAddrAIS4C9: "("^rx5^"++#"^inc^")" is cond=0 & rx5 & rx5_ & s0508 [ inc = s0508 << shift; ] { + tmp:4 = rx5 + inc; + export rx5; + <> + rx5 = tmp; +} +LdAddrAIS4C9: "("^rx5^"++#"^inc^")" is cond=1 & rx5 & rx5_ & s0508 [ inc = s0508 << shift; ] { + tmp:4 = rx5 + inc; + export rx5; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdMemAIS4C9d: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 3; ] { export *[ram]:8 LdAddrAIS4C9; } +LdMemAIS4C9w: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 2; ] { export *[ram]:4 LdAddrAIS4C9; } +LdMemAIS4C9h: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 1; ] { export *[ram]:2 LdAddrAIS4C9; } +LdMemAIS4C9b0: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 0; ] { export *[ram]:1 LdAddrAIS4C9; } +LdMemAIS4C9b1: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 1; ] { export *[ram]:1 LdAddrAIS4C9; } +LdMemAIS4C9b2: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 2; ] { export *[ram]:1 LdAddrAIS4C9; } + +# Class-9 Load Memory: Rx++#s4:circ(Mu) -- 'cond=1' context must be set by conditional instructions! +LdAddrAIS4CircMuC9: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=0 & rx5 & rx5_ & mu & s0508 + [ inc = s0508 << shift; ] { + tmp:4 = circularAdd(rx5, inc:1, mu); + export rx5; + <> + rx5 = tmp; +} +LdAddrAIS4CircMuC9: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=1 & rx5 & rx5_ & mu & s0508 + [ inc = s0508 << shift; ] { + tmp:4 = circularAdd(rx5, inc:1, mu); + export rx5; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdMemAIS4CircMuC9d: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 3; ] { export *[ram]:8 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9w: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 2; ] { export *[ram]:4 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9h: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 1; ] { export *[ram]:2 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9b0: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 0; ] { export *[ram]:1 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9b1: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 1; ] { export *[ram]:1 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9b2: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 2; ] { export *[ram]:1 LdAddrAIS4CircMuC9; } + +# Class-9 Load Memory: Rx++I:circ(Mu) -- 'cond=1' context must be set by conditional instructions! +LdAddrAIICircMuC9: "("^rx5^"++I:circ("^mu^"))" is cond=0 & rx5 & rx5_ & mu { + i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + tmp:4 = circularAdd(rx5, i, mu); + export rx5; + <> + rx5 = tmp; +} +LdAddrAIICircMuC9: "("^rx5^"++I:circ("^mu^"))" is cond=1 & rx5 & rx5_ & mu { + i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + tmp:4 = circularAdd(rx5, i, mu); + export rx5; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdMemAIICircMuC9d: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:8 LdAddrAIICircMuC9; } +LdMemAIICircMuC9w: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:4 LdAddrAIICircMuC9; } +LdMemAIICircMuC9h: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:2 LdAddrAIICircMuC9; } +LdMemAIICircMuC9b: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:1 LdAddrAIICircMuC9; } + +# Class-9 Load Memory: Rx++Mu and Rx++Mu:brev - op25 selects mode -- 'cond=1' context must be set by conditional instructions! +LdAddrAIMuC9: "("^rx5^"++"^mu^")" is cond=0 & op25=0 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +LdAddrAIMuC9: "("^rx5^"++"^mu^")" is cond=1 & op25=0 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdAddrAIMuC9: "("^rx5^"++"^mu^":brev)" is cond=0 & op25=1 & rx5 & rx5_ & mu { + ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff); + tmp:4 = rx5 + mu; + export ptr; + <> + rx5 = tmp; +} +LdAddrAIMuC9: "("^rx5^"++"^mu^":brev)" is cond=1 & op25=1 & rx5 & rx5_ & mu { + ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff); + tmp:4 = rx5 + mu; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdMemAIMuC9d: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:8 LdAddrAIMuC9; } +LdMemAIMuC9w: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:4 LdAddrAIMuC9; } +LdMemAIMuC9h: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:2 LdAddrAIMuC9; } +LdMemAIMuC9b: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:1 LdAddrAIMuC9; } + + +# Class-9 Load Memory: #u6x - (no shift factor) +LdAddrU6xC9: "(#"^offs^")" is i1620 & i8 & immexted=0 [ offs = (i1620 << 1) | i8; ] { + export *[const]:4 offs; +} +LdAddrU6xC9: "(##"^offs^")" is i1620 & i8 & immexted=1 [ offs = (immext << 6) | (i1620 << 1) | i8; ] { + export *[const]:4 offs; +} +#LdMemU6xC9d: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:8 LdAddrU6xC9; } +#LdMemU6xC9w: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:4 LdAddrU6xC9; } +LdMemU6xC9h: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:2 LdAddrU6xC9; } +#LdMemU6xC9b: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:1 LdAddrU6xC9; } + + +# +# Class-10 Memory Access +# + +# Class-9 Load Memory: (Rs32, Pd4) # predicate displayed only! +StAddrRsRelPdC9: "("^rs5,pu0001^")" is rs5 & pu0001 { export rs5; } +StMemRsRelPdC9w: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:4 StAddrRsRelPdC9; } +StMemRsRelPdC9d: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:8 StAddrRsRelPdC9; } +#StMemRsRelPdC9h: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:2 StAddrRsRelPdC9; } +#StMemRsRelPdC9b: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:1 StAddrRsRelPdC9; } + +# Class-10 Store Memory: Rf=#U6x -- 'cond=1' context must be set by conditional instructions! +StAddrRsAssignxC10: "("^rf5^"="^Uimm32_0005x^")" is cond=0 & rf5 & rf5_ & Uimm32_0005x { + # TODO: Need to verify behavior !! + rf5_ = Uimm32_0005x; + export rf5_; + <> + rf5 = rf5_; +} +StAddrRsAssignxC10: "("^rf5^"="^Uimm32_0005x^")" is cond=1 & rf5 & rf5_ & Uimm32_0005x { + # TODO: Need to verify behavior !! + rf5_ = Uimm32_0005x; + export rf5_; + <> + if (ConditionReg == 0) goto ; + rf5 = rf5_; + +} +StMemRsAssignxC10d: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:8 StAddrRsAssignxC10; } +StMemRsAssignxC10w: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:4 StAddrRsAssignxC10; } +StMemRsAssignxC10h: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:2 StAddrRsAssignxC10; } +StMemRsAssignxC10b: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:1 StAddrRsAssignxC10; } + +# Class-10 Store Memory: #u6x +StAddrAbsU6xC10: "("^Uimm32_1617_0306x^")" is Uimm32_1617_0306x { export Uimm32_1617_0306x; } + +StMemAbsU6xC10d: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:8 StAddrAbsU6xC10; } +StMemAbsU6xC10w: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:4 StAddrAbsU6xC10; } +StMemAbsU6xC10h: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:2 StAddrAbsU6xC10; } +StMemAbsU6xC10b: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:1 StAddrAbsU6xC10; } + +# Class-10 Store Memory: ( Rs32 << #n2 + #U6x ) +StAddrRsRelShiftxC10: "("^rs5^"+"^Uimm32_0005x^")" is rs5 & op13=0 & op6=0 & Uimm32_0005x { + tmp:4 = rs5 + Uimm32_0005x; + export tmp; +} +StAddrRsRelShiftxC10: "("^rs5^"<<"^Uimm2_13_06^"+"^Uimm32_0005x^")" is rs5 & Uimm2_13_06 & Uimm32_0005x { + # TODO: verify order of operation + # TODO: Is there an alignment shift? + tmp:4 = (rs5 << Uimm2_13_06) + Uimm32_0005x; + export tmp; +} +StMemRsRelShiftxC10d: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:8 StAddrRsRelShiftxC10; } +StMemRsRelShiftxC10w: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:4 StAddrRsRelShiftxC10; } +StMemRsRelShiftxC10h: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:2 StAddrRsRelShiftxC10; } +StMemRsRelShiftxC10b: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:1 StAddrRsRelShiftxC10; } + +# Class-10 Store Memory: Rs+#s11x +StAddrRsRelxC10: "("^rs5^")" is op27=0 & rs5 & s2526=0 & i13=0 & i0007=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +StAddrRsRelxC10: "("^rs5^"+#"^offs^")" is op27=0 & rs5 & s2526 & i13 & i0007 & immexted=0 + [ offs = ((s2526 << 9) | (i13 << 8) | i0007) << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StAddrRsRelxC10: "("^rs5^"+##"^offs^")" is op27=0 & rs5 & i0005 & immexted=1 [ offs = (immext << 6) | i0005; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StMemRsRelxC10d: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 3; ] { export *[ram]:8 StAddrRsRelxC10; } +StMemRsRelxC10w: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 2; ] { export *[ram]:4 StAddrRsRelxC10; } +StMemRsRelxC10h: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 1; ] { export *[ram]:2 StAddrRsRelxC10; } +StMemRsRelxC10b: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 0; ] { export *[ram]:1 StAddrRsRelxC10; } + +# Class-10 Store Memory: Rx++#s4 -- 'cond=1' context must be set by conditional instructions! +StAddrAIS4C10: "("^rx5^"++#"^inc^")" is cond=0 & op2527=5 & rx5 & rx5_ & s0306 + [ inc = s0306 << shift; ] { + tmp:4 = rx5 + inc; + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +StAddrAIS4C10: "("^rx5^"++#"^inc^")" is cond=1 & op2527=5 & rx5 & rx5_ & s0306 + [ inc = s0306 << shift; ] { + tmp:4 = rx5 + inc; + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StMemAIS4C10d: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 3; ] { export *[ram]:8 StAddrAIS4C10; } +StMemAIS4C10w: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 2; ] { export *[ram]:4 StAddrAIS4C10; } +StMemAIS4C10h: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 1; ] { export *[ram]:2 StAddrAIS4C10; } +StMemAIS4C10b: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 0; ] { export *[ram]:1 StAddrAIS4C10; } + +# Class-10 Store Memory: Rx++#s4:circ(Mu) -- 'cond=1' context must be set by conditional instructions! +StAddrAIS4CircMuC10: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=0 & op2527=4 & rx5 & rx5_ & mu & i1=0 & s0306 + [ inc = s0306 << shift; ] { + tmp:4 = circularAdd(rx5, inc:1, mu); + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +StAddrAIS4CircMuC10: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=1 & op2527=4 & rx5 & rx5_ & mu & i1=0 & s0306 + [ inc = s0306 << shift; ] { + tmp:4 = circularAdd(rx5, inc:1, mu); + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StMemAIS4CircMuC10d: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 3; ] { export *[ram]:8 StAddrAIS4CircMuC10; } +StMemAIS4CircMuC10w: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 2; ] { export *[ram]:4 StAddrAIS4CircMuC10; } +StMemAIS4CircMuC10h: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 1; ] { export *[ram]:2 StAddrAIS4CircMuC10; } +StMemAIS4CircMuC10b: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 0; ] { export *[ram]:1 StAddrAIS4CircMuC10; } + +# Class-10 Store Memory: Rx++I:circ(Mu) -- 'cond=1' context must be set by conditional instructions! +StAddrAIICircMuC10: "("^rx5^"++I:circ("^mu^"))" is cond=0 & op2527=4 & rx5 & rx5_ & mu & i1=1 { + i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + tmp:4 = circularAdd(rx5, i, mu); + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +StAddrAIICircMuC10: "("^rx5^"++I:circ("^mu^"))" is cond=1 & op2527=4 & rx5 & rx5_ & mu & i1=1 { + i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + tmp:4 = circularAdd(rx5, i, mu); + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StMemAIICircMuC10d: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:8 StAddrAIICircMuC10; } +StMemAIICircMuC10w: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:4 StAddrAIICircMuC10; } +StMemAIICircMuC10h: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:2 StAddrAIICircMuC10; } +StMemAIICircMuC10b: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:1 StAddrAIICircMuC10; } + +# Class-10 Store Memory: Rx++Mu and Rx++Mu:brev - op25 selects mode -- 'cond=1' context must be set by conditional instructions! +StAddrAIMuC10: "("^rx5^"++"^mu^")" is cond=0 & op2527=6 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +StAddrAIMuC10: "("^rx5^"++"^mu^")" is cond=1 & op2527=6 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StAddrAIMuC10: "("^rx5^"++"^mu^":brev)" is cond=0 & op2527=7 & rx5 & rx5_ & mu { + ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff); + tmp:4 = rx5 + mu; + export ptr; + <> + rx5 = tmp; +} +StAddrAIMuC10: "("^rx5^"++"^mu^":brev)" is cond=1 & op2527=7 & rx5 & rx5_ & mu { + ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff); + tmp:4 = rx5 + mu; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StMemAIMuC10d: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:8 StAddrAIMuC10; } +StMemAIMuC10w: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:4 StAddrAIMuC10; } +StMemAIMuC10h: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:2 StAddrAIMuC10; } +StMemAIMuC10b: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:1 StAddrAIMuC10; } + + +# +# Left Memory Access +# + +# Left Sp-Relative Memory (Sp+#u5:2) +MemSpRelU5Lw: "("^SP^"+#"^offs^")" is SP & i2024 [ offs = i2024 << 2; ] { + ptr:4 = SP + offs; + export *[ram]:4 ptr; +} + +# Left Sp-Relative Memory (Sp+#u5:3) +MemSpRelU5Ld: "("^SP^"+#"^offs^")" is SP & i1923 [ offs = i1923 << 3; ] { + ptr:4 = SP + offs; + export *[ram]:8 ptr; +} + +# Left Sp-Relative Memory (Sp+#s6:3) +MemSpRelS6Ld: "("^SP^"+#"^offs^")" is SP & s1924 [ offs = s1924 << 3; ] { + ptr:4 = SP + offs; + export *[ram]:8 ptr; +} + + +# Left Rs-Relative Memory (Rs16+#u4:2) +MemRsRelU4Lw: "("^rs4l^")" is rs4l & i2427=0 { + ptr:4 = rs4l; + export *[ram]:4 ptr; +} +MemRsRelU4Lw: "("^rs4l^"+#"^offs^")" is rs4l & i2427 [ offs = i2427 << 2; ] { + ptr:4 = rs4l + offs; + export *[ram]:4 ptr; +} + +# Left Rs-Relative Memory (Rs16+#u4:0) +MemRsRelU4Lb: "("^rs4l^")" is rs4l & i2427=0 { + ptr:4 = rs4l; + export *[ram]:1 ptr; +} +MemRsRelU4Lb: "("^rs4l^"+#"^i2427^")" is rs4l & i2427 { + ptr:4 = rs4l + i2427; + export *[ram]:1 ptr; +} + +# Left Rs-Relative Memory (Rs16+#u3:1) +MemRsRelU3Lh: "("^rs4l^")" is rs4l & i2426=0 { + ptr:4 = rs4l; + export *[ram]:2 ptr; +} +MemRsRelU3Lh: "("^rs4l^"+#"^offs^")" is rs4l & i2426 [ offs = i2426 << 1; ] { + ptr:4 = rs4l + offs; + export *[ram]:2 ptr; +} + +# Left Rs-Relative Memory (Rs16+#u3:0) +MemRsRelU3Lb: "("^rs4l^")" is rs4l & i2426=0 { + ptr:4 = rs4l; + export *[ram]:1 ptr; +} +MemRsRelU3Lb: "("^rs4l^"+#"^i2426^")" is rs4l & i2426 { + ptr:4 = rs4l + i2426; + export *[ram]:1 ptr; +} + +# +# Class-15-Left Memory Access +# + +# Class-15 (LEFT) Store Rs-Relative Memory (Rs16+#u4:2) +StMemRsRelC15Lw: "("^rs4l^")" is rs4l & i1619=0 { + ptr:4 = rs4l; + export *[ram]:4 ptr; +} +StMemRsRelC15Lw: "("^rs4l^"+#"^offs^")" is rs4l & i1619 [ offs = i1619 << 2; ] { + ptr:4 = rs4l + offs; + export *[ram]:4 ptr; +} + +# Class-15 (LEFT) Store Rs-Relative Memory (Rs16+#u4:0) +StMemRsRelC15Lb: "("^rs4l^")" is rs4l & i1619=0 { + ptr:4 = rs4l; + export *[ram]:1 ptr; +} +StMemRsRelC15Lb: "("^rs4l^"+#"^i1619^")" is rs4l & i1619 { + ptr:4 = rs4l + i1619; + export *[ram]:1 ptr; +} + + +# +# Right Memory Access (used with both Load and Store) +# + +# Right Rs-Relative Memory (Rs16+#u4:2) +MemRsRelU4Rw: "("^rs4r^")" is rs4r & i0811=0 { + ptr:4 = rs4r; + export *[ram]:4 ptr; +} +MemRsRelU4Rw: "("^rs4r^"+#"^offs^")" is rs4r & i0811 [ offs = i0811 << 2; ] { + ptr:4 = rs4r + offs; + export *[ram]:4 ptr; +} + +# Right Rs-Relative Memory (Rs16+#u4:0) +MemRsRelU4Rb: "("^rs4r^")" is rs4r & i0811=0 { + ptr:4 = rs4r; + export *[ram]:1 ptr; +} +MemRsRelU4Rb: "("^rs4r^"+#"^i0811^")" is rs4r & i0811 { + ptr:4 = rs4r + i0811; + export *[ram]:1 ptr; +} + +# Right Rs-Relative Memory (Rs16+#u4:0) +MemRsRelU4Rnb: "("^rs4r^")" is rs4r & i0003=0 { + ptr:4 = rs4r; + export *[ram]:1 ptr; +} +MemRsRelU4Rnb: "("^rs4r^"+#"^i0003^")" is rs4r & i0003 { + ptr:4 = rs4r + i0003; + export *[ram]:1 ptr; +} + +# Right Rs-Relative Memory (Rs16+#u3:0) +MemRsRelU3Rb: "("^rs4r^")" is rs4r & i0810=0 { + ptr:4 = rs4r; + export *[ram]:1 ptr; +} +MemRsRelU3Rb: "("^rs4r^"+#"^i0810^")" is rs4r & i0810 { + ptr:4 = rs4r + i0810; + export *[ram]:1 ptr; +} + +# Right Rs-Relative Memory (Rs16+#u3:1) +MemRsRelU3Rh: "("^rs4r^")" is rs4r & i0810=0 { + ptr:4 = rs4r; + export *[ram]:2 ptr; +} +MemRsRelU3Rh: "("^rs4r^"+#"^offs^")" is rs4r & i0810 [ offs = i0810 << 1; ] { + ptr:4 = rs4r + offs; + export *[ram]:2 ptr; +} + +# Right Sp-Relative Memory (Sp+#u5:2) +MemSpRelU5Rw: "("^SP^"+#"^offs^")" is SP & i0408 [ offs = i0408 << 2; ] { + ptr:4 = SP + offs; + export *[ram]:4 ptr; +} + +# Right Sp-Relative Memory (Sp+#u5:3) +MemSpRelU5Rd: "("^SP^"+#"^offs^")" is SP & i0307 [ offs = i0307 << 3; ] { + ptr:4 = SP + offs; + export *[ram]:8 ptr; +} + +# Right Sp-Relative Memory (Sp+#s6:3) +MemSpRelS6Rd: "("^SP^"+#"^offs^")" is SP & s0308 [ offs = s0308 << 3; ] { + ptr:4 = SP + offs; + export *[ram]:8 ptr; +} + + +# +# Class-15-Right Memory Access +# + +# Class-15 (RIGHT) Store Rs-Relative Memory (Rs16+#u4:2) +StMemRsRelC15Rw: "("^rs4r^")" is rs4r & i0003=0 { + ptr:4 = rs4r; + export *[ram]:4 ptr; +} +StMemRsRelC15Rw: "("^rs4r^"+#"^offs^")" is rs4r & i0003 [ offs = i0003 << 2; ] { + ptr:4 = rs4r + offs; + export *[ram]:4 ptr; +} + +# +# ^instruction phases +# + +# Pcode Phases: +# All constructors and subconstructors must support the following named pcode +# phases which are assembled at the end of each packet: +# <> - this phase performs all conditional executions to allow for new predicate use +# <> - this phase performs all unconditional writes +# <> - this phase performs all conditional writes +# <> - this phase performs all conditional and unconditional flows + +# 'parse' bits (PP,EE) decoding (see V2 manual section 10.5 Loop packets for additional detail): +# +# '01' & '10' normal 'PP' instruction +# '11' normal 'PP' instruction when last instruction in packet +# '00' duplex/packed 'EE' instruction (v4, always last instruction in packet) +# + +# reset packetBits if this is first instruction in packet +ResetPacketBits: is packetOffset=0 [ packetBits=0; ] { } +ResetPacketBits: is epsilon { } + +# Phase-0: Update packet offset for next instruction (does not alter packetOffset) +:^instruction is phase=0 & (parse=1 | parse=2) & ResetPacketBits & instruction + [ tmpCtx2 = packetOffset; + packetOffset=packetOffset+1; + globalset(inst_next,packetOffset); + packetOffset = tmpCtx2; + phase = 1; ] { } +:^instruction is phase=0 & (parse=3 | parse=0) & ResetPacketBits & instruction [ +# Rely on default context packetOffset=0 to be used for start of next packet +# tmpCtx2 = packetOffset; +# packetOffset=0; # next instr would start new execute packet (slot-0) +# globalset(inst_next,packetOffset); +# packetOffset = tmpCtx2; + phase=1; ] { } + +# Phase-1: End of H/W Loop packet detection (update parse1 or parse2 context) +# if (start-of-packet) init shadow registers +:^instruction is phase=1 & instruction [ phase = 2; ] { } +:^instruction is phase=1 & packetOffset=1 & parse & instruction [ parse2 = parse; phase = 2; ] { } +:^instruction is phase=1 & packetOffset=0 & parse & instruction [ parse1 = parse; phase = 2; ] +{ + # NOTE: The following execution packet intitialization appears at the start + # of every execute packet. + + # Initilize Auto-AND predicates at start of execute packet. + # We rely on the hexagon compiler to enforce and predicate/auto-AND restrictions. + P0.new = 0xff; + P1.new = 0xff; + P2.new = 0xff; + P3.new = 0xff; + + build instruction; +} + +# Phase-2: Identify instruction parse phase +# 'PP' instructions parsed in Phase-3 +# 'EE' duplex/packed-instructions parsed in Phase-4 +:^instruction is phase=2 & (parse_0=1 | parse_1=1) & instruction [ phase = 3; ] { } +:^instruction is phase=2 & parse=0 & instruction [ phase = 4; ] { } + +# Phase-3: Actual instruction decode for packet-based (PP) instructions +# - instructions may use packetOffset context to obtain adjusted inst_start +# - instructions may alter other packedBits context sub-registers +# +# All packet type instructions (PP) must use the following pattern: +# Note: flow/loop instructions must also manipulate certain context +# +# : EndPacket is & $(END_PACKET) { +# +# build EndPacket; +# } +# +# End of Packet Handling ('PP' instructions only, resumes phase processing via EndPacket +# subconstructors following constructor match) +# - EndPacket subconstructor must be included with all non-packed instructions as +# the last operand and 'build EndPacket' must appear at end of pcode. +# - END_PACKET Can't specify [ ] since this may be specified by instruction +# +@define END_PACKET "phase=3 & EndPacket " + +# Phase-4: Parse Left subinstruction within duplex/packed 'EE' instruction +# This phase relies on instruction constructors to match the first/left-side +# subinstruction. All such instructions must employ the following pattern: +# +# : EndPackedLeft is & $(END_PACKED_LEFT) { +# +# build EndPackedLeft; +# } +# +# Sample: +# +# :assign Rdd3l,Uimm2_2122 EndPackedLeft is iclass3031=1 & iclass28=1 & op2327=0x18 & op1920=0 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { +# Rdd3l = zext(Uimm2_2122); +# build EndPackedLeft; +# } +# +# - END_PACKET_LEFT Can't specify [ ] since this may be specified by instruction +# +@define END_PACKED_LEFT "phase=4 & EndPackedLeft " + +# Phase-5: Parse Right subinstruction within duplex/packed 'EE' instruction +# This phase relies on instruction constructors to match the second/right-side +# subinstruction. All such instructions must employ the following pattern: +# +# : EndPackedRight is & $(END_PACKED_RIGHT) { +# +# build EndPackedRight; +# } +# +# Sample: +# +# :deallocframe EndPackedRight is op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) { +# deallocframe(); +# build EndPackedRight; +# } +# +# - END_PACKET_RIGHT Can't specify [ ] since this may be specified by instruction +# +@define END_PACKED_RIGHT "phase=5 & EndPackedRight " + +# +PropogateLoopCfg: is useLoopCfg=1 [ globalset(inst_next,useLoopCfg); ] { } +PropogateLoopCfg: is useLoopCfg=0 { } + +# Check for pipelined loop count and inject pcode if needed +CheckLpcfg: is useLoopCfg=0 { } +CheckLpcfg: is useLoopCfg=1 [ useLoopCfg=0; ] { + lpcfg:1 = $(LPCFG); + if (lpcfg == 0) goto ; + lpcfg = lpcfg - 1; + $(LPCFG) = lpcfg; + P3 = (lpcfg == 0); # set P3 once pipeline count (1-3) has lapsed + # NOTE: may be incorrect to clear P3 if not done yet + +} + +# EndPacket: End of HW Loop handling (uses parse1 and parse2) + +EndOfLoop: is PropogateLoopCfg { } # not end-of-loop - propogate useLoopCfg if active +EndOfLoop: " :endloop0" is parse1=2 & CheckLpcfg { # Last in HW Loop 0 + # :endloop0 - TODO: not sure how to display + build CheckLpcfg; + if (LC0 <= 1) goto inst_next; + LC0 = LC0 - 1; + goto [SA0]; +} +EndOfLoop: " :endloop1" is parse1=1 & parse2=2 & PropogateLoopCfg { # Last in HW Loop 1 - propogate useLoopCfg if active + # :endloop1 - TODO: not sure how to display + if (LC1 <= 1) goto inst_next; + LC1 = LC1 - 1; + goto [SA1]; +} +EndOfLoop: " :endloop0 :endloop1" is parse1=2 & parse2=2 & CheckLpcfg { # Last in HW Loop 0 & 1 + # :endloop0:endloop1 - TODO: not sure how to display + build CheckLpcfg; + if (LC0 <= 1) goto inst_next; + LC0 = LC0 - 1; + goto [SA0]; + if (LC1 <= 1) goto inst_next; + LC1 = LC1 - 1; + goto [SA1]; +} + +# CrossBuild: +# - include <> <> and <> pcode for all instructions in packet + +CrossBuildAddr0: loc is epsilon [ loc = inst_start; ] { export *:4 loc; } +CrossBuildAddr1: loc is epsilon [ loc = inst_start - 4; ] { export *:4 loc; } +CrossBuildAddr2: loc is epsilon [ loc = inst_start - 8; ] { export *:4 loc; } +CrossBuildAddr3: loc is epsilon [ loc = inst_start - 12; ] { export *:4 loc; } + +CrossBuild: is packetOffset=0 & CrossBuildAddr0 [ phase=8; ] { + crossbuild CrossBuildAddr0,EXEC_COND; + crossbuild CrossBuildAddr0,COMMIT; + crossbuild CrossBuildAddr0,COMMIT_COND; + ReturnAddr = inst_next; + crossbuild CrossBuildAddr0,FLOW; +} +CrossBuild: is packetOffset=1 & CrossBuildAddr0 & CrossBuildAddr1 [ phase=8; ] { + crossbuild CrossBuildAddr1,EXEC_COND; + crossbuild CrossBuildAddr0,EXEC_COND; + crossbuild CrossBuildAddr1,COMMIT; + crossbuild CrossBuildAddr0,COMMIT; + crossbuild CrossBuildAddr1,COMMIT_COND; + crossbuild CrossBuildAddr0,COMMIT_COND; + ReturnAddr = inst_next; + crossbuild CrossBuildAddr1,FLOW; + crossbuild CrossBuildAddr0,FLOW; +} +CrossBuild: is packetOffset=2 & CrossBuildAddr0 & CrossBuildAddr1 & CrossBuildAddr2 [ phase=8; ] { + crossbuild CrossBuildAddr2,EXEC_COND; + crossbuild CrossBuildAddr1,EXEC_COND; + crossbuild CrossBuildAddr0,EXEC_COND; + crossbuild CrossBuildAddr2,COMMIT; + crossbuild CrossBuildAddr1,COMMIT; + crossbuild CrossBuildAddr0,COMMIT; + crossbuild CrossBuildAddr2,COMMIT_COND; + crossbuild CrossBuildAddr1,COMMIT_COND; + crossbuild CrossBuildAddr0,COMMIT_COND; + ReturnAddr = inst_next; + crossbuild CrossBuildAddr2,FLOW; + crossbuild CrossBuildAddr1,FLOW; + crossbuild CrossBuildAddr0,FLOW; +} +CrossBuild: is packetOffset=3 & CrossBuildAddr0 & CrossBuildAddr1 & CrossBuildAddr2 & CrossBuildAddr3 [ phase=8; ] { + crossbuild CrossBuildAddr3,EXEC_COND; + crossbuild CrossBuildAddr2,EXEC_COND; + crossbuild CrossBuildAddr1,EXEC_COND; + crossbuild CrossBuildAddr0,EXEC_COND; + crossbuild CrossBuildAddr3,COMMIT; + crossbuild CrossBuildAddr2,COMMIT; + crossbuild CrossBuildAddr1,COMMIT; + crossbuild CrossBuildAddr0,COMMIT; + crossbuild CrossBuildAddr3,COMMIT_COND; + crossbuild CrossBuildAddr2,COMMIT_COND; + crossbuild CrossBuildAddr1,COMMIT_COND; + crossbuild CrossBuildAddr0,COMMIT_COND; + ReturnAddr = inst_next; + crossbuild CrossBuildAddr3,FLOW; + crossbuild CrossBuildAddr2,FLOW; + crossbuild CrossBuildAddr1,FLOW; + crossbuild CrossBuildAddr0,FLOW; +} + +# End of Packet pcode +# - if NOT end-of-packet propogate packet context bits and skip further checks +# - if end-of-packet include CrossBuild and EndOfLoop pcode +EndPacket: is (parse=1 | parse=2) & PropogateLoopCfg [ globalset(inst_next,packetBits); ] { } # this is not end-of-packet - propogate packetBits and useLoopCfg if needed +EndPacket: EndOfLoop is (parse=0 | parse=3) & CrossBuild & EndOfLoop { # EndOfLoop will propogate useLoopCfg if needed + build CrossBuild; + build EndOfLoop; +} + +# End of First/Left packed 'EE' instruction helper +EndPackedLeft: "; "^instruction is instruction [ phase = 5; ] { build instruction; } + +# End of Second/Left packed 'EE' instruction helper +EndPackedRight: is EndPacket [ phase = 6; ] { build EndPacket; } # resume EndPacket processing + + +# +# MACROS +# + +# +# frame layout +# +# +-----------+ +# | | <- SP.new +# | local | +# | | +# | | +# +-----------+ +# | saved FP | <- FP.new +# +-----------+ +# | saved LR | +# +-----------+ +# | | (initial SP) +# + +# NOTE: allocframe and dealloc_frame macro should be invoked from the +# <>, <> or <> pcode section only + +macro deallocframe(reg) { + ptr:4 = reg; + FP = *[ram]:4 ptr; + ptr = ptr + 4; + LR = (*[ram]:4 ptr) ^ FRAMEKEY; + SP = ptr + 4; +} + +macro allocframe(reg,sze) { + ptr:4 = reg - 4; + *[ram]:4 ptr = (LR ^ FRAMEKEY); + ptr = ptr - 4; + *[ram]:4 ptr = FP; + FP = ptr; + reg = ptr - zext(sze); +} + +# +# INSTRUCTIONS +# +# Pattern convention: +# '-' indicates don't-care bit (bit should not be constrained) +# '+' indicates don't care bit (bit should be constrained as '0') +# + + +# (v2,8) abs -- "Rd32 = abs ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:abs Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x04 & Rd5 & rs5 & $(END_PACKET) { + neg:1 = (rs5 s< 0); + Rd5 = (zext(neg) * -rs5) + (zext(!neg) * rs5); + build EndPacket; +} + +# (v2,8) abs -- "Rd32 = abs ( Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 0 1 d d d d d + +define pcodeop absSat; + +:abs":sat" Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x05 & Rd5 & rs5 & $(END_PACKET) { + + pos:1 = (rs5 s>= 0); + toobig:1 = (rs5 == 0x80000000); # Only one saturation case + Rd5 = (zext(pos) * rs5) + (zext(!pos) * ((zext(toobig) * 0x7fffffff) + (zext(!toobig) * -rs5))); + build EndPacket; + <> + $(OVF) = $(OVF) | toobig; +} + +# (v2,8) abs -- "Rdd32 = abs ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 1 0 d d d d d + +:abs Rdd5,rss5 EndPacket is iclass=0x8 & op2127=0x04 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) +{ + neg:1 = (rss5 s< 0); + Rdd5 = (zext(neg) * -rss5) + (zext(!neg) * rss5); + build EndPacket; +} + +# (v2,11) add -- "Rd32 = add ( Rs32 , #s16x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 1 i i i i i i i s s s s s P P i i i i i i i i i d d d d d + +:add Rd5,rs5,Simm32_2127_0513x EndPacket is iclass=0xb & Rd5 & rs5 & Simm32_2127_0513x & $(END_PACKET) { + Rd5 = rs5 + Simm32_2127_0513x; + build EndPacket; +} + +# (v2,15) add -- "Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t + + + d d d d d + +:add Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x18 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = rs5 + rt5; + build EndPacket; +} + +# (v4,15) add -- "Rd32 = add ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 0 1 0 s s s s s P P + t t t t t + + + d d d d d + +:add^":sat" Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x32 & rs5 & op13=0 & rt5 & op0507=0x0 & Rd5 & $(END_PACKET) +{ + sat:1 = scarry(rs5, rt5); + addSat32(Rd5, rs5, rt5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,13) add -- "Rd32 = add ( Rs32 , Rt32 ) :sat :deprecated" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 0 0 s s s s s P P + t t t t t 0 + + d d d d d + +:add^":sat:deprecated" Rd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x2c & rs5 & op13=0 & rt5 & op0507=0x0 & Rd5 & $(END_PACKET) +{ + sat:1 = scarry(rs5, rt5); + addSat32(Rd5, rs5, rt5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v4,13) add -- "Rd32 = add ( Rs32 , add ( Ru32 , #s6x ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 1 0 i i s s s s s P P i d d d d d i i i u u u u u +# +# (v4,13) add -- "Rd32 = add ( Rs32 , sub ( #s6x , Ru32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 1 1 i i s s s s s P P i d d d d d i i i u u u u u + +AddSubOp23: "add("ru5,Simm32_2122_13_0507x")" is op23=0 & ru5 & Simm32_2122_13_0507x { + tmp:4 = ru5 + Simm32_2122_13_0507x; + export tmp; +} +AddSubOp23: "sub("Simm32_2122_13_0507x,ru5")" is op23=1 & ru5 & Simm32_2122_13_0507x { + tmp:4 = Simm32_2122_13_0507x - ru5; + export tmp; +} + +:add Rd0812,rs5,AddSubOp23 EndPacket is iclass=13 & op2427=11 & Rd0812 & rs5 & AddSubOp23 & $(END_PACKET) { + Rd0812 = rs5 + AddSubOp23; + build EndPacket; +} + +# (v4,13) add -- "Rd32 = add ( Ru32 , mpyi ( #u6:2 , Rs32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 1 0 i i s s s s s P P i d d d d d i i i u u u u u +# +# (v4,13) add -- "Rd32 = add ( Ru32 , mpyi ( Rs32 , #u6x ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 1 1 i i s s s s s P P i d d d d d i i i u u u u u + +MpyiOp23: "mpyi("Uimm32_2122_13_0507_shift2,rs5")" is op23=0 & rs5 & Uimm32_2122_13_0507_shift2 { + tmp:4 = rs5 * Uimm32_2122_13_0507_shift2; + export tmp; +} +MpyiOp23: "mpyi("Uimm32_2122_13_0507x,rs5")" is op23=1 & rs5 & Uimm32_2122_13_0507x { + tmp:4 = rs5 * Uimm32_2122_13_0507x; + export tmp; +} + +:add Rd0812,ru5,MpyiOp23 EndPacket is iclass=13 & op2427=15 & Rd0812 & ru5 & MpyiOp23 & $(END_PACKET) { + Rd0812 = ru5 + MpyiOp23; + build EndPacket; +} + +# (v4,13) add -- "Rd32 = add ( #u6x , mpyi ( Rs32 , #U6 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 0 0 I i i s s s s s P P i d d d d d i i i I I I I I + +MpyiRs32U6: "mpyi("rs5,Uimm8_23_0004")" is rs5 & Uimm8_23_0004 { + tmp:4 = rs5 * zext(Uimm8_23_0004); + export tmp; +} + +:add Rd0812,Uimm32_2122_13_0507x,MpyiRs32U6 EndPacket is iclass=13 & op2427=8 & Rd0812 & Uimm32_2122_13_0507x & MpyiRs32U6 & $(END_PACKET) { + Rd0812 = Uimm32_2122_13_0507x + MpyiRs32U6; + build EndPacket; +} + +# (v4,13) add -- "Rd32 = add ( #u6x , mpyi ( Rs32 , Rt32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 1 1 0 i i s s s s s P P i t t t t t i i i d d d d d + +MpyiRs32Rt32: "mpyi("rs5,rt5")" is rs5 & rt5 { + tmp:4 = rs5 * rt5; + export tmp; +} + +:add Rd5,Uimm32_2122_13_0507x,MpyiRs32Rt32 EndPacket is iclass=13 & op2327=0x0e & Rd5 & Uimm32_2122_13_0507x & MpyiRs32Rt32 & $(END_PACKET) { + Rd5 = Uimm32_2122_13_0507x + MpyiRs32Rt32; + build EndPacket; +} + +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 1 + d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 + d d d d d + +:add Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op13=0 & op7=0 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) +{ + Rd5 = sext(rt5L + Rs5HL06); + build EndPacket; +} + +# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.h ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.l ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:add^":<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op13=0 & op7=0 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +{ + Rd5 = zext(Rs5HL05 + Rt5HL06) << 16; + build EndPacket; +} + +# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.h ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.l ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:add^":sat:<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op13=0 & op7=1 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +{ + temp:2 = 0; + addSat16(temp, Rs5HL05, Rt5HL06); + Rd5 = zext(temp) << 16; + sat:1 = scarry(Rt5HL06, Rs5HL05); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 + d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 0 + d d d d d + +:add^":sat" Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op13=0 & op7=1 & op5=0 & Rs5HL06 & rt5L & Rd5 & $(END_PACKET) +{ + temp:2 = 0; + addSat16(temp, Rs5HL06, rt5L); + Rd5 = zext(temp); + sat:1 = scarry(Rs5HL06, rt5L); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v4,8) add -- "Rd32 = add ( clb ( Rs32 ) , #s6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 1 s s s s s P P i i i i i i 0 0 0 d d d d d + +ClbRs: "clb("^rs5")" is rs5 { cnt:4 = countLeadingBits(rs5); export cnt; } + +:add Rd5,ClbRs,Simm8_0813 EndPacket is iclass=8 & op2127=0x61 & op0507=0 & Rd5 & ClbRs & Simm8_0813 & $(END_PACKET) +{ + Rd5 = ClbRs + sext(Simm8_0813); + build EndPacket; +} + +# (v4,8) add -- "Rd32 = add ( clb ( Rss32 ) , #s6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P i i i i i i 0 1 + d d d d d + +ClbRss: "clb("^rss5")" is rss5 { cnt:4 = countLeadingBits(rss5); export cnt; } + +:add Rd5,ClbRss,Simm8_0813 EndPacket is iclass=8 & op2127=0x43 & op0507=2 & Rd5 & ClbRss & Simm8_0813 & $(END_PACKET) +{ + Rd5 = ClbRss + sext(Simm8_0813); + build EndPacket; +} + +# (v4,6) add -- "Rd32 = add ( pc , #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 P P + i i i i i i + + d d d d d + +:assign Rd5,PacketPC EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & op13=0 & op0506=0 & i0712=0 & immext=0 & Rd5 & PacketPC & $(END_PACKET) +{ + Rd5 = PacketPC; + build EndPacket; +} + +:add Rd5,PacketPC,Uimm32_0712x EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & op13=0 & op0506=0 & Rd5 & PacketPC & Uimm32_0712x & $(END_PACKET) +{ + Rd5 = PacketPC + Uimm32_0712x; + build EndPacket; +} + +# (v2,13) add -- "Rdd32 = add ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +:add Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rss5 + rtt5; + build EndPacket; +} + +# (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop addRawHi; + +:add":raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rtt5 + sext(rss5[32,32]); + build EndPacket; +} + +# (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop addRawLo; + +:add":raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x6 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rtt5 + sext(rss5[0,32]); + build EndPacket; +} + +# (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop addSat; + +:add":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = addSat(rss5, rtt5); + build EndPacket; +} + +# (v4,12) add -- "Rdd32 = add ( Rss32 , Rtt32 , Px4 ) :carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 0 1 1 0 s s s s s P P + t t t t t + x x d d d d d + +:add":carry" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=0xc & op2127=0x16 & rss5 & op13=0 & rtt5 & op7=0 & Rdd5 & pu0506 & pu0506_ & $(END_PACKET) +unimpl + +# (v2,14) add -- "Rx32 += add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 1 0 0 + + s s s s s P P + i i i i i i i i x x x x x + +:add+= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2127=0x10 & rs5 & op13=0 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 + rs5 + Simm32_0512x; + build EndPacket; +} + +# (v2,14) add -- "Rx32 += add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 1 x x x x x + +:add+= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x78 & rs5 & op13=0 & op0507=0x1 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 + rs5 + rt5; + build EndPacket; +} + +# (v2,14) add -- "Rx32 -= add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 1 0 1 + + s s s s s P P + i i i i i i i i x x x x x + +:add-= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2127=0x14 & op13=0 & rs5 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 - rs5 + Simm32_0512x; + build EndPacket; +} + +# (v2,14) add -- "Rx32 -= add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P + t t t t t + 0 1 x x x x x + +:add-= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7c & rs5 & op13=0 & rt5 & op0507=0x1 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 - ( rs5 + rt5 ); + build EndPacket; +} + +# (v4,13) add -- "Rx32 = add ( #u8x , asl ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 1 0 + +# +# (v4,13) add -- "Rx32 = add ( #u8x , lsr ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 1 0 + + +:add Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=4 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +{ + Rx5 = Uimm32_2123_13_0507_03x + ShiftRx_D04_I0812; + build EndPacket; +} + +# (v4,14) add -- "Rx32 = add ( Ru32 , mpyi ( Rx32 , Rs32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 1 1 0 0 0 s s s s s P P + x x x x x + + + u u u u u + +MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { + tmp:4 = rs5 * rt5; + export tmp; +} + +:add Rd0812,ru5,MpyiRx32Rs32 EndPacket is iclass=14 & op2127=0x18 & op13=0 & op0507=0 & Rd0812 & MpyiRx32Rs32 & ru5 & $(END_PACKET) +{ + Rd0812 = ru5 + MpyiRx32Rs32; + build EndPacket; +} + +# (v2,7) add -- "if ( Pu4 ) Rd32 = add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 0 0 u u s s s s s P P 0 i i i i i i i i d d d d d +# +# (v2,7) add -- "if ( ! Pu4 ) Rd32 = add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 0 1 u u s s s s s P P 0 i i i i i i i i d d d d d +# +# (v2,7) add -- "if ( Pu4 .new ) Rd32 = add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 0 0 u u s s s s s P P 1 i i i i i i i i d d d d d +# +# (v2,7) add -- "if ( ! Pu4 .new ) Rd32 = add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 0 1 u u s s s s s P P 1 i i i i i i i i d d d d d + +:add^PuCond2122_N13_S23 rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2427=4 & PuCond2122_N13_S23 & rs5 & Simm32_0512x & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond2122_N13_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 + Simm32_0512x; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# if ([!]Pu4[.new]) Rd32 = Rs32 ( simplification of if ([!]Pu4[.new]) Rd32 = add(Rs32,#0) +:assign^PuCond2122_N13_S23 rd5,rs5 EndPacket is iclass=7 & op2427=4 & PuCond2122_N13_S23 & rs5 & op0512=0 & immexted=0 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond2122_N13_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,15) add -- "if ( Pu4 ) Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) add -- "if ( ! Pu4 ) Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) add -- "if ( Pu4 .new ) Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) add -- "if ( ! Pu4 .new ) Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 1 t t t t t 1 u u d d d d d + +:add^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x16 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 + rt5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,12) addasl -- "Rd32 = addasl ( Rt32 , Rs32 , #u3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 0 0 0 0 s s s s s P P 0 t t t t t i i i d d d d d + +:addasl Rd5,rt5,rs5,Uimm3_0507 EndPacket is iclass=12 & op2127=0x20 & op13=0 & Rd5 & rt5 & rs5 & Uimm3_0507 & $(END_PACKET) +{ + Rd5 = rt5 + (rs5 << Uimm3_0507); + build EndPacket; +} + +# (v2,6) all8 -- "Pd4 = all8 ( Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 0 1 0 - - s s P P 0 - - - - - - - - - - - d d + +:all8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5d & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((pu1617 == 0xff) * 0xff); + build EndPacket; +} + +# (v2,10) allocframe -- "allocframe ( #u11:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 0 1 1 1 0 1 P P 0 0 0 i i i i i i i i i i i + +:allocframe Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & op1620=0x1d & op1113=0 & Uimm16_0010_shift3 & $(END_PACKET) { + allocframe(SP, Uimm16_0010_shift3); + build EndPacket; +} + +# (v2,10) allocframe -- "allocframe ( Rx32, #u11:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 0 x x x x x P P 0 0 0 i i i i i i i i i i i + +:allocframe rx5, Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & rx5 & op1113=0 & Uimm16_0010_shift3 & $(END_PACKET) { + allocframe(rx5, Uimm16_0010_shift3); + build EndPacket; +} + +# (v4,6) and -- "Pd4 = and ( Ps4 , and ( Pt4 , Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 0 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) and -- "Pd4 = and ( Ps4 , and ( Pt4 , ! Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 0 0 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) and -- "Pd4 = and ( Ps4 , or ( Pt4 , Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 1 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) and -- "Pd4 = and ( Ps4 , or ( Pt4 , ! Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 0 1 1 + + s s P P 0 - - - t t u u - - - - d d + +:and Pd2,pu1617,PredLogic_L21_S23_P0809_P0607 EndPacket is iclass=6 & op2427=0xb & op22=0 & op1820=4 & pu1617 & Pd2 & PredLogic_L21_S23_P0809_P0607 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 & PredLogic_L21_S23_P0809_P0607); + build EndPacket; +} + +# (v2,6) and -- "Pd4 = and ( Pt4 , Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 0 0 - - s s P P 0 - - - t t - - - - - - d d + +:and Pd2,pu0809,pu1617 EndPacket is iclass=6 & op2127=0x58 & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 & pu0809); + build EndPacket; +} + +# (v2,6) and -- "Pd4 = and ( Pt4 , ! Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 1 1 0 - - s s P P 0 - - - t t - - - - - - d d + +:and Pd2,pu0809,NotPs2 EndPacket is iclass=6 & op2127=0x5b & op1820=0 & op1013=0 & op0207=0 & pu0809 & NotPs2 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (NotPs2 & pu0809); + build EndPacket; +} + +# (v2,7) and -- "Rd32 = and ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 1 0 0 0 i s s s s s P P i i i i i i i i i d d d d d + +:and Rd5,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x18 & Rd5 & rs5 & Simm32_21_0513x & $(END_PACKET) { + Rd5 = rs5 & Simm32_21_0513x; + build EndPacket; +} + +# (v2,15) and -- "Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 0 0 0 s s s s s P P - t t t t t - - - d d d d d + +:and Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x08 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = rs5 & rt5; + build EndPacket; +} + +# (v4,15) and -- "Rd32 = and ( Rt32 , ~ Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 1 0 0 s s s s s P P - t t t t t - - - d d d d d + +:and Rd5,rt5,OnesCompRs5 EndPacket is iclass=15 & op2127=0x0c & Rd5 & OnesCompRs5 & rt5 & $(END_PACKET) { + Rd5 = rt5 & OnesCompRs5; + build EndPacket; +} + +# (v2,13) and -- "Rdd32 = and ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 0 0 d d d d d + +:and Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1f & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = rss5 & rtt5; + build EndPacket; +} + +# (v4,13) and -- "Rdd32 = and ( Rtt32 , ~ Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 0 1 d d d d d + +:and Rdd5,rtt5,OnesCompRss5 EndPacket is iclass=13 & op2127=0x1f & op0507=1 & Rdd5 & OnesCompRss5 & rtt5 & $(END_PACKET) { + Rdd5 = rtt5 & OnesCompRss5; + build EndPacket; +} + +# (v4,14) and -- "Rx32 &= and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 0 0 x x x x x + +:and&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 & rs5 & rt5; + build EndPacket; +} + +# (v4,14) and -- "Rx32 &= and ( Rs32 , ~ Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 0 1 x x x x x + +:and&= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=1 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 & rs5 & OnesCompRt5; + build EndPacket; +} + +# (v4,13) and -- "Rx32 = and ( #u8x , asl ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 0 0 - +# +# (v4,13) and -- "Rx32 = and ( #u8x , lsr ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 0 0 + + +:and Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=0 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +{ + Rx5 = Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812; + build EndPacket; +} + +# (v4,14) and -- "Rx32 ^= and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 1 0 x x x x x + +:and"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=2 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 ^ (rs5 & rt5); + build EndPacket; +} + +# (v4,14) and -- "Rx32 ^= and ( Rs32 , ~ Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 1 0 x x x x x + +:and"^=" Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=2 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 ^ (rs5 & OnesCompRt5); + build EndPacket; +} + +# (v4,13) and -- "Rx32 |= and ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 0 0 0 i s s s s s P P i i i i i i i i i x x x x x + +:and|= Rd5,rs5,Simm32_21_0513x EndPacket is iclass=13 & op2227=0x28 & Rd5 & rd5 & Simm32_21_0513x & rs5 & $(END_PACKET) { + Rd5 = rd5 | (rs5 & Simm32_21_0513x); + build EndPacket; +} + +# (v4,14) and -- "Rx32 |= and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 1 1 x x x x x + +:and|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 | (rs5 & rt5); + build EndPacket; +} + +# (v4,14) and -- "Rx32 |= and ( Rs32 , ~ Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 0 0 x x x x x + +:and|= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=0 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 | (rs5 & OnesCompRt5); + build EndPacket; +} + +# (v2,15) and -- "if ( Pu4 ) Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) and -- "if ( ! Pu4 ) Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) and -- "if ( Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) and -- "if ( ! Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 1 t t t t t 1 u u d d d d d + +:and^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 & rt5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,6) any8 -- "Pd4 = any8 ( Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 0 0 0 + + s s P P 0 + + + + + + + + + + + d d + +:any8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5c & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((pu1617 != 0) * 0xff); + build EndPacket; +} + +# any8 -- "Pd4 = any8 ( vcmpb.eq ( Rss32 , Rtt32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 0 0 + + + d d + +define pcodeop vcmpb.eq; + +VcmpbEq: "vcmpb.eq("^rss5,rtt5^")" is rss5 & rtt5 { tmp:1 = vcmpb.eq(rss5,rtt5); export tmp; } + +:any8 Pd2,VcmpbEq EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) { + Pd2 = Pd2 & ((VcmpbEq != 0) * 0xff); + build EndPacket; +} + +# (v4,13) any8 -- "Pd4 = !any8 ( vcmpb.eq ( Rss32 , Rtt32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 0 1 - - - d d + +:any8! Pd2,VcmpbEq EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=8 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) { + Pd2 = Pd2 & ~((VcmpbEq != 0) * 0xff); + build EndPacket; +} + + +# (v2,8) rol -- "Rd32 = rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 1 1 d d d d d + +:rol Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=3 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = (rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1); + build EndPacket; +} + +# (v2,8) asl -- "Rd32 = asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d + +:asl Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=2 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rs5 << Uimm8_0812; + build EndPacket; +} + +# (v2,8) asl -- "Rd32 = asl ( Rs32 , #u5 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d + +define pcodeop aslSat; + +:asl":sat" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x62 & op13=0 & op0507=2 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = aslSat(rs5, Uimm8_0812); + build EndPacket; +} + +# (v2,12) asl -- "Rd32 = asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +:asl Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + Rd5 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + build EndPacket; +} + +# (v2,12) asl -- "Rd32 = asl ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:asl":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x30 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = aslSat(rs5, rt5); + build EndPacket; +} + +# (v2,8) asl -- "Rdd32 = asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 1 0 d d d d d + +:asl Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=2 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rss5 << Uimm8_0813; + build EndPacket; +} + +# (v2,8) rol -- "Rdd32 = rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 1 1 d d d d d + +:rol Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=3 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = (rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1); + build EndPacket; +} + +# (v2,12) asl -- "Rdd32 = asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:asl Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=4 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + Rdd5 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + build EndPacket; +} + +# (v2,8) asl -- "Rx32 &= asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 1 0 x x x x x + +:asl&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 & (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 &= rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 1 1 x x x x x + +:rol&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 & ((rs5 << Uimm8_0812) | zext((rs5 s<0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rx32 &= asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 1 0 + x x x x x + +:asl&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 & result; + build EndPacket; +} + +# (v2,8) asl -- "Rx32 += asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 1 0 x x x x x + +:asl+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 + (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 += rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 1 1 x x x x x + +:rol+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 + ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rx32 += asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 1 0 + x x x x x + +:asl+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 + result; + build EndPacket; +} + +# (v2,8) asl -- "Rx32 -= asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 1 0 x x x x x + +:asl-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 - (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 -= rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 1 1 x x x x x + +:rol-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 - ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rx32 -= asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 1 0 + x x x x x + +:asl-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 - result; + build EndPacket; +} + +# (v2,8) asl -- "Rx32 ^= asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 1 0 x x x x x + +:asl"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 ^ (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 ^= rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 1 1 x x x x x + +:rol"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 ^ ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); + build EndPacket; +} + +# (v2,8) asl -- "Rx32 |= asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 1 0 x x x x x + +:asl|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 | (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 |= rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 1 1 x x x x x + +:rol|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 | ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rx32 |= asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 1 0 + x x x x x + +:asl|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 | result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 &= asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 1 0 x x x x x + +:asl&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 & (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 &= rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 1 1 x x x x x + +:rol&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 & ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rxx32 &= asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 & result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 += asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 1 0 x x x x x + +:asl+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 + (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 += rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 1 1 x x x x x + +:rol+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 + ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rxx32 += asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 + result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 -= asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 1 0 x x x x x + +:asl-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 - (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 -= rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 1 1 x x x x x + +:rol-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 - ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rxx32 -= asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 - result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 ^= asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 1 0 x x x x x + +:asl"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 ^ (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 ^= rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 1 1 x x x x x + +:rol"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 ^ ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v4,12) asl -- "Rxx32 ^= asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 ^ result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 |= asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 1 0 x x x x x + +:asl|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 | (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 |= rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 1 1 x x x x x + +:rol|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 | ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rxx32 |= asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 | result; + build EndPacket; +} + +# (v2,7) aslh -- "Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 0 + + + + + + + + d d d d d + +:aslh Rd5,rs5 EndPacket is iclass=7 & op2127=0 & op13=0 & op0512=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = rs5 << 16; + build EndPacket; +} + +# (v4,7) aslh -- "if ( Pu4 ) Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 0 0 u u - - - d d d d d +# +# (v4,7) aslh -- "if ( ! Pu4 ) Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 1 0 u u - - - d d d d d +# +# (v4,7) aslh -- "if ( Pu4 .new ) Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 0 1 u u - - - d d d d d +# +# (v4,7) aslh -- "if ( ! Pu4 .new ) Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 1 1 u u - - - d d d d d + +:aslh^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0 & op13=1 & rd5 & rd5_ & SetNRegRd5 & rs5 & PuCond0809_N10_S11 & $(END_PACKET) { + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 << 16; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,8) asr -- "Rd32 = asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d + +:asr Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rs5 s>> Uimm8_0812; + build EndPacket; +} + +# (v2,8) asr -- "Rd32 = asr ( Rs32 , #u5 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d + +:asr":rnd" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x62 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = roundArithmetic(rs5 s>> Uimm8_0812, 1:1); + build EndPacket; +} + +# (v5,8) asr -- "Rdd32 = asr ( Rss32 , #u6 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 0 s s s s s P P i i i i i i 1 1 1 d d d d d + +:asr":rnd" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x06 & op0507=7 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = roundArithmetic(rss5 s>> Uimm8_0813, 1:1); + build EndPacket; +} + +# (v2,12) asr -- "Rd32 = asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +:asr Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + Rd5 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + build EndPacket; +} + +# (v2,12) asr -- "Rd32 = asr ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop asrSat; + +:asr":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x30 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = asrSat(rs5, rt5); + build EndPacket; +} + +# (v2,8) asr -- "Rdd32 = asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 0 0 d d d d d + +:asr Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=0 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rss5 s>> Uimm8_0813; + build EndPacket; +} + +# (v2,12) asr -- "Rdd32 = asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:asr Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=0 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + Rdd5 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + build EndPacket; +} + +# (v2,8) asr -- "Rx32 &= asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 0 0 x x x x x + +:asr&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 & (rs5 s>> Uimm8_0812); + build EndPacket; +} + +# (v2,12) asr -- "Rx32 &= asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 0 0 + x x x x x + +:asr&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 & result; + build EndPacket; +} + +# (v2,8) asr -- "Rx32 += asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 0 0 x x x x x + +:asr+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 + (rs5 s>> Uimm8_0812); + build EndPacket; +} + +# (v2,12) asr -- "Rx32 += asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 0 0 + x x x x x + +:asr+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 + result; + build EndPacket; +} + +# (v2,8) asr -- "Rx32 -= asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 0 0 x x x x x + +:asr-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 - (rs5 s>> Uimm8_0812); + build EndPacket; +} + +# (v2,12) asr -- "Rx32 -= asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 0 0 + x x x x x + +:asr-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 - result; + build EndPacket; +} + +# (v2,8) asr -- "Rx32 |= asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 0 0 x x x x x + +:asr|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 | (rs5 s>> Uimm8_0812); + build EndPacket; +} + +# (v2,12) asr -- "Rx32 |= asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 0 0 + x x x x x + +:asr|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 | result; + build EndPacket; +} + +# (v2,8) asr -- "Rxx32 &= asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 0 0 x x x x x + +:asr&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 & (rss5 s>> Uimm8_0813); + build EndPacket; +} + +# (v2,12) asr -- "Rxx32 &= asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 & result; + build EndPacket; +} + +# (v2,8) asr -- "Rxx32 += asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 0 0 x x x x x + +:asr+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 + (rss5 s>> Uimm8_0813); + build EndPacket; +} + +# (v2,12) asr -- "Rxx32 += asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 + result; + build EndPacket; +} + +# (v2,8) asr -- "Rxx32 -= asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 0 0 x x x x x + +:asr-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 - (rss5 s>> Uimm8_0813); + build EndPacket; +} + +# (v2,12) asr -- "Rxx32 -= asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 - result; + build EndPacket; +} + +# (v4,12) asr -- "Rxx32 ^= asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 ^ result; + build EndPacket; +} + +# (v2,8) asr -- "Rxx32 |= asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 0 0 x x x x x + +:asr|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 | (rss5 s>> Uimm8_0813); + build EndPacket; +} + +# (v2,12) asr -- "Rxx32 |= asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 | result; + build EndPacket; +} + +# (v2,7) asrh -- "Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 0 + + + + + + + + d d d d d + +:asrh Rd5,rs5 EndPacket is iclass=7 & op2127=1 & op13=0 & op0512=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = rs5 s>> 16; + build EndPacket; +} + +# (v4,7) asrh -- "if ( Pu4 ) Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 0 0 u u - - - d d d d d +# +# (v4,7) asrh -- "if ( ! Pu4 ) Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 1 0 u u - - - d d d d d +# +# (v4,7) asrh -- "if ( Pu4 .new ) Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 0 1 u u - - - d d d d d +# +# (v4,7) asrh -- "if ( ! Pu4 .new ) Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 1 1 u u - - - d d d d d + +:asrh^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=1 & op13=1 & rd5 & rd5_ & SetNRegRd5 & rs5 & PuCond0809_N10_S11 & $(END_PACKET) { + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 s>> 16; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,6) assign -- "Cd32 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +:assign Cd5,rs5 EndPacket is iclass=6 & op2127=0x11 & op0513=0 & Cd5 & rs5 & $(END_PACKET) { + # NOTE: Assuming that PC will not be directly assigned + Cd5 = rs5; + build EndPacket; +} + +# (v4,6) assign -- "Cdd32 = Rss32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 1 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +:assign Cdd5,rss5 EndPacket is iclass=6 & op2127=0x19 & op0513=0 & Cdd5 & rss5 & $(END_PACKET) { + # NOTE: Assuming that PC will not be directly assigned + Cdd5 = rss5; + build EndPacket; +} + +# (v4,6) assign -- "Gd32 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +:assign Gd5,rs5 EndPacket is iclass=6 & op2127=0x10 & op0513=0 & Gd5 & rs5 & $(END_PACKET) { + Gd5 = rs5; + build EndPacket; +} + +# (v4,6) assign -- "Gdd32 = Rss32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 1 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +:assign Gdd5,rss5 EndPacket is iclass=6 & op2127=0x18 & op0513=0 & Gdd5 & rss5 & $(END_PACKET) { + Gdd5 = rss5; + build EndPacket; +} + +# (v2,8) assign -- "Pd4 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 0 1 + s s s s s P P + + + + + + + + + + + + d d + +:assign Pd2,rs5 EndPacket is iclass=8 & op2127=0x2a & rs5 & op0213=0 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & rs5:1; + build EndPacket; +} + +# (v2,7) assign -- "Rd32 = #s16x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 0 0 0 i i - i i i i i P P i i i i i i i i i d d d d d + +:assign Rd5,Simm32_2223_1620_0513x EndPacket is iclass=7 & op2427=8 & op21=0 & Rd5 & Simm32_2223_1620_0513x & $(END_PACKET) { + Rd5 = Simm32_2223_1620_0513x; + build EndPacket; +} + +# (v2,6) assign -- "Rd32 = Cs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +:assign Rd5,Cs5 EndPacket is iclass=6 & op2127=0x50 & op0513=0 & Rd5 & Cs5 & $(END_PACKET) { + Rd5 = Cs5; + build EndPacket; +} + +# (v4,6) assign -- "Rd32 = Gs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +:assign Rd5,gs5 EndPacket is iclass=6 & op2127=0x51 & op0513=0 & Rd5 & gs5 & $(END_PACKET) { + Rd5 = gs5; + build EndPacket; +} + +# (v2,8) assign -- "Rd32 = Ps4" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 1 + 1 + + + + s s P P + + + + + + + + + d d d d d + +:assign Rd5,pu1617 EndPacket is iclass=8 & op1827=0x250 & pu1617 & op0513=0 & Rd5 & $(END_PACKET) { + Rd5 = zext( pu1617 ); + build EndPacket; +} + +# (v2,7) assign -- "Rd32 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 1 1 s s s s s P P 0 - - - - - - - - d d d d d + +:assign Rd5,rs5 EndPacket is iclass=7 & op2127=0x03 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = rs5; + build EndPacket; +} + +# (v2,6) assign -- "Rd32 = Ss64" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 1 0 1 + s s s s s s P P + + + + + + + + + d d d d d + +:assign Rd5,ss6 EndPacket is iclass=6 & op2227=0x3a & op0513=0 & Rd5 & ss6 & $(END_PACKET) { + Rd5 = ss6; + build EndPacket; +} + +# (v4,6) assign -- "Rdd32 = Css32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +:assign Rdd5,css5 EndPacket is iclass=6 & op2127=0x40 & op0513=0 & Rdd5 & css5 & $(END_PACKET) { + Rdd5 = css5; + build EndPacket; +} + +# (v4,6) assign -- "Rdd32 = Gss32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +:assign Rdd5,gss5 EndPacket is iclass=6 & op2127=0x41 & op0513=0 & Rdd5 & gss5 & $(END_PACKET) { + Rdd5 = gss5; + build EndPacket; +} + +# (v4,6) assign -- "Rdd32 = Sss64" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 1 1 + + s s s s s s P P + + + + + + + + + d d d d d + +:assign Rdd5,sss6 EndPacket is iclass=6 & op2227=0x3c & op0513=0 & Rdd5 & sss6 & $(END_PACKET) { + Rdd5 = sss6; + build EndPacket; +} + +# (v2,7) assign -- "Rx32.h = #u16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 0 i i 1 x x x x x P P i i i i i i i i i i i i i i + +:assign Rx5H,Uimm16_2223_0013 EndPacket is iclass=7 & op2427=2 & op21=1 & Rx5H & Uimm16_2223_0013 & $(END_PACKET) { + Rx5H = Uimm16_2223_0013; + build EndPacket; +} + +# (v2,7) assign -- "Rx32.l = #u16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 1 i i 1 x x x x x P P i i i i i i i i i i i i i i + +:assign Rx5L,Uimm16_2223_0013 EndPacket is iclass=7 & op2427=1 & op21=1 & Rx5L & Uimm16_2223_0013 & $(END_PACKET) { + Rx5L = Uimm16_2223_0013; + build EndPacket; +} + +# (v2,6) assign -- "Sd64 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 1 1 0 0 + s s s s s P P + + + + + + + + d d d d d d + +:assign Sd6,rs5 EndPacket is iclass=6 & op2127=0x38 & op0613=0 & Sd6 & rs5 & $(END_PACKET) { + Sd6 = rs5; + build EndPacket; +} + +# (v4,6) assign -- "Sdd64 = Rss32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 1 0 + + s s s s s P P + + + + + + + + d d d d d d + +:assign Sdd6,rss5 EndPacket is iclass=6 & op2127=0x68 & op0613=0 & Sdd6 & rss5 & $(END_PACKET) { + Sdd6 = rss5; + build EndPacket; +} + +# (v2,7) assign -- "if ( Pu4 ) Rd32 = #s12x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 0 0 u u 0 i i i i P P 0 i i i i i i i i d d d d d +# +# (v2,7) assign -- "if ( ! Pu4 ) Rd32 = #s12x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 0 1 u u 0 i i i i P P 0 i i i i i i i i d d d d d +# +# (v2,7) assign -- "if ( Pu4 .new ) Rd32 = #s12x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 0 0 u u 0 i i i i P P 1 i i i i i i i i d d d d d +# +# (v2,7) assign -- "if ( ! Pu4 .new ) Rd32 = #s12x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 0 1 u u 0 i i i i P P 1 i i i i i i i i d d d d d + +:assign^PuCond2122_N13_S23 rd5,Simm32_1619_0512x EndPacket is iclass=7 & op2427=0xe & op20=0 & PuCond2122_N13_S23 & rd5 & rd5_ & SetNRegRd5 & Simm32_1619_0512x & $(END_PACKET) { + build PuCond2122_N13_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = Simm32_1619_0512x; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,10) barrier -- "barrier" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 0 + + + + + P P + + + + + + + + + + + + + + + +define pcodeop barrier; + +:barrier EndPacket is iclass=10 & op2127=0x40 & op1620=0 & op0013=0 & $(END_PACKET) { + barrier(); + build EndPacket; +} + +# (v2,8) bitsclr -- "Pd4 = bitsclr ( Rs32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 1 0 0 s s s s s P P i i i i i i + + + + + + d d + +:bitsclr Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2c & op0207=0 & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) { + isClr:1 = (rs5 & zext(Uimm8_0813)) == 0; + Pd2 = Pd2 & (isClr * 0xff); + build EndPacket; +} + +# (v4,8) bitsclr -- "Pd4 = ! bitsclr ( Rs32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 1 0 1 s s s s s P P i i i i i i + + + + + + d d + +:bitsclr! Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2d & op0207=0 & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) { + notClr:1 = (rs5 & zext(Uimm8_0813)) != 0; + Pd2 = Pd2 & (notClr * 0xff); + build EndPacket; +} + +# (v2,12) bitsclr -- "Pd4 = bitsclr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t + + + + + + d d + +:bitsclr Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3c & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + isClr:1 = (rs5 & rt5) == 0; + Pd2 = Pd2 & (isClr * 0xff); + build EndPacket; +} + +# (v4,12) bitsclr -- "Pd4 = ! bitsclr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 0 1 s s s s s P P + t t t t t + + + + + + d d + +:bitsclr! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3d & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + notClr:1 = (rs5 & rt5) != 0; + Pd2 = Pd2 & (notClr * 0xff); + build EndPacket; +} + +# (v4,8) bitsplit -- "Rdd32 = bitsplit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 1 0 + d d d d d + +:bitsplit Rdd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=4 & Rdd5 & rdd5h_ & rd5_ & rs5 & Uimm8_0812 & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = rs5 >> Uimm8_0812; + mask:4 = ~(-1 << Uimm8_0812); + rd5_ = rs5 & mask; + build EndPacket; +} + +# (v4,13) bitsplit -- "Rdd32 = bitsplit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 0 + + 1 s s s s s P P + t t t t t + + + d d d d d + +:bitsplit Rdd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x21 & op13=0 & op0507=0 & Rdd5 & rdd5h_ & rd5_ & rs5 & rt5 & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + cnt:4 = rt5 & 0x1f; + rdd5h_ = rs5 >> cnt; + mask:4 = ~(-1 << cnt); + rd5_ = rs5 & mask; + build EndPacket; +} + +# (v2,12) bitsset -- "Pd4 = bitsset ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t + + + + + + d d + +:bitsset Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3a & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + isSet:1 = (rs5 & rt5) == rt5; + Pd2 = Pd2 & (isSet * 0xff); + build EndPacket; +} + +# (v4,12) bitsset -- "Pd4 = ! bitsset ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t + + + + + + d d + +:bitsset! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3b & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + notSet:1 = (rs5 & rt5) != rt5; + Pd2 = Pd2 & (notSet * 0xff); + build EndPacket; +} + +# (v4,13) boundscheck -- "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 1 0 1 + + + d d + +:boundscheck":raw:hi" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x28 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + upper:4 = rtt5(4); + lower:4 = rtt5:4; + src:4 = rss5(4); + # TODO: unclear if comparison should be signed or unsigned + bool:1 = (src >= lower) && (src < upper); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) boundscheck -- "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 1 0 0 + + + d d + +:boundscheck":raw:lo" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x20 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + upper:4 = rtt5(4); + lower:4 = rtt5:4; + src:4 = rss5:4; + # TODO: unclear if comparison should be signed or unsigned + bool:1 = (src >= lower) && (src < upper); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,8) brev -- "Rd32 = brev ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 1 0 d d d d d + +:brev Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=0x06 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = bitReverse(rs5); + build EndPacket; +} + +# (v4,8) brev -- "Rdd32 = brev ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 1 0 d d d d d + +:brev Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = bitReverse(rss5); + build EndPacket; +} + +# (v2,6) brkpt -- "brkpt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 0 0 - - - - - + +define pcodeop brkpt; + +:brkpt EndPacket is iclass=6 & op2127=0x61 & op0507=0 & $(END_PACKET) { + brkpt(); + build EndPacket; +} + +# (v2,5) call -- "call #r22:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 0 1 i i i i i i i i i P P i i i i i i i i i i i i i 0 + +:call RelDest22x EndPacket is iclass=5 & op2527=5 & op0=0 & RelDest22x & $(END_PACKET) { + build EndPacket; + <> + LR = ReturnAddr; + call RelDest22x; +} + +# (v2,5) call -- "if ( Pu4 ) call #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 1 i i 0 i i i i i P P i 0 0 + u u i i i i i i i + +# +# (v2,5) call -- "if ( ! Pu4 ) call #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 1 i i 1 i i i i i P P i 0 0 + u u i i i i i i i + + +:call^FlowCondUU RelDest15x EndPacket is iclass=5 & op2427=0xd & op1112=0 & op10=0 & op0=0 & FlowCondUU & RelDest15x & $(END_PACKET) { + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + LR = ReturnAddr; + call RelDest15x; + +} + +# (v2,5) callr -- "callr Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 0 1 0 1 s s s s s P P + + + + + + + + + + + + + + + +:callr rs5 EndPacket is iclass=5 & op2127=0x05 & op0013=0 & rs5 & $(END_PACKET) { + dest:4 = rs5; + build EndPacket; + <> + LR = ReturnAddr; + call [dest]; +} + +# callrh -- "callrh Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 0 1 1 0 s s s s s P P + + + + + + + + + + + + + + + +:callrh rs5 EndPacket is iclass=5 & op2127=0x06 & op0013=0 & rs5 & $(END_PACKET) { + dest:4 = rs5; + build EndPacket; + <> + LR = ReturnAddr; + call [dest]; +} + +# (v2,5) callr -- "if ( Pu4 ) callr Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 1 0 0 0 s s s s s P P + + + + u u + + + + + + + + +# +# (v2,5) callr -- "if ( ! Pu4 ) callr Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 1 0 0 1 s s s s s P P + + + + u u + + + + + + + + + +:callr^FlowCondUU rs5 EndPacket is iclass=5 & op2227=0x04 & op1013=0 & op0007=0 & rs5 & FlowCondUU & $(END_PACKET) { + dest:4 = rs5; + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + LR = ReturnAddr; + call [dest]; + +} + +# (v2,6) ciad -- "ciad ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 1 1 + + + + + + +:ciad rs5 EndPacket is iclass=6 & op2127=0x20 & op0507=3 & rs5 & $(END_PACKET) { + S22 = S22 & ~(rs5); + build EndPacket; +} + +# (v2,8) cl0 -- "Rd32 = cl0 ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 0 1 d d d d d + +:cl0 Rd5,rs5 EndPacket is iclass=8 & op2127=0x60 & op0507=5 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = lzcount(rs5); + build EndPacket; +} + +# (v2,8) cl0 -- "Rd32 = cl0 ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 0 1 0 d d d d d + +:cl0 Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=2 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = lzcount(rss5); + build EndPacket; +} + +# (v2,8) cl1 -- "Rd32 = cl1 ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 1 0 d d d d d + +:cl1 Rd5,rs5 EndPacket is iclass=8 & op2127=0x60 & op0507=6 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = lzcount(~rs5); + build EndPacket; +} + +# (v2,8) cl1 -- "Rd32 = cl1 ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:cl1 Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=4 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = lzcount(~rss5); + build EndPacket; +} + +# (v2,8) clb -- "Rd32 = clb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:clb Rd5,rs5 EndPacket is iclass=8 & op2127=0x60 & op0507=4 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = countLeadingBits(rs5); + build EndPacket; +} + +# (v2,8) clb -- "Rd32 = clb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 0 0 0 d d d d d + +:clb Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=0 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = countLeadingBits(rss5); + build EndPacket; +} + +# (v66,8) clip -- "Rd32 = clip ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 + + + + + 1 0 1 d d d d d + +define pcodeop clip; +:clip Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=5 & rs5 & Rd5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = clip(rs5, Uimm8_0812); + build EndPacket; +} + +# (v2,8) clrbit -- "Rd32 = clrbit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P 0 i i i i i 0 0 1 d d d d d + +:clrbit Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x66 & op13=0 & op0507=1 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + Rd5 = rs5 & ~mask; + build EndPacket; +} + +# (v2,12) clrbit -- "Rd32 = clrbit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:clrbit Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0507=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { + mask:4 = 1 << rt5; + Rd5 = rs5 & ~mask; + build EndPacket; +} + +# (v2,7) cmp.eq -- "Pd4 = cmp.eq ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 0 0 i s s s s s P P i i i i i i i i i 0 0 0 d d + +:cmp.eq Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x14 & op0204=0 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 == Simm32_21_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,7) cmp.eq -- "Pd4 = ! cmp.eq ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 0 0 i s s s s s P P i i i i i i i i i 1 0 0 d d + +:cmp.eq! Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x14 & op0204=4 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 != Simm32_21_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,15) cmp.eq -- "Pd4 = cmp.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 0 0 s s s s s P P + t t t t t + + + 0 0 0 d d + +:cmp.eq Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x10 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 == rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,15) cmp.eq -- "Pd4 = ! cmp.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 0 0 s s s s s P P + t t t t t + + + 1 0 0 d d + +:cmp.eq! Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x10 & op13=0 & op0207=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 != rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,13) cmp.eq -- "Pd4 = cmp.eq ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 + + s s s s s P P + t t t t t 0 0 + + + + d d + +:cmp.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x14 & op13=0 & op0207=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + bool:1 = (rss5 == rtt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,7) cmp.gt -- "Pd4 = cmp.gt ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 0 1 i s s s s s P P i i i i i i i i i 0 0 0 d d + +:cmp.gt Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x15 & op0204=0 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 s> Simm32_21_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,7) cmp.gt -- "Pd4 = ! cmp.gt ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 0 1 i s s s s s P P i i i i i i i i i 1 0 0 d d + +:cmp.gt! Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x15 & op0204=4 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 s<= Simm32_21_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,15) cmp.gt -- "Pd4 = cmp.gt ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 1 0 s s s s s P P + t t t t t + + + 0 0 0 d d + +:cmp.gt Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x12 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 s> rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,15) cmp.gt -- "Pd4 = ! cmp.gt ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 1 0 s s s s s P P + t t t t t + + + 1 0 0 d d + +:cmp.gt! Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x12 & op13=0 & op0207=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 s<= rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,13) cmp.gt -- "Pd4 = cmp.gt ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 + + s s s s s P P + t t t t t 0 1 + + + + d d + +:cmp.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x14 & op13=0 & op0207=0x10 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + bool:1 = (rss5 s> rtt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,7) cmp.gtu -- "Pd4 = cmp.gtu ( Rs32 , #u9x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 1 0 0 s s s s s P P i i i i i i i i i 0 0 0 d d + +:cmp.gtu Pd2,rs5,Uimm32_0513x EndPacket is iclass=7 & op2127=0x2c & op0204=0 & rs5 & Uimm32_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 > Uimm32_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,7) cmp.gtu -- "Pd4 = ! cmp.gtu ( Rs32 , #u9x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 1 0 0 s s s s s P P i i i i i i i i i 1 0 0 d d + +:cmp.gtu! Pd2,rs5,Uimm32_0513x EndPacket is iclass=7 & op2127=0x2c & op0204=4 & rs5 & Uimm32_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 <= Uimm32_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,15) cmp.gtu -- "Pd4 = cmp.gtu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 1 1 s s s s s P P + t t t t t + + + 0 0 0 d d + +:cmp.gtu Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x13 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 > rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,15) cmp.gtu -- "Pd4 = ! cmp.gtu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 1 1 s s s s s P P + t t t t t + + + 1 0 0 d d + +:cmp.gtu! Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x13 & op0207=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 <= rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,13) cmp.gtu -- "Pd4 = cmp.gtu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 + + s s s s s P P + t t t t t 1 0 + + + + d d + +:cmp.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x14 & op13=0 & op0207=0x20 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + bool:1 = (rss5 > rtt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,7) cmp.eq -- "Rd32 = cmp.eq ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 + 1 0 s s s s s P P 1 i i i i i i i i d d d d d + +:cmp.eq Rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2127=0x1a & op13=1 & rs5 & Rd5 & Simm32_0512x & $(END_PACKET) { + # TODO: Verify output value - assuming 0/1 boolean + Rd5 = zext(rs5 == Simm32_0512x); + build EndPacket; +} + +# (v4,7) cmp.eq -- "Rd32 = ! cmp.eq ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 + 1 1 s s s s s P P 1 i i i i i i i i d d d d d + +:cmp.eq! Rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2127=0x1b & op13=1 & rs5 & Rd5 & Simm32_0512x & $(END_PACKET) { + # TODO: Verify output value - assuming 0/1 boolean + Rd5 = zext(rs5 != Simm32_0512x); + build EndPacket; +} + +# (v4,15) cmp.eq -- "Rd32 = cmp.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t + + + d d d d d + +:cmp.eq Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x1a & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = zext(rs5 == rt5); + build EndPacket; +} + +# (v4,15) cmp.eq -- "Rd32 = ! cmp.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t + + + d d d d d + +:cmp.eq! Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x1b & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = zext(rs5 != rt5); + build EndPacket; +} + +# (v4,13) cmpb.eq -- "Pd4 = cmpb.eq ( Rs32 , #u8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 0 0 s s s s s P P + i i i i i i i i 0 0 + d d + +:cmpb.eq Pd2,rs5,Uimm8_0512 EndPacket is iclass=13 & op2127=0x68 & op13=0 & op0204=0 & rs5 & Uimm8_0512 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 == Uimm8_0512); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmpb.eq -- "Pd4 = cmpb.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 1 0 + + + d d + +:cmpb.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x30 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 == rt5:1); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmpb.gt -- "Pd4 = cmpb.gt ( Rs32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 0 1 s s s s s P P + i i i i i i i i 0 0 + d d + +:cmpb.gt Pd2,rs5,Simm8_0512 EndPacket is iclass=13 & op2127=0x69 & op13=0 & op0204=0 & rs5 & Simm8_0512 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 s> Simm8_0512); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmpb.gt -- "Pd4 = cmpb.gt ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 0 1 0 + + + d d + +:cmpb.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x10 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 s> rt5:1); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmpb.gtu -- "Pd4 = cmpb.gtu ( Rs32 , #u7x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 1 0 s s s s s P P + 0 i i i i i i i 0 0 + d d + +:cmpb.gtu Pd2,rs5,Uimm8_0511x EndPacket is iclass=13 & op2127=0x6a & op1213=0 & op0204=0 & rs5 & Uimm8_0511x & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 > Uimm8_0511x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmpb.gtu -- "Pd4 = cmpb.gtu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 1 1 + + + d d + +:cmpb.gtu Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x38 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 > rt5:1); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmph.eq -- "Pd4 = cmph.eq ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 0 0 s s s s s P P + i i i i i i i i 0 1 + d d + +:cmph.eq Pd2,rs5,Simm16_0512x EndPacket is iclass=13 & op2127=0x68 & op13=0 & op0204=2 & rs5 & Simm16_0512x & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 == Simm16_0512x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmph.eq -- "Pd4 = cmph.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 0 1 1 + + + d d + +:cmph.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x18 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 == rt5:2); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmph.gt -- "Pd4 = cmph.gt ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 0 1 s s s s s P P + i i i i i i i i 0 1 + d d + +:cmph.gt Pd2,rs5,Simm16_0512x EndPacket is iclass=13 & op2127=0x69 & op13=0 & op0204=2 & rs5 & Simm16_0512x & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 s> Simm16_0512x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmph.gt -- "Pd4 = cmph.gt ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 0 0 + + + d d + +:cmph.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x20 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 s> rt5:2); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmph.gtu -- "Pd4 = cmph.gtu ( Rs32 , #u7x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 1 0 s s s s s P P + 0 i i i i i i i 0 1 + d d + +:cmph.gtu Pd2,rs5,Uimm16_0511x EndPacket is iclass=13 & op2127=0x6a & op1213=0 & op0204=2 & rs5 & Uimm16_0511x & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 > Uimm16_0511x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmph.gtu -- "Pd4 = cmph.gtu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 0 1 + + + d d + +:cmph.gtu Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x28 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 > rt5:2); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpyX2RndSat; + +:cmpy":<<1:rnd:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=6 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = cmpyX2RndSat(rs5,rt5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpyRndSat; + +:cmpy":rnd:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x69 & op13=0 & op0507=6 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = cmpyRndSat(rs5,rt5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 * ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:cmpy":<<1:rnd:sat" Rd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x6f & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rd5 & $(END_PACKET) { + Rd5 = cmpyX2RndSat(rs5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 * ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:cmpy":rnd:sat" Rd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x6b & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rd5 & $(END_PACKET) { + Rd5 = cmpyRndSat(rs5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpyX2Sat; + +:cmpy":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2c & op13=0 & op0507=6 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2Sat(rs5,rt5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpySat; + +:cmpy":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=6 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySat(rs5,rt5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 * ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:cmpy":<<1:sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x2e & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2Sat(rs5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 * ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:cmpy":sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x2a & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySat(rs5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +define pcodeop cmpyX2SatAdd; + +:cmpy+=":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=6 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2SatAdd(rs5,rt5,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +define pcodeop cmpySatAdd; + +:cmpy+=":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=6 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySatAdd(rs5,rt5,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 * ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +:cmpy+=":<<1:sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=6 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2SatAdd(rs5,Rt5Conjugate,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 * ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +:cmpy+=":sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3a & op13=0 & op0507=6 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySatAdd(rs5,Rt5Conjugate,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop cmpyX2SatSub; + +:cmpy-=":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=7 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2SatSub(rs5,rt5,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop cmpySatSub; + +:cmpy-=":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=7 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySatSub(rs5,rt5,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 * ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +:cmpy-=":<<1:sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=7 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2SatSub(rs5,Rt5Conjugate,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 * ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +:cmpy-=":sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3a & op13=0 & op0507=7 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySatSub(rs5,Rt5Conjugate,rdd5); + build EndPacket; +} + +# (v2,14) cmpyi -- "Rdd32 = cmpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:cmpyi Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=1 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + # Rdd = (Rs.h[1] * Rt.h[0]) - (Rs.h[0] * Rt.h[1]); + rsR:2 = rs5[0,16]; + rtR:2 = rt5[0,16]; + rsI:2 = rs5[16,16]; + rtI:2 = rt5[16,16]; + p1:4 = sext(rsI) * sext(rtR); # (Rs.h[1] * Rt.h[0]) + p2:4 = sext(rsR) * sext(rtI); # (Rs.h[0] * Rt.h[1]) + Rdd5 = sext(p1) + sext(p2); + build EndPacket; +} + +# (v2,14) cmpyi -- "Rxx32 += cmpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:cmpyi+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=1 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + # Rdd = (Rs.h[1] * Rt.h[0]) - (Rs.h[0] * Rt.h[1]); + rsR:2 = rs5[0,16]; + rtR:2 = rt5[0,16]; + rsI:2 = rs5[16,16]; + rtI:2 = rt5[16,16]; + p1:4 = sext(rsI) * sext(rtR); # (Rs.h[1] * Rt.h[0]) + p2:4 = sext(rsR) * sext(rtI); # (Rs.h[0] * Rt.h[1]) + Rdd5 = rdd5 + (sext(p1) + sext(p2)); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P 0 t t t t t 0 1 0 d d d d d +define pcodeop cmpyiw; + +:cmpyiw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x43 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiw(rss5,rtt5); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32* )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 0 1 0 d d d d d + +:cmpyiw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x47 & op13=0 & op0507=2 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiw(rss5,Rtt5Conjugate); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d +define pcodeop cmpyiwX2Sat; + +:cmpyiw":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x49 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwX2Sat(rss5,rtt5); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32* ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 0 0 s s s s s P P 0 t t t t t 1 0 0 d d d d d + +:cmpyiw":<<1:sat" Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x48 & op13=0 & op0507=4 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwX2Sat(rss5,Rtt5Conjugate); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 0 0 s s s s s P P 0 t t t t t 1 0 0 d d d d d +define pcodeop cmpyiwX2RndSat; + +:cmpyiw":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x4c & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwX2RndSat(rss5,rtt5); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32* ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:cmpyiw":<<1:rnd:sat" Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x4d & op13=0 & op0507=0 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwX2RndSat(rss5,Rtt5Conjugate); + build EndPacket; +} + +define pcodeop cmpyiwAdd; +# (v4,12) cmpyiw -- "Rxx32 += cmpyiw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P 0 t t t t t 0 1 0 x x x x x +:cmpyiw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x53 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwAdd(rdd5,rss5,rtt5); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rxx32 += cmpyiw ( Rss32 , Rtt32* )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x + +:cmpyiw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x52 & op13=0 & op0507=6 & rss5 & Rtt5Conjugate & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwAdd(rdd5,rss5,Rtt5Conjugate); + build EndPacket; +} + +# (v5,12) cmpyiwh -- "Rd32 = cmpyiwh ( Rss32 , Rt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 1 0 0 d d d d d + +define pcodeop cmpyiwhX2RndSat; + +:cmpyiwh":<<1:rnd:sat" Rd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=4 & rss5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = cmpyiwhX2RndSat(rd5,rss5,rt5); + build EndPacket; +} + +# (v5,12) cmpyiwh -- "Rd32 = cmpyiwh ( Rss32 , Rt32 * ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 + + + s s s s s P P + t t t t t 1 0 1 d d d d d + +:cmpyiwh":<<1:rnd:sat" Rd5,rss5,Rt5Conjugate EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=5 & rss5 & Rt5Conjugate & Rd5 & rd5 & $(END_PACKET) { + Rd5 = cmpyiwhX2RndSat(rd5,rss5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpyr -- "Rdd32 = cmpyr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +:cmpyr Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=2 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + # Rdd = (Rs.h[0] * Rt.h[0]) - (Rs.h[1] * Rt.h[1]); + rsR:2 = rs5[0,16]; + rtR:2 = rt5[0,16]; + rsI:2 = rs5[16,16]; + rtI:2 = rt5[16,16]; + p1:4 = sext(rsR) * sext(rtR); # (Rs.h[0] * Rt.h[0]) + p2:4 = sext(rsI) * sext(rtI); # (Rs.h[1] * Rt.h[1]) + Rdd5 = sext(p1) - sext(p2); + build EndPacket; +} + +# (v2,14) cmpyr -- "Rxx32 += cmpyr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x + +:cmpyr+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=2 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + # Rdd += (Rs.h[0] * Rt.h[0]) - (Rs.h[1] * Rt.h[1]); + rsR:2 = rs5[0,16]; + rtR:2 = rt5[0,16]; + rsI:2 = rs5[16,16]; + rtI:2 = rt5[16,16]; + p1:4 = sext(rsR) * sext(rtR); # (Rs.h[0] * Rt.h[0]) + p2:4 = sext(rsI) * sext(rtI); # (Rs.h[1] * Rt.h[1]) + Rdd5 = rdd5 + (sext(p1) - sext(p2)); + build EndPacket; +} + +define pcodeop cmpyrw; +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d + +:cmpyrw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x44 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrw(rss5,rtt5); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d + +:cmpyrw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x46 & op13=0 & op0507=2 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrw(rss5,Rtt5Conjugate); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d +define pcodeop cmpyrwX2Sat; + +:cmpyrw":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x4a & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwX2Sat(rss5,rtt5); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:cmpyrw":<<1:sat" Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x4b & op13=0 & op0507=0 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwX2Sat(rss5,Rtt5Conjugate); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d +define pcodeop cmpyrwX2RndSat; + +:cmpyrw":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x4e & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwX2RndSat(rss5,rtt5); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:cmpyrw":<<1:rnd:sat" Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x4f & op13=0 & op0507=0 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwX2RndSat(rss5,Rtt5Conjugate); + build EndPacket; +} + +# cmpyrw -- "Rxx32 += cmpyrw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x +define pcodeop cmpyrwAdd; + +:cmpyrw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x54 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwAdd(rdd5,rss5,rtt5); + build EndPacket; +} + +# cmpyrw -- "Rxx32 += cmpyrw ( Rss32 , Rtt32* )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x + +:cmpyrw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x56 & op13=0 & op0507=2 & rss5 & Rtt5Conjugate & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwAdd(rdd5,rss5,Rtt5Conjugate); + build EndPacket; +} + + +# (v4,12) cmpyrwh -- "Rd32 = cmpyrwh ( Rss32 , Rt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 + + + s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpyrwhX2RndSat; +:cmpyrwh":<<1:rnd:sat" Rd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=6 & rss5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = cmpyrwhX2RndSat(rd5,rss5,rt5); + build EndPacket; +} +# (v5,12) cmpyrwh -- "Rd32 = cmpyrwh ( Rss32 , Rt32 * ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 + + + s s s s s P P + t t t t t 1 1 1 d d d d d + +:cmpyrwh":<<1:rnd:sat" Rd5,rss5,Rt5Conjugate EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=7 & rss5 & Rt5Conjugate & Rd5 & rd5 & $(END_PACKET) { + Rd5 = cmpyrwhX2RndSat(rd5,rss5,Rt5Conjugate); + build EndPacket; +} + +# (v2,15) combine -- "Rd32 = combine ( Rt32.h , Rs32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t - - - d d d d d + +:combine Rd5,rt5H,rs5H EndPacket is iclass=0xf & op2127=0x1c & op13=0 & op0507=0 & Rd5 & rt5H & rs5H & $(END_PACKET) { + Rd5 = (zext(rt5H) << 16) + zext(rs5H); + build EndPacket; +} + +# (v2,15) combine -- "Rd32 = combine ( Rt32.h , Rs32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t - - - d d d d d + +:combine Rd5,rt5H,rs5L EndPacket is iclass=0xf & op2127=0x1d & op13=0 & op0507=0 & Rd5 & rt5H & rs5L & $(END_PACKET) { + Rd5 = (zext(rt5H) << 16) + zext(rs5L); + build EndPacket; +} + +# (v2,15) combine -- "Rd32 = combine ( Rt32.l , Rs32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t - - - d d d d d + +:combine Rd5,rt5L,rs5H EndPacket is iclass=0xf & op2127=0x1e & op13=0 & op0507=0 & Rd5 & rt5L & rs5H & $(END_PACKET) { + Rd5 = (zext(rt5L) << 16) + zext(rs5H); + build EndPacket; +} + +# (v2,15) combine -- "Rd32 = combine ( Rt32.l , Rs32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t - - - d d d d d + +:combine Rd5,rt5L,rs5L EndPacket is iclass=0xf & op2127=0x1f & op13=0 & op0507=0 & Rd5 & rt5L & rs5L & $(END_PACKET) { + Rd5 = (zext(rt5L) << 16) + zext(rs5L); + build EndPacket; +} + +# (v4,7) combine -- "Rdd32 = combine ( #s8 , #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 0 0 1 + + I I I I I P P I i i i i i i i i d d d d d + +:combine Rdd5,Simm8_0512,Uimm32_1620_13x EndPacket is iclass=7 & op2127=0x64 & Rdd5 & rdd5h_ & rd5_ & Simm8_0512 & Uimm32_1620_13x & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = sext(Simm8_0512); + rd5_ = Uimm32_1620_13x; + build EndPacket; +} + +# (v2,7) combine -- "Rdd32 = combine ( #s8x , #S8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 0 0 0 I I I I I I I P P I i i i i i i i i d d d d d + +:combine Rdd5,Simm32_0512x,Simm8_1622_13 EndPacket is iclass=7 & op2427=0xc & op23=0 & Rdd5 & rdd5h_ & rd5_ & Simm8_1622_13 & Simm32_0512x & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = Simm32_0512x; + rd5_ = sext(Simm8_1622_13); + build EndPacket; +} +# Special case (no immext): Rdd=combine(#-1,#s8) where s8 < 0 (maps to Rdd=#s8) +:assign Rdd5,Simm8_1622_13 EndPacket is iclass=7 & op2427=0xc & op23=0 & Rdd5 & Simm8_1622_13 & s0512=0xff & s22=1 & immext=0 & $(END_PACKET) { + Rdd5 = sext(Simm8_1622_13); + build EndPacket; +} +# Special case (no immext): Rdd=combine(#0,#s8) where s8 > 0 (maps to Rdd=#s8) +:assign Rdd5,Simm8_1622_13 EndPacket is iclass=7 & op2427=0xc & op23=0 & Rdd5 & Simm8_1622_13 & s0512=0 & s22=0 & immext=0 & $(END_PACKET) { + Rdd5 = zext(Simm8_1622_13); + build EndPacket; +} + +# (v4,7) combine -- "Rdd32 = combine ( #s8x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 + 0 1 s s s s s P P 1 i i i i i i i i d d d d d + +:combine Rdd5,Simm32_0512x,rs5 EndPacket is iclass=7 & op2127=0x19 & op13=1 & Rdd5 & rdd5h_ & rd5_ & rs5 & Simm32_0512x & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = Simm32_0512x; + rd5_ = rs5; + build EndPacket; +} + +# (v4,7) combine -- "Rdd32 = combine ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 + 0 0 s s s s s P P 1 i i i i i i i i d d d d d + +:combine Rdd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2127=0x18 & op13=1 & Rdd5 & rdd5h_ & rd5_ & rs5 & Simm32_0512x & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = rs5; + rd5_ = Simm32_0512x; + build EndPacket; +} + +# (v2,15) combine -- "Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 0 1 0 - - s s s s s P P - t t t t t - - - d d d d d + +:combine Rdd5,rs5,rt5 EndPacket is iclass=0xf & op2427=5 & op2123=0 & op13=0 & op0507=0 & Rdd5 & rdd5h_ & rd5_ & rs5 & rt5 & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = rs5; + rd5_ = rt5; + build EndPacket; +} + +# (v2,15) combine -- "if ( Pu4 ) Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 1 0 1 - - - s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) combine -- "if ( ! Pu4 ) Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 1 0 1 - - - s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) combine -- "if ( Pu4 .new ) Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 1 0 1 - - - s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) combine -- "if ( ! Pu4 .new ) Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 1 0 1 + + + s s s s s P P 1 t t t t t 1 u u d d d d d + +:combine^PuCond0506_N13_S07 rdd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x68 & PuCond0506_N13_S07 & rs5 & rt5 & rdd5 & rdd5h & rd5 & $(END_PACKET) { + hi:4 = rs5; + lo:4 = rt5; + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + # Write hi/lo regs separately to simplify analysis + rdd5h = hi; + rd5 = lo; + +} + +# if ([!]Pu4[.new]) Rdd32 = Rs32:Rt32 ( simplification of if ([!]Pu4[.new]) Rdd32 = combine ( Rs32 , Rt32 ) +# where Rs32 is odd and Rt32 is the corresponding low reg +:assign^PuCond0506_N13_S07 rdd5,rtt5 EndPacket is iclass=15 & op2127=0x68 & op16=1 & op8=0 & op0912=op1720 & PuCond0506_N13_S07 & rtt5 & rdd5 & $(END_PACKET) { + tmp:8 = rtt5; + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v4,8) cround -- "Rd32 = cround ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 0 0 + d d d d d + +:cround Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = roundConvergent(rs5, Uimm8_0812); + build EndPacket; +} + +:cround Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0507=2 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = roundConvergent(rss5, Uimm8_0813); + build EndPacket; +} + + +# (v4,12) cround -- "Rd32 = cround ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +:cround Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = roundConvergent(rs5, rt5); + build EndPacket; +} + +:cround Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=2 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + Rdd5 = roundConvergent(rss5, rt5); + build EndPacket; +} + +# (v2,6) crswap -- "crswap ( Rx32 , sgp0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 1 0 0 0 x x x x x P P + + + + + + + + + + + + + + + +:crswap Rx5,S0 EndPacket is iclass=6 & op2127=0x28 & op0013=0x00 & Rx5 & rx5 & S0 & $(END_PACKET) { + # TODO: Verify semantics - this was a guess based upon mnemonic + tmp:4 = S0; + S0 = rx5; + Rx5 = tmp; + build EndPacket; +} + +# (v4,6) crswap -- "crswap ( Rx32 , sgp1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 1 0 0 1 x x x x x P P + + + + + + + + + + + + + + + +:crswap Rx5,S1 EndPacket is iclass=6 & op2127=0x29 & op0013=0x00 & Rx5 & rx5 & S1 & $(END_PACKET) { + # TODO: Verify semantics - this was a guess based upon mnemonic + tmp:4 = S1; + S1 = rx5; + Rx5 = tmp; + build EndPacket; +} + +# (v4,6) crswap -- "crswap ( Rxx32 , sgp1:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 1 1 + + x x x x x P P + + + + + + + + + 0 0 0 0 0 + +:crswap Rxx5,S1S0 EndPacket is iclass=6 & op2127=0x6c & op0013=0x00 & Rxx5 & rxx5 & S1S0 & $(END_PACKET) { + # TODO: Verify semantics - this was a guess based upon mnemonic + tmp:8 = S1S0; + S1S0 = rxx5; + Rxx5 = tmp; + build EndPacket; +} + +# (v2,6) cswi -- "cswi ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 0 1 + + + + + + +define pcodeop cswi; + +:cswi rs5 EndPacket is iclass=6 & op2127=0x20 & op0013=0x20 & rs5 & $(END_PACKET) { + cswi(rs5); + build EndPacket; +} + +# (v2,8) ct0 -- "Rd32 = ct0 ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:ct0 Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=4 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = countTrailingZeros(rs5); + build EndPacket; +} + +# (v4,8) ct0 -- "Rd32 = ct0 ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P + + + + + + 0 1 + d d d d d + +:ct0 Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0513=2 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = countTrailingZeros(rss5); + build EndPacket; +} + +# (v2,8) ct1 -- "Rd32 = ct1 ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 0 1 d d d d d + +:ct1 Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=5 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = countTrailingOnes(rs5); + build EndPacket; +} + +# (v4,8) ct1 -- "Rd32 = ct1 ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P + + + + + + 1 0 + d d d d d + +:ct1 Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0513=0x04 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = countTrailingOnes(rss5); + build EndPacket; +} + +# (v65,6) ctlbw -- "Rd32 = ctlbw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 1 1 0 s s s s s P P 0 t t t t t + + + d d d d d + +define pcodeop ctlbw; +:ctlbw Rd5,rss5,rt5 EndPacket is iclass=6 & op2127=0x66 & op13=0 & rss5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = ctlbw(rss5, rt5); + build EndPacket; +} + +# (v2,10) dccleana -- "dccleana ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 0 0 0 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dccleana; + +:dccleana rs5 EndPacket is iclass=10 & op2127=0 & op0013=0 & rs5 & $(END_PACKET) { + dccleana(rs5); + build EndPacket; +} + +# (v2,10) dccleanidx -- "dccleanidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 1 0 0 0 1 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dccleanidx; + +:dccleanidx rs5 EndPacket is iclass=10 & op2127=0x11 & op0013=0 & rs5 & $(END_PACKET) { + dccleanidx(rs5); + build EndPacket; +} + +# (v2,10) dccleaninva -- "dccleaninva ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 0 1 0 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dccleaninva; + +:dccleaninva rs5 EndPacket is iclass=10 & op2127=0x02 & op0013=0 & rs5 & $(END_PACKET) { + dccleaninva(rs5); + build EndPacket; +} + +# (v2,10) dccleaninvidx -- "dccleaninvidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 1 0 0 1 1 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dccleaninvidx; + +:dccleaninvidx rs5 EndPacket is iclass=10 & op2127=0x13 & op0013=0 & rs5 & $(END_PACKET) { + dccleaninvidx(rs5); + build EndPacket; +} + +# (v2,9) dcfetch -- "dcfetch ( Rs32 + #u11:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 0 0 0 0 0 s s s s s P P 0 + + i i i i i i i i i i i + +FetchAddrRsReld: "("^rs5^"+"^Uimm16_0010_shift3^")" is rs5 & Uimm16_0010_shift3 { ptr:4 = rs5 + zext(Uimm16_0010_shift3); export *[ram]:8 ptr; } +FetchAddrRsReld: "("^rs5^")" is rs5 & i0010=0 { export *[ram]:8 rs5; } + +define pcodeop dcfetch; + +:dcfetch FetchAddrRsReld EndPacket is iclass=9 & op2127=0x20 & op1112=0 & FetchAddrRsReld & $(END_PACKET) { + dcfetch(FetchAddrRsReld); + build EndPacket; +} + +# (v2,10) dcinva -- "dcinva ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 0 0 1 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dcinva; + +:dcinva rs5 EndPacket is iclass=10 & op2127=0x01 & op0013=0 & rs5 & $(END_PACKET) { + dcinva(rs5); + build EndPacket; +} + +# (v2,10) dcinvidx -- "dcinvidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 1 0 0 1 0 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dcinvidx; + +:dcinvidx rs5 EndPacket is iclass=10 & op2127=0x12 & op0013=0 & rs5 & $(END_PACKET) { + dcinvidx(rs5); + build EndPacket; +} + +# (v2,10) dckill -- "dckill" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 1 0 0 0 0 + + + + + P P + + + + + + + + + + + + + + + +define pcodeop dckill; + +:dckill EndPacket is iclass=10 & op2127=0x10 & op1620=0 & op0013=0 & $(END_PACKET) { + dckill(); + build EndPacket; +} + +# (v2,10) dctagr -- "Rd32 = dctagr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 0 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop dctagr; + +:dctagr Rd5,rs5 EndPacket is iclass=10 & op2127=0x21 & op0513=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = dctagr(rs5); + build EndPacket; +} + +# (v2,10) dctagw -- "dctagw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + + + + + + + + + +define pcodeop dctagw; + +:dctagw rs5,rt5 EndPacket is iclass=10 & op2127=0x20 & op13=0 & op0007=0 & rs5 & rt5 & $(END_PACKET) { + dctagw(rs5,rt5); + build EndPacket; +} + +# (v2,10) dczeroa -- "dczeroa ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 0 s s s s s P P 0 + + + + + + + + + + + + + + +define pcodeop dczeroa; + +:dczeroa rs5 EndPacket is iclass=10 & op2127=0x06 & op0013=0 & rs5 & $(END_PACKET) { + dczeroa(rs5); + build EndPacket; +} + +# (v4,9) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 0 0 + + + + + 1 1 1 1 0 + +:dealloc_return EndPacket is iclass=9 & op2127=0x30 & op1620=0x1e & op0013=0x001e & $(END_PACKET) { + build EndPacket; + <> + deallocframe(FP); + return [LR]; +} + +# (v4,9) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 0 0 0 + + + + + 1 1 1 1 0 + +:dealloc_return rs5 EndPacket is iclass=9 & op2127=0x30 & rs5 & op0013=0x001e & $(END_PACKET) { + build EndPacket; + <> + deallocframe(rs5); + return [LR]; +} + +# dealloc_return -- "if ( Ps4 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 0 0 s s + + + 1 1 1 1 0 +# +# dealloc_return -- "if ( ! Ps4 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 0 0 s s + + + 1 1 1 1 0 +# +# dealloc_return:nt -- "if ( Ps4 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 1 0 s s + + + 1 1 1 1 0 +# +# dealloc_return:nt -- "if ( ! Ps4 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 0 1 0 s s + + + 1 1 1 1 0 +# +# dealloc_return:t -- "if ( Ps4 .new ) dealloc_return:t" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 1 0 s s + + + 1 1 1 1 0 +# +# dealloc_return:t -- "if ( ! Ps4 .new ) dealloc_return:t" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 1 0 s s + + + 1 1 1 1 0 + +DRTaken12: is op11=0 & op12=1 { } +DRTaken12: ":t" is op11=1 & op12=1 { } +DRTaken12: ":nt" is op11=1 & op12=0 { } + +:dealloc_return^FlowCond0809_N11_S13^DRTaken12 EndPacket is iclass=9 & op2127=0x30 & op1620=0x1e & (op1112=2 | op11=1) & op0007=0x1e & FlowCond0809_N11_S13 & DRTaken12 & $(END_PACKET) { + build FlowCond0809_N11_S13; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + deallocframe(FP); + return [LR]; + +} + +# (v4,9) dealloc_return -- "if ( Ps4 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 1 0 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return -- "if ( ! Ps4 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 1 0 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return:nt -- "if ( Ps4 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 0 1 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return:nt -- "if ( ! Ps4 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 0 1 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return:t -- "if ( Ps4 .new ) dealloc_return:t" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 1 1 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return:t -- "if ( ! Ps4 .new ) dealloc_return:t" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 1 1 0 s s + + + 1 1 1 1 0 + +:dealloc_return^FlowCond0809_N11_S13^DRTaken12 rs5 EndPacket is iclass=9 & op2127=0x30 & rs5 & (op1112=2 | op11=1) & op0007=0x1e & FlowCond0809_N11_S13 & DRTaken12 & $(END_PACKET) { + build FlowCond0809_N11_S13; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + deallocframe(rs5); + return [LR]; + +} + + +# (v2,9) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 P P 0 - - - - - - - - 1 1 1 1 0 + +:deallocframe EndPacket is iclass=9 & op2527=0 & op2224=0 & op21=0 & op1620=0x1e & op13=0 & op0512=0 & op0004=0x1e & $(END_PACKET) { + build EndPacket; + <> + deallocframe(FP); +} + +# (v4,12) decbin -- "Rdd32 = decbin ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop decbin; +:decbin Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = decbin(rss5, rtt5); + build EndPacket; +} + +# (v2,8) deinterleave -- "Rdd32 = deinterleave ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 0 0 d d d d d +define pcodeop deinterleave; +:deinterleave Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x04 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = deinterleave(rss5); + build EndPacket; +} + +# (v69,6) diag -- "diag ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + + + + + + 0 0 1 + + + + + + +define pcodeop diag; +:diag rs5 EndPacket is iclass=6 & op2127=0x12 & op0507=1 & rs5 & $(END_PACKET) { + diag(rs5); + build EndPacket; +} + +# (v69,6) diag0 -- "diag0 ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 + + + + + + +define pcodeop diag0; +:diag0 rss5,rtt5 EndPacket is iclass=6 & op2127=0x12 & op0507=2 & rss5 & rtt5 & $(END_PACKET) { + diag0(rss5, rtt5); + build EndPacket; +} + +# (v69,6) diag1 -- "diag1 ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + t t t t t 0 1 1 + + + + + + +define pcodeop diag1; +:diag1 rss5,rtt5 EndPacket is iclass=6 & op2127=0x12 & op0507=3 & rss5 & rtt5 & $(END_PACKET) { + diag1(rss5, rtt5); + build EndPacket; +} + +# (v68,10) dmsyncht -- "Rd32 = dmsyncht" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 0 - - - - - P P - - - - - 0 1 1 1 d d d d d + +define pcodeop dmsyncht; +:dmsyncht Rd5 EndPacket is iclass=10 & op2127=0x40 & op0508=7 & Rd5 & $(END_PACKET) { + Rd5 = dmsyncht(); # Rd5=DM0; What is DM0 ? + build EndPacket; +} + +# (v4,8) extract -- "Rd32 = extract ( Rs32 , #u5 , #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 1 1 I I s s s s s P P 0 i i i i i I I I d d d d d + +:extract Rd5,rs5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1b & op13=0 & Rd5 & rs5 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { + # width: Uimm8_0812 + # offset: Uimm8_2122_0507 + mask:4 = ~(-1 << Uimm8_0812); + tmp:4 = (rs5 >> Uimm8_2122_0507) & mask; + # force sign extension + ext:1 = 32 - Uimm8_0812; + Rd5 = (tmp << ext) >> ext; + build EndPacket; +} + +# (v4,12) extract -- "Rd32 = extract ( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 0 1 0 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:extract Rd5,rs5,rtt5 EndPacket is iclass=12 & op2127=0x48 & op13=0 & op0507=2 & Rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + mask:4 = ~(-1 << rtt5h); + tmp:4 = (rs5 >> rt5) & mask; + # force sign extension + ext:4 = 32 - rtt5h; + Rd5 = (tmp << ext) >> ext; + build EndPacket; +} + +# (v4,8) extract -- "Rdd32 = extract ( Rss32 , #u6 , #U6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 0 I I I s s s s s P P i i i i i i I I I d d d d d + +:extract Rdd5,rss5,Uimm8_0813,Uimm8_2123_0507 EndPacket is iclass=8 & op2427=0xa & Rdd5 & rss5 & Uimm8_0813 & Uimm8_2123_0507 & $(END_PACKET) { + # width: Uimm8_0813 + # offset: Uimm8_2123_0507 + mask:8 = ~(-1 << Uimm8_0813); + tmp:8 = (rss5 >> Uimm8_2123_0507) & mask; + # force sign extension + ext:1 = 64 - Uimm8_0813; + Rdd5 = (tmp << ext) >> ext; + build EndPacket; +} + +# (v4,12) extract -- "Rdd32 = extract ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +:extract Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + mask:8 = ~(-1 << rtt5h); + tmp:8 = (rss5 >> rt5) & mask; + # force sign extension + ext:4 = 64 - rtt5h; + Rdd5 = (tmp << ext) >> ext; + build EndPacket; +} + +# (v2,8) extractu -- "Rd32 = extractu ( Rs32 , #u5 , #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 1 0 I I s s s s s P P 0 i i i i i I I I d d d d d + +:extractu Rd5,rs5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1a & op13=0 & Rd5 & rs5 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { + # width: Uimm8_0812 + # offset: Uimm8_2122_0507 + mask:4 = ~(-1 << Uimm8_0812); + Rd5 = (rs5 >> Uimm8_2122_0507) & mask; + build EndPacket; +} + +# (v2,12) extractu -- "Rd32 = extractu ( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 0 1 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:extractu Rd5,rs5,rtt5 EndPacket is iclass=12 & op2127=0x48 & op13=0 & op0507=0 & Rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + mask:4 = ~(-1 << rtt5h); + Rd5 = (rs5 >> rt5) & mask; + build EndPacket; +} + +# (v2,8) extractu -- "Rdd32 = extractu ( Rss32 , #u6 , #U6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 1 I I I s s s s s P P i i i i i i I I I d d d d d + +:extractu Rdd5,rss5,Uimm8_0813,Uimm8_2123_0507 EndPacket is iclass=8 & op2427=1 & Rdd5 & rss5 & Uimm8_0813 & Uimm8_2123_0507 & $(END_PACKET) { + # width: Uimm8_0813 + # offset: Uimm8_2123_0507 + mask:8 = ~(-1 << Uimm8_0813); + Rdd5 = (rss5 >> Uimm8_2123_0507) & mask; + build EndPacket; +} + +# (v2,12) extractu -- "Rdd32 = extractu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:extractu Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + mask:8 = ~(-1 << rtt5h); + Rdd5 = (rss5 >> rt5) & mask; + build EndPacket; +} + +# (v4,6) fastcorner9 -- "Pd4 = fastcorner9 ( Ps4 , Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 0 0 + + s s P P 1 + + + t t 1 + + 1 + + d d + +define pcodeop fastcorner9; + +:fastcorner9 Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x58 & op1820=0 & op13=1 & op1012=0 & op0207=0x24 & Pd2 & pu1617 & pu0809 & $(END_PACKET) { + Pd2 = Pd2 & fastcorner9(pu1617,pu0809); + build EndPacket; +} + +# (v4,6) fastcorner9 -- "Pd4 = ! fastcorner9 ( Ps4 , Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 0 1 + + s s P P 1 + + + t t 1 + + 1 + + d d + +:fastcorner9! Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x58 & op1820=4 & op13=1 & op1012=0 & op0207=0x24 & Pd2 & pu1617 & pu0809 & $(END_PACKET) { + Pd2 = Pd2 & ~fastcorner9(pu1617,pu0809); + build EndPacket; +} + +# (v4,6) getimask -- "Rd32 = getimask ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop getimask; + +:getimask Rd5,rs5 EndPacket is iclass=6 & op2127=0x30 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = getimask(rs5); + build EndPacket; +} + +# (v4,5) hintjr -- "hintjr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 0 1 0 1 s s s s s P P + + + + + + + + + + + + + + + +:hintjr rs5 EndPacket is iclass=5 & op2127=0x15 & op0013=0 & rs5 & $(END_PACKET) { + # TODO: appears in decomp compilation - not sure what it does + build EndPacket; +} + +# (v2,6) iassignr -- "Rd32 = iassignr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 1 0 0 1 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop iassignr; + +:iassignr Rd5,rs5 EndPacket is iclass=6 & op2127=0x33 & op0513=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = iassignr(rs5); + build EndPacket; +} + +# (v2,6) iassignw -- "iassignw ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 1 0 + + + + + + +define pcodeop iassignw; # TODO: What affect does this have + +:iassignw rs5 EndPacket is iclass=6 & op2127=0x20 & op0013=0x40 & rs5 & $(END_PACKET) { + iassignw(rs5); + build EndPacket; +} + +# (v4,5) icdatar -- "Rd32 = icdatar ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 1 1 0 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop icdatar; + +:icdatar Rd5,rs5 EndPacket is iclass=5 & op2127=0x2d & op0513=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = icdatar(rs5); + build EndPacket; +} + +# (v66,5) icdataw -- "icdataw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 1 1 1 0 s s s s s P P + t t t t t + + + + + + + + + +define pcodeop icache_data_write; # TODO: What affect does this have + +:icdataw rs5, rt5 EndPacket is iclass=5 & op2127=0x36 & rs5 & rt5 & $(END_PACKET) { + icache_data_write(rs5, rt5); + build EndPacket; +} + +# (v2,5) icinva -- "icinva ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 0 + + + + + + + + + + + + +define pcodeop icache_inv_addr; + +:icinva rs5 EndPacket is iclass=5 & op2127=0x36 & op0013=0 & rs5 & $(END_PACKET) { + icache_inv_addr(rs5); + build EndPacket; +} + +# (v2,5) icinvidx -- "icinvidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 1 + + + + + + + + + + + + +define pcodeop icinvidx; # TODO: What affect does this have + +:icinvidx rs5 EndPacket is iclass=5 & op2127=0x36 & op0013=0x800 & rs5 & $(END_PACKET) { + icinvidx(rs5); + build EndPacket; +} + +# (v2,5) ickill -- "ickill" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 0 1 1 0 + + + + + P P 0 1 0 + + + + + + + + + + + + +define pcodeop ickill; + +:ickill EndPacket is iclass=5 & op2127=0x36 & op1113=2 & $(END_PACKET) { + ickill(); + build EndPacket; +} + +# (v2,5) ictagr -- "Rd32 = ictagr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 1 1 1 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop ictagr; + +:ictagr Rd5,rs5 EndPacket is iclass=5 & op2127=0x2f & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = ictagr(rs5); + build EndPacket; +} + +# (v4,5) ictagw -- "ictagw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 1 1 1 0 s s s s s P P + t t t t t + + + + + + + + + +define pcodeop ictagw; + +:ictagw rs5,rt5 EndPacket is iclass=5 & op2127=0x2e & op13=0 & op0007=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + ictagw(rs5, rt5); + build EndPacket; +} + +# (v4,0) immext -- "immext ( #u26:6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 0 i i i i i i i i i i i i P P i i i i i i i i i i i i i i + +Uimm32_1627_0013_6: "#"^val is i1627 & i0013 [ val = (i1627 << 20) | (i0013 << 6); xreg = xreg + 1; globalset(inst_next, xreg); ] { export *[const]:4 val; } + +:immext Uimm32_1627_0013_6 EndPacket is iclass=0 & i1627 & i0013 & Uimm32_1627_0013_6 & $(END_PACKET) + [ immext = (i1627 << 14) | i0013; globalset(inst_next,immext); immexted = 1; globalset(inst_next,immexted);] +{ + # Not sure about behavior - may be NOP and used as immediate value for next instruction + build EndPacket; +} + +# (v2,8) insert -- "Rx32 = insert ( Rs32 , #u5 , #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 1 0 I I s s s s s P P 0 i i i i i I I I x x x x x + +:insert Rd5,rs5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1e & op13=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { + # width: Uimm8_0812 + # offset: Uimm8_2122_0507 + clrMask:4 = ~(((1 << Uimm8_0812) - 1) << Uimm8_2122_0507); + setMask:4 = (rs5 & ((1 << Uimm8_0812) - 1)) << Uimm8_2122_0507; + Rd5 = (rd5 & clrMask) | setMask; + build EndPacket; +} + +# (v2,12) insert -- "Rx32 = insert ( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 0 0 + + + s s s s s P P + t t t t t + + + x x x x x + +:insert Rd5,rs5,rtt5 EndPacket is iclass=12 & op2127=0x40 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + clrMask:4 = ~(((1 << rtt5h) - 1) << rt5); + setMask:4 = (rs5 & ((1 << rtt5h) - 1)) << rt5; + Rd5 = (rd5 & clrMask) | setMask; + build EndPacket; +} + +# (v2,8) insert -- "Rxx32 = insert ( Rss32 , #u6 , #U6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 1 I I I s s s s s P P i i i i i i I I I x x x x x + +:insert Rdd5,rss5,Uimm8_0813,Uimm8_2123_0507 EndPacket is iclass=8 & op2427=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & Uimm8_2123_0507 & $(END_PACKET) { + # width: Uimm8_0813 + # offset: Uimm8_2123_0507 + clrMask:8 = ~(((1 << Uimm8_0813) - 1) << Uimm8_2123_0507); + setMask:8 = (rss5 & ((1 << Uimm8_0813) - 1)) << Uimm8_2123_0507; + Rdd5 = (rdd5 & clrMask) | setMask; + build EndPacket; +} + +# (v2,12) insert -- "Rxx32 = insert ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 0 0 + + s s s s s P P + t t t t t + + + x x x x x + +:insert Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x50 & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + clrMask:8 = ~(((1 << rtt5h) - 1) << rt5); + setMask:8 = (rss5 & ((1 << rtt5h) - 1)) << rt5; + Rdd5 = (rdd5 & clrMask) | setMask; + build EndPacket; +} + +# (v2,8) interleave -- "Rdd32 = interleave ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 0 1 d d d d d +define pcodeop interleave; +:interleave Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x05 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = interleave(rss5); + build EndPacket; +} + +# (v2,5) isync -- "isync" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 P P 0 - - - 0 0 0 0 0 0 0 0 1 0 + +define pcodeop isync; + +:isync EndPacket is iclass=5 & op2127=0x3e & op1620=0 & $(END_PACKET) { + isync(); + build EndPacket; +} + +# (v2,5) jump -- "jump #r22:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 0 0 i i i i i i i i i P P i i i i i i i i i i i i i - + +:jump RelDest22x EndPacket is iclass=5 & op2527=4 & op0=0 & RelDest22x & $(END_PACKET) { + build EndPacket; + <> + goto RelDest22x; +} + +# (v2,5) jump -- "if ( Pu4 ) jump #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i - 0 - u u i i i i i i i - +# +# (v2,5) jump -- "if ( ! Pu4 ) jump #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i - 0 - u u i i i i i i i - + +:jump^FlowCondUU RelDest15x EndPacket is iclass=5 & op2427=0xc & op1112=0 & op10=0 & op0=0 & FlowCondUU & RelDest15x & $(END_PACKET) { + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto RelDest15x; + +} + +# (v60,5) jump:nt -- "if ( Pu4 ) jump:nt #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 0 + u u i i i i i i i + +# +# (v60,5) jump:nt -- "if ( ! Pu4 ) jump:nt #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 0 + u u i i i i i i i + +# +# (v60,5) jump:t -- "if ( Pu4 ) jump:t #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 0 + u u i i i i i i i + +# +# (v60,5) jump:t -- "if ( ! Pu4 ) jump:t #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 0 + u u i i i i i i i + + +:jump^FlowCondUU^Taken12 RelDest15x EndPacket is iclass=5 & op2427=0xc & op1011=0 & op0=0 & Taken12 & FlowCondUU & RelDest15x & $(END_PACKET) { + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto RelDest15x; + +} + +# (v2,5) jump:nt -- "if ( Pu4 .new ) jump:nt #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 1 + u u i i i i i i i + +# +# (v2,5) jump:nt -- "if ( ! Pu4 .new ) jump:nt #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 1 + u u i i i i i i i + +# +# (v2,5) jump:t -- "if ( Pu4 .new ) jump:t #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 1 + u u i i i i i i i + +# +# (v2,5) jump:t -- "if ( ! Pu4 .new ) jump:t #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 1 + u u i i i i i i i + + +:jump^FlowCondNewUU^Taken12 RelDest15x EndPacket is iclass=5 & op2427=0xc & op1011=2 & op0=0 & Taken12 & FlowCondNewUU & RelDest15x & $(END_PACKET) { + build FlowCondNewUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto RelDest15x; + +} + +# (v4,6) jump:nt -- "if ( Rs32 != #0 ) jump:nt #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 0 i i i i i i i i i i i + +# +# (v4,6) jump:t -- "if ( Rs32 != #0 ) jump:t #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 1 i i i i i i i i i i i + +# +# (v4,6) jump:nt -- "if ( Rs32 <= #0 ) jump:nt #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 0 i i i i i i i i i i i + +# +# (v4,6) jump:t -- "if ( Rs32 <= #0 ) jump:t #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 1 i i i i i i i i i i i + +# +# (v4,6) jump:nt -- "if ( Rs32 == #0 ) jump:nt #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 0 i i i i i i i i i i i + +# +# (v4,6) jump:t -- "if ( Rs32 == #0 ) jump:t #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 1 i i i i i i i i i i i + +# +# (v4,6) jump:nt -- "if ( Rs32 >= #0 ) jump:nt #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 0 i i i i i i i i i i i + +# +# (v4,6) jump:t -- "if ( Rs32 >= #0 ) jump:t #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 1 i i i i i i i i i i i + + +JmpRsCmp_2223: "("^rs5^"!=#0)" is op2223=0 & rs5 { tmp:1 = rs5 != 0; export tmp; } +JmpRsCmp_2223: "("^rs5^">=#0)" is op2223=1 & rs5 { tmp:1 = rs5 s>= 0; export tmp; } +JmpRsCmp_2223: "("^rs5^"==#0)" is op2223=2 & rs5 { tmp:1 = rs5 == 0; export tmp; } +JmpRsCmp_2223: "("^rs5^"<=#0)" is op2223=3 & rs5 { tmp:1 = rs5 s<= 0; export tmp; } + +:jump.if^Taken12 JmpRsCmp_2223,RelDest13 EndPacket is iclass=6 & op2427=1 & op0=0 & Taken12 & JmpRsCmp_2223 & RelDest13 & $(END_PACKET) { + build EndPacket; + <> + if (JmpRsCmp_2223 == 0) goto ; + goto RelDest13; + +} + +# (v4,2) jump:nt -- "if ( cmp.eq ( Ns8 .new , #-1 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 0 0 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.eq ( Ns8 .new , #-1 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 0 1 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.eq ( Ns8 .new , #-1 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 0 0 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.eq ( Ns8 .new , #-1 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 0 1 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.eq ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 0 0 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.eq ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 0 1 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.eq ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 0 0 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.eq ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 0 1 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.eq ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 0 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.eq ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 0 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.eq ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 0 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.eq ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 0 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gt ( Ns8 .new , #-1 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 1 0 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gt ( Ns8 .new , #-1 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 1 1 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gt ( Ns8 .new , #-1 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 1 0 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gt ( Ns8 .new , #-1 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 1 1 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gt ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 1 0 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gt ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 1 1 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gt ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 1 0 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gt ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 1 1 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gt ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 1 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gt ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 1 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gt ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 1 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gt ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 1 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gt ( Rt32 , Ns8 .new ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 1 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gt ( Rt32 , Ns8 .new ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 1 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gt ( Rt32 , Ns8 .new ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 1 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gt ( Rt32 , Ns8 .new ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 1 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gtu ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 0 0 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gtu ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 0 1 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gtu ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 0 0 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gtu ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 0 1 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gtu ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 0 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gtu ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 0 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gtu ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 0 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gtu ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 0 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gtu ( Rt32 , Ns8 .new ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 1 0 0 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gtu ( Rt32 , Ns8 .new ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 1 0 0 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gtu ( Rt32 , Ns8 .new ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 1 0 0 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gtu ( Rt32 , Ns8 .new ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 1 0 0 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( tstbit ( Ns8 .new , #0 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 1 0 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! tstbit ( Ns8 .new , #0 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 1 1 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( tstbit ( Ns8 .new , #0 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 1 0 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! tstbit ( Ns8 .new , #0 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 1 1 i i - s s s P P 1 - - - - - i i i i i i i - + +# All normal class-2 instructions are conditional jumps with compare +# and are handled by a single constructor although op2326 is not fully utilized + +JumpCmp_2326: "cmp.eq("^Nreg1618,rt5^")" is op2326=0 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (Nreg1618 == tmp); +} +JumpCmp_2326: "cmp.gt("^Nreg1618,rt5^")" is op2326=1 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (Nreg1618 s> tmp); +} +JumpCmp_2326: "cmp.gtu("^Nreg1618,rt5^")" is op2326=2 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (Nreg1618 > tmp); +} +JumpCmp_2326: "cmp.gt("^rt5,Nreg1618^")" is op2326=3 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (tmp s> Nreg1618); +} +JumpCmp_2326: "cmp.gtu("^rt5,Nreg1618^")" is op2326=4 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (tmp > Nreg1618); +} +### -- op2326 values 5-7 unused +JumpCmp_2326: "cmp.eq("^Nreg1618,Uimm8_0812^")" is op2326=8 & Nreg1618 & Uimm8_0812 { + <> + ConditionReg = (Nreg1618 == zext(Uimm8_0812)); +} +JumpCmp_2326: "cmp.gt("^Nreg1618,Uimm8_0812^")" is op2326=9 & Nreg1618 & Uimm8_0812 { + <> + ConditionReg = (Nreg1618 s> zext(Uimm8_0812)); +} +JumpCmp_2326: "cmp.gtu("^Nreg1618,Uimm8_0812^")" is op2326=10 & Nreg1618 & Uimm8_0812 { + <> + ConditionReg = (Nreg1618 > zext(Uimm8_0812)); +} +JumpCmp_2326: "tstbit("^Nreg1618,"#0)" is op2326=11 & Nreg1618 { + <> + ConditionReg = ((Nreg1618 & 1) != 0); +} +JumpCmp_2326: "cmp.eq("^Nreg1618,"#-1)" is op2326=12 & Nreg1618 { + <> + ConditionReg = (Nreg1618 == -1); +} +JumpCmp_2326: "cmp.gt("^Nreg1618,"#-1)" is op2326=13 & Nreg1618 { + <> + ConditionReg = (Nreg1618 s> -1); +} +### -- op2326 values 14-15 unused + +JumpIf_2326_S22: JumpCmp_2326 is op22=0 & JumpCmp_2326 { } +JumpIf_2326_S22: "!"^JumpCmp_2326 is op22=1 & JumpCmp_2326 { + <> + build JumpCmp_2326; + ConditionReg = !ConditionReg; +} + +:jump.if^Taken13 JumpIf_2326_S22,RelDest9x EndPacket is iclass=2 & op27=0 & Taken13 & JumpIf_2326_S22 & RelDest9x & $(END_PACKET) { + build EndPacket; + <> + build JumpIf_2326_S22; + if (ConditionReg == 0) goto ; + goto RelDest9x; + +} + + +# (v2,5) jumpr -- "jumpr Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 0 1 0 0 s s s s s P P - - - - - - - - - - - - - - + +:jumpr rs5 EndPacket is iclass=5 & op2127=0x14 & op0013=0 & rs5 & $(END_PACKET) { + dest:4 = rs5; + build EndPacket; + <> + goto [dest]; +} + +# jumpr LR (special case: treat as return) +:jumpr LR EndPacket is iclass=5 & op2127=0x14 & op1620=31 & op0013=0 & LR & $(END_PACKET) { + dest:4 = LR; + build EndPacket; + <> + return [dest]; +} + +# jumprh -- "jumprh Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 0 1 1 0 s s s s s P P - - - - - - - - - - - - - - + +:jumprh rs5 EndPacket is iclass=5 & op2127=0x16 & op0013=0 & rs5 & $(END_PACKET) { + dest:4 = rs5; + build EndPacket; + <> + goto [dest]; +} + +# jumpr LR (special case: treat as return) +:jumprh LR EndPacket is iclass=5 & op2127=0x16 & op1620=31 & op0013=0 & LR & $(END_PACKET) { + dest:4 = LR; + build EndPacket; + <> + return [dest]; +} + +# (v2,5) jumpr:nt -- "if ( Pu4 ) jumpr:nt Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 0 0 - u u - - - - - - - - +# +# (v2,5) jumpr:nt -- "if ( ! Pu4 ) jumpr:nt Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 0 0 - u u - - - - - - - - +# +# (v2,5) jumpr:t -- "if ( Pu4 ) jumpr:t Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 1 0 - u u - - - - - - - - +# +# (v2,5) jumpr:t -- "if ( ! Pu4 ) jumpr:t Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 1 0 - u u - - - - - - - - + +:jumpr^FlowCondUU^Taken12 rs5 EndPacket is iclass=5 & op2227=0xd & Taken12 & op11=0 & op0007=0 & rs5 & FlowCondUU & $(END_PACKET) { + dest:4 = rs5; + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto [dest]; + +} + +# if ([!]Pu) jumpr LR (special case: treat as conditional return) +:jumpr^FlowCondUU^Taken12 LR EndPacket is iclass=5 & op2227=0xd & op1620=31 & Taken12 & op11=0 & op0007=0 & LR & FlowCondUU & $(END_PACKET) { + dest:4 = LR; + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + return [dest]; + +} + +# (v4,5) jumpr:nt -- "if ( Pu4 .new ) jumpr:nt Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 0 1 - u u - - - - - - - - +# +# (v4,5) jumpr:nt -- "if ( ! Pu4 .new ) jumpr:nt Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 0 1 - u u - - - - - - - - +# +# (v4,5) jumpr:t -- "if ( Pu4 .new ) jumpr:t Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 1 1 - u u - - - - - - - - +# +# (v4,5) jumpr:t -- "if ( ! Pu4 .new ) jumpr:t Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 1 1 - u u - - - - - - - - + +:jumpr^FlowCondNewUU^Taken12 rs5 EndPacket is iclass=5 & op2227=0xd & Taken12 & op11=1 & rs5 & FlowCondNewUU & $(END_PACKET) { + dest:4 = rs5; + build FlowCondNewUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto [dest]; + +} + +# if ([!]Pu.new) jumpr LR (special case: treat as conditional return) +:jumpr^FlowCondNewUU LR EndPacket is iclass=5 & op2227=0xd & op1620=31 & Taken12 & op11=1 & LR & FlowCondNewUU & $(END_PACKET) { + dest:4 = LR; + build FlowCondNewUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + return [dest]; + +} + +# (v4,6) k0lock -- "k0lock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 1 1 - - - - - + +define pcodeop k0lock; + +:k0lock EndPacket is iclass=6 & op2127=0x61 & op0507=3 & $(END_PACKET) { + k0lock(); + build EndPacket; +} + +# (v4,6) k0unlock -- "k0unlock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 1 0 0 - - - - - + +define pcodeop k0unlock; + +:k0unlock EndPacket is iclass=6 & op2127=0x61 & op0507=4 & $(END_PACKET) { + k0unlock(); + build EndPacket; +} + +# (v65,10) l2cleanidx -- "l2cleanidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 0 1 s s s s s P P - - - - - - - - - - - - - - + +define pcodeop l2cleanidx; + +:l2cleanidx rs5 EndPacket is iclass=10 & op2127=0x31 & rs5 & $(END_PACKET) { + l2cleanidx(rs5); + build EndPacket; +} + +# (v4,10) l2cleaninvidx -- "l2cleaninvidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 1 1 s s s s s P P - - - - - - - - - - - - - - + +define pcodeop l2cleaninvidx; + +:l2cleaninvidx rs5 EndPacket is iclass=10 & op2127=0x43 & rs5 & $(END_PACKET) { + l2cleaninvidx(rs5); + build EndPacket; +} + +# (v4,10) l2fetch -- "l2fetch ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 + + s s s s s P P - t t t t t - - - - - - - - + +define pcodeop l2fetch; + +:l2fetch rs5,rt5 EndPacket is iclass=10 & op2127=0x30 & rs5 & rt5 & op13=0 & op0007=0 & $(END_PACKET) { + l2fetch(rs5,rt5); + build EndPacket; +} + +# (v?,10) l2fetch -- "l2fetch ( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 1 + + s s s s s P P - t t t t t - - - - - - - - + +:l2fetch rs5,rtt5 EndPacket is iclass=10 & op2127=0x34 & rs5 & rtt5 & $(END_PACKET) { + l2fetch(rs5,rtt5); + build EndPacket; +} + +# (v65,10) l2gclean -- "l2gclean" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 1 + + + + + P P - 1 0 0 - - - - - - - - - - + +define pcodeop l2gclean; + +:l2gclean EndPacket is iclass=10 & op2127=0x41 & op1012=4 & $(END_PACKET) { + l2gclean(); + build EndPacket; +} + +# (v65,10) l2gclean -- "l2gclean ( Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 1 0 1 + + + + + P P - t t t t t - - - - - - - - + +:l2gclean rtt5 EndPacket is iclass=10 & op2127=0x35 & rtt5 & $(END_PACKET) { + l2gclean(rtt5); + build EndPacket; +} + +# (v65,10) l2gcleaninv -- "l2gcleaninv" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 1 + + + + + P P - 1 1 0 - - - - - - - - - - + +define pcodeop l2gcleaninv; + +:l2gcleaninv EndPacket is iclass=10 & op2127=0x41 & op1012=6 & $(END_PACKET) { + l2gcleaninv(); + build EndPacket; +} + +# (v65,10) l2gcleaninv -- "l2gcleaninv ( Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 1 1 0 + + + + + P P - t t t t t - - - - - - - - + +:l2gcleaninv rtt5 EndPacket is iclass=10 & op2127=0x36 & rtt5 & $(END_PACKET) { + l2gcleaninv(rtt5); + build EndPacket; +} + +# (v65,10) l2gunlock -- "l2gunlock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 1 + + + + + P P - 0 1 0 - - - - - - - - - - + +define pcodeop l2gunlock; + +:l2gunlock EndPacket is iclass=10 & op2127=0x41 & op1012=2 & $(END_PACKET) { + l2gunlock(); + build EndPacket; +} + +# (v65,10) l2invidx -- "l2invidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 1 0 s s s s s P P - - - - - - - - - - - - - - + +define pcodeop l2invidx; + +:l2invidx rs5 EndPacket is iclass=10 & op2127=0x32 & rs5 & $(END_PACKET) { + l2invidx(rs5); + build EndPacket; +} + +# (v2,10) l2kill -- "l2kill" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 1 - - - - - P P - 0 0 0 - - - - - - - - - - + +define pcodeop l2kill; + +:l2kill EndPacket is iclass=10 & op2127=0x41 & op1012=0 & $(END_PACKET) { + l2kill(); + build EndPacket; +} + +# (v65,10) l2tagr -- "Rd32 = l2tagr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - - - - d d d d d + +define pcodeop l2tagr; + +:l2tagr Rd5,rs5 EndPacket is iclass=10 & op2127=0x23 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = l2tagr(rs5); + build EndPacket; +} + +# (v65,10) l2tagw -- "l2tagw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 0 0 0 1 0 s s s s s P P 0 t t t t t - - - - - - - - + +define pcodeop l2tagw; + +:l2tagw rs5,rt5 EndPacket is iclass=10 & op2127=0x22 & op13=0 & rs5 & rt5 & $(END_PACKET) { + l2tagw(rs5,rt5); + build EndPacket; +} + +# (v4,10) l2unlocka -- "l2unlocka ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 1 1 s s s s s P P - - - - - - - - - - - - - - + +define pcodeop l2unlocka; + +:l2unlocka rs5 EndPacket is iclass=10 & op2127=0x33 & rs5 & $(END_PACKET) { + l2unlocka(rs5); + build EndPacket; +} + +# (v65,10) l2locka -- "Pd2 = l2locka ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 1 - - - - - - - - - - - d d + +define pcodeop l2locka; + +:l2locka Pd2,rs5 EndPacket is iclass=10 & op2127=0x7 & op13=1 & Pd2 & rs5 & $(END_PACKET) { + Pd2 = l2locka(rs5); + build EndPacket; +} + +# (v2,12) lfs -- "Rdd32 = lfs ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop lfs; +:lfs Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = lfs(rss5, rtt5); + build EndPacket; +} + + +# linecpy -- "Rdd32 = linecpy( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 1 1 t t t t t P P 0 s s s s s 0 0 1 d d d d d + +define pcodeop linecpy; +:linecpy Rdd5,rt5,rss5 EndPacket is iclass=0x9 & op2127=0x4f & op13=0 & op0507=1 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + Rdd5 = linecpy(rt5, rss5); +} + +# +# loop0/loop1 subconstructors +# + +# Loop relative addresseses support immext +LoopRelAddr7x: val is s0812 & i0304 & immexted=0 [ val = (((s0812 << 2) | i0304) << 2) + $(PKT_START); ] { export *[const]:4 val; } +LoopRelAddr7x: val is i0811 & immexted=1 [ val = (simmext << 6) | (i0811 << 2) + $(PKT_START); ] { export *[const]:4 val; } + +LoopRelMem7x: LoopRelAddr7x is LoopRelAddr7x { export *[ram]:4 LoopRelAddr7x; } + +LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << 2) | i0001; ] { export *[const]:4 val; } + +# (v2,6) loop0 -- "loop0 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 0 0 0 I I I I I P P - i i i i i I I I i i - I I + +:loop0 LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x48 & op13=0 & op2=0 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) { + SA0_ = LoopRelAddr7x; + LC0_ = LoopUimm10; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 0; +} + +# (v2,6) loop0 -- "loop0 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 0 0 0 s s s s s P P - i i i i i - - - i i - - - + +:loop0 LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=0 & op13=0 & op0507=0 & op0002=0 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) { + SA0_ = LoopRelAddr7x; + LC0_ = rs5; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 0; +} + +# (v2,6) loop1 -- "loop1 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 0 0 1 I I I I I P P - i i i i i I I I i i - I I + +:loop1 LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x49 & op13=0 & op2=0 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) { + SA1_ = LoopRelAddr7x; + LC1_ = LoopUimm10; + build EndPacket; + <> + SA1 = SA1_; + LC1 = LC1_; + $(LPCFG) = 0; +} + +# (v2,6) loop1 -- "loop1 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 0 0 1 s s s s s P P - i i i i i - - - i i - - - + +:loop1 LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=1 & op13=0 & op0507=0 & op0002=0 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) { + SA1_ = LoopRelAddr7x; + LC1_ = rs5; + build EndPacket; + <> + SA1 = SA1_; + LC1 = LC1_; + $(LPCFG) = 0; +} + +# (v4,12) lsl -- "Rd32 = lsl ( #s6 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 0 + i i i i i P P + t t t t t 1 1 i d d d d d + +:lsl Rd5,Simm8_1620_05,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0607=3 & Rd5 & rt5 & Simm8_1620_05 & $(END_PACKET) { + Rd5 = sext(Simm8_1620_05) << rt5; + build EndPacket; +} + +# (v2,12) lsl -- "Rd32 = lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +:lsl Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=6 & Rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + Rd5 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + build EndPacket; +} + +# (v2,12) lsl -- "Rdd32 = lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 1 1 + d d d d d + +:lsl Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=6 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + Rdd5 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + build EndPacket; +} + +# (v2,12) lsl -- "Rx32 &= lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 & result; + build EndPacket; +} + +# (v2,12) lsl -- "Rx32 += lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 + result; + build EndPacket; +} + +# (v2,12) lsl -- "Rx32 -= lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 - result; + build EndPacket; +} + +# (v2,12) lsl -- "Rx32 |= lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 | result; + build EndPacket; +} + +# (v2,12) lsl -- "Rxx32 &= lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = rdd5 & (rss5 << rt5); + build EndPacket; +} + +# (v2,12) lsl -- "Rxx32 += lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 + result; + build EndPacket; +} + +# (v2,12) lsl -- "Rxx32 -= lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 - result; + build EndPacket; +} + +# (v4,12) lsl -- "Rxx32 ^= lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 ^ result; + build EndPacket; +} + +# (v2,12) lsl -- "Rxx32 |= lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 | result; + build EndPacket; +} + +# (v2,8) lsr -- "Rd32 = lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 0 1 d d d d d + +:lsr Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=1 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rs5 >> Uimm8_0812; + build EndPacket; +} + +# (v2,12) lsr -- "Rd32 = lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +:lsr Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + Rd5 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + build EndPacket; +} + +# (v2,8) lsr -- "Rdd32 = lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 0 1 d d d d d + +:lsr Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=1 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rss5 >> Uimm8_0813; + build EndPacket; +} + +# (v2,12) lsr -- "Rdd32 = lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:lsr Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=2 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + Rdd5 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 &= lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 0 1 x x x x x + +:lsr&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 & (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,12) lsr -- "Rx32 &= lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 & result; + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 += lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 0 1 x x x x x + +:lsr+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=5 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 + (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,12) lsr -- "Rx32 += lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 + result; + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 -= lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 0 1 x x x x x + +:lsr-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 - (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,12) lsr -- "Rx32 -= lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 - result; + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 ^= lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 0 1 x x x x x + +:lsr"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 ^ (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 |= lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 0 1 x x x x x + +:lsr|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=5 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 | (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,12) lsr -- "Rx32 |= lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 | result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 &= lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 0 1 x x x x x + +:lsr&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 & (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v2,12) lsr -- "Rxx32 &= lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 & result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 += lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 0 1 x x x x x + +:lsr+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=5 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 + (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v2,12) lsr -- "Rxx32 += lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 + result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 -= lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 0 1 x x x x x + +:lsr-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 - (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v2,12) lsr -- "Rxx32 -= lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 - result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 ^= lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 0 1 x x x x x + +:lsr"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 ^ (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v4,12) lsr -- "Rxx32 ^= lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 ^ result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 |= lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 0 1 x x x x x + +:lsr|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=5 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 | (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v2,12) lsr -- "Rxx32 |= lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 | result; + build EndPacket; +} + +# (v2,8) mask -- "Rdd32 = mask ( Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 0 + + + + + + + + P P + + + + t t + + + d d d d d + +define pcodeop maskGenerate; +:mask Rdd5,pu0809 EndPacket is iclass=8 & op2127=0x30 & op1620=0 & op1013=0 & op0507=0 & Rdd5 & pu0809 & $(END_PACKET) { + val:1 = 0xff; + Rdd5[0,8] = val * (pu0809) & 1; + Rdd5[8,8] = val * (pu0809 >> 1) & 1; + Rdd5[16,8] = val * (pu0809 >> 2) & 1; + Rdd5[24,8] = val * (pu0809 >> 3) & 1; + Rdd5[32,8] = val * (pu0809 >> 4) & 1; + Rdd5[40,8] = val * (pu0809 >> 5) & 1; + Rdd5[48,8] = val * (pu0809 >> 6) & 1; + Rdd5[56,8] = val * (pu0809 >> 7) & 1; + build EndPacket; +} + +# mask -- "Rd32 = mask ( #u5 , #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 1 0 I I - - - - - P P 1 i i i i i I I I d d d d d + +:mask Rd5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1a & op13=1 & Rd5 & op1620=0 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { + Rd5 = ((1< rt5; + Rd5 = (zext(bool) * rs5) + (zext(!bool) * rt5); + build EndPacket; +} + +# (v4,13) max -- "Rdd32 = max ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:max Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + bool:1 = rss5 s> rtt5; + Rdd5 = (zext(bool) * rss5) + (zext(!bool) * rtt5); + build EndPacket; +} + +# (v2,13) maxu -- "Rd32 = maxu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 1 0 s s s s s P P + t t t t t 1 + + d d d d d + +:maxu Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2e & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + bool:1 = rs5 > rt5; + Rd5 = (zext(bool) * rs5) + (zext(!bool) * rt5); + build EndPacket; +} + +# (v4,13) maxu -- "Rdd32 = maxu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +:maxu Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=5 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + bool:1 = rss5 > rtt5; + Rdd5 = (zext(bool) * rss5) + (zext(!bool) * rtt5); + build EndPacket; +} + +# (v2,9) memb -- "Rd32 = memb ( Rs32 + #s11:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 0 0 0 s s s s s P P i i i i i i i i i d d d d d + +:memb Rd5,LdMemRsRelxC9b0 EndPacket is iclass=9 & op27=0 & op2224=4 & op21=0 & Rd5 & LdMemRsRelxC9b0 & $(END_PACKET) { + Rd5 = sext(LdMemRsRelxC9b0); + build EndPacket; +} + +# (v4,3) memb -- "Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 0 0 0 s s s s s P P n t t t t t n + + d d d d d + +:memb Rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2127=0x50 & op0506=0 & Rd5 & MemRsRelShiftC3b & $(END_PACKET) { + Rd5 = sext(MemRsRelShiftC3b); + build EndPacket; +} + +# (v4,9) memb -- "Rd32 = memb ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 0 0 t t t t t P P n 1 I I I I n I I d d d d d + +:memb Rd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x68 & op12=1 & Rd5 & LdMemRsRelShiftxC9b & $(END_PACKET) { + Rd5 = sext(LdMemRsRelShiftxC9b); + build EndPacket; +} + +# (v4,9) memb -- "Rd32 = memb ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 f f f f f P P 0 1 I I I I + I I d d d d d + +:memb Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x58 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { + Rd5 = sext(LdMemRsAssignxC9b); + build EndPacket; +} + +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 0 0 + + + i i i i d d d d d + +:memb Rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x58 & op0913=0 & Rd5 & LdMemAIS4C9b0 & $(END_PACKET) { + Rd5 = sext(LdMemAIS4C9b0); + build EndPacket; +} + +# +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memb Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=8 & op0512=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { + Rd5 = sext(LdMemAIMuC9b); + build EndPacket; +} + +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 0 0 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memb Rd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x48 & op0912=0 & Rd5 & LdMemAIS4CircMuC9b0 & $(END_PACKET) { + Rd5 = sext(LdMemAIS4CircMuC9b0); + build EndPacket; +} + +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 0 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memb Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x48 & op0512=0x10 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { + Rd5 = sext(LdMemAIICircMuC9b); + build EndPacket; +} + +# (v2,4) memb -- "Rd32 = memb ( gp + #u16:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 0 0 0 i i i i i P P i i i i i i i i i d d d d d + +:memb Rd5,LdMemGPRelxC4b EndPacket is iclass=4 & op27=1 & op2224=4 & op21=0 & Rd5 & LdMemGPRelxC4b & $(END_PACKET) { + Rd5 = sext(LdMemGPRelxC4b); + build EndPacket; +} + + +# (v4,10) memb -- "memb ( Rf32 = #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 0 0 t t t 1 + I I I I I I + +:memb StMemRsAssignxC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=0 & op0607=2 & Nreg0810 & StMemRsAssignxC10b & $(END_PACKET) { + build EndPacket; + <> + StMemRsAssignxC10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Rf32 = #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 f f f f f P P 0 t t t t t 1 + I I I I I I + +:memb StMemRsAssignxC10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=0 & op0607=2 & rt5 & StMemRsAssignxC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemRsAssignxC10b = tmp; +} + +# (v4,10) memb -- "memb ( Rs32 + #s11:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 0 1 s s s s s P P i 0 0 t t t i i i i i i i i + +:memb StMemRsRelxC10b,Nreg0810 EndPacket is iclass=10 & op27=0 & op2224=6 & op21=1 & op1112=0 & Nreg0810 & StMemRsRelxC10b & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelxC10b = Nreg0810:1; +} + +# (v2,10) memb -- "memb ( Rs32 + #s11:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 0 0 0 s s s s s P P i t t t t t i i i i i i i i + +:memb StMemRsRelxC10b,rt5 EndPacket is iclass=10 & op27=0 & op2224=4 & op21=0 & rt5 & StMemRsRelxC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemRsRelxC10b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0 ) = #S8x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 0 + + 0 0 s s s s s P P I i i i i i i I I I I I I I + +:memb StMemRsRelC3b,Simm8_13_0006x EndPacket is iclass=3 & op2127=0x60 & StMemRsRelC3b & Simm8_13_0006x & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelC3b = Simm8_13_0006x; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) &= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 1 0 t t t t t + +:memb&= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=2 & StMemRsRelxC3b & ru5 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b & ru5:1; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) += #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 0 0 I I I I I + +:memb+= StMemRsRelxC3b,Uimm8_0004 EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=0 & StMemRsRelxC3b & Uimm8_0004 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b + Uimm8_0004; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) += Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 0 0 t t t t t + +:memb+= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=0 & StMemRsRelxC3b & ru5 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b + ru5:1; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) -= #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 0 1 I I I I I + +:memb-= StMemRsRelxC3b,Uimm8_0004 EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=1 & StMemRsRelxC3b & Uimm8_0004 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b - Uimm8_0004; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) -= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 0 1 t t t t t + +:memb-= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=1 & StMemRsRelxC3b & ru5 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b - ru5:1; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) = clrbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 1 0 I I I I I + +:memb StMemRsRelxC3b,ClrBit_0004b EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=2 & StMemRsRelxC3b & ClrBit_0004b & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b & ClrBit_0004b; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) = setbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 1 1 I I I I I + +:memb StMemRsRelxC3b,SetBit_0004b EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=3 & StMemRsRelxC3b & SetBit_0004b & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b | SetBit_0004b; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) |= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 1 1 t t t t t + +:memb|= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=3 & StMemRsRelxC3b & ru5 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b | ru5:1; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n + + 0 0 t t t + +:memb MemRsRelShiftC3b,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0306=0 & MemRsRelShiftC3b & Nreg0002 & $(END_PACKET) { + build EndPacket; + <> + MemRsRelShiftC3b = Nreg0002:1; +} + +# (v4,3) memb -- "memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 0 0 0 s s s s s P P n u u u u u n + + t t t t t + +:memb MemRsRelShiftC3b,ru5 EndPacket is iclass=3 & op2127=0x58 & op0506=0 & MemRsRelShiftC3b & ru5 & $(END_PACKET) { + tmp:1 = ru5:1; + build EndPacket; + <> + MemRsRelShiftC3b = tmp; +} + +# (v4,10) memb -- "memb ( Ru32 << #n2 + #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 u u u u u P P n 0 0 t t t 1 n I I I I I I + +:memb StMemRsRelShiftxC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x6d & op1112=0 & op7=1 & Nreg0810 & StMemRsRelShiftxC10b & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelShiftxC10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Ru32 << #n2 + #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 0 0 u u u u u P P n t t t t t 1 n I I I I I I + +:memb StMemRsRelShiftxC10b,rt5 EndPacket is iclass=10 & op2127=0x68 & op7=1 & rt5 & StMemRsRelShiftxC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemRsRelShiftxC10b = tmp; +} + +# (v4,10) memb -- "memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 0 0 t t t 0 i i i i + 0 + + +:memb StMemAIS4C10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=0 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4C10b & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4C10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 i i i i + 0 + + +:memb StMemAIS4CircMuC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=0 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4CircMuC10b & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4CircMuC10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Rz32 ++ Mu2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 + + + + + + + +# +# (v4,10) memb -- "memb ( Rz32 ++ Mu2 :brev ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 0 0 t t t 0 + + + + + + + + +:memb StMemAIMuC10b,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=0 & op0007=0 & Nreg0810 & StMemAIMuC10b & $(END_PACKET) { + build EndPacket; + <> + StMemAIMuC10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 + + + + + 1 + + +:memb StMemAIICircMuC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=0 & op0007=2 & Nreg0810 & StMemAIICircMuC10b & $(END_PACKET) { + build EndPacket; + <> + StMemAIICircMuC10b = Nreg0810:1; +} + +# (v2,10) memb -- "memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 0 t t t t t 0 i i i i + 0 + + +:memb StMemAIS4C10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=0 & op7=0 & op0002=0 & rt5 & StMemAIS4C10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemAIS4C10b = tmp; +} + +# (v2,10) memb -- "memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 0 0 z z z z z P P u t t t t t 0 i i i i + 0 + + +:memb StMemAIS4CircMuC10b,rt5 EndPacket is iclass=10 & op2127=0x48 & op7=0 & op0002=0 & rt5 & StMemAIS4CircMuC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemAIS4CircMuC10b = tmp; +} + +# (v2,10) memb -- "memb ( Rz32 ++ Mu2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 0 0 z z z z z P P u t t t t t 0 + + + + + + + +# +# (v2,10) memb -- "memb ( Rz32 ++ Mu2 :brev ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 z z z z z P P u t t t t t 0 + + + + + + + + +:memb StMemAIMuC10b,rt5 EndPacket is iclass=10 & op2627=3 & op2124=8 & op0007=0 & rt5 & StMemAIMuC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemAIMuC10b = tmp; +} + +# (v2,10) memb -- "memb ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 0 0 z z z z z P P u t t t t t 0 + + + + + 1 + + +:memb StMemAIICircMuC10b,rt5 EndPacket is iclass=10 & op2127=0x48 & op0007=0x2 & rt5 & StMemAIICircMuC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemAIICircMuC10b = tmp; +} + +# (v4,4) memb -- "memb ( gp + #u16:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 0 1 i i i i i P P i 0 0 t t t i i i i i i i i + +:memb StMemGPRelxC4b,Nreg0810 EndPacket is iclass=4 & op27=1 & op2224=2 & op21=1 & op1112=0 & Nreg0810 & StMemGPRelxC4b & $(END_PACKET) { + build EndPacket; + <> + StMemGPRelxC4b = Nreg0810:1; +} + +# (v2,4) memb -- "memb ( gp + #u16:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 0 0 0 i i i i i P P i t t t t t i i i i i i i i + +:memb StMemGPRelxC4b,rt5 EndPacket is iclass=4 & op27=1 & op2224=0 & op21=0 & rt5 & StMemGPRelxC4b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemGPRelxC4b = tmp; +} + +# (v4,9) memb -- "if ( Pt4 ) Rd32 = memb ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memb -- "if ( ! Pt4 ) Rd32 = memb ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memb -- "if ( Pt4 .new ) Rd32 = memb ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memb -- "if ( ! Pt4 .new ) Rd32 = memb ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memb^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9b EndPacket is iclass=9 & op2127=0x78 & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9b & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemAbsU6xC9b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memb -- "if ( Pt4 ) Rd32 = memb ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memb -- "if ( ! Pt4 ) Rd32 = memb ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memb -- "if ( Pt4 .new ) Rd32 = memb ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memb -- "if ( ! Pt4 .new ) Rd32 = memb ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d + +:memb^PuCond1112_N25_S26 rd5,LdMemRsRelxC4b EndPacket is iclass=4 & op27=0 & op2124=8 & op13=0 & rd5 & LdMemRsRelxC4b & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemRsRelxC4b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memb -- "if ( Pt4 ) Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memb -- "if ( ! Pt4 ) Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memb -- "if ( Pt4 .new ) Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memb -- "if ( ! Pt4 .new ) Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memb^PuCond0910_N12_S11 rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x58 & op13=1 & rd5 & LdMemAIS4C9b0 & rs5 & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemAIS4C9b0); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memb -- "if ( Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 0 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memb -- "if ( ! Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 0 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memb -- "if ( Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 0 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memb -- "if ( ! Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 0 0 0 s s s s s P P n t t t t t n v v d d d d d + +:memb^PuCond0506_N25_S24 rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2627=0 & op2123=0 & rd5_ & rd5 & MemRsRelShiftC3b & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(MemRsRelShiftC3b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,10) memb -- "if ( Pv4 ) memb ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 0 t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( Pv4 .new ) memb ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 0 t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 ) memb ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 0 t t t 1 i i i i 1 v v +# +# (v4,10) memb -- "if ( ! Pv4 .new ) memb ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 0 t t t 1 i i i i 1 v v + +:memb^PuCond0001_N13_S02 StMemAbsU6xC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1820=0 & op1112=0 & op7=1 & Nreg0810 & StMemAbsU6xC10b & PuCond0001_N13_S02 & $(END_PACKET) { + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10b = Nreg0810:1; + +} + +# (v4,10) memb -- "if ( Pv4 ) memb ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 ) memb ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memb -- "if ( Pv4 .new ) memb ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 .new ) memb ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v + +:memb^PuCond0001_N13_S02 StMemAbsU6xC10b,rt5 EndPacket is iclass=10 & op2127=0x78 & op1820=0 & op7=1 & rt5 & StMemAbsU6xC10b & PuCond0001_N13_S02 & $(END_PACKET) { + tmp:1 = rt5:1; + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10b = tmp; + +} + +# (v4,3) memb -- "if ( Pv4 ) memb ( Rs32 + #u6:0 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 0 0 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memb -- "if ( ! Pv4 ) memb ( Rs32 + #u6:0 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 1 0 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memb -- "if ( Pv4 .new ) memb ( Rs32 + #u6:0 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 0 0 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + #u6:0 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 1 0 0 s s s s s P P I i i i i i i v v I I I I I + +:memb^PuCond0506_N24_S23 StMemRsRelC3b,Simm8_13_0004x EndPacket is iclass=3 & op2527=4 & op2122=0 & Simm8_13_0004x & StMemRsRelC3b & PuCond0506_N24_S23 & $(END_PACKET) { + build PuCond0506_N24_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelC3b = Simm8_13_0004x; + +} + +# (v4,4) memb -- "if ( Pv4 ) memb ( Rs32 + #u6:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v +# +# (v4,4) memb -- "if ( Pv4 .new ) memb ( Rs32 + #u6:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v +# +# (v4,4) memb -- "if ( ! Pv4 ) memb ( Rs32 + #u6:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v +# +# (v4,4) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + #u6:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v + +:memb^PuCond0001_N25_S26 StMemRsRelxC4b,Nreg0810 EndPacket is iclass=4 & op27=0 & op2224=2 & op21=1 & op1112=0 & op2=0 & Nreg0810 & StMemRsRelxC4b & PuCond0001_N25_S26 & $(END_PACKET) { + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4b = Nreg0810:1; + +} + +# (v4,4) memb -- "if ( Pv4 .new ) memb ( Rs32 + #u6:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + #u6:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memb -- "if ( Pv4 ) memb ( Rs32 + #u6:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memb -- "if ( ! Pv4 ) memb ( Rs32 + #u6:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v + +:memb^PuCond0001_N25_S26 StMemRsRelxC4b,rt5 EndPacket is iclass=4 & op27=0 & op2124=0 & op2=0 & rt5 & StMemRsRelxC4b & PuCond0001_N25_S26 & $(END_PACKET) { + tmp:1 = rt5:1; + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4b = tmp; + +} + +# (v4,3) memb -- "if ( Pv4 ) memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 0 1 s s s s s P P n u u u u u n v v 0 0 t t t +# +# (v4,3) memb -- "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 0 1 s s s s s P P n u u u u u n v v 0 0 t t t +# +# (v4,3) memb -- "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 0 1 s s s s s P P n u u u u u n v v 0 0 t t t +# +# (v4,3) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 0 1 s s s s s P P n u u u u u n v v 0 0 t t t + +:memb^PuCond0506_N25_S24 MemRsRelShiftC3b,Nreg0002 EndPacket is iclass=3 & op2627=1 & op2123=5 & op0304=0 & Nreg0002 & MemRsRelShiftC3b & PuCond0506_N25_S24 & $(END_PACKET) { + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3b = Nreg0002:1; + +} + +# (v4,3) memb -- "if ( Pv4 ) memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 0 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memb -- "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 0 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memb -- "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 0 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 0 0 0 s s s s s P P n u u u u u n v v t t t t t + +:memb^PuCond0506_N25_S24 MemRsRelShiftC3b,ru5 EndPacket is iclass=3 & op2627=1 & op2223=0 & op21=0 & ru5 & MemRsRelShiftC3b & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:1 = ru5:1; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3b = tmp; + +} + +# (v4,10) memb -- "if ( Pv4 ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 0 t t t 0 i i i i 0 v v +# +# (v4,10) memb -- "if ( Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 0 t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 0 t t t 0 i i i i 1 v v +# +# (v4,10) memb -- "if ( ! Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 0 t t t 1 i i i i 1 v v + +:memb^PuCond0001_N07_S02 StMemAIS4C10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=4 & Nreg0810 & StMemAIS4C10b & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10b = Nreg0810:1; + +} + +# (v4,10) memb -- "if ( Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v2,10) memb -- "if ( Pv4 ) memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memb -- "if ( ! Pv4 ) memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v + +:memb^PuCond0001_N07_S02 StMemAIS4C10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=1 & rt5 & StMemAIS4C10b & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + tmp:1 = rt5:1; + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10b = tmp; + +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 0 0 f f f f f P P 0 1 I I I I + I I y y y y y + + +:memb_fifo Rdd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x54 & op1213=1 & op7=0 & LdMemRsAssignxC9b & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemRsAssignxC9b; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rs32 + #s11:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 1 0 0 s s s s s P P i i i i i i i i i y y y y y + +:memb_fifo Rdd5,LdMemRsRelxC9b0 EndPacket is iclass=9 & op27=0 & op2124=4 & LdMemRsRelxC9b0 & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemRsRelxC9b0; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 0 0 t t t t t P P n 1 I I I I n I I y y y y y + +:memb_fifo Rdd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x64 & op12=1 & LdMemRsRelShiftxC9b & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemRsRelShiftxC9b; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 0 0 z z z z z P P 0 0 + + + i i i i y y y y y + +:memb_fifo Rdd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x54 & op0913=0 & LdMemAIS4C9b0 & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemAIS4C9b0; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 0 0 z z z z z P P u 0 + + 0 i i i i y y y y y + +:memb_fifo Rdd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x44 & op0912=0 & LdMemAIS4CircMuC9b0 & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemAIS4CircMuC9b0; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 0 0 z z z z z P P u 0 + + + + 0 + + y y y y y +# +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 1 0 0 z z z z z P P u 0 + + + + 0 + + y y y y y + +:memb_fifo Rdd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=4 & op0512=0 & LdMemAIMuC9b & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemAIMuC9b; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 0 0 z z z z z P P u 0 + + 1 + 0 + + y y y y y + +:memb_fifo Rdd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x44 & op0512=0x10 & LdMemAIICircMuC9b & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemAIICircMuC9b; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 0 1 f f f f f P P 0 1 I I I I + I I d d d d d + +# TODO: Uncertain how dest register is modified - could be very simple +define pcodeop membh32; # It is assumed that a byte is loaded from memory at the specified address +define pcodeop membh64; # It is assumed that a byte is loaded from memory at the specified address + +:membh Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x51 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { + Rd5 = membh32(LdMemRsAssignxC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 0 0 1 s s s s s P P i i i i i i i i i d d d d d + +:membh Rd5,LdMemRsRelxC9b1 EndPacket is iclass=9 & op27=0 & op2224=0 & op21=1 & Rd5 & LdMemRsRelxC9b1 & $(END_PACKET) { + Rd5 = membh32(LdMemRsRelxC9b1); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 0 1 t t t t t P P n 1 I I I I n I I d d d d d + +:membh Rd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x61 & op12=1 & Rd5 & LdMemRsRelShiftxC9b & $(END_PACKET) { + Rd5 = membh32(LdMemRsRelShiftxC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 0 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:membh Rd5,LdMemAIS4C9b1 EndPacket is iclass=9 & op2127=0x51 & op0913=0 & Rd5 & LdMemAIS4C9b1 & $(END_PACKET) { + Rd5 = membh32(LdMemAIS4C9b1); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 0 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:membh Rd5,LdMemAIS4CircMuC9b1 EndPacket is iclass=9 & op2127=0x41 & op0912=0 & Rd5 & LdMemAIS4CircMuC9b1 & $(END_PACKET) { + Rd5 = membh32(LdMemAIS4CircMuC9b1); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:membh Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=1 & op0512=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { + Rd5 = membh32(LdMemAIMuC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 0 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:membh Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x41 & op0512=0x10 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { + Rd5 = membh32(LdMemAIICircMuC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 1 1 f f f f f P P 0 1 I I I I + I I d d d d d + +:membh Rdd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x57 & op1213=1 & op7=0 & Rdd5 & LdMemRsAssignxC9b & $(END_PACKET) { + Rdd5 = membh64(LdMemRsAssignxC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rs32 + #s11:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 1 1 1 s s s s s P P i i i i i i i i i d d d d d + +:membh Rdd5,LdMemRsRelxC9b2 EndPacket is iclass=9 & op27=0 & op2224=3 & op21=1 & Rdd5 & LdMemRsRelxC9b2 & $(END_PACKET) { + Rdd5 = membh64(LdMemRsRelxC9b2); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 1 1 t t t t t P P n 1 I I I I n I I d d d d d + +:membh Rdd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x67 & op12=1 & Rdd5 & LdMemRsRelShiftxC9b & $(END_PACKET) { + Rdd5 = membh32(LdMemRsRelShiftxC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 1 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:membh Rdd5,LdMemAIS4C9b2 EndPacket is iclass=9 & op2127=0x57 & op0913=0 & Rdd5 & LdMemAIS4C9b2 & $(END_PACKET) { + Rdd5 = membh64(LdMemAIS4C9b2); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 1 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:membh Rdd5,LdMemAIS4CircMuC9b2 EndPacket is iclass=9 & op2127=0x47 & op0912=0 & Rdd5 & LdMemAIS4CircMuC9b2 & $(END_PACKET) { + Rdd5 = membh64(LdMemAIS4CircMuC9b2); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 1 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:membh Rdd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=7 & op0512=0 & Rdd5 & LdMemAIMuC9b & $(END_PACKET) { + Rdd5 = membh64(LdMemAIMuC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 1 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:membh Rdd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x47 & op0512=0x10 & Rdd5 & LdMemAIICircMuC9b & $(END_PACKET) { + Rdd5 = membh64(LdMemAIICircMuC9b); + build EndPacket; +} + +# (v4,9) memd -- "Rdd32 = memd ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 f f f f f P P 0 1 I I I I + I I d d d d d + +:memd Rdd5,LdMemRsAssignxC9d EndPacket is iclass=9 & op2127=0x5e & op7=0 & op1213=1 & Rdd5 & LdMemRsAssignxC9d & $(END_PACKET) { + Rdd5 = LdMemRsAssignxC9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rs32 + #s11:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 1 1 0 s s s s s P P i i i i i i i i i d d d d d + +:memd Rdd5,LdMemRsRelxC9d EndPacket is iclass=9 & op27=0 & op2224=7 & op21=0 & Rdd5 & LdMemRsRelxC9d & $(END_PACKET) { + Rdd5 = LdMemRsRelxC9d; + build EndPacket; +} + +# (v4,3) memd -- "Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 1 1 0 s s s s s P P n t t t t t n - - d d d d d + +:memd Rdd5,MemRsRelShiftC3d EndPacket is iclass=3 & op2127=0x56 & Rdd5 & MemRsRelShiftC3d & $(END_PACKET) { + Rdd5 = MemRsRelShiftC3d; + build EndPacket; +} + +# (v4,9) memd -- "Rdd32 = memd ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 1 1 0 t t t t t P P n 1 I I I I n I I d d d d d + +:memd Rdd5,LdMemRsRelShiftxC9d EndPacket is iclass=9 & op2127=0x6e & op12=1 & Rdd5 & LdMemRsRelShiftxC9d & $(END_PACKET) { + Rdd5 = LdMemRsRelShiftxC9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 0 0 + + + i i i i d d d d d + +:memd Rdd5,LdMemAIS4C9d EndPacket is iclass=9 & op2127=0x5e & op0913=0 & Rdd5 & LdMemAIS4C9d & $(END_PACKET) { + Rdd5 = LdMemAIS4C9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ #s4:3 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 1 0 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memd Rdd5,LdMemAIS4CircMuC9d EndPacket is iclass=9 & op2127=0x4e & op0912=0 & Rdd5 & LdMemAIS4CircMuC9d & $(END_PACKET) { + Rdd5 = LdMemAIS4CircMuC9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 1 1 0 z z z z z P P u 0 - - - - 0 - - d d d d d +# +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memd Rdd5,LdMemAIMuC9d EndPacket is iclass=9 & op2627=3 & op2124=0xe & op0512=0 & Rdd5 & LdMemAIMuC9d & $(END_PACKET) { + Rdd5 = LdMemAIMuC9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 1 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memd Rdd5,LdMemAIICircMuC9d EndPacket is iclass=9 & op2127=0x4e & op0512=0x10 & Rdd5 & LdMemAIICircMuC9d & $(END_PACKET) { + Rdd5 = LdMemAIICircMuC9d; + build EndPacket; +} + +# (v2,4) memd -- "Rdd32 = memd ( gp + #u16:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 1 1 0 i i i i i P P i i i i i i i i i d d d d d + +:memd Rdd5,LdMemGPRelxC4d EndPacket is iclass=4 & op27=1 & op2224=7 & op21=0 & Rdd5 & LdMemGPRelxC4d & $(END_PACKET) { + Rdd5 = LdMemGPRelxC4d; + build EndPacket; +} + + +# (v4,10) memd -- "memd ( Rf32 = #U6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 f f f f f P P 0 t t t t t 1 + I I I I I I + +:memd StMemRsAssignxC10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=0 & op0607=2 & rtt5 & StMemRsAssignxC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemRsAssignxC10d = tmp; +} + +# (v2,10) memd -- "memd ( Rs32 + #s11:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 1 0 s s s s s P P i t t t t t i i i i i i i i + +:memd StMemRsRelxC10d,rtt5 EndPacket is iclass=10 & op27=0 & op2224=7 & op21=0 & rtt5 & StMemRsRelxC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemRsRelxC10d = tmp; +} + +# (v4,3) memd -- "memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 1 0 s s s s s P P n u u u u u n - - t t t t t + +:memd MemRsRelShiftC3d,ruu5 EndPacket is iclass=3 & op2127=0x5e & ruu5 & MemRsRelShiftC3d & $(END_PACKET) { + tmp:8 = ruu5; + build EndPacket; + <> + MemRsRelShiftC3d = tmp; +} + +# (v4,10) memd -- "memd ( Ru32 << #n2 + #U6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 1 0 u u u u u P P n t t t t t 1 n I I I I I I + +:memd StMemRsRelShiftxC10d,rtt5 EndPacket is iclass=10 & op2127=0x6e & op7=1 & rtt5 & StMemRsRelShiftxC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemRsRelShiftxC10d = tmp; +} + +# (v2,10) memd -- "memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 0 t t t t t 0 i i i i + 0 + + +:memd StMemAIS4C10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=0 & op7=0 & op0002=0 & rtt5 & StMemAIS4C10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemAIS4C10d = tmp; +} + +# (v2,10) memd -- "memd ( Rz32 ++ #s4:3 :circ ( Mu2 ) ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 1 0 z z z z z P P u t t t t t 0 i i i i + 0 + + +:memd StMemAIS4CircMuC10d,rtt5 EndPacket is iclass=10 & op2127=0x4e & op7=0 & op0002=0 & rtt5 & StMemAIS4CircMuC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemAIS4CircMuC10d = tmp; +} + +# (v2,10) memd -- "memd ( Rz32 ++ Mu2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 1 0 z z z z z P P u t t t t t 0 + + + + + + + +# +# (v2,10) memd -- "memd ( Rz32 ++ Mu2 :brev ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 z z z z z P P u t t t t t 0 + + + + + + + + +:memd StMemAIMuC10d,rtt5 EndPacket is iclass=10 & op2627=3 & op2124=0xe & rtt5 & StMemAIMuC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemAIMuC10d = tmp; +} + +# (v2,10) memd -- "memd ( Rz32 ++I :circ ( Mu2 ) ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 1 0 z z z z z P P u t t t t t 0 + + + + + 1 + + +:memd StMemAIICircMuC10d,rtt5 EndPacket is iclass=10 & op2127=0x4e & op0007=2 & rtt5 & StMemAIICircMuC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemAIICircMuC10d = tmp; +} + +# (v2,4) memd -- "memd ( gp + #u16:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 1 0 i i i i i P P i t t t t t i i i i i i i i + +:memd StMemGPRelxC4d,rtt5 EndPacket is iclass=4 & op27=1 & op2224=3 & op21=0 & rtt5 & StMemGPRelxC4d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemGPRelxC4d = tmp; +} + +# (v4,9) memd -- "if ( Pt4 ) Rdd32 = memd ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memd -- "if ( ! Pt4 ) Rdd32 = memd ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memd -- "if ( Pt4 .new ) Rdd32 = memd ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memd -- "if ( ! Pt4 .new ) Rdd32 = memd ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memd^PuCond0910_N12_S11 rdd5,LdMemAbsU6xC9d EndPacket is iclass=9 & op2127=0x7e & op13=1 & op0507=4 & rdd5 & LdMemAbsU6xC9d & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:8 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemAbsU6xC9d; + + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v2,4) memd -- "if ( Pt4 ) Rdd32 = memd ( Rs32 + #u6:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memd -- "if ( ! Pt4 ) Rdd32 = memd ( Rs32 + #u6:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memd -- "if ( Pt4 .new ) Rdd32 = memd ( Rs32 + #u6:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memd -- "if ( ! Pt4 .new ) Rdd32 = memd ( Rs32 + #u6:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d + +:memd^PuCond1112_N25_S26 rdd5,LdMemRsRelxC4d EndPacket is iclass=4 & op27=0 & op2224=7 & op21=0 & op13=0 & rdd5 & LdMemRsRelxC4d & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:8 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemRsRelxC4d; + + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v2,9) memd -- "if ( Pt4 ) Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memd -- "if ( ! Pt4 ) Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memd -- "if ( Pt4 .new ) Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memd -- "if ( ! Pt4 .new ) Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memd^PuCond0910_N12_S11 rdd5,LdMemAIS4C9d EndPacket is iclass=9 & op2127=0x5e & op13=1 & rdd5 & LdMemAIS4C9d & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:8 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemAIS4C9d; + + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v4,3) memd -- "if ( Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 1 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memd -- "if ( ! Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 1 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memd -- "if ( Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 1 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memd -- "if ( ! Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 1 1 0 s s s s s P P n t t t t t n v v d d d d d + +:memd^PuCond0506_N25_S24 rdd5,MemRsRelShiftC3d EndPacket is iclass=3 & op2627=0 & op2123=6 & rdd5 & MemRsRelShiftC3d & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:8 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = MemRsRelShiftC3d; + + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v4,10) memd -- "if ( Pv4 ) memd ( #u6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memd -- "if ( ! Pv4 ) memd ( #u6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memd -- "if ( Pv4 .new ) memd ( #u6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memd -- "if ( ! Pv4 .new ) memd ( #u6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 1 t t t t t 1 i i i i 1 v v + +:memd^PuCond0001_N13_S02 StMemAbsU6xC10d,rtt5 EndPacket is iclass=10 & op2127=0x7e & op1820=0 & op7=1 & rtt5 & StMemAbsU6xC10d & PuCond0001_N13_S02 & $(END_PACKET) { + tmp:8 = rtt5; + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10d = tmp; + +} + +# (v4,4) memd -- "if ( Pv4 .new ) memd ( Rs32 + #u6:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memd -- "if ( ! Pv4 .new ) memd ( Rs32 + #u6:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memd -- "if ( Pv4 ) memd ( Rs32 + #u6:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memd -- "if ( ! Pv4 ) memd ( Rs32 + #u6:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v + +:memd^PuCond0001_N25_S26 StMemRsRelxC4d,rtt5 EndPacket is iclass=4 & op27=0 & op2224=3 & op21=0 & op2=0 & rtt5 & StMemRsRelxC4d & PuCond0001_N25_S26 & $(END_PACKET) { + tmp:8 = rtt5; + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4d = tmp; + +} + +# (v4,3) memd -- "if ( Pv4 ) memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memd -- "if ( ! Pv4 ) memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memd -- "if ( Pv4 .new ) memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memd -- "if ( ! Pv4 .new ) memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 1 0 s s s s s P P n u u u u u n v v t t t t t + +:memd^PuCond0506_N25_S24 MemRsRelShiftC3d,ruu5 EndPacket is iclass=3 & op2627=1 & op2223=3 & op21=0 & ruu5 & MemRsRelShiftC3d & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:8 = ruu5; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3d = tmp; + +} + +# (v4,10) memd -- "if ( Pv4 .new ) memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memd -- "if ( ! Pv4 .new ) memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v2,10) memd -- "if ( Pv4 ) memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memd -- "if ( ! Pv4 ) memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v + +:memd^PuCond0001_N07_S02 StMemAIS4C10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=1 & rtt5 & StMemAIS4C10d & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + tmp:8 = rtt5; + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10d = tmp; + +} + +# memd_aq -- "Rdd32 = memd_aq ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 1 1 - - - 0 0 0 d d d d d + +:memd_aq Rdd5,LdMemRsRelC9d EndPacket is iclass=9 & op2527=1 & op2224=0 & op21=0 & Rdd5 & op1113=3 & op0810=0 & op0507=0 & LdMemRsRelC9d & $(END_PACKET) { + Rdd5 = LdMemRsRelC9d; + build EndPacket; +} + +# memd_rl -- "memd_rl ( Rs32 ):at = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 0 0 1 0 d d +define pcodeop waitAllThreads; +:memd_rl":at" StMemRsRelPdC9d, rtt5 EndPacket is iclass=0xa & op2527=0 & op2224=3 & op21=1 & op13=0 & rtt5 & op0607=0 & op0205=0x2 & StMemRsRelPdC9d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + waitAllThreads(); + StMemRsRelPdC9d = tmp; +} + +# memd_rl -- "memd_rl ( Rs32 ):st = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 1 0 1 0 d d +define pcodeop waitSameDomain; +:memd_rl":st" StMemRsRelPdC9d, rtt5 EndPacket is iclass=0xa & op2527=0 & op2224=3 & op21=1 & op13=0 & rtt5 & op0607=0 & op0205=0xa & StMemRsRelPdC9d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + waitSameDomain(); + StMemRsRelPdC9d = tmp; +} + +# (v4,9) memd_locked -- "Rdd32 = memd_locked ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 1 + + + + + + + d d d d d + +:memd_locked Rdd5,StMemRsRelPdC9d EndPacket is iclass=9 & op2127=0x10 & op0513=0x80 & Rdd5 & StMemRsRelPdC9d & $(END_PACKET) { + # NOTE: Manual does not indicate lock use, cannot be group with other instructions + Rdd5 = StMemRsRelPdC9d; + build EndPacket; +} + +# (v4,10) memd_locked -- "memd_locked ( Rs32 , Pd4 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P + t t t t t + + + + + + d d + +:memd_locked StMemRsRelPdC9d,rtt5 EndPacket is iclass=10 & op2127=0x07 & op13=0 & op0207=0 & StMemRsRelPdC9d & rtt5 & pu0001 & $(END_PACKET) { + # NOTE: cannot be group with other instructions + rc:1 = lock(); + lockOK:1 = rc != 0; + tmp:8 = rtt5; + build EndPacket; + <> + pu0001 = lockOK * 0xff; + <> + if (!lockOK) goto ; + StMemRsRelPdC9d = tmp; + unlock(); + +} + +# (v4,9) memh -- "Rd32 = memh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 f f f f f P P 0 1 I I I I + I I d d d d d + +:memh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x5a & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { + Rd5 = sext(LdMemRsAssignxC9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 0 1 0 s s s s s P P i i i i i i i i i d d d d d + +:memh Rd5,LdMemRsRelxC9h EndPacket is iclass=9 & op27=0 & op2224=5 & op21=0 & Rd5 & LdMemRsRelxC9h & $(END_PACKET) { + Rd5 = sext(LdMemRsRelxC9h); + build EndPacket; +} + +# (v4,3) memh -- "Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 0 1 0 s s s s s P P n t t t t t n + + d d d d d + +:memh Rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2127=0x52 & op0506=0 & Rd5 & MemRsRelShiftC3h & $(END_PACKET) { + Rd5 = sext(MemRsRelShiftC3h); + build EndPacket; +} + +# (v4,9) memh -- "Rd32 = memh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 1 0 t t t t t P P n 1 I I I I n I I d d d d d + +:memh Rd5,LdMemRsRelShiftxC9h EndPacket is iclass=9 & op2127=0x6a & op12=1 & Rd5 & LdMemRsRelShiftxC9h & $(END_PACKET) { + Rd5 = sext(LdMemRsRelShiftxC9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 0 0 + + + i i i i d d d d d + +:memh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5a & op0913=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { + Rd5 = sext(LdMemAIS4C9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 1 0 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x4a & op0912=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { + Rd5 = sext(LdMemAIS4CircMuC9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 1 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0xa & op0512=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { + Rd5 = sext(LdMemAIMuC9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 1 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x4a & op0512=0x10 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { + Rd5 = sext(LdMemAIICircMuC9h); + build EndPacket; +} + +# (v2,4) memh -- "Rd32 = memh ( gp + #u16:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 0 1 0 i i i i i P P i i i i i i i i i d d d d d + +:memh Rd5,LdMemGPRelxC4h EndPacket is iclass=4 & op27=1 & op2224=5 & op21=0 & Rd5 & LdMemGPRelxC4h & $(END_PACKET) { + Rd5 = sext(LdMemGPRelxC4h); + build EndPacket; +} + +# (v4,10) memh -- "memh ( Rf32 = #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 0 1 t t t 1 + I I I I I I + +:memh StMemRsAssignxC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=1 & op0607=2 & Nreg0810 & StMemRsAssignxC10h & $(END_PACKET) { + build EndPacket; + <> + StMemRsAssignxC10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Rf32 = #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 f f f f f P P 0 t t t t t 1 + I I I I I I +# +# (v4,10) memh -- "memh ( Rf32 = #U6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 f f f f f P P 0 t t t t t 1 + I I I I I I + +:memh StMemRsAssignxC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=0 & op0607=2 & Rt5HL21 & StMemRsAssignxC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemRsAssignxC10h = tmp; +} + +# (v4,10) memh -- "memh ( Rs32 + #s11:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 0 1 s s s s s P P i 0 1 t t t i i i i i i i i + +:memh StMemRsRelxC10h,Nreg0810 EndPacket is iclass=10 & op27=0 & op2224=6 & op21=1 & op1112=1 & Nreg0810 & StMemRsRelxC10h & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelxC10h = Nreg0810:2; +} + +# (v2,10) memh -- "memh ( Rs32 + #s11:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 0 1 0 s s s s s P P i t t t t t i i i i i i i i +# +# (v2,10) memh -- "memh ( Rs32 + #s11:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 0 1 1 s s s s s P P i t t t t t i i i i i i i i + +:memh StMemRsRelxC10h,Rt5HL21 EndPacket is iclass=10 & op27=0 & op2224=5 & Rt5HL21 & StMemRsRelxC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemRsRelxC10h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1 ) = #S8x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 0 + + 0 1 s s s s s P P I i i i i i i I I I I I I I + +:memh StMemRsRelC3h,Simm16_13_0006x EndPacket is iclass=3 & op2127=0x61 & StMemRsRelC3h & Simm16_13_0006x & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelC3h = Simm16_13_0006x; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) &= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 1 0 t t t t t + +:memh&= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=2 & StMemRsRelxC3h & ru5 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h & ru5:2; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) += #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 0 0 I I I I I + +:memh+= StMemRsRelxC3h,Uimm8_0004 EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=0 & StMemRsRelxC3h & Uimm8_0004 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h + zext(Uimm8_0004); + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) += Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 0 0 t t t t t + +:memh+= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=0 & StMemRsRelxC3h & ru5 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h + ru5:2; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) -= #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 0 1 I I I I I + +:memh-= StMemRsRelxC3h,Uimm8_0004 EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=1 & StMemRsRelxC3h & Uimm8_0004 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h - zext(Uimm8_0004); + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) -= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 0 1 t t t t t + +:memh-= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=1 & StMemRsRelxC3h & ru5 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h - ru5:2; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) = clrbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 1 0 I I I I I + +:memh StMemRsRelxC3h,ClrBit_0004h EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=2 & StMemRsRelxC3h & ClrBit_0004h & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h & ClrBit_0004h; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) = setbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 1 1 I I I I I + +:memh StMemRsRelxC3h,SetBit_0004h EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=3 & StMemRsRelxC3h & SetBit_0004h & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h | SetBit_0004h; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) |= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 1 1 t t t t t + +:memh|= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=3 & StMemRsRelxC3h & ru5 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h | ru5:2; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n + + 0 1 t t t + +:memh MemRsRelShiftC3h,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0306=1 & MemRsRelShiftC3h & Nreg0002 & $(END_PACKET) { + build EndPacket; + <> + MemRsRelShiftC3h = Nreg0002:2; +} + +# (v4,3) memh -- "memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 0 1 0 s s s s s P P n u u u u u n + + t t t t t +# +# (v4,3) memh -- "memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 0 1 1 s s s s s P P n u u u u u n + + t t t t t + +:memh MemRsRelShiftC3h,Ru5HL21 EndPacket is iclass=3 & op2227=0x2d & op0506=0 & MemRsRelShiftC3h & Ru5HL21 & $(END_PACKET) { + tmp:2 = Ru5HL21; + build EndPacket; + <> + MemRsRelShiftC3h = tmp; +} + +# (v4,10) memh -- "memh ( Ru32 << #n2 + #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 u u u u u P P n 0 1 t t t 1 n I I I I I I + +:memh StMemRsRelShiftxC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x6d & op1112=1 & op7=1 & Nreg0810 & StMemRsRelShiftxC10h & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelShiftxC10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Ru32 << #n2 + #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 1 0 u u u u u P P n t t t t t 1 n I I I I I I +# +# (v4,10) memh -- "memh ( Ru32 << #n2 + #U6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 1 1 u u u u u P P n t t t t t 1 n I I I I I I + +:memh StMemRsRelShiftxC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x35 & op7=1 & Rt5HL21 & StMemRsRelShiftxC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemRsRelShiftxC10h = tmp; +} + +# (v4,10) memh -- "memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 0 1 t t t 0 i i i i + 0 + + +:memh StMemAIS4C10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=1 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4C10h & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4C10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 i i i i + 0 + + +:memh StMemAIS4CircMuC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=1 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4CircMuC10h & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4CircMuC10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Rz32 ++ Mu2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 + + + + + + + +# +# (v4,10) memh -- "memh ( Rz32 ++ Mu2 :brev ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 0 1 t t t 0 + + + + + + + + +:memh StMemAIMuC10h,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=1 & op0007=0 & Nreg0810 & StMemAIMuC10h & $(END_PACKET) { + build EndPacket; + <> + StMemAIMuC10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 + + + + + 1 + + +:memh StMemAIICircMuC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=1 & op0007=2 & Nreg0810 & StMemAIICircMuC10h & $(END_PACKET) { + build EndPacket; + <> + StMemAIICircMuC10h = Nreg0810:2; +} + +# (v2,10) memh -- "memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 0 t t t t t 0 i i i i + 0 + +# +# (v2,10) memh -- "memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 0 t t t t t 0 i i i i + 0 + + +:memh StMemAIS4C10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=0 & op7=0 & op0002=0 & Rt5HL21 & StMemAIS4C10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemAIS4C10h = tmp; +} + +# (v2,10) memh -- "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 1 0 z z z z z P P u t t t t t 0 i i i i + 0 + +# +# (v2,10) memh -- "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 1 1 z z z z z P P u t t t t t 0 i i i i + 0 + + +:memh StMemAIS4CircMuC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x25 & op7=0 & op0002=0 & Rt5HL21 & StMemAIS4CircMuC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemAIS4CircMuC10h = tmp; +} + +# (v2,10) memh -- "memh ( Rz32 ++ Mu2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 1 0 z z z z z P P u t t t t t 0 - - - - - - - +# +# (v2,10) memh -- "memh ( Rz32 ++ Mu2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 1 1 z z z z z P P u t t t t t 0 - - - - - - - +# +# (v2,10) memh -- "memh ( Rz32 ++ Mu2 :brev ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 z z z z z P P u t t t t t 0 + + + + + + + +# +# (v2,10) memh -- "memh ( Rz32 ++ Mu2 :brev ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 z z z z z P P u t t t t t 0 + + + + + + + + +:memh StMemAIMuC10h,Rt5HL21 EndPacket is iclass=10 & op2627=3 & op2224=5 & op0007=0 & Rt5HL21 & StMemAIMuC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemAIMuC10h = tmp; +} + +# (v2,10) memh -- "memh ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 1 0 z z z z z P P u t t t t t 0 + + + + + 1 + +# +# (v2,10) memh -- "memh ( Rz32 ++I :circ ( Mu2 ) ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 1 1 z z z z z P P u t t t t t 0 + + + + + 1 + + +:memh StMemAIICircMuC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x25 & op0007=2 & Rt5HL21 & StMemAIICircMuC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemAIICircMuC10h = tmp; +} + +# (v4,4) memh -- "memh ( gp + #u16:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 0 1 i i i i i P P i 0 1 t t t i i i i i i i i + +:memh StMemGPRelxC4h,Nreg0810 EndPacket is iclass=4 & op27=1 & op2124=5 & op1112=1 & Nreg0810 & StMemGPRelxC4h & $(END_PACKET) { + build EndPacket; + <> + StMemGPRelxC4h = Nreg0810:2; +} + +# (v2,4) memh -- "memh ( gp + #u16:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 0 1 0 i i i i i P P i t t t t t i i i i i i i i +# +# (v2,4) memh -- "memh ( gp + #u16:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 0 1 1 i i i i i P P i t t t t t i i i i i i i i + +:memh StMemGPRelxC4h,Rt5HL21 EndPacket is iclass=4 & op27=1 & op2224=1 & Rt5HL21 & StMemGPRelxC4h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemGPRelxC4h = tmp; +} + +# (v4,9) memh -- "if ( Pt4 ) Rd32 = memh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memh -- "if ( ! Pt4 ) Rd32 = memh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memh -- "if ( Pt4 .new ) Rd32 = memh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memh -- "if ( ! Pt4 .new ) Rd32 = memh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memh^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9h EndPacket is iclass=9 & op2127=0x7a & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9h & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemAbsU6xC9h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memh -- "if ( Pt4 ) Rd32 = memh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memh -- "if ( ! Pt4 ) Rd32 = memh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memh -- "if ( Pt4 .new ) Rd32 = memh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memh -- "if ( ! Pt4 .new ) Rd32 = memh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d + +:memh^PuCond1112_N25_S26 rd5,LdMemRsRelxC4h EndPacket is iclass=4 & op27=0 & op2224=5 & op21=0 & op13=0 & rd5 & LdMemRsRelxC4h & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemRsRelxC4h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memh -- "if ( Pt4 ) Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memh -- "if ( ! Pt4 ) Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memh -- "if ( Pt4 .new ) Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memh -- "if ( ! Pt4 .new ) Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memh^PuCond0910_N12_S11 rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5a & op13=1 & rd5 & LdMemAIS4C9h & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemAIS4C9h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memh -- "if ( Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 0 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memh -- "if ( ! Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 0 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memh -- "if ( Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 0 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memh -- "if ( ! Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 0 1 0 s s s s s P P n t t t t t n v v d d d d d + +:memh^PuCond0506_N25_S24 rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2627=0 & op2123=2 & rd5 & MemRsRelShiftC3h & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(MemRsRelShiftC3h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,10) memh -- "if ( Pv4 ) memh ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 1 t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 1 t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 ) memh ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 1 t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 1 t t t 1 i i i i 1 v v + +:memh^PuCond0001_N13_S02 StMemAbsU6xC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1820=0 & op1112=1 & op7=1 & Nreg0810 & StMemAbsU6xC10h & PuCond0001_N13_S02 & $(END_PACKET) { + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10h = Nreg0810:2; + +} + +# (v4,10) memh -- "if ( Pv4 ) memh ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 ) memh ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( Pv4 ) memh ( #u6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 ) memh ( #u6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( #u6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( #u6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 1 t t t t t 1 i i i i 1 v v + +:memh^PuCond0001_N13_S02 StMemAbsU6xC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x3d & op1820=0 & op7=1 & Rt5HL21 & StMemAbsU6xC10h & PuCond0001_N13_S02 & $(END_PACKET) { + tmp:2 = Rt5HL21; + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10h = tmp; + +} + +# (v4,3) memh -- "if ( Pv4 ) memh ( Rs32 + #u6:1 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 0 0 1 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memh -- "if ( ! Pv4 ) memh ( Rs32 + #u6:1 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 1 0 1 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memh -- "if ( Pv4 .new ) memh ( Rs32 + #u6:1 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 0 0 1 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 1 0 1 s s s s s P P I i i i i i i v v I I I I I + +:memh^PuCond0506_N24_S23 StMemRsRelC3h,Simm16_13_0004x EndPacket is iclass=3 & op2527=4 & op2122=1 & Simm16_13_0004x & StMemRsRelC3h & PuCond0506_N24_S23 & $(END_PACKET) { + build PuCond0506_N24_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelC3h = Simm16_13_0004x; + +} + +# (v4,4) memh -- "if ( Pv4 ) memh ( Rs32 + #u6:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( Pv4 .new ) memh ( Rs32 + #u6:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( ! Pv4 ) memh ( Rs32 + #u6:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v + +:memh^PuCond0001_N25_S26 StMemRsRelxC4h,Nreg0810 EndPacket is iclass=4 & op27=0 & op2224=2 & op21=1 & op1112=1 & op2=0 & Nreg0810 & StMemRsRelxC4h & PuCond0001_N25_S26 & $(END_PACKET) { + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4h = Nreg0810:2; + +} + +# (v2,4) memh -- "if ( Pv4 ) memh ( Rs32 + #u6:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memh -- "if ( ! Pv4 ) memh ( Rs32 + #u6:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memh -- "if ( Pv4 ) memh ( Rs32 + #u6:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memh -- "if ( ! Pv4 ) memh ( Rs32 + #u6:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( Pv4 .new ) memh ( Rs32 + #u6:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( Pv4 .new ) memh ( Rs32 + #u6:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v + +:memh^PuCond0001_N25_S26 StMemRsRelxC4h,Rt5HL21 EndPacket is iclass=4 & op27=0 & op2224=1 & op2=0 & Rt5HL21 & StMemRsRelxC4h & PuCond0001_N25_S26 & $(END_PACKET) { + tmp:2 = Rt5HL21; + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4h = tmp; + +} + +# (v4,3) memh -- "if ( Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 0 1 s s s s s P P n u u u u u n v v 0 1 t t t +# +# (v4,3) memh -- "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 0 1 s s s s s P P n u u u u u n v v 0 1 t t t +# +# (v4,3) memh -- "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 0 1 s s s s s P P n u u u u u n v v 0 1 t t t +# +# (v4,3) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 0 1 s s s s s P P n u u u u u n v v 0 1 t t t + +:memh^PuCond0506_N25_S24 MemRsRelShiftC3h,Nreg0002 EndPacket is iclass=3 & op2627=1 & op2123=5 & op0304=1 & Nreg0002 & MemRsRelShiftC3h & PuCond0506_N25_S24 & $(END_PACKET) { + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3h = Nreg0002:2; + +} + +# (v4,3) memh -- "if ( Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 0 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 0 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 0 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 0 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 0 1 1 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 0 1 1 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 0 1 1 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 0 1 1 s s s s s P P n u u u u u n v v t t t t t + +:memh^PuCond0506_N25_S24 MemRsRelShiftC3h,Ru5HL21 EndPacket is iclass=3 & op2627=1 & op2223=1 & Ru5HL21 & MemRsRelShiftC3h & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:2 = Ru5HL21; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3h = tmp; + +} + +# (v4,10) memh -- "if ( Pv4 ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 1 t t t 0 i i i i 0 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 1 t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 1 t t t 0 i i i i 1 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 1 t t t 1 i i i i 1 v v + +:memh^PuCond0001_N07_S02 StMemAIS4C10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=5 & Nreg0810 & StMemAIS4C10h & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10h = Nreg0810:2; + +} + +# (v4,10) memh -- "if ( Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v2,10) memh -- "if ( Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memh -- "if ( ! Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v +# +# (v2,10) memh -- "if ( Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memh -- "if ( ! Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 1 t t t t t 0 i i i i 1 v v +# + +:memh^PuCond0001_N07_S02 StMemAIS4C10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=1 & Rt5HL21 & StMemAIS4C10h & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + tmp:2 = Rt5HL21; + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10h = tmp; + +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 1 0 f f f f f P P 0 1 I I I I + I I y y y y y + +:memh_fifo Rdd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x52 & op1213=1 & op7=0 & LdMemRsAssignxC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemRsAssignxC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 0 1 0 s s s s s P P i i i i i i i i i y y y y y + +:memh_fifo Rdd5,LdMemRsRelxC9h EndPacket is iclass=9 & op27=0 & op2124=2 & LdMemRsRelxC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemRsRelxC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 1 0 t t t t t P P n 1 I I I I n I I y y y y y + +:memh_fifo Rdd5,LdMemRsRelShiftxC9h EndPacket is iclass=9 & op2127=0x62 & op12=1 & LdMemRsRelShiftxC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemRsRelShiftxC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 1 0 z z z z z P P 0 0 + + + i i i i y y y y y + +:memh_fifo Rdd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x52 & op0913=0 & LdMemAIS4C9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemAIS4C9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 1 0 z z z z z P P u 0 + + 0 i i i i y y y y y + +:memh_fifo Rdd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x42 & op0912=0 & LdMemAIS4CircMuC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemAIS4CircMuC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 1 0 z z z z z P P u 0 + + + + 0 + + y y y y y +# +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 0 1 0 z z z z z P P u 0 + + + + 0 + + y y y y y + +:memh_fifo Rdd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=2 & op0512=0 & LdMemAIMuC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemAIMuC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 1 0 z z z z z P P u 0 + + 1 + 0 + + y y y y y + +:memh_fifo Rdd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x42 & op0512=0x10 & LdMemAIICircMuC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemAIICircMuC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memub -- "Rd32 = memub ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 f f f f f P P 0 1 I I I I + I I d d d d d + +:memub Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x59 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { + Rd5 = zext(LdMemRsAssignxC9b); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rs32 + #s11:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 0 0 1 s s s s s P P i i i i i i i i i d d d d d + +:memub Rd5,LdMemRsRelxC9b0 EndPacket is iclass=9 & op27=0 & op2224=4 & op21=1 & Rd5 & LdMemRsRelxC9b0 & $(END_PACKET) { + Rd5 = zext(LdMemRsRelxC9b0); + build EndPacket; +} + +# (v4,3) memub -- "Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 0 0 1 s s s s s P P n t t t t t n + + d d d d d + +:memub Rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2127=0x51 & op0506=0 & Rd5 & MemRsRelShiftC3b & $(END_PACKET) { + Rd5 = zext(MemRsRelShiftC3b); + build EndPacket; +} + +# (v4,9) memub -- "Rd32 = memub ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 0 1 t t t t t P P n 1 I I I I n I I d d d d d + +:memub Rd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x69 & op12=1 & Rd5 & LdMemRsRelShiftxC9b & $(END_PACKET) { + Rd5 = zext(LdMemRsRelShiftxC9b); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:memub Rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x59 & op0913=0 & Rd5 & LdMemAIS4C9b0 & $(END_PACKET) { + Rd5 = zext(LdMemAIS4C9b0); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 0 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memub Rd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x49 & op0912=0 & Rd5 & LdMemAIS4CircMuC9b0 & $(END_PACKET) { + Rd5 = zext(LdMemAIS4CircMuC9b0); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memub Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=9 & op0512=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { + Rd5 = zext(LdMemAIMuC9b); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 0 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memub Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x49 & op0512=0x10 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { + Rd5 = zext(LdMemAIICircMuC9b); + build EndPacket; +} + +# (v2,4) memub -- "Rd32 = memub ( gp + #u16:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 0 0 1 i i i i i P P i i i i i i i i i d d d d d + +:memub Rd5,LdMemGPRelxC4b EndPacket is iclass=4 & op27=1 & op2224=4 & op21=1 & Rd5 & LdMemGPRelxC4b & $(END_PACKET) { + Rd5 = zext(LdMemGPRelxC4b); + build EndPacket; +} + +# (v4,9) memub -- "if ( Pt4 ) Rd32 = memub ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memub -- "if ( ! Pt4 ) Rd32 = memub ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memub -- "if ( Pt4 .new ) Rd32 = memub ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memub -- "if ( ! Pt4 .new ) Rd32 = memub ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memub^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9b EndPacket is iclass=9 & op2127=0x79 & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9b & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemAbsU6xC9b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memub -- "if ( Pt4 ) Rd32 = memub ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memub -- "if ( ! Pt4 ) Rd32 = memub ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memub -- "if ( Pt4 .new ) Rd32 = memub ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memub -- "if ( ! Pt4 .new ) Rd32 = memub ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d + +:memub^PuCond1112_N25_S26 rd5,LdMemRsRelxC4b EndPacket is iclass=4 & op27=0 & op2224=4 & op21=1 & op13=0 & rd5 & LdMemRsRelxC4b & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemRsRelxC4b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memub -- "if ( Pt4 ) Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memub -- "if ( ! Pt4 ) Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memub -- "if ( Pt4 .new ) Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memub -- "if ( ! Pt4 .new ) Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memub^PuCond0910_N12_S11 rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x59 & op13=1 & rd5 & LdMemAIS4C9b0 & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemAIS4C9b0); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memub -- "if ( Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 0 0 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memub -- "if ( ! Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 0 0 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memub -- "if ( Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 0 0 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memub -- "if ( ! Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 0 0 1 s s s s s P P n t t t t t n v v d d d d d + +:memub^PuCond0506_N25_S24 rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2627=0 & op2123=1 & rd5 & MemRsRelShiftC3b & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(MemRsRelShiftC3b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,9) memubh -- "Rd32 = memubh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 1 1 f f f f f P P 0 1 I I I I + I I d d d d d + +macro unpack16to32(src2, dest4) { + hi:2 = src2 & 0xff00; + lo:2 = src2 & 0x00ff; + dest4 = (zext(hi) << 8) + zext(lo); +} + +:memubh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x53 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { + unpack16to32(LdMemRsAssignxC9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 0 1 1 s s s s s P P i i i i i i i i i d d d d d + +:memubh Rd5,LdMemRsRelxC9h EndPacket is iclass=9 & op27=0 & op2224=1 & op21=1 & Rd5 & LdMemRsRelxC9h & $(END_PACKET) { + unpack16to32(LdMemRsRelxC9h, Rd5); + build EndPacket; +} + +# (v4,9) memubh -- "Rd32 = memubh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 1 1 t t t t t P P n 1 I I I I n I I d d d d d + +:memubh Rd5,LdMemRsRelShiftxC9h EndPacket is iclass=9 & op2127=0x63 & op12=1 & Rd5 & LdMemRsRelShiftxC9h & $(END_PACKET) { + unpack16to32(LdMemRsRelShiftxC9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 1 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:memubh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x53 & op0913=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { + unpack16to32(LdMemAIS4C9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 1 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memubh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x43 & op0912=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { + unpack16to32(LdMemAIS4CircMuC9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memubh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0x3 & op0512=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { + unpack16to32(LdMemAIMuC9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 1 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memubh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x43 & op0512=0x10 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { + unpack16to32(LdMemAIICircMuC9h, Rd5); + build EndPacket; +} + +# (v4,9) memubh -- "Rdd32 = memubh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 0 1 f f f f f P P 0 1 I I I I + I I d d d d d + +macro unpack32to64(src4, dest8) { + hi0:4 = src4 & 0x0000ff00; + lo0:4 = src4 & 0x000000ff; + hi1:4 = src4 & 0xff000000; + lo1:4 = src4 & 0x00ff0000; + dest8 = (zext(hi1) << 32) + (zext(lo1) << 16) + (zext(hi0) << 8) + zext(lo0); +} + +:memubh Rdd5,LdMemRsAssignxC9w EndPacket is iclass=9 & op2127=0x55 & op1213=1 & op7=0 & Rdd5 & LdMemRsAssignxC9w & $(END_PACKET) { + unpack32to64(LdMemRsAssignxC9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rs32 + #s11:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 1 0 1 s s s s s P P i i i i i i i i i d d d d d + +:memubh Rdd5,LdMemRsRelxC9w EndPacket is iclass=9 & op27=0 & op2224=2 & op21=1 & Rdd5 & LdMemRsRelxC9w & $(END_PACKET) { + unpack32to64(LdMemRsRelxC9w, Rdd5); + build EndPacket; +} + +# (v4,9) memubh -- "Rdd32 = memubh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 0 1 t t t t t P P n 1 I I I I n I I d d d d d + +:memubh Rdd5,LdMemRsRelShiftxC9w EndPacket is iclass=9 & op2127=0x65 & op12=1 & Rdd5 & LdMemRsRelShiftxC9w & $(END_PACKET) { + unpack32to64(LdMemRsRelShiftxC9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 0 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:memubh Rdd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x55 & op0913=0 & Rdd5 & LdMemAIS4C9w & $(END_PACKET) { + unpack32to64(LdMemAIS4C9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 0 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memubh Rdd5,LdMemAIS4CircMuC9w EndPacket is iclass=9 & op2127=0x45 & op0912=0 & Rdd5 & LdMemAIS4CircMuC9w & $(END_PACKET) { + unpack32to64(LdMemAIS4CircMuC9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 1 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memubh Rdd5,LdMemAIMuC9w EndPacket is iclass=9 & op2627=3 & op2124=0x5 & op0512=0 & Rdd5 & LdMemAIMuC9w & $(END_PACKET) { + unpack32to64(LdMemAIMuC9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 0 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memubh Rdd5,LdMemAIICircMuC9w EndPacket is iclass=9 & op2127=0x45 & op0512=0x10 & Rdd5 & LdMemAIICircMuC9w & $(END_PACKET) { + unpack32to64(LdMemAIICircMuC9w, Rdd5); + build EndPacket; +} + +# (v4,9) memuh -- "Rd32 = memuh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 f f f f f P P 0 1 I I I I + I I d d d d d + +:memuh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x5b & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { + Rd5 = zext(LdMemRsAssignxC9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 0 1 1 s s s s s P P i i i i i i i i i d d d d d + +:memuh Rd5,LdMemRsRelxC9h EndPacket is iclass=9 & op27=0 & op2224=5 & op21=1 & Rd5 & LdMemRsRelxC9h & $(END_PACKET) { + Rd5 = zext(LdMemRsRelxC9h); + build EndPacket; +} + +# (v4,3) memuh -- "Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 0 1 1 s s s s s P P n t t t t t n + + d d d d d + +:memuh Rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2127=0x53 & op0506=0 & Rd5 & MemRsRelShiftC3h & $(END_PACKET) { + Rd5 = zext(MemRsRelShiftC3h); + build EndPacket; +} + +# (v4,9) memuh -- "Rd32 = memuh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 1 1 t t t t t P P n 1 I I I I n I I d d d d d + +:memuh Rd5,LdMemRsRelShiftxC9h EndPacket is iclass=9 & op2127=0x6b & op12=1 & Rd5 & LdMemRsRelShiftxC9h & $(END_PACKET) { + Rd5 = zext(LdMemRsRelShiftxC9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:memuh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5b & op0913=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { + Rd5 = zext(LdMemAIS4C9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 1 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memuh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x4b & op0912=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { + Rd5 = zext(LdMemAIS4CircMuC9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memuh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0xb & op0512=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { + Rd5 = zext(LdMemAIMuC9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 1 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memuh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x4b & op0512=0x10 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { + Rd5 = zext(LdMemAIICircMuC9h); + build EndPacket; +} + +# (v2,4) memuh -- "Rd32 = memuh ( gp + #u16:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 0 1 1 i i i i i P P i i i i i i i i i d d d d d + +:memuh Rd5,LdMemGPRelxC4h EndPacket is iclass=4 & op27=1 & op2224=5 & op21=1 & Rd5 & LdMemGPRelxC4h & $(END_PACKET) { + Rd5 = zext(LdMemGPRelxC4h); + build EndPacket; +} + +# (v4,9) memuh -- "if ( Pt4 ) Rd32 = memuh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memuh -- "if ( ! Pt4 ) Rd32 = memuh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memuh -- "if ( Pt4 .new ) Rd32 = memuh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memuh -- "if ( ! Pt4 .new ) Rd32 = memuh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memuh^PuCond0910_N12_S11 rd5,LdMemU6xC9h EndPacket is iclass=9 & op2127=0x7b & op13=1 & op0507=4 & rd5 & LdMemU6xC9h & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemU6xC9h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memuh -- "if ( Pt4 ) Rd32 = memuh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memuh -- "if ( ! Pt4 ) Rd32 = memuh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memuh -- "if ( Pt4 .new ) Rd32 = memuh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memuh -- "if ( ! Pt4 .new ) Rd32 = memuh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d + +:memuh^PuCond1112_N25_S26 rd5,LdMemRsRelxC4h EndPacket is iclass=4 & op27=0 & op2224=5 & op21=1 & op13=0 & rd5 & LdMemRsRelxC4h & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemRsRelxC4h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memuh -- "if ( Pt4 ) Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memuh -- "if ( ! Pt4 ) Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memuh -- "if ( Pt4 .new ) Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memuh -- "if ( ! Pt4 .new ) Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memuh^PuCond0910_N12_S11 rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5b & op13=1 & rd5 & LdMemAIS4C9h & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemAIS4C9h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memuh -- "if ( Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 0 1 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memuh -- "if ( ! Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 0 1 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memuh -- "if ( Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 0 1 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memuh -- "if ( ! Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 0 1 1 s s s s s P P n t t t t t n v v d d d d d + +:memuh^PuCond0506_N25_S24 rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2627=0 & op2123=3 & rd5 & MemRsRelShiftC3h & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(MemRsRelShiftC3h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,9) memw -- "Rd32 = memw ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 f f f f f P P 0 1 I I I I + I I d d d d d + +:memw Rd5,LdMemRsAssignxC9w EndPacket is iclass=9 & op2127=0x5c & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9w & $(END_PACKET) { + Rd5 = LdMemRsAssignxC9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rs32 + #s11:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 1 0 0 s s s s s P P i i i i i i i i i d d d d d + +:memw Rd5,LdMemRsRelxC9w EndPacket is iclass=9 & op27=0 & op2224=6 & op21=0 & Rd5 & LdMemRsRelxC9w & $(END_PACKET) { + Rd5 = LdMemRsRelxC9w; + build EndPacket; +} + +# (v4,3) memw -- "Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 1 0 0 s s s s s P P n t t t t t n + + d d d d d + +:memw Rd5,MemRsRelShiftC3w EndPacket is iclass=3 & op2127=0x54 & op0506=0 & Rd5 & MemRsRelShiftC3w & $(END_PACKET) { + Rd5 = MemRsRelShiftC3w; + build EndPacket; +} + +# (v4,9) memw -- "Rd32 = memw ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 1 0 0 t t t t t P P n 1 I I I I n I I d d d d d + +:memw Rd5,LdMemRsRelShiftxC9w EndPacket is iclass=9 & op2127=0x6c & op12=1 & Rd5 & LdMemRsRelShiftxC9w & $(END_PACKET) { + Rd5 = LdMemRsRelShiftxC9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 0 0 + + + i i i i d d d d d + +:memw Rd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x5c & op0913=0 & Rd5 & LdMemAIS4C9w & $(END_PACKET) { + Rd5 = LdMemAIS4C9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 0 0 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memw Rd5,LdMemAIS4CircMuC9w EndPacket is iclass=9 & op2127=0x4c & op0912=0 & Rd5 & LdMemAIS4CircMuC9w & $(END_PACKET) { + Rd5 = LdMemAIS4CircMuC9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 1 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memw Rd5,LdMemAIMuC9w EndPacket is iclass=9 & op2627=3 & op2124=0xc & op0512=0 & Rd5 & LdMemAIMuC9w & $(END_PACKET) { + Rd5 = LdMemAIMuC9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 0 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memw Rd5,LdMemAIICircMuC9w EndPacket is iclass=9 & op2127=0x4c & op0512=0x10 & Rd5 & LdMemAIICircMuC9w & $(END_PACKET) { + Rd5 = LdMemAIICircMuC9w; + build EndPacket; +} + +# (v2,4) memw -- "Rd32 = memw ( gp + #u16:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 1 0 0 i i i i i P P i i i i i i i i i d d d d d + +:memw Rd5,LdMemGPRelxC4w EndPacket is iclass=4 & op27=1 & op2224=6 & op21=0 & Rd5 & LdMemGPRelxC4w & $(END_PACKET) { + Rd5 = LdMemGPRelxC4w; + build EndPacket; +} + +# (v4,10) memw -- "memw ( Rf32 = #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 1 0 t t t 1 + I I I I I I + +:memw StMemRsAssignxC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=2 & op0607=2 & Nreg0810 & StMemRsAssignxC10w & $(END_PACKET) { + build EndPacket; + <> + StMemRsAssignxC10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Rf32 = #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 f f f f f P P 0 t t t t t 1 - I I I I I I + +:memw StMemRsAssignxC10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=0 & op0607=2 & rt5 & StMemRsAssignxC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemRsAssignxC10w = tmp; +} + +# (v4,10) memw -- "memw ( Rs32 + #s11:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 0 1 s s s s s P P i 1 0 t t t i i i i i i i i + +:memw StMemRsRelxC10w,Nreg0810 EndPacket is iclass=10 & op27=0 & op2224=6 & op21=1 & op1112=2 & Nreg0810 & StMemRsRelxC10w & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelxC10w = Nreg0810; +} + +# (v2,10) memw -- "memw ( Rs32 + #s11:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 0 0 s s s s s P P i t t t t t i i i i i i i i + +:memw StMemRsRelxC10w,rt5 EndPacket is iclass=10 & op27=0 & op2224=6 & op21=0 & rt5 & StMemRsRelxC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemRsRelxC10w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2 ) = #S8x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 0 + + 1 0 s s s s s P P I i i i i i i I I I I I I I + +:memw StMemRsRelC3w,Simm32_13_0006x EndPacket is iclass=3 & op2127=0x62 & StMemRsRelC3w & Simm32_13_0006x & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelC3w = Simm32_13_0006x; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) &= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 1 0 t t t t t + +:memw&= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=2 & StMemRsRelxC3w & ru5 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w & ru5; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) += #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 0 0 I I I I I + +:memw+= StMemRsRelxC3w,Uimm8_0004 EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=0 & StMemRsRelxC3w & Uimm8_0004 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w + zext(Uimm8_0004); + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) += Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 0 0 t t t t t + +:memw+= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=0 & StMemRsRelxC3w & ru5 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w + ru5; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) -= #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 0 1 I I I I I + +:memw-= StMemRsRelxC3w,Uimm8_0004 EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=1 & StMemRsRelxC3w & Uimm8_0004 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w - zext(Uimm8_0004); + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) -= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 0 1 t t t t t + +:memw-= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=1 & StMemRsRelxC3w & ru5 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w - ru5; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) = clrbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 1 0 I I I I I + +:memw StMemRsRelxC3w,ClrBit_0004w EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=2 & StMemRsRelxC3w & ClrBit_0004w & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w & ClrBit_0004w; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) = setbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 1 1 I I I I I + +:memw StMemRsRelxC3w,SetBit_0004w EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=3 & StMemRsRelxC3w & SetBit_0004w & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w | SetBit_0004w; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) |= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 1 1 t t t t t + +:memw|= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=3 & StMemRsRelxC3w & ru5 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w | ru5; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n + + 1 0 t t t + +:memw MemRsRelShiftC3w,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0306=2 & MemRsRelShiftC3w & Nreg0002 & $(END_PACKET) { + build EndPacket; + <> + MemRsRelShiftC3w = Nreg0002; +} + +# (v4,3) memw -- "memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 0 0 s s s s s P P n u u u u u n + + t t t t t + +:memw MemRsRelShiftC3w,ru5 EndPacket is iclass=3 & op2127=0x5c & op0506=0 & MemRsRelShiftC3w & ru5 & $(END_PACKET) { + tmp:4 = ru5; + build EndPacket; + <> + MemRsRelShiftC3w = tmp; +} + +# (v4,10) memw -- "memw ( Ru32 << #n2 + #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 u u u u u P P n 1 0 t t t 1 n I I I I I I + +:memw StMemRsRelShiftxC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x6d & op1112=2 & op7=1 & Nreg0810 & StMemRsRelShiftxC10w & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelShiftxC10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Ru32 << #n2 + #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 0 u u u u u P P n t t t t t 1 n I I I I I I + +:memw StMemRsRelShiftxC10w,rt5 EndPacket is iclass=10 & op2127=0x6c & op7=1 & rt5 & StMemRsRelShiftxC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemRsRelShiftxC10w = tmp; +} + +# (v4,10) memw -- "memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 1 0 t t t 0 i i i i + 0 + + +:memw StMemAIS4C10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=2 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4C10w & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4C10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 i i i i + 0 + + +:memw StMemAIS4CircMuC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=2 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4CircMuC10w & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4CircMuC10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Rz32 ++ Mu2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 + + + + + + + +# +# (v4,10) memw -- "memw ( Rz32 ++ Mu2 :brev ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 1 0 t t t 0 + + + + + + + + +:memw StMemAIMuC10w,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=2 & op0007=0 & Nreg0810 & StMemAIMuC10w & $(END_PACKET) { + build EndPacket; + <> + StMemAIMuC10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 + + + + + 1 + + +:memw StMemAIICircMuC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=2 & op0007=2 & Nreg0810 & StMemAIICircMuC10w & $(END_PACKET) { + build EndPacket; + <> + StMemAIICircMuC10w = Nreg0810; +} + +# (v2,10) memw -- "memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 0 t t t t t 0 i i i i - 0 - + +:memw StMemAIS4C10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=0 & op7=0 & op0002=0 & rt5 & StMemAIS4C10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemAIS4C10w = tmp; +} + +# (v2,10) memw -- "memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 0 z z z z z P P u t t t t t 0 i i i i + 0 + + +:memw StMemAIS4CircMuC10w,rt5 EndPacket is iclass=10 & op2127=0x4c & op7=0 & op0002=0 & rt5 & StMemAIS4CircMuC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemAIS4CircMuC10w = tmp; +} + +# (v2,10) memw -- "memw ( Rz32 ++ Mu2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 0 z z z z z P P u t t t t t 0 + + + + + + + +# +# (v2,10) memw -- "memw ( Rz32 ++ Mu2 :brev ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 z z z z z P P u t t t t t 0 + + + + + + + + +:memw StMemAIMuC10w,rt5 EndPacket is iclass=10 & op2627=3 & op2124=0xc & op0007=0 & rt5 & StMemAIMuC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemAIMuC10w = tmp; +} + +# (v2,10) memw -- "memw ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 0 z z z z z P P u t t t t t 0 + + + + + 1 + + +:memw StMemAIICircMuC10w,rt5 EndPacket is iclass=10 & op2127=0x4c & op0007=2 & rt5 & StMemAIICircMuC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemAIICircMuC10w = tmp; +} + +# (v4,4) memw -- "memw ( gp + #u16:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 0 1 i i i i i P P i 1 0 t t t i i i i i i i i + +:memw StMemGPRelxC4w,Nreg0810 EndPacket is iclass=4 & op27=1 & op2224=2 & op21=1 & op1112=2 & Nreg0810 & StMemGPRelxC4w & $(END_PACKET) { + build EndPacket; + <> + StMemGPRelxC4w = Nreg0810; +} + +# (v2,4) memw -- "memw ( gp + #u16:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 0 0 i i i i i P P i t t t t t i i i i i i i i + +:memw StMemGPRelxC4w,rt5 EndPacket is iclass=4 & op27=1 & op2224=2 & op21=0 & rt5 & StMemGPRelxC4w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemGPRelxC4w = tmp; +} + +# (v4,9) memw -- "if ( Pt4 ) Rd32 = memw ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memw -- "if ( ! Pt4 ) Rd32 = memw ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memw -- "if ( Pt4 .new ) Rd32 = memw ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memw -- "if ( ! Pt4 .new ) Rd32 = memw ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memw^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9w EndPacket is iclass=9 & op2127=0x7c & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9w & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemAbsU6xC9w; + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memw -- "if ( Pt4 ) Rd32 = memw ( Rs32 + #u6:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memw -- "if ( ! Pt4 ) Rd32 = memw ( Rs32 + #u6:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memw -- "if ( Pt4 .new ) Rd32 = memw ( Rs32 + #u6:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memw -- "if ( ! Pt4 .new ) Rd32 = memw ( Rs32 + #u6:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d + +:memw^PuCond1112_N25_S26 rd5,LdMemRsRelxC4w EndPacket is iclass=4 & op27=0 & op2224=6 & op21=0 & op13=0 & rd5 & LdMemRsRelxC4w & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemRsRelxC4w; + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memw -- "if ( Pt4 ) Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memw -- "if ( ! Pt4 ) Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memw -- "if ( Pt4 .new ) Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memw -- "if ( ! Pt4 .new ) Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memw^PuCond0910_N12_S11 rd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x5c & op13=1 & rd5 & LdMemAIS4C9w & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemAIS4C9w; + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memw -- "if ( Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 1 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memw -- "if ( ! Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 1 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memw -- "if ( Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 1 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memw -- "if ( ! Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 1 0 0 s s s s s P P n t t t t t n v v d d d d d + +:memw^PuCond0506_N25_S24 rd5,MemRsRelShiftC3w EndPacket is iclass=3 & op2627=0 & op2123=4 & rd5 & MemRsRelShiftC3w & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = MemRsRelShiftC3w; + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,10) memw -- "if ( Pv4 ) memw ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 1 0 t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( Pv4 .new ) memw ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 1 0 t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 ) memw ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 1 0 t t t 1 i i i i 1 v v +# +# (v4,10) memw -- "if ( ! Pv4 .new ) memw ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 1 0 t t t 1 i i i i 1 v v + +:memw^PuCond0001_N13_S02 StMemAbsU6xC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1820=0 & op1112=2 & op7=1 & Nreg0810 & StMemAbsU6xC10w & PuCond0001_N13_S02 & $(END_PACKET) { + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10w = Nreg0810; + +} + +# (v4,10) memw -- "if ( Pv4 ) memw ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 ) memw ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memw -- "if ( Pv4 .new ) memw ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 .new ) memw ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 + + + i i P P 1 t t t t t 1 i i i i 1 v v + +:memw^PuCond0001_N13_S02 StMemAbsU6xC10w,rt5 EndPacket is iclass=10 & op2127=0x7c & op1820=0 & op7=1 & rt5 & StMemAbsU6xC10w & PuCond0001_N13_S02 & $(END_PACKET) { + tmp:4 = rt5; + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10w = tmp; + +} + +# (v4,3) memw -- "if ( Pv4 ) memw ( Rs32 + #u6:2 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 0 1 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memw -- "if ( ! Pv4 ) memw ( Rs32 + #u6:2 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 1 1 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memw -- "if ( Pv4 .new ) memw ( Rs32 + #u6:2 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 0 1 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + #u6:2 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 1 1 0 s s s s s P P I i i i i i i v v I I I I I + +:memw^PuCond0506_N24_S23 StMemRsRelC3w,Simm32_13_0004x EndPacket is iclass=3 & op2527=4 & op2122=2 & Simm32_13_0004x & StMemRsRelC3w & PuCond0506_N24_S23 & $(END_PACKET) { + build PuCond0506_N24_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelC3w = Simm32_13_0004x; + +} + +# (v4,4) memw -- "if ( Pv4 ) memw ( Rs32 + #u6:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( ! Pv4 ) memw ( Rs32 + #u6:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( Pv4 .new ) memw ( Rs32 + #u6:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + #u6:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v + +:memw^PuCond0001_N25_S26 StMemRsRelxC4w,Nreg0810 EndPacket is iclass=4 & op27=0 & op2224=2 & op21=1 & op1112=2 & op2=0 & Nreg0810 & StMemRsRelxC4w & PuCond0001_N25_S26 & $(END_PACKET) { + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4w = Nreg0810; + +} + +# (v2,4) memw -- "if ( Pv4 ) memw ( Rs32 + #u6:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memw -- "if ( ! Pv4 ) memw ( Rs32 + #u6:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( Pv4 .new ) memw ( Rs32 + #u6:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + #u6:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v + +:memw^PuCond0001_N25_S26 StMemRsRelxC4w,rt5 EndPacket is iclass=4 & op27=0 & op2224=2 & op21=0 & op2=0 & rt5 & StMemRsRelxC4w & PuCond0001_N25_S26 & $(END_PACKET) { + tmp:4 = rt5; + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4w = tmp; + +} + +# (v4,3) memw -- "if ( Pv4 ) memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 0 1 s s s s s P P n u u u u u n v v 1 0 t t t +# +# (v4,3) memw -- "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 0 1 s s s s s P P n u u u u u n v v 1 0 t t t +# +# (v4,3) memw -- "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 0 1 s s s s s P P n u u u u u n v v 1 0 t t t +# +# (v4,3) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 0 1 s s s s s P P n u u u u u n v v 1 0 t t t + +:memw^PuCond0506_N25_S24 MemRsRelShiftC3w,Nreg0002 EndPacket is iclass=3 & op2627=1 & op2123=5 & op0304=2 & Nreg0002 & MemRsRelShiftC3w & PuCond0506_N25_S24 & $(END_PACKET) { + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3w = Nreg0002; + +} + +# (v4,3) memw -- "if ( Pv4 ) memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memw -- "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memw -- "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 0 0 s s s s s P P n u u u u u n v v t t t t t + +:memw^PuCond0506_N25_S24 MemRsRelShiftC3w,ru5 EndPacket is iclass=3 & op2627=1 & op2223=2 & op21=0 & ru5 & MemRsRelShiftC3w & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = ru5; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3w = tmp; + +} + +# (v4,10) memw -- "if ( Pv4 ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 1 0 t t t 0 i i i i 0 v v +# +# (v4,10) memw -- "if ( Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 1 0 t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 1 0 t t t 0 i i i i 1 v v +# +# (v4,10) memw -- "if ( ! Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 1 0 t t t 1 i i i i 1 v v + +:memw^PuCond0001_N07_S02 StMemAIS4C10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=6 & Nreg0810 & StMemAIS4C10w & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10w = Nreg0810; + +} + +# (v4,10) memw -- "if ( Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v2,10) memw -- "if ( Pv4 ) memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memw -- "if ( ! Pv4 ) memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v + +:memw^PuCond0001_N07_S02 StMemAIS4C10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=1 & rt5 & StMemAIS4C10w & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + tmp:4 = rt5; + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10w = tmp; + +} + +# memw_rl -- "memw_rl ( Rs32 ):at = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P - t t t t t - - 0 0 1 0 d d + +:memw_rl":at" StMemRsRelPdC9w, rt5 EndPacket is iclass=0xa & op2127=0x05 & op13=0 & rt5 & op0607=0 & op0205=0x2 & StMemRsRelPdC9w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + waitAllThreads(); + StMemRsRelPdC9w = tmp; +} + +# memw_rl -- "memw_rl ( Rs32 ):st = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P - t t t t t - - 1 0 1 0 d d + +:memw_rl":st" StMemRsRelPdC9w, rt5 EndPacket is iclass=0xa & op2127=0x05 & op13=0 & rt5 & op0607=0 & op0205=0xa & StMemRsRelPdC9w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + waitSameDomain(); + StMemRsRelPdC9w = tmp; +} + + +# (v2,9) memw_locked -- "Rd32 = memw_locked ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 0 + + + + + + + d d d d d + +:memw_locked Rd5,LdMemRsRelC9w EndPacket is iclass=9 & op2127=0x10 & op0513=0 & Rd5 & LdMemRsRelC9w & $(END_PACKET) { + # NOTE: Manual does not indicate lock use, cannot be group with other instructions + Rd5 = LdMemRsRelC9w; + build EndPacket; +} + +# (v2,10) memw_locked -- "memw_locked ( Rs32 , Pd4 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P + t t t t t + + + + + + d d + +:memw_locked StMemRsRelPdC9w,rt5 EndPacket is iclass=10 & op2127=0x05 & op13=0 & op0207=0 & StMemRsRelPdC9w & rt5 & pu0001 & $(END_PACKET) { + # NOTE: cannot be group with other instructions + rc:1 = lock(); + lockOK:1 = rc != 0; + tmp:4 = rt5; + build EndPacket; + <> + pu0001 = lockOK * 0xff; + <> + if (!lockOK) goto ; + StMemRsRelPdC9w = tmp; + unlock(); + +} + +# (v4,9) memw_phys -- "Rd32 = memw_phys ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 1 t t t t t + + + d d d d d + +define pcodeop memw_phys; + +:memw_phys Rd5,rs5,rt5 EndPacket is iclass=9 & op2127=0x10 & op13=1 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = memw_phys(rs5,rt5); + build EndPacket; +} + +# (v2,13) min -- "Rd32 = min ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 0 1 s s s s s P P + t t t t t 0 + + d d d d d + +define pcodeop min; + +:min Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2d & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = min(rt5,rs5); + build EndPacket; +} + +# (v4,13) min -- "Rdd32 = min ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:min Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = min(rtt5,rss5); + build EndPacket; +} + +# (v2,13) minu -- "Rd32 = minu ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 0 1 s s s s s P P + t t t t t 1 + + d d d d d + +define pcodeop minu; + +:minu Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2d & op13=0 & op0507=4 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = minu(rt5,rs5); + build EndPacket; +} + +# (v4,13) minu -- "Rdd32 = minu ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:minu Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=7 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = minu(rtt5,rss5); + build EndPacket; +} + +# (v4,13) modwrap -- "Rd32 = modwrap ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d +define pcodeop modwrap; +:modwrap Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x1f & op13=0 & op0507=7 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = modwrap(rs5,rt5); + build EndPacket; +} + +# movlen -- "Rd32 = movlen ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 1 1 1 1 1 t t t t t P P 0 s s s s s 0 1 0 d d d d d +# (Rs and Rt are swapped in this instruction) +define pcodeop movlen; + +:movlen Rd5,rt5,rs5 EndPacket is iclass=6 & op2127=0x7f & op13=0 & op0507=2 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = movlen(rt5,rs5); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpy Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x68 & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + tmp:8 = sext(rs5) * sext(rt5); + Rd5 = tmp(4); # Use upper 32-bits of result + build EndPacket; +} + +# (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:mpy^":<<1" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=2 & rs5 & rt5 & Rd5 & $(END_PACKET) { + tmp:8 = (sext(rs5) * sext(rt5)) << 1; + Rd5 = tmp(4); # Use upper 32-bits of result + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpy^":rnd" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x69 & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET){ + tmp:8 = (sext(rs5) * sext(rt5)) + 0x80000000; + Rd5 = tmp(4); # Use upper 32-bits of result + build EndPacket; +} + +# (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +# mpyX2SatUpper(a,b,shift) sat_32( ((a * b) << 1) >> shift ) +# Multiply (a * b) with additional x2 multiplier and use shifted result before saturation for a 32-bit result +define pcodeop mpyX2SatUpper; + +:mpy^":<<1:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6f & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatUpper(rs5, rt5, 32:1); + build EndPacket; +} + +# (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy^":<<1:sat" Rd5,rs5,rt5H EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=0 & rs5 & rt5H & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatUpper(rs5, rt5H, 16:1); + build EndPacket; +} + +# (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpy^":<<1:sat" Rd5,rs5,rt5L EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=1 & rs5 & rt5L & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatUpper(rs5, rt5L, 16:1); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.h ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpyX2RndSatUpper(a,b,shift) sat_32( ( ((a * b) << 1 + (1<<(shift-1)) ) >> shift ) +# Multiply (a * b) with additional x2 multiplier and use shifted and rounded result before saturation for a 32-bit result +define pcodeop mpyX2RndSatUpper; + +:mpy^":<<1:rnd:sat" Rd5,rs5,rt5H EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=4 & rs5 & rt5H & Rd5 & $(END_PACKET) { + Rd5 = mpyX2RndSatUpper(rs5, rt5H, 16:1); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.l ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:mpy^":<<1:rnd:sat" Rd5,rs5,rt5L EndPacket is iclass=14 & op2127=0x6f & op13=0 & op0507=4 & rs5 & rt5L & Rd5 & $(END_PACKET) { + Rd5 = mpyX2RndSatUpper(rs5, rt5L, 16:1); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x60 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = sext(Rs5HL06) * sext(Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x64 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = (sext(Rs5HL06) * sext(Rt5HL05)) << 1; + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy^":<<1:rnd" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x65 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + tmp:4 = ((sext(Rs5HL06) * sext(Rt5HL05)) << 1) + 0x8000; + Rd5 = tmp >> 16; # Use upper 16-bits of result + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpyX2RndSat(a,b) sat_32( ( ((a * b) << 1 + (1<<(shift-1)) ) ) +# Multiply (a * b) with additional x2 multiplier and use rounded result before saturation for a 32-bit result +define pcodeop mpyX2RndSat; + +:mpy^":<<1:rnd:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x65 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2RndSat(Rs5HL06, Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpyX2Sat(a,b) sat_32( ((a * b) << 1 ) +# Multiply (a * b) with additional x2 multiplier before saturation for a 32-bit result +define pcodeop mpyX2Sat; + +:mpy^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x64 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2Sat(Rs5HL06, Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy^":rnd" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x61 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + tmp:4 = (sext(Rs5HL06) * sext(Rt5HL05)) + 0x8000; + Rd5 = tmp >> 16; # Use upper 16-bits of result + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpyRndSat(a,b) sat_32( ( ((a * b) + (1<<(shift-1)) ) ) +# Multiply (a * b) and use rounded result before saturation for a 32-bit result +define pcodeop mpyRndSat; + +:mpy^":rnd:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x61 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = mpyRndSat(Rs5HL06, Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpySat(a,b) sat_32( a * b ) +# Multiply (a * b) with saturation for a 32-bit result +define pcodeop mpySat; + +:mpy^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x60 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = mpySat(Rs5HL06, Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + Rdd5 = sext(rs5) * sext(rt5); + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpy Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x20 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + Rdd5 = sext(Rs5HL06) * sext(Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpy^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x24 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + Rdd5 = (sext(Rs5HL06) * sext(Rt5HL05)) << 1; + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpy^":<<1:rnd" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x25 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + tmp:8 = ((sext(Rs5HL06) * sext(Rt5HL05)) << 1) + 0x80000000; + Rdd5 = tmp >> 32; + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpy^":rnd" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x21 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + tmp:8 = (sext(Rs5HL06) * sext(Rt5HL05)) + 0x80000000; + Rdd5 = tmp >> 32; + build EndPacket; +} + +# (v4,14) mpy -- "Rx32 += mpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P + t t t t t + 0 0 x x x x x + +# mpyX2SatAddUpper(a,b,shift,accumulator) sat_32( ((a * b) << 1) >> shift + accumulator ) +# Multiply (a * b) with additional x2 multiplier and shifted result added to accumulator before saturation for a 32-bit result +define pcodeop mpyX2SatAddUpper; + +:mpy+=^":<<1:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x7b & op13=0 & op0507=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatAddUpper(rs5, rt5, 32:1, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +# mpyX2SatAdd(a,b,accumulator) sat_32( ((a * b) << 1) + accumulator ) +# Multiply (a * b) with additional x2 multiplier and add to accumulator before saturation for a 32-bit result +define pcodeop mpyX2SatAdd; + +:mpy+=^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x74 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatAdd(Rs5HL06, Rt5HL05, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x70 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 + (sext(Rs5HL06) * sext(Rt5HL05)); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x74 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + tmp:4 = sext(Rs5HL06) * sext(Rt5HL05); + Rd5 = rd5 + (tmp << 1); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +# mpySatAdd(a,b,accumulator) sat_32( (a * b) + accumulator ) +# Multiply (a * b) with additional x2 multiplier and add to accumulator before saturation for a 32-bit result +define pcodeop mpySatAdd; + +:mpy+=^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x70 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpySatAdd(Rs5HL06, Rt5HL05, rd5); + build EndPacket; +} + +# (v4,14) mpy -- "Rx32 -= mpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P + t t t t t + 0 1 x x x x x + +# mpyX2SatSubUpper(a,b,shift,accumulator) sat_32( accumulator - ((a * b) << 1) >> shift ) +# Multiply (a * b) with additional x2 multiplier and shifted result subtracted from accumulator before saturation for a 32-bit result +define pcodeop mpyX2SatSubUpper; + +:mpy-=^":<<1:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x7b & op13=0 & op0507=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatSubUpper(rs5, rt5, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P - t t t t t 1 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +# mpyX2SatSub(a,b,accumulator) sat_32( accumulator - ((a * b) << 1) ) +# Multiply (a * b) with additional x2 multiplier and subtract from accumulator before saturation for a 32-bit result +define pcodeop mpyX2SatSub; + +:mpy-=^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x75 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatSub(Rs5HL06, Rt5HL05, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x71 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 - (sext(Rs5HL06) * sext(Rt5HL05)); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x75 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + # TODO: is only upper 16-bits of mpy result used? + tmp:4 = sext(Rs5HL06) * sext(Rt5HL05); + Rd5 = rd5 - (tmp << 1); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +# mpySatSub(a,b,accumulator) sat_32( accumulator - (a * b) ) +# Multiply (a * b) and subtract from accumulator before saturation for a 32-bit result +define pcodeop mpySatSub; + +:mpy-=^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x71 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpySatSub(Rs5HL06, Rt5HL05, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(rs5) * sext(rt5); + Rdd5 = rdd5 + tmp; + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x30 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); + Rdd5 = rdd5 + tmp; + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x34 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); + Rdd5 = rdd5 + (tmp << 1); + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x39 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 - (sext(rs5) * sext(rt5)); + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x31 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); + Rdd5 = rdd5 - tmp; + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x35 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); + Rdd5 = rdd5 - (tmp << 1); + build EndPacket; +} + +# (v2,14) mpyi -- "Rd32 = + mpyi ( Rs32 , #u8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 0 0 0 + + s s s s s P P + i i i i i i i i d d d d d + +:"+mpyi" Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 &op2127=0x00 & op13=0 & rs5 & Rd5 & Uimm32_0512x & $(END_PACKET) { + Rd5 = rs5 * Uimm32_0512x; + build EndPacket; +} + +# (v2,14) mpyi -- "Rd32 = - mpyi ( Rs32 , #u8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 0 0 1 + + s s s s s P P + i i i i i i i i d d d d d + +:"-mpyi" Rd5,rs5,Uimm8_0512 EndPacket is iclass=14 &op2127=0x04 & op13=0 & rs5 & Rd5 & Uimm8_0512 & $(END_PACKET) { + Rd5 = rs5 * sext(-Uimm8_0512); + build EndPacket; +} + +# (v2,14) mpyi -- "Rd32 = mpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 0 s s s s s P P - t t t t t 0 0 0 d d d d d + +:mpyi Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x68 & op13=0 & rs5 & rt5 & op0507=0 & Rd5 & $(END_PACKET) { + Rd5 = rs5 * rt5; + build EndPacket; +} + +# (v2,14) mpyi -- "Rx32 += mpyi ( Rs32 , #u8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 0 1 0 + + s s s s s P P + i i i i i i i i x x x x x + +:mpyi+= Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 &op2127=0x08 & op13=0 & rs5 & Rd5 & rd5 & Uimm32_0512x & $(END_PACKET) { + Rd5 = rd5 + (rs5 * Uimm32_0512x); + build EndPacket; +} + +# (v2,14) mpyi -- "Rx32 += mpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 0 x x x x x + +:mpyi+= Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x78 & op13=0 & op0507=0 & rs5 & Rd5 & rd5 & rt5 & $(END_PACKET) { + Rd5 = rd5 + (rs5 * rt5); + build EndPacket; +} + +# (v2,14) mpyi -- "Rx32 -= mpyi ( Rs32 , #u8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 0 1 1 + + s s s s s P P + i i i i i i i i x x x x x + +:mpyi-= Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 &op2127=0x0c & op13=0 & rs5 & Rd5 & rd5 & Uimm32_0512x & $(END_PACKET) { + Rd5 = rd5 - (rs5 * Uimm32_0512x); + build EndPacket; +} + +# (v2,14) mpyi -- "Rx32 -= mpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 0 x x x x x + +:mpyi-= Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x7c & op13=0 & op0507=0 & rs5 & Rd5 & rd5 & rt5 & $(END_PACKET) { + Rd5 = rd5 - (rs5 * rt5); + build EndPacket; +} + +# (v4,14) mpysu -- "Rd32 = mpysu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpysu Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6b & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + tmp:8 = sext(rs5) * zext(rt5); + Rd5 = tmp(4); # use upper 32-bits of result + build EndPacket; +} + +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpyu Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6a & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + tmp:8 = zext(rs5) * zext(rt5); + Rd5 = tmp(4); # use upper 32-bits of result + build EndPacket; +} + +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpyu Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x62 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = zext(Rs5HL06) * zext(Rt5HL05); + build EndPacket; +} + +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpyu^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x66 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = zext(Rs5HL06) * zext(Rs5HL06); + Rd5 = Rd5 << 1; + build EndPacket; +} + +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpyu Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2a & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + Rdd5 = zext(rs5) * zext(rt5); + build EndPacket; +} + +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpyu Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x22 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + Rdd5 = zext(Rs5HL06) * zext(Rt5HL05); + build EndPacket; +} + +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpyu^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x26 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + Rdd5 = zext(Rs5HL06) * zext(Rt5HL05); + Rdd5 = Rdd5 << 1; + build EndPacket; +} + +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x72 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 + (zext(Rs5HL06) * zext(Rt5HL05)); + build EndPacket; +} + +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x76 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + tmp:4 = zext(Rs5HL06) * zext(Rt5HL05); + Rd5 = rd5 + (tmp << 1); + build EndPacket; +} + +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x73 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 - (zext(Rs5HL06) * zext(Rt5HL05)); + build EndPacket; +} + +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x77 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + tmp:4 = zext(Rs5HL06) * zext(Rt5HL05); + Rd5 = rd5 - (tmp << 1); + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3a & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(rs5) * zext(rt5); + Rdd5 = rdd5 + tmp; + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x32 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); + Rdd5 = rdd5 + tmp; + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x36 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(Rs5HL06) * zext(Rs5HL06); + Rdd5 = rdd5 + (tmp << 1); + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3b & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(rs5) * zext(rt5); + Rdd5 = rdd5 - tmp; + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x33 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); + Rdd5 = rdd5 - tmp; + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x37 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); + Rdd5 = rdd5 - (tmp << 1); + build EndPacket; +} + +# (v2,7) mux -- "Rd32 = mux ( Pu4 , #s8x , #S8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 0 1 u u I I I I I I I P P I i i i i i i i i d d d d d + +:mux Rd5,pu2324,Simm32_0512x,Simm8_1622_13 EndPacket is iclass=7 & op2527=5 & Rd5 & pu2324 & Simm32_0512x & Simm8_1622_13 & $(END_PACKET) { + if ((pu2324 & 1) != 0) goto ; + Rd5 = sext(Simm8_1622_13); + goto ; + + Rd5 = Simm32_0512x; + + build EndPacket; +} + +# (v2,7) mux -- "Rd32 = mux ( Pu4 , #s8x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 1 u u s s s s s P P 0 i i i i i i i i d d d d d + +:mux Rd5,pu2122,Simm32_0512x,rs5 EndPacket is iclass=7 & op2327=7 & op13=0 & Rd5 & pu2122 & Simm32_0512x & rs5 & $(END_PACKET) { + if ((pu2122 & 1) != 0) goto ; + Rd5 = rs5; + goto ; + + Rd5 = Simm32_0512x; + + build EndPacket; +} + +# (v2,7) mux -- "Rd32 = mux ( Pu4 , Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 0 u u s s s s s P P 0 i i i i i i i i d d d d d + +:mux Rd5,pu2122,rs5,Simm32_0512x EndPacket is iclass=7 & op2327=6 & op13=0 & Rd5 & pu2122 & Simm32_0512x & rs5 & $(END_PACKET) { + if ((pu2122 & 1) != 0) goto ; + Rd5 = Simm32_0512x; + goto ; + + Rd5 = rs5; + + build EndPacket; +} + +# (v2,15) mux -- "Rd32 = mux ( Pu4 , Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 0 0 + + + s s s s s P P + t t t t t + u u d d d d d + +# Sleigh can't distinguish the two simplification cases when -l option is used with compiler +#:mux Rd5,pu0506,rs5,rt5 EndPacket is iclass=15 & op2127=0x20 & op13=0 & op7=0 & Rd5 & rd5=op1620 & rs5 & rt5 & pu0506 & $(END_PACKET) { +# if ((pu0506 & 1) == 0) goto ; +# Rd5 = rs5; +# goto ; +# +# build EndPacket; +#} +#:mux Rd5,pu0506,rs5,rt5 EndPacket is iclass=15 & op2127=0x20 & op13=0 & op7=0 & Rd5 & rd5=op0812 & rs5 & rt5 & pu0506 & $(END_PACKET) { +# if ((pu0506 & 1) != 0) goto ; +# Rd5 = rt5; +# goto ; +# +# build EndPacket; +#} + +:mux Rd5,pu0506,rs5,rt5 EndPacket is iclass=15 & op2127=0x20 & op13=0 & op7=0 & Rd5 & rs5 & rt5 & pu0506 & $(END_PACKET) { + if ((pu0506 & 1) != 0) goto ; + Rd5 = rt5; + goto ; + + Rd5 = rs5; + + build EndPacket; +} + +# (v2,8) neg -- "Rd32 = neg ( Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 1 0 d d d d d + +:neg":sat" Rd5,rs5 EndPacket is iclass=0x8 & op2127=0x64 & op0513=0x06 & Rd5 & rs5 & $(END_PACKET) +{ + tmp:8 = -sext(rs5); + Rd5 = saturate32(tmp); + sat:1 = sborrow(0:4, rs5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) neg -- "Rdd32 = neg ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 0 1 d d d d d + +:neg Rdd5,rss5 EndPacket is iclass=0x8 & op2127=0x04 & op0513=0x05 & Rdd5 & rss5 & $(END_PACKET) +{ + Rdd5 = -rss5; + build EndPacket; +} + +# (v4,6) nmi -- "nmi ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 1 s s s s s P P + + + + + + 0 1 0 + + + + + + +define pcodeop nmi; # TODO: Need to determine what is affected + +:nmi rs5 EndPacket is iclass=0x6 & op2127=0x23 & op0013=0x40 & rs5 & $(END_PACKET) +{ + nmi(rs5); + build EndPacket; +} + +# (v2,7) nop -- "nop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 1 - - - - - - - - P P - - - - - - - - - - - - - - + +:nop EndPacket is iclass=0x7 & op2427=0xf & $(END_PACKET) { + build EndPacket; +} + +# (v2,8) normamt -- "Rd32 = normamt ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 1 1 d d d d d + +:normamt Rd5,rs5 EndPacket is iclass=0x8 & op2127=0x60 & op0513=0x07 & Rd5 & rs5 & $(END_PACKET) +{ + if (rs5 != 0) goto ; + Rd5 = 0; + goto ; + + Rd5 = countLeadingBits(rs5); + + build EndPacket; +} + +# (v4,8) normamt -- "Rd32 = normamt ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P + + + + + + 0 0 + d d d d d + +:normamt Rd5,rss5 EndPacket is iclass=0x8 & op2127=0x43 & op0513=0x0 & Rd5 & rss5 & $(END_PACKET) +{ + if (rss5 != 0) goto ; + Rd5 = 0; + goto ; + + Rd5 = countLeadingBits(rss5); + + build EndPacket; +} + +# (v2,6) not -- "Pd4 = not ( Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 1 0 0 - - s s P P 0 - - - - - - - - - - - d d + +:not Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5e & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ~pu1617; # NOTE: Implemented as full byte logic instead of single-bit boolean logic + build EndPacket; +} + +# (v2,8) not -- "Rdd32 = not ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P - - - - - - 1 0 0 d d d d d + +:not Rdd5,rss5 EndPacket is iclass=8 & op2127=0x04 & op0507=4 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = ~rss5; + build EndPacket; +} + +# (v4,6) or -- "Pd4 = or ( Ps4 , and ( Pt4 , Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 1 0 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) or -- "Pd4 = or ( Ps4 , and ( Pt4 , ! Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 1 0 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) or -- "Pd4 = or ( Ps4 , or ( Pt4 , Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 1 1 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) or -- "Pd4 = or ( Ps4 , or ( Pt4 , ! Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 1 1 1 + + s s P P 0 - - - t t u u - - - - d d + +:or Pd2,pu1617,PredLogic_L21_S23_P0809_P0607 EndPacket is iclass=6 & op2427=0xb & op22=1 & op1820=4 & pu1617 & Pd2 & PredLogic_L21_S23_P0809_P0607 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 | PredLogic_L21_S23_P0809_P0607); + build EndPacket; +} + +# (v2,6) or -- "Pd4 = or ( Pt4 , Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 1 0 - - s s P P 0 - - - t t - - - - - - d d + +:or Pd2,pu0809,pu1617 EndPacket is iclass=6 & op2127=0x59 & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 | pu0809); + build EndPacket; +} + +# Pd=Pd ( simplification of Pd=or(Ps,Pt) ) +:assign Pd2,pu1617 EndPacket is iclass=6 & op2127=0x59 & op1820=0 & op1013=0 & op0207=0 & pu0809=op1617 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & pu1617; + build EndPacket; +} + +# (v2,6) or -- "Pd4 = or ( Pt4 , ! Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 1 1 0 - - s s P P 0 - - - t t - - - - - - d d + +:or Pd2,pu0809,NotPs2 EndPacket is iclass=6 & op2127=0x5f & op1820=0 & op1013=0 & op0207=0 & pu0809 & NotPs2 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (NotPs2 | pu0809); + build EndPacket; +} + +# (v2,7) or -- "Rd32 = or ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 1 0 1 0 i s s s s s P P i i i i i i i i i d d d d d + +:or Rd5,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x1a & Rd5 & rs5 & Simm32_21_0513x & $(END_PACKET) { + Rd5 = rs5 | Simm32_21_0513x; + build EndPacket; +} + +# (v2,15) or -- "Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 0 0 1 s s s s s P P - t t t t t - - - d d d d d + +:or Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x09 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = rs5 | rt5; + build EndPacket; +} + +# (v4,15) or -- "Rd32 = or ( Rt32 , ~ Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 1 0 1 s s s s s P P - t t t t t - - - d d d d d + +:or Rd5,rt5,OnesCompRs5 EndPacket is iclass=15 & op2127=0x0d & Rd5 & OnesCompRs5 & rt5 & $(END_PACKET) { + Rd5 = rt5 | OnesCompRs5; + build EndPacket; +} + +# (v2,13) or -- "Rdd32 = or ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 1 0 d d d d d + +:or Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1f & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = rss5 | rtt5; + build EndPacket; +} + +# (v4,13) or -- "Rdd32 = or ( Rtt32 , ~ Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 1 1 d d d d d + +:or Rdd5,rtt5,OnesCompRss5 EndPacket is iclass=13 & op2127=0x1f & op0507=3 & Rdd5 & OnesCompRss5 & rtt5 & $(END_PACKET) { + Rdd5 = rtt5 | OnesCompRss5; + build EndPacket; +} + +# (v4,14) or -- "Rx32 &= or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 0 1 x x x x x + +:or&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 & (rs5 | rt5); + build EndPacket; +} + +# (v4,13) or -- "Rx32 = or ( #u8x , asl ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 0 1 + +# +# (v4,13) or -- "Rx32 = or ( #u8x , lsr ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 0 1 + + +:or Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=2 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +{ + Rx5 = Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812; + build EndPacket; +} + +# (v4,13) or -- "Rx32 = or ( Ru32 , and ( Rx32 , #s10x ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 0 0 1 i x x x x x P P i i i i i i i i i u u u u u + +AndRx_21_0513: "and("^rx5,Simm32_21_0513x^")" is rx5 & Simm32_21_0513x { + tmp:4 = rx5 & Simm32_21_0513x; + export tmp; +} + +:or Rx5,ru5,AndRx_21_0513 EndPacket is iclass=13 & op2227=0x29 & AndRx_21_0513 & Rx5 & ru5 & $(END_PACKET) +{ + Rx5 = ru5 | AndRx_21_0513; + build EndPacket; +} + +# (v4,14) or -- "Rx32 ^= or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 1 1 x x x x x + +:or"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 ^ (rs5 | rt5); + build EndPacket; +} + +# (v4,13) or -- "Rx32 |= or ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 0 1 0 i s s s s s P P i i i i i i i i i x x x x x + +:or|= Rd5,rs5,Simm32_21_0513x EndPacket is iclass=13 & op2227=0x2a & Rd5 & rd5 & Simm32_21_0513x & rs5 & $(END_PACKET) { + Rd5 = rd5 | (rs5 | Simm32_21_0513x); + build EndPacket; +} + +# (v4,14) or -- "Rx32 |= or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 0 0 x x x x x + +:or|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 | rs5 | rt5; + build EndPacket; +} + +# (v2,15) or -- "if ( Pu4 ) Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) or -- "if ( ! Pu4 ) Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) or -- "if ( Pu4 .new ) Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) or -- "if ( ! Pu4 .new ) Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 1 t t t t t 1 u u d d d d d + +:or^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=0 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 | rt5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v4,15) packhl -- "Rdd32 = packhl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 0 1 1 + + s s s s s P P + t t t t t + + + d d d d d + +:packhl Rdd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x2c & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = (zext(rs5 & 0xff00) << 32) + (zext(rt5 & 0xff00) << 16) + (zext(rs5 & 0xff) << 8) + zext(rt5 & 0xff); + build EndPacket; +} + +# (v2,13) packhl -- "Rdd32 = packhl ( Rs32 , Rt32 ) :deprecated" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 0 + + 0 s s s s s P P + t t t t t + + + d d d d d + +:packhl^":deprecated" Rdd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x20 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = (zext(rs5 & 0xff00) << 32) + (zext(rt5 & 0xff00) << 16) + (zext(rs5 & 0xff) << 8) + zext(rt5 & 0xff); + build EndPacket; +} + +# (v4,13) parity -- "Rd32 = parity ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 1 1 s s s s s P P + t t t t t + + + d d d d d + +define pcodeop parity; + +:parity Rd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x2f & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + Rd5 = parity(rs5,rt5); + build EndPacket; +} + +# (v2,13) parity -- "Rd32 = parity ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 0 0 + + + s s s s s P P + t t t t t + + + d d d d d + +:parity Rd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x0 & op13=0 & op0507=0 & rss5 & rtt5 & Rd5 & $(END_PACKET) +{ + Rd5 = parity(rss5,rtt5); + build EndPacket; +} + +# (v4,5) pause -- "pause ( #u10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 0 0 1 - - - - i i P P - i i i i i - - - i i i - - + +define pcodeop pause; + +:pause Uimm10_1617_0812_0204 EndPacket is iclass=0x5 & op2127=0x22 & op1820=0 & op13=0 & op0507=0 & op0001=0 & Uimm10_1617_0812_0204 & $(END_PACKET) +{ + pause(Uimm10_1617_0812_0204); + build EndPacket; +} + +# unpause -- "unpause" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 1 1 1 1 - - - - - P P 0 1 - - - - 0 0 0 - - - - - + +define pcodeop unpause; + +:unpause EndPacket is iclass=0x5 & op2127=0x3f & op1620=0 & op0213=0x400 & op0001=0 & $(END_PACKET) +{ + unpause(); + build EndPacket; +} + +# pmemcpy -- "Rdd32 = pmemcpy ( Rx32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 1 1 t t t t t P P 0 x x x x x 0 0 0 d d d d d + +define pcodeop pmemcpy; + +:pmemcpy Rdd5,rt5,rss5 EndPacket is iclass=0x9 & op2127=0x4f & op13=0 & op0507=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = pmemcpy(rt5,rss5); + build EndPacket; +} + +# (v4,14) pmpyw -- "Rdd32 = pmpyw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop pmpyw; + +:pmpyw Rdd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x2a & op13=0 & op0507=7 & rs5 & rt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = pmpyw(rs5,rt5); + build EndPacket; +} + +# (v4,14) pmpyw -- "Rxx32 ^= pmpyw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +:pmpyw"^=" Rdd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x39 & op13=0 & op0507=7 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rdd5 ^ pmpyw(rs5,rt5); + build EndPacket; +} + +# (v2,6) resume -- "resume ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P + + + + + + 0 0 1 + + + + + + +# (v5,8) popcount -- "Rd32 = popcount ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P + + + + + + 0 1 1 d d d d d + +:popcount Rd5,rss5 EndPacket is iclass=8 & op2127=0x43 & op0513=0x03 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = popcount(rss5); + build EndPacket; +} + +# (v68,10) release -- "release ( Rs32 ) :at" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 0 0 1 1 d d + +define pcodeop releaseAllThreads; +:release^":at" rs5 EndPacket is iclass=10 & op2127=0x07 & op13=0 & op0205=3 & rs5 & $(END_PACKET) { + releaseAllThreads(rs5); # release_at(rs5); # encoded rt5 and rd2 not used ?? +} + +# (v68,10) release -- "release ( Rs32 ) :st" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 1 0 1 1 d d + +define pcodeop releaseSameDomain; +:release^":st" rs5 EndPacket is iclass=10 & op2127=0x07 & op13=0 & op0205=0xb & rs5 & $(END_PACKET) { + releaseSameDomain(rs5); # release_st(rs5); # encoded rt5 and rd2 not used ?? +} + +# (v4,6) resume -- "resume ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P + + + + + + 0 0 1 + + + + + + +define pcodeop resume; +:resume rs5 EndPacket is iclass=0x6 & op2127=0x22 & op0507=1 & rs5 & $(END_PACKET) +{ + resume(rs5); + build EndPacket; +} + +# (v4,8) round -- "Rd32 = round ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 0 + d d d d d + +:round Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0507=4 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = roundArithmetic(rs5, Uimm8_0812); + build EndPacket; +} + +# (v4,8) round -- "Rd32 = round ( Rs32 , #u5 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 1 + d d d d d + +:round":sat" Rd5,rs5,Uimm8_0812 EndPacket is iclass=0x8 & op2127=0x67 & op13=0 & op0507=6 & Uimm8_0812 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = roundArithmeticSaturate(rs5, Uimm8_0812); + build EndPacket; +} + +# (v4,12) round -- "Rd32 = round ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +:round Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = roundArithmetic(rs5, rt5); + build EndPacket; +} + +# (v4,12) round -- "Rd32 = round ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +:round":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=6 & rt5 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = roundArithmeticSaturate(rs5, rt5); + build EndPacket; +} + +# (v5,8) round -- "Rd32 = round ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +define pcodeop roundArithmeticPSat; +:round":sat" Rd5,rss5 EndPacket is iclass=8 & op2127=0x46 & op0513=1 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = roundArithmeticPSat(rss5); + build EndPacket; +} + +# (v2,5) rte -- "rte" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 1 1 1 1 + + + + + P P 0 0 + + + + 0 0 0 + + + + + + +:rte EndPacket is iclass=5 & op2127=0x3f & op1620=0 & op0013=0 & $(END_PACKET) { + # Treat as return + dest:4 = $(ELR); + build EndPacket; + <> + return [dest]; +} + + +# (v2,8) sat -- "Rd32 = sat ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P + + + + + + 0 0 + d d d d d + +:sat Rd5,rss5 EndPacket is iclass=8 & op2127=0x46 & op0513=0 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = saturate32(rss5); + sat:1 = (rss5 s< 0xffffffff80000000) || (rss5 s> 0x7fffffff); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) satb -- "Rd32 = satb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 1 1 d d d d d + +:satb Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=7 & Rd5 & rs5 & $(END_PACKET) { + byte:1 = saturate8(rs5); + Rd5 = sext(byte); + sat:1 = (rs5 s< 0xffffff80) || (rs5 s> 0x7f); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) sath -- "Rd32 = sath ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:sath Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=4 & Rd5 & rs5 & $(END_PACKET) { + half:2 = saturate16(rs5); + Rd5 = sext(half); + sat:1 = (rs5 s< 0xffff8000) || (rs5 s> 0x7fff); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) satub -- "Rd32 = satub ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 1 0 d d d d d + +:satub Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=6 & Rd5 & rs5 & $(END_PACKET) { + byte:1 = usaturate8(rs5); + Rd5 = zext(byte); + sat:1 = (rs5 > 0x7f); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) satuh -- "Rd32 = satuh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 0 1 d d d d d + +:satuh Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=5 & Rd5 & rs5 & $(END_PACKET) { + half:2 = usaturate16(rs5); + Rd5 = zext(half); + sat:1 = (rs5 > 0x7fff); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) setbit -- "Rd32 = setbit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d + +:setbit Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x66 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + Rd5 = rs5 | mask; + build EndPacket; +} + +# (v2,12) setbit -- "Rd32 = setbit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:setbit Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + mask:4 = 1 << rt5; + Rd5 = rs5 | mask; + build EndPacket; +} + +# (v4,6) setimask -- "setimask ( Pt4 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P + + + + t t 0 0 0 + + + + + + +define pcodeop setimask; # TODO: Determine what is affected by this instruction + +:setimask pu0809,rs5 EndPacket is iclass=6 & op2127=0x24 & op1013=0 & op0007=0 & pu0809 & rs5 & $(END_PACKET) { + setimask(pu0809,rs5); + build EndPacket; +} + +# (v66,6) or -- "setprio ( Pt4 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P - - - - t t 0 0 1 - - - - - + +define pcodeop setprio; +:setprio pu0809,rs5 EndPacket is iclass=6 & op2127=0x24 & op0507=1 & pu0809 & rs5 & $(END_PACKET) { + setprio(pu0809, rs5); + build EndPacket; +} + +# (v2,12) shuffeb -- "Rdd32 = shuffeb ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +define pcodeop shuffeb; + +:shuffeb Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffeb(rss5,rtt5); + build EndPacket; +} + +# (v2,12) shuffeh -- "Rdd32 = shuffeh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop shuffeh; + +:shuffeh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffeh(rss5,rtt5); + build EndPacket; +} + +# (v2,12) shuffob -- "Rdd32 = shuffob ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +define pcodeop shuffob; + +:shuffob Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffob(rss5,rtt5); + build EndPacket; +} + +# (v2,12) shuffoh -- "Rdd32 = shuffoh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop shuffoh; + +:shuffoh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffoh(rss5,rtt5); + build EndPacket; +} + +# (v4,6) siad -- "siad ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P + + + + + + 0 1 1 + + + + + + +:siad rs5 EndPacket is iclass=6 & op2127=0x24 & op0013=0x60 & rs5 & $(END_PACKET) { + S22 = S22 | rs5; + build EndPacket; +} + +# (v2,6) sp1loop0 -- "p3 = sp1loop0 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 1 0 1 I I I I I P P - i i i i i I I I i i - I I + +:sp1loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4d & op13=0 & op2=0 & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = LoopUimm10; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 1; + P3 = 0; +} + +# (v2,6) sp1loop0 -- "p3 = sp1loop0 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 1 0 1 s s s s s P P - i i i i i - - - i i - - - + +:sp1loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=5 & op13=0 & op0507=0 & op0002=0 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = rs5; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 1; + P3 = 0; +} + +# (v2,6) sp2loop0 -- "p3 = sp2loop0 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 1 1 0 I I I I I P P - i i i i i I I I i i - I I + +:sp2loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4e & op13=0 & op2=0 & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = LoopUimm10; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 2; + P3 = 0; +} + +# (v2,6) sp2loop0 -- "p3 = sp2loop0 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 1 1 0 s s s s s P P - i i i i i - - - i i - - - + +:sp2loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=6 & op13=0 & op0507=0 & op0002=0 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = rs5; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 2; + P3 = 0; +} + +# (v2,6) sp3loop0 -- "p3 = sp3loop0 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 1 1 1 I I I I I P P - i i i i i I I I i i - I I + +:sp3loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4f & op13=0 & op2=0 & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = LoopUimm10; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 3; + P3 = 0; +} + +# (v2,6) sp3loop0 -- "p3 = sp3loop0 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 1 1 1 s s s s s P P - i i i i i - - - i i - - - + +:sp3loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=7 & op13=0 & op0507=0 & op0002=0 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = rs5; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 3; + P3 = 0; +} + +# (v2,6) start -- "start ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - 0 0 1 - - - - - + +define pcodeop start; + +:start rs5 EndPacket is iclass=6 & op2127=0x23 & op0507=1 & rs5 & packetOffset=0 & $(END_PACKET) { # solo instruction + start(rs5); # resets threads specified by rs5 + build EndPacket; +} + +# (v2,6) stop -- "stop ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - 0 0 0 - - - - - + +define pcodeop stop; + +:stop rs5 EndPacket is iclass=6 & op2127=0x23 & op0507=0 & rs5 & packetOffset=0 & $(END_PACKET) { # solo instruction + build EndPacket; + <> + stop(rs5); # cause calling thread to enter stop mode + goto inst_start; # we loop on instruction to simulate but this may not emulate well +} + +# (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.h ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.l ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:sub^":sat:<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2b & op13=0 & op7=1 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +unimpl + +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 0 1 + d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 0 0 + d d d d d + +:sub Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x29 & op13=0 & op7=0 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) +{ + Rd5 = sext(rt5L - Rs5HL06); + build EndPacket; +} + +# (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.h ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.l ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:sub^":<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2b & op13=0 & op7=0 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +{ + Rd5 = zext(Rt5HL06 - Rs5HL05) << 16; + build EndPacket; +} + +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 1 1 + d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 1 0 + d d d d d + +:sub^":sat" Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x29 & rs5 & op13=0 & op7=1 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) +{ + subSat16(Rd5, rt5L, Rs5HL06); + sat:1 = sborrow(rt5L, Rs5HL06); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,7) sub -- "Rd32 = sub ( #s10x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 1 0 0 1 i s s s s s P P i i i i i i i i i d d d d d + +:sub Rd5,Simm32_21_0513x,rs5 EndPacket is iclass=0x7 & op2227=0x19 & rs5 & Rd5 & Simm32_21_0513x & $(END_PACKET) +{ + Rd5 = Simm32_21_0513x - rs5; + build EndPacket; +} + +# Special case for sub(#-1,Rs) +:not Rd5,rs5 EndPacket is iclass=0x7 & op2227=0x19 & s21=1 & i0513=0x1ff & immexted=0 & rs5 & Rd5 & $(END_PACKET) +{ + Rd5 = ~rs5; + build EndPacket; +} + +# (v2,15) sub -- "Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t + + + d d d d d + +:sub Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x19 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + Rd5 = rt5 - rs5; + build EndPacket; +} + +# (v4,15) sub -- "Rd32 = sub ( Rt32 , Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 1 1 0 s s s s s P P + t t t t t + + + d d d d d + +:sub":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x36 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + subSat32(Rd5, rt5, rs5); + sat:1 = sborrow(rt5, rs5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,13) sub -- "Rd32 = sub ( Rt32 , Rs32 ) :sat :deprecated" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 + + d d d d d + +:sub":sat:deprecated" Rd5,rt5,rs5 EndPacket is iclass=13 & op2127=0x2c & op13=0 & op0507=4 & rs5 & rt5 & Rd5 & $(END_PACKET) { + subSat32(Rd5, rt5, rs5); + sat:1 = sborrow(rt5, rs5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v4,12) sub -- "Rdd32 = sub ( Rss32 , Rtt32 , Px4 ) :carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 0 1 1 1 s s s s s P P + t t t t t + x x d d d d d + +:sub":carry" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=12 & op2127=0x17 & op13=0 & op7=0 & Rdd5 & rss5 & rtt5 & pu0506 & pu0506_ & $(END_PACKET) { + prevCarry:8 = zext(pu0506); + pu0506_ = (rss5 < rtt5) | carry(rtt5,prevCarry); # compute new carry + Rdd5 = rss5 - rtt5 - prevCarry; + build EndPacket; + <> + pu0506 = pu0506_; +} + +# (v2,13) sub -- "Rdd32 = sub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:sub Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x19 & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rtt5 - rss5; + build EndPacket; +} + +# (v2,14) sub -- "Rx32 += sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 1 1 x x x x x + +:sub+= Rd5,rt5,rs5 EndPacket is iclass=0xe & op2127=0x78 & rs5 & op13=0 & op0507=0x3 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 + (rt5 - rs5); + build EndPacket; +} + +# (v4,13) sub -- "Rx32 = sub ( #u8x , asl ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 1 1 + +# +# (v4,13) sub -- "Rx32 = sub ( #u8x , lsr ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 1 1 + + +:sub Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=6 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +{ + Rx5 = Uimm32_2123_13_0507_03x - ShiftRx_D04_I0812; + build EndPacket; +} + +# (v2,15) sub -- "if ( Pu4 ) Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) sub -- "if ( ! Pu4 ) Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) sub -- "if ( Pu4 .new ) Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) sub -- "if ( ! Pu4 .new ) Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 1 t t t t t 1 u u d d d d d + +:sub^PuCond0506_N13_S07 rd5,rt5,rs5 EndPacket is iclass=15 & op2327=0x16 & op22=0 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rt5 - rs5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,6) swi -- "swi ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 0 0 + + + + + + +define pcodeop swi; + +:swi rs5 EndPacket is iclass=6 & op2127=0x20 & op0013=0x00 & rs5 & $(END_PACKET) { + swi(rs5); + build EndPacket; +} + +# (v2,8) swiz -- "Rd32 = swiz ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 1 1 d d d d d + +define pcodeop swizzle; + +:swiz Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x07 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = swizzle(rs5); + build EndPacket; +} + +# (v2,7) sxtb -- "Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 0 + + + + + + + + d d d d d + +:sxtb Rd5,rs5 EndPacket is iclass=7 & op2127=0x05 & op0513=0 & rs5 & Rd5 & $(END_PACKET) +{ + Rd5 = sext(rs5:1); + build EndPacket; +} + +# (v4,7) sxtb -- "if ( Pu4 ) Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 0 0 u u + + + d d d d d +# +# (v4,7) sxtb -- "if ( ! Pu4 ) Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 1 0 u u + + + d d d d d +# +# (v4,7) sxtb -- "if ( Pu4 .new ) Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 0 1 u u + + + d d d d d +# +# (v4,7) sxtb -- "if ( ! Pu4 .new ) Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 1 1 u u + + + d d d d d + +:sxtb^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x05 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +{ + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = sext(rs5:1); + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,7) sxth -- "Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + + + + d d d d d + +:sxth Rd5,rs5 EndPacket is iclass=7 & op2127=0x07 & op0513=0 & rs5 & Rd5 & $(END_PACKET) +{ + Rd5 = sext(rs5:2); + build EndPacket; +} + +# (v4,7) sxth -- "if ( Pu4 ) Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 0 0 u u + + + d d d d d +# +# (v4,7) sxth -- "if ( ! Pu4 ) Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 1 0 u u + + + d d d d d +# +# (v4,7) sxth -- "if ( Pu4 .new ) Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 0 1 u u + + + d d d d d +# +# (v4,7) sxth -- "if ( ! Pu4 .new ) Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 1 1 u u + + + d d d d d + +:sxth^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x07 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +{ + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = sext(rs5:2); + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,8) sxtw -- "Rdd32 = sxtw ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 1 + s s s s s P P + + + + + + 0 0 + d d d d d + +:sxtw Rdd5,rs5 EndPacket is iclass=8 & op2127=0x22 & op0513=0 & rs5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = sext(rs5); + build EndPacket; +} + +# (v2,10) syncht -- "syncht" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 1 0 - - - - - P P - - - - - - - - - - - - - - + +define pcodeop syncht; + +:syncht EndPacket is iclass=10 & op2127=0x42 & $(END_PACKET) { + syncht(); + build EndPacket; +} + +# (v2,8) tableidxb -- "Rx32 = tableidxb ( Rs32 , #u4 , #S6 ) :raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 1 0 0 i s s s s s P P I I I I I I i i i x x x x x + +:tableidxb^":raw" Rd5,rs5,Uimm8_21_0507,Simm8_0813 EndPacket is iclass=8 & op2227=0x1c & rs5 & Uimm8_21_0507 & Simm8_0813 & Rd5 & rd5 & $(END_PACKET) { + local width = Uimm8_21_0507; + local offs = Simm8_0813; + fieldMask:4 = (-1 << width); + tmp:4 = rd5 & fieldMask; # clear dest field + src:4 = (rs5 >> offs) & (~fieldMask); + Rd5 = tmp | src; + build EndPacket; +} + +# (v2,8) tableidxd -- "Rx32 = tableidxd ( Rs32 , #u4 , #S6 ) :raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 1 1 1 i s s s s s P P I I I I I I i i i x x x x x + +:tableidxd^":raw" Rd5,rs5,Uimm8_21_0507,Simm8_0813 EndPacket is iclass=8 & op2227=0x1f & rs5 & Uimm8_21_0507 & Simm8_0813 & Rd5 & rd5 & $(END_PACKET) { + local width = Uimm8_21_0507; + local offs = Simm8_0813 + 3; + fieldMask:4 = (-1 << width); + tmp:4 = rd5 & (fieldMask << 3); # clear dest field + src:4 = ((rs5 & (~fieldMask << offs)) >> offs) << 3; + Rd5 = tmp | src; + build EndPacket; +} + +# (v2,8) tableidxh -- "Rx32 = tableidxh ( Rs32 , #u4 , #S6 ) :raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 1 0 1 i s s s s s P P I I I I I I i i i x x x x x + +:tableidxh^":raw" Rd5,rs5,Uimm8_21_0507,Simm8_0813 EndPacket is iclass=8 & op2227=0x1d & rs5 & Uimm8_21_0507 & Simm8_0813 & Rd5 & rd5 & $(END_PACKET) { + local width = Uimm8_21_0507; + local offs = Simm8_0813 + 1; + fieldMask:4 = (-1 << width); + tmp:4 = rd5 & (fieldMask << 1); # clear dest field + src:4 = ((rs5 & (~fieldMask << offs)) >> offs) << 1; + Rd5 = tmp | src; + build EndPacket; +} + +# (v2,8) tableidxw -- "Rx32 = tableidxw ( Rs32 , #u4 , #S6 ) :raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 1 1 0 i s s s s s P P I I I I I I i i i x x x x x + +:tableidxw^":raw" Rd5,rs5,Uimm8_21_0507,Simm8_0813 EndPacket is iclass=8 & op2227=0x1e & rs5 & Uimm8_21_0507 & Simm8_0813 & Rd5 & rd5 & $(END_PACKET) { + local width = Uimm8_21_0507; + local offs = Simm8_0813 + 2; + fieldMask:4 = (-1 << width); + tmp:4 = rd5 & (fieldMask << 2); # clear dest field + src:4 = ((rs5 & (~fieldMask << offs)) >> offs) << 2; + Rd5 = tmp | src; + build EndPacket; +} + +# (v65,6) tlbinvasid -- "tlbinvasid( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 1 0 1 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop tlbinvasid; + +:tlbinvasid rs5 EndPacket is iclass=6 & op2127=0x65 & rs5 & $(END_PACKET) { + tlbinvasid(rs5); + build EndPacket; +} + +# (v4,6) tlblock -- "tlblock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 + + + + + P P + + + + + + 0 0 1 + + + + + + +define pcodeop tlblock; + +:tlblock EndPacket is iclass=6 & op2127=0x61 & op1620=0 & op0013=0x20 & $(END_PACKET) { + tlblock(); + build EndPacket; +} + +# (v4,13) tlbmatch -- "Pd4 = tlbmatch ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 1 1 + + + d d + +define pcodeop tlbmatch; + +:tlbmatch Pd2,rss5,rt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x18 & Pd2 & rss5 & rt5 & $(END_PACKET) { + Pd2 = tlbmatch(rss5,rt5); + build EndPacket; +} + +# (v65,6) tlboc -- "Rd32 = tlboc( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 1 1 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop tlboc; + +:tlboc Rd5,rss5 EndPacket is iclass=6 & op2127=0x67 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = tlboc(rss5); + build EndPacket; +} + +# (v2,6) tlbp -- "Rd32 = tlbp ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop tlbp; + +:tlbp Rd5,rs5 EndPacket is iclass=6 & op2127=0x64 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = tlbp(rs5); + build EndPacket; +} + +# (v2,6) tlbr -- "Rdd32 = tlbr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop tlbr; + +:tlbr Rdd5,rs5 EndPacket is iclass=6 & op2127=0x62 & op0513=0 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = tlbr(rs5); + build EndPacket; +} + +# (v4,6) tlbunlock -- "tlbunlock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 + + + + + P P + + + + + + 0 1 0 + + + + + + +define pcodeop tlbunlock; + +:tlbunlock EndPacket is iclass=6 & op2127=0x61 & op1620=0 & op0013=0x40 & $(END_PACKET) { + tlbunlock(); + build EndPacket; +} + +# (v2,6) tlbw -- "tlbw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 0 s s s s s P P 0 t t t t t + + + + + + + + + +define pcodeop tlbw; + +:tlbw rss5,rt5 EndPacket is iclass=6 & op2127=0x60 & op13=0 & op0007=0 & rss5 & rt5 & $(END_PACKET) { + tlbw(rss5, rt5); + build EndPacket; +} + +# (v2,8) togglebit -- "Rd32 = togglebit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d + +:togglebit Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x66 & op13=0 & op0507=2 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + Rd5 = rs5 ^ mask; + build EndPacket; +} + +# (v2,12) togglebit -- "Rd32 = togglebit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:togglebit Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + if (rt5 > 31) goto ; + mask:4 = 1 << rt5; + Rd5 = rs5 ^ mask; + + build EndPacket; +} + +# (v4,6) trace -- "trace ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop trace; + +:trace rs5 EndPacket is iclass=6 & op2127=0x12 & op0013=0 & rs5 & $(END_PACKET) { + trace(rs5); + build EndPacket; +} + +# (v2,5) trap0 -- "trap0 ( #u8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 0 0 0 + + + + + + P P - i i i i i - - - i i i - - + +define pcodeop getTrap0Vector; + +:trap0 Uimm8_0812_0204 EndPacket is iclass=5 & op2127=0x20 & op1620=0 & op13=0 & op0507=0 & op0001=0 & Uimm8_0812_0204 & $(END_PACKET) { + dest:4 = getTrap0Vector(); + build EndPacket; + <> + $(CAUSE) = Uimm8_0812_0204; + # $(ELR) = ReturnAddr; + call [dest]; +} + +# (v2,5) trap1 -- "trap1 ( Rx32, #u8 )" +# trap1(#u8) Assembler mapped to: "trap1(R0,#u8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 0 1 0 - x x x x x P P - i i i i i - - - i i i - - + +define pcodeop getTrap1Vector; + +:trap1 rx5, Uimm8_0812_0204 EndPacket is iclass=5 & op2127=0x24 & rx5 & op13=0 & op0507=0 & op0001=0 & Uimm8_0812_0204 & $(END_PACKET) { + # TODO: Instruction manual does not specify the behavior of the Rx register in this instruction + dest:4 = getTrap1Vector(); + build EndPacket; + <> + $(CAUSE) = Uimm8_0812_0204; + # $(ELR) = ReturnAddr; + call [dest]; +} + +:trap1 Uimm8_0812_0204 EndPacket is iclass=5 & op2127=0x24 & op1620=0 & op13=0 & op0507=0 & op0001=0 & Uimm8_0812_0204 & $(END_PACKET) { + dest:4 = getTrap1Vector(); + build EndPacket; + <> + $(CAUSE) = Uimm8_0812_0204; + # $(ELR) = ReturnAddr; + call [dest]; +} + +# (v2,8) tstbit -- "Pd4 = tstbit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 0 0 0 s s s s s P P 0 i i i i i - - - - - - d d + +:tstbit Pd2,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x28 & rs5 & Uimm8_0812 & Pd2 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + bool:1 = (rs5 & mask) != 0; + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,8) tstbit -- "Pd4 = ! tstbit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 0 0 1 s s s s s P P 0 i i i i i - - - - - - d d + +:"!tstbit" Pd2,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x29 & rs5 & Uimm8_0812 & Pd2 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + bool:1 = (rs5 & mask) == 0; + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,12) tstbit -- "Pd4 = tstbit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t + + + + + + d d + +:tstbit Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x38 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + mask:4 = 1 << rt5; + bool:1 = (rs5 & mask) != 0; + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) tstbit -- "Pd4 = ! tstbit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t + + + + + + d d + +:"!tstbit" Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x39 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + mask:4 = 1 << rt5; + bool:1 = (rs5 & mask) == 0; + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v65,14) vabsdiffb -- "Rdd32 = vabsdiffb ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +define pcodeop vabsdiffb; + +:vabsdiffb Rdd5,rtt5,rss5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsdiffb(rtt5,rss5); + build EndPacket; +} + +# (v65,14) vabsdiffub -- "Rdd32 = vabsdiffub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +define pcodeop vabsdiffub; + +:vabsdiffub Rdd5,rtt5,rss5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsdiffub(rtt5,rss5); + build EndPacket; +} + +# (v2,14) vabsdiffh -- "Rdd32 = vabsdiffh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vabsdiffh; + +:vabsdiffh Rdd5,rtt5,rss5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsdiffh(rtt5,rss5); + build EndPacket; +} + +# (v2,14) vabsdiffw -- "Rdd32 = vabsdiffw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vabsdiffw; + +:vabsdiffw Rdd5,rtt5,rss5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsdiffw(rtt5,rss5); + build EndPacket; +} + +# (v2,8) vabsh -- "Rdd32 = vabsh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 0 0 d d d d d + +define pcodeop vabsh; + +:vabsh Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=4 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsh(rss5); + build EndPacket; +} + +# (v2,8) vabsh -- "Rdd32 = vabsh ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 0 1 d d d d d + +define pcodeop vabshSat; + +:vabsh":sat" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabshSat(rss5); + build EndPacket; +} + +# (v2,8) vabsw -- "Rdd32 = vabsw ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 1 0 d d d d d + +define pcodeop vabsw; + +:vabsw Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=6 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsw(rss5); + build EndPacket; +} + +# (v2,8) vabsw -- "Rdd32 = vabsw ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 1 1 d d d d d + +define pcodeop vabswSat; + +:vabsw":sat" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=7 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabswSat(rss5); + build EndPacket; +} + +# (v55,14) vacsh -- "Rxx,Pe = vacsh ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P 0 t t t t t 0 e e x x x x x + +:vacsh Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op7=0 & rss5 & rtt5 & pu0506 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,15) vaddh -- "Rd32 = vaddh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 0 0 0 s s s s s P P + t t t t t + + + d d d d d + +:vaddh Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x30 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5[0,16] = rs5[0,16] + rt5[0,16]; + Rd5[16,16] = rs5[16,16] + rt5[16,16]; + build EndPacket; +} + +# (v2,15) vaddh -- "Rd32 = vaddh ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 0 0 1 s s s s s P P + t t t t t + + + d d d d d + +:vaddh":sat" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x31 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + h:2 = 0; + addSat16(h, rt5[0,16], rs5[0,16]); + Rd5[0,16] = h; + addSat16(h, rt5[16,16], rs5[16,16]); + Rd5[16,16] = h; + build EndPacket; +} + +# (v2,13) vaddh -- "Rdd32 = vaddh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vaddh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5[0,16] = rss5[0,16] + rtt5[0,16]; + Rdd5[16,16] = rss5[16,16] + rtt5[16,16]; + Rdd5[32,16] = rss5[32,16] + rtt5[32,16]; + Rdd5[48,16] = rss5[48,16] + rtt5[48,16]; + build EndPacket; +} + +# (v2,13) vaddh -- "Rdd32 = vaddh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vaddh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + h:2 = 0; + addSat16(h, rtt5[0,16], rss5[0,16]); + Rdd5[0,16] = h; + addSat16(h, rtt5[16,16], rss5[16,16]); + Rdd5[16,16] = h; + addSat16(h, rtt5[32,16], rss5[32,16]); + Rdd5[32,16] = h; + addSat16(h, rtt5[48,16], rss5[48,16]); + Rdd5[48,16] = h; + build EndPacket; +} + +# (v?,12) vaddhub -- "Rd32 = vaddhub ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vaddhub_sat; + +:vaddhub":sat" Rd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=1 & rss5 & rtt5 & Rd5 & $(END_PACKET) { + Rd5 = vaddhub_sat(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vaddub -- "Rdd32 = vaddub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vaddub; + +:vaddub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vaddub(rss5,rtt5); + build EndPacket; +} + +# (v2,13) vaddub -- "Rdd32 = vaddub ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vaddubSat; + +:vaddub":sat" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = vaddubSat(rss5,rtt5); + build EndPacket; +} + +# (v2,15) vadduh -- "Rd32 = vadduh ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 0 1 1 s s s s s P P + t t t t t + + + d d d d d + +:vadduh":sat" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x33 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + h:2 = 0; + adduSat16(h, rt5[0,16], rs5[0,16]); + Rd5[0,16] = h; + adduSat16(h, rt5[16,16], rs5[16,16]); + Rd5[16,16] = h; + build EndPacket; +} + +# (v2,13) vadduh -- "Rdd32 = vadduh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vadduh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + h:2 = 0; + adduSat16(h, rtt5[0,16], rss5[0,16]); + Rdd5[0,16] = h; + adduSat16(h, rtt5[16,16], rss5[16,16]); + Rdd5[16,16] = h; + adduSat16(h, rtt5[32,16], rss5[32,16]); + Rdd5[32,16] = h; + adduSat16(h, rtt5[48,16], rss5[48,16]); + Rdd5[48,16] = h; + build EndPacket; +} + +# (v2,13) vaddw -- "Rdd32 = vaddw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +:vaddw Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x18 & op13=0 & op0507=5 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,32] = rtt5[0,32] + rss5[0,32]; + Rdd5[32,32] = rtt5[32,32] + rss5[32,32]; + build EndPacket; +} + +# (v2,13) vaddw -- "Rdd32 = vaddw ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vaddw":sat" Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x18 & op13=0 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + w:4 = 0; + addSat32(w, rtt5[0,32], rss5[0,32]); + Rdd5[0,32] = w; + addSat32(w, rtt5[32,32], rss5[32,32]); + Rdd5[32,32] = w; + build EndPacket; +} + +# (v2,12) valignb -- "Rdd32 = valignb ( Rtt32 , Rss32 , #u3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 0 0 + + s s s s s P P + t t t t t i i i d d d d d + +macro valignb(d, s, t, align) { + d = (s >> (align * 8)) | (t << ((8-align)*8)); +} + +:valignb Rdd5,rtt5,rss5,Uimm8_0507 EndPacket is iclass=0xc & op2127=0 & rss5 & op13=0 & rtt5 & Rdd5 & Uimm8_0507 & $(END_PACKET) +{ + valignb(Rdd5, rss5, rtt5, Uimm8_0507); + build EndPacket; +} + +# (v2,12) valignb -- "Rdd32 = valignb ( Rtt32 , Rss32 , Pu4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 0 0 + + s s s s s P P + t t t t t + u u d d d d d + +:valignb Rdd5,rtt5,rss5,pu0506 EndPacket is iclass=0xc & op2127=0x10 & rss5 & op13=0 & op7=0 & rtt5 & Rdd5 & pu0506 & $(END_PACKET) +{ + valignb(Rdd5, rss5, rtt5, pu0506 & 0x7); + build EndPacket; +} + +# (v2,8) vaslh -- "Rdd32 = vaslh ( Rss32 , #u4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P 0 0 i i i i 0 1 0 d d d d d + +:vaslh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x04 & op1213=0 & op0507=2 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = rss5[0,16] << Uimm8_0811; + Rdd5[16,16] = rss5[16,16] << Uimm8_0811; + Rdd5[32,16] = rss5[32,16] << Uimm8_0811; + Rdd5[48,16] = rss5[48,16] << Uimm8_0811; + build EndPacket; +} + +# (v2,12) vaslh -- "Rdd32 = vaslh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +:vaslh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=4 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s< 0; + h:2 = rss5[0,16]; + Rdd5[0,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[16,16]; + Rdd5[16,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[32,16]; + Rdd5[32,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[48,16]; + Rdd5[48,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + build EndPacket; +} + +# (v2,8) vaslw -- "Rdd32 = vaslw ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P 0 i i i i i 0 1 0 d d d d d + +:vaslw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x02 & op13=0 & op0507=2 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,32] = rss5[0,32] << Uimm8_0812; + Rdd5[32,32] = rss5[32,32] << Uimm8_0812; + build EndPacket; +} + +# (v2,12) vaslw -- "Rdd32 = vaslw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:vaslw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=4 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s< 0; + w:4 = rss5[0,32]; + Rdd5[0,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + w = rss5[32,32]; + Rdd5[32,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + build EndPacket; +} + +# (v2,8) vasrh -- "Rdd32 = vasrh ( Rss32 , #u4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P 0 0 i i i i 0 0 0 d d d d d + +:vasrh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x04 & op1213=0 & op0507=0 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = rss5[0,16] s>> Uimm8_0811; + Rdd5[16,16] = rss5[16,16] s>> Uimm8_0811; + Rdd5[32,16] = rss5[32,16] s>> Uimm8_0811; + Rdd5[48,16] = rss5[48,16] s>> Uimm8_0811; + build EndPacket; +} + +# (v?,8) vasrh -- "Rdd32 = vasrh ( Rss32 , #u4 ):raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d + +:vasrh":raw" Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x01 & op1213=0 & op0507=0 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = ((rss5[0,16] s>> Uimm8_0811) + 1) >> 1; + Rdd5[16,16] = ((rss5[16,16] s>> Uimm8_0811) + 1) >> 1; + Rdd5[32,16] = ((rss5[32,16] s>> Uimm8_0811) + 1) >> 1; + Rdd5[48,16] = ((rss5[48,16] s>> Uimm8_0811) + 1) >> 1; + build EndPacket; +} + +# (v2,12) vasrh -- "Rdd32 = vasrh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +:vasrh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s>= 0; + h:2 = rss5[0,16]; + Rdd5[0,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[16,16]; + Rdd5[16,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[32,16]; + Rdd5[32,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[48,16]; + Rdd5[48,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + build EndPacket; +} + + +# (v?,8) vasrhub -- "Rd32 = vasrhub ( Rss32 , #u4 ):raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d + +define pcodeop vasrhub_raw; + +:vasrhub":raw" Rd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x43 & op1213=0 & op0507=4 & rss5 & rt5 & Rd5 & Uimm8_0811 & $(END_PACKET) +{ + Rd5 = vasrhub_raw(rss5, Uimm8_0811); + build EndPacket; +} + +# (v?,8) vasrhub -- "Rd32 = vasrhub ( Rss32 , #u4 ):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d + +define pcodeop vasrhub_sat; + +:vasrhub":sat" Rd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x43 & op1213=0 & op0507=5 & rss5 & rt5 & Rd5 & Uimm8_0811 & $(END_PACKET) +{ + Rd5 = vasrhub_sat(rss5, Uimm8_0811); + build EndPacket; +} + +# (v2,8) vasrw -- "Rd32 = vasrw ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 0 1 + d d d d d + +:vasrw Rd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=2 & rss5 & Uimm8_0812 & Rd5 & $(END_PACKET) +{ + res:4 = rss5[0,32] s>> Uimm8_0812; + Rd5[0,16] = res:2; + res = rss5[32,32] s>> Uimm8_0812; + Rd5[16,16] = res:2; + build EndPacket; +} + +# (v2,12) vasrw -- "Rd32 = vasrw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 0 1 0 d d d d d + +:vasrw Rd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=2 & rss5 & rt5 & Rd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s>= 0; + w:4 = rss5[0,32]; + res:4 = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + Rd5[0,16] = res:2; + w = rss5[32,32]; + res = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + Rd5[16,16] = res:2; + build EndPacket; +} + +# (v2,8) vasrw -- "Rdd32 = vasrw ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P 0 i i i i i 0 0 0 d d d d d + +:vasrw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x02 & op13=0 & op0507=0 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,32] = rss5[0,32] s>> Uimm8_0812; + Rdd5[32,32] = rss5[32,32] s>> Uimm8_0812; + build EndPacket; +} + +# (v2,12) vasrw -- "Rdd32 = vasrw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:vasrw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s>= 0; + w:4 = rss5[0,32]; + Rdd5[0,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + w = rss5[32,32]; + Rdd5[32,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + build EndPacket; +} + +# (v2,15) vavgh -- "Rd32 = vavgh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 1 + 0 0 s s s s s P P + t t t t t + + + d d d d d + +:vavgh Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x38 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + Rd5[0,16] = (rs5[0,16] + rt5[0,16]) >> 1; + Rd5[16,16] = (rs5[16,16] + rt5[16,16]) >> 1; + build EndPacket; +} + +# (v2,15) vavgh -- "Rd32 = vavgh ( Rs32 , Rt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 1 + 0 1 s s s s s P P + t t t t t + + + d d d d d + +:vavgh":rnd" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x39 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + Rd5[0,16] = (rs5[0,16] + rt5[0,16] + 1) >> 1; + Rd5[16,16] = (rs5[16,16] + rt5[16,16] + 1) >> 1; + build EndPacket; +} + +# (v2,13) vavgh -- "Rdd32 = vavgh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vavgh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = (rss5[0,16] + rtt5[0,16]) >> 1; + Rdd5[16,16] = (rss5[16,16] + rtt5[16,16]) >> 1; + Rdd5[32,16] = (rss5[32,16] + rtt5[32,16]) >> 1; + Rdd5[48,16] = (rss5[48,16] + rtt5[48,16]) >> 1; + build EndPacket; +} + +# (v2,13) vavgh -- "Rdd32 = vavgh ( Rss32 , Rtt32 ) :crnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vavgh":crnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = roundConvergent(rss5[0,16] + rtt5[0,16] + 1, 1:1) >> 1; + Rdd5[16,16] = roundConvergent(rss5[16,16] + rtt5[16,16] + 1, 1:1) >> 1; + Rdd5[32,16] = roundConvergent(rss5[32,16] + rtt5[32,16] + 1, 1:1) >> 1; + Rdd5[48,16] = roundConvergent(rss5[48,16] + rtt5[48,16] + 1, 1:1) >> 1; + build EndPacket; +} + +# (v2,13) vavgh -- "Rdd32 = vavgh ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vavgh":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = (rss5[0,16] + rtt5[0,16] + 1) >> 1; + Rdd5[16,16] = (rss5[16,16] + rtt5[16,16] + 1) >> 1; + Rdd5[32,16] = (rss5[32,16] + rtt5[32,16] + 1) >> 1; + Rdd5[48,16] = (rss5[48,16] + rtt5[48,16] + 1) >> 1; + build EndPacket; +} + +# (v2,13) vavgub -- "Rdd32 = vavgub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:vavgub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavgub -- "Rdd32 = vavgub ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vavgub":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavguh -- "Rdd32 = vavguh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +:vavguh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=5 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavguh -- "Rdd32 = vavguh ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 1 1 + d d d d d + +:vavguh":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavguw -- "Rdd32 = vavguw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vavguw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavguw -- "Rdd32 = vavguw ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vavguw":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavgw -- "Rdd32 = vavgw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:vavgw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavgw -- "Rdd32 = vavgw ( Rss32 , Rtt32 ) :crnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vavgw":crnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavgw -- "Rdd32 = vavgw ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vavgw":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v65,8) vclip -- "Rdd32 = vclip ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 1 1 0 d d d d d + +define pcodeop vclip; + +:vclip Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=6 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) { + Rdd5 = vclip(rss5,Uimm8_0812); + build EndPacket; +} + +# (v4,13) vcmpb.eq -- "Pd4 = vcmpb.eq ( Rss32 , #u8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 0 s s s s s P P + i i i i i i i i 0 0 + d d + +:vcmpb.eq Pd2,rss5,Uimm8_0512 EndPacket is iclass=13 & op2127=0x60 & op13=0 & op0204=0 & Uimm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.eq(rss5,Uimm8_0512); + build EndPacket; +} + +# (v2,13) vcmpb.eq -- "Pd4 = vcmpb.eq ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 1 0 + + + d d + +:vcmpb.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x30 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.eq(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpb.gt -- "Pd4 = vcmpb.gt ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 1 s s s s s P P + i i i i i i i i 0 0 + d d + +define pcodeop vcmpb.gt; + +:vcmpb.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x61 & op13=0 & op0204=0 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.gt(rss5,Simm8_0512); + build EndPacket; +} + +# (v4,13) vcmpb.gt -- "Pd4 = vcmpb.gt ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 1 0 + + + d d + +:vcmpb.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x10 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.gt(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpb.gtu -- "Pd4 = vcmpb.gtu ( Rss32 , #u7 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 1 0 s s s s s P P + 0 i i i i i i i 0 0 + d d + +define pcodeop vcmpb.gtu; + +:vcmpb.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2127=0x62 & op1213=0 & op0204=0 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.gtu(rss5,Uimm8_0511); + build EndPacket; +} + +# (v2,13) vcmpb.gtu -- "Pd4 = vcmpb.gtu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 1 1 + + + d d + +:vcmpb.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x38 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.gtu(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmph.eq -- "Pd4 = vcmph.eq ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 0 s s s s s P P - i i i i i i i i 0 1 + d d + +define pcodeop vcmph.eq; + +:vcmph.eq Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x60 & op13=0 & op0204=2 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.eq(rss5,Simm8_0512); + build EndPacket; +} + +# (v2,13) vcmph.eq -- "Pd4 = vcmph.eq ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 1 1 + + + d d + +:vcmph.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x18 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.eq(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmph.gt -- "Pd4 = vcmph.gt ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 1 s s s s s P P + i i i i i i i i 0 1 + d d + +define pcodeop vcmph.gt; + +:vcmph.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x61 & op13=0 & op0204=2 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.gt(rss5,Simm8_0512); + build EndPacket; +} + +# (v2,13) vcmph.gt -- "Pd4 = vcmph.gt ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 0 0 + + + d d + +:vcmph.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x20 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.gt(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmph.gtu -- "Pd4 = vcmph.gtu ( Rss32 , #u7 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 1 0 s s s s s P P + 0 i i i i i i i 0 1 + d d + +define pcodeop vcmph.gtu; + +:vcmph.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2127=0x62 & op1213=0 & op0204=2 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.gtu(rss5,Uimm8_0511); + build EndPacket; +} + +# (v2,13) vcmph.gtu -- "Pd4 = vcmph.gtu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 0 1 + + + d d + +:vcmph.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x28 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.gtu(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpw.eq -- "Pd4 = vcmpw.eq ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 0 s s s s s P P + i i i i i i i i 1 0 + d d + +define pcodeop vcmpw.eq; + +:vcmpw.eq Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x60 & op13=0 & op0204=4 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.eq(rss5,Simm8_0512); + build EndPacket; +} + +# (v2,13) vcmpw.eq -- "Pd4 = vcmpw.eq ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 0 0 + + + d d + +:vcmpw.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.eq(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpw.gt -- "Pd4 = vcmpw.gt ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 - 0 1 s s s s s P P + i i i i i i i i 1 0 + d d + +define pcodeop vcmpw.gt; + +:vcmpw.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x61 & op13=0 & op0204=4 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.gt(rss5,Simm8_0512); + build EndPacket; +} + +# (v2,13) vcmpw.gt -- "Pd4 = vcmpw.gt ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 0 1 + + + d d + +:vcmpw.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x08 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.gt(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpw.gtu -- "Pd4 = vcmpw.gtu ( Rss32 , #u7 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 1 0 s s s s s P P + 0 i i i i i i i 1 0 + d d + +define pcodeop vcmpw.gtu; + +:vcmpw.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2127=0x62 & op1213=0 & op0204=4 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.gtu(rss5,Uimm8_0511); + build EndPacket; +} + +# (v2,13) vcmpw.gtu -- "Pd4 = vcmpw.gtu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 1 0 + + + d d + +:vcmpw.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x10 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.gtu(rss5,rtt5); + build EndPacket; +} + +# (v2,14) vcmpyi -- "Rdd32 = vcmpyi ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vcmpyi":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,14) vcmpyi -- "Rdd32 = vcmpyi ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vcmpyi":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,14) vcmpyi -- "Rxx32 += vcmpyi ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +:vcmpyi+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=4 & rtt5 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,14) vcmpyr -- "Rdd32 = vcmpyr ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vcmpyrX2Sat; + +:vcmpyr":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcmpyrX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vcmpyr -- "Rdd32 = vcmpyr ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vcmpyrSat; + +:vcmpyr":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcmpyrSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vcmpyr -- "Rxx32 += vcmpyr ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +define pcodeop vcmpyrSatAdd; + +:vcmpyr+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=4 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcmpyrSat(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v4,12) vcnegh -- "Rdd32 = vcnegh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +:vcnegh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1e & op13=0 & op0507=2 & rt5 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,8) vconj -- "Rdd32 = vconj ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 1 1 d d d d d + +define pcodeop vconjSat; + +:vconj":sat" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x04 & op0513=0x07 & rss5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = vconjSat(rss5); + build EndPacket; +} + +# (v2,12) vcrotate -- "Rdd32 = vcrotate ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop vcrotate; + +:vcrotate Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1e & op13=0 & op0507=0 & rt5 & rss5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = vcrotate(rss5, rt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rd32 = vdmpy ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 + + s s s s s P P + t t t t t + 0 0 d d d d d + +define pcodeop vdmpyX2RndSat; + +:vdmpy":<<1:rnd:sat" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x4c & op13=0 & op0507=0 & rtt5 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = vdmpyX2RndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rd32 = vdmpy ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 + + s s s s s P P + t t t t t + 0 0 d d d d d + +define pcodeop vdmpyRndSat; + +:vdmpy":rnd:sat" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x48 & op13=0 & op0507=0 & rtt5 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = vdmpyRndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rdd32 = vdmpy ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +define pcodeop vdmpyX2Sat; + +:vdmpy":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=4 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpyX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rdd32 = vdmpy ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +define pcodeop vdmpySat; + +:vdmpy":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=4 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpySat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rxx32 += vdmpy ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +define pcodeop vdmpyX2SatAdd; + +:vdmpy+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=4 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpyX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rxx32 += vdmpy ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +define pcodeop vdmpySatAdd; + +:vdmpy+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=4 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpySatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v?,14) vdmpybsu -- "Rxx32 = vdmpybsu ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x + +define pcodeop vdmpybsuSat; + +:vdmpybsu=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=1 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpybsuSat(rss5, rtt5); + build EndPacket; +} + +# (v?,14) vdmpybsu -- "Rxx32 += vdmpybsu ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x + +define pcodeop vdmpybsuSatAdd; + +:vdmpybsu+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=1 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpybsuSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,8) vitpack -- "Rd32 = vitpack ( Ps4 , Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 1 + 0 + + + + s s P P + + + + t t + + + d d d d d + +:vitpack Rd5,pu1617,pu0809 EndPacket is iclass=8 & op2127=0x48 & op1820=0 & op1013=0 & op0507=0 & pu1617 & pu0809 & Rd5 & $(END_PACKET) +{ + Rd5 = zext((pu1617 & 0x55) | (pu0809 & 0xaa)); + build EndPacket; +} + +# (v2,12) vlslh -- "Rdd32 = vlslh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop vlslh; + +:vlslh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=6 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vlslh(rss5, rt5); + build EndPacket; +} + +# (v2,12) vlslw -- "Rdd32 = vlslw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop vlslw; + +:vlslw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=6 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vlslw(rss5, rt5); + build EndPacket; +} + +# (v2,8) vlsrh -- "Rdd32 = vlsrh ( Rss32 , #u4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P 0 0 i i i i 0 0 1 d d d d d + +define pcodeop vlsrh; + +:vlsrh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x04 & op1213=0 & op0507=1 & Rdd5 & Uimm8_0811 & rss5 & $(END_PACKET) { + Rdd5 = vlsrh(rss5, Uimm8_0811); + build EndPacket; +} + +# (v2,12) vlsrh -- "Rdd32 = vlsrh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +:vlsrh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=2 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vlsrh(rss5, rt5); + build EndPacket; +} + +# (v2,8) vlsrw -- "Rdd32 = vlsrw ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P 0 i i i i i 0 0 1 d d d d d + +define pcodeop vlsrw; + +:vlsrw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x02 & op13=0 & op0507=1 & Rdd5 & Uimm8_0812 & rss5 & $(END_PACKET) { + Rdd5 = vlsrw(rss5, Uimm8_0812); + build EndPacket; +} + +# (v2,12) vlsrw -- "Rdd32 = vlsrw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:vlsrw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=2 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vlsrw(rss5, rt5); + build EndPacket; +} + +# (v4,13) vmaxb -- "Rdd32 = vmaxb ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vmaxb; + +:vmaxb Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxb(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxh -- "Rdd32 = vmaxh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vmaxh; + +:vmaxh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxh(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxub -- "Rdd32 = vmaxub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vmaxub; + +:vmaxub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxub(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxuh -- "Rdd32 = vmaxuh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +define pcodeop vmaxuh; + +:vmaxuh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxuh(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxuw -- "Rdd32 = vmaxuw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmaxuw; + +:vmaxuw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxuw(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxw -- "Rdd32 = vmaxw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d + +define pcodeop vmaxw; + +:vmaxw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxw(rss5, rtt5); + build EndPacket; +} + +# (v4,13) vminb -- "Rdd32 = vminb ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vminb; + +:vminb Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminb(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminh -- "Rdd32 = vminh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vminh; + +:vminh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminh(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminub -- "Rdd32 = vminub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vminub; + +:vminub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminub(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminuh -- "Rdd32 = vminuh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +define pcodeop vminuh; + +:vminuh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminuh(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminuw -- "Rdd32 = vminuw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +define pcodeop vminuw; + +:vminuw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminuw(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminw -- "Rdd32 = vminw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d + +define pcodeop vminw; + +:vminw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminw(rss5, rtt5); + build EndPacket; +} + +# (v4,14) vmpybsu -- "Rdd32 = vmpybsu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vmpybsu; + +:vmpybsu Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2a & op13=0 & op0507=1 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpybsu(rs5, rt5); + build EndPacket; +} + +# (v4,14) vmpybsu -- "Rxx32 += vmpybsu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vmpybsu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) +unimpl + +# (v4,14) vmpybu -- "Rdd32 = vmpybu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vmpybu; + +:vmpybu Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2c & op13=0 & op0507=1 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpybu(rs5, rt5); + build EndPacket; +} + +# (v4,14) vmpybu -- "Rxx32 += vmpybu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vmpybu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) +unimpl + +# (v2,14) vmpyeh -- "Rdd32 = vmpyeh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vmpyehX2Sat; + +:vmpyeh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyeh -- "Rdd32 = vmpyeh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vmpyehSat; + +:vmpyeh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyeh -- "Rxx32 += vmpyeh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x + +define pcodeop vmpyehAdd; + +:vmpyeh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=2 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyeh -- "Rxx32 += vmpyeh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +define pcodeop vmpyehX2SatAdd; + +:vmpyeh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=6 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyeh -- "Rxx32 += vmpyeh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +define pcodeop vmpyehSatAdd; + +:vmpyeh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=6 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rd32 = vmpyh ( Rs32 , Rt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpyhX2RndSat; + +:vmpyh":<<1:rnd:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=7 & Rd5 & rt5 & rs5 & $(END_PACKET) { + Rd5 = vmpyhX2RndSat(rs5, rt5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rd32 = vmpyh ( Rs32 , Rt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpyhRndSat; + +:vmpyh":rnd:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x69 & op13=0 & op0507=7 & Rd5 & rt5 & rs5 & $(END_PACKET) { + Rd5 = vmpyhRndSat(rs5, rt5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rdd32 = vmpyh ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyhX2Sat; + +:vmpyh":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2c & op13=0 & op0507=5 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhX2Sat(rs5, rt5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rdd32 = vmpyh ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyhSat; + +:vmpyh":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=5 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhSat(rs5, rt5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rxx32 += vmpyh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x + +define pcodeop vmpyhAdd; + +:vmpyh+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x39 & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rxx32 += vmpyh ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyhX2SatAdd; + +:vmpyh+=":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=5 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhX2SatAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rxx32 += vmpyh ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyhSatAdd; + +:vmpyh+=":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=5 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhSatAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v4,14) vmpyhsu -- "Rdd32 = vmpyhsu ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpyhsuX2Sat; + +:vmpyhsu":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2c & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhsuX2Sat(rs5, rt5); + build EndPacket; +} + +# (v4,14) vmpyhsu -- "Rdd32 = vmpyhsu ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpyhsuSat; + +:vmpyhsu":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhsuSat(rs5, rt5); + build EndPacket; +} + +# (v4,14) vmpyhsu -- "Rxx32 += vmpyhsu ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyhsuX2SatAdd; + +:vmpyhsu+=":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3f & op13=0 & op0507=5 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhsuX2SatAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v4,14) vmpyhsu -- "Rxx32 += vmpyhsu ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyhsuSatAdd; + +:vmpyhsu+=":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3b & op13=0 & op0507=5 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhsuSatAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpywehX2RndSat; + +:vmpyweh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehX2RndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpywehX2Sat; + +:vmpyweh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpywehRndSat; + +:vmpyweh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehRndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpywehSat; + +:vmpyweh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpywehX2RndSatAdd; + +:vmpyweh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehX2RndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpywehX2SatAdd; + +:vmpyweh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpywehRndSatAdd; + +:vmpyweh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehRndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpywehSatAdd; + +:vmpyweh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyweuhX2RndSat; + +:vmpyweuh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhX2RndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyweuhX2Sat; + +:vmpyweuh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyweuhRndSat; + +:vmpyweuh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhRndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyweuhSat; + +:vmpyweuh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyweuhX2RndSatAdd; + +:vmpyweuh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhX2RndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyweuhX2SatAdd; + +:vmpyweuh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyweuhRndSatAdd; + +:vmpyweuh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhRndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyweuhSatAdd; + +:vmpyweuh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpywohX2RndSat; + +:vmpywoh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohX2RndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpywohX2Sat; + +:vmpywoh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpywohRndSat; + +:vmpywoh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohRndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpywohSat; + +:vmpywoh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop vmpywohX2RndSatAdd; + +:vmpywoh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohX2RndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop vmpywohX2SatAdd; + +:vmpywoh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop vmpywohRndSatAdd; + +:vmpywoh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohRndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop vmpywohSatAdd; + +:vmpywoh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vmpywouh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vmpywouh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vmpywouh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vmpywouh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +:vmpywouh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +:vmpywouh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P - t t t t t 1 1 1 x x x x x + +:vmpywouh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +:vmpywouh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,13) vmux -- "Rdd32 = vmux ( Pu4 , Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 0 1 + + + s s s s s P P + t t t t t + u u d d d d d + +define pcodeop vmux; + +:vmux Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=13 & op2127=0x08 & op13=0 & op7=0 & Rdd5 & rss5 & rtt5 & pu0506 & $(END_PACKET) { + Rdd5 = vmux(pu0506,rss5,rtt5); + build EndPacket; +} + +# (v2,15) vnavgh -- "Rd32 = vnavgh ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 1 + 1 1 s s s s s P P + t t t t t + + + d d d d d + +:vnavgh Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x3b & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) +{ + Rd5[0,16] = (rt5[0,16] - rs5[0,16]) >> 1; + Rd5[16,16] = (rt5[16,16] - rs5[16,16]) >> 1; + build EndPacket; +} + +# (v2,13) vnavgh -- "Rdd32 = vnavgh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:vnavgh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +{ + Rdd5[0,16] = (rtt5[0,16] - rss5[0,16]) >> 1; + Rdd5[16,16] = (rtt5[16,16] - rss5[16,16]) >> 1; + Rdd5[32,16] = (rtt5[32,16] - rss5[32,16]) >> 1; + Rdd5[48,16] = (rtt5[48,16] - rss5[48,16]) >> 1; + build EndPacket; +} + +# (v2,13) vnavgh -- "Rdd32 = vnavgh ( Rtt32 , Rss32 ) :crnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +define pcodeop vnavghCrndSat; + +:vnavgh":crnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vnavghCrndSat(rtt5, rss5); + build EndPacket; +} + +# (v2,13) vnavgh -- "Rdd32 = vnavgh ( Rtt32 , Rss32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vnavghRndSat; + +:vnavgh":rnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vnavghRndSat(rtt5, rss5); + build EndPacket; +} + +# (v2,13) vnavgw -- "Rdd32 = vnavgw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vnavgw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +{ + Rdd5[0,32] = (rtt5[0,32] - rss5[0,32]) >> 1; + Rdd5[32,32] = (rtt5[32,32] - rss5[32,32]) >> 1; + build EndPacket; +} + +# (v2,13) vnavgw -- "Rdd32 = vnavgw ( Rtt32 , Rss32 ) :crnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop vnavgwCrndSat; + +:vnavgw":crnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vnavgwCrndSat(rtt5, rss5); + build EndPacket; +} + +# (v2,13) vnavgw -- "Rdd32 = vnavgw ( Rtt32 , Rss32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 1 0 + d d d d d + +define pcodeop vnavgwRndSat; + +:vnavgw":rnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vnavgwRndSat(rtt5, rss5); + build EndPacket; +} + +# (v4,14) vpmpyh -- "Rdd32 = vpmpyh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vpmpyh Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2e & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) +unimpl + +# (v4,14) vpmpyh -- "Rxx32 ^= vpmpyh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +:vpmpyh"^=" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3d & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) +unimpl + +# (v4,14) vraddh -- "Rd32 = vraddh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 + 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vraddh Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x49 & op13=0 & op0507=7 & Rd5 & rtt5 & rss5 & $(END_PACKET) { + tmp:4 = sext(rss5[0,16]); + tmp = tmp + sext(rss5[16,16]); + tmp = tmp + sext(rss5[32,16]); + tmp = tmp + sext(rss5[48,16]); + tmp = tmp + sext(rtt5[0,16]); + tmp = tmp + sext(rtt5[16,16]); + tmp = tmp + sext(rtt5[32,16]); + tmp = tmp + sext(rtt5[48,16]); + Rd5 = tmp; + build EndPacket; +} + +# (v2,14) vraddub -- "Rdd32 = vraddub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vraddub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vraddub -- "Rxx32 += vraddub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vraddub+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vradduh -- "Rd32 = vradduh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 + + s s s s s P P + t t t t t + 0 1 d d d d d + +:vradduh Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x48 & op13=0 & op0507=1 & Rd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vrcmpyi -- "Rdd32 = vrcmpyi ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vrcmpyi; + +:vrcmpyi Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyi(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vrcmpyi -- "Rdd32 = vrcmpyi ( Rss32 , Rtt32 * )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:vrcmpyi Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=0 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyi(rss5, Rtt5Conjugate); + build EndPacket; +} + +# (v2,14) vrcmpyi -- "Rxx32 += vrcmpyi ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +define pcodeop vrcmpyiAdd; + +:vrcmpyi+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=0 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyiAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vrcmpyi -- "Rxx32 += vrcmpyi ( Rss32 , Rtt32 * )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:vrcmpyi+= Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=0 & rdd5 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyiAdd(rss5, Rtt5Conjugate, rdd5); + build EndPacket; +} + +# (v2,14) vrcmpyr -- "Rdd32 = vrcmpyr ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vrcmpyr; + +:vrcmpyr Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyr(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vrcmpyr -- "Rdd32 = vrcmpyr ( Rss32 , Rtt32 * )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vrcmpyr Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=1 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyr(rss5, Rtt5Conjugate); + build EndPacket; +} + +# (v2,14) vrcmpyr -- "Rxx32 += vrcmpyr ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +define pcodeop vrcmpyrAdd; + +:vrcmpyr+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=1 & rdd5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyrAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vrcmpyr -- "Rxx32 += vrcmpyr ( Rss32 , Rtt32 * )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vrcmpyr+= Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=1 & rdd5 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyrAdd(rss5, Rtt5Conjugate, rdd5); + build EndPacket; +} + +# (v4,14) vrcmpys -- "Rd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :rnd :sat :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 + 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vrcmpys":<<1:rnd:sat:raw:hi" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x4d & op13=0 & op0507=6 & Rd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :rnd :sat :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 + 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vrcmpys":<<1:rnd:sat:raw:lo" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x4d & op13=0 & op0507=7 & Rd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rdd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vrcmpys":<<1:sat:raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rdd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vrcmpys":<<1:sat:raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rxx32 += vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +:vrcmpys+=":<<1:sat:raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rxx32 += vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +:vrcmpys+=":<<1:sat:raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrcnegh -- "Rxx32 += vrcnegh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 t t t t t 1 1 1 x x x x x + +:vrcnegh+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=7 & Rdd5 & rt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrcrotate -- "Rdd32 = vrcrotate ( Rss32 , Rt32 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 1 + s s s s s P P i t t t t t 1 1 i d d d d d + +:vrcrotate Rdd5,rss5,rt5,Uimm2_13_05 EndPacket is iclass=12 & op2127=0x1e & op0607=3 & Uimm2_13_05 & Rdd5 & rt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrcrotate -- "Rxx32 += vrcrotate ( Rss32 , Rt32 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 1 s s s s s P P i t t t t t + + i x x x x x + +:vrcrotate+= Rdd5,rss5,rt5,Uimm2_13_05 EndPacket is iclass=12 & op2127=0x5d & op0607=0 & Uimm2_13_05 & Rdd5 & rt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrmaxh -- "Rxx32 = vrmaxh ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 0 0 1 u u u u u + +:vrmaxh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=1 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrmaxuh -- "Rxx32 = vrmaxuh ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 0 1 u u u u u + +:vrmaxuh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=1 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrmaxuw -- "Rxx32 = vrmaxuw ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 1 0 u u u u u + +:vrmaxuw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=2 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrmaxw -- "Rxx32 = vrmaxw ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 0 1 0 u u u u u + +:vrmaxw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=2 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrminh -- "Rxx32 = vrminh ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 0 1 u u u u u + +:vrminh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=5 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrminuh -- "Rxx32 = vrminuh ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 0 1 u u u u u + +:vrminuh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=5 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrminuw -- "Rxx32 = vrminuw ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 1 0 u u u u u + +:vrminuw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=6 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrminw -- "Rxx32 = vrminw ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 1 0 u u u u u + +:vrminw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=6 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpybsu -- "Rdd32 = vrmpybsu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vrmpybsu Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpybsu -- "Rxx32 += vrmpybsu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vrmpybsu+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpybu -- "Rdd32 = vrmpybu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vrmpybu Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpybu -- "Rxx32 += vrmpybu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vrmpybu+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vrmpyh -- "Rdd32 = vrmpyh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +define pcodeop vrmpyh; + +:vrmpyh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpyh(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vrmpyh -- "Rxx32 += vrmpyh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x + +define pcodeop vrmpyhAdd; + +:vrmpyh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=2 & rdd5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpyhAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v4,14) vrmpyweh -- "Rdd32 = vrmpyweh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vrmpyweh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpyweh -- "Rdd32 = vrmpyweh ( Rss32 , Rtt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vrmpyweh":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpyweh -- "Rxx32 += vrmpyweh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x + +:vrmpyweh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpyweh -- "Rxx32 += vrmpyweh ( Rss32 , Rtt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x + +:vrmpyweh+=":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpywoh -- "Rdd32 = vrmpywoh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vrmpywoh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpywoh -- "Rdd32 = vrmpywoh ( Rss32 , Rtt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vrmpywoh":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpywoh -- "Rxx32 += vrmpywoh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P + t t t t t 1 1 0 x x x x x + +:vrmpywoh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpywoh -- "Rxx32 += vrmpywoh ( Rss32 , Rtt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 1 0 x x x x x + +:vrmpywoh+=":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,8) vrndwh -- "Rd32 = vrndwh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 1 0 + d d d d d + +define pcodeop vrndwh; + +:vrndwh Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0x04 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vrndwh(rss5); + build EndPacket; +} + +# (v2,8) vrndwh -- "Rd32 = vrndwh ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 1 1 + d d d d d + +define pcodeop vrndwhSat; + +:vrndwh":sat" Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0x06 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vrndwhSat(rss5); + build EndPacket; +} + +# (v2,14) vrsadub -- "Rdd32 = vrsadub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vrsadub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vrsadub -- "Rxx32 += vrsadub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x + +:vrsadub+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,8) vsathb -- "Rd32 = vsathb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 + s s s s s P P + + + + + + 0 0 + d d d d d + +define pcodeop vsathb; + +:vsathb Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = vsathb(rs5); + build EndPacket; +} + +# (v2,8) vsathb -- "Rd32 = vsathb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 1 1 + d d d d d + + +:vsathb Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0x06 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vsathb(rss5); + build EndPacket; +} + +# (v2,8) vsathb -- "Rdd32 = vsathb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 1 1 d d d d d + +:vsathb Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x07 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = vsathb(rss5); + build EndPacket; +} + +# (v2,8) vsathub -- "Rd32 = vsathub ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 + s s s s s P P + + + + + + 0 1 + d d d d d + +:vsathub Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x02 & Rd5 & rs5 & $(END_PACKET) +unimpl + +# (v2,8) vsathub -- "Rd32 = vsathub ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 0 0 + d d d d d + +:vsathub Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0 & Rd5 & rss5 & $(END_PACKET) +unimpl + +# (v2,8) vsathub -- "Rdd32 = vsathub ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 0 0 d d d d d + +:vsathub Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x04 & Rdd5 & rss5 & $(END_PACKET) +unimpl + +# (v2,8) vsatwh -- "Rd32 = vsatwh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 0 1 + d d d d d + +define pcodeop vsatwh; + +:vsatwh Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0x02 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vsatwh(rss5); + build EndPacket; +} + +# (v2,8) vsatwh -- "Rdd32 = vsatwh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 1 0 d d d d d + +:vsatwh Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = vsatwh(rss5); + build EndPacket; +} + +# (v2,8) vsatwuh -- "Rd32 = vsatwuh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 1 0 + d d d d d + +define pcodeop vsatwuh; + +:vsatwuh Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0x04 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vsatwuh(rss5); + build EndPacket; +} + +# (v2,8) vsatwuh -- "Rdd32 = vsatwuh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 0 1 d d d d d + +:vsatwuh Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x05 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = vsatwuh(rss5); + build EndPacket; +} + +# (v2,8) vsplatb -- "Rd32 = vsplatb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 1 1 d d d d d + +define pcodeop vsplatb; + +:vsplatb Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0813=0 & op0507=7 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = vsplatb(rs5); + build EndPacket; +} + +# (?,8) vsplatb -- "Rdd32 = vsplatb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 1 + s s s s s P P + + + + + + 1 0 + d d d d d + +:vsplatb Rdd5,rs5 EndPacket is iclass=8 & op2127=0x22 & op0813=0 & op0507=4 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = vsplatb(rs5); + build EndPacket; +} + +# (v2,8) vsplath -- "Rdd32 = vsplath ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 1 + s s s s s P P + + + + + + 0 1 + d d d d d + +define pcodeop vsplath; + +:vsplath Rdd5,rs5 EndPacket is iclass=8 & op2127=0x22 & op0813=0 & op0507=2 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = vsplath(rs5); + build EndPacket; +} + +# (v2,12) vspliceb -- "Rdd32 = vspliceb ( Rss32 , Rtt32 , #u3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 0 1 + + s s s s s P P + t t t t t i i i d d d d d + +:vspliceb Rdd5,rss5,rtt5,Uimm3_0507 EndPacket is iclass=12 & op2127=0x04 & op13=0 & Uimm3_0507 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + cnt:1 = 8 * Uimm3_0507; + mask:8 = -1 >> (64 - cnt); + Rdd5 = (rtt5 << cnt) | (mask & rss5); + build EndPacket; +} + +# (v2,12) vspliceb -- "Rdd32 = vspliceb ( Rss32 , Rtt32 , Pu4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 0 1 0 + s s s s s P P + t t t t t + u u d d d d d + +:vspliceb Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=12 & op2127=0x14 & op13=0 & op7=0 & pu0506 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + cnt:1 = 8 * (pu0506 & 0x7); + mask:8 = -1 >> (64 - cnt); + Rdd5 = (rtt5 << cnt) | (mask & rss5); + build EndPacket; +} + +# (v2,15) vsubh -- "Rd32 = vsubh ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 1 0 0 s s s s s P P + t t t t t + + + d d d d d + +:vsubh Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x34 & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) { + Rd5[0,16] = rt5[0,16] - rs5[0,16]; + Rd5[16,16] = rt5[16,16] - rs5[16,16]; + build EndPacket; +} + +# (v2,15) vsubh -- "Rd32 = vsubh ( Rt32 , Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 1 0 1 s s s s s P P + t t t t t + + + d d d d d + +:vsubh":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x35 & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) { + h:2 = 0; + subSat16(h, rt5[0,16], rs5[0,16]); + Rd5[0,16] = h; + subSat16(h, rt5[16,16], rs5[16,16]); + Rd5[16,16] = h; + build EndPacket; +} + +# (v2,13) vsubh -- "Rdd32 = vsubh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vsubh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5[0,16] = rtt5[0,16] - rss5[0,16]; + Rdd5[16,16] = rtt5[16,16] - rss5[16,16]; + Rdd5[32,16] = rtt5[32,16] - rss5[32,16]; + Rdd5[48,16] = rtt5[48,16] - rss5[48,16]; + build EndPacket; +} + +# (v2,13) vsubh -- "Rdd32 = vsubh ( Rtt32 , Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vsubh":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + h:2 = 0; + subSat16(h, rtt5[0,16], rss5[0,16]); + Rdd5[0,16] = h; + subSat16(h, rtt5[16,16], rss5[16,16]); + Rdd5[16,16] = h; + subSat16(h, rtt5[32,16], rss5[32,16]); + Rdd5[32,16] = h; + subSat16(h, rtt5[48,16], rss5[48,16]); + Rdd5[48,16] = h; + build EndPacket; +} + +# (v2,13) vsubub -- "Rdd32 = vsubub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vsubub; + +:vsubub Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vsubub(rtt5,rss5); + build EndPacket; +} + +# (v2,13) vsubub -- "Rdd32 = vsubub ( Rtt32 , Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vsububSat; + +:vsubub":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vsububSat(rtt5,rss5); + build EndPacket; +} + +# (v2,15) vsubuh -- "Rd32 = vsubuh ( Rt32 , Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 1 1 1 s s s s s P P + t t t t t + + + d d d d d + +:vsubuh":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x37 & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) { + h:2 = 0; + subuSat16(h, rt5[0,16], rs5[0,16]); + Rd5[0,16] = h; + subuSat16(h, rt5[16,16], rs5[16,16]); + Rd5[16,16] = h; + build EndPacket; +} + +# (v2,13) vsubuh -- "Rdd32 = vsubuh ( Rtt32 , Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vsubuh":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + h:2 = 0; + subuSat16(h, rtt5[0,16], rss5[0,16]); + Rdd5[0,16] = h; + subuSat16(h, rtt5[16,16], rss5[16,16]); + Rdd5[16,16] = h; + subuSat16(h, rtt5[32,16], rss5[32,16]); + Rdd5[32,16] = h; + subuSat16(h, rtt5[48,16], rss5[48,16]); + Rdd5[48,16] = h; + build EndPacket; +} + +# (v2,13) vsubw -- "Rdd32 = vsubw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +:vsubw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5[0,32] = rtt5[0,32] - rss5[0,32]; + Rdd5[32,32] = rtt5[32,32] - rss5[32,32]; + build EndPacket; +} + +# (v2,13) vsubw -- "Rdd32 = vsubw ( Rtt32 , Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vsubw":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + w:4 = 0; + subSat32(w, rtt5[0,32], rss5[0,32]); + Rdd5[0,32] = w; + subSat32(w, rtt5[32,32], rss5[32,32]); + Rdd5[32,32] = w; + build EndPacket; +} + +# (v2,8) vsxtbh -- "Rdd32 = vsxtbh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 0 0 + d d d d d + +define pcodeop vsxtbh; + +:vsxtbh Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = vsxtbh(rs5); + build EndPacket; +} + +# (v2,8) vsxthw -- "Rdd32 = vsxthw ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 1 0 + d d d d d + +:vsxthw Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0x04 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5[0,32] = sext(rs5[0,16]); + Rdd5[32,32] = sext(rs5[16,16]); + build EndPacket; +} + +# (v2,8) vtrunehb -- "Rd32 = vtrunehb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 0 1 + d d d d d + +define pcodeop vtrunehb; + +:vtrunehb Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0x02 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vtrunehb(rss5); + build EndPacket; +} + +# (v2,12) vtrunewh -- "Rdd32 = vtrunewh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:vtrunewh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5[0,16] = rtt5[0,16]; + Rdd5[16,16] = rtt5[32,16]; + Rdd5[32,16] = rss5[0,16]; + Rdd5[48,16] = rss5[32,16]; + build EndPacket; +} + +# (v2,8) vtrunohb -- "Rd32 = vtrunohb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 0 0 + d d d d d + +define pcodeop vtrunohb; + +:vtrunohb Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vtrunohb(rss5); + build EndPacket; +} + +# (v2,12) vtrunowh -- "Rdd32 = vtrunowh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:vtrunowh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5[0,16] = rtt5[16,16]; + Rdd5[16,16] = rtt5[48,16]; + Rdd5[32,16] = rss5[16,16]; + Rdd5[48,16] = rss5[48,16]; + build EndPacket; +} + +# (v4,12) vxaddsubh -- "Rdd32 = vxaddsubh ( Rss32 , Rtt32 ) :rnd :>>1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop vxaddsubhRndX2Sat; + +:vxaddsubh":rnd:>>1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxaddsubhRndX2Sat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxaddsubh -- "Rdd32 = vxaddsubh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +define pcodeop vxaddsubhSat; + +:vxaddsubh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxaddsubhSat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxaddsubw -- "Rdd32 = vxaddsubw ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop vxaddsubwSat; + +:vxaddsubw":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxaddsubwSat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxsubaddh -- "Rdd32 = vxsubaddh ( Rss32 , Rtt32 ) :rnd :>>1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +define pcodeop vxsubaddhRndX2Sat; + +:vxsubaddh":rnd:>>1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxsubaddhRndX2Sat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxsubaddh -- "Rdd32 = vxsubaddh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop vxsubaddhSat; + +:vxsubaddh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxsubaddhSat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxsubaddw -- "Rdd32 = vxsubaddw ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +define pcodeop vxsubaddwSat; + +:vxsubaddw":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxsubaddwSat(rtt5,rss5); + build EndPacket; +} + +# (v2,8) vzxtbh -- "Rdd32 = vzxtbh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 0 1 + d d d d d + +define pcodeop vzxtbh; + +:vzxtbh Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0x02 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = vzxtbh(rs5); + build EndPacket; +} + +# (v2,8) vzxthw -- "Rdd32 = vzxthw ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 1 1 + d d d d d + +:vzxthw Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0x06 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5[0,32] = zext(rs5[0,16]); + Rdd5[32,32] = zext(rs5[16,16]); + build EndPacket; +} + +# (v2,6) wait -- "wait ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P - - - - - - 0 0 0 - - - - - + +define pcodeop wait; + +:wait rs5 EndPacket is iclass=6 & op2127=0x22 & op0507=0 & rs5 & $(END_PACKET) { + wait(rs5); + build EndPacket; +} + +# (v2,6) xor -- "Pd4 = xor ( Ps4 , Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 1 0 0 - - s s P P 0 - - - t t - - - - - - d d + +:xor Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x5a & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 ^ pu0809); + build EndPacket; +} + +# (v2,15) xor -- "Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 0 1 1 s s s s s P P - t t t t t - - - d d d d d + +:xor Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x0b & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = rs5 ^ rt5; + build EndPacket; +} + +# (v2,13) xor -- "Rdd32 = xor ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 1 0 0 d d d d d + +:xor Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1f & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = rss5 ^ rtt5; + build EndPacket; +} + +# (v4,14) xor -- "Rx32 &= xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 1 0 x x x x x + +:xor&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=2 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 & (rs5 ^ rt5); + build EndPacket; +} + +# (v2,14) xor -- "Rx32 ^= xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P + t t t t t + 1 1 x x x x x + +:xor"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7c & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 ^ (rs5 ^ rt5); + build EndPacket; +} + +# (v4,14) xor -- "Rx32 |= xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 0 1 x x x x x + +:xor|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 | (rs5 ^ rt5); + build EndPacket; +} + +# (v4,12) xor -- "Rxx32 ^= xor ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 0 1 + + s s s s s P P + t t t t t + + + x x x x x + +:xor"^=" Rdd5,rss5,rtt5 EndPacket is iclass=0xc & op2127=0x54 & op13=0 & op0507=0 & rss5 & rtt5 & rdd5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rdd5 ^ (rss5 ^ rtt5); + build EndPacket; +} + +# (v2,15) xor -- "if ( Pu4 ) Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) xor -- "if ( ! Pu4 ) Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) xor -- "if ( Pu4 .new ) Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) xor -- "if ( ! Pu4 .new ) Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 1 t t t t t 1 u u d d d d d + +:xor^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=1 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 ^ rt5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v4,7) zxtb -- "if ( Pu4 ) Rd32 = zxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 0 0 u u + + + d d d d d +# +# (v4,7) zxtb -- "if ( ! Pu4 ) Rd32 = zxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 1 0 u u + + + d d d d d +# +# (v4,7) zxtb -- "if ( Pu4 .new ) Rd32 = zxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 0 1 u u + + + d d d d d +# +# (v4,7) zxtb -- "if ( ! Pu4 .new ) Rd32 = zxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 1 1 u u + + + d d d d d + +:zxtb^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x04 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +{ + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = zext(rs5:1); + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,7) zxth -- "Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 0 + + + + + + + + d d d d d + +:zxth Rd5,rs5 EndPacket is iclass=7 & op2127=0x06 & op0513=0 & rs5 & Rd5 & $(END_PACKET) +{ + Rd5 = zext(rs5:2); + build EndPacket; +} + +# (v4,7) zxth -- "if ( Pu4 ) Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 0 0 u u + + + d d d d d +# +# (v4,7) zxth -- "if ( ! Pu4 ) Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 1 0 u u + + + d d d d d +# +# (v4,7) zxth -- "if ( Pu4 .new ) Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 0 1 u u + + + d d d d d +# +# (v4,7) zxth -- "if ( ! Pu4 .new ) Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 1 1 u u + + + d d d d d + +:zxth^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x06 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +{ + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = zext(rs5:2); + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# +# Dual-Instructions with PP bits +# + +JmpRel9: "; jump" RelDest9x is RelDest9x { + <> + goto RelDest9x; +} + +# (v4,1) jump -- "Rd16 = #U6 ; jump #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 - 1 1 0 - - i i d d d d P P I I I I I I i i i i i i i - + +:assign Rd1619,Uimm8_0813 JmpRel9 EndPacket is iclass=1 & op2426=6 & Uimm8_0813 & Rd1619 & JmpRel9 & $(END_PACKET) { + Rd1619 = zext(Uimm8_0813); + build EndPacket; +} + +# (v4,1) jump -- "Rd16 = Rs16 ; jump #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 - 1 1 1 - - i i s s s s P P - - d d d d i i i i i i i - + +:assign Rd0811,rs4p JmpRel9 EndPacket is iclass=1 & op2426=7 & rs4p & Rd0811 & JmpRel9 & $(END_PACKET) { + Rd0811 = rs4p; + build JmpRel9; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 0 - - - 0 0 i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 0 - - - 0 0 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 1 - - - 0 0 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 1 - - - 0 0 i i i i i i i - +# + +FlowCond_Pu25_S22: ".if("pu25name".new)" is op22=0 & pu25name & pu25_ { tmp:1 = pu25_ & 1; export tmp; } +FlowCond_Pu25_S22: ".if(!"pu25name".new)" is op22=1 & pu25name & pu25_ { tmp:1 = !(pu25_ & 1); export tmp; } + +IfJmpRel9_Pu25_T13_S22: "; jump"^FlowCond_Pu25_S22^Taken13 RelDest9x is FlowCond_Pu25_S22 & Taken13 & RelDest9x { + <> + if (FlowCond_Pu25_S22 == 0) goto ; + goto RelDest9x; + +} + +:cmp.eq Pd25,rs4p,MinusOne IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=3 & op0809=0 & Pd25 & rs4p & MinusOne & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p == -1); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 0 0 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 0 1 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 0 0 i i s s s s P P 1 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 0 1 i i s s s s P P 1 I I I I I i i i i i i i - + +:cmp.eq Pd25,rs4p,Uimm8_0812 IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=0 & Pd25 & rs4p & Uimm8_0812 & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p == zext(Uimm8_0812)); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 0 0 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 0 1 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 0 0 i i s s s s P P 1 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 0 1 i i s s s s P P 1 u t t t t i i i i i i i - + +FlowCond_Pu12_S22: ".if("pu12name".new)" is op22=0 & pu12name & pu12_ { tmp:1 = pu12_ & 1; export tmp; } +FlowCond_Pu12_S22: ".if(!"pu12name".new)" is op22=1 & pu12name & pu12_ { tmp:1 = !(pu12_ & 1); export tmp; } + +IfJmpRel9_Pu12_T13_S22: "; jump"^FlowCond_Pu12_S22^Taken13 RelDest9x is FlowCond_Pu12_S22 & Taken13 & RelDest9x { + <> + if (FlowCond_Pu12_S22 == 0) goto ; + goto RelDest9x; + +} + +:cmp.eq Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2327=8 & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p == rt4p); + Pd12 = Pd12 & (bool * 0xff); + build IfJmpRel9_Pu12_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 0 - - - 0 1 i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 0 - - - 0 1 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 1 - - - 0 1 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 1 - - - 0 1 i i i i i i i - + +:cmp.gt Pd25,rs4p,MinusOne IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=3 & op0809=1 & Pd25 & rs4p & MinusOne & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p s> -1); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 1 0 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 1 1 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 1 0 i i s s s s P P 1 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 1 1 i i s s s s P P 1 I I I I I i i i i i i i - + +:cmp.gt Pd25,rs4p,Uimm8_0812 IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=1 & Pd25 & rs4p & Uimm8_0812 & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p s> zext(Uimm8_0812)); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 1 0 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 1 1 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 1 0 i i s s s s P P 1 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 1 1 i i s s s s P P 1 u t t t t i i i i i i i - + +:cmp.gt Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2327=9 & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p s> rt4p); + Pd12 = Pd12 & (bool * 0xff); + build IfJmpRel9_Pu12_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 0 0 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 0 1 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 0 0 i i s s s s P P 1 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 0 1 i i s s s s P P 1 I I I I I i i i i i i i - + +:cmp.gtu Pd25,rs4p,Uimm8_0812 IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=2 & Pd25 & rs4p & Uimm8_0812 & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p > zext(Uimm8_0812)); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 1 0 0 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 1 0 1 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 1 0 0 i i s s s s P P 1 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 1 0 1 i i s s s s P P 1 u t t t t i i i i i i i - + +:cmp.gtu Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2327=0xa & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p > rt4p); + Pd12 = Pd12 & (bool * 0xff); + build IfJmpRel9_Pu12_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 0 - - - 1 1 i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 0 - - - 1 1 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 1 - - - 1 1 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 1 - - - 1 1 i i i i i i i - + +:tstbit Pd25,rs4p,Zero IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=3 & op0809=3 & Pd25 & rs4p & Zero & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p & 1) != 0; + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} diff --git a/pypcode/processors/Hexagon/data/languages/hexagon.slaspec b/pypcode/processors/Hexagon/data/languages/hexagon.slaspec new file mode 100755 index 00000000..778d7a78 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon.slaspec @@ -0,0 +1,888 @@ +# Qualcomm Hexagon (V73) and HVX (V69) + +## KNOWN ISSUES +# 1. Shift amounts may be positive or negative, however in some cases no special handling +# is provided for negative shift amounts. +# 2. There are many complex instructions with unimplemented pcode or simple custom pcodeops +# +## NOTES +# 1. Implementation includes V73 system registers, instruction set may be incomplete +# 2. HVX vector register size is 128-bytes (see defines below), paired size is 256-bytes +# +## VERSIONS +# 1.x - preliminary versions (pre-release) +# 2.0 - initial release +# 2.1 - added support for conditional commit of modifying operands, e.g. (r0++#4) (r0=#4) +# 2.2 - TBD (research change history) +# 2.3 - Added missing instructions and corrected invalid DF instructions. The disabled +# ADD_DP_OPS property has been used to contain these although they may be removed +# in the future. +# 2.4 - Added EXEC_COND crossbuild (12.0.1) and added HVX support (12.0.2) +# + +@define HVX_VECTOR_SIZE "128" +@define HVX_VECTOR_PAIR_SIZE "256" +@define HVX_VECTOR_BASE "0x2000" +@define HVX_VECTOR_TMP_BASE "0x3000" + +@define HVX_PREDICATE_SIZE "16" + +define endian=little; +define alignment=4; + +define space ram type=ram_space size=4 default; +define space register type=register_space size=4; + +# General purpose registers +# Register aliases have been used for R29(SP), R30(FP) and R31(LR) + +define register offset=0 size=8 [ R1R0 R3R2 R5R4 R7R6 R9R8 R11R10 R13R12 R15R14 + R17R16 R19R18 R21R20 R23R22 R25R24 R27R26 R29R28 R31R30 ]; + +define register offset=0 size=4 [ R0 R1 R2 R3 R4 R5 R6 R7 + R8 R9 R10 R11 R12 R13 R14 R15 + R16 R17 R18 R19 R20 R21 R22 R23 + R24 R25 R26 R27 R28 SP FP LR ]; + +define register offset=0 size=2 [ R0.L R0.H R1.L R1.H R2.L R2.H R3.L R3.H + R4.L R4.H R5.L R5.H R6.L R6.H R7.L R7.H + R8.L R8.H R9.L R9.H R10.L R10.H R11.L R11.H + R12.L R12.H R13.L R13.H R14.L R14.H R15.L R15.H + R16.L R16.H R17.L R17.H R18.L R18.H R19.L R19.H + R20.L R20.H R21.L R21.H R22.L R22.H R23.L R23.H + R24.L R24.H R25.L R25.H R26.L R26.H R27.L R27.H + R28.L R28.H R29.L R29.H R30.L R30.H R31.L R31.H ]; + +# General purpose shadow registers (used to delay register writes until end of instruction packet) + +define register offset=0x100 size=8 [ R1R0_ R3R2_ R5R4_ R7R6_ R9R8_ R11R10_ R13R12_ R15R14_ + R17R16_ R19R18_ R21R20_ R23R22_ R25R24_ R27R26_ R29R28_ R31R30_ ]; + +define register offset=0x100 size=4 [ R0.new R1.new R2.new R3.new R4.new R5.new R6.new R7.new + R8.new R9.new R10.new R11.new R12.new R13.new R14.new R15.new + R16.new R17.new R18.new R19.new R20.new R21.new R22.new R23.new + R24.new R25.new R26.new R27.new R28.new SP.new FP.new LR.new ]; + +define register offset=0x100 size=2 [ R0.L_ R0.H_ R1.L_ R1.H_ R2.L_ R2.H_ R3.L_ R3.H_ + R4.L_ R4.H_ R5.L_ R5.H_ R6.L_ R6.H_ R7.L_ R7.H_ + R8.L_ R8.H_ R9.L_ R9.H_ R10.L_ R10.H_ R11.L_ R11.H_ + R12.L_ R12.H_ R13.L_ R13.H_ R14.L_ R14.H_ R15.L_ R15.H_ + R16.L_ R16.H_ R17.L_ R17.H_ R18.L_ R18.H_ R19.L_ R19.H_ + R20.L_ R20.H_ R21.L_ R21.H_ R22.L_ R22.H_ R23.L_ R23.H_ + R24.L_ R24.H_ R25.L_ R25.H_ R26.L_ R26.H_ R27.L_ R27.H_ + R28.L_ R28.H_ R29.L_ R29.H_ R30.L_ R30.H_ R31.L_ R31.H_ ]; + +# Control registers (range C16-C31 not defined by V5/V55) +# TODO: Check Control register naming across versions - with only one variant not sure how we handle this +define register offset=0x200 size=8 [ C1C0 C3C2 C5C4 C7C6 C9C8 C11C10 C13C12 UPCYCLE + C17C16 PKTCOUNT C21C20 C23C22 C25C24 C27C26 C29C28 UTIMER ]; + +define register offset=0x200 size=4 [ SA0 LC0 SA1 LC1 P3P0 C5 M0 M1 + USR PC UGP GP CS0 CS1 UPCYCLELO UPCYCLEHI + FRAMELIMIT FRAMEKEY PKTCOUNTLO PKTCOUNTHI C20 C21 C22 C23 + C24 C25 C26 C27 C28 C29 UTIMERLO UTIMERHI ]; + +define register offset=0x210 size=1 [ P3 P2 P1 P0 ]; # corresponds to P3P0 + +# TODO: Do ALL of the control registers need shadows for writing/flushing ?? +define register offset=0x300 size=8 [ C1C0_ C3C2_ C5C4_ C7C6_ C9C8_ C11C10_ C13C12_ UPCYCLE_ + C17C16_ PKTCOUNT_ C21C20_ C23C22_ C25C24_ C27C26_ C29C28_ UTIMER_ ]; + +define register offset=0x300 size=4 [ SA0_ LC0_ SA1_ LC1_ P3P0_ C5_ M0_ M1_ + USR_ PC_ UGP_ GP_ CS0_ CS1_ UPCYCLELO_ UPCYCLEHI_ + FRAMELIMIT_ FRAMEKEY_ PKTCOUNTLO_ PKTCOUNTHI_ C20_ C21_ C22_ C23_ + C24_ C25_ C26_ C27_ C28_ C29_ UTIMERLO_ UTIMERHI_ ]; # shadow versions + +define register offset=0x310 size=1 [ P3.new P2.new P1.new P0.new ]; # new/shadow versions, corresponds to P3P0_ + +# Guest Registers (see pspec for renaming) +# TODO: Do all guest registers need shadows for writing/flushing ?? +define register offset=0x400 size=8 [ G1G0 G3G2 G5G4 G7G6 G9G8 G11G10 G13G12 G15G14 + G17G16 G19G18 G21G20 G23G22 G25G24 G27G26 G29G28 G31G30 ]; + +define register offset=0x400 size=4 [ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 + G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 ]; + +# System Registers (see pspec for renaming) +# TODO: Do all system registers need shadows for writing/flushing ?? +define register offset=0x800 size=8 [ S1S0 S3S2 S5S4 S7S6 S9S8 S11S10 S13S12 S15S14 + S17S16 S19S18 S21S20 S23S22 S25S24 S27S26 S29S28 S31S30 + S33S32 S35S34 S37S36 S39S38 S41S40 S43S42 S45S44 S47S46 + S49S48 S51S50 S53S52 S55S54 S57S56 S59S58 S61S60 S63S62 ]; + +define register offset=0x800 size=4 [ S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 + S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 + S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 + S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 ]; + +# System register mappings (may differ with version) +@define ELR "S3" +@define SSR "S6" +@define CAUSE "S6[0,8]" # SSR bits 0..7, Exception/Trap Cause + +# Hidden language registers + +# ConditionReg: The condition register set by various +# conditional subconstructors which should be built within the +# appropriate <> or <> pcode section for an instruction +# immediately before using the ConditionReg value. +# +# WARNING! This may present a limitation if multiple condition/predicate +# registers are utilized within a single execute packet. +# +# <> +# build PuCondXYZ; +# if (ConditionReg == 0) goto ; +# rd5 = rd5_; +# + +define register offset=0x1000 size=1 [ ConditionReg ]; + +# ReturnAddr: This register is updated with inst_next for use within the <> section +# to facilitate LR assignment prior to a CALL flow. + +define register offset=0x1004 size=4 [ ReturnAddr ]; + +define register offset=$(HVX_VECTOR_BASE) size=$(HVX_VECTOR_PAIR_SIZE) + [ V1V0 V3V2 V5V4 V7V6 V9V8 V11V10 V13V12 V15V14 + V17V16 V19V18 V21V20 V23V22 V25V24 V27V26 V29V28 V31V30 ]; + +define register offset=$(HVX_VECTOR_BASE) size=$(HVX_VECTOR_SIZE) + [ V0 V1 V2 V3 V4 V5 V6 V7 + V8 V9 V10 V11 V12 V13 V14 V15 + V16 V17 V18 V19 V20 V21 V22 V23 + V24 V25 V26 V27 V28 V29 V30 V31 ]; + +# +# HVX vector temporary / shadow registers +# + +define register offset=$(HVX_VECTOR_TMP_BASE) size=$(HVX_VECTOR_PAIR_SIZE) + [ V1V0_ V3V2_ V5V4_ V7V6_ V9V8_ V11V10_ V13V12_ V15V14_ + V17V16_ V19V18_ V21V20_ V23V22_ V25V24_ V27V26_ V29V28_ V31V30_ ]; + + +define register offset=$(HVX_VECTOR_TMP_BASE) size=$(HVX_VECTOR_SIZE) + [ V0.new V1.new V2.new V3.new V4.new V5.new V6.new V7.new + V8.new V9.new V10.new V11.new V12.new V13.new V14.new V15.new + V16.new V17.new V18.new V19.new V20.new V21.new V22.new V23.new + V24.new V25.new V26.new V27.new V28.new V29.new V30.new V31.new ]; + +# +# HVX Predicate Registers (four predicate registers, each having 1-bit per byte of a vector register) +# +define register offset=0x4000 size=$(HVX_PREDICATE_SIZE) [ Q0 Q1 Q2 Q3 ]; + +# +# Define context bits +# + +define register offset=0x5000 size=12 contextreg; + +define context contextreg + + # Stored context bits + immext = (0,25) noflow # unshifted extended immediate value (26-bits << 6) + simmext = (0,25) signed noflow # unshifted extended immediate value (26-bits << 6) + immexted = (26,26) noflow # flag indicating previous instr was immext + + packetOffset = (27,28) noflow # instruction number within packet (distance from start of packet) + # The packetOffset is set prior to the actual instruction decode phase + packetOffset0 = (28,28) noflow # packetOffset bit-0 (lsb) + packetOffset1 = (27,27) noflow # packetOffset bit-1 (msb) + + useLoopCfg = (29,29) noflow # indicates body of h/w loop where LPCFG!=0 + + unused1 = (30,31) # Required to prevent field split across 32-bit integer boundary + + # NOTE: bulk packetBits used to simplify context propogation + packetBits = (32,63) noflow # allows bulk propagation (part 1 of 2) + + #--- start of auto-propogated packetBits (all sub-fields must be noflow) --- + + parse1 = (32,33) noflow #(keep) parse value for first instruction in packet (used for end of loop detection) + parse2 = (34,35) noflow #(keep) parse value for second instruction in packet (used for end of loop detection) + + # Ns8 / Os8 new register operand tracking + nreg0 = (36,40) noflow #(keep) slot-0 assigned reg (raw reg-number) + nreg1 = (41,45) noflow #(keep) slot-1 assigned reg (raw reg-number) + nreg2 = (46,50) noflow #(keep) slot-2 assigned reg (raw reg-number) + + removed1 = (51,55) noflow # no longer used - available for reuse + + # xreg - tracks immext use required for Ns8 and Os8 new register tracking + xreg = (56,60) noflow #(keep) slot reduction count when identifying nreg assignment slot + + unused2 = (61,63) noflow # Required to prevent field split across 32-bit integer boundary + + #--- end of auto-propogated packetBits --- + + # Transient context bits + phase = (64,66) #(keep) 3-bit instruction parse phase (used by :^instruction) + + # (keep) Localized transient context bits which may utilize overlapping regions in some controlled cases + tmpCtx3 = (67,69) # Temporary 3-bit context storage + tmpCtx2 = (67,68) # Temporary 2-bit context storage + nregSlot = (67,68) # computed nreg/vnreg slot derived from upper 2-bits of 3-bit Ns8 or Os8 encoding + shift = (67,68) # memory address shift factor (0-3) + + # Ns8 and Os8 .new register decode assist + nregr = (69,73) # computed new register 5-bit index (raw reg-number) + nreg = (69,73) # computed new scalar register (attached) - R0..R31 + nreg_ = (69,73) # computed new scalar shadow register (attached) - R0_..R31_ + vnreg = (69,73) # computed new vector register (attached) - V0..V31 + vnreg_ = (69,73) # computed new vector shadow register (attached) - V0_..V31_ + + cond = (74,74) # set if instruction is conditional with complex operand and ConditionReg will be set + # (not used by packed instructions) + + unused3 = (75,95) +; + +# USR Register Fields +@define LPCFG "USR[8,2]" +@define LPCFG_ "USR_[8,2]" +@define OVF "USR[0,1]" +@define OVF_ "USR_[0,1]" + +# Tokens + +define token instr (32) + iclass = (28,31) # instruction class (see page 118) + iclass3031 = (30,31) + iclass2931 = (29,31) + iclass2829 = (28,29) + iclass31 = (31,31) + iclass30 = (30,30) + iclass29 = (29,29) + iclass28 = (28,28) + + parse = (14,15) # packet/loop bits (01/10-not end of packet, 11-end of packet, 00-EE instruction) + parse_0 = (14,14) + parse_1 = (15,15) + + op2627 = (26,27) + op2527 = (25,27) + op2427 = (24,27) + op2426 = (24,26) + op2327 = (23,27) + op2326 = (23,26) + op2324 = (23,24) + op2227 = (22,27) + op2224 = (22,24) + op2223 = (22,23) + op2127 = (21,27) + op2125 = (21,25) + op2124 = (21,24) + op2123 = (21,23) + op2122 = (21,22) + op1920 = (19,20) + op1820 = (18,20) + op1827 = (18,27) + op1720 = (17,20) + op1620 = (16,20) + op1617 = (16,17) + op1213 = (12,13) + op1113 = (11,13) + op1112 = (11,12) + op1013 = (10,13) + op1012 = (10,12) + op1011 = (10,11) + op0913 = (9,13) + op0912 = (9,12) + op0911 = (9,11) + op0910 = (9,10) + op0813 = (8,13) + op0812 = (8,12) + op0810 = (8,10) + op0809 = (8,9) + op0613 = (6,13) + op0612 = (6,12) + op0607 = (6,7) + op0513 = (5,13) + op0512 = (5,12) + op0508 = (5,8) + op0507 = (5,7) + op0506 = (5,6) + op0412 = (4,12) + op0306 = (3,6) + op0304 = (3,4) + op0213 = (2,13) + op0207 = (2,7) + op0205 = (2,5) + op0204 = (2,4) + op0013 = (0,13) + op0007 = (0,7) + op0004 = (0,4) + op0002 = (0,2) + op0001 = (0,1) + + op27 = (27,27) + op26 = (26,26) + op25 = (25,25) + op24 = (24,24) + op23 = (23,23) + op22 = (22,22) + op21 = (21,21) + op20 = (20,20) + op19 = (19,19) + op18 = (18,18) + op16 = (16,16) + op13 = (13,13) + op12 = (12,12) + op11 = (11,11) + op10 = (10,10) + op8 = (8,8) + op7 = (7,7) + op6 = (6,6) + op5 = (5,5) + op4 = (4,4) + op3 = (3,3) + op2 = (2,2) + op1 = (1,1) + op0 = (0,0) + + s2526 = (25,26) signed + s2223 = (22,23) signed + s22 = (22,22) signed + s2127 = (21,27) signed + s2122 = (21,22) signed + s21 = (21,21) signed + s2026 = (20,26) signed + s2021 = (20,21) signed + s1924 = (19,24) signed + s1624 = (16,24) signed + s1622 = (16,22) signed + s1620 = (16,20) signed + s1619 = (16,19) signed + s13 = (13,13) signed + s0813 = (8,13) signed + s0812 = (8,12) signed + s0810 = (8,10) signed + s0712 = (7,12) signed + s0513 = (5,13) signed + s0512 = (5,12) signed + s0508 = (5,8) signed + s0410 = (4,10) signed + s0308 = (3,8) signed + s0306 = (3,6) signed + + i2526 = (25,26) + i2427 = (24,27) + i2426 = (24,26) + i24 = (24,24) + i2223 = (22,23) + i2127 = (21,27) + i2123 = (21,23) + i2122 = (21,22) + i2025 = (20,25) + i2024 = (20,24) + i1923 = (19,23) + i1627 = (16,27) + i1620 = (16,20) + i1619 = (16,19) + i1617 = (16,17) + i13 = (13,13) + i1213 = (12,13) + i9 = (9,9) + i0813 = (8,13) + i0812 = (8,12) + i0811 = (8,11) + i0810 = (8,10) + i8 = (8,8) + i0712 = (7,12) + i0513 = (5,13) + i0512 = (5,12) + i0511 = (5,11) + i0510 = (5,10) + i0509 = (5,9) + i0507 = (5,7) + i0506 = (5,6) + i5 = (5,5) + i0409 = (4,9) + i0408 = (4,8) + i0307 = (3,7) + i0306 = (3,6) + i0304 = (3,4) + i3 = (3,3) + i0204 = (2,4) + i0113 = (1,13) + i0111 = (1,11) + i0107 = (1,7) + i1 = (1,1) + i0013 = (0,13) + i0010 = (0,10) + i0007 = (0,7) + i0006 = (0,6) + i0005 = (0,5) + i0004 = (0,4) + i0003 = (0,3) + i0001 = (0,1) + + pu2324 = (23,24) # 8-bit predicate reg + pu2122 = (21,22) # 8-bit predicate reg + pu2122_ = (21,22) # 8-bit predicate reg (shadow) + pu2122name = (21,22) # 8-bit predicate reg (name) + pu1617 = (16,17) # 8-bit predicate reg + pu1112 = (11,12) # 8-bit predicate reg + pu1112_ = (11,12) # 8-bit predicate reg (shadow) + pu1112name = (11,12) # 8-bit predicate reg (name) + pu0910 = (9,10) # 8-bit predicate reg + pu0910_ = (9,10) # 8-bit predicate reg (shadow) + pu0910name = (9,10) # 8-bit predicate reg (name) + pu0809 = (8,9) # 8-bit predicate reg + pu0809_ = (8,9) # 8-bit predicate reg (shadow) + pu0809name = (8,9) # 8-bit predicate reg (name) + pu0607 = (6,7) # 8-bit predicate reg + pu0506 = (5,6) # 8-bit predicate reg + pu0506_ = (5,6) # 8-bit predicate reg (shadow) + pu0506name = (5,6) # 8-bit predicate reg (name) + pu0001 = (0,1) # 8-bit predicate reg + pu0001_ = (0,1) # 8-bit predicate reg (shadow) + pu0001name = (0,1) # 8-bit predicate reg (name) + + pu25 = (25,25) # P0/P1 + pu25_ = (25,25) # P0.new/P1.new + pu25name = (25,25) # P0/P1 (name) + pu12 = (12,12) # P0/P1 + pu12_ = (12,12) # P0.new/P1.new + pu12name = (12,12) # P0/P1 (name) + + qv0001 = (0,1) # HVX Vector predicate reg (Q0..Q3) + qv0506 = (5,6) # HVX Vector predicate reg (Q0..Q3) + qv0809 = (8,9) # HVX Vector predicate reg (Q0..Q3) + qv1112 = (11,12) # HVX Vector predicate reg (Q0..Q3) + qv2223 = (22,23) # HVX Vector predicate reg (Q0..Q3) + + mu = (13,13) # M0/M1 reg + + cs5 = (16,20) # 32-bit control reg + css5 = (16,20) # dual 32-bit control reg + + gs5 = (16,20) # 32-bit guest reg + gss5 = (16,20) # dual 32-bit guest reg + + rs5 = (16,20) # 32-bit general reg + rs5H = (16,20) # 16-bit general reg (high halfword) + rs5L = (16,20) # 16-bit general reg (low halfword) + rss5 = (16,20) # 64-bit general reg + rss5h = (16,20) # 32-bit high reg for rss5 + + rxx5 = (16,20) # 64-bit general reg + rxx5_ = (16,20) # 64-bit general reg (shadow) + rx5 = (16,20) # 32-bit general reg + rx5_ = (16,20) # 32-bit general reg (shadow) + rf5 = (16,20) # 32-bit general reg + rf5_ = (16,20) # 32-bit general reg (shadow) + rx5H = (16,20) # 16-bit general reg (high halfword) + rx5H_ = (16,20) # 16-bit general reg (high halfword, shadow) + rx5L = (16,20) # 16-bit general reg (low halfword) + rx5L_ = (16,20) # 16-bit general reg (low halfword, shadow) + + + rtt5 = (8,12) # 64-bit general reg + rtt5h = (8,12) # 32-bit high reg for rtt5 + rt5 = (8,12) # 32-bit general reg + rt5H = (8,12) # 16-bit general reg (high halfword) + rt5L = (8,12) # 16-bit general reg (low halfword) + + rd0812 = (8,12) # 32-bit general reg + rd0812_ = (8,12) # 32-bit general reg (shadow) + rdd0812 = (8,12) # 64-bit general reg + rdd0812_ = (8,12) # 64-bit general reg (shadow) + + rd5 = (0,4) # 32-bit general reg + rd5_ = (0,4) # 32-bit general reg (shadow) + rdd5 = (0,4) # 64-bit general reg + rdd5_ = (0,4) # 64-bit general reg (shadow) + rdd5h = (0,4) # hi (odd) 32-bit reg of a 64-bit general reg (use rd5 for lo/even) + rdd5h_ = (0,4) # hi (odd) 32-bit reg of a 64-bit general reg (use rd5 for lo/even) (shadow) + + rt1618 = (16,18) # 32-bit general reg (r0..r7) + + cd5 = (0,4) # 32-bit control reg + cd5_ = (0,4) # 32-bit control reg (shadow) + cdd5 = (0,4) # dual 32-bit control reg + cdd5_ = (0,4) # dual 32-bit control reg (shadow) + + gd5 = (0,4) # 32-bit guest reg + gdd5 = (0,4) # dual 32-bit guest regs + + ru5 = (0,4) # 32-bit control reg + ruu5 = (0,4) # 64-bit general reg + ru5H = (0,4) # 16-bit general reg (high halfword) + ru5L = (0,4) # 16-bit general reg (low halfword) + + vdd5 = (0,4) # HVX vector register pair + vdd5_ = (0,4) # HVX vector register pair (shadow) + + vss5 = (0,4) # HVX vector register pair + + vuu5 = (8,12) # HVX vector register pair +# vuu5_ = (8,12) # HVX vector register pair (shadow) + + vvv5 = (16,20) # HVX vector register pair +# vvv5_ = (16,20) # HVX vector register pair (shadow) + + vd5 = (0,4) # HVX vector register + vd5_ = (0,4) # HVX vector register (shadow) + + vs5 = (0,4) # HVX vector register +# vs5_ = (0,4) # HVX vector register (shadow) + + vu5 = (8,12) # HVX vector register +# vu5_ = (8,12) # HVX vector register (shadow) + + vv5 = (16,20) # HVX vector register +# vv5_ = (16,20) # HVX vector register (shadow) + + vz5 = (19,23) # HVX vector register +# vz5_ = (19,23) # HVX vector register (shadow) + + nreg_1618 = (16,18) # Ns8 32-bit general register .new (3-bit encoded) + nreg_0810 = (8,10) # Ns8 32-bit general register .new (3-bit encoded) + nreg_0002 = (0,2) # Ns8 32-bit general register or Os8 vector .new (3-bit encoded) + nreg_0002lsb = (0,0) # lsb of 3-bit encoding for alternate .new register use + + sd6 = (0,5) # supervisory register (assumed to be 32-bits each) + sdd6 = (0,5) # supervisory register (assumed to be 64-bits each) + ss6 = (16,21) # supervisory register (assumed to be 32-bits each) + sss6 = (16,21) # supervisory register (assumed to be 64-bits each) + + # duplex/packed fields - PP mode + + rs4p = (16,19) # 16-bit general reg + rt4p = (8,11) # 16-bit general reg + rd0811 = (8,11) # 16-bit general reg + rd0811_ = (8,11) # 16-bit general reg (shadow) + rd1619 = (16,19) # 16-bit general reg + rd1619_ = (16,19) # 16-bit general reg (shadow) + + # duplex/packed fields - left side (register attachments are somewhat assumed) + + rdd3l = (16,18) # 64-bit general reg + rdd3l_ = (16,18) # 64-bit general reg (shadow) + rtt3l = (16,18) # 64-bit general reg + rd4l = (16,19) # 32-bit general reg + rd4l_ = (16,19) # 32-bit general reg (shadow) + rt4l = (16,19) # 32-bit general reg + rs4l = (20,23) # 32-bit general reg + + # duplex/packed fields - right side (register attachments are somewhat assumed) + + rdd3r = (0,2) # 64-bit general reg + rdd3r_ = (0,2) # 64-bit general reg + rtt3r = (0,2) # 64-bit general reg + rd4r = (0,3) # 32-bit general reg + rd4r_ = (0,3) # 32-bit general reg (shadow) + rs4r = (4,7) # 32-bit general reg + rt4r = (0,3) # 32-bit general reg +; + +# +# Attach statements +# + +# 64-bit reg selector is 5-bits - the LS bit must always be 0 (even reg) + +attach variables [ rdd5 rxx5 rss5 rtt5 ruu5 rdd0812 ] + [ R1R0 _ R3R2 _ R5R4 _ R7R6 _ R9R8 _ R11R10 _ R13R12 _ R15R14 _ + R17R16 _ R19R18 _ R21R20 _ R23R22 _ R25R24 _ R27R26 _ R29R28 _ R31R30 _ ]; + +attach variables [ rdd5_ rxx5_ rdd0812_ ] + [ R1R0_ _ R3R2_ _ R5R4_ _ R7R6_ _ R9R8_ _ R11R10_ _ R13R12_ _ R15R14_ _ + R17R16_ _ R19R18_ _ R21R20_ _ R23R22_ _ R25R24_ _ R27R26_ _ R29R28_ _ R31R30_ _]; + +# Access to high word reg of specified long word rtt5, rt5 can be used for low word reg +attach variables [ rtt5h rss5h ] + [ R1 _ R3 _ R5 _ R7 _ R9 _ R11 _ R13 _ R15 _ R17 _ R19 _ R21 _ R23 _ R25 _ R27 _ SP _ LR _ ]; + +# Access to high word reg of specified long word rdd5, rd5 can be used for low word reg +attach variables [ rdd5h ] + [ R1 _ R3 _ R5 _ R7 _ + R9 _ R11 _ R13 _ R15 _ + R17 _ R19 _ R21 _ R23 _ + R25 _ R27 _ SP _ LR _ ]; +attach variables [ rdd5h_ ] + [ R1.new _ R3.new _ R5.new _ R7.new _ + R9.new _ R11.new _ R13.new _ R15.new _ + R17.new _ R19.new _ R21.new _ R23.new _ + R25.new _ R27.new _ SP.new _ LR.new _ ]; + +attach variables [ rdd3l rtt3l rdd3r rtt3r ] + [ R1R0 R3R2 R5R4 R7R6 R17R16 R19R18 R21R20 R23R22 ]; +attach variables [ rdd3l_ rdd3r_ ] + [ R1R0_ R3R2_ R5R4_ R7R6_ R17R16_ R19R18_ R21R20_ R23R22_ ]; + +attach variables [ rd5 rd0812 rs5 rt5 ru5 rx5 rf5 nreg ] + [ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 SP FP LR ]; + +attach variables [ rt1618 ] + [ R0 R1 R2 R3 R4 R5 R6 R7 ]; + +attach variables [ rd5_ rd0812_ rx5_ rf5_ nreg_ ] + [ R0.new R1.new R2.new R3.new R4.new R5.new R6.new R7.new + R8.new R9.new R10.new R11.new R12.new R13.new R14.new R15.new + R16.new R17.new R18.new R19.new R20.new R21.new R22.new R23.new + R24.new R25.new R26.new R27.new R28.new SP.new FP.new LR.new ]; + +attach variables [ rx5H rs5H rt5H ru5H ] + [ R0.H R1.H R2.H R3.H R4.H R5.H R6.H R7.H + R8.H R9.H R10.H R11.H R12.H R13.H R14.H R15.H + R16.H R17.H R18.H R19.H R20.H R21.H R22.H R23.H + R24.H R25.H R26.H R27.H R28.H R29.H R30.H R31.H ]; + +attach variables [ rx5H_ ] + [ R0.H_ R1.H_ R2.H_ R3.H_ R4.H_ R5.H_ R6.H_ R7.H_ + R8.H_ R9.H_ R10.H_ R11.H_ R12.H_ R13.H_ R14.H_ R15.H_ + R16.H_ R17.H_ R18.H_ R19.H_ R20.H_ R21.H_ R22.H_ R23.H_ + R24.H_ R25.H_ R26.H_ R27.H_ R28.H_ R29.H_ R30.H_ R31.H_ ]; + +attach variables [ rx5L rs5L rt5L ru5L ] + [ R0.L R1.L R2.L R3.L R4.L R5.L R6.L R7.L + R8.L R9.L R10.L R11.L R12.L R13.L R14.L R15.L + R16.L R17.L R18.L R19.L R20.L R21.L R22.L R23.L + R24.L R25.L R26.L R27.L R28.L R29.L R30.L R31.L ]; + +attach variables [ rx5L_ ] + [ R0.L_ R1.L_ R2.L_ R3.L_ R4.L_ R5.L_ R6.L_ R7.L_ + R8.L_ R9.L_ R10.L_ R11.L_ R12.L_ R13.L_ R14.L_ R15.L_ + R16.L_ R17.L_ R18.L_ R19.L_ R20.L_ R21.L_ R22.L_ R23.L_ + R24.L_ R25.L_ R26.L_ R27.L_ R28.L_ R29.L_ R30.L_ R31.L_ ]; + +attach variables [ rs4p rt4p rs4l rt4l rs4r rd4l rd4r rt4r rd0811 rd1619 ] + [ R0 R1 R2 R3 R4 R5 R6 R7 R16 R17 R18 R19 R20 R21 R22 R23]; +attach variables [ rd4l_ rd4r_ rd0811_ rd1619_ ] + [ R0.new R1.new R2.new R3.new R4.new R5.new R6.new R7.new + R16.new R17.new R18.new R19.new R20.new R21.new R22.new R23.new]; + +attach variables [ cd5 cs5 ] + [ SA0 LC0 SA1 LC1 P3P0 C5 M0 M1 + USR PC UGP GP CS0 CS1 UPCYCLELO UPCYCLEHI + FRAMELIMIT FRAMEKEY PKTCOUNTLO PKTCOUNTHI C20 C21 C22 C23 + C24 C25 C26 C27 C28 C29 UTIMERLO UTIMERHI ]; + +attach variables [ cd5_ ] + [ SA0_ LC0_ SA1_ LC1_ P3P0_ C5_ M0_ M1_ + USR_ PC UGP_ GP_ CS0_ CS1_ UPCYCLELO_ UPCYCLEHI_ + FRAMELIMIT_ FRAMEKEY_ PKTCOUNTLO_ PKTCOUNTHI_ C20_ C21_ C22_ C23_ + C24_ C25_ C26_ C27_ C28_ C29_ UTIMERLO_ UTIMERHI_ ]; + +attach variables [ css5 cdd5 ] + [ C1C0 _ C3C2 _ C5C4 _ C7C6 _ + C9C8 _ C11C10 _ C13C12 _ UPCYCLE _ + C17C16 _ PKTCOUNT _ C21C20 _ C23C22 _ + C25C24 _ C27C26 _ C29C28 _ UTIMER _ ]; + +attach variables [ cdd5_ ] + [ C1C0_ _ C3C2_ _ C5C4_ _ C7C6_ _ + C9C8_ _ C11C10_ _ C13C12_ _ UPCYCLE_ _ + C17C16_ _ PKTCOUNT_ _ C21C20_ _ C23C22_ _ + C25C24_ _ C27C26_ _ C29C28_ _ UTIMER_ _ ]; + +attach variables [ mu ] [ M0 M1 ]; + +attach variables [ pu12 pu25 ] [ P0 P1 ]; +attach variables [ pu12_ pu25_ ] [ P0.new P1.new ]; +attach names [ pu12name pu25name ] [ "P0" "P1" ]; + +attach variables [ pu0001 pu0506 pu0607 pu0809 pu1112 pu0910 pu1617 pu2122 pu2324 ] [ P0 P1 P2 P3 ]; +attach variables [ pu0001_ pu0506_ pu0809_ pu0910_ pu1112_ pu2122_ ] [ P0.new P1.new P2.new P3.new ]; +attach names [ pu0001name pu0506name pu0809name pu1112name pu0910name pu2122name ] [ "P0" "P1" "P2" "P3" ]; + +attach variables [ qv0001 qv0506 qv0809 qv1112 qv2223 ] [ Q0 Q1 Q2 Q3 ]; + +attach variables [ ss6 sd6 ] # TODO: Shadow reg's not implemented for system regs + [ S0 S1 S2 S3 S4 S5 S6 S7 + S8 S9 S10 S11 S12 S13 S14 S15 + S16 S17 S18 S19 S20 S21 S22 S23 + S24 S25 S26 S27 S28 S29 S30 S31 + S32 S33 S34 S35 S36 S37 S38 S39 + S40 S41 S42 S43 S44 S45 S46 S47 + S48 S49 S50 S51 S52 S53 S54 S55 + S56 S57 S58 S59 S60 S61 S62 S63 ]; + +attach variables [ sss6 sdd6 ] # TODO: Shadow reg's not implemented for system regs + [ S1S0 _ S3S2 _ S5S4 _ S7S6 _ + S9S8 _ S11S10 _ S13S12 _ S15S14 _ + S17S16 _ S19S18 _ S21S20 _ S23S22 _ + S25S24 _ S27S26 _ S29S28 _ S31S30 _ + S33S32 _ S35S34 _ S37S36 _ S39S38 _ + S41S40 _ S43S42 _ S45S44 _ S47S46 _ + S49S48 _ S51S50 _ S53S52 _ S55S54 _ + S57S56 _ S59S58 _ S61S60 _ S63S62 _ ]; + +attach variables [ gss5 gdd5 ] [ # TODO: Shadow reg's not implemented for guest regs + G1G0 _ G3G2 _ G5G4 _ G7G6 _ + G9G8 _ G11G10 _ G13G12 _ G15G14 _ + G17G16 _ G19G18 _ G21G20 _ G23G22 _ + G25G24 _ G27G26 _ G29G28 _ G31G30 _ ]; + +attach variables [ gs5 gd5 ] [ # TODO: Shadow reg's not implemented for guest regs + G0 G1 G2 G3 G4 G5 G6 G7 + G8 G9 G10 G11 G12 G13 G14 G15 + G16 G17 G18 G19 G20 G21 G22 G23 + G24 G25 G26 G27 G28 G29 G30 G31 ]; + +# +# HVX vector registers +# + +# NOTE: HVX Vector register access size and signedness are generally indicated by a +# suffix in assembly source, e.g., .b .ub .h .uh .w.uw +# We currently do not name lane-access registers and rely on lane access sizes as +# defined by the pspec. + +# double-vector reg selector is 5-bits - the LS bit must always be 0 (even reg) + +attach variables [ vdd5 vss5 vuu5 vvv5 ] + [ V1V0 _ V3V2 _ V5V4 _ V7V6 _ V9V8 _ V11V10 _ V13V12 _ V15V14 _ + V17V16 _ V19V18 _ V21V20 _ V23V22 _ V25V24 _ V27V26 _ V29V28 _ V31V30 _ ]; + +attach variables [ vd5 vs5 vu5 vv5 vz5 vnreg ] + [ V0 V1 V2 V3 V4 V5 V6 V7 + V8 V9 V10 V11 V12 V13 V14 V15 + V16 V17 V18 V19 V20 V21 V22 V23 + V24 V25 V26 V27 V28 V29 V30 V31 ]; + +attach variables [ vdd5_ ] # TODO: Removed vuu5_ vvv5_ + [ V1V0_ _ V3V2_ _ V5V4_ _ V7V6_ _ V9V8_ _ V11V10_ _ V13V12_ _ V15V14_ _ + V17V16_ _ V19V18_ _ V21V20_ _ V23V22_ _ V25V24_ _ V27V26_ _ V29V28_ _ V31V30_ _ ]; + +attach variables [ vd5_ vnreg_ ] # TODO: Removed vs5_ vu5_ vv5_ vz5_ + [ V0.new V1.new V2.new V3.new V4.new V5.new V6.new V7.new + V8.new V9.new V10.new V11.new V12.new V13.new V14.new V15.new + V16.new V17.new V18.new V19.new V20.new V21.new V22.new V23.new + V24.new V25.new V26.new V27.new V28.new V29.new V30.new V31.new ]; + +# +# Ns8 .new scalar register support +# + +# The assigned register must be written to the nreg slot which corresponds to +# the packet slot minus the xreg value. The xreg value is incremented +# anytime an immext instruction is encountered within the packet. +# Assumptions: +# 1. Packet contains 4 instruction slots +# 2. Use of Rx.new will always be the last instruction within a packet +# 3. At most 2 immext instructions may exist in packet +# 4. Two adjacent immext instructions not allowed +# 5. left/right EE instructions are of no concern (they are always last in packet) +# 6. 64-bit scalar register destination is not allowed but we do not prevent it +# 7. New value store context may be shared for scalar and vector register use since +# only one or the other will be forwarded by any one instruction. + +# Set appropriate nreg based upon packetOffset less number of preceeding immext ops +# Cases have been optimized based upon valid placement of immext within packet + +# Set appropriate new value store index 'nreg#' using default destination register field rd5_ +# This new value store subconstructor can be shared with vd5_ and vdd5_, which all use the +# same token bit range (00,04). +SetNRegRd5: is packetOffset=0 & rd5_ [ nreg0=rd5_; ] { } +SetNRegRd5: is packetOffset=1 & rd5_ [ nreg1=rd5_; ] { } +SetNRegRd5: is packetOffset=1 & xreg=1 & rd5_ [ nreg0=rd5_; ] { } +SetNRegRd5: is packetOffset=2 & rd5_ [ nreg2=rd5_; ] { } +SetNRegRd5: is packetOffset=2 & xreg=1 & rd5_ [ nreg1=rd5_; ] { } +SetNRegRd5: is packetOffset=3 { } # no need to retain new value register for last instruction + +# Set appropriate nreg using rx5_ +SetNRegRx5: is packetOffset=0 & rx5_ [ nreg0=rx5_; ] { } +SetNRegRx5: is packetOffset=1 & rx5_ [ nreg1=rx5_; ] { } +SetNRegRx5: is packetOffset=1 & xreg=1 & rx5_ [ nreg0=rx5_; ] { } +SetNRegRx5: is packetOffset=2 & rx5_ [ nreg2=rx5_; ] { } +SetNRegRx5: is packetOffset=2 & xreg=1 & rx5_ [ nreg1=rx5_; ] { } +SetNRegRx5: is packetOffset=3 { } # no need to retain new value register for last instruction + +# Set appropriate nreg using rd0812_ +SetNRegRd0812: is packetOffset=0 & rd0812_ [ nreg0=rd0812_; ] { } +SetNRegRd0812: is packetOffset=1 & rd0812_ [ nreg1=rd0812_; ] { } +SetNRegRd0812: is packetOffset=1 & xreg=1 & rd0812_ [ nreg0=rd0812_; ] { } +SetNRegRd0812: is packetOffset=2 & rd0812_ [ nreg2=rd0812_; ] { } +SetNRegRd0812: is packetOffset=2 & xreg=1 & rd0812_ [ nreg1=rd0812_; ] { } +SetNRegRd0812: is packetOffset=3 { } # no need to retain new value register for last instruction + +# TODO: If needed, add SetNReg for: Re32 Rx32 Rd16 Re16 Rx16 Ry16 Rd8 + +# Compute new value store index context 'nregr' based upon 'nregSlot' and appropriate 'nreg#' context. +# This subcontructor may be shared by both Ns8 (new scalar reg) and Os8 (new vector reg) decode since +# they share the underlying new value index 'nreg#' context storage. +# NOTE: The nregSlot must preceed the current packetOffset +GetNReg: is nregSlot=0 & (packetOffset0=1 | packetOffset1=1) & nreg0 [ nregr = nreg0; ] { } +GetNReg: is nregSlot=1 & packetOffset1=1 & nreg1 [ nregr = nreg1; ] { } +GetNReg: is nregSlot=2 & packetOffset=3 & nreg2 [ nregr = nreg2; ] { } + +# Decode 3-bit encoded Ns8 .new register, setting nregSlot (lsb of 3-bit nreg field ignored) +# and return appropriate nreg (R0.new - R31.new). The nregSlot must refer to a previous +# instruction slot within the same execute packet. +# +# NOTE: Since the non-shadow register location is returned (while .new is displayed) is is assumed +# that the location will not be read until the <> phase or later + +Nreg1618: nreg_ is GetNReg & nreg_ & nreg & nreg_1618 [ nregSlot = packetOffset - xreg - (nreg_1618 >> 1); ] { export nreg; } +Nreg0810: nreg_ is GetNReg & nreg_ & nreg & nreg_0810 [ nregSlot = packetOffset - xreg - (nreg_0810 >> 1); ] { export nreg; } +Nreg0002: nreg_ is GetNReg & nreg_ & nreg & nreg_0002 [ nregSlot = packetOffset - xreg - (nreg_0002 >> 1); ] { export nreg; } + +# +# HVX Os8 .new vector register support +# Employs the same strategy as the Ns8 above with some context fields sharing use for both Os8 and Ns8 +# + +# NOTE: More investigation is needed for the correct 3-bit Os8 encoding. Some information suggests +# that bits identify the specific pipeline which produced the vector result and is not based on +# packetOffset as originally believed. + +# Set appropriate new value index 'nregr' using vd5_ or vdd5_ (same as rd5_ field) +SetVNRegVd5: is SetNRegRd5 { } + +# Compute Os8 new value store index 'nregr' based upon 'nregSlot' when Os8 lsb is '0'. +# NOTE: We can share GetNReg use with Ns8 decode for this case. +GetVNReg: is GetNReg { } + +# Compute alternate Os8 new value store index 'nregr' based upon 'nregSlot' when Os8 lsb is '1'. +# This will produce a new value store index that corresponds to the other vector register within +# the same pair (e.g., if vnreg# indicates V0 index, V1 index will be use by inverting lsb for 'nregr') +# NOTE: The nregSlot must preceed the current packetOffset +GetVNAltReg: is nregSlot=0 & (packetOffset0=1 | packetOffset1=1) & nreg0 [ nregr = nreg0 ^ 1; ] { } +GetVNAltReg: is nregSlot=1 & packetOffset1=1 & nreg1 [ nregr = nreg1 ^ 1; ] { } +GetVNAltReg: is nregSlot=2 & packetOffset=3 & nreg2 [ nregr = nreg2 ^ 1; ] { } + +# Decode 3-bit encoded Os8 .new vector register, setting nregSlot (lsb of 3-bit nreg field ignored) +# and return appropriate vnreg (V0.new - V31.new). The nregSlot must refer to a previous +# instruction slot within the same execute packet. +# +# NOTE: Since the non-shadow register location is returned (while .new is displayed) is is assumed +# that the location will not be read until the <> phase or later + +# The lsb of 3-bit Os8 field indicates an alternate register. It appears to have two cases: +# 1) register pair: if '1' .new corresponds to the other register in the aligned pair (GetVNAltReg) +# 2) dual independent registers: Vx(0), Vy(1) use case (not yet supported) + +VNreg0002: vnreg_ is GetVNReg & vnreg_ & vnreg & nreg_0002lsb=0 & nreg_0002 [ nregSlot = packetOffset - xreg - (nreg_0002 >> 1); ] { export vnreg; } +VNreg0002: vnreg_ is GetVNAltReg & vnreg_ & vnreg & nreg_0002lsb=1 & nreg_0002 [ nregSlot = packetOffset - xreg - (nreg_0002 >> 1); ] { export vnreg; } + +# +# General Instruction Set parse and execute packet and crossbuild constructors +# +@include "hexagon.sinc" + +# +# Packed/Duplex 'EE' Instruction Set +# 29..31 Instruction Class +# 14..15 PP parse bits +# 00..12 Right sub-instruction (Slot-0) +# 16..28 Left sub-instruction (Slot-1) +# +@include "hexagon_left.sinc" +@include "hexagon_right.sinc" + +# +# Floating Point Instruction Set +# +@include "hexagon_float.sinc" + +# +# Vector Instruction Set (HVX extension) +# +@include "hexagon_hvx.sinc" + diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_float.sinc b/pypcode/processors/Hexagon/data/languages/hexagon_float.sinc new file mode 100644 index 00000000..de104c13 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon_float.sinc @@ -0,0 +1,872 @@ +# +# Floating Point Instructions +# Added with V5x: +# convert_sf2d, convert_sf2df, convert_sf2ud, convert_sf2uw, convert_sf2w +# convert_d2sf, convert_ud2sf, convert_uw2sf, convert_w2sf +# convert_df2d, convert_df2sf, convert_df2ud, convert_df2uw, convert_df2w +# convert_d2df, convert_ud2df, convert_uw2df, convert_w2df +# sfadd, sfclass, sfcmp.*, sffixupd, sffixupn, sffixupr, sfmake, sfmax, sfmin, sfmpy, sfsub +# dfclass, dfcmp.*, dfmake +# Added with V65: +# sfinvsqrta, sfrecipa +# Added with V66: +# dfadd, dfsub +# Added with V67: +# dfmax, dfmin, dfmpyfix, dfmpyhh, dfmpylh, dfmpyll +# +# See bottom of this file for additional instruction patterns found within QEMU source code. +# Use of the undocumented double-precission floating instructions are disabled by default +# due to conflicts with V6 instructions. The option ADD_DP_OPS must be defined to +# to enable the use of these undocumented instructions which will disable the use of +# corresponding V6 instructions which conflict. +# + +define pcodeop convertFloat2UInt; +define pcodeop chopFloat2UInt; + +# +# V5x Floating Point Instructions +# + +# (v5,8) convert_sf2d -- "Rdd = convert_sf2d ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 1 0 0 d d d d d + +:convert_sf2d Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=4 & rs5 & Rdd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + Rdd5 = trunc(rs5); + build EndPacket; +} + +# (v5,8) convert_sf2d -- "Rdd = convert_sf2d ( Rs ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 1 1 0 d d d d d + +:convert_sf2d^":chop" Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=6 & rs5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + Rdd5 = trunc(rs5); + build EndPacket; +} + +# (v5,8) convert_sf2df -- "Rdd = convert_sf2df ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_sf2df Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=0 & rs5 & Rdd5 & $(END_PACKET) { + Rdd5 = float2float(rs5); + build EndPacket; +} + +# (v5,8) convert_sf2ud -- "Rdd = convert_sf2ud ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 1 1 d d d d d + +:convert_sf2ud Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=3 & rs5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:4 = float2float(rs5); + Rdd5 = convertFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_sf2ud -- "Rdd = convert_sf2ud ( Rs ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 1 0 1 d d d d d + +:convert_sf2ud^":chop" Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=5 & rs5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:4 = float2float(rs5); + Rdd5 = chopFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_sf2uw -- "Rd = convert_sf2uw ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 0 1 1 s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_sf2uw Rd5,rs5 EndPacket is iclass=8 & op2127=0x5b & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + float:4 = float2float(rs5); + Rd5 = convertFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_sf2uw -- "Rd = convert_sf2uw ( Rs ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 0 1 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_sf2uw^":chop" Rd5,rs5 EndPacket is iclass=8 & op2127=0x5b & op0813=0 & op0507=1 & rs5 & Rd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:4 = float2float(rs5); + Rd5 = chopFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_sf2w -- "Rd = convert_sf2w ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 0 0 s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_sf2w Rd5,rs5 EndPacket is iclass=8 & op2127=0x5c & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + Rd5 = trunc(rs5); + build EndPacket; +} + +# (v5,8) convert_sf2w -- "Rd = convert_sf2w ( Rs ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 0 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_sf2w^":chop" Rd5,rs5 EndPacket is iclass=8 & op2127=0x5c & op0813=0 & op0507=1 & rs5 & Rd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + Rd5 = trunc(rs5); + build EndPacket; +} + +# (v5,8) convert_d2sf -- "Rd = convert_d2sf ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_d2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = int2float(rss5); + build EndPacket; +} + +# (v5,8) convert_ud2sf -- "Rd = convert_ud2sf ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +# TODO: we do not have an unsigned int2float - could zext but not with 8-byte reg if we want to emulate +define pcodeop convertUInt2float; + +:convert_ud2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x41 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + tmp:9 = zext(rss5); + Rd5 = int2float(tmp); + build EndPacket; +} + +# (v5,8) convert_uw2sf -- "Rd = convert_uw2sf ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 0 0 1 s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_uw2sf Rd5,rs5 EndPacket is iclass=8 & op2127=0x59 & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + tmp:8 = zext(rs5); + Rd5 = int2float(tmp); + build EndPacket; +} + +# (v5,8) convert_w2sf -- "Rd = convert_w2sf ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 0 1 0 s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_w2sf Rd5,rs5 EndPacket is iclass=8 & op2127=0x5a & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = int2float(rs5); + build EndPacket; +} + +# (v5,8) convert_df2d -- "Rdd = convert_df2d ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 0 0 d d d d d + +:convert_df2d Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=0 & rss5 & Rdd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + Rdd5 = trunc(rss5); + build EndPacket; +} + +# (v5,8) convert_df2d -- "Rdd = convert_df2d ( Rss ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 1 1 0 d d d d d + +:convert_df2d^":chop" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=6 & rss5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + Rdd5 = trunc(rss5); + build EndPacket; +} + +# (v5,8) convert_df2sf -- "Rd = convert_df2sf ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = float2float(rss5); + build EndPacket; +} + +# (v5,8) convert_df2ud -- "Rdd = convert_df2ud ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 0 1 d d d d d + +:convert_df2ud Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=1 & rss5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:8 = float2float(rss5); + Rdd5 = convertFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_df2ud -- "Rdd = convert_df2ud ( Rss ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 1 1 1 d d d d d + +:convert_df2ud^":chop" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=7 & rss5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:8 = float2float(rss5); + Rdd5 = chopFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_df2uw -- "Rd = convert_df2uw ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2uw Rd5,rss5 EndPacket is iclass=8 & op2127=0x43 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + float:8 = float2float(rss5); + Rd5 = convertFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_df2uw -- "Rd = convert_df2uw ( Rss ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2uw^":chop" Rd5,rss5 EndPacket is iclass=8 & op2127=0x45 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:8 = float2float(rss5); + Rd5 = chopFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_df2w -- "Rd = convert_df2w ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2w Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + Rd5 = trunc(rss5); + build EndPacket; +} + +# (v5,8) convert_df2w -- "Rd = convert_df2w ( Rss ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2w^":chop" Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + Rd5 = trunc(rss5); + build EndPacket; +} + +# (v5,8) convert_d2df -- "Rdd = convert_d2df ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 1 1 d d d d d + +:convert_d2df Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=3 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = int2float(rss5); + build EndPacket; +} + +# (v5,8) convert_ud2df -- "Rdd = convert_ud2df ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 1 0 d d d d d + +:convert_ud2df Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=2 & rss5 & Rdd5 & $(END_PACKET) { + tmp:9 = zext(rss5); + Rdd5 = int2float(tmp); + build EndPacket; +} + +# (v5,8) convert_uw2df -- "Rdd = convert_uw2df ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_uw2df Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=1 & rs5 & Rdd5 & $(END_PACKET) { + tmp:9 = zext(rs5); + Rdd5 = int2float(tmp); + build EndPacket; +} + +# (v5,8) convert_w2df -- "Rdd = convert_w2df ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 1 0 d d d d d + +:convert_w2df Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=2 & rs5 & Rdd5 & $(END_PACKET) { + Rdd5 = int2float(rs5); + build EndPacket; +} + +# (v5,14) sfadd -- "Rd = sfadd ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:sfadd Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x58 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = rs5 f+ rt5; + build EndPacket; +} + +# (v5,8) sfclass -- "Pd = sfclass ( Rs, #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 1 1 1 s s s s s P P 0 i i i i i + + + + + + d d + +define pcodeop isClassifiedFloat; + +:sfclass Pd2,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x2f & op13=0 & op0207=0 & Uimm8_0812 & rs5 & Pd2 & $(END_PACKET) { + float:4 = float2float(rs5); + bool:1 = isClassifiedFloat(float,Uimm8_0812); + Pd2 = Pd2 & ((bool != 0) * 0xff); + build EndPacket; +} + +# (v5,12) sfcmp.ge -- "Pd = sfcmp.ge ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 0 0 0 + + + d d + +:sfcmp.ge Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=0 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rt5 f<= rs5) * 0xff); + build EndPacket; +} + +# (v5,12) sfcmp.uo -- "Pd = sfcmp.uo ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 0 0 1 + + + d d + +:sfcmp.uo Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=1 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + float1:4 = float2float(rs5); + float2:4 = float2float(rt5); + bool:1 = nan(float1) || nan(float2); + Pd2 = Pd2 & ((bool != 0) * 0xff); + build EndPacket; +} + +# (v5,12) sfcmp.eq -- "Pd = sfcmp.eq ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 0 1 1 + + + d d + +:sfcmp.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=3 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rt5 f== rs5) * 0xff); + build EndPacket; +} + +# (v5,12) sfcmp.gt -- "Pd = sfcmp.gt ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 1 0 0 + + + d d + +:sfcmp.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=4 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rs5 f> rt5) * 0xff); + build EndPacket; +} + +# (v5,14) sffixupd -- "Rd = sffixupd ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d +define pcodeop sffixupd; +:sffixupd Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5e & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = sffixupd(rs5, rt5); + build EndPacket; +} + +# (v5,14) sffixupn -- "Rd = sffixupn ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d +define pcodeop sffixupn; +:sffixupn Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5e & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = sffixupn(rs5, rt5); + build EndPacket; +} + +# (v5,8) sffixupr -- "Rd = sffixupr ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 0 1 s s s s s P P + + + + + + 0 0 0 d d d d d +define pcodeop sffixupr; +:sffixupr Rd5,rs5 EndPacket is iclass=8 & op2127=0x5d & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = sffixupr(rs5); + build EndPacket; +} + +# (v5,13) sfmake -- "Rd = sfmake ( #u10 ) :neg" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 1 0 0 1 i + + + + + P P i i i i i i i i i d d d d d + +:sfmake^":neg" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x19 & op1620=0 & Uimm16_21_0513 & Rd5 & $(END_PACKET) { + Rd5 = int2float(-Uimm16_21_0513); # TODO: assumed functionality + build EndPacket; +} + +# (v5,13) sfmake -- "Rd = sfmake ( #u10 ) :pos" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 1 0 0 0 i + + + + + P P i i i i i i i i i d d d d d + +:sfmake^":pos" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x18 & op1620=0 & Uimm16_21_0513 & Rd5 & $(END_PACKET) { + Rd5 = int2float(Uimm16_21_0513); # TODO: assumed functionality + build EndPacket; +} + +# (v5,14) sfmax -- "Rd = sfmax ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:sfmax Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5c & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + if (nan(rs5) || (rs5 f< rt5)) goto ; + Rd5 = rs5; + goto ; + + Rd5 = rt5; + + build EndPacket; +} + +# (v5,14) sfmin -- "Rd = sfmin ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d + +:sfmin Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5c & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + if (nan(rs5) || (rt5 f< rs5)) goto ; + Rd5 = rs5; + goto ; + + Rd5 = rt5; + + build EndPacket; +} + +# (v5,14) sfmpy -- "Rd = sfmpy ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:sfmpy Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5a & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = rs5 f* rt5; + build EndPacket; +} + +# (v5,14) sfmpy+= -- "Rx += sfmpy ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 0 0 x x x x x + +:sfmpy+= Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x78 & op13=0 & op0507=4 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 f+ (rs5 f* rt5); + build EndPacket; +} + +# (v5,14) sfmpy+= -- "Rx += sfmpy ( Rs, Rt, Pu ) :scale" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P 0 t t t t t 1 u u x x x x x + +:sfmpy+=^":scale" Rd5,rs5,rt5,pu0506 EndPacket is iclass=14 & op2127=0x7b & op13=0 & op7=1 & pu0506 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = multiplyAddScale(Rd5, rs5, rt5); + build EndPacket; +} + +# (v5,14) sfmpy-= -- "Rx -= sfmpy ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 0 1 x x x x x + +:sfmpy-= Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x78 & op13=0 & op0507=5 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 f- (rs5 f* rt5); + build EndPacket; +} + + + +# (v5,14) sfmpy+= -- "Rx += sfmpy ( Rs, Rt ) :lib" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x + +:sfmpy+=^":lib" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x78 & op13=0 & op0507=6 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 f+ (rs5 f* rt5); + build EndPacket; +} + +# (v5,14) sfmpy-= -- "Rx -= sfmpy ( Rs, Rt ) :lib" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x + +:sfmpy-=^":lib" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x78 & op13=0 & op0507=7 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 f- (rs5 f* rt5); + build EndPacket; +} + + + + +# (v5,14) sfsub -- "Rd = sfsub ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d + +:sfsub Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x58 & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = rs5 f- rt5; + build EndPacket; +} + +# (v5,13) dfclass -- "Pd = dfclass ( Rss, #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 1 0 0 s s s s s P P + 0 0 0 i i i i i 1 0 + d d + +:dfclass Pd2,rss5,Uimm8_0509 EndPacket is iclass=13 & op2127=0x64 & op1013=0 & op0204=4 & Uimm8_0509 & rss5 & Pd2 & $(END_PACKET) { + float:8 = float2float(rss5); + result:1 = isClassifiedFloat(float,Uimm8_0509); + Pd2 = Pd2 & result; + build EndPacket; +} + +# (v5,13) dfcmp.eq -- "Pd = dfcmp.eq ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 0 0 + + + d d + +:dfcmp.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=0 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rtt5 f== rss5) * 0xff); + build EndPacket; +} + +# (v5,13) dfcmp.gt -- "Pd = dfcmp.gt ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 0 1 + + + d d + +:dfcmp.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=1 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rss5 f> rtt5) * 0xff); + build EndPacket; +} + +# (v5,13) dfcmp.ge -- "Pd = dfcmp.ge ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 1 0 + + + d d + +:dfcmp.ge Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=2 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rtt5 f<= rss5) * 0xff); + build EndPacket; +} + +# (v5,13) dfcmp.uo -- "Pd = dfcmp.uo ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 1 1 + + + d d + +:dfcmp.uo Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=3 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + float1:8 = float2float(rss5); + float2:8 = float2float(rtt5); + bool:1 = nan(float1) || nan(float2); + Pd2 = Pd2 & ((bool != 0) * 0xff); + build EndPacket; +} + +# (v5,13) dfmake -- "Rdd = dfmake ( #u10 ) :neg" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 0 1 0 1 i + + + + + P P i i i i i i i i i d d d d d + +:dfmake^":neg" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x25 & op1620=0 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) { + Rdd5 = int2float(-Uimm16_21_0513); # TODO: assumed functionality + build EndPacket; +} + +# (v5,13) dfmake -- "Rdd = dfmake ( #u10 ) :pos" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 0 1 0 0 i + + + + + P P i i i i i i i i i d d d d d + +:dfmake^":pos" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x24 & op1620=0 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) { + Rdd5 = int2float(Uimm16_21_0513); # TODO: assumed functionality + build EndPacket; +} + +# +# V65 Floating Point Instructions +# + +# (v65,8) sfinvsqrta -- "Rd,Pe = sfinvsqrta ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 1 1 s s s s s P P + + + + + + 0 e e d d d d d + +:sfinvsqrta Rd5,pu0506,rs5 EndPacket is iclass=8 & op2127=0x5f & op0813=0 & op7=0 & pu0506_ & pu0506 & rs5 & Rd5 & $(END_PACKET) +unimpl + +# (v65,14) sfrecipa -- "Rd,Pe = sfrecipa ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 1 1 s s s s s P P 0 t t t t t 1 e e d d d d d + +:sfrecipa Rd5,Pd0506,rs5,rt5 EndPacket is iclass=14 & op2127=0x5f & op13=0 & op7=1 & Pd0506 & rs5 & rt5 & Rd5 & $(END_PACKET) { + src1:4 = rs5; + src2:4 = rt5; + Rd5 = reciprocal(src1, src2); + Pd0506 = Pd0506 & reciprocalAdjust(src1, src2); + build EndPacket; +} + +# +# V66 Floating Point Instructions +# + +# (v66,14) dfadd -- "Rdd = dfadd ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +:dfadd Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = rss5 f+ rtt5; + build EndPacket; +} + +# (v66,14) dfsub -- "Rdd = dfsub ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +:dfsub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = rss5 f- rtt5; + build EndPacket; +} + +# +# V67 Floating Point Instructions +# + +# (v67,14) dfmax -- "Rdd = dfmax ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +:dfmax Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + if (nan(rss5) || (rss5 f< rtt5)) goto ; + Rdd5 = rss5; + goto ; + + Rdd5 = rtt5; + + build EndPacket; +} + +# (v67,14) dfmin -- "Rdd = dfmin ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +:dfmin Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + if (nan(rss5) || (rtt5 f< rss5)) goto ; + Rdd5 = rss5; + goto ; + + Rdd5 = rtt5; + + build EndPacket; +} + +# (v5,14) c -- "Rdd = dfmpyfix ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +define pcodeop dfmpyfix; +:dfmpyfix Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = dfmpyfix(rss5, rtt5); + build EndPacket; +} + +@ifndef ADD_DP_OPS + +# (v67,14) dfmpyhh+= -- "Rxx += dfmpyhh ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +define pcodeop dfmpyhh; +:dfmpyhh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = dfmpyhh(rdd5, rss5, rtt5); + build EndPacket; +} + +# (v67,14) dfmpylh+= -- "Rxx += dfmpylh ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +define pcodeop dfmpylh; +:dfmpylh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = dfmpylh(rdd5, rss5, rtt5); + build EndPacket; +} + +# (v5,14) dfmpyll -- "Rdd = dfmpyll ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +define pcodeop dfmpyll; +:dfmpyll Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = dfmpyll(rss5, rtt5); + build EndPacket; +} + +@endif # not ADD_DP_OPS + + +############################################################################################################# +# +# WARNING: The following instructions were discovered within various QEMU revisions not associated with a +# specific processor version that we have been able to identify. These instructions are for experimental +# use only and may be intended for QEMU development testing only. +# +############################################################################################################# + +@ifdef ADD_DP_OPS + +# (??,14) dffixupn -- "Rdd = dffixupn ( Rss, Rtt )" +# NOTE: replaces V67 dfmpyll +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +define pcodeop dffixupn; +:dffixupn Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = dffixupn(rss5, rtt5); + build EndPacket; +} + +# (??,14) dffixupd -- "Rdd = dffixupd ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +define pcodeop dffixupd; +:dffixupd Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET){ + Rdd5 = dffixupd(rss5, rtt5); + build EndPacket; +} + +# (??,14) dfrecipa -- "Rdd,Pe = dfrecipa ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 0 e e d d d d d + +:dfrecipa Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op7=0 & pu0506_ & pu0506 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (??,14) dfmpyhh -- "Rdd += dfmpyhh ( Rss, Rtt )" +# NOTE: unexplained redfinition of V67 dfmpyhh += +# NOTE: conflicts with dfmpy+= :lib (see below) +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x +# :dfmpyhh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) +# unimpl + +# (??,14) dfmpy+= -- "Rxx += dfmpy ( Rss, Rtt )" +# NOTE: replaces V67 dfmpylh += +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +:dfmpy+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 f+ (rss5 f* rtt5); + build EndPacket; +} + +# (??,14) dfmpy-= -- "Rxx -= dfmpy ( Rss, Rtt )" +# NOTE: replaces V67 dfmpyhh += +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +:dfmpy-= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 f- (rss5 f* rtt5); + build EndPacket; +} + +# (??,14) dfmpy+= -- "Rxx += dfmpy ( Rss, Rtt ) :lib" +# NOTE: conflicts with replacement above for dfmpyhh += +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +:dfmpy+=^":lib" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 f+ (rss5 f* rtt5); + build EndPacket; +} + +# (??,14) dfmpy-= -- "Rxx -= dfmpy ( Rss, Rtt ) :lib" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +:dfmpy-=^":lib" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 f- (rss5 f* rtt5); + build EndPacket; +} + +# (??,14) dfmpy+= -- "Rxx += dfmpy ( Rss, Rtt, Pu ) :scale" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P 0 t t t t t 0 u u x x x x x + +:dfmpy+=^":scale" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op7=0 & pu0506 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = multiplyAddScale(Rdd5, rss5, rtt5); + build EndPacket; +} + +# (??,8) dffixupr -- "Rdd = dffixupr ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 1 0 0 d d d d d +define pcodeop dffixupr; +:dffixupr Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=4 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = dffixupr(rss5); + build EndPacket; +} + +# (??,8) dfinvsqrta -- "Rdd32 , Pe4 = dfinvsqrta ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 1 + + + + + 0 e e d d d d d + +:dfinvsqrta Rdd5,pu0506,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0x20 & op7=0 & pu0506_ & pu0506 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +@endif # ADD_DP_OPS diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_hvx.sinc b/pypcode/processors/Hexagon/data/languages/hexagon_hvx.sinc new file mode 100644 index 00000000..0b6ede08 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon_hvx.sinc @@ -0,0 +1,6537 @@ +# Qualcomm Hexagon HVX Instruction Set (V69) + +# NOTES: +# - HVX implemntation based upon V69 +# - HVX hardware supports either 64-byte or 128-byte vector lengths +# - Vector register write are comitted immediately - we assume assembler enforces read-after-write +# hazzards for vector registers so we do not shadow writes. + +# UNDERSTANDING / ASSUMPTIONS: +# - The term "forwarding" indicates that a vector update immediately modifies a tmp shadow +# register which may be read via a subequent .new access within the same execute packet. +# - The vector .cur update is taken to mean a non-forwarding register update that is +# committed to the register file at the end of the execute packet and not available for +# reading via a .new access. +# - All conditional instructions which are conditional are treated as non-forwarding. +# - Unless specified as a .cur update, all unconditional vector register updates are treated +# as "forwarding" and commit to register file and the end of the execute packet. + +# +# Vector Pair Operands (e.g., V0V1 ) +# + +# Vector pair unconditional write (0,4) (new vector store forwarded and comitted) +Vdd5: vdd5 is cond=0 & vdd5 & vdd5_ & SetVNRegVd5 { + export vdd5_; # must be updated unconditionally + <> + vdd5 = vdd5_; +} + +# Vector pair temporary write (0,4) (new vector store forwarded, not comitted) +Vdd5tmp: vdd5^".tmp" is vdd5_ & vdd5 & SetVNRegVd5 { + export vdd5_; # must be updated unconditionally +} + +# destination vector pair (0,4) - unconditional write-only use - see Vdd5 (used for lane naming only) +VddW_0004: Vdd5^".w" is Vdd5 { export Vdd5; } +VddH_0004: Vdd5^".h" is Vdd5 { export Vdd5; } +VddB_0004: Vdd5^".b" is Vdd5 { export Vdd5; } +VddUW_0004: Vdd5^".uw" is Vdd5 { export Vdd5; } +VddUH_0004: Vdd5^".uh" is Vdd5 { export Vdd5; } +VddUB_0004: Vdd5^".ub" is Vdd5 { export Vdd5; } +VddQF32_0004: Vdd5^".qf32" is Vdd5 { export Vdd5; } + +# source vector pair (0,4) - read-only use +Vss_0004:vdd5 is vdd5 { + tmp:$(HVX_VECTOR_PAIR_SIZE) = vdd5; + export tmp; +} + +# read-only use - see Vuu_0812 (used for lane naming only) +VssW_0004:Vss_0004^".w" is Vss_0004 { export Vss_0004; } + +# source vector pair (8,12) - read-only use +Vuu_0812:vuu5 is vuu5 { + tmp:$(HVX_VECTOR_PAIR_SIZE) = vuu5; + export tmp; +} + +# read-only use - see Vuu_0812 (used for lane naming only) +VuuW_0812:Vuu_0812^".w" is Vuu_0812 { export Vuu_0812; } +VuuH_0812:Vuu_0812^".h" is Vuu_0812 { export Vuu_0812; } +VuuB_0812:Vuu_0812^".b" is Vuu_0812 { export Vuu_0812; } +VuuUW_0812:Vuu_0812^".uw" is Vuu_0812 { export Vuu_0812; } +VuuUH_0812:Vuu_0812^".uh" is Vuu_0812 { export Vuu_0812; } +VuuUB_0812:Vuu_0812^".ub" is Vuu_0812 { export Vuu_0812; } +VuuQF32_0812: Vuu_0812^".qf32" is Vuu_0812 { export Vuu_0812; } + +# source vector pair (16,20) - read-only use +Vvv_1620:vvv5 is vvv5 { + tmp:$(HVX_VECTOR_PAIR_SIZE) = vvv5; + export tmp; +} + +# read-only use - see Vvv_1620 (used for lane naming only) +VvvW_1620:Vvv_1620^".w" is Vvv_1620 { export Vvv_1620; } +VvvH_1620:Vvv_1620^".h" is Vvv_1620 { export Vvv_1620; } +VvvB_1620:Vvv_1620^".b" is Vvv_1620 { export Vvv_1620; } +VvvUW_1620:Vvv_1620^".uw" is Vvv_1620 { export Vvv_1620; } +VvvUH_1620:Vvv_1620^".uh" is Vvv_1620 { export Vvv_1620; } +VvvUB_1620:Vvv_1620^".ub" is Vvv_1620 { export Vvv_1620; } + +# +# Single Vector Operands (e.g., V0) +# + +# Vector unconditional write (new vector store forwarded and comitted) +Vd5: vd5 is cond=0 & vd5 & vd5_ & SetVNRegVd5 { + export vd5_; # must be updated unconditionally + <> + vd5 = vd5_; +} + +# Vector .cur unconditional write (not-forwarded, unconditionally committed at end of packet) +Vd5cur: vd5^".cur" is cond=0 & vd5 & vd5_{ + export vd5_; # must be updated unconditionally + <> + vd5 = vd5_; +} +# Vector .cur conditional write (not-forwarded, conditionally committed at end of packet) +Vd5cur: vd5^".cur" is cond=1 & vd5 & vd5_ { + export vd5_; + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# Vector temporary write (new vector store forwarded, not comitted) +Vd5tmp: vd5^".tmp" is vd5 & vd5_ & SetVNRegVd5 { + export vd5_; +} + +# destination vector - unconditional write-only use - see Vd5 (used for lane naming only) +VdW_0004: Vd5^".w" is Vd5 { export Vd5; } +VdH_0004: Vd5^".h" is Vd5 { export Vd5; } +VdB_0004: Vd5^".b" is Vd5 { export Vd5; } +VdUW_0004: Vd5^".uw" is Vd5 { export Vd5; } +VdUH_0004: Vd5^".uh" is Vd5 { export Vd5; } +VdUB_0004: Vd5^".ub" is Vd5 { export Vd5; } +VdHF_0004: Vd5^".hf" is Vd5 { export Vd5; } +VdSF_0004: Vd5^".sf" is Vd5 { export Vd5; } +VdQF16_0004: Vd5^".qf16" is Vd5 { export Vd5; } +VdQF32_0004: Vd5^".qf32" is Vd5 { export Vd5; } + +# source vector (0,4) - read-only use +Vs_0004: vs5 is vs5 { + tmp:$(HVX_VECTOR_SIZE) = vs5; + export tmp; +} + +# source vector - read-only use - see Vs_0004 (used for lane naming only) +VsW_0004:Vs_0004^".w" is Vs_0004 { export Vs_0004; } +VsH_0004:Vs_0004^".h" is Vs_0004 { export Vs_0004; } +VsB_0004:Vs_0004^".b" is Vs_0004 { export Vs_0004; } + +# source vector (8,12) - read-only use +Vu_0812: vu5 is vu5 { + tmp:$(HVX_VECTOR_SIZE) = vu5; + export tmp; +} + +# source vector - read-only use - see Vu_0812 (used for lane naming only) +VuW_0812: Vu_0812^".w" is Vu_0812 { export Vu_0812; } +VuH_0812: Vu_0812^".h" is Vu_0812 { export Vu_0812; } +VuB_0812: Vu_0812^".b" is Vu_0812 { export Vu_0812; } +VuUW_0812: Vu_0812^".uw" is Vu_0812 { export Vu_0812; } +VuUH_0812: Vu_0812^".uh" is Vu_0812 { export Vu_0812; } +VuUB_0812: Vu_0812^".ub" is Vu_0812 { export Vu_0812; } +VuSF_0812: Vu_0812^".sf" is Vu_0812 { export Vu_0812; } +VuHF_0812: Vu_0812^".hf" is Vu_0812 { export Vu_0812; } +VuQF16_0812: Vu_0812^".qf16" is Vu_0812 { export Vu_0812; } +VuQF32_0812: Vu_0812^".qf32" is Vu_0812 { export Vu_0812; } + +# source vector (16,20) - read-only use +Vv_1620: vv5 is vv5 { + tmp:$(HVX_VECTOR_SIZE) = vv5; + export tmp; +} + +# source vector - read-only use - see Vv_1620 (used for lane naming only) +VvW_1620: Vv_1620^".w" is Vv_1620 { export Vv_1620; } +VvH_1620: Vv_1620^".h" is Vv_1620 { export Vv_1620; } +VvB_1620: Vv_1620^".b" is Vv_1620 { export Vv_1620; } +VvUH_1620: Vv_1620^".uh" is Vv_1620 { export Vv_1620; } +VvUW_1620: Vv_1620^".uw" is Vv_1620 { export Vv_1620; } +VvUB_1620: Vv_1620^".ub" is Vv_1620 { export Vv_1620; } +VvSF_1620: Vv_1620^".sf" is Vv_1620 { export Vv_1620; } +VvHF_1620: Vv_1620^".hf" is Vv_1620 { export Vv_1620; } +VvQF16_1620: Vv_1620^".qf16" is Vv_1620 { export Vv_1620; } +VvQF32_1620: Vv_1620^".qf32" is Vv_1620 { export Vv_1620; } + +# source vector (19,23) - read-only use +Vz_1923: vz5 is vz5 { + tmp:$(HVX_VECTOR_SIZE) = vz5; + export tmp; +} + +# source vector - read-only use - see Vz_1923 (used for lane naming only) +VzW_1923: Vz_1923^".w" is Vz_1923 { export Vz_1923; } +VzH_1923: Vz_1923^".h" is Vz_1923 { export Vz_1923; } +VzB_1923: Vz_1923^".b" is Vz_1923 { export Vz_1923; } +VzUW_1923: Vz_1923^".uw" is Vz_1923 { export Vz_1923; } +VzUH_1923: Vz_1923^".uh" is Vz_1923 { export Vz_1923; } + +# +# General register operand w/ lanes +# + +# source scalar register pair - read-only use - see rxx5 (used for lane naming only) +RttH_1620: rxx5^".h" is rxx5 { tmp:8 = rxx5; export tmp; } +RttUH_1620: rxx5^".uh" is rxx5 { tmp:8 = rxx5; export tmp; } + +# source scalar register - read-only use - see rx5 (used for lane naming only) +RtH_1620: rx5^".h" is rx5 { tmp:4 = rx5; export tmp; } +RtB_1620: rx5^".b" is rx5 { tmp:4 = rx5; export tmp; } +RtUH_1620: rx5^".uh" is rx5 { tmp:4 = rx5; export tmp; } +RtUB_1620: rx5^".ub" is rx5 { tmp:4 = rx5; export tmp; } + +# +# Vector Predicate operands +# + +# Corresponds to Qd4 in documentation (vector predicate destination Q0..Q3, handles unconditional commit) +Qd2: qv0001 is qv0001 & cond=0 { + tmp:$(HVX_PREDICATE_SIZE) = qv0001; + export tmp; + <> + qv0001 = tmp; +} + +# Vector predicate source qv1112 with invert based on op5 +Qv_1112_S05: qv1112 is qv1112 & op5=0 { + tmp:$(HVX_PREDICATE_SIZE) = qv1112; + export tmp; +} +Qv_1112_S05: "!"^qv1112 is qv1112 & op5=1 { + tmp:$(HVX_PREDICATE_SIZE) = ~qv1112; + export tmp; +} + + +# Predicate Register Condition (least significant bit only) + +# map: Ps_0506 -> PuCond0506_S21 +# map: Px_0506 -> pu0506 (read only register use) + +VPuCond0506_S21: ".if("pu0506name")" is op21=0 & pu0506 & pu0506name [cond=1;] { + condition:1 = (pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +VPuCond0506_S21: ".if(!"pu0506name")" is op21=1 & pu0506 & pu0506name [cond=1;] { + condition:1 = !(pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} + +# Predicate Register Condition (least significant bit only) +# map: Pv_1112 -> PuCond1112_S05 + +VPuCond1112_S05: ".if("pu1112name")" is op5=0 & pu1112 & pu1112name [cond=1;] { + condition:1 = (pu1112 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +VPuCond1112_S05: ".if(!"pu1112name")" is op5=1 & pu1112 & pu1112name [cond=1;] { + condition:1 = !(pu1112 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Signed immediate s3 +Simm32_0810: "#"^s0810 is s0810 { export *[const]:4 s0810; } + +# Signed immediate s4 (split into s13 and i0810) +Simm32_0810_13: "#"^simm is s13 & i0810 [ simm = (s13 << 3) | i0810; ] { export *[const]:4 simm; } + +# Vector memory (rx++Mu) load/store vector-sized ram address +# -- 'cond=1' context must be set by conditional instructions! +VAlignMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=0 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; + <> + rx5 = tmp; +} +VAlignMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=1 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +<> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} + +# Vector memory (rx++Mu) unaligned load/store vector-sized ram address +# -- 'cond=1' context must be set by conditional instructions! +VMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=0 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + export *[ram]:$(HVX_VECTOR_SIZE) rx5; + <> + rx5 = tmp; +} +VMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=1 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + export *[ram]:$(HVX_VECTOR_SIZE) rx5; +<> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} + +# Vector memory (rx++#s3) load/store vector-sized ram address +# -- 'cond=1' context must be set by conditional instructions! +VAlignMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=0 & rx5 & rx5_ & Simm32_0810 { + tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); + ptr:4 = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; + <> + rx5 = tmp; +} +VAlignMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=1 & rx5 & rx5_ & Simm32_0810 { + tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); + ptr:4 = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +<> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} + +# Vector memory (rx++#s3) unaligned load/store vector-sized ram address +# -- 'cond=1' context must be set by conditional instructions! +VMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=0 & rx5 & rx5_ & Simm32_0810 { + tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); + export *[ram]:$(HVX_VECTOR_SIZE) rx5; + <> + rx5 = tmp; +} +VMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=1 & rx5 & rx5_ & Simm32_0810 { + tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); + export *[ram]:$(HVX_VECTOR_SIZE) rx5; +<> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} + +# Vector memory (rx+#s4) load/store vector-sized ram address +VAlignMemAddrRxS4: "("^rx5^"+"^Simm32_0810_13^")" is rx5 & Simm32_0810_13 { + ptr:4 = rx5 + (Simm32_0810_13 * $(HVX_VECTOR_SIZE) ); + ptr = ptr & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +} +VAlignMemAddrRxS4: "("^rx5^")" is rx5 & op0810=0 & op13=0 { + ptr = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +} + +# Vector memory (rx+#s4) unaligned load/store vector-sized ram address +VMemAddrRxS4: "("^rx5^"+"^Simm32_0810_13^")" is rx5 & Simm32_0810_13 { + ptr:4 = rx5 + (Simm32_0810_13 * $(HVX_VECTOR_SIZE) ); + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +} +VMemAddrRxS4: "("^rx5^")" is rx5 & op0810=0 & op13=0 { + export *[ram]:$(HVX_VECTOR_SIZE) rx5; +} + + +# optional nontemporal hint :nt +ntHint22: is op22=0 { } +ntHint22:":nt" is op22=1 { } + +# +# HVX Instructions +# + +# (hvx,1) "vwhist256" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 0 1 0 0 - - - - - + +:vwhist256 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0x4 & $(END_PACKET) unimpl + +# (hvx,1) vwhist256 -- "vwhist256:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 1 1 0 0 - - - - - + +:vwhist256^":sat" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0xc & $(END_PACKET) unimpl + +# (hvx,1) "vwhist128" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 0 - 1 0 0 - - - - - + +:vwhist128 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x2 & op0507=0x4 & $(END_PACKET) unimpl + +# (hvx,1) vwhist128 -- "vwhist128(#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 1 i 1 0 0 - - - - - + +:vwhist128 "#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x3 & op0507=0x4 & i8 & $(END_PACKET) unimpl + +# (hvx,1) vwhist256 -- "vwhist256(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 0 1 0 0 - - - - - + +:vwhist256 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x2 & op0507=0x4 & qv2223 & $(END_PACKET) unimpl + +# (hvx,1) vwhist256 -- "vwhist256(Qv4):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 1 1 0 0 - - - - - + +:vwhist256^":sat" qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x3 & op0507=0x4 & qv2223 & $(END_PACKET) unimpl + +# (hvx,1) vwhist128 -- "vwhist128(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 0 - 1 0 0 - - - - - + +:vwhist128 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x2 & op0507=0x4 & qv2223 & $(END_PACKET) unimpl + +# (hvx,1) vwhist128 -- "vwhist128(Qv4,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 1 i 1 0 0 - - - - - + +:vwhist128 qv2223,"#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x3 & op0507=0x4 & qv2223 & i8 & $(END_PACKET) unimpl + +# (hvx,1) and -- "Qd4=and(Qs4,Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 0 d d + +:and Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x0 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 & qv2223; + build EndPacket; +} + +# (hvx,1) or -- "Qd4=or(Qs4,Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 1 d d + +:or Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x1 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 | qv2223; + build EndPacket; +} + +# (hvx,1) xor -- "Qd4=xor(Qs4,Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 1 d d + +:xor Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x3 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 ^ qv2223; + build EndPacket; +} + +# (hvx,1) or -- "Qd4=or(Qs4,!Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 0 d d + +:or Qd2,qv0809,"!"^qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x4 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 | ~qv2223; + build EndPacket; +} + +# (hvx,1) and -- "Qd4=and(Qs4,!Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d + +:and Qd2,qv0809,"!"^qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x5 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 & ~qv2223; + build EndPacket; +} + +# (hvx,1) vshuffe -- "Qd4.b=vshuffe(Qs4.h,Qt4.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 0 d d + +define pcodeop vshuffe_QhQh; + +:vshuffe Qd2^".b",qv0809^".h",qv2223^".h" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x6 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = vshuffe_QhQh(qv0809,qv2223); + build EndPacket; +} + +# (hvx,1) vshuffe -- "Qd4.h=vshuffe(Qs4.w,Qt4.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 1 d d + +define pcodeop vshuffe_QwQw; + +:vshuffe Qd2^".h",qv0809^".w",qv2223^".w" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x7 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = vshuffe_QhQh(qv0809,qv2223); + build EndPacket; +} + +# (hvx,1) vcombine -- "if (!Ps) Vdd=vcombine(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 1 0 v v v v v P P - u u u u u - s s d d d d d +# +# (hvx,1) vcombine -- "if (Ps) Vdd=vcombine(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 1 1 v v v v v P P - u u u u u - s s d d d d d + +define pcodeop vcombine; + +:vcombine^VPuCond0506_S21 vdd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2227=0x29 & VPuCond0506_S21 & vdd5 & vdd5_ & SetNRegRd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + build VPuCond0506_S21; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vdd5_ = vcombine(Vu_0812,Vv_1620); + + <> + if (ConditionReg == 0) goto ; + vdd5 = vdd5_; + +} + +# (hvx,1) vcombine -- "Vdd=vcombine(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +:vcombine Vdd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x7 & Vdd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vdd5 = vcombine(Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vshuffoe -- "Vdd.h=vshuffoe(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vshuffoe_VhVh; + +:vshuffoe VddH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x5 & VddH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddH_0004 = vshuffoe_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vshuffoe -- "Vdd.b=vshuffoe(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vshuffoe_VbVb; + +:vshuffoe VddB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x6 & VddB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VddB_0004 = vshuffoe_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vswap -- "Vdd=vswap(Qt4,Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 1 u u u u u - t t d d d d d + +define pcodeop vswap_QVwVw; + +:vswap Vdd5,qv0506,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x1 & Vdd5 & qv0506 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vdd5 = vswap_QVwVw(qv0506,Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vzxt -- "Vdd.uh=vzxt(Vu.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vzxt_Vub; + +:vzxt VddUH_0004,VuUB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x1 & VddUH_0004 & VuUB_0812 & $(END_PACKET) { + VddUH_0004 = vzxt_Vub(VuUB_0812); + build EndPacket; +} + +# (hvx,1) vzxt -- "Vdd.uw=vzxt(Vu.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vzxt_Vuh; + +:vzxt VddUW_0004,VuUH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x2 & VddUW_0004 & VuUH_0812 & $(END_PACKET) { + VddUW_0004 = vzxt_Vuh(VuUH_0812); + build EndPacket; +} + +# (hvx,1) vsxt -- "Vdd.h=vsxt(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vsxt_Vb; + +:vsxt VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x3 & VddH_0004 & VuB_0812 & $(END_PACKET) { + VddH_0004 = vsxt_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vsxt -- "Vdd.w=vsxt(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Ww_vsxt_Vh; + +:vsxt VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x4 & VddW_0004 & VuH_0812 & $(END_PACKET) { + VddW_0004 = Ww_vsxt_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vadd_WbWb; + +:vadd VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x4 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) { + VddB_0004 = vadd_WbWb(VuuB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vadd_WhWh; + +:vadd VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x5 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) { + VddH_0004 = vadd_WhWh(VuuH_0812,VvvH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Ww_vadd_WwWw; + +:vadd VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x6 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) { + VddW_0004 = Ww_vadd_WwWw(VuuW_0812,VvvW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.ub=vadd(Vuu.ub,Vvv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vadd_WubWub_sat; + +:vadd^":sat" VddUB_0004,VuuUB_0812,VvvUB_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x7 & VddUB_0004 & VuuUB_0812 & VvvUB_1620 & $(END_PACKET) { + VddUB_0004 = vadd_WubWub_sat(VuuUB_0812,VvvUB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.uh=vadd(Vuu.uh,Vvv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_WuhWuh_sat; + +:vadd^":sat" VddUH_0004,VuuUH_0812,VvvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x0 & VddUH_0004 & VuuUH_0812 & VvvUH_1620 & $(END_PACKET) { + VddUH_0004 = vadd_WuhWuh_sat(VuuUH_0812,VvvUH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vadd_WhWh_sat; + +:vadd^":sat" VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x1 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) { + VddH_0004 = vadd_WhWh_sat(VuuH_0812,VvvH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Ww_vadd_WwWw_sat; + +:vadd^":sat" VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x2 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) { + VddW_0004 = Ww_vadd_WwWw_sat(VuuW_0812,VvvW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vsub_WbWb; + +:vsub VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x3 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) { + VddB_0004 = vsub_WbWb(VuuB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vsub_WhWh; + +:vsub VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x4 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) { + VddH_0004 = vsub_WhWh(VuuH_0812,VvvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Ww_vsub_WwWw; + +:vsub VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x5 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) { + VddW_0004 = Ww_vsub_WwWw(VuuW_0812,VvvW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.ub=vsub(Vuu.ub,Vvv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vsub_WubWub_sat; + +:vsub^":sat" VddUB_0004,VuuUB_0812,VvvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x6 & VddUB_0004 & VuuUB_0812 & VvvUB_1620 & $(END_PACKET) { + VddUB_0004 = vsub_WubWub_sat(VuuUB_0812,VvvUB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.uh=vsub(Vuu.uh,Vvv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vsub_WuhWuh_sat; + +:vsub^":sat" VddUH_0004,VuuUH_0812,VvvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x7 & VddUH_0004 & VuuUH_0812 & VvvUH_1620 & $(END_PACKET) { + VddUH_0004 = vsub_WuhWuh_sat(VuuUH_0812,VvvUH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vsub_WhWh_sat; + +:vsub^":sat" VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x0 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) { + VddH_0004 = vsub_WhWh_sat(VuuH_0812,VvvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Ww_vsub_WwWw_sat; + +:vsub^":sat" VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x1 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) { + VddW_0004 = Ww_vsub_WwWw_sat(VuuW_0812,VvvW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_WbWb_sat; + +:vadd^":sat" VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x0 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) { + VddB_0004 = vadd_WbWb_sat(VuuB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vsub_WbWb_sat; + +:vsub^":sat" VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x1 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) { + VddB_0004 = vsub_WbWb_sat(VuuB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.uw=vadd(Vuu.uw,Vvv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vadd_WuwWuw_sat; + +:vadd^":sat" VddUW_0004,VuuUW_0812,VvvUW_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x2 & VddUW_0004 & VuuUW_0812 & VvvUW_1620 & $(END_PACKET) { + VddUW_0004 = vadd_WuwWuw_sat(VuuUW_0812,VvvUW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.uw=vsub(Vuu.uw,Vvv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vsub_WuwWuw_sat; + +:vsub^":sat" VddUW_0004,VuuUW_0812,VvvUW_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x3 & VddUW_0004 & VuuUW_0812 & VvvUW_1620 & $(END_PACKET) { + VddUW_0004 = vsub_WuwWuw_sat(VuuUW_0812,VvvUW_1620); + build EndPacket; +} + +# (hvx,1) not -- "Qd4=not(Qs4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 0 d d + +:not Qd2,qv0809 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x2 & Qd2 & qv0809 & $(END_PACKET) { + Qd2 = ~qv0809; + build EndPacket; +} + +# (hvx,1) vand -- "Vd=vand(Qv4,Vu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop vand_QV; + +:vand Vd5,qv2223,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x0 & Vd5 & qv2223 & Vu_0812 & $(END_PACKET) { + Vd5 = vand_QV(qv2223,Vu_0812); + build EndPacket; +} + +# (hvx,1) vand -- "Vd=vand(!Qv4,Vu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 1 d d d d d + +:vand Vd5,qv2223,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x1 & Vd5 & qv2223 & Vu_0812 & $(END_PACKET) { + Vd5 = vand_QV(~qv2223,Vu_0812); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.ub=vmin(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vmin_VubVub; + +:vmin VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x1 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vmin_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.uh=vmin(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vmin_VuhVuh; + +:vmin VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vmin_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.h=vmin(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vmin_VhVh; + +:vmin VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vmin_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.w=vmin(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vmin_VwVw; + +:vmin VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vmin_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.ub=vmax(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmax_VubVub; + +:vmax VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x5 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vmax_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.uh=vmax(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vmax_VuhVuh; + +:vmax VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x6 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vmax_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.h=vmax(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmax_VhVh; + +:vmax VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x7 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vmax_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.w=vmax(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmax_VwVw; + +:vmax VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vmax_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.b=vmin(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vmin_VbVb; + +:vmin VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x4 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vmin_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.b=vmax(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmax_VbVb; + +:vmax VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x5 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vmax_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.sf=vmax(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop vmax_VsfVsf; + +:vmax VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x1 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdSF_0004 = vmax_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.sf=vmin(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d + +define pcodeop vmin_VsfVsf; + +:vmin VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x2 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdSF_0004 = vmin_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.hf=vmax(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop vmax_VhfVhf; + +:vmax VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x3 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = vmax_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.hf=vmin(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop vmin_VhfVhf; + +:vmin VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x4 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = vmin_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.h=vabs(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vabs_Vh; + +:vabs VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x0 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = vabs_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.h=vabs(Vu.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vabs_Vh_sat; + +:vabs^":sat" VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = vabs_Vh_sat(VuH_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.w=vabs(Vu.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vabs_Vw; + +:vabs VdW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x2 & VdW_0004 & VuW_0812 & $(END_PACKET) { + VdW_0004 = vabs_Vw(VuW_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.w=vabs(Vu.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vabs_Vw_sat; + +:vabs^":sat" VdW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x3 & VdW_0004 & VuW_0812 & $(END_PACKET) { + VdW_0004 = vabs_Vw_sat(VuW_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.b=vabs(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vabs_Vb; + +:vabs VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x4 & VdB_0004 & VuB_0812 & $(END_PACKET) { + VdB_0004 = vabs_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.b=vabs(Vu.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vabs_Vb_sat; + +:vabs^":sat" VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x5 & VdB_0004 & VuB_0812 & $(END_PACKET) { + VdB_0004 = vabs_Vb_sat(VuB_0812); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_VwVw; + +:vadd VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vadd_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vadd_VubVub_sat; + +:vadd^":sat" VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x1 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vadd_VubVub_sat(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.uh=vadd(Vu.uh,Vv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vadd_VuhVuh_sat; + +:vadd^":sat" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vadd_VuhVuh_sat(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vadd_VhVh_sat; + +:vadd^":sat" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vadd_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vadd_VwVw_sat; + +:vadd^":sat" VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vadd_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vsub_VbVb; + +:vsub VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x5 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vsub_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vsub_VhVh; + +:vsub VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vsub_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vsub_VwVw; + +:vsub VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vsub_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vsub_VubVub_sat; + +:vsub^":sat" VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x0 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vsub_VubVub_sat(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.uh=vsub(Vu.uh,Vv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vsub_VuhVuh_sat; + +:vsub^":sat" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vsub_VuhVuh_sat(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vsub_VhVh_sat; + +:vsub^":sat" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x2 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vsub_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vsub_VwVw_sat; + +:vsub^":sat" VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x3 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vsub_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vadd_VubVb_sat; + +:vadd^":sat" VdUB_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x4 & VdUB_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VdUB_0004 = vadd_VubVb_sat(VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vsub_VubVb_sat; + +:vsub^":sat" VdUB_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x5 & VdUB_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VdUB_0004 = vsub_VubVb_sat(VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_VbVb_sat; + +:vadd^":sat" VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x0 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vadd_VbVb_sat(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vsub_VbVb_sat; + +:vsub^":sat" VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x2 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vsub_VbVb_sat(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.uw=vadd(Vu.uw,Vv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vadd_VuwVuw_sat; + +:vadd^":sat" VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x1 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = vadd_VuwVuw_sat(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vadd_VbVb; + +:vadd VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x6 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vadd_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vadd_VhVh; + +:vadd VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x7 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vadd_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.uw=vsub(Vu.uw,Vv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vsub_VuwVuw_sat; + +:vsub^":sat" VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x4 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = vsub_VuwVuw_sat(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qx4):carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 0 x x d d d d d + +define pcodeop vsub_VwVwQ_carry; + +:vadd^":carry" VdW_0004,VuW_0812,VvW_1620,qv0506 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x1 & op7=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & qv0506 & $(END_PACKET) { + VdW_0004 = vsub_VwVwQ_carry(VuW_0812,VvW_1620,qv0506); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w,Qx4):carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 1 x x d d d d d + +define pcodeop vsub_VwVwQ_carry_sat; + +:vsub^":carry" VdW_0004,VuW_0812,VvW_1620,qv0506 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x1 & op7=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & qv0506 & $(END_PACKET) { + VdW_0004 = vsub_VwVwQ_carry_sat(VuW_0812,VvW_1620,qv0506); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qs4):carry:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 0 s s d d d d d + +define pcodeop vadd_VwVwQ_carry_sat; + +:vadd^":carry:sat" VdW_0004,VuW_0812,VvW_1620,qv0506 EndPacket is iclass=0x1 & op2127=0x6c & op13=0x1 & op7=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & qv0506 & $(END_PACKET) { + VdW_0004 = vadd_VwVwQ_carry_sat(VuW_0812,VvW_1620,qv0506); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w,Qe4=vadd(Vu.w,Vv.w):carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 0 e e d d d d d + +define pcodeop vadd_VwVw_carryResult; + +:vadd^":carry" VdW_0004,qv0506,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x6d & op13=0x1 & op7=0x0 & VdW_0004 & qv0506 & VuW_0812 & VvW_1620 & $(END_PACKET) { + tmpQ:$(HVX_PREDICATE_SIZE) = vadd_VwVw_carryResult(VuW_0812,VvW_1620); + VdW_0004 = vadd_VwVw(VuW_0812,VvW_1620); + build EndPacket; + <> + qv0506 = tmpQ; +} + +# (hvx,1) vsub -- "Vd.w,Qe4=vsub(Vu.w,Vv.w):carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 1 e e d d d d d + +define pcodeop vsub_VwVw_carryResult; + +:vsub^":carry" VdW_0004,qv0506,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x6d & op13=0x1 & op7=0x1 & VdW_0004 & qv0506 & VuW_0812 & VvW_1620 & $(END_PACKET) { + tmpQ:$(HVX_PREDICATE_SIZE) = vsub_VwVw_carryResult(VuW_0812,VvW_1620); + VdW_0004 = vsub_VwVw(VuW_0812,VvW_1620); + build EndPacket; + <> + qv0506 = tmpQ; +} + +# (hvx,1) vand -- "Vd=vand(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +:vand Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x5 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = Vu_0812 & Vv_1620; + build EndPacket; +} + +# (hvx,1) vor -- "Vd=vor(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +:vor Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x6 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = Vu_0812 | Vv_1620; + build EndPacket; +} + +# (hvx,1) vxor -- "Vd=vxor(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +:vxor Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x7 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = Vu_0812 ^ Vv_1620; + build EndPacket; +} + +# (hvx,1) vnot -- "Vd=vnot(Vu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 0 0 d d d d d + +:vnot Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x4 & Vd5 & Vu_0812 & $(END_PACKET) { + Vd5 = ~Vu_0812; + build EndPacket; +} + +# (hvx,1) "if (Ps) Vd=Vu" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 0 0 - - - - - P P - u u u u u - s s d d d d d +# +# (hvx,1) "if (!Ps) Vd=Vu" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 0 1 - - - - - P P - u u u u u - s s d d d d d + +:assign^VPuCond0506_S21 vd5,Vu_0812 EndPacket is iclass=0x1 & op2227=0x28 & VPuCond0506_S21 & vd5 & vd5_ & SetVNRegVd5 & Vu_0812 & $(END_PACKET) [ cond=1; ] { + build VPuCond0506_S21; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vd5_ = Vu_0812; + + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# (hvx,1) "Vd=Vu" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 1 1 P P 1 u u u u u 1 1 1 d d d d d + +:assign Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x7 & Vd5 & Vu_0812 & $(END_PACKET) [ cond=0; ] { + Vd5 = Vu_0812; # Vd5 handles unconditional commit + build EndPacket; +} + +# (hvx,1) "Vd.tmp=Vu" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 0 d d d d d + +:assign Vd5tmp,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x6 & Vd5tmp & Vu_0812 & $(END_PACKET) { + Vd5tmp = Vu_0812; + build EndPacket; +} + +# (hvx,1) vcombine -- "Vdd.tmp=vcombine(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +:vcombine Vdd5tmp,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x7 & Vdd5tmp & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vdd5tmp = vcombine(Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vavg_VubVub; + +:vavg VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x4 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vavg_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vavg_VuhVuh; + +:vavg VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x5 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vavg_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vavg_VhVh; + +:vavg VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vavg_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vavg_VwVw; + +:vavg VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vavg_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vnavg -- "Vd.b=vnavg(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vnavg_VubVub; + +:vnavg VdB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x0 & VdB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdB_0004 = vnavg_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vnavg -- "Vd.h=vnavg(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vnavg_VhVh; + +:vnavg VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vnavg_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vnavg -- "Vd.w=vnavg(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vnavg_VwVw; + +:vnavg VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x2 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vnavg_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vavg_VubVub_rnd; + +:vavg^":rnd" VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x3 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vavg_VubVub_rnd(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vavg_VuhVuh_rnd; + +:vavg^":rnd" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x4 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vavg_VuhVuh_rnd(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vavg_VhVh_rnd; + +:vavg^":rnd" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x5 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vavg_VhVh_rnd(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vavg_VwVw_rnd; + +:vavg^":rnd" VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x6 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vavg_VwVw_rnd(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d + +define pcodeop vavg_VuwVuw; + +:vavg VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x2 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = vavg_VuwVuw(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop vavg_VuwVuw_rnd; + +:vavg^":rnd" VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x3 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = vavg_VuwVuw_rnd(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop vavg_VbVb; + +:vavg VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x4 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vavg_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop vavg_VbVb_rnd; + +:vavg^":rnd" VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x5 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vavg_VbVb_rnd(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vnavg -- "Vd.b=vnavg(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop vnavg_VbVb; + +:vnavg VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x6 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vnavg_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 0 d d + +define pcodeop vcmp_eq_VbVb; + +:vcmp.eq Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x0 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_eq_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 1 d d + +define pcodeop vcmp_eq_VhVh; + +:vcmp.eq Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x1 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_eq_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 1 0 d d + +define pcodeop vcmp_eq_VwVw; + +:vcmp.eq Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x2 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_eq_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 0 d d + +define pcodeop vcmp_gt_VbVb; + +:vcmp.gt Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x4 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 1 d d + +define pcodeop vcmp_gt_VhVh; + +:vcmp.gt Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x5 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 1 0 d d + +define pcodeop vcmp_gt_VwVw; + +:vcmp.gt Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x6 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 0 d d + +define pcodeop vcmp_gt_VubVub; + +:vcmp.gt Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x8 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 1 d d + +define pcodeop vcmp_gt_VuhVuh; + +:vcmp.gt Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x9 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 1 0 d d + +define pcodeop vcmp_gt_VuwVuw; + +:vcmp.gt Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0xa & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VuwVuw(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 0 x x + +define pcodeop vcmp_eqand_QVbVb; + +:vcmp.eq Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x0 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_eqand_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 1 x x + +define pcodeop vcmp_eqand_QVhVh; + +:vcmp.eq Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_eqand_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 1 0 x x + +define pcodeop vcmp_eqand_QVwVw; + +:vcmp.eq Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x2 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_eqand_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 0 x x + +define pcodeop vcmp_gtand_QVbVb; + +:vcmp.gt Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x4 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 1 x x + +define pcodeop vcmp_gtand_QVhVh; + +:vcmp.gt Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x5 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 1 0 x x + +define pcodeop vcmp_gtand_QVwVw; + +:vcmp.gt Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x6 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 0 x x + +define pcodeop vcmp_gtand_QVubVub; + +:vcmp.gt Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x8 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVubVub(Qd2,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 1 x x + +define pcodeop vcmp_gtand_QVuhVuh; + +:vcmp.gt Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x9 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVuhVuh(Qd2,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 1 0 x x + +define pcodeop vcmp_gtand_QVuwVuw; + +:vcmp.gt Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xa & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVuwVuw(Qd2,VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 0 x x + +define pcodeop vcmp_gtor_QVsfVsf; + +:vcmp.gt|= Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xc & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVsfVsf(Qd2,VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 1 x x + +define pcodeop vcmp_gtor_QVhfVhf; + +:vcmp.gt|= Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xd & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVhfVhf(Qd2,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 0 x x + +define pcodeop vcmp_eqor_QVbVb; + +:vcmp.eq|= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x10 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_eqor_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 1 x x + +define pcodeop vcmp_eqor_QVhVh; + +:vcmp.eq|= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x11 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_eqor_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 1 0 x x + +define pcodeop vcmp_eqor_QVwVw; + +:vcmp.eq|= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x12 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_eqor_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 0 x x + +define pcodeop vcmp_gtor_QVbVb; + +:vcmp.gt|= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x14 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 1 x x + +define pcodeop vcmp_gtor_QVhVh; + +:vcmp.gt|= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x15 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 1 0 x x + +define pcodeop vcmp_gtor_QVwVw; + +:vcmp.gt|= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x16 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 0 x x + +define pcodeop vcmp_gtor_QVubVub; + +:vcmp.gt|= Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x18 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVubVub(Qd2,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 1 x x + +define pcodeop vcmp_gtor_QVuhVuh; + +:vcmp.gt|= Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x19 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVuhVuh(Qd2,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 1 0 x x + +define pcodeop vcmp_gtor_QVuwVuw; + +:vcmp.gt|= Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1a & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVuwVuw(Qd2,VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 0 d d + +define pcodeop vcmp_gt_VsfVsf; + +:vcmp.gt Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1c & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 1 d d + +define pcodeop vcmp_gt_VhfVhf; + +:vcmp.gt Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1d & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 0 x x + +define pcodeop vcmp_eqxacc_QVbVb; + +:vcmp.eq^"^=" Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x20 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_eqxacc_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 1 x x + +define pcodeop vcmp_eqxacc_QVhVh; + +:vcmp.eq^"^=" Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x21 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_eqxacc_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 1 0 x x + +define pcodeop vcmp_eqxacc_QVwVw; + +:vcmp.eq^"^=" Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x22 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_eqxacc_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 0 x x + +define pcodeop vcmp_gtxacc_QVbVb; + +:vcmp.gt^"^=" Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x24 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 1 x x + +define pcodeop vcmp_gtxacc_QVhVh; + +:vcmp.gt^"^=" Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x25 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 1 0 x x + +define pcodeop vcmp_gtxacc_QVwVw; + +:vcmp.gt^"^=" Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x26 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 0 x x + +define pcodeop vcmp_gtxacc_QVubVub; + +:vcmp.gt^"^=" Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x28 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVubVub(Qd2,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 1 x x + +define pcodeop vcmp_gtxacc_QVuhVuh; + +:vcmp.gt^"^=" Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x29 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVuhVuh(Qd2,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 1 0 x x + +define pcodeop vcmp_gtxacc_QVuwVuw; + +:vcmp.gt^"^=" Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x2a & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVuwVuw(Qd2,VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 0 x x + +define pcodeop vcmp_gtand_QVsfVsf; + +:vcmp.gt^"&=" Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x32 & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVsfVsf(Qd2,VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 1 x x + +define pcodeop vcmp_gtand_QVhfVhf; + +:vcmp.gt^"&=" Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x33 & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVhfVhf(Qd2,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 0 x x + +define pcodeop vcmp_gtxacc_QVsfVsf; + +:vcmp.gt^"^=" Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x3a & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVsfVsf(Qd2,VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 1 x x + +define pcodeop vcmp_gtxacc_QVhfVhf; + +:vcmp.gt^"^=" Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x3b & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVhfVhf(Qd2,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.b+=Vu.b" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop condnac_QnVbVb; + +:accum^".if("^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x0 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QnVbVb(qv2223,VsB_0004,VuB_0812); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.h+=Vu.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop condnac_QnVhVh; + +:accum^".if("^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x1 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QnVhVh(qv2223,VsH_0004,VuH_0812); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.w+=Vu.w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop condnac_QnVwVw; + +:accum^".if("^qv2223^")+=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x2 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { + Vd5 = condnac_QnVwVw(qv2223,VsW_0004,VuW_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.b+=Vu.b" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x + +:accum^".if(!"^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QnVbVb(~qv2223,VsB_0004,VuB_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.h+=Vu.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x + +:accum^".if(!"^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x4 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QnVhVh(~qv2223,VsH_0004,VuH_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.w+=Vu.w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 1 x x x x x + +:accum^".if(!"^qv2223^")+=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x5 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { + Vd5 = condnac_QnVwVw(~qv2223,VsW_0004,VuW_0812); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.b-=Vu.b" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop condnac_QVbVb; + +:accum^".if("^qv2223^")-=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x6 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QVbVb(qv2223,VsB_0004,VuB_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.b-=Vu.b" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 1 x x x x x + +:accum^".if(!"^qv2223^")-=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x1 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QVbVb(~qv2223,VsB_0004,VuB_0812); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.h-=Vu.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop condnac_QVhVh; + +:accum^".if("^qv2223^")-=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x7 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QVhVh(qv2223,VsH_0004,VuH_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.h-=Vu.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 0 x x x x x + +:accum^".if(!"^qv2223^")-=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x2 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QVhVh(~qv2223,VsH_0004,VuH_0812); + build EndPacket; +} + + +# (hvx,1) "if (Qv4) Vx.w-=Vu.w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop condnac_QVwVw; + +:accum^".if("^qv2223^")-=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x0 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { + Vd5 = condnac_QVwVw(qv2223,VsW_0004,VuW_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.w-=Vu.w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 1 x x x x x + +:accum^".if(!"^qv2223^")-=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { + Vd5 = condnac_QVwVw(~qv2223,VsW_0004,VuW_0812); + build EndPacket; +} + +# (hvx,1) vmux -- "Vd=vmux(Qt4,Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 1 1 v v v v v P P 1 u u u u u - t t d d d d d + +define pcodeop vmux_QVV; + +:vmux Vd5,qv0506,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x77 & op13=0x1 & Vd5 & qv0506 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = vmux_QVV(qv0506,Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vsatdw -- "Vd.w=vsatdw(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop vsatdw_VwVw; + +:vsatdw VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x6c & op13=0x1 & op0507=0x7 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vsatdw_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vsat -- "Vd.uh=vsat(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vuh_vsat_VuwVuw; + +:vsat VdUH_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x6 & VdUH_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vsat_VuwVuw(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vsat -- "Vd.ub=vsat(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vub_vsat_VhVh; + +:vsat VdUB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x2 & VdUB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vsat_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsat -- "Vd.h=vsat(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vh_vsat_VwVw; + +:vsat VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x3 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vsat_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vshuffe -- "Vd.b=vshuffe(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vshuffe_VbVb; + +:vshuffe VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x1 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vshuffe_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vshuffo -- "Vd.b=vshuffo(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vshuffo_VbVb; + +:vshuffo VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x2 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vshuffo_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vshuffe -- "Vd.h=vshuffe(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vshuffe_VhVh; + +:vshuffe VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vshuffe_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vshuffo -- "Vd.h=vshuffo(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vshuffo_VhVh; + +:vshuffo VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x4 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vshuffo_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,9) vextract -- "Rd=vextract(Vu,Rs)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 u u u u u 0 0 1 d d d d d + +:vextract Rd5,Vu_0812,rx5 EndPacket is iclass=0x9 & op2127=0x10 & op13=0x0 & op0507=0x1 & Rd5 & Vu_0812 & rx5 & $(END_PACKET) { + # solo instruction in packet - assume .tmp vector not relavent + wordOff:4 = rx5 & ($(HVX_VECTOR_SIZE) - 1) & ~0x3; + vptr:4 = $(HVX_VECTOR_BASE) + wordOff; + Rd5 = *[register]:4 vptr; + build EndPacket; +} + +# (hvx,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vvv.w).h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 1 0 - - - v v v v v + +define pcodeop vgather_RMWw; + +:vgather.h rx5,mu,VssW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x2 & rx5 & mu & VssW_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_RMWw(rx5,mu,VssW_0004); + build EndPacket; +} + +# (hvx,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vvv.w).h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 1 0 - s s v v v v v + +define pcodeop vgather_QRMWw; + +:vgather.h^".if("^qv0506^")" rx5,mu,VssW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x6 & qv0506 & rx5 & mu & VssW_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_QRMWw(qv0506,rx5,mu,VssW_0004); # conditional handled within vgatherIf function + build EndPacket; +} + +# (hvx,2) vgather -- "vtmp.w=vgather(Rt,Mu,Vv.w).w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 0 - - - v v v v v + +define pcodeop vgather_RMVw; + +:vgather.w rx5,mu,VsW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x0 & rx5 & mu & VsW_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_RMVw(rx5,mu,VsW_0004); + build EndPacket; +} + +# (hvx,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vv.h).h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 1 - - - v v v v v + +define pcodeop vgather_RMVh; + +:vgather.h rx5,mu,VsH_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x1 & rx5 & mu & VsH_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_RMVh(rx5,mu,VsH_0004); + build EndPacket; +} + +# (hvx,2) vgather -- "if (Qs4) vtmp.w=vgather(Rt,Mu,Vv.w).w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 0 - s s v v v v v + +# NOTES: +# - Rt identifies a memory source area to be gathered into temp vector +# - Mu identifies length-1 of memory region in bytes +# - Vv.w or Vv.h identifies bytes offsets into the memory region +# - vgather must be paired with vmem Vtmp.new store + +define pcodeop vgather_QRMVw; + +:vgather.w^".if("^qv0506^")" rx5,mu,VsW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x4 & qv0506 & rx5 & mu & VsW_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_QRMVw(qv0506,rx5,mu,VsW_0004); # conditional handled within vgatherIf function + build EndPacket; +} + +# (hvx,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vv.h).h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 1 - s s v v v v v + +define pcodeop vgather_QRMVh; + +:vgather.h^".if("^qv0506^")" rx5,mu,VsH_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x5 & qv0506 & rx5 & mu & VsH_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_QRMVh(qv0506,rx5,mu,VsH_0004); # conditional handled within vgatherIf function + build EndPacket; +} + +# (hvx,2) vmem -- "Vd=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d +# +# (hvx,2) vmem -- "Vd=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d + +:vmem^ntHint22 Vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x10 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=0; ] { + Vd5 = VAlignMemAddrRxS4; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x11 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxS4 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vd5_ = VAlignMemAddrRxS4; + + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# (hvx,2) vmem -- "Vd=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d +# +# (hvx,2) vmem -- "Vd=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d + +:vmem^ntHint22 Vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x12 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { + Vd5 = VAlignMemAddrRxAIS3; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x13 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vd5_ = VAlignMemAddrRxAIS3; + + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# (hvx,2) vmem -- "Vd=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d +# +# (hvx,2) vmem -- "Vd=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d + +:vmem^ntHint22 Vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x16 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { + Vd5 = VAlignMemAddrRxAIMu; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x17 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vd5_ = VAlignMemAddrRxAIMu; + + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# (hvx,2) vmem -- "Vd.cur=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d +# +# (hvx,2) vmem -- "Vd.cur=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d + +:vmem^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x10 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond = 0; ] { + Vd5cur = VAlignMemAddrRxS4; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x11 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5cur = VAlignMemAddrRxS4; + +} + +# (hvx,2) vmem -- "Vd.cur=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d +# +# (hvx,2) vmem -- "Vd.cur=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d +# + +:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x12 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { + Vd5cur = VAlignMemAddrRxAIS3; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x13 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5cur = VAlignMemAddrRxAIS3; + +} + +# (hvx,2) vmem -- "Vd.cur=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d +# +# (hvx,2) vmem -- "Vd.cur=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d + +:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x16 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0;] { + Vd5cur = VAlignMemAddrRxAIMu; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x17 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5cur = VAlignMemAddrRxAIMu; + +} + +# (hvx,2) vmem -- "Vd.tmp=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "Vd.tmp=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d + +:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x10 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) { + Vd5tmp = VAlignMemAddrRxS4; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 0 d d d d d +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x11 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5tmp = VAlignMemAddrRxS4; + +} + +# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d + +:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x12 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { + Vd5tmp = VAlignMemAddrRxAIS3; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x13 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5tmp = VAlignMemAddrRxAIS3; + +} + +# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d +# +# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d + +:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x16 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { + Vd5tmp = VAlignMemAddrRxAIMu; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x17 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5tmp = VAlignMemAddrRxAIMu; + +} + +# (hvx,2) vmemu -- "Vd=vmemu(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 1 1 1 d d d d d + +:vmemu Vd5,VMemAddrRxS4 EndPacket is iclass=0x2 & op2127=0x40 & op1112=0x0 & op0507=0x7 & Vd5 & VMemAddrRxS4 & $(END_PACKET) { + Vd5 = VMemAddrRxS4; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmemu -- "Vd=vmemu(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 1 1 1 d d d d d + +:vmemu Vd5,VMemAddrRxAIS3 EndPacket is iclass=0x2 & op2127=0x48 & op1112=0x0 & op0507=0x7 & Vd5 & VMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { + Vd5 = VMemAddrRxAIS3; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmemu -- "Vd=vmemu(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 1 1 1 d d d d d + +:vmemu Vd5,VMemAddrRxAIMu EndPacket is iclass=0x2 & op2127=0x58 & op1112=0x0 & op0507=0x7 & Vd5 & VMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { + Vd5 = VMemAddrRxAIMu; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):v" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 0 i i x x x x x + +define pcodeop Ww_v6mpyacc_WwWubWbI_v; + +:v6mpy+=^":v" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x0 & vss5 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpyacc_WwWubWbI_v(vss5,VuuUB_0812,VvvB_1620,Uimm2_0506); + build EndPacket; +} + +# (hvx,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 1 i i x x x x x + +define pcodeop Ww_v6mpyacc_WwWubWbI_h; + +:v6mpy+=^":h" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x1 & vss5 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpyacc_WwWubWbI_h(vss5,VuuUB_0812,VvvB_1620,Uimm2_0506); + build EndPacket; +} + +# (hvx,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):v" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 0 i i d d d d d + +define pcodeop Ww_v6mpy_WubWbI_v; + +:v6mpy^":v" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x1 & op7=0x0 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpy_WubWbI_v(VuuUB_0812,VvvB_1620,Uimm2_0506); + build EndPacket; +} + +# (hvx,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 1 i i d d d d d + +define pcodeop Ww_v6mpy_WubWbI_h; + +:v6mpy^":h" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x1 & op7=0x1 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpy_WubWbI_h(VuuUB_0812,VvvB_1620,Uimm2_0506); + build EndPacket; +} + +# (hvx,1) vadd -- "Vxx.w+=vadd(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop Ww_vaddacc_WwVhVh; + +:vadd+= VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x2 & vss5 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vaddacc_WwVhVh(vss5,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vxx.w+=vadd(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop Ww_vaddacc_WwVuhVuh; + +:vadd+= VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x4 & vss5 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vaddacc_WwVuhVuh(vss5,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vxx.h+=vadd(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop Wh_vaddacc_WhVubVub; + +:vadd+= VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x5 & vss5 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddH_0004 = Wh_vaddacc_WhVubVub(vss5,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.h=vadd(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Wh_vadd_VubVub; + +:vadd VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x2 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddH_0004 = Wh_vadd_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.w=vadd(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Ww_vadd_VuhVuh; + +:vadd VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x3 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vadd_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.w=vadd(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Ww_vadd_VhVh; + +:vadd VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x4 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vadd_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.h=vsub(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Wh_vsub_VubVub; + +:vsub VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x5 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddH_0004 = Wh_vsub_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.w=vsub(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Ww_vsub_VuhVuh; + +:vsub VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x6 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vsub_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.w=vsub(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Ww_vsub_VhVh; + +:vsub VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x7 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vsub_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vdd.h=vdmpy(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Ww_vdmpy_WubRb; + +:vdmpy VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x7 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = Ww_vdmpy_WubRb(VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vxx.h+=vdmpy(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vdmpyacc_WhWubRb; + +:vdmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x7 & vss5 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vdmpyacc_WhWubRb(vss5,VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.uh,#1):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vw_vdmpy_WhRuh_sat; + +:vdmpy^":sat" VdW_0004,VuuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x1 & VdW_0004 & VuuH_0812 & RtUH_1620 & $(END_PACKET) { + VdW_0004 = Vw_vdmpy_WhRuh_sat(VuuH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vw_vdmpy_WhRh_sat; + +:vdmpy^":sat" VdW_0004,VuuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x3 & VdW_0004 & VuuH_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = Vw_vdmpy_WhRh_sat(VuuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vdd.w=vdmpy(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Ww_vdmpy_WhRb; + +:vdmpy VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x4 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = Ww_vdmpy_WhRb(VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.uh,#1):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vdmpyacc_VwWhRuh_sat; + +:vdmpy+=^":sat" VdW_0004,VuuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & VuuH_0812 & RtUH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwWhRuh_sat(vs5,VuuH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vdmpyacc_VwWhRh_sat; + +:vdmpy+=^":sat" VdW_0004,VuuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuuH_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwWhRh_sat(vs5,VuuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vxx.w+=vdmpy(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vdmpyacc_WwWhRb; + +:vdmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x4 & vss5 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vdmpyacc_WwWhRb(vss5,VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vdmpyacc_VwVhVh_sat; + +:vdmpy+=^":sat" VdW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwVhVh_sat(vs5,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vlut4 -- "Vd.h=vlut4(Vu.uh,Rtt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vlut4_VuhPh; + +:vlut4 VdH_0004,VuUH_0812,RttH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x4 & VdH_0004 & VuUH_0812 & RttH_1620 & $(END_PACKET) { + VdH_0004 = vlut4_VuhPh(VuUH_0812,RttH_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.h,Rtt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vmpa_VhVhVhPh_sat; + +:vmpa^":sat" VdH_0004,VsH_0004,VuH_0812,RttH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x4 & VdH_0004 & VsH_0004 & VuH_0812 & RttH_1620 & $(END_PACKET) { + VdH_0004 = vmpa_VhVhVhPh_sat(VsH_0004,VuH_0812,RttH_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vmpa_VhVhVuhPuh_sat; + +:vmpa^":sat" VdH_0004,VsH_0004,VuUH_0812,RttUH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x5 & VdH_0004 & VsH_0004 & VuUH_0812 & RttUH_1620 & $(END_PACKET) { + VdH_0004 = vmpa_VhVhVuhPuh_sat(VsH_0004,VuUH_0812,RttUH_1620); + build EndPacket; +} + +# (hvx,1) vmps -- "Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmps_VhVhVuhPuh_sat; + +:vmps^":sat" VdH_0004,VsH_0004,VuUH_0812,RttUH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x6 & VdH_0004 & VsH_0004 & VuUH_0812 & RttUH_1620 & $(END_PACKET) { + VdH_0004 = vmps_VhVhVuhPuh_sat(VsH_0004,VuUH_0812,RttUH_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vmpa_WubRb; + +:vmpa VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x6 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpa_WubRb(VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.w=vmpa(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmpa_WhRb; + +:vmpa VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x7 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpa_WhRb(VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmpaacc_WhWubRb; + +:vmpa+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x6 & vss5 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpaacc_WhWubRb(vss5,VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vxx.w+=vmpa(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vmpaacc_WwWhRb; + +:vmpa+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x7 & vss5 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpaacc_WwWhRb(vss5,VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vmpa_WubRub; + +:vmpa VddH_0004,VuuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x3 & VddH_0004 & VuuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddH_0004 = vmpa_WubRub(VuuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.w=vmpa(Vuu.uh,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmpa_WuhRb; + +:vmpa VddW_0004,VuuUH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x5 & VddW_0004 & VuuUH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpa_WuhRb(VuuUH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vxx.w+=vmpa(Vuu.uh,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vmpaacc_WwWuhRb; + +:vmpa+= VddW_0004,VuuUH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x2 & vss5 & VddW_0004 & VuuUH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpaacc_WwWuhRb(vss5,VuuUH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vmpaacc_WhWubRub; + +:vmpa+= VddH_0004,VuuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x4 & vss5 & VddH_0004 & VuuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddH_0004 = vmpaacc_WhWubRub(vss5,VuuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vmpa_WubWb; + +:vmpa VddH_0004,VuuUB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x3 & VddH_0004 & VuuUB_0812 & VvvB_1620 & $(END_PACKET) { + VddH_0004 = vmpa_WubWb(VuuUB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmpa_WubWub; + +:vmpa VddH_0004,VuuUB_0812,VvvUB_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x7 & VddH_0004 & VuuUB_0812 & VvvUB_1620 & $(END_PACKET) { + VddH_0004 = vmpa_WubWub(VuuUB_0812,VvvUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmpy_VubRb; + +:vmpy VddH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x5 & VddH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpy_VubRb(VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vmpyacc_WhVubRb; + +:vmpy+= VddH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x5 & vss5 & VddH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpyacc_WhVubRb(vss5,VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.w=vmpy(Vu.h,Rt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpy_VhRh; + +:vmpy VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x0 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VddW_0004 = vmpy_VhRh(VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vmpy_VuhRuh; + +:vmpy VddUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x3 & VddUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpy_VuhRuh(VuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vmpyacc_WwVhRh_sat; + +:vmpy+=^":sat" VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x0 & vss5 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VddW_0004 = vmpyacc_WwVhRh_sat(vss5,VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vmpyacc_WuwVuhRuh; + +:vmpy+= VddUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x1 & vss5 & VddUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpyacc_WuwVuhRuh(vss5,VuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vmpyacc_WuhVubRub; + +:vmpy+= VddUH_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x0 & vss5 & VddUH_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpyacc_WuhVubRub(vss5,VuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmpyacc_WwVhRh; + +:vmpy+= VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x6 & vss5 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VddW_0004 = vmpyacc_WwVhRh(vss5,VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpy_VubRub; + +:vmpy VddUH_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4e & op13=0x0 & op0507=0x0 & VddUH_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpy_VubRub(VuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.h=vmpy(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vmpy_VbVb; + +:vmpy VddH_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x4 & VddH_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpy_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmpy_VubVub; + +:vmpy VddUH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x5 & VddUH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpy_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vmpy_VubVb; + +:vmpy VddH_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x6 & VddH_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpy_VubVb(VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.h+=vmpy(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vmpyacc_WhVbVb; + +:vmpy+= VddH_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x4 & vss5 & VddH_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpyacc_WhVbVb(vss5,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vmpyacc_WuhVubVub; + +:vmpy+= VddUH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x5 & vss5 & VddUH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpyacc_WuhVubVub(vss5,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmpyacc_WhVubVb; + +:vmpy+= VddH_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x6 & vss5 & VddH_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpyacc_WhVubVb(vss5,VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpy_VuhVuh; + +:vmpy VddUW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x0 & VddUW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpy_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vmpyacc_WuwVuhVuh; + +:vmpy+= VddUW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x0 & vss5 & VddUW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpyacc_WuwVuhVuh(vss5,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop Wqf32_vmpy_Vqf16Vhf; + +:vmpy VddQF32_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x1 & op0507=0x0 & VddQF32_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) { + VddQF32_0004 = Wqf32_vmpy_Vqf16Vhf(VuQF16_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop vmpy_Vqf16Vqf16; + +:vmpy VdQF16_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x3 & VdQF16_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) { + VdQF16_0004 = vmpy_Vqf16Vqf16(VuQF16_0812,VvQF16_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf16=vmpy(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop vmpy_VhfVhf; + +:vmpy VdQF16_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x4 & VdQF16_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = vmpy_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop vmpy_Vqf16Vhf; + +:vmpy VdQF16_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x5 & VdQF16_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = vmpy_Vqf16Vhf(VuQF16_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop Wqf32_vmpy_Vqf16Vqf16; + +:vmpy VddQF32_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x6 & VddQF32_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) { + VddQF32_0004 = Wqf32_vmpy_Vqf16Vqf16(VuQF16_0812,VvQF16_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.qf32=vmpy(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop Wqf32_vmpy_VhfVhf; + +:vmpy VddQF32_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x7 & VddQF32_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VddQF32_0004 = Wqf32_vmpy_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vmpyi_VhVh; + +:vmpyi VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x4 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vmpyi_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vmpyiacc_VhVhVh; + +:vmpyi+= VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x4 & vs5 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vmpyiacc_VhVhVh(vs5,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vmpyieacc_VwVwVuh; + +:vmpyie+= VdW_0004,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x5 & vs5 & VdW_0004 & VuW_0812 & VvUH_1620 & $(END_PACKET) { + VdW_0004 = vmpyieacc_VwVwVuh(vs5,VuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vmpyieacc_VwVwVh; + +:vmpyie+= VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x0 & vs5 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyieacc_VwVwVh(vs5,VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyie -- "Vd.w=vmpyie(Vu.w,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyie_VwVuh; + +:vmpyie VdW_0004,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvUH_1620 & $(END_PACKET) { + VdW_0004 = vmpyie_VwVuh(VuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyio -- "Vd.w=vmpyio(Vu.w,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vmpyio_VwVh; + +:vmpyio VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x1 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyio_VwVh(VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vmpyiacc_VwVwRh; + +:vmpyi+= VdW_0004,VuW_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuW_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vmpyiacc_VwVwRh(vs5,VuW_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmpyi_VwRh; + +:vmpyi VdW_0004,VuW_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vmpyi_VwRh(VuW_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf32=vmpy(Vu.qf32,Vv.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop vmpy_Vqf32Vqf32; + +:vmpy VdQF32_0004,VuQF32_0812,VvQF32_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x0 & VdQF32_0004 & VuQF32_0812 & VvQF32_1620 & $(END_PACKET) { + VdQF32_0004 = vmpy_Vqf32Vqf32(VuQF32_0812,VvQF32_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf32=vmpy(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop vmpy_VsfVsf; + +:vmpy VdQF32_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x1 & VdQF32_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = vmpy_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vxx+=vmpyo(Vu.w,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vmpyoacc_WVwVh; + +:vmpyo+= Vdd5,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x3 & vss5 & Vdd5 & VuW_0812 & VvH_1620 & $(END_PACKET) { + Vdd5 = vmpyoacc_WVwVh(vss5,VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:sat:shift" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmpyoacc_VwVwVh_s1_sat_shift; + +:vmpyo+=^":<<1:sat:shift" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x6 & vs5 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyoacc_VwVwVh_s1_sat_shift(vs5,VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vmpyoacc_VwVwVh_s1_rnd_sat_shift; + +:vmpyo+=^":<<1:rnd:sat:shift" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x7 & vs5 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyoacc_VwVwVh_s1_rnd_sat_shift(vs5,VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpye -- "Vdd=vmpye(Vu.w,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop W_vmpye_VwVuh; + +:vmpye Vdd5,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x6 & Vdd5 & VuW_0812 & VvUH_1620 & $(END_PACKET) { + Vdd5 = W_vmpye_VwVuh(VuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyo_VwVh_s1_rnd_sat; + +:vmpyo^":<<1:rnd:sat" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyo_VwVh_s1_rnd_sat(VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpye -- "Vd.w=vmpye(Vu.w,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmpye_VwVuh; + +:vmpye VdW_0004,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x5 & VdW_0004 & VuW_0812 & VvUH_1620 & $(END_PACKET) { + VdW_0004 = vmpye_VwVuh(VuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmpyo_VwVh_s1_sat; + +:vmpyo^":<<1:sat" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyo_VwVh_s1_sat(VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vdd.w=vrmpy(Vuu.ub,Rt.b,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 0 i d d d d d + +define pcodeop vrmpy_WubRbI; + +:vrmpy VddW_0004,VuuUB_0812,RtB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0607=0x2 & VddW_0004 & VuuUB_0812 & RtB_1620 & Uimm1_05 & $(END_PACKET) { + VddW_0004 = vrmpy_WubRbI(VuuUB_0812,RtB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vxx.w+=vrmpy(Vuu.ub,Rt.b,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 0 i x x x x x + +define pcodeop vrmpyacc_WwWubRbI; + +:vrmpy+= VddW_0004,VuuUB_0812,RtB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x2 & vss5 & VddW_0004 & VuuUB_0812 & RtB_1620 & Uimm1_05 & $(END_PACKET) { + VddW_0004 = vrmpyacc_WwWubRbI(vss5,VuuUB_0812,RtB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vxx.uw+=vrmpy(Vuu.ub,Rt.ub,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 1 i x x x x x + +define pcodeop vrmpyacc_WuwWubRubI; + +:vrmpy+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0607=0x3 & vss5 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrmpyacc_WuwWubRubI(vss5,VuuUB_0812,RtUB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vdd.uw=vrmpy(Vuu.ub,Rt.ub,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 1 i d d d d d + +define pcodeop vrmpy_WubRubI; + +:vrmpy VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0607=0x3 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrmpy_WubRubI(VuuUB_0812,RtUB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vrmpyacc_VuwVubVub; + +:vrmpy+= VdUW_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x0 & vs5 & VdUW_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUW_0004 = vrmpyacc_VuwVubVub(vs5,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.w+=vrmpy(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vrmpyacc_VwVbVb; + +:vrmpy+= VdW_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdW_0004 = vrmpyacc_VwVbVb(vs5,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vrmpyacc_VwVubVb; + +:vrmpy+= VdW_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VdW_0004 = vrmpyacc_VwVubVb(vs5,VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vdd.h=vtmpy(Vuu.b,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vtmpy_WbRb; + +:vtmpy VddH_0004,VuuB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x0 & VddH_0004 & VuuB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpy_WbRb(VuuB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vdd.h=vtmpy(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vtmpy_WubRb; + +:vtmpy VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x1 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpy_WubRb(VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.b,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vtmpyacc_WhWbRb; + +:vtmpy+= VddH_0004,VuuB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x0 & vss5 & VddH_0004 & VuuB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpyacc_WhWbRb(vss5,VuuB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vtmpyacc_WhWubRb; + +:vtmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x1 & vss5 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpyacc_WhWubRb(vss5,VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vxx.w+=vtmpy(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vtmpyacc_WwWhRb; + +:vtmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x2 & vss5 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vtmpyacc_WwWhRb(vss5,VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vdd.w=vtmpy(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vtmpy_WhRb; + +:vtmpy VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x4 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vtmpy_WhRb(VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdsad -- "Vdd.uw=vdsad(Vuu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vdsad_WuhRuh; + +:vdsad VddUW_0004,VuuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x5 & VddUW_0004 & VuuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vdsad_WuhRuh(VuuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdsad -- "Vxx.uw+=vdsad(Vuu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vdsadacc_WuwWuhRuh; + +:vdsad+= VddUW_0004,VuuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x0 & vss5 & VddUW_0004 & VuuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vdsadacc_WuwWuhRuh(vss5,VuuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vrsad -- "Vdd.uw=vrsad(Vuu.ub,Rt.ub,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 1 i d d d d d + +define pcodeop vrsad_WubRubI; + +:vrsad VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0607=0x3 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrsad_WubRubI(VuuUB_0812,RtUB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrsad -- "Vxx.uw+=vrsad(Vuu.ub,Rt.ub,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 1 i x x x x x + +define pcodeop vrsadacc_WuwWubRubI; + +:vrsad+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x3 & vss5 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrsadacc_WuwWubRubI(vss5,VuuUB_0812,RtUB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vdmpy_VhRb; + +:vdmpy VdW_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x2 & VdW_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vdmpy_VhRb(VuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.h=vdmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vdmpy_VubRb; + +:vdmpy VdH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x6 & VdH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VdH_0004 = vdmpy_VubRb(VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vdmpyacc_VwVhRb; + +:vdmpy+= VdW_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwVhRb(vs5,VuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.h+=vdmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vdmpyacc_VhVubRb; + +:vdmpy+= VdH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x6 & vs5 & VdH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VdH_0004 = vdmpyacc_VhVubRb(vs5,VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vdmpy_VhRuh_sat; + +:vdmpy^":sat" VdW_0004,VuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x0 & VdW_0004 & VuH_0812 & RtUH_1620 & $(END_PACKET) { + VdW_0004 = vdmpy_VhRuh_sat(VuH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vdmpy_VhRh_sat; + +:vdmpy^":sat" VdW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x2 & VdW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vdmpy_VhRh_sat(VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vdmpyacc_VwVhRuh_sat; + +:vdmpy+=^":sat" VdW_0004,VuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x0 & vs5 & VdW_0004 & VuH_0812 & RtUH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwVhRuh_sat(vs5,VuH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vdmpyacc_VwVhRh_sat; + +:vdmpy+=^":sat" VdW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwVhRh_sat(vs5,VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vdmpy_VhVh_sat; + +:vdmpy^":sat" VdW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x3 & VdW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vdmpy_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vmpy_VhRh_s1_sat; + +:vmpy^":<<1:sat" VdH_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VdH_0004 = vmpy_VhRh_s1_sat(VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vmpy_VhRh_s1_rnd_sat; + +:vmpy^":<<1:rnd:sat" VdH_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x2 & VdH_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VdH_0004 = vmpy_VhRh_s1_rnd_sat(VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.uh=vmpy(Vu.uh,Vv.uh):>>16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop vmpy_VuhVuh_rs16; + +:vmpy^":>>16" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x7 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vmpy_VuhVuh_rs16(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyieo -- "Vd.w=vmpyieo(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyieo_VhVh; + +:vmpyieo VdW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x0 & VdW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyieo_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vmpyiacc_VwVwRb; + +:vmpyi+= VdW_0004,VuW_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuW_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vmpyiacc_VwVwRb(vs5,VuW_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyi_VhRb; + +:vmpyi VdH_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x0 & VdH_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) { + VdH_0004 = vmpyi_VhRb(VuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vmpyiacc_VhVhRb; + +:vmpyi+= VdH_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x1 & vs5 & VdH_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) { + VdH_0004 = vmpyiacc_VhVhRb(vs5,VuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vmpyi_VwRub; + +:vmpyi VdW_0004,VuW_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x6 & VdW_0004 & VuW_0812 & RtUB_1620 & $(END_PACKET) { + VdW_0004 = vmpyi_VwRub(VuW_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vmpyiacc_VwVwRub; + +:vmpyi+= VdW_0004,VuW_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & VuW_0812 & RtUB_1620 & $(END_PACKET) { + VdW_0004 = vmpyiacc_VwVwRub(vs5,VuW_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyi_VwRb; + +:vmpyi VdW_0004,VuW_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vmpyi_VwRb(VuW_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpye -- "Vd.uw=vmpye(Vu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vmpye_VuhRuh; + +:vmpye VdUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x2 & VdUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { + VdUW_0004 = vmpye_VuhRuh(VuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vmpye -- "Vx.uw+=vmpye(Vu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vmpyeacc_VuwVuhRuh; + +:vmpye+= VdUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x3 & vs5 & VdUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { + VdUW_0004 = vmpyeacc_VuwVuhRuh(vs5,VuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vrmpy_VubRub; + +:vrmpy VdUW_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x3 & VdUW_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { + VdUW_0004 = vrmpy_VubRub(VuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vw_vrmpy_VubRb; + +:vrmpy VdW_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x4 & VdW_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = Vw_vrmpy_VubRb(VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vrmpyacc_VuwVubRub; + +:vrmpy+= VdUW_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x4 & vs5 & VdUW_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { + VdUW_0004 = vrmpyacc_VuwVubRub(vs5,VuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vrmpyacc_VwVubRb; + +:vrmpy+= VdW_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x5 & vs5 & VdW_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vrmpyacc_VwVubRb(vs5,VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vuw_vrmpy_VubVub; + +:vrmpy VdUW_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x0 & VdUW_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUW_0004 = Vuw_vrmpy_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.w=vrmpy(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vw_vrmpy_VbVb; + +:vrmpy VdW_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x1 & VdW_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdW_0004 = Vw_vrmpy_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vw_vrmpy_VubVb; + +:vrmpy VdW_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x2 & VdW_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VdW_0004 = Vw_vrmpy_VubVb(VuUB_0812,VvB_1620); + build EndPacket; +} + +# +# NOTE: The vsplat instruction from V60 was removed in later versions +# + +# (hvx,1) vsplat -- "Vd=vsplat(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - 0 0 0 1 d d d d d + +define pcodeop V_vsplat_R; + +:vsplat Vd5,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0508=0x1 & Vd5 & rx5 & $(END_PACKET) { + Vd5 = V_vsplat_R(rx5); + build EndPacket; +} + +# (hvx,1) vsplat -- "Vd.h=vsplat(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 0 1 d d d d d + +define pcodeop Vh_vsplat_R; + +:vsplat VdH_0004,rx5 EndPacket is iclass=0x1 & op2127=0x4e & op13=0x0 & op0507=0x1 & VdH_0004 & rx5 & $(END_PACKET) { + VdH_0004 = Vh_vsplat_R(rx5); + build EndPacket; +} + +# (hvx,1) vsplat -- "Vd.b=vsplat(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 1 0 d d d d d + +define pcodeop Vb_vsplat_R; + +:vsplat VdB_0004,rx5 EndPacket is iclass=0x1 & op2127=0x4e & op13=0x0 & op0507=0x2 & VdB_0004 & rx5 & $(END_PACKET) { + VdB_0004 = Vb_vsplat_R(rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Qx4|=vand(Vu,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 0 - - - x x + +define pcodeop Q_vandor_QVR; + +:vand|= Qd2,Vu_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x4 & Qd2 & Vu_0812 & rx5 & $(END_PACKET) { + Qd2 = Q_vandor_QVR(Qd2,Vu_0812,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Qd4=vand(Vu,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 1 0 - 1 0 d d + +define pcodeop Q_vand_VR; + +:vand Qd2,Vu_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x2 & op3=0x1 & op2=0x0 & Qd2 & Vu_0812 & rx5 & $(END_PACKET) { + Qd2 = Q_vand_VR(Vu_0812,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Vx|=vand(Qu4,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 0 u u 0 1 1 x x x x x + +define pcodeop V_vandor_VQR; + +:vand|= Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x0 & op0507=0x3 & Vd5 & vs5 & qv0809 & rx5 & $(END_PACKET) { + Vd5 = V_vandor_VQR(vs5,qv0809,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Vx|=vand(!Qu4,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 1 u u 0 1 1 x x x x x + +:vand|= Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x1 & op0507=0x3 & Vd5 & vs5 & qv0809 & rx5 & $(END_PACKET) { + Vd5 = V_vandor_VQR(vs5,~qv0809,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Vd=vand(Qu4,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 0 u u 1 0 1 d d d d d + +define pcodeop V_vand_QR; + +:vand Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x0 & op0507=0x5 & Vd5 & qv0809 & rx5 & $(END_PACKET) { + Vd5 = V_vand_QR(qv0809,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Vd=vand(!Qu4,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 1 u u 1 0 1 d d d d d + +:vand Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x1 & op0507=0x5 & Vd5 & qv0809 & rx5 & $(END_PACKET) { + Vd5 = V_vand_QR(~qv0809,rx5); + build EndPacket; +} + +# (hvx,1) vabsdiff -- "Vd.ub=vabsdiff(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vub_vabsdiff_VubVub; + +:vabsdiff VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x0 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vabsdiff_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vuh_vabsdiff_VhVh; + +:vabsdiff VdUH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vabsdiff_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vuh_vabsdiff_VuhVuh; + +:vabsdiff VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vabsdiff_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vabsdiff -- "Vd.uw=vabsdiff(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vuw_vabsdiff_VwVw; + +:vabsdiff VdUW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x3 & VdUW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdUW_0004 = Vuw_vabsdiff_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vinsert -- "Vx.w=vinsert(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 - - - - - 0 0 1 x x x x x + +define pcodeop vinsert_VwR; + +:vinsert VdW_0004,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & rx5 & $(END_PACKET) { + VdW_0004 = vinsert_VwR(vs5,rx5); + build EndPacket; +} + +# (hvx,1) vror -- "Vd=vror(Vu,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vror_VR; + +:vror Vd5,Vu_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x1 & Vd5 & Vu_0812 & rx5 & $(END_PACKET) { + Vd5 = vror_VR(Vu_0812,rx5); + build EndPacket; +} + +# (hvx,1) valign -- "Vd=valign(Vu,Vv,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop valign_VVR; + +:valign Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x0 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) { + Vd5 = valign_VVR(Vu_0812,Vz_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlalign -- "Vd=vlalign(Vu,Vv,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vlalign_VVR; + +:vlalign Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x1 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) { + Vd5 = vlalign_VVR(Vu_0812,Vz_1923,rt1618); + build EndPacket; +} + +# (hvx,1) valign -- "Vd=valign(Vu,Vv,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 1 u u u u u i i i d d d d d + +define pcodeop V_valign_VVI; + +:valign Vd5,Vu_0812,Vv_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x71 & op13=0x1 & Vd5 & Vu_0812 & Vv_1620 & Uimm8_0507 & $(END_PACKET) { + Vd5 = V_valign_VVI(Vu_0812,Vv_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vlalign -- "Vd=vlalign(Vu,Vv,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 1 u u u u u i i i d d d d d + +define pcodeop V_vlalign_VVI; + +:vlalign Vd5,Vu_0812,Vv_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x73 & op13=0x1 & Vd5 & Vu_0812 & Vv_1620 & Uimm8_0507 & $(END_PACKET) { + Vd5 = V_vlalign_VVI(Vu_0812,Vv_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vdelta -- "Vd=vdelta(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vdelta_VV; + +:vdelta Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x1 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = vdelta_VV(Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vrdelta -- "Vd=vrdelta(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vrdelta_VV; + +:vrdelta Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x3 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = vrdelta_VV(Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vdeal -- "Vd.h=vdeal(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vdeal_Vh; + +:vdeal VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = vdeal_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vdeal -- "Vd.b=vdeal(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vdeal_Vb; + +:vdeal VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x7 & VdB_0004 & VuB_0812 & $(END_PACKET) { + VdB_0004 = vdeal_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vshuff -- "Vd.h=vshuff(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vshuff_Vh; + +:vshuff VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x7 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = vshuff_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vshuff -- "Vd.b=vshuff(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vshuff_Vb; + +:vshuff VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x0 & VdB_0004 & VuB_0812 & $(END_PACKET) { + VdB_0004 = vshuff_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vdeale -- "Vd.b=vdeale(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vdeale_VbVb; + +:vdeale VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x7 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vdeale_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vpacke -- "Vd.b=vpacke(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vb_vpacke_VhVh; + +:vpacke VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x2 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdB_0004 = Vb_vpacke_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vpacke -- "Vd.h=vpacke(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vh_vpacke_VwVw; + +:vpacke VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x3 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vpacke_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vpack -- "Vd.ub=vpack(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vb_vpack_VhVh_sat; + +:vpack^":sat" VdUB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x5 & VdUB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdUB_0004 = Vb_vpack_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vpack -- "Vd.b=vpack(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vb_vpacko_VhVh_sat; + +:vpack^":sat" VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x6 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdB_0004 = Vb_vpacko_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vpack -- "Vd.uh=vpack(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vuh_vpack_VwVw_sat; + +:vpack^":sat" VdUH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x7 & VdUH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vpack_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vpack -- "Vd.h=vpack(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vh_vpack_VwVw_sat; + +:vpack^":sat" VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x0 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vpack_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vpacko -- "Vd.b=vpacko(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vb_vpacko_VhVh; + +:vpacko VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x1 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdB_0004 = Vb_vpacko_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vpacko -- "Vd.h=vpacko(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vh_vpacko_VwVw; + +:vpacko VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x2 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vpacko_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vsetq -- "Qd4=vsetq(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 0 1 d d + +define pcodeop Q_vsetq_R; + +:vsetq Qd2,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x2 & op3=0x0 & op2=0x1 & Qd2 & rx5 & $(END_PACKET) { + Qd2 = Q_vsetq_R(rx5); + build EndPacket; +} + +# (hvx,1) vsetq2 -- "Qd4=vsetq2(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 1 1 d d + +define pcodeop Q_vsetq2_R; + +:vsetq2 Qd2,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x2 & op3=0x1 & op2=0x1 & Qd2 & rx5 & $(END_PACKET) { + Qd2 = Q_vsetq2_R(rx5); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt):nomatch" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vb_vlut32_VbVbR_nomatch; + +:vlut32^":nomatch" VdB_0004,VuB_0812,VzB_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x3 & VdB_0004 & VuB_0812 & VzB_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = Vb_vlut32_VbVbR_nomatch(VuB_0812,VzB_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop Vb_vlut32_VbVbR; + +:vlut32 VdB_0004,VuB_0812,VzB_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x1 & VdB_0004 & VuB_0812 & VzB_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = Vb_vlut32_VbVbR(VuB_0812,VzB_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 0 u u u u u i i i d d d d d + +define pcodeop Vb_vlut32_VbVbI; + +:vlut32 VdB_0004,VuB_0812,VvB_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x71 & op13=0x0 & VdB_0004 & VuB_0812 & VvB_1620 & Uimm8_0507 & $(END_PACKET) { + VdB_0004 = Vb_vlut32_VbVbI(VuB_0812,VvB_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vasrinto -- "Vxx.w=vasrinto(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 1 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vasrinto_WwVwVw; + +:vasrinto VddW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x55 & op13=0x1 & op0507=0x7 & vss5 & VddW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VddW_0004 = vasrinto_WwVwVw(vss5,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vshuff -- "vshuff(Vy,Vx,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 0 1 x x x x x + +define pcodeop vshuff_VwVwR; + +:vshuff vu5,vs5,rx5 EndPacket is iclass=0x1 & op2127=0x4f & op13=0x1 & op0507=0x1 & vu5 & vs5 & rx5 & $(END_PACKET) { + # NOTE: Uncertain if this logic is correct or if .new value store should be updated in some way + pair:$(HVX_VECTOR_PAIR_SIZE) = vshuff_VwVwR(vu5,vs5,rx5); + build EndPacket; + <> + # Extract updated Vy and Vx vectors from 'pair' result from vshuff + vu5 = pair($(HVX_VECTOR_SIZE)); + vs5 = pair:$(HVX_VECTOR_SIZE); +} + +# (hvx,1) vdeal -- "vdeal(Vy,Vx,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 1 0 x x x x x + +define pcodeop vdeal_VwVwR; + +:vdeal vu5,vs5,rx5 EndPacket is iclass=0x1 & op2127=0x4f & op13=0x1 & op0507=0x2 & vu5 & vs5 & rx5 & $(END_PACKET) { + # NOTE: Uncertain if this logic is correct or if .new value store should be updated in some way + pair:$(HVX_VECTOR_PAIR_SIZE) = vdeal_VwVwR(vu5,vs5,rx5); + build EndPacket; + <> + # Extract updated Vy and Vx vectors from 'pair' result from vdeal + vu5 = pair($(HVX_VECTOR_SIZE)); + vs5 = pair:$(HVX_VECTOR_SIZE); +} + +# (hvx,1) vshuff -- "Vdd=vshuff(Vu,Vv,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 1 1 d d d d d + +:vshuff Vdd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x3 & Vdd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) { + Vdd5 = vshuff_VwVwR(Vu_0812,Vz_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vdeal -- "Vdd=vdeal(Vu,Vv,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d + +:vdeal Vdd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x4 & Vdd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) { + Vdd5 = vdeal_VwVwR(Vu_0812,Vz_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt):nomatch" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vlut16_VbVhR_nomatch; + +:vlut16^":nomatch" VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x4 & vss5 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VddH_0004 = vlut16_VbVhR_nomatch(vss5,VuB_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vlut32or_VbVbVbR; + +:vlut32|= VdB_0004,VuB_0812,VzB_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x5 & vs5 & VdB_0004 & VuB_0812 & VzB_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = vlut32or_VbVbVbR(vs5,VuB_0812,VzB_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop vlut16_VbVhR; + +:vlut16 VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x6 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VddH_0004 = vlut16_VbVhR(VuB_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vlut16or_WhVbVhR; + +:vlut16|= VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x7 & vss5 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VddH_0004 = vlut16or_WhVbVhR(vss5,VuB_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 1 u u u u u i i i x x x x x + +define pcodeop vlut32or_VbVbVbI; + +:vlut32|= VdB_0004,VuB_0812,VvB_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x1 & vs5 & VdB_0004 & VuB_0812 & VvB_1620 & Uimm8_0507 & $(END_PACKET) { + VdB_0004 = vlut32or_VbVbVbI(vs5,VuB_0812,VvB_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 1 u u u u u i i i x x x x x + +define pcodeop vlut16or_WhVbVhI; + +:vlut16|= VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x1 & vss5 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) { + VddH_0004 = vlut16or_WhVbVhI(vss5,VuB_0812,VvH_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 0 u u u u u i i i d d d d d + +define pcodeop vlut16_VbVhI; + +:vlut16 VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x73 & op13=0x0 & vss5 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) { + VddH_0004 = vlut16_VbVhI(vss5,VuB_0812,VvH_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vunpack -- "Vdd.uh=vunpack(Vu.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Wuh_vunpack_Vub; + +:vunpack VddUH_0004,VuUB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x0 & VddUH_0004 & VuUB_0812 & $(END_PACKET) { + VddUH_0004 = Wuh_vunpack_Vub(VuUB_0812); + build EndPacket; +} + +# (hvx,1) vunpack -- "Vdd.uw=vunpack(Vu.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Wuw_vunpack_Vuh; + +:vunpack VddUW_0004,VuUH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x1 & VddUW_0004 & VuUH_0812 & $(END_PACKET) { + VddUW_0004 = Wuw_vunpack_Vuh(VuUH_0812); + build EndPacket; +} + +# (hvx,1) vunpack -- "Vdd.h=vunpack(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Wh_vunpack_Vb; + +:vunpack VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x2 & VddH_0004 & VuB_0812 & $(END_PACKET) { + VddH_0004 = Wh_vunpack_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vunpack -- "Vdd.w=vunpack(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Ww_vunpack_Vh; + +:vunpack VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x3 & VddW_0004 & VuH_0812 & $(END_PACKET) { + VddW_0004 = Ww_vunpack_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vunpacko -- "Vxx.h|=vunpacko(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vunpackoor_WhVb; + +:vunpacko|= VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x0 & vss5 & VddH_0004 & VuB_0812 & $(END_PACKET) { + VddH_0004 = vunpackoor_WhVb(vss5,VuB_0812); + build EndPacket; +} + +# (hvx,1) vunpacko -- "Vxx.w|=vunpacko(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vunpackoor_WwVh; + +:vunpacko|= VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x1 & vss5 & VddW_0004 & VuH_0812 & $(END_PACKET) { + VddW_0004 = vunpackoor_WwVh(vss5,VuH_0812); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vvv.w).h=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 1 0 w w w w w + +define pcodeop vscatter_RMWwV; + +:vscatter.h rt5,mu,VuuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x2 & rt5 & mu & VuuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_RMWwV(rt5,mu,VuuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vvv.w).h+=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 1 0 w w w w w + +define pcodeop vscatteracc_RMWwV; + +:vscatter.h+= rt5,mu,VuuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x6 & rt5 & mu & VuuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatteracc_RMWwV(rt5,mu,VuuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "if (Qs4) vscatter(Rt,Mu,Vvv.w).h=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 1 0 1 t t t t t P P u v v v v v 0 s s w w w w w + +define pcodeop vscatter_QRMWwV; + +:vscatter.h^".if("^qv0506^")" rt5,mu,VuuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x7d & op7=0x0 & qv0506 & rt5 & mu & VuuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_QRMWwV(qv0506,rt5,mu,VuuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vv.w).w=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 0 w w w w w + +define pcodeop vscatter_RMVwV; + +:vscatter.w rt5,mu,VuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x0 & rt5 & mu & VuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_RMVwV(rt5,mu,VuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vv.h).h=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 1 w w w w w + +define pcodeop vscatter_RMVhV; + +:vscatter.h rt5,mu,VuH_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x1 & rt5 & mu & VuH_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_RMVhV(rt5,mu,VuH_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vv.w).w+=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 0 w w w w w + +define pcodeop vscatteracc_RMVwV; + +:vscatter.w+= rt5,mu,VuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x4 & rt5 & mu & VuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatteracc_RMVwV(rt5,mu,VuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vv.h).h+=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 1 w w w w w + +define pcodeop vscatteracc_RMVhV; + +:vscatter.h+= rt5,mu,VuH_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x5 & rt5 & mu & VuH_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatteracc_RMVhV(rt5,mu,VuH_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "if (Qs4) vscatter(Rt,Mu,Vv.w).w=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 0 s s w w w w w + +define pcodeop vscatter_QRMVwV; + +:vscatter.w^".if("^qv0506^")" rt5,mu,VuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x7c & op7=0x0 & qv0506 & rt5 & mu & VuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_QRMVwV(qv0506,rt5,mu,VuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "if (Qs4) vscatter(Rt,Mu,Vv.h).h=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 1 s s w w w w w + +define pcodeop vscatter_QRMVhV; + +:vscatter.h^".if("^qv0506^")" rt5,mu,VuH_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x7c & op7=0x1 & qv0506 & rt5 & mu & VuH_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_QRMVhV(qv0506,rt5,mu,VuH_0812,Vs_0004); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vb_vasr_VhVhR_sat; + +:vasr^":sat" VdB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x0 & VdB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = Vb_vasr_VhVhR_sat(VuH_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vasr_VhVhR_rnd_sat; + +:vasr^":rnd:sat" VdUH_0004,VuUW_0812,VzUW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuUW_0812 & VzUW_1923 & rt1618 & $(END_PACKET) { + VdUH_0004 = vasr_VhVhR_rnd_sat(VuUW_0812,VzUW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vuh_vasr_VwVwR_rnd_sat; + +:vasr^":rnd:sat" VdUH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_VwVwR_rnd_sat(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vub_vasr_VuhVuhR_rnd_sat; + +:vasr^":rnd:sat" VdUB_0004,VuUH_0812,VzUH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x7 & VdUB_0004 & VuUH_0812 & VzUH_1923 & rt1618 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_VuhVuhR_rnd_sat(VuUH_0812,VzUH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop Vuh_vasr_VuwVuwR_sat; + +:vasr^":sat" VdUH_0004,VuUW_0812,VzUW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x1 & op0507=0x4 & VdUH_0004 & VuUW_0812 & VzUW_1923 & rt1618 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_VuwVuwR_sat(VuUW_0812,VzUW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop Vub_vasr_VuhVuhR_sat; + +:vasr^":sat" VdUB_0004,VuUH_0812,VzUH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x1 & op0507=0x5 & VdUB_0004 & VuUH_0812 & VzUH_1923 & rt1618 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_VuhVuhR_sat(VuUH_0812,VzUH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vh_vasr_VwVwR; + +:vasr VdH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x2 & VdH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdH_0004 = Vh_vasr_VwVwR(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vh_vasr_VwVwR_sat; + +:vasr^":sat" VdH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x3 & VdH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdH_0004 = Vh_vasr_VwVwR_sat(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vh_vasr_VwVwR_rnd_sat; + +:vasr^":rnd:sat" VdH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x4 & VdH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdH_0004 = Vh_vasr_VwVwR_rnd_sat(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vuh_vasr_VwVwR_sat; + +:vasr^":sat" VdUH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x5 & VdUH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_VwVwR_sat(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vub_vasr_VhVhR_sat; + +:vasr^":sat" VdUB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x6 & VdUB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_VhVhR_sat(VuH_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vub_vasr_VhVhR_rnd_sat; + +:vasr^":rnd:sat" VdUB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x7 & VdUB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_VhVhR_rnd_sat(VuH_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop Vb_vasr_VhVhR_rnd_sat; + +:vasr^":rnd:sat" VdB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x0 & VdB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = Vb_vasr_VhVhR_rnd_sat(VuH_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) prefixsum -- "Vd.b=prefixsum(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 0 0 1 0 d d d d d + +define pcodeop Vb_prefixsum_Q; + +:prefixsum VdB_0004,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0810=0x0 & op0507=0x2 & VdB_0004 & qv2223 & $(END_PACKET) { + VdB_0004 = Vb_prefixsum_Q(qv2223); + build EndPacket; +} + +# (hvx,1) prefixsum -- "Vd.h=prefixsum(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 1 0 1 0 d d d d d + +define pcodeop Vh_prefixsum_Q; + +:prefixsum VdH_0004,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0810=0x1 & op0507=0x2 & VdH_0004 & qv2223 & $(END_PACKET) { + VdH_0004 = Vh_prefixsum_Q(qv2223); + build EndPacket; +} + +# (hvx,1) prefixsum -- "Vd.w=prefixsum(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 1 0 0 1 0 d d d d d + +define pcodeop Vw_prefixsum_Q; + +:prefixsum VdW_0004,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0810=0x2 & op0507=0x2 & VdW_0004 & qv2223 & $(END_PACKET) { + VdW_0004 = Vw_prefixsum_Q(qv2223); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d + +define pcodeop Vqf16_vadd_Vqf16Vqf16; + +:vadd VdQF16_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x2 & VdQF16_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vadd_Vqf16Vqf16(VuQF16_0812,VvQF16_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf16=vadd(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop Vqf16_vadd_VhfVhf; + +:vadd VdQF16_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x3 & VdQF16_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vadd_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop Vqf16_vadd_Vqf16Vhf; + +:vadd VdQF16_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x4 & VdQF16_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vadd_Vqf16Vhf(VuQF16_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop Vqf32_vadd_Vqf32Vqf32; + +:vadd VdQF32_0004,VuQF32_0812,VvQF32_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x0 & VdQF32_0004 & VuQF32_0812 & VvQF32_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vadd_Vqf32Vqf32(VuQF32_0812,VvQF32_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf32=vadd(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop Vqf32_vadd_VsfVsf; + +:vadd VdQF32_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x1 & VdQF32_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vadd_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d + +define pcodeop Vqf32_vadd_Vqf32Vsf; + +:vadd VdQF32_0004,VuQF32_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x2 & VdQF32_0004 & VuQF32_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vadd_Vqf32Vsf(VuQF32_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vasl -- "Vx.w+=vasl(Vu.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vaslacc_VwVwR; + +:vasl+= VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) { + VdW_0004 = vaslacc_VwVwR(vs5,VuW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vx.w+=vasr(Vu.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vasracc_VwVwR; + +:vasr+= VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x5 & vs5 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) { + VdW_0004 = vasracc_VwVwR(vs5,VuW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vx.h+=vasr(Vu.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vasracc_VhVhR; + +:vasr+= VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x7 & vs5 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) { + VdH_0004 = vasracc_VhVhR(vs5,VuH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasl -- "Vx.h+=vasl(Vu.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vaslacc_VhVhR; + +:vasl+= VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x5 & vs5 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) { + VdH_0004 = vaslacc_VhVhR(vs5,VuH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.w=vasr(Vu.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vasr_VwR; + +:vasr VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x5 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) { + VdW_0004 = vasr_VwR(VuW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vasr_VhR; + +:vasr VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) { + VdH_0004 = vasr_VhR(VuH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasl -- "Vd.w=vasl(Vu.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vasl_VwR; + +:vasl VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) { + VdW_0004 = vasl_VwR(VuW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasl -- "Vd.h=vasl(Vu.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vasl_VhR; + +:vasl VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x0 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) { + VdH_0004 = vasl_VhR(VuH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.uw=vlsr(Vu.uw,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vlsr_VuwR; + +:vlsr VdUW_0004,VuUW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x1 & VdUW_0004 & VuUW_0812 & rx5 & $(END_PACKET) { + VdUW_0004 = vlsr_VuwR(VuUW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.uh=vlsr(Vu.uh,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vlsr_VuhR; + +:vlsr VdUH_0004,VuUH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & rx5 & $(END_PACKET) { + VdUH_0004 = vlsr_VuhR(VuUH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.ub=vlsr(Vu.ub,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vlsr_VubR; + +:vlsr VdUB_0004,VuUB_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x3 & VdUB_0004 & VuUB_0812 & rx5 & $(END_PACKET) { + VdUB_0004 = vlsr_VubR(VuUB_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.w=vasr(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vasr_VwVw; + +:vasr VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vasr_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.w=vlsr(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vlsr_VwVw; + +:vlsr VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vlsr_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.h=vlsr(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vlsr_VhVh; + +:vlsr VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x2 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vlsr_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vasr_VhVh; + +:vasr VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vasr_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vasl -- "Vd.w=vasl(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vasl_VwVw; + +:vasl VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vasl_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vasl -- "Vd.h=vasl(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vasl_VhVh; + +:vasl VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x5 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vasl_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vuh_vasr_WwVuh_sat; + +:vasr^":sat" VdUH_0004,VuuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x0 & VdUH_0004 & VuuW_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_WwVuh_sat(VuuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vuh_vasr_WwVuh_rnd_sat; + +:vasr^":rnd:sat" VdUH_0004,VuuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuuW_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_WwVuh_rnd_sat(VuuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vub_vasr_WuhVub_sat; + +:vasr^":sat" VdUB_0004,VuuUH_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x2 & VdUB_0004 & VuuUH_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_WuhVub_sat(VuuUH_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vub_vasr_WuhVub_rnd_sat; + +:vasr^":rnd:sat" VdUB_0004,VuuUH_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x3 & VdUB_0004 & VuuUH_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_WuhVub_rnd_sat(VuuUH_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) "Vd.sf=Vu.qf32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop Vsf_equals_Vqf32; + +:assign VdSF_0004,VuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x0 & VdSF_0004 & VuQF32_0812 & $(END_PACKET) { + VdSF_0004 = Vsf_equals_Vqf32(VuQF32_0812); + build EndPacket; +} + +# (hvx,1) "Vd.hf=Vu.qf16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop Vhf_equals_Vqf16; + +:assign VdHF_0004,VuQF16_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x3 & VdHF_0004 & VuQF16_0812 & $(END_PACKET) { + VdHF_0004 = Vhf_equals_Vqf16(VuQF16_0812); + build EndPacket; +} + +# (hvx,1) "Vd.hf=Vuu.qf32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop Vhf_equals_Wqf32; + +:assign VdHF_0004,VuuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x6 & VdHF_0004 & VuuQF32_0812 & $(END_PACKET) { + VdHF_0004 = Vhf_equals_Wqf32(VuuQF32_0812); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.h=vround(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vh_vround_VwVw_sat; + +:vround^":sat" VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x4 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vround_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.uh=vround(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vuh_vround_VwVw_sat; + +:vround^":sat" VdUH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x5 & VdUH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vround_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.b=vround(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vb_vround_VhVh_sat; + +:vround^":sat" VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x6 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdB_0004 = Vb_vround_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.ub=vround(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vub_vround_VhVh_sat; + +:vround^":sat" VdUB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x7 & VdUB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vround_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.ub=vround(Vu.uh,Vv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vub_vround_VuhVuh_sat; + +:vround^":sat" VdUB_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x3 & VdUB_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vround_VuhVuh_sat(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.uh=vround(Vu.uw,Vv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vuh_vround_VuwVuw_sat; + +:vround^":sat" VdUH_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x4 & VdUH_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vround_VuwVuw_sat(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vrotr -- "Vd.uw=vrotr(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop Vuw_vrotr_VuwVuw; + +:vrotr VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x54 & op13=0x1 & op0507=0x7 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = Vuw_vrotr_VuwVuw(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop Vqf16_vsub_Vqf16Vqf16; + +:vsub VdQF16_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x5 & VdQF16_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vsub_Vqf16Vqf16(VuQF16_0812,VvQF16_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf16=vsub(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop Vqf16_vsub_VhfVhf; + +:vsub VdQF16_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x6 & VdQF16_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vsub_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop Vqf16_vsub_Vqf16Vhf; + +:vsub VdQF16_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x7 & VdQF16_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vsub_Vqf16Vhf(VuQF16_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop Vqf32_vsub_Vqf32Vqf32; + +:vsub VdQF32_0004,VuQF32_0812,VvQF32_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x3 & VdQF32_0004 & VuQF32_0812 & VvQF32_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vsub_Vqf32Vqf32(VuQF32_0812,VvQF32_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf32=vsub(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop Vqf32_vsub_VsfVsf; + +:vsub VdQF32_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x4 & VdQF32_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vsub_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop Vqf32_vsub_Vqf32Vsf; + +:vsub VdQF32_0004,VuQF32_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x5 & VdQF32_0004 & VuQF32_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vsub_Vqf32Vsf(VuQF32_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcl0 -- "Vd.uw=vcl0(Vu.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vuw_vcl0_Vuw; + +:vcl0 VdUW_0004,VuUW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x5 & VdUW_0004 & VuUW_0812 & $(END_PACKET) { + VdUW_0004 = Vuw_vcl0_Vuw(VuUW_0812); + build EndPacket; +} + +# (hvx,1) vpopcount -- "Vd.h=vpopcount(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vh_vpopcount_Vh; + +:vpopcount VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = Vh_vpopcount_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vcl0 -- "Vd.uh=vcl0(Vu.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vuh_vcl0_Vuh; + +:vcl0 VdUH_0004,VuUH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x7 & VdUH_0004 & VuUH_0812 & $(END_PACKET) { + VdUH_0004 = Vuh_vcl0_Vuh(VuUH_0812); + build EndPacket; +} + +# (hvx,1) vnormamt -- "Vd.w=vnormamt(Vu.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vw_vnormamt_Vw; + +:vnormamt VdW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & $(END_PACKET) { + VdW_0004 = Vw_vnormamt_Vw(VuW_0812); + build EndPacket; +} + +# (hvx,1) vnormamt -- "Vd.h=vnormamt(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vh_vnormamt_Vh; + +:vnormamt VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0507=0x5 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = Vh_vnormamt_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.h=vadd(vclb(Vu.h),Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_vclb_VhVh; + +:vadd VdH_0004,"vclb("^VuH_0812^")",VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x0 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + build EndPacket; + <> + VdH_0004 = vadd_vclb_VhVh(VuH_0812,VvH_1620); +} + +# (hvx,1) vadd -- "Vd.w=vadd(vclb(Vu.w),Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop vadd_vclb_VwVw; + +:vadd VdW_0004,"vclb("^VuW_0812^")",VvW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + build EndPacket; + <> + VdW_0004 = vadd_vclb_VwVw(VuW_0812,VvW_1620); +} + +# (hvx,2) "if (Qv4) vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (Qv4) vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 1 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 1 s s s s s + +define pcodeop vmemStoreIf; # aligned store of vector bytes where corresponding predicate bit is set + +:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x44 & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxS4, Vs_0004); +} + +# (hvx,2) "if (Qv4) vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (Qv4) vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 1 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 1 s s s s s + +:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x4c & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxAIS3, Vs_0004); +} + +# (hvx,2) "if (Qv4) vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 0 s s s s s +# +# (hvx,2) "if (Qv4) vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 0 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 1 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 1 s s s s s + +:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x5c & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxAIMu, Vs_0004); +} + +# (hvx,2) "vmem(Rt+#s4)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 0 s s s +# +# (hvx,2) "vmem(Rt+#s4):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 1 - - s s s + +:vmem^ntHint22 VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x1 & op3=0x0 & ntHint22 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) { + build EndPacket; + <> + VAlignMemAddrRxS4 = VNreg0002; +} + +# (hvx,2) "if (Pv) vmem(Rt+#s4)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 0 0 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rt+#s4)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 1 0 1 s s s +# +# (hvx,2) "if (Pv) vmem(Rt+#s4):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 0 1 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rt+#s4):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 1 1 1 s s s +# +# NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op21=1 & op2327=0x11 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxS4 = VNreg0002; + +} + +# (hvx,2) "vmem(Rx++#s3)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 0 s s s +# +# (hvx,2) "vmem(Rx++#s3):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 1 - - s s s + +:vmem^ntHint22 VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x1 & op3=0x0 & ntHint22 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VAlignMemAddrRxAIS3 = VNreg0002; +} + +# (hvx,2) "if (Pv) vmem(Rx++#s3)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 0 0 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++#s3)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 1 0 1 s s s +# +# (hvx,2) "if (Pv) vmem(Rx++#s3):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 0 1 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++#s3):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 1 1 1 s s s +# +# NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op21=1 & op2327=0x13 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxAIS3 = VNreg0002; + +} + +# (hvx,2) "vmem(Rx++Mu)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 0 s s s +# +# (hvx,2) "vmem(Rx++Mu):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 1 - - s s s + +:vmem^ntHint22 VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x1 & op3=0x0 & ntHint22 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VAlignMemAddrRxAIMu = VNreg0002; +} + +# (hvx,2) "if (Pv) vmem(Rx++Mu)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 0 0 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++Mu)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 1 0 1 s s s +# +# (hvx,2) "if (Pv) vmem(Rx++Mu):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 0 1 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++Mu):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 1 1 1 s s s +# +# NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op21=1 & op2327=0x17 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxAIMu = VNreg0002; + +} + +# (hvx,2) "vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 0 s s s s s +# +# (hvx,2) "vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 0 s s s s s + +:vmem^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x10 & op0507=0x0 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + VAlignMemAddrRxS4 = Vs_0004; +} + +# (hvx,2) "if (Pv) vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 1 s s s s s +# +# (hvx,2) "if (Pv) vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 1 s s s s s + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x11 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxS4 = Vs_0004; + +} + +# (hvx,2) "vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 0 s s s s s +# +# (hvx,2) "vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 0 s s s s s + +:vmem^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x12 & op0607=0x0 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VAlignMemAddrRxAIS3 = Vs_0004; +} + +# (hvx,2) "if (Pv) vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 1 s s s s s +# +# (hvx,2) "if (Pv) vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 1 s s s s s + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x13 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxAIS3 = Vs_0004; + +} + +# (hvx,2) "vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 0 s s s s s +# +# (hvx,2) "vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 0 s s s s s + +:vmem^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x16 & op0507=0x0 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VAlignMemAddrRxAIMu = Vs_0004; +} + +# (hvx,2) "if (Pv) vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 1 s s s s s +# +# (hvx,2) "if (Pv) vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 1 s s s s s + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x17 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxAIMu = Vs_0004; + +} + +# (hvx,2) "vmemu(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 1 1 1 s s s s s + +:vmemu VMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x7 & VMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + VMemAddrRxS4 = Vs_0004; +} + +# (hvx,2) "if (Pv) vmemu(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 0 s s s s s +# +# (hvx,2) "if (!Pv) vmemu(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 1 s s s s s +# + +:vmemu^VPuCond1112_S05 VMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x45 & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VMemAddrRxS4 = Vs_0004; + +} + +# (hvx,2) "vmemu(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 1 1 1 s s s s s + +:vmemu VMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x7 & VMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VMemAddrRxAIS3 = Vs_0004; +} + +# +# (hvx,2) "if (Pv) vmemu(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 0 s s s s s +# +# (hvx,2) "if (!Pv) vmemu(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 1 s s s s s + +:vmemu^VPuCond1112_S05 VMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x4d & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VMemAddrRxAIS3 = Vs_0004; + +} + +# (hvx,2) "vmemu(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 1 1 1 s s s s s + +:vmemu VMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x7 & VMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VMemAddrRxAIMu = Vs_0004; +} + +# (hvx,2) "if (Pv) vmemu(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 0 s s s s s +# +# (hvx,2) "if (!Pv) vmemu(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 1 s s s s s + +:vmemu^VPuCond1112_S05 VMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x5d & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VMemAddrRxAIMu = Vs_0004; + +} + +# +# NOTE: vmem scatter_release is specific to the V66 to address a V60/V61 pipeline issue where an +# explicit release was required to avoid a scatter storage hazard. These vmem instructions were +# a microarchitectural workaround that existed only for V60‑class cores and was never part of the +# stable, forward‑compatible HVX ISA. +# + +define pcodeop scatter_release; + +# (hvx,2) vmem -- "vmem(Rt+#s4):scatter_release" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 1 - - - + +:vmem^":scatter_release" VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxS4 & $(END_PACKET) { + build EndPacket; + <> + scatter_release(VAlignMemAddrRxS4); +} + +# (hvx,2) vmem -- "vmem(Rx++#s3):scatter_release" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 1 - - - + +:vmem^":scatter_release" VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxAIS3 & $(END_PACKET) { + build EndPacket; + <> + scatter_release(VAlignMemAddrRxAIS3); +} + +# (hvx,2) vmem -- "vmem(Rx++Mu):scatter_release" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 1 - - - + +:vmem^":scatter_release" VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxAIMu & $(END_PACKET) { + build EndPacket; + <> + scatter_release(VAlignMemAddrRxAIMu); +} + + diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_hvx.txt b/pypcode/processors/Hexagon/data/languages/hexagon_hvx.txt new file mode 100644 index 00000000..6a8dc214 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon_hvx.txt @@ -0,0 +1,618 @@ +Hexagon V69 HVX instruction patterns + +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 0 1 0 0 - - - - - vwhist256 +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 1 1 0 0 - - - - - vwhist256:sat +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 0 - 1 0 0 - - - - - vwhist128 +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 1 i 1 0 0 - - - - - vwhist128(#u1) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 0 1 0 0 - - - - - vwhist256(Qv4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 1 1 0 0 - - - - - vwhist256(Qv4):sat +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 0 - 1 0 0 - - - - - vwhist128(Qv4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 1 i 1 0 0 - - - - - vwhist128(Qv4,#u1) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 0 d d Qd4=and(Qs4,Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 1 d d Qd4=or(Qs4,Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 1 d d Qd4=xor(Qs4,Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 0 d d Qd4=or(Qs4,!Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d Qd4=and(Qs4,!Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 0 d d Qd4.b=vshuffe(Qs4.h,Qt4.h) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 1 d d Qd4.h=vshuffe(Qs4.w,Qt4. +0 0 0 1 1 0 1 0 0 1 0 v v v v v P P - u u u u u - s s d d d d d if (!Ps) Vdd=vcombine(Vu,Vv) +0 0 0 1 1 0 1 0 0 1 1 v v v v v P P - u u u u u - s s d d d d d if (Ps) Vdd=vcombine(Vu,Vv) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd=vcombine(Vu,Vv) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vshuffoe(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.b=vshuffoe(Vu.b,Vv.b) +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 1 u u u u u - t t d d d d d Vdd=vswap(Qt4,Vu,Vv) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 1 d d d d d Vdd.uh=vzxt(Vu.ub) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 0 d d d d d Vdd.uw=vzxt(Vu.uh) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 1 d d d d d Vdd.h=vsxt(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vsxt(Vu.h) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.b=vadd(Vuu.b,Vvv.b) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vadd(Vuu.h,Vvv.h) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.w=vadd(Vuu.w,Vvv.w) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.ub=vadd(Vuu.ub,Vvv.ub):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.uh=vadd(Vuu.uh,Vvv.uh):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vdd.h=vadd(Vuu.h,Vvv.h):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vdd.w=vadd(Vuu.w,Vvv.w):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.b=vsub(Vuu.b,Vvv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.h=vsub(Vuu.h,Vvv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.w=vsub(Vuu.w,Vvv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.ub=vsub(Vuu.ub,Vvv.ub):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.uh=vsub(Vuu.uh,Vvv.uh):sat +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.h=vsub(Vuu.h,Vvv.h):sat +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vdd.w=vsub(Vuu.w,Vvv.w):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.b=vadd(Vuu.b,Vvv.b):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vdd.b=vsub(Vuu.b,Vvv.b):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vdd.uw=vadd(Vuu.uw,Vvv.uw):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.uw=vsub(Vuu.uw,Vvv.uw):sat +0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 0 d d Qd4=not(Qs4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 0 d d d d d Vd=vand(Qv4,Vu) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 1 d d d d d Vd=vand(!Qv4,Vu) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.ub=vmin(Vu.ub,Vv.ub) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vmin(Vu.uh,Vv.uh) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vmin(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.w=vmin(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.ub=vmax(Vu.ub,Vv.ub) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.uh=vmax(Vu.uh,Vv.uh) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.h=vmax(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmax(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.b=vmin(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.b=vmax(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.sf=vmax(Vu.sf,Vv.sf) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.sf=vmin(Vu.sf,Vv.sf) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.hf=vmax(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.hf=vmin(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 0 d d d d d Vd.h=vabs(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 1 d d d d d Vd.h=vabs(Vu.h):sat +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 0 d d d d d Vd.w=vabs(Vu.w) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 1 d d d d d Vd.w=vabs(Vu.w):sat +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 0 d d d d d Vd.b=vabs(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 1 d d d d d Vd.b=vabs(Vu.b):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vadd(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.ub=vadd(Vu.ub,Vv.ub):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vadd(Vu.uh,Vv.uh):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vadd(Vu.h,Vv.h):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.w=vadd(Vu.w,Vv.w):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.b=vsub(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.h=vsub(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.w=vsub(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.ub=vsub(Vu.ub,Vv.ub):sat +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vsub(Vu.uh,Vv.uh):sat +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.h=vsub(Vu.h,Vv.h):sat +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.w=vsub(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.ub=vadd(Vu.ub,Vv.b):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.ub=vsub(Vu.ub,Vv.b):sat +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.b=vadd(Vu.b,Vv.b):sat +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.b=vsub(Vu.b,Vv.b):sat +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uw=vadd(Vu.uw,Vv.uw):sat +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.b=vadd(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.h=vadd(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.uw=vsub(Vu.uw,Vv.uw):sat +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 0 x x d d d d d Vd.w=vadd(Vu.w,Vv.w,Qx4):carry +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 1 x x d d d d d Vd.w=vsub(Vu.w,Vv.w,Qx4):carry +0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 0 s s d d d d d Vd.w=vadd(Vu.w,Vv.w,Qs4):carry:sat +0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 0 e e d d d d d Vd.w,Qe4=vadd(Vu.w,Vv.w):carry +0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 1 e e d d d d d Vd.w,Qe4=vsub(Vu.w,Vv.w):carry +1 1 0 0 0 0 1 0 1 1 0 s s s s s P P - t t t t t - x x d d d d d Rdd=add(Rss,Rtt,Px):carry +1 1 0 0 0 0 1 0 1 1 1 s s s s s P P - t t t t t - x x d d d d d Rdd=sub(Rss,Rtt,Px):carry +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd=vand(Vu,Vv) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd=vor(Vu,Vv) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd=vxor(Vu,Vv) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 0 0 d d d d d Vd=vnot(Vu) +0 0 0 1 1 0 1 0 0 0 0 - - - - - P P - u u u u u - s s d d d d d if (Ps) Vd=Vu +0 0 0 1 1 0 1 0 0 0 1 - - - - - P P - u u u u u - s s d d d d d if (!Ps) Vd=Vu +0 0 0 1 1 1 1 0 - - 0 - - 0 1 1 P P 1 u u u u u 1 1 1 d d d d d Vd=Vu +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 0 d d d d d Vd.tmp=Vu +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.tmp=vcombine(Vu,Vv) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.ub=vavg(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vavg(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.h=vavg(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.w=vavg(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.b=vnavg(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.h=vnavg(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.w=vnavg(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vavg(Vu.ub,Vv.ub):rnd +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.uh=vavg(Vu.uh,Vv.uh):rnd +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.h=vavg(Vu.h,Vv.h):rnd +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.w=vavg(Vu.w,Vv.w):rnd +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.uw=vavg(Vu.uw,Vv.uw) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.uw=vavg(Vu.uw,Vv.uw):rnd +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.b=vavg(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.b=vavg(Vu.b,Vv.b):rnd +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d Vd.b=vnavg(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 0 x x Qx4&=vcmp.eq(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 1 x x Qx4&=vcmp.eq(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 1 0 x x Qx4&=vcmp.eq(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 0 x x Qx4&=vcmp.gt(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 1 x x Qx4&=vcmp.gt(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 1 0 x x Qx4&=vcmp.gt(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 0 x x Qx4&=vcmp.gt(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 1 x x Qx4&=vcmp.gt(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 1 0 x x Qx4&=vcmp.gt(Vu.uw,Vv.uw) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 0 x x Qx4|=vcmp.gt(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 1 x x Qx4|=vcmp.gt(Vu.hf,Vv.hf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 0 x x Qx4|=vcmp.eq(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 1 x x Qx4|=vcmp.eq(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 1 0 x x Qx4|=vcmp.eq(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 0 x x Qx4|=vcmp.gt(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 1 x x Qx4|=vcmp.gt(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 1 0 x x Qx4|=vcmp.gt(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 0 x x Qx4|=vcmp.gt(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 1 x x Qx4|=vcmp.gt(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 1 0 x x Qx4|=vcmp.gt(Vu.uw,Vv.uw) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 0 d d Qd4=vcmp.gt(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 1 d d Qd4=vcmp.gt(Vu.hf,Vv.hf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 0 x x Qx4^=vcmp.eq(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 1 x x Qx4^=vcmp.eq(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 1 0 x x Qx4^=vcmp.eq(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 0 x x Qx4^=vcmp.gt(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 1 x x Qx4^=vcmp.gt(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 1 0 x x Qx4^=vcmp.gt(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 0 x x Qx4^=vcmp.gt(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 1 x x Qx4^=vcmp.gt(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 1 0 x x Qx4^=vcmp.gt(Vu.uw,Vv.uw) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 0 x x Qx4&=vcmp.gt(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 1 x x Qx4&=vcmp.gt(Vu.hf,Vv.hf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 0 x x Qx4^=vcmp.gt(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 1 x x Qx4^=vcmp.gt(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 0 d d Qd4=vcmp.eq(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 1 d d Qd4=vcmp.eq(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 1 0 d d Qd4=vcmp.eq(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 0 d d Qd4=vcmp.gt(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 1 d d Qd4=vcmp.gt(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 1 0 d d Qd4=vcmp.gt(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 0 d d Qd4=vcmp.gt(Vu.ub,Vv.ub) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 1 d d Qd4=vcmp.gt(Vu.uh,Vv.uh) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 1 0 d d Qd4=vcmp.gt(Vu.uw,Vv.uw) +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 0 x x x x x if (Qv4) Vx.b+=Vu.b +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 1 x x x x x if (Qv4) Vx.h+=Vu.h +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 0 x x x x x if (Qv4) Vx.w+=Vu.w +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x if (!Qv4) Vx.b+=Vu.b +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x if (!Qv4) Vx.h+=Vu.h +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 1 x x x x x if (!Qv4) Vx.w+=Vu.w +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 0 x x x x x if (Qv4) Vx.b-=Vu.b +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 1 x x x x x if (Qv4) Vx.h-=Vu.h +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 0 x x x x x if (Qv4) Vx.w-=Vu.w +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 1 x x x x x if (!Qv4) Vx.b-=Vu.b +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 0 x x x x x if (!Qv4) Vx.h-=Vu.h +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 1 x x x x x if (!Qv4) Vx.w-=Vu.w +0 0 0 1 1 1 1 0 1 1 1 v v v v v P P 1 u u u u u - t t d d d d d Vd=vmux(Qt4,Vu,Vv) +0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.w=vsatdw(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.uh=vsat(Vu.uw,Vv.uw) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.ub=vsat(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vsat(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.b=vshuffe(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.b=vshuffo(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vshuffe(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.h=vshuffo(Vu.h,Vv.h) +1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 u u u u u 0 0 1 d d d d d Rd=vextract(Vu,Rs) +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 1 0 - - - v v v v v vtmp.h=vgather(Rt,Mu,Vvv.w).h +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 1 0 - s s v v v v v if (Qs4) vtmp.h=vgather(Rt,Mu,Vvv.w).h +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 0 - - - v v v v v vtmp.w=vgather(Rt,Mu,Vv.w).w +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 1 - - - v v v v v vtmp.h=vgather(Rt,Mu,Vv.h).h +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 0 - s s v v v v v if (Qs4) vtmp.w=vgather(Rt,Mu,Vv.w).w +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 1 - s s v v v v v if (Qs4) vtmp.h=vgather(Rt,Mu,Vv.h).h +0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++#s3):nt +0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d Vd=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d Vd=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++Mu):nt +0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++#s3):nt +0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d Vd.cur=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d Vd.cur=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++Mu):nt +0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++#s3):nt +0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d Vd.tmp=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d Vd.tmp=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++Mu):nt +0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 1 1 1 d d d d d Vd=vmemu(Rt+#s4) +0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 1 1 1 d d d d d Vd=vmemu(Rx++#s3) +0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 1 1 1 d d d d d Vd=vmemu(Rx++Mu) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 0 i i x x x x x Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):v +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 1 i i x x x x x Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):h +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 0 i i d d d d d Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):v +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 1 i i d d d d d Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):h +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 0 x x x x x Vxx.w+=vadd(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x Vxx.w+=vadd(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x Vxx.h+=vadd(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vdd.h=vadd(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.w=vadd(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vadd(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vsub(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.w=vsub(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.w=vsub(Vu.h,Vv.h) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vdd.h=vdmpy(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x Vxx.h+=vdmpy(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd.w=vdmpy(Vuu.h,Rt.uh,#1):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vd.w=vdmpy(Vuu.h,Rt.h):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vdmpy(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vx.w+=vdmpy(Vuu.h,Rt.uh,#1):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vdmpy(Vuu.h,Rt.h):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vxx.w+=vdmpy(Vuu.h,Rt.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vdmpy(Vu.h,Vv.h):sat +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vd.h=vlut4(Vu.uh,Rtt.h) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vx.h=vmpa(Vx.h,Vu.h,Rtt.h):sat +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh):sat +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vdd.h=vmpa(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vdd.w=vmpa(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vxx.h+=vmpa(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 1 x x x x x Vxx.w+=vmpa(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vdd.h=vmpa(Vuu.ub,Rt.ub) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vdd.w=vmpa(Vuu.uh,Rt.b) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vxx.w+=vmpa(Vuu.uh,Rt.b) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vxx.h+=vmpa(Vuu.ub,Rt.ub) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.h=vmpa(Vuu.ub,Vvv.b) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.h=vmpa(Vuu.ub,Vvv.ub) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vxx.h+=vmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vdd.w=vmpy(Vu.h,Rt.h) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vdd.uw=vmpy(Vu.uh,Rt.uh) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.w+=vmpy(Vu.h,Rt.h):sat +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vxx.uw+=vmpy(Vu.uh,Rt.uh) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.uh+=vmpy(Vu.ub,Rt.ub) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vxx.w+=vmpy(Vu.h,Rt.h) +0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vdd.uh=vmpy(Vu.ub,Rt.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.h=vmpy(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.uh=vmpy(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.h=vmpy(Vu.ub,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x Vxx.h+=vmpy(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x Vxx.uh+=vmpy(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 1 0 x x x x x Vxx.h+=vmpy(Vu.ub,Vv.b) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.uw=vmpy(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 0 0 x x x x x Vxx.uw+=vmpy(Vu.uh,Vv.uh) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vdd.qf32=vmpy(Vu.qf16,Vv.hf) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.qf16=vmpy(Vu.qf16,Vv.qf16) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.qf16=vmpy(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.qf16=vmpy(Vu.qf16,Vv.hf) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d Vdd.qf32=vmpy(Vu.qf16,Vv.qf16) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vdd.qf32=vmpy(Vu.hf,Vv.hf) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.h=vmpyi(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 0 x x x x x Vx.h+=vmpyi(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 1 x x x x x Vx.w+=vmpyie(Vu.w,Vv.uh) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x Vx.w+=vmpyie(Vu.w,Vv.h) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyie(Vu.w,Vv.uh) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.w=vmpyio(Vu.w,Vv.h) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vmpyi(Vu.w,Rt.h) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vd.w=vmpyi(Vu.w,Rt.h) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vd.qf32=vmpy(Vu.qf32,Vv.qf32) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.qf32=vmpy(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 1 x x x x x Vxx+=vmpyo(Vu.w,Vv.h) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 0 x x x x x Vx.w+=vmpyo(Vu.w,Vv.h):<<1:sat:shift +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x Vx.w+=vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd=vmpye(Vu.w,Vv.uh) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyo(Vu.w,Vv.h):<<1:rnd:sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.w=vmpye(Vu.w,Vv.uh) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.w=vmpyo(Vu.w,Vv.h):<<1:sat +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 0 i d d d d d Vdd.w=vrmpy(Vuu.ub,Rt.b,#u1) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 0 i x x x x x Vxx.w+=vrmpy(Vuu.ub,Rt.b,#u1) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 1 i x x x x x Vxx.uw+=vrmpy(Vuu.ub,Rt.ub,#u1) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 1 i d d d d d Vdd.uw=vrmpy(Vuu.ub,Rt.ub,#u1) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x Vx.uw+=vrmpy(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 1 x x x x x Vx.w+=vrmpy(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vrmpy(Vu.ub,Vv.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vdd.h=vtmpy(Vuu.b,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vdd.h=vtmpy(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.h+=vtmpy(Vuu.b,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vxx.h+=vtmpy(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vxx.w+=vtmpy(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vtmpy(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vdd.uw=vdsad(Vuu.uh,Rt.uh) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.uw+=vdsad(Vuu.uh,Rt.uh) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 1 i d d d d d Vdd.uw=vrsad(Vuu.ub,Rt.ub,#u1) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 1 i x x x x x Vxx.uw+=vrsad(Vuu.ub,Rt.ub,#u1) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.w=vdmpy(Vu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vd.h=vdmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vdmpy(Vu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vx.h+=vdmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.w=vdmpy(Vu.h,Rt.uh):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.w=vdmpy(Vu.h,Rt.h):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vx.w+=vdmpy(Vu.h,Rt.uh):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vdmpy(Vu.h,Rt.h):sat +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.w=vdmpy(Vu.h,Vv.h):sat +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd.h=vmpy(Vu.h,Rt.h):<<1:sat +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.h=vmpy(Vu.h,Rt.h):<<1:md:sat +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.uh=vmpy(Vu.uh,Vv.uh):>>16 +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyieo(Vu.h,Vv.h) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vmpyi(Vu.w,Rt.b) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.h=vmpyi(Vu.h,Rt.b) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vx.h+=vmpyi(Vu.h,Rt.b) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vd.w=vmpyi(Vu.w,Rt.ub) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vx.w+=vmpyi(Vu.w,Rt.ub) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyi(Vu.w,Rt.b) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uw=vmpye(Vu.uh,Rt.uh) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.uw+=vmpye(Vu.uh,Rt.uh) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vd.uw=vrmpy(Vu.ub,Rt.ub) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vd.w=vrmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vx.uw+=vrmpy(Vu.ub,Rt.ub) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.w+=vrmpy(Vu.ub,Rt.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.uw=vrmpy(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.w=vrmpy(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.w=vrmpy(Vu.ub,Vv.b) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - 0 0 0 1 d d d d d Vd=vsplat(Rt) +0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 0 1 d d d d d Vd.h=vsplat(Rt) +0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 1 0 d d d d d Vd.b=vsplat(Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 0 - - - x x Qx4|=vand(Vu,Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 1 0 - 1 0 d d Qd4=vand(Vu,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 0 u u 0 1 1 x x x x x Vx|=vand(Qu4,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 1 u u 0 1 1 x x x x x Vx|=vand(!Qu4,Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 0 u u 1 0 1 d d d d d Vd=vand(Qu4,Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 1 u u 1 0 1 d d d d d Vd=vand(!Qu4,Rt) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.ub=vabsdiff(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vabsdiff(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vabsdiff(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.uw=vabsdiff(Vu.w,Vv.w) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 - - - - - 0 0 1 x x x x x Vx.w=vinsert(Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd=vror(Vu,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d Vd=valign(Vu,Vv,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d Vd=vlalign(Vu,Vv,Rt) +0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 1 u u u u u i i i d d d d d Vd=valign(Vu,Vv,#u3) +0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 1 u u u u u i i i d d d d d Vd=vlalign(Vu,Vv,#u3) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd=vdelta(Vu,Vv) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd=vrdelta(Vu,Vv) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 0 d d d d d Vd.h=vdeal(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 1 d d d d d Vd.b=vdeal(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 1 d d d d d Vd.h=vshuff(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 0 d d d d d Vd.b=vshuff(Vu.b) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.b=vdeale(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.b=vpacke(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vpacke(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.ub=vpack(Vu.h,Vv.h):sat +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.b=vpack(Vu.h,Vv.h):sat +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.uh=vpack(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.h=vpack(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.b=vpacko(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.h=vpacko(Vu.w,Vv.w) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 0 1 d d Qd4=vsetq(Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 1 1 d d Qd4=vsetq2(Rt) +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d Vd.b=vlut32(Vu.b,Vv.b,Rt):nomatch +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 1 d d d d d Vd.b=vlut32(Vu.b,Vv.b,Rt) +0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 0 u u u u u i i i d d d d d Vd.b=vlut32(Vu.b,Vv.b,#u3) +0 0 0 1 1 0 1 0 1 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x Vxx.w=vasrinto(Vu.w,Vv.w) +0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 0 1 x x x x x vshuff(Vy,Vx,Rt) +0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 1 0 x x x x x vdeal(Vy,Vx,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 1 1 d d d d d Vdd=vshuff(Vu,Vv,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d Vdd=vdeal(Vu,Vv,Rt) +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d Vdd.h=vlut16(Vu.b,Vv.h,Rt):nomatch +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 1 x x x x x Vx.b|=vlut32(Vu.b,Vv.b,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 0 d d d d d Vdd.h=vlut16(Vu.b,Vv.h,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 1 x x x x x Vxx.h|=vlut16(Vu.b,Vv.h,Rt) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 1 u u u u u i i i x x x x x Vx.b|=vlut32(Vu.b,Vv.b,#u3) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 1 u u u u u i i i x x x x x Vxx.h|=vlut16(Vu.b,Vv.h,#u3) +0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 0 u u u u u i i i d d d d d Vdd.h=vlut16(Vu.b,Vv.h,#u3) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 0 d d d d d Vdd.uh=vunpack(Vu.ub) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 1 d d d d d Vdd.uw=vunpack(Vu.uh) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 0 d d d d d Vdd.h=vunpack(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 1 d d d d d Vdd.w=vunpack(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 0 x x x x x Vxx.h|=vunpacko(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 1 x x x x x Vxx.w|=vunpacko(Vu.h) +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 1 0 w w w w w vscatter(Rt,Mu,Vvv.w).h=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 1 0 w w w w w vscatter(Rt,Mu,Vvv.w).h+=Vw32 +0 0 1 0 1 1 1 1 1 0 1 t t t t t P P u v v v v v 0 s s w w w w w if (Qs4) vscatter(Rt,Mu,Vvv.w).h=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 0 w w w w w vscatter(Rt,Mu,Vv.w).w=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 1 w w w w w vscatter(Rt,Mu,Vv.h).h=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 0 w w w w w vscatter(Rt,Mu,Vv.w).w+=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 1 w w w w w vscatter(Rt,Mu,Vv.h).h+=Vw32 +0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 0 s s w w w w w if (Qs4) vscatter(Rt,Mu,Vv.w).w=Vw32 +0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 1 s s w w w w w if (Qs4) vscatter(Rt,Mu,Vv.h).h=Vw32 + +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat + +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 0 0 1 0 d d d d d Vd.b=prefixsum(Qv4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 1 0 1 0 d d d d d Vd.h=prefixsum(Qv4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 1 0 0 1 0 d d d d d Vd.w=prefixsum(Qv4) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.qf16=vadd(Vu.qf16,Vv.qf16) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.qf16=vadd(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.qf16=vadd(Vu.qf16,Vv.hf) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vd.qf32=vadd(Vu.qf32,Vv.qf32) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.qf32=vadd(Vu.sf,Vv.sf) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.qf32=vadd(Vu.qf32,Vv.sf) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vasl(Vu.w,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.w+=vasr(Vu.w,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x Vx.h+=vasr(Vu.h,Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.h+=vasl(Vu.h,Rt) + +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat + +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vd.w=vasr(Vu.w,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vd.h=vasr(Vu.h,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vd.w=vasl(Vu.w,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.h=vasl(Vu.h,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd.uw=vlsr(Vu.uw,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vlsr(Vu.uh,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vlsr(Vu.ub,Rt) + +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt) +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat + +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vasr(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.w=vlsr(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.h=vlsr(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vasr(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.w=vasl(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.h=vasl(Vu.h,Vv.h) +0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.uh=vasr(Vuu.w,Vv.uh):sat +0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vasr(Vuu.w,Vv.uh):rnd:sat +0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.ub=vasr(Vuu.uh,Vv.ub):sat +0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vasr(Vuu.uh,Vv.ub):rnd:sat +0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 0 0 d d d d d Vd.sf=Vu.qf32 +0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 1 1 d d d d d Vd.hf=Vu.qf16 +0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 1 1 0 d d d d d Vd.hf=Vuu.qf32 +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.h=vround(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vround(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.b=vround(Vu.h,Vv.h):sat +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vround(Vu.h,Vv.h):sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vround(Vu.uh,Vv.uh):sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.uh=vround(Vu.uw,Vv.uw):sat +0 0 0 1 1 0 1 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.uw=vrotr(Vu.uw,Vv.uw) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.qf16=vsub(Vu.qf16,Vv.qf16) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d Vd.qf16=vsub(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.qf16=vsub(Vu.qf16,Vv.hf) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.qf32=vsub(Vu.qf32,Vv.qf32) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.qf32=vsub(Vu.sf,Vv.sf) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.qf32=vsub(Vu.qf32,Vv.sf) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 1 d d d d d Vd.uw=vcl0(Vu.uw) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 0 d d d d d Vd.h=vpopcount(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 1 d d d d d Vd.uh=vcl0(Vu.uh) +0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 0 d d d d d Vd.w=vnormamt(Vu.w) +0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 1 d d d d d Vd.h=vnormamt(Vu.h) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vd.h=vadd(vclb(Vu.h),Vv.h) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.w=vadd(vclb(Vu.w),Vv.w) +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 0 s s s s s if (Qv4) vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Qv4) vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 0 s s s s s if (Qv4) vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Qv4) vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 0 s s s vmem(Rt+#s4)=Os8.new +0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 1 - - s s s vmem(Rt+#s4):nt=Os8.new +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 0 0 0 s s s if (Pv) vmem(Rt+#s4)=Os8.new +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 1 0 1 s s s if (!Pv) vmem(Rt+#s4)=Os8.new +0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 0 1 0 s s s if (Pv) vmem(Rt+#s4):nt=Os8.new +0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 1 1 1 s s s if (!Pv) vmem(Rt+#s4):nt=Os8.new +0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 0 s s s vmem(Rx++#s3)=Os8.new +0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 1 - - s s s vmem(Rx++#s3):nt=Os8.new +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 0 0 0 s s s if (Pv) vmem(Rx++#s3)=Os8.new +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 1 0 1 s s s if (!Pv) vmem(Rx++#s3)=Os8.new +0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 0 1 0 s s s if (Pv) vmem(Rx++#s3):nt=Os8.new +0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 1 1 1 s s s if (!Pv) vmem(Rx++#s3):nt=Os8.new +0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 0 s s s vmem(Rx++Mu)=Os8.new +0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 1 - - s s s vmem(Rx++Mu):nt=Os8.new +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 0 0 0 s s s if (Pv) vmem(Rx++Mu)=Os8.new +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 1 0 1 s s s if (!Pv) vmem(Rx++Mu)=Os8.new +0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 0 1 0 s s s if (Pv) vmem(Rx++Mu):nt=Os8.new +0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 1 1 1 s s s if (!Pv) vmem(Rx++Mu):nt=Os8.ne +0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 0 s s s s s vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 0 s s s s s vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 0 s s s s s if (Pv) vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 0 s s s s s if (Pv) vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 0 s s s s s vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 0 s s s s s vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 0 s s s s s if (Pv) vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 0 s s s s s if (Pv) vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 0 s s s s s vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 0 s s s s s vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 0 s s s s s if (Pv) vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Pv) vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 0 s s s s s if (Pv) vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Pv) vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 1 1 1 s s s s s vmemu(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 0 s s s s s if (Pv) vmemu(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 1 s s s s s if (!Pv) vmemu(Rt+#s4)=Vs +0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 1 1 1 s s s s s vmemu(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 0 s s s s s if (Pv) vmemu(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 1 s s s s s if (!Pv) vmemu(Rx++#s3)=Vs +0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 1 1 1 s s s s s vmemu(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 0 s s s s s if (Pv) vmemu(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 1 s s s s s if (!Pv) vmemu(Rx++Mu)=Vs +0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 1 - - - vmem(Rt+#s4):scatter_release +0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 1 - - - vmem(Rx++#s3):scatter_release +0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 1 - - - vmem(Rx++Mu):scatter_release + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_left.sinc b/pypcode/processors/Hexagon/data/languages/hexagon_left.sinc new file mode 100644 index 00000000..e7dcf8d1 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon_left.sinc @@ -0,0 +1,648 @@ +# +# First/Left Packed 'EE' Instructions +# NOTE: It may be that Left-side patterns can ignore bits 0-12 +# + +# (v4,left,5,7) add -- "Rd16 = add ( Rs16 , #-1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 0 1 1 s s s s d d d d - - - - - - - - - - - - - - - - + +:add Rd4l,rs4l,MinusOne EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=3 & Rd4l & MinusOne & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l - 1; + build EndPackedLeft; +} + +# (v4,left,3) add -- "Rd16 = add ( Ru16 , #-1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:add Rd4l,rs4l,MinusOne EndPackedLeft is iclass=3 & op2427=3 & op13=1 & Rd4l & MinusOne & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l - 1; + build EndPackedLeft; +} + +# (v4,left,5,7) add -- "Rd16 = add ( Rs16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 0 0 1 s s s s d d d d - - - - - - - - - - - - - - - - + +:add Rd4l,rs4l,One EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=1 & Rd4l & One & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l + 1; + build EndPackedLeft; +} + +# (v4,left,3) add -- "Rd16 = add ( Ru16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:add Rd4l,rs4l,One EndPackedLeft is iclass=3 & op2427=1 & op13=1 & Rd4l & One & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l + 1; + build EndPackedLeft; +} + +# (v4,left,2) add -- "Rd16 = add ( Sp , #U6:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 I I I I I I d d d d - - 1 - - - - - - - - - - - - - + +:add Rd4l,SP,Uimm8_2025_shift2 EndPackedLeft is iclass=2 & op2627=3 & op13=1 & Rd4l & SP & Uimm8_2025_shift2 & $(END_PACKED_LEFT) { + Rd4l = SP + zext(Uimm8_2025_shift2); + build EndPackedLeft; +} + +# (v4,left,4,6) add -- "Rd16 = add ( Sp , #u6:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 0 1 1 i i i i i i d d d d - - - - - - - - - - - - - - - - + +:add Rd4l,SP,Uimm8_2025_shift2 EndPackedLeft is iclass3031=1 & iclass28=0 & op2627=3 & Rd4l & SP & Uimm8_2025_shift2 & $(END_PACKED_LEFT) { + Rd4l = SP + zext(Uimm8_2025_shift2); + build EndPackedLeft; +} + +# (v4,left,3) add -- "Rx16 = add ( Rs16 , Rx16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 s s s s x x x x - - 1 - - - - - - - - - - - - - + +:add Rd4l,rs4l,rd4l EndPackedLeft is iclass=3 & op2427=8 & op13=1 & Rd4l & rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l + rd4l; + build EndPackedLeft; +} + +# (v4,left,5,7) add -- "Rx16 = add ( Rs16 , Rx16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 0 0 s s s s x x x x - - - - - - - - - - - - - - - - + +:add Rd4l,rs4l,rd4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=8 & Rd4l & rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l + rd4l; + build EndPackedLeft; +} + +# (v4,left,2) add -- "Rx16 = add ( Rx16 , #S7x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 0 I I I I I I I x x x x - - 1 - - - - - - - - - - - - - + +:add Rd4l,rd4l,Simm32_2026x EndPackedLeft is iclass=2 & op27=0 & op13=1 & Rd4l & rd4l & Simm32_2026x & $(END_PACKED_LEFT) { + Rd4l = rd4l + Simm32_2026x; + build EndPackedLeft; +} + +# (v4,left,4,6) add -- "Rx16 = add ( Rx16 , #S7x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 0 0 I I I I I I I x x x x - - - - - - - - - - - - - - - - + +:add Rd4l,rd4l,Simm32_2026x EndPackedLeft is iclass3031=1 & iclass28=0 & op27=0 & Rd4l & rd4l & Simm32_2026x & $(END_PACKED_LEFT) { + Rd4l = rd4l + Simm32_2026x; + build EndPackedLeft; +} + +# (v4,left,5,7) and -- "Rd16 = and ( Rs16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 0 1 0 s s s s d d d d - - - - - - - - - - - - - - - - + +:and Rd4l,rs4l,One EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=2 & Rd4l & One & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 1; + build EndPackedLeft; +} + +# (v4,left,5,7) and -- "Rd16 = and ( Rs16 , #255 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 1 1 1 s s s s d d d d - - - - - - - - - - - - - - - - + +:and Rd4l,rs4l,FF EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=7 & Rd4l & FF & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 0xff; + build EndPackedLeft; +} + +# (v4,left,3) and -- "Rd16 = and ( Ru16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:and Rd4l,rs4l,One EndPackedLeft is iclass=3 & op2427=2 & op13=1 & Rd4l & One & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 1; + build EndPackedLeft; +} + +# (v4,left,3) and -- "Rd16 = and ( Ru16 , #255 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:and Rd4l,rs4l,FF EndPackedLeft is iclass=3 & op2427=7 & op13=1 & Rd4l & FF & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 0xff; + build EndPackedLeft; +} + +# (v4,left,5,7) assign -- "Rd16 = #-1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 0 + + d d d d - - - - - - - - - - - - - - - - + +:assign Rd4l,MinusOne EndPackedLeft is iclass3031=1 & iclass28=1 & op2127=0x50 & op20=0 & Rd4l & MinusOne & $(END_PACKED_LEFT) { + Rd4l = -1; + build EndPackedLeft; +} + +# (v4,left,2) assign -- "Rd16 = #U6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 I I I I I I d d d d - - 1 - - - - - - - - - - - - - + +:assign Rd4l,Uimm32_2025x EndPackedLeft is iclass=2 & op2627=2 & op13=1 & Rd4l & Uimm32_2025x & $(END_PACKED_LEFT) { + Rd4l = Uimm32_2025x; + build EndPackedLeft; +} + +# (v4,left,4,6) assign -- "Rd16 = #U6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 0 1 0 I I I I I I d d d d - - - - - - - - - - - - - - - - + +:assign Rd4l,Uimm32_2025x EndPackedLeft is iclass3031=1 & iclass28=0 & op2627=2 & Rd4l & Uimm32_2025x & $(END_PACKED_LEFT) { + Rd4l = Uimm32_2025x; + build EndPackedLeft; +} + +# (v4,left,5,7) assign -- "Rd16 = Rs16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 0 0 0 s s s s d d d d - - - - - - - - - - - - - - - - + +:assign Rd4l,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=0 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l; + build EndPackedLeft; +} + +# (v4,left,3) assign -- "Rd16 = Ru16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 u u u u d d d d - - 1 1 - - - - - - - - - - - - + +:assign Rd4l,rs4l EndPackedLeft is iclass=3 & op2427=0 & op13=1 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l; + build EndPackedLeft; +} + +# (v4,left,3) assign -- "Re16 = #-1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 0 + + e e e e - - 1 - - - - - - - - - - - - - + +:assign Rd4l,MinusOne EndPackedLeft is iclass=3 & op2127=0x50 & op20=0 & op13=1 & Rd4l & MinusOne & $(END_PACKED_LEFT) { + Rd4l = -1; + build EndPackedLeft; +} + +# (v4,left,5,7) assign -- "if ( ! p0 ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 1 1 1 d d d d - - - - - - - - - - - - - - - - +# +# (v4,left,5,7) assign -- "if ( ! p0 .new ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 1 0 1 d d d d - - - - - - - - - - - - - - - - +# +# (v4,left,5,7) assign -- "if ( p0 ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 1 1 0 d d d d - - - - - - - - - - - - - - - - +# +# (v4,left,5,7) assign -- "if ( p0 .new ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 1 0 0 d d d d - - - - - - - - - - - - - - - - + +:assign^P0Cond_N21_S20 rd4l,Zero EndPackedLeft is iclass3031=1 & iclass28=1 & op2227=0x29 & rd4l & P0Cond_N21_S20 & Zero & $(END_PACKED_LEFT) { + build P0Cond_N21_S20; + build EndPackedLeft; + <> + if (ConditionReg == 0) goto ; + rd4l = 0; + +} + +# (v4,left,3) assign -- "if ( ! p0 ) Re16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 1 1 1 e e e e - - 1 - - - - - - - - - - - - - +# +# (v4,left,3) assign -- "if ( ! p0 .new ) Re16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 1 0 1 e e e e - - 1 - - - - - - - - - - - - - +# +# (v4,left,3) assign -- "if ( p0 ) Re16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 1 1 0 e e e e - - 1 - - - - - - - - - - - - - +# +# (v4,left,3) assign -- "if ( p0 .new ) Re16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 1 0 0 e e e e - - 1 - - - - - - - - - - - - - + +:assign^P0Cond_N21_S20 rd4l,Zero EndPackedLeft is iclass=3 & op2227=0x29 & op13=1 & rd4l & P0Cond_N21_S20 & Zero & $(END_PACKED_LEFT) { + build P0Cond_N21_S20; + build EndPackedLeft; + <> + if (ConditionReg == 0) goto ; + rd4l = 0; + +} + +# (v4,left,3) cmp.eq -- "p0 = cmp.eq ( Rs16 , #U2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 s s s s - - I I - - 1 - - - - - - - - - - - - - + +:cmp.eq P0dest,rs4l,Uimm2_1617 EndPackedLeft is iclass=3 & op2427=9 & op13=1 & P0dest & rs4l & Uimm2_1617 & $(END_PACKED_LEFT) { + bool:1 = (rs4l == zext(Uimm2_1617)); + P0dest = P0dest & (bool * 0xff); + build EndPackedLeft; +} + +# (v4,left,5,7) cmp.eq -- "p0 = cmp.eq ( Rs16 , #U2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 0 1 s s s s - - I I - - - - - - - - - - - - - - - - + +:cmp.eq P0dest,rs4l,Uimm2_1617 EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=9 & P0dest & rs4l & Uimm2_1617 & $(END_PACKED_LEFT) { + bool:1 = (rs4l == zext(Uimm2_1617)); + P0dest = P0dest & (bool * 0xff); + build EndPackedLeft; +} + +# (v4,left,5,7) combine -- "Rdd8 = combine ( #n2 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 1 + 0 + i i n n d d d - - - - - - - - - - - - - - - - + +:combine Rdd3l,Uimm2_1920,Uimm2_2122 EndPackedLeft is iclass3031=1 & iclass28=1 & op2327=0x18 & Uimm2_1920 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = (zext(Uimm2_1920) << 32) + zext(Uimm2_2122); + build EndPackedLeft; +} + +# Simplification: "Rdd8 = #u2" +:assign Rdd3l,Uimm2_2122 EndPackedLeft is iclass3031=1 & iclass28=1 & op2327=0x18 & op1920=0 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(Uimm2_2122); + build EndPackedLeft; +} + +# (v4,left,3) combine -- "Rdd8 = combine ( #n2 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 + 0 + i i n n d d d - - 1 - - - - - - - - - - - - - + +:combine Rdd3l,Uimm2_1920,Uimm2_2122 EndPackedLeft is iclass=3 & op2327=0x18 & op13=1 & Uimm2_1920 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = (zext(Uimm2_1920) << 32) + zext(Uimm2_2122); + build EndPackedLeft; +} + +# Simplification: "Rdd8 = #u2" +:assign Rdd3l,Uimm2_2122 EndPackedLeft is iclass=3 & op2327=0x18 & op1920=0 & op13=1 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(Uimm2_2122); + build EndPackedLeft; +} + +# (v4,left,5,7) combine -- "Rdd8 = combine ( #0 , Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 1 + 1 s s s s 0 d d d - - - - - - - - - - - - - - - - + +:combine Rdd3l,Zero,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=13 & op19=0 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(rs4l); + build EndPackedLeft; +} + +# (v4,left,3) combine -- "Ree8 = combine ( #0 , Ru16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 + 1 u u u u 0 e e e - - 1 - - - - - - - - - - - - - + +:combine Rdd3l,Zero,rs4l EndPackedLeft is iclass=3 & op2427=13 & op19=0 & op13=1 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(rs4l); + build EndPackedLeft; +} + +# (v4,left,5,7) combine -- "Rdd8 = combine ( Rs16 , #0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 1 + 1 s s s s 1 d d d - - - - - - - - - - - - - - - - + +:combine Rdd3l,rs4l,Zero EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=13 & op19=1 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(rs4l) << 32; + build EndPackedLeft; +} + +# (v4,left,3) combine -- "Ree8 = combine ( Ru16 , #0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 + 1 u u u u 1 e e e - - 1 - - - - - - - - - - - - - + +:combine Rdd3l,rs4l,Zero EndPackedLeft is iclass=3 & op2427=13 & op19=1 & op13=1 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(rs4l) << 32; + build EndPackedLeft; +} + +# (v4,left,3) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 0 0 - - - 0 - - - - 0 - - - - - - - - - - - - - + +:deallocframe EndPackedLeft is iclass=3 & op2227=0x3c & op18=0 & op13=0 & $(END_PACKED_LEFT) { + build EndPackedLeft; + <> + deallocframe(FP); +} + +# (v4,left,9,13) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 1 1 0 0 - - - 0 - - - - 1 - - - - - - - - - - - - - + +:deallocframe EndPackedLeft is iclass31=1 & iclass2829=1 & op2227=0x3c & op18=0 & op13=1 & $(END_PACKED_LEFT) { + build EndPackedLeft; + <> + deallocframe(FP); +} + +# (v4,left,9,13) memb -- "Rd16 = memb ( Ru16 + #U3:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 0 I I I u u u u d d d d - - 1 - - - - - - - - - - - - - + +:memb Rd4l,MemRsRelU3Lb EndPackedLeft is iclass31=1 & iclass2829=1 & op27=0 & op13=1 & MemRsRelU3Lb & Rd4l & $(END_PACKED_LEFT) { + Rd4l = sext(MemRsRelU3Lb); + build EndPackedLeft; +} + +# (v4,left,3) memb -- "Rd16 = memb ( Rs16 + #u3:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 i i i s s s s d d d d - - 0 - - - - - - - - - - - - - + +:memb Rd4l,MemRsRelU3Lb EndPackedLeft is iclass=3 & op27=0 & op13=0 & MemRsRelU3Lb & Rd4l & $(END_PACKED_LEFT) { + Rd4l = sext(MemRsRelU3Lb); + build EndPackedLeft; +} + +# (v4,left,15) memb -- "memb ( Rs16 + #U4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 n s s s s I I I I - - 0 - - - - - - - - - - - - - + +:memb StMemRsRelC15Lb,Uimm1_24 EndPackedLeft is iclass=15 & op2527=1 & op13=0 & StMemRsRelC15Lb & Uimm1_24 & $(END_PACKED_LEFT) { + StMemRsRelC15Lb = Uimm1_24; + build EndPackedLeft; +} + +# (v4,left,11) memb -- "memb ( Rs16 + #U4:0 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 1 I I I I s s s s t t t t - - - - - - - - - - - - - - - - + +:memb MemRsRelU4Lb,rt4l EndPackedLeft is iclass=11 & MemRsRelU4Lb & rt4l & $(END_PACKED_LEFT) { + MemRsRelU4Lb = rt4l:1; + build EndPackedLeft; +} + +# (v4,left,9,13) memd -- "Rdd8 = memd ( Sp + #U5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 1 0 I I I I I d d d - - 1 - - - - - - - - - - - - - + +:memd Rdd3l,MemSpRelU5Ld EndPackedLeft is iclass31=1 & iclass2829=1 & op2427=14 & op13=1 & MemSpRelU5Ld & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = MemSpRelU5Ld; + build EndPackedLeft; +} + +# (v4,left,3) memd -- "Rdd8 = memd ( Sp + #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 i i i i i d d d - - 0 - - - - - - - - - - - - - + +:memd Rdd3l,MemSpRelU5Ld EndPackedLeft is iclass=3 & op2427=14 & op13=0 & MemSpRelU5Ld & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = MemSpRelU5Ld; + build EndPackedLeft; +} + +# (v4,left,14) memd -- "memd ( Sp + #S6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 I I I I I I t t t - - 0 - - - - - - - - - - - - - + +:memd MemSpRelS6Ld,rtt3l EndPackedLeft is iclass=14 & op2527=5 & op13=0 & MemSpRelS6Ld & rtt3l & $(END_PACKED_LEFT) { + MemSpRelS6Ld = rtt3l; + build EndPackedLeft; +} + +# (v4,left,8,12) memh -- "Rd16 = memh ( Rs16 + #U3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 0 0 I I I s s s s d d d d - - 1 - - - - - - - - - - - - - + +:memh Rd4l,MemRsRelU3Lh EndPackedLeft is iclass31=1 & iclass2829=0 & op27=0 & op13=1 & MemRsRelU3Lh & Rd4l & $(END_PACKED_LEFT) { + Rd4l = sext(MemRsRelU3Lh); + build EndPackedLeft; +} + +# (v4,left,2) memh -- "Rd16 = memh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 0 i i i s s s s d d d d - - 0 - - - - - - - - - - - - - + +:memh Rd4l,MemRsRelU3Lh EndPackedLeft is iclass=2 & op27=0 & op13=0 & MemRsRelU3Lh & Rd4l & $(END_PACKED_LEFT) { + Rd4l = sext(MemRsRelU3Lh); + build EndPackedLeft; +} + +# (v4,left,14) memh -- "memh ( Rs16 + #U3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 I I I s s s s t t t t - - 0 - - - - - - - - - - - - - + +:memh MemRsRelU3Lh,rt4l EndPackedLeft is iclass=14 & op27=0 & op13=0 & MemRsRelU3Lh & rt4l & $(END_PACKED_LEFT) { + MemRsRelU3Lh = rt4l:2; + build EndPackedLeft; +} + +# (v4,left,1) memub -- "Rd16 = memub ( Rs16 + #u4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 i i i i s s s s d d d d - - - - - - - - - - - - - - - - + +:memub Rd4l,MemRsRelU4Lb EndPackedLeft is iclass=1 & MemRsRelU4Lb & Rd4l & $(END_PACKED_LEFT) { + Rd4l = zext(MemRsRelU4Lb); + build EndPackedLeft; +} + +# (v4,left,9,13) memub -- "Rd16 = memub ( Ru16 + #U4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 I I I I u u u u d d d d - - 0 - - - - - - - - - - - - - + +:memub Rd4l,MemRsRelU4Lb EndPackedLeft is iclass31=1 & iclass2829=1 & op13=0 & MemRsRelU4Lb & Rd4l & $(END_PACKED_LEFT) { + Rd4l = zext(MemRsRelU4Lb); + build EndPackedLeft; +} + +# (v4,left,2) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 i i i s s s s d d d d - - 0 - - - - - - - - - - - - - + +:memuh Rd4l,MemRsRelU3Lh EndPackedLeft is iclass=2 & op27=1 & op13=0 & MemRsRelU3Lh & Rd4l & $(END_PACKED_LEFT) { + Rd4l = zext(MemRsRelU3Lh); + build EndPackedLeft; +} + +# (v4,left,8,12) memuh -- "Rd16 = memuh ( Ru16 + #U3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 0 1 I I I u u u u d d d d - - 1 - - - - - - - - - - - - - + +:memuh Rd4l,MemRsRelU3Lh EndPackedLeft is iclass31=1 & iclass2829=0 & op27=1 & op13=1 & MemRsRelU3Lh & Rd4l & $(END_PACKED_LEFT) { + Rd4l = zext(MemRsRelU3Lh); + build EndPackedLeft; +} + +# (v4,left,0) memw -- "Rd16 = memw ( Rs16 + #u4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 0 i i i i s s s s d d d d - - - - - - - - - - - - - - - - + +:memw Rd4l,MemRsRelU4Lw EndPackedLeft is iclass=0 & MemRsRelU4Lw & Rd4l & $(END_PACKED_LEFT) { + Rd4l = MemRsRelU4Lw; + build EndPackedLeft; +} + +# (v4,left,8,12) memw -- "Rd16 = memw ( Ru16 + #U4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 0 I I I I u u u u d d d d - - 0 - - - - - - - - - - - - - + +:memw Rd4l,MemRsRelU4Lw EndPackedLeft is iclass31=1 & iclass2829=0 & op13=0 & MemRsRelU4Lw & Rd4l & $(END_PACKED_LEFT) { + Rd4l = MemRsRelU4Lw; + build EndPackedLeft; +} + +# (v4,left,9,13) memw -- "Rd16 = memw ( Sp + #U5:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 0 I I I I I d d d d - - 1 - - - - - - - - - - - - - + +:memw Rd4l,MemSpRelU5Lw EndPackedLeft is iclass31=1 & iclass2829=1 & op2527=6 & op13=1 & MemSpRelU5Lw & Rd4l & $(END_PACKED_LEFT) { + Rd4l = MemSpRelU5Lw; + build EndPackedLeft; +} + +# (v4,left,3) memw -- "Rd16 = memw ( Sp + #u5:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 0 i i i i i d d d d - - 0 - - - - - - - - - - - - - + +:memw Rd4l,MemSpRelU5Lw EndPackedLeft is iclass=3 & op2527=6 & op13=0 & MemSpRelU5Lw & Rd4l & $(END_PACKED_LEFT) { + Rd4l = MemSpRelU5Lw; + build EndPackedLeft; +} + +# (v4,left,15) memw -- "memw ( Rs16 + #U4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 n s s s s I I I I - - 0 - - - - - - - - - - - - - + +:memw StMemRsRelC15Lw,Uimm1_24 EndPackedLeft is iclass=15 & op2527=0 & op13=0 & StMemRsRelC15Lw & Uimm1_24 & $(END_PACKED_LEFT) { + StMemRsRelC15Lw = zext(Uimm1_24); + build EndPackedLeft; +} + +# (v4,left,10) memw -- "memw ( Rs16 + #U4:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 I I I I s s s s t t t t - - - - - - - - - - - - - - - - + +:memw MemRsRelU4Lw,rt4l EndPackedLeft is iclass=10 & MemRsRelU4Lw & rt4l & $(END_PACKED_LEFT) { + MemRsRelU4Lw = rt4l; + build EndPackedLeft; +} + +# (v4,left,14) memw -- "memw ( Sp + #U5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 I I I I I t t t t - - 0 - - - - - - - - - - - - - + +:memw MemSpRelU5Lw,rt4l EndPackedLeft is iclass=14 & op2527=4 & op13=0 & MemSpRelU5Lw & rt4l & $(END_PACKED_LEFT) { + MemSpRelU5Lw = rt4l; + build EndPackedLeft; +} + +# (v4,left,5,7) sxtb -- "Rd16 = sxtb ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 1 0 1 s s s s d d d d - - - - - - - - - - - - - - - - + +:sxtb Rd4l,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=5 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = (rs4l << 24) s>> 24; + build EndPackedLeft; +} + +# (v4,left,3) sxtb -- "Rd16 = sxtb ( Ru16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:sxtb Rd4l,rs4l EndPackedLeft is iclass=3 & op2427=5 & op13=1 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = (rs4l << 24) s>> 24; + build EndPackedLeft; +} + +# (v4,left,5,7) sxth -- "Rd16 = sxth ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 1 0 0 s s s s d d d d - - - - - - - - - - - - - - - - + +:sxth Rd4l,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=4 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = (rs4l << 16) s>> 16; + build EndPackedLeft; +} + +# (v4,left,3) sxth -- "Rd16 = sxth ( Ru16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:sxth Rd4l,rs4l EndPackedLeft is iclass=3 & op2427=4 & op13=1 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = (rs4l << 16) s>> 16; + build EndPackedLeft; +} + +# (v4,left,5,7) zxth -- "Rd16 = zxth ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 1 1 0 s s s s d d d d - - - - - - - - - - - - - - - - + +:zxth Rd4l,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=6 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 0xffff; + build EndPackedLeft; +} + +# (v4,left,3) zxth -- "Rd16 = zxth ( Ru16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:zxth Rd4l,rs4l EndPackedLeft is iclass=3 & op2427=6 & op13=1 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 0xffff; + build EndPackedLeft; +} \ No newline at end of file diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_right.sinc b/pypcode/processors/Hexagon/data/languages/hexagon_right.sinc new file mode 100644 index 00000000..ed7f7c52 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon_right.sinc @@ -0,0 +1,776 @@ +# +# Second/Right Packed 'EE' Instructions +# + + +# (v4,right,2,3) add -- "Rd16 = add ( Rs16 , #-1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 1 s s s s d d d d + +:add Rd4r,rs4r,MinusOne EndPackedRight is iclass2931=1 & op0813=0x33 & Rd4r & MinusOne & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r - 1; + build EndPackedRight; +} + +# (v4,right,2,3) add -- "Rd16 = add ( Rs16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 1 s s s s d d d d + +:add Rd4r,rs4r,One EndPackedRight is iclass2931=1 & op0813=0x31 & Rd4r & One & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r + 1; + build EndPackedRight; +} + +# (v4,right,2) add -- "Rd16 = add ( Sp , #u6:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 1 0 1 1 i i i i i i d d d d + +:add Rd4r,SP,Uimm8_0409_shift2 EndPackedRight is iclass=2 & op1013=11 & Rd4r & SP & Uimm8_0409_shift2 & $(END_PACKED_RIGHT) { + Rd4r = SP + zext(Uimm8_0409_shift2); + build EndPackedRight; +} + +# (v4,right,2,3) add -- "Rx16 = add ( Rs16 , Rx16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 0 0 s s s s x x x x + +:add Rd4r,rs4r,rd4r EndPackedRight is iclass2931=1 & op0813=0x38 & Rd4r & rd4r & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r + rd4r; + build EndPackedRight; +} + +# (v4,right,2) add -- "Rx16 = add ( Rx16 , #s7 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 1 0 0 i i i i i i i x x x x + +:add Rd4r,rd4r,Simm8_0410 EndPackedRight is iclass=2 & op1113=4 & Rd4r & rd4r & Simm8_0410 & $(END_PACKED_RIGHT) { + Rd4r = rd4r + sext(Simm8_0410); + build EndPackedRight; +} + +# (v4,right,6,7) allocframe -- "allocframe ( #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i - - - - +# +# (v4,right,10,11) allocframe -- "allocframe ( #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i - - - - + +:allocframe Uimm8_0408_shift3 EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x1e & Uimm8_0408_shift3 & $(END_PACKED_RIGHT) { + allocframe(SP, Uimm8_0408_shift3); + build EndPackedRight; +} + +# (v4,right,12,13) allocframe -- "allocframe ( #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 1 1 1 0 i i i i i - - - - + +:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=6 & op0912=14 & Uimm8_0408_shift3 & $(END_PACKED_RIGHT) { + allocframe(SP, Uimm8_0408_shift3); + build EndPackedRight; +} + +# (v4,right,14,15) allocframe -- "allocframe ( #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 1 1 1 0 i i i i i - - - - + +:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=7 & op0913=0x0e & Uimm8_0408_shift3 & $(END_PACKED_RIGHT) { + allocframe(SP, Uimm8_0408_shift3); + build EndPackedRight; +} + +# (v4,right,2,3) and -- "Rd16 = and ( Rs16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 0 s s s s d d d d + +:and Rd4r,rs4r,One EndPackedRight is iclass2931=1 & op0813=0x32 & Rd4r & One & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r & 1; + build EndPackedRight; +} + +# (v4,right,2,3) and -- "Rd16 = and ( Rs16 , #255 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 1 1 s s s s d d d d + +:and Rd4r,rs4r,FF EndPackedRight is iclass2931=1 & op0813=0x37 & Rd4r & FF & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r & 0xff; + build EndPackedRight; +} + +# (v4,right,2,3) assign -- "Rd16 = #-1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 0 + + d d d d + +:assign Rd4r,MinusOne EndPackedRight is iclass2931=1 & op13=1 & op0412=0x1a0 & Rd4r & MinusOne & $(END_PACKED_RIGHT) { + Rd4r = -1; + build EndPackedRight; +} + +# (v4,right,2) assign -- "Rd16 = #u6" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 1 0 1 0 i i i i i i d d d d + +:assign Rd4r,Uimm8_0409 EndPackedRight is iclass=2 & op1013=10 & Rd4r & Uimm8_0409 & $(END_PACKED_RIGHT) { + Rd4r = zext(Uimm8_0409); + build EndPackedRight; +} + +# (v4,right,2,3) assign -- "Rd16 = Rs16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 0 s s s s d d d d + +:assign Rd4r,rs4r EndPackedRight is iclass2931=1 & op13=1 & op0812=0x10 & Rd4r & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r; + build EndPackedRight; +} + +# (v4,right,2,3) assign -- "if ( ! p0 ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 1 1 d d d d +# +# (v4,right,2,3) assign -- "if ( ! p0 .new ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 0 1 d d d d +# +# (v4,right,2,3) assign -- "if ( p0 ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 1 0 d d d d +# +# (v4,right,2,3) assign -- "if ( p0 .new ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 0 0 d d d d + +:assign^P0Cond_N05_S04 rd4r,Zero EndPackedRight is iclass2931=1 & op13=1 & op0612=0x69 & rd4r & Zero & P0Cond_N05_S04 & $(END_PACKED_RIGHT) { + build P0Cond_N05_S04; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + rd4r = 0; + +} + +# (v4,right,2,3) cmp.eq -- "p0 = cmp.eq ( Rs16 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 0 1 s s s s - - i i + +:cmp.eq P0,rs4r,Uimm8_0001 EndPackedRight is iclass2931=1 & op13=1 & op0812=0x19 & P0 & rs4r & Uimm8_0001 & $(END_PACKED_RIGHT) { + bool:1 = (rs4r == zext(Uimm8_0001)); + P0.new = P0.new & (bool * 0xff); + build EndPackedRight; + <> + P0 = P0.new; +} + +# (v4,right,2,3) combine -- "Rdd8 = combine ( #n2 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 + 0 - i i n n d d d + +:combine Rdd3r,Uimm2_0304,Uimm2_0506 EndPackedRight is iclass2931=1 & op0813=0x3c & Uimm2_0304 & Uimm2_0506 & Rdd3r & Zero & $(END_PACKED_RIGHT) { + Rdd3r = (zext(Uimm2_0304) << 32) + zext(Uimm2_0506); + build EndPackedRight; +} + +# (v4,right,2,3) combine -- "Rdd8 = combine ( #0 , Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 + 1 s s s s 0 d d d + +:combine Rdd3r,Zero,rs4r EndPackedRight is iclass2931=1 & op0813=0x3d & op3=0 & rs4r & Rdd3r & Zero & $(END_PACKED_RIGHT) { + Rdd3r = zext(rs4r); + build EndPackedRight; +} + +# (v4,right,2,3) combine -- "Rdd8 = combine ( Rs16 , #0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 + 1 s s s s 1 d d d + +:combine Rdd3r,rs4r,Zero EndPackedRight is iclass2931=1 & op0813=0x3d & op3=1 & rs4r & Rdd3r & Zero & $(END_PACKED_RIGHT) { + Rdd3r = zext(rs4r) << 32; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 0 - - + +:dealloc_return EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7d & op2=0 & $(END_PACKED_RIGHT) { + build EndPackedRight; + <> + deallocframe(FP); + return [LR]; +} + +# (v4,right,2,3) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 0 - - + +:dealloc_return EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7d & op2=0 & $(END_PACKED_RIGHT) { + build EndPackedRight; + <> + deallocframe(FP); + return [LR]; +} + +# (v4,right,0,1,4,5) dealloc_return -- "if ( ! p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 0 1 +# +# (v4,right,0,1,4,5) dealloc_return:nt -- "if ( ! p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 1 1 +# +# (v4,right,0,1,4,5) dealloc_return -- "if ( p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 0 0 +# +# (v4,right,0,1,4,5) dealloc_return:nt -- "if ( p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 1 0 + +:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7d & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & $(END_PACKED_RIGHT) { + build FlowP0Cond_N01_S00; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + deallocframe(FP); + return [LR]; + +} + +# (v4,right,2,3) dealloc_return -- "if ( ! p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 0 1 +# +# (v4,right,2,3) dealloc_return:nt -- "if ( ! p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 1 1 +# +# (v4,right,2,3) dealloc_return -- "if ( p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 0 0 +# +# (v4,right,2,3) dealloc_return:nt -- "if ( p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 1 0 + +:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7d & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & $(END_PACKED_RIGHT) { + build FlowP0Cond_N01_S00; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + deallocframe(FP); + return [LR]; + +} + +# (v4,right,0,1,4,5) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 0 - - - 0 - - + +:deallocframe EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) { + build EndPackedRight; + <> + deallocframe(FP); +} + +# (v4,right,2,3) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 0 - - - 0 - - + +:deallocframe EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) { + build EndPackedRight; + <> + deallocframe(FP); +} + +# (v4,right,0,1,4,5) jumpr -- "jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 0 - - + +:jumpr LR EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7f & op2=0 & LR & $(END_PACKED_RIGHT) { + dest:4 = LR; + build EndPackedRight; + <> + return [dest]; +} + +# (v4,right,2,3) jumpr -- "jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 0 - - + +:jumpr LR EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7f & op2=0 & LR & $(END_PACKED_RIGHT) { + dest:4 = LR; + build EndPackedRight; + <> + return [dest]; +} + +# (v4,right,0,1,4,5) jumpr -- "if ( ! p0 ) jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 0 1 +# +# (v4,right,0,1,4,5) jumpr:nt -- "if ( ! p0 .new ) jumpr:nt Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 1 1 +# +# (v4,right,0,1,4,5) jumpr -- "if ( p0 ) jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 0 0 +# +# (v4,right,0,1,4,5) jumpr:nt -- "if ( p0 .new ) jumpr:nt Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 1 0 + +# Conditional Return +:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7f & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) { + dest:4 = LR; + build FlowP0Cond_N01_S00; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + return [dest]; + +} + +# (v4,right,2,3) jumpr -- "if ( ! p0 ) jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 0 1 +# +# (v4,right,2,3) jumpr:nt -- "if ( ! p0 .new ) jumpr:nt Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 1 1 +# +# (v4,right,2,3) jumpr -- "if ( p0 ) jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 0 0 +# +# (v4,right,2,3) jumpr:nt -- "if ( p0 .new ) jumpr:nt Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 1 0 + +:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7f & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) { + dest:4 = LR; + build FlowP0Cond_N01_S00; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + return [dest]; + +} + +# (v4,right,0,1,4,5) memb -- "Rd16 = memb ( Rs16 + #u3:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 0 i i i s s s s d d d d + +:memb Rd4r,MemRsRelU3Rb EndPackedRight is iclass31=0 & iclass29=0 & op1113=6 & MemRsRelU3Rb & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = sext(MemRsRelU3Rb); + build EndPackedRight; +} + +# (v4,right,2,3) memb -- "Rd16 = memb ( Rs16 + #u3:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 0 i i i s s s s d d d d + +:memb Rd4r,MemRsRelU3Rb EndPackedRight is iclass2931=1 & op1113=2 & MemRsRelU3Rb & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = sext(MemRsRelU3Rb); + build EndPackedRight; +} + +# (v4,right,6,7) memb -- "memb ( Rs16 + #u4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 1 0 0 1 n s s s s i i i i +# +# (v4,right,10,11) memb -- "memb ( Rs16 + #u4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 n s s s s i i i i + +:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x19 & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) { + MemRsRelU4Rnb = Uimm1_08; + build EndPackedRight; +} + +# (v4,right,12,13) memb -- "memb ( Rs16 + #u4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 1 0 0 1 n s s s s i i i i + +:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is iclass2931=6 & op0912=9 & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) { + MemRsRelU4Rnb = Uimm1_08; + build EndPackedRight; +} + +# (v4,right,14,15) memb -- "memb ( Rs16 + #u4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 1 0 0 1 n s s s s i i i i + +:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is iclass2931=7 & op0913=9 & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) { + MemRsRelU4Rnb = Uimm1_08; + build EndPackedRight; +} + +# (v4,right,6,7) memb -- "memb ( Rs16 + #u4:0 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 0 1 i i i i s s s s t t t t +# +# (v4,right,10,11) memb -- "memb ( Rs16 + #u4:0 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 0 1 i i i i s s s s t t t t + +:memb MemRsRelU4Rb,rt4r EndPackedRight is (iclass2931=3 | iclass2931=5) & op1213=1 & MemRsRelU4Rb & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU4Rb = rt4r:1; + build EndPackedRight; +} + +# (v4,right,8,9) memb -- "memb ( Rs16 + #u4:0 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 - - - - - - - - - - - - - - - - 1 i i i i s s s s t t t t + +:memb MemRsRelU4Rb,rt4r EndPackedRight is iclass2931=4 & op12=1 & MemRsRelU4Rb & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU4Rb = rt4r:1; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memd -- "Rdd8 = memd ( Sp + #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 0 i i i i i d d d +:memd Rdd3r,MemSpRelU5Rd EndPackedRight is iclass31=0 & iclass29=0 & op0813=0x3e & MemSpRelU5Rd & Rdd3r & $(END_PACKED_RIGHT) { + Rdd3r = MemSpRelU5Rd; + build EndPackedRight; +} + +# (v4,right,2,3) memd -- "Rdd8 = memd ( Sp + #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 0 i i i i i d d d + +:memd Rdd3r,MemSpRelU5Rd EndPackedRight is iclass2931=1 & op0813=0x1e & MemSpRelU5Rd & Rdd3r & $(END_PACKED_RIGHT) { + Rdd3r = MemSpRelU5Rd; + build EndPackedRight; +} + +# (v4,right,6,7) memd -- "memd ( Sp + #s6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 0 1 0 1 i i i i i i t t t +# +# (v4,right,10,11) memd -- "memd ( Sp + #s6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 0 1 0 1 i i i i i i t t t + +:memd MemSpRelS6Rd,rtt3r EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x15 & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) { + MemSpRelS6Rd = rtt3r; + build EndPackedRight; +} + +# (v4,right,12,13) memd -- "memd ( Sp + #s6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 0 1 0 1 i i i i i i t t t + +:memd MemSpRelS6Rd,rtt3r EndPackedRight is iclass2931=6 & op0912=5 & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) { + MemSpRelS6Rd = rtt3r; + build EndPackedRight; +} + +# (v4,right,14,15) memd -- "memd ( Sp + #s6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 0 1 0 1 i i i i i i t t t + +:memd MemSpRelS6Rd,rtt3r EndPackedRight is iclass2931=7 & op0913=0x05 & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) { + MemSpRelS6Rd = rtt3r; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memh -- "Rd16 = memh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s d d d d + +:memh Rd4r,MemRsRelU3Rh EndPackedRight is iclass31=0 & iclass29=0 & op1113=4 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = sext(MemRsRelU3Rh); + build EndPackedRight; +} + +# (v4,right,2) memh -- "Rd16 = memh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 0 0 0 i i i s s s s d d d d + +:memh Rd4r,MemRsRelU3Rh EndPackedRight is iclass=2 & op1113=0 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = sext(MemRsRelU3Rh); + build EndPackedRight; +} + +# (v4,right,6,7) memh -- "memh ( Rs16 + #u3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s t t t t +# +# (v4,right,10,11) memh -- "memh ( Rs16 + #u3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s t t t t + +:memh MemRsRelU3Rh,rt4r EndPackedRight is (iclass2931=3 | iclass2931=5) & op1113=4 & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU3Rh = rt4r:2; + build EndPackedRight; +} + +# (v4,right,12,13) memh -- "memh ( Rs16 + #u3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 0 0 i i i s s s s t t t t + +:memh MemRsRelU3Rh,rt4r EndPackedRight is iclass2931=6 & op1112=0 & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU3Rh = rt4r:2; + build EndPackedRight; +} + +# (v4,right,14,15) memh -- "memh ( Rs16 + #u3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 0 0 i i i s s s s t t t t + +:memh MemRsRelU3Rh,rt4r EndPackedRight is iclass2931=7 & op1113=0 & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU3Rh = rt4r:2; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memub -- "Rd16 = memub ( Rs16 + #u4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 0 1 i i i i s s s s d d d d + +:memub Rd4r,MemRsRelU4Rb EndPackedRight is iclass31=0 & iclass29=0 & op1213=1 & MemRsRelU4Rb & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = zext(MemRsRelU4Rb); + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 0 1 i i i s s s s d d d d + +:memuh Rd4r,MemRsRelU3Rh EndPackedRight is iclass31=0 & iclass29=0 & op1113=5 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = zext(MemRsRelU3Rh); + build EndPackedRight; +} + +# (v4,right,2) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 0 0 1 i i i s s s s d d d d + +:memuh Rd4r,MemRsRelU3Rh EndPackedRight is iclass=2 & op1113=1 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = zext(MemRsRelU3Rh); + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memw -- "Rd16 = memw ( Rs16 + #u4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 0 0 i i i i s s s s d d d d + +:memw Rd4r,MemRsRelU4Rw EndPackedRight is iclass31=0 & iclass29=0 & op1213=0 & MemRsRelU4Rw & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = MemRsRelU4Rw; + build EndPackedRight; +} + +# (v4,right,6,7) memw -- "memw ( Rs16 + #u4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 1 0 0 0 n s s s s i i i i +# +# (v4,right,10,11) memw -- "memw ( Rs16 + #u4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 n s s s s i i i i + +:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is (iclass2931=3 | iclass2931=5) & op13=1 & op0912=8 & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) { + StMemRsRelC15Rw = zext(Uimm1_08); + build EndPackedRight; +} + +# (v4,right,12,13) memw -- "memw ( Rs16 + #u4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 1 0 0 0 n s s s s i i i i + +:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is iclass2931=6 & op0912=8 & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) { + StMemRsRelC15Rw = zext(Uimm1_08); + build EndPackedRight; +} + +# (v4,right,14,15) memw -- "memw ( Rs16 + #u4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 1 0 0 0 n s s s s i i i i + +:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is iclass2931=7 & op13=0 & op0912=8 & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) { + StMemRsRelC15Rw = zext(Uimm1_08); + build EndPackedRight; +} + +# (v4,right,8,9) memw -- "memw ( Rs16 + #u4:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 - - - - - - - - - - - - - - - - 0 i i i i s s s s t t t t + +:memw MemRsRelU4Rw,rt4r EndPackedRight is iclass2931=4 & op12=0 & MemRsRelU4Rw & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU4Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,6,7) memw -- "memw ( Rs16 + #u4:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 0 0 i i i i s s s s t t t t +# +# (v4,right,10,11) memw -- "memw ( Rs16 + #u4:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 0 0 i i i i s s s s t t t t + +:memw MemRsRelU4Rw,rt4r EndPackedRight is (iclass2931=5 | iclass2931=3) & op1213=0 & MemRsRelU4Rw & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU4Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memw -- "Rd16 = memw ( Sp + #u5:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i d d d d + +:memw Rd4r,MemSpRelU5Rw EndPackedRight is iclass31=0 & iclass29=0 & op0913=0x1e & MemSpRelU5Rw & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = MemSpRelU5Rw; + build EndPackedRight; +} + +# (v4,right,2,3) memw -- "Rd16 = memw ( Sp + #u5:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 0 i i i i i d d d d + +:memw Rd4r,MemSpRelU5Rw EndPackedRight is iclass2931=1 & op0913=0x0e & MemSpRelU5Rw & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = MemSpRelU5Rw; + build EndPackedRight; +} + +# (v4,right,6,7) memw -- "memw ( Sp + #u5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 0 1 0 0 i i i i i t t t t +# +# (v4,right,10,11) memw -- "memw ( Sp + #u5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 0 1 0 0 i i i i i t t t t + +:memw MemSpRelU5Rw,rt4r EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x14 & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) { + MemSpRelU5Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,12,13) memw -- "memw ( Sp + #u5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 0 1 0 0 i i i i i t t t t + +:memw MemSpRelU5Rw,rt4r EndPackedRight is iclass2931=6 & op0912=4 & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) { + MemSpRelU5Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,14,15) memw -- "memw ( Sp + #u5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 0 1 0 0 i i i i i t t t t + +:memw MemSpRelU5Rw,rt4r EndPackedRight is iclass2931=7 & op0913=0x04 & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) { + MemSpRelU5Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,2,3) sxtb -- "Rd16 = sxtb ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 0 1 s s s s d d d d + +:sxtb Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x35 & rs4r & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = (rs4r << 24) s>> 24; + build EndPackedRight; +} + +# (v4,right,2,3) sxth -- "Rd16 = sxth ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 0 0 s s s s d d d d + +:sxth Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x34 & rs4r & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = (rs4r << 16) s>> 16; + build EndPackedRight; +} + +# (v4,right,2,3) zxth -- "Rd16 = zxth ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 1 0 s s s s d d d d + +:zxth Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x36 & rs4r & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r & 0xffff; + build EndPackedRight; +} \ No newline at end of file diff --git a/pypcode/processors/Hexagon/data/patterns/Hexagon_patterns.xml b/pypcode/processors/Hexagon/data/patterns/Hexagon_patterns.xml new file mode 100755 index 00000000..ac73cb66 --- /dev/null +++ b/pypcode/processors/Hexagon/data/patterns/Hexagon_patterns.xml @@ -0,0 +1,72 @@ + + + + + + + 01000000 00111111 ........ 0.0..... + 01000000 00011111 ........ 001..... + + 11000000 00111111 ........ 0.0..... + 11000000 00011111 ........ 001..... + + 00011110 11000000 00011110 10010110 + 00011110 01000000 00011110 10010110 ........ 11...... ........ ........ + 00011110 01000000 00011110 10010110 ........ 00...... ........ ........ + 00011110 01000000 00011110 10010110 ........ 01...... ........ ........ ........ 11...... ........ ........ + 00011110 01000000 00011110 10010110 ........ 01...... ........ ........ ........ 00...... ........ ........ + 00011110 01000000 00011110 10010110 ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 11...... ........ ........ + + .......0 11...... ........ 0101100. + .......0 01...... ........ 0101100. ........ 11...... ........ ........ + .......0 01...... ........ 0101100. ........ 00...... ........ ........ + .......0 01...... ........ 0101100. ........ 01...... ........ ........ ........ 11...... ........ ........ + .......0 01...... ........ 0101100. ........ 01...... ........ ........ ........ 00...... ........ ........ + .......0 01...... ........ 0101100. ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 11...... ........ ........ + + 00000000 01000000 100..... 01010010 + 00000000 01000000 100..... 01010010 ........ 11...... ........ ........ + 00000000 01000000 100..... 01010010 ........ 00...... ........ ........ + 00000000 01000000 100..... 01010010 ........ 01...... ........ ........ ........ 11...... ........ ........ + 00000000 01000000 100..... 01010010 ........ 01...... ........ ........ ........ 00...... ........ ........ + 00000000 01000000 100..... 01010010 ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 11...... ........ ........ + + + + + + + ........ .1000... 10011101 10100000 + ....0000 0011110. ........ 011..... + ....0000 0011110. ........ 101..... + ....0000 00.1110. ........ 110..... + ....0000 0001110. ........ 111..... + + + ........ 01...... ........ ........ ........ .1000... 10011101 10100000 + ........ 01...... ........ ........ ....0000 0011110. ........ 011..... + ........ 01...... ........ ........ ....0000 0011110. ........ 101..... + ........ 01...... ........ ........ ....0000 00.1110. ........ 110..... + ........ 01...... ........ ........ ....0000 0001110. ........ 111..... + + + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ .1000... 10011101 10100000 + ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0011110. ........ 011..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0011110. ........ 101..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 00.1110. ........ 110..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0001110. ........ 111..... + + + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 11000... 10011101 10100000 + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0011110. ........ 011..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0011110. ........ 101..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 00.1110. ........ 110..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0001110. ........ 111..... + + + + + + + + diff --git a/pypcode/processors/Hexagon/data/patterns/patternconstraints.xml b/pypcode/processors/Hexagon/data/patterns/patternconstraints.xml new file mode 100755 index 00000000..23217b7b --- /dev/null +++ b/pypcode/processors/Hexagon/data/patterns/patternconstraints.xml @@ -0,0 +1,5 @@ + + + Hexagon_patterns.xml + + \ No newline at end of file diff --git a/pypcode/processors/MIPS/data/languages/mips.sinc b/pypcode/processors/MIPS/data/languages/mips.sinc index c1e52917..18c86524 100644 --- a/pypcode/processors/MIPS/data/languages/mips.sinc +++ b/pypcode/processors/MIPS/data/languages/mips.sinc @@ -502,6 +502,10 @@ define token instr(32) prime = (26,31) bit25 = (25,25) zero2425 = (24,25) + svrs_xreg = (23,25) + svrs_xregb0 = (23,23) + svrs_xregb1 = (24,24) + svrs_xregb2 = (25,25) zero2325 = (23,25) zero1 = (22,25) rs32 = (21,25) @@ -530,6 +534,7 @@ define token instr(32) off21 = (0,20) signed # 21 bit signed offset in conditional branch/link off16 = (0,15) signed # 16 bit signed offset in conditional branch/link bit21 = (21,21) + svrs_frame_hi = (19,22) bitz19 = (19,20) pcrel = (19,20) pcrel2 = (18,20) @@ -557,8 +562,16 @@ define token instr(32) lohiacx = (16,19) nd = (17,17) tf = (16,16) + svrs_aregb3 = (18,18) + svrs_aregb2 = (17,17) + svrs_aregb1 = (16,16) + svrs_aregb0 = (15,15) + svrs_areg = (15,18) + zero1320 = (13,20) zero1315 = (13,15) + save = (13,13) + svrs_ra = (12,12) szero = (11,25) mask = (11,20) baser6 = (11,15) @@ -600,7 +613,9 @@ define token instr(32) ac = (11,12) bp = (11,12) bit10 = (10,10) + svrs_s0 = (11,11) spec2 = (9,10) + svrs_s1 = (10,10) spec3 = (8,10) simmed9 = (7,15) zero2 = (7,10) @@ -613,7 +628,7 @@ define token instr(32) fct2 = (6,10) zero5 = (6,10) wsbh = (6,10) - + svrs_frame_low = (6,9) bp3 = (6,8) sel_0608 = (6,8) sa2 = (6,7) @@ -904,9 +919,12 @@ DXuPos: pos is lsb [ pos = lsb + 32; ] { tmp:1 DinsXSize: mysize is msbd & lsb [ mysize = msbd - lsb + 1 + 32; ] { tmp:1 = mysize; export tmp; } @endif +define pcodeop setISAMode; + macro JXWritePC(addr) { @ifdef ISA_VARIANT ISAModeSwitch = (addr & 0x1) != 0; + setISAMode(ISAModeSwitch); tmp:$(REGSIZE) = -2; tmp = tmp & addr; pc = tmp; diff --git a/pypcode/processors/MIPS/data/languages/mips16.sinc b/pypcode/processors/MIPS/data/languages/mips16.sinc index 61175f27..56c13530 100644 --- a/pypcode/processors/MIPS/data/languages/mips16.sinc +++ b/pypcode/processors/MIPS/data/languages/mips16.sinc @@ -12,6 +12,14 @@ define token m16instr (16) m16_op=(11,15) + m16_rd0_0 = (0,4) + m16_rd0_1 = (0,4) + m16_rd0_2 = (0,4) + m16_rd0_3 = (0,4) + m16_rd0_4 = (0,4) + m16_rd0_5 = (0,4) + m16_rd0_6 = (0,4) + m16_rd0_7 = (0,4) m16_i_imm=(0,4) m16_rx=(8,10) m16_rxa=(8,10) @@ -74,6 +82,95 @@ attach variables [ ext_m16r32 m16_i8_r32 ] [ t8 t9 k0 k1 gp sp s8 ra ]; + +attach variables [ m16_rd0_0 ] [ + Index Random EntryLo0 EntryLo1 + Context PageMask Wired HWREna + BadVAddr Count EntryHi Compare + Status Cause EPC PRId + Config LLAddr WatchLo WatchHi + XContext cop0_reg21 cop0_reg22 Debug + DEPC PerfCnt ErrCtl CacheErr + TagLo TagHi ErrorEPC DESAVE +]; + +attach variables [ m16_rd0_1 ] [ + MVPControl VPEControl TCStatus cop0_reg3.1 + ContextConfig PageGrain SRSConf0 cop0_reg7.1 + cop0_reg8.1 cop0_reg9.1 cop0_reg10.1 cop0_reg11.1 + IntCtl cop0_reg13.1 cop0_reg14.1 EBase + Config1 cop0_reg17.1 WatchLo.1 WatchHi.1 + cop0_reg20.1 cop0_reg21.1 cop0_reg22.1 TraceControl + cop0_reg24.1 PerfCnt.1 cop0_reg26.1 CacheErr.1 + DataLo.1 DataHi.1 cop0_reg30.1 cop0_reg31.1 +]; + +attach variables [ m16_rd0_2 ] [ + MVPConf0 VPEConf0 TCBind cop0_reg3.2 + cop0_reg4.2 cop0_reg5.2 SRSConf1 cop0_reg7.2 + cop0_reg8.2 cop0_reg9.2 cop0_reg10.2 cop0_reg11.2 + SRSCtl cop0_reg13.2 cop0_reg14.2 cop0_reg15.2 + Config2 cop0_reg17.2 WatchLo.2 WatchHi.2 + cop0_reg20.2 cop0_reg21.2 cop0_reg22.2 TraceControl2 + cop0_reg24.2 PerfCnt.2 cop0_reg26.2 CacheErr.2 + TagLo.2 TagHi.2 cop0_reg30.2 cop0_reg31.2 +]; + +attach variables [ m16_rd0_3 ] [ + MVPConf1 VPEConf1 TCRestart cop0_reg3.3 + cop0_reg4.3 cop0_reg5.3 SRSConf2 cop0_reg7.3 + cop0_reg8.3 cop0_reg9.3 cop0_reg10.3 cop0_reg11.3 + SRSMap cop0_reg13.3 cop0_reg14.3 cop0_reg15.3 + Config3 cop0_reg17.3 WatchLo.3 WatchHi.3 + cop0_reg20.3 cop0_reg21.3 cop0_reg22.3 UserTraceData + cop0_reg24.3 PerfCnt.3 cop0_reg26.3 CacheErr.3 + DataLo.3 DataHi.3 cop0_reg30.3 cop0_reg31.3 +]; + +attach variables [ m16_rd0_4 ] [ + cop0_reg0.4 YQMask TCHalt cop0_reg3.4 + cop0_reg4.4 cop0_reg5.4 SRSConf3 cop0_reg7.4 + cop0_reg8.4 cop0_reg9.4 cop0_reg10.4 cop0_reg11.4 + cop0_reg12.4 cop0_reg13.4 cop0_reg14.4 cop0_reg15.4 + cop0_reg16.4 cop0_reg17.4 WatchLo.4 WatchHi.4 + cop0_reg20.4 cop0_reg21.4 cop0_reg22.4 TraceBPC + cop0_reg24.4 PerfCnt.4 cop0_reg26.4 CacheErr.4 + TagLo.4 TagHi.4 cop0_reg30.4 cop0_reg31.4 +]; + +attach variables [ m16_rd0_5 ] [ + cop0_reg0.5 VPESchedule TCContext cop0_reg3.5 + cop0_reg4.5 cop0_reg5.5 SRSConf4 cop0_reg7.5 + cop0_reg8.5 cop0_reg9.5 cop0_reg10.5 cop0_reg11.5 + cop0_reg12.5 cop0_reg13.5 cop0_reg14.5 cop0_reg15.5 + cop0_reg16.5 cop0_reg17.5 WatchLo.5 WatchHi.5 + cop0_reg20.5 cop0_reg21.5 cop0_reg22.5 cop0_reg23.5 + cop0_reg24.5 PerfCnt.5 cop0_reg26.5 CacheErr.5 + DataLo.5 DataHi.5 cop0_reg30.5 cop0_reg31.5 +]; + +attach variables [ m16_rd0_6 ] [ + cop0_reg0.6 VPEScheFBack TCSchedule cop0_reg3.6 + cop0_reg4.6 cop0_reg5.6 cop0_reg6.6 cop0_reg7.6 + cop0_reg8.6 cop0_reg9.6 cop0_reg10.6 cop0_reg11.6 + cop0_reg12.6 cop0_reg13.6 cop0_reg14.6 cop0_reg15.6 + cop0_reg16.6 cop0_reg17.6 WatchLo.6 WatchHi.6 + cop0_reg20.6 cop0_reg21.6 cop0_reg22.6 cop0_reg23.6 + cop0_reg24.6 PerfCnt.6 cop0_reg26.6 CacheErr.6 + TagLo.6 TagHi.6 cop0_reg30.6 cop0_reg31.6 +]; + +attach variables [ m16_rd0_7 ] [ + cop0_reg0.7 VPEOpt TCScheFBack cop0_reg3.7 + cop0_reg4.7 cop0_reg5.7 cop0_reg6.7 cop0_reg7.7 + cop0_reg8.7 cop0_reg9.7 cop0_reg10.7 cop0_reg11.7 + cop0_reg12.7 cop0_reg13.7 cop0_reg14.7 cop0_reg15.7 + cop0_reg16.7 cop0_reg17.7 WatchLo.7 WatchHi.7 + cop0_reg20.7 cop0_reg21.7 cop0_reg22.7 cop0_reg23.7 + cop0_reg24.7 PerfCnt.7 cop0_reg26.7 CacheErr.7 + DataLo.7 DataHi.7 cop0_reg30.7 cop0_reg31.7 +]; + @ifdef MIPS64 attach variables [ m16_rxa m16_rya m16_rza m16_mv_rza] [ s0_lo s1_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo ]; @@ -87,6 +184,7 @@ attach variables [ ext_m16r32a m16_i8_r32a ] [ RZ: m16_rz is m16_rz { export m16_rz; } + @else # !MIPS64 attach variables [ m16_rxa m16_rya m16_rza m16_mv_rza ] [ s0 s1 v0 v1 a0 a1 a2 a3 ]; @@ -517,7 +615,8 @@ SAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT is EXT_FRAME & SAVE_RA } -:jal Abs26_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=0 & Abs26_m16 [ ext_delay=0b10; globalset(inst_next, ext_delay);] { +:jal Abs26_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=0 & Abs26_m16 +[ ext_delay=0b10; globalset(inst_next, ext_delay); ] { ra = inst_next | 0x1; delayslot( 1 ); call Abs26_m16; @@ -525,7 +624,7 @@ SAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT is EXT_FRAME & SAVE_RA } :jalr m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=1 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx -[ ext_delay=0b01; globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { +[ ext_delay=0b01; globalset(inst_next, ext_delay); ] { JXWritePC(m16_rx); ra = inst_next | 0x1; delayslot( 1 ); @@ -539,22 +638,23 @@ SAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT is EXT_FRAME & SAVE_RA } :jalx Abs26_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=1 & Abs26_m16 -[ ext_delay=0b10; ISA_MODE = 0; globalset(Abs26_m16, ISA_MODE); globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { - ra = inst_next | 0x1; +[ ext_delay=0b10; ISA_MODE = 0; globalset(Abs26_m16, ISA_MODE); globalset(inst_next, ext_delay); ] { + ra = inst_next | 0x1; delayslot( 1 ); - ISAModeSwitch = 0; + ISAModeSwitch = 0; + setISAMode(ISAModeSwitch); call Abs26_m16; } :jr ra is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=1 & ra & m16_rr_f=0b00000 & m16_rx=0 -[ ext_delay=0b01; globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { +[ ext_delay=0b01; globalset(inst_next, ext_delay); ] { JXWritePC(ra); delayslot( 1 ); return [pc]; } :jr m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx -[ ext_delay=0b01; globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { +[ ext_delay=0b01; globalset(inst_next, ext_delay); ] { JXWritePC(m16_rx); delayslot( 1 ); goto [pc]; @@ -883,7 +983,7 @@ E2_REGOFF: imm is ext_imm_2124 & m16_i_imm [ imm = m16_i_imm | (ext_imm_2124 << lockload(tmp); } -:lui m16_rx, EXT_LIU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01101 & m16_rx & m16_ri_z=1 & EXT_LIU8 { +:lui m16_rx, EXT_LIU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b01101 & m16_rx & m16_ri_z=1 & EXT_LIU8 { m16_rx = zext(EXT_LIU8) << 16; } @@ -911,14 +1011,24 @@ E2_REGOFF: imm is ext_imm_2124 & m16_i_imm [ imm = m16_i_imm | (ext_imm_2124 << m16_rx = sext( valOrig | valLoad ); } -:mfc0 m16_ry, m16_i_imm, ext_imm_2123 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=0 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm { - m16_ry = getCopReg(0:1,m16_i_imm:1,ext_imm_2123:1); + +m16_RD0: m16_rd0_0 is m16_rd0_0 & ext_imm_2123=0 { export m16_rd0_0; } +m16_RD0: m16_rd0_1 is m16_rd0_1 & ext_imm_2123=1 { export m16_rd0_1; } +m16_RD0: m16_rd0_2 is m16_rd0_2 & ext_imm_2123=2 { export m16_rd0_2; } +m16_RD0: m16_rd0_3 is m16_rd0_3 & ext_imm_2123=3 { export m16_rd0_3; } +m16_RD0: m16_rd0_4 is m16_rd0_4 & ext_imm_2123=4 { export m16_rd0_4; } +m16_RD0: m16_rd0_5 is m16_rd0_5 & ext_imm_2123=5 { export m16_rd0_5; } +m16_RD0: m16_rd0_6 is m16_rd0_6 & ext_imm_2123=6 { export m16_rd0_6; } +m16_RD0: m16_rd0_7 is m16_rd0_7 & ext_imm_2123=7 { export m16_rd0_7; } + +:mfc0 m16_ry, m16_RD0 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=0 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_RD0 { + m16_ry = zext( m16_RD0:$(SIZETO4) ); } -:mtc0 m16_ry, m16_i_imm, ext_imm_2123 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=1 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm { - setCopReg(0:1,m16_ry,m16_i_imm:1,ext_imm_2123:1); +:mtc0 m16_ry, m16_RD0 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=1 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_RD0 { + setCopReg(0:1, m16_RD0, m16_ry); } -:movz m16_rx, m16_ry, ext_rb is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=1 & m16_shft_f=0b10 { +:movz m16_rx, ext_rb, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=1 & m16_shft_f=0b10 { if(m16_ry != 0) goto inst_next; m16_rx = ext_rb; } @@ -928,7 +1038,7 @@ E2_REGOFF: imm is ext_imm_2124 & m16_i_imm [ imm = m16_i_imm | (ext_imm_2124 << m16_rx = 0; } -:movn m16_rx, m16_ry, ext_rb is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=2 & m16_shft_f=0b10 { +:movn m16_rx, ext_rb, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=2 & m16_shft_f=0b10 { if(m16_ry == 0) goto inst_next; m16_rx = ext_rb; } diff --git a/pypcode/processors/MIPS/data/languages/mips32.pspec b/pypcode/processors/MIPS/data/languages/mips32.pspec index f4cb53e2..3bcfe9ea 100644 --- a/pypcode/processors/MIPS/data/languages/mips32.pspec +++ b/pypcode/processors/MIPS/data/languages/mips32.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/MIPS/data/languages/mips32Instructions.sinc b/pypcode/processors/MIPS/data/languages/mips32Instructions.sinc index de6a1fad..4e8a72f2 100644 --- a/pypcode/processors/MIPS/data/languages/mips32Instructions.sinc +++ b/pypcode/processors/MIPS/data/languages/mips32Instructions.sinc @@ -191,11 +191,13 @@ define pcodeop special2; # 0100 0010 0000 0000 0000 0000 0001 1000 :eret is $(AMODE) & prime=0x10 & fct=0x18 & bit25=1 & copfill=0 { - return[EPC]; + JXWritePC(EPC); + return[EPC]; } :eretnc is $(AMODE) & prime=0x10 & fct=0x18 & bit25=1 & copfill=1 { - return[EPC]; + JXWritePC(EPC); + return[EPC]; } # 0111 11ss ssst tttt mmmm mLLL LL00 0000 @@ -423,13 +425,13 @@ define pcodeop special2; # 0100 1000 000t tttt iiii iiii iiii iiii :mfc2 RT, immed is $(AMODE) & prime=0x12 & copop=0 & RT & immed { - tmp:$(REGSIZE) = getCopReg(2:1, immed:4); + tmp:4 = getCopReg(2:1, immed:4); RT = sext( tmp ); } # 0100 1000 011t tttt iiii iiii iiii iiii :mfhc2 RT, immed is $(AMODE) & prime=0x12 & copop=3 & RT & fs & immed { - tmp:$(REGSIZE) = getCopReg(2:1, immed:4); + tmp:4 = getCopReg(2:1, immed:4); RT = sext(tmp >> 32); } @@ -450,16 +452,20 @@ define pcodeop special2; } # 0100 0000 100t tttt dddd d000 0000 0sss -:mtc0 RTsrc, RD0, sel is $(AMODE) & prime=0x10 & copop=4 & RTsrc & RD0 & zero6=0 & sel { - setCopReg(0:1, RD0, RTsrc, sel:1); +:mtc0 RTsrc, RD0 is $(AMODE) & prime=0x10 & copop=4 & RTsrc & RD0 & zero6=0 { + setCopReg(0:1, RD0, RTsrc); } + # 0100 1000 100t tttt iiii iiii iiii iiii :mtc2 RTsrc, immed is $(AMODE) & prime=0x12 & copop=4 & RTsrc & immed { setCopReg(2:1, immed:4, RTsrc); } :mthc0 RTsrc, RD0, sel is $(AMODE) & prime=0x10 & copop=6 & RTsrc & RD0 & zero6=0 & sel { - setCopReg(0:1, RD0, RTsrc, sel:1); + tmp:4 = RTsrc:$(SIZETO4); + low:4 = RD0:4; + val:8 = (zext(tmp) << 32) + zext(low); + setCopReg(0:1, RD0, val); } # 0100 1000 111t tttt iiii iiii iiii iiii @@ -1012,6 +1018,7 @@ define pcodeop SYNC; ra = inst_next; delayslot( 1 ); ISAModeSwitch = 1; + setISAMode(ISAModeSwitch); call Abs26; } @endif @@ -1747,5 +1754,224 @@ define pcodeop SYNC; signalReservedInstruction(immed:2); } +rsRa: is svrs_ra=0 {} +rsRa: ra is svrs_ra=1 & ra { + tsp = tsp-$(REGSIZE); + MemSrcCast(ra,tsp); +} + +svRa: is svrs_ra=0 {} +svRa: ra is svrs_ra=1 & ra { + tsp = tsp-$(REGSIZE); + MemDestCast(tsp,ra); +} + +rs_statReg: is svrs_areg {} +rs_statReg: ",a3" is (svrs_areg=1 | svrs_areg=5 | svrs_areg=9 |svrs_areg=0xd) { + tsp = tsp-4; + MemSrcCast(a3,tsp); +} +rs_statReg: ",a2-a3" is (svrs_areg=2 | svrs_areg=6 | svrs_areg=0xa) { + tsp = tsp-4; + MemSrcCast(a3,tsp); + tsp = tsp-4; + MemSrcCast(a2,tsp); +} +rs_statReg: ",a1-a3" is (svrs_areg=3 | svrs_areg=7) { + tsp = tsp-4; + MemSrcCast(a3,tsp); + tsp = tsp-4; + MemSrcCast(a2,tsp); + tsp = tsp-4; + MemSrcCast(a1,tsp); +} +rs_statReg: ",a0-a3" is svrs_areg=0xb { + tsp = tsp-4; + MemSrcCast(a3,tsp); + tsp = tsp-4; + MemSrcCast(a2,tsp); + tsp = tsp-4; + MemSrcCast(a1,tsp); + tsp = tsp-4; + MemSrcCast(a0,tsp); +} + +rsStat: is svrs_areg=0 | svrs_areg=4 | svrs_areg=8 | svrs_areg=0xc | svrs_areg=0xe {} +rsStat: rs_statReg is rs_statReg { + build rs_statReg; +} + + +sv_statReg: is svrs_areg {} +sv_statReg: ",a3" is (svrs_areg=1 | svrs_areg=5 | svrs_areg=9 | svrs_areg=0xd) { + tsp = tsp-4; + MemDestCast(tsp,a3); +} +sv_statReg: ",a2-a3" is (svrs_areg=2 | svrs_areg=6 | svrs_areg=0xa) { + tsp = tsp-4; + MemDestCast(tsp,a3); + tsp = tsp-4; + MemDestCast(tsp,a2); +} +sv_statReg: ",a1-a3" is (svrs_areg=3 | svrs_areg=7) { + tsp = tsp-4; + MemDestCast(tsp,a3); + tsp = tsp-4; + MemDestCast(tsp,a2); + tsp = tsp-4; + MemDestCast(tsp,a1); +} +sv_statReg: ",a0-a3" is svrs_areg=0xb { + tsp = tsp-4; + MemDestCast(tsp,a3); + tsp = tsp-4; + MemDestCast(tsp,a2); + tsp = tsp-4; + MemDestCast(tsp,a1); + tsp = tsp-4; + MemDestCast(tsp,a0); +} + +svStat: is svrs_areg=0 | svrs_areg=4 | svrs_areg=8 | svrs_areg=0xc | svrs_areg=0xe {} +svStat: sv_statReg is sv_statReg { + build sv_statReg; +} + +sv_areg1: is svrs_aregb2=0 {} +sv_areg1: "a0," is svrs_aregb2=1 { + ptr:$(REGSIZE) = sp; + MemDestCast(ptr,a0); +} + +sv_areg2: sv_areg1 is sv_areg1 { build sv_areg1; } +sv_areg2: "a0-a1," is svrs_aregb3=1 & svrs_aregb2=0 & (svrs_aregb1=0 | svrs_aregb0=0) { + ptr:$(REGSIZE) = sp; + MemDestCast(ptr,a0); + ptr = sp+4; + MemDestCast(ptr,a1); +} + +sv_areg3: sv_areg2 is sv_areg2 { build sv_areg2; } +sv_areg3: "a0-a2," is svrs_aregb3=1 & svrs_aregb2=1 & svrs_aregb1=0 { + ptr:$(REGSIZE) = sp; + MemDestCast(ptr,a0); + ptr = sp+4; + MemDestCast(ptr,a1); + ptr = sp+8; + MemDestCast(ptr,a2); +} + +sv_areg4: sv_areg3 is sv_areg3 { build sv_areg3; } +sv_areg4: "a0-a3," is svrs_areg=0xe { + ptr:$(REGSIZE) = sp; + MemDestCast(ptr,a0); + ptr = sp+4; + MemDestCast(ptr,a1); + ptr = sp+8; + MemDestCast(ptr,a2); + ptr = sp+12; + MemDestCast(ptr,a3); +} + +svAregs: is svrs_aregb3=0 | svrs_areg=0xb | svrs_areg=0xf {} +svAregs: sv_areg4 is sv_areg4 { + build sv_areg4; +} + +rs_s0: is svrs_s0 {} +rs_s0: is svrs_s0=1 { tsp = tsp-$(REGSIZE); MemSrcCast(s0,tsp); } + +rs_s1: is svrs_s1 {} +rs_s1: is svrs_s1=1 { tsp = tsp-$(REGSIZE); MemSrcCast(s1,tsp); } + +rs_s8: is svrs_xreg=6 {} +rs_s8: is svrs_xreg { tsp = tsp-$(REGSIZE); MemSrcCast(s8,tsp); } + +rs_s7: is svrs_xreg=5 {} +rs_s7: is rs_s8 { build rs_s8; tsp = tsp-$(REGSIZE); MemSrcCast(s7,tsp); } + +rs_s6: is svrs_xreg=4 {} +rs_s6: is rs_s7 { build rs_s7; tsp = tsp-$(REGSIZE); MemSrcCast(s6,tsp); } + +rs_s5: is svrs_xreg=3 {} +rs_s5: is rs_s6 { build rs_s6; tsp = tsp-$(REGSIZE); MemSrcCast(s5,tsp); } + +rs_s4: is svrs_xreg=2 {} +rs_s4: is rs_s5 { build rs_s5; tsp = tsp-$(REGSIZE); MemSrcCast(s4,tsp); } + +rs_s3: is svrs_xreg=1 {} +rs_s3: is rs_s4 { build rs_s4; tsp = tsp-$(REGSIZE); MemSrcCast(s3,tsp); } + +rs_s2: is svrs_xreg=0 {} +rs_s2: is rs_s3 { build rs_s3; tsp = tsp-$(REGSIZE); MemSrcCast(s2,tsp); } + +rsXsregs: is svrs_s0=0 & svrs_s1=0 & svrs_xreg=0 {} +rsXsregs: ","svrs_xreg is svrs_s0 & svrs_s1 & svrs_xreg & rs_s2 & rs_s1 & rs_s0 { + build rs_s2; + build rs_s1; + build rs_s0; +} + +sv_s0: is svrs_s0 {} +sv_s0: is svrs_s0=1 { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s0);} + +sv_s1: is svrs_s1 {} +sv_s1: is svrs_s1=1 { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s1); } + +sv_s8: is svrs_xreg=6 {} +sv_s8: is svrs_xreg { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s8); } + +sv_s7: is svrs_xreg=5 {} +sv_s7: is sv_s8 { build sv_s8; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s7); } + +sv_s6: is svrs_xreg=4 {} +sv_s6: is sv_s7 { build sv_s7; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s6); } +sv_s5: is svrs_xreg=3 {} +sv_s5: is sv_s6 { build sv_s6; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s5); } + +sv_s4: is svrs_xreg=2 {} +sv_s4: is sv_s5 { build sv_s5; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s4); } + +sv_s3: is svrs_xreg=1 {} +sv_s3: is sv_s4 { build sv_s4; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s3); } + +sv_s2: is svrs_xreg=0 {} +sv_s2: is sv_s3 { build sv_s3; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s2); } + +svXsregs: is svrs_s0=0 & svrs_s0=0 & svrs_xreg=0 {} +svXsregs: ","svrs_xreg is svrs_s0 & svrs_s1 & svrs_xreg & sv_s0 & sv_s1 & sv_s2 { + build sv_s2; + build sv_s1; + build sv_s0; +} + +svFramesize: ,val is svrs_frame_hi=0 & svrs_frame_low=0 [val = 128; ] {export *[const]:2 val;} +svFramesize: ,val is svrs_frame_hi & svrs_frame_low [val = ((svrs_frame_hi << 4) | svrs_frame_low) << 3;] {export *[const]:2 val;} + + +:save svRa^svXsregs^svAregs^svFramesize is $(AMODE) & prime=0x1c & fct=0x1f & save=0x01 & svRa & svXsregs & svAregs & svStat & svFramesize { + tsp = sp; + build svAregs; + build svRa; + build svXsregs; + build svStat; + build svFramesize; + + tmp:2 = svFramesize; + sp = sp - zext(tmp); +} + +:restore rsRa^rsXsregs^rsStat^svFramesize is $(AMODE) & prime=0x1c & fct=0x1f & save=0x00 & rsRa & rsXsregs & rsStat & svFramesize { + build svFramesize; + + tmp:2 = svFramesize; + tsp = sp+zext(tmp); + + build rsRa; + build rsXsregs; + build rsStat; + + sp = sp+zext(tmp); +} @include "mipsfloat.sinc" diff --git a/pypcode/processors/MIPS/data/languages/mips32R6.pspec b/pypcode/processors/MIPS/data/languages/mips32R6.pspec index 6bcce3f4..66177d02 100644 --- a/pypcode/processors/MIPS/data/languages/mips32R6.pspec +++ b/pypcode/processors/MIPS/data/languages/mips32R6.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/MIPS/data/languages/mips32_eabi.cspec b/pypcode/processors/MIPS/data/languages/mips32_eabi.cspec index 235b5351..7868b883 100644 --- a/pypcode/processors/MIPS/data/languages/mips32_eabi.cspec +++ b/pypcode/processors/MIPS/data/languages/mips32_eabi.cspec @@ -154,5 +154,15 @@ - + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips32_fp64.cspec b/pypcode/processors/MIPS/data/languages/mips32_fp64.cspec index 2e061b20..eb73508e 100644 --- a/pypcode/processors/MIPS/data/languages/mips32_fp64.cspec +++ b/pypcode/processors/MIPS/data/languages/mips32_fp64.cspec @@ -84,5 +84,15 @@ - + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips32be.cspec b/pypcode/processors/MIPS/data/languages/mips32be.cspec index bd621b77..3327ed70 100644 --- a/pypcode/processors/MIPS/data/languages/mips32be.cspec +++ b/pypcode/processors/MIPS/data/languages/mips32be.cspec @@ -183,6 +183,15 @@ - - + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips32le.cspec b/pypcode/processors/MIPS/data/languages/mips32le.cspec index 13e5c299..f1e74a50 100644 --- a/pypcode/processors/MIPS/data/languages/mips32le.cspec +++ b/pypcode/processors/MIPS/data/languages/mips32le.cspec @@ -174,5 +174,15 @@ - + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips32micro.pspec b/pypcode/processors/MIPS/data/languages/mips32micro.pspec index 2db2de7b..22ed608c 100644 --- a/pypcode/processors/MIPS/data/languages/mips32micro.pspec +++ b/pypcode/processors/MIPS/data/languages/mips32micro.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/MIPS/data/languages/mips64.pspec b/pypcode/processors/MIPS/data/languages/mips64.pspec index 0dca0029..739c58f7 100644 --- a/pypcode/processors/MIPS/data/languages/mips64.pspec +++ b/pypcode/processors/MIPS/data/languages/mips64.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/MIPS/data/languages/mips64R6.pspec b/pypcode/processors/MIPS/data/languages/mips64R6.pspec index 53695d33..f7b5f558 100644 --- a/pypcode/processors/MIPS/data/languages/mips64R6.pspec +++ b/pypcode/processors/MIPS/data/languages/mips64R6.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/MIPS/data/languages/mips64_32_n32.cspec b/pypcode/processors/MIPS/data/languages/mips64_32_n32.cspec index 255cb362..15252a8e 100644 --- a/pypcode/processors/MIPS/data/languages/mips64_32_n32.cspec +++ b/pypcode/processors/MIPS/data/languages/mips64_32_n32.cspec @@ -133,4 +133,15 @@ + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips64_32_o32.cspec b/pypcode/processors/MIPS/data/languages/mips64_32_o32.cspec index 1b01bf46..35e48441 100644 --- a/pypcode/processors/MIPS/data/languages/mips64_32_o32.cspec +++ b/pypcode/processors/MIPS/data/languages/mips64_32_o32.cspec @@ -125,4 +125,15 @@ + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips64_32_o64.cspec b/pypcode/processors/MIPS/data/languages/mips64_32_o64.cspec index bbb7a459..15c9a4d6 100644 --- a/pypcode/processors/MIPS/data/languages/mips64_32_o64.cspec +++ b/pypcode/processors/MIPS/data/languages/mips64_32_o64.cspec @@ -95,4 +95,15 @@ + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips64be.cspec b/pypcode/processors/MIPS/data/languages/mips64be.cspec index dbcf456c..f0fdd2c3 100644 --- a/pypcode/processors/MIPS/data/languages/mips64be.cspec +++ b/pypcode/processors/MIPS/data/languages/mips64be.cspec @@ -186,4 +186,15 @@ + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips64le.cspec b/pypcode/processors/MIPS/data/languages/mips64le.cspec index 6cebc649..0c5842d7 100644 --- a/pypcode/processors/MIPS/data/languages/mips64le.cspec +++ b/pypcode/processors/MIPS/data/languages/mips64le.cspec @@ -170,4 +170,15 @@ + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips64micro.pspec b/pypcode/processors/MIPS/data/languages/mips64micro.pspec index 7819d36f..e03bb43f 100644 --- a/pypcode/processors/MIPS/data/languages/mips64micro.pspec +++ b/pypcode/processors/MIPS/data/languages/mips64micro.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/MIPS/data/languages/mipsmicro.sinc b/pypcode/processors/MIPS/data/languages/mipsmicro.sinc index f9fc0d99..24561f06 100644 --- a/pypcode/processors/MIPS/data/languages/mipsmicro.sinc +++ b/pypcode/processors/MIPS/data/languages/mipsmicro.sinc @@ -1313,7 +1313,7 @@ STORE_TOP16: STORE_SREG^ra,EXT_CODE4E(sp) is mic_listr6 & REL6=1 & STORE_SREG & break(mic_code:2); } -:sdbbp16 SDB16 is ISA_MODE=1 & RELP=0 & mic_op=0b100010 & SDB16 & ((mic_break=0b101100 & REL6=0) | (mic_breakr6=0b111011 & REL6=1)) { +:sdbbp16 SDB16 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & SDB16 & ((mic_break=0b101100 & REL6=0) | (mic_breakr6=0b111011 & REL6=1)) { break(SDB16); } @@ -2369,7 +2369,8 @@ STORE_TOP16: STORE_SREG^ra,EXT_CODE4E(sp) is mic_listr6 & REL6=1 & STORE_SREG & :jalx Abs26_mic2 is ISA_MODE=1 & RELP=0 & mic_op=0b111100 & REL6=0 & mic_code ; Abs26_mic2 [ ext_32_code = mic_code; ISA_MODE = 0; globalset(Abs26_mic2, ISA_MODE);] { ra = inst_next | 0x1; delayslot( 1 ); - ISAModeSwitch = 0; + ISAModeSwitch = 0; + setISAMode(ISAModeSwitch); call Abs26_mic2; } diff --git a/pypcode/processors/PIC/data/languages/pic18_instructions.sinc b/pypcode/processors/PIC/data/languages/pic18_instructions.sinc index a5c5fa85..5c28d527 100644 --- a/pypcode/processors/PIC/data/languages/pic18_instructions.sinc +++ b/pypcode/processors/PIC/data/languages/pic18_instructions.sinc @@ -340,7 +340,7 @@ fREGLoc: freg is a=0 & f8=0xdb & freg { } # Direct File register data -srcREG: fREGLoc is fREGLoc { export fREGLoc; } +srcREG: fREGLoc is fREGLoc { export fREGLoc; } # PCL read - latch PC into PCL, PCLATH, and PCLATU srcREG: "PC" is a=0 & f8=0xf9 { @@ -348,18 +348,133 @@ srcREG: "PC" is a=0 & f8=0xf9 { export PCL; } -# Destination register (either srcREG or WREG) -destREG: "0" is d=0 { export WREG; } -destREG: "1" is d=1 & srcREG { export srcREG; } -#destREG: "1" is d=1 & f8=0xf9 { -# # Storing to PCL must write the PC using both the stored PCL (PC<7:0>), PCLATH (PC<15:8>) and PCLATU (PC<21:16>) -# # The ADDWF and MOVWF definitions below have a specific case to handle this write to PCL -# export PCL; -#} +dfLoc: f8 is a=1 & f8 { # (Banked mode) + addr:2 = (zext(BSR) << 8) + f8; + export *[DATA]:1 addr; +} + +dfLoc: f8 is a=0 & f8_57=0x0 & f8 { export *[DATA]:1 f8; } # 0x00-0x1f (Access mode) +dfLoc: f8 is a=0 & f8_57=0x1 & f8 { export *[DATA]:1 f8; } # 0x20-0x3f (Access mode) +dfLoc: f8 is a=0 & f8_57=0x2 & f8 { export *[DATA]:1 f8; } # 0x40-0x5f (Access mode) +dfLoc: freg is a=0 & freg { export freg; } # 0xf60-0xfff (Access mode) + +# TOSL - access mirrored into stack space using STKPTR +dfLoc: freg is a=0 & f8=0xfd & freg { + addr:1 = STKPTR + 1; + export *[HWSTACK]:1 addr; +} + +# TOSH - access mirrored into stack space using STKPTR +dfLoc: freg is a=0 & f8=0xfe & freg { + addr:1 = STKPTR + 2; + export *[HWSTACK]:1 addr; +} + +# TOSU - access mirrored into stack space using STKPTR +dfLoc: freg is a=0 & f8=0xff & freg { + addr:1 = STKPTR + 3; + export *[HWSTACK]:1 addr; +} + +# Indirect File Register access - INDF0 +dfLoc: freg is a=0 & f8=0xef & freg { + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF1 +dfLoc: freg is a=0 & f8=0xe7 & freg { + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF2 +dfLoc: freg is a=0 & f8=0xdf & freg { + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +## Post-increment File Register access - POSTINC0 +dfLoc: freg is a=0 & f8=0xee & freg { + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC1 +dfLoc: freg is a=0 & f8=0xe6 & freg { + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC2 +dfLoc: freg is a=0 & f8=0xde & freg { + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC0 +dfLoc: freg is a=0 & f8=0xed & freg { + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC1 +dfLoc: freg is a=0 & f8=0xe5 & freg { + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +dfLoc: freg is a=0 & f8=0xdd & freg { + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC0 +dfLoc: freg is a=0 & f8=0xec & freg { + FSR0 = FSR0 + 1; + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC1 +dfLoc: freg is a=0 & f8=0xe4 & freg { + FSR1 = FSR1 + 1; + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC2 +dfLoc: freg is a=0 & f8=0xdc & freg { + FSR2 = FSR2 + 1; + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW0 +dfLoc: freg is a=0 & f8=0xeb & freg { + FSR0 = FSR0 + 1; + addr:2 = FSR0 + sext(WREG); + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW1 +dfLoc: freg is a=0 & f8=0xe3 & freg { + FSR1 = FSR1 + 1; + addr:2 = FSR1 + sext(WREG); + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW2 +dfLoc: freg is a=0 & f8=0xdb & freg { + FSR2 = FSR2 + 1; + addr:2 = FSR2 + sext(WREG); + export *[DATA]:1 addr; +} # Destination operand representation (w: W register is destination; f: specified fREG is destination) -D: "w" is d=0 { } -D: "f" is d=1 { } +# Destination register (either srcREG or WREG) +destREG: "w" is d=0 { export WREG; } +destREG: "f" is d=1 & dfLoc { export dfLoc; } # Source File Registers specified by a 12-bit absolute offsets within 32-bit instriction srcREG32: fs is fs { export *[DATA]:1 fs; } # 0x000-0xeff @@ -667,7 +782,7 @@ A: "BANKED" is a=1 { } # BYTE-ORIENTED FILE REGISTER OPERATIONS # -:ADDWF srcREG, D, A is op6=0x09 & srcREG & A & destREG & D { +:ADDWF srcREG, destREG, A is op6=0x09 & srcREG & destREG & A { # 0010 01da ffff ffff # 0010 0100 0000 0000 -> ADDWF DAT_DATA_0000, w, ACCESS # 0010 0101 0000 0000 -> ADDWF REG0x0, w, BANKED @@ -677,7 +792,8 @@ A: "BANKED" is a=1 { } # 0010 0111 0000 0000 -> ADDWF REG0x0, f, BANKED # 0010 0110 1101 1000 -> ADDWF STATUS, f, ACCESS # 0010 0111 1101 1000 -> ADDWF REG0xD8, f, BANKED - # 0010 0100 1111 1001 -> ADDWF PC, w, ACCESS + build destREG; + build srcREG; tmp:1 = srcREG; # read only once! setAddFlags(tmp, WREG); tmp = tmp + WREG; @@ -685,7 +801,7 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:ADDWF pcl, D, A is op6=0x09 & A & D & d=1 & pcl { +:ADDWF pcl, destREG, A is op6=0x09 & A & destREG & pcl { # 0010 01da ffff ffff # 0010 0110 1111 1001 -> ADDWF PC, f, ACCESS addr:3 = inst_start; @@ -700,7 +816,7 @@ A: "BANKED" is a=1 { } goto [addr]; } -:ADDWFC srcREG, D, A is op6=0x08 & srcREG & destREG & D & A { +:ADDWFC srcREG, destREG, A is op6=0x08 & srcREG & destREG & A { # 0010 00da ffff ffff # 0010 0000 0000 0000 -> ADDWFC DAT_DATA_0000, w, ACCESS # 0010 0001 0000 0000 -> ADDWFC REG0x0, w, BANKED @@ -710,6 +826,8 @@ A: "BANKED" is a=1 { } # 0010 0011 0000 0000 -> ADDWFC REG0x0, f, BANKED # 0010 0010 1101 1000 -> ADDWFC STATUS, f, ACCESS # 0010 0011 1101 1000 -> ADDWFC REG0xD8, f, BANKED + build destREG; + build srcREG; local tmpC = C & 1; tmp:1 = srcREG; setAddCFlags(tmp, WREG); @@ -718,7 +836,7 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:ANDWF srcREG, D, A is op6=0x05 & srcREG & destREG & D & A { +:ANDWF srcREG, destREG, A is op6=0x05 & srcREG & destREG & A { # 0001 01da ffff ffff # 0001 0100 0000 0000 -> ANDWF DAT_DATA_0000, w, ACCESS # 0001 0101 0000 0000 -> ANDWF REG0x0, w, BANKED @@ -728,6 +846,8 @@ A: "BANKED" is a=1 { } # 0001 0111 0000 0000 -> ANDWF REG0x0, f, BANKED # 0001 0110 1101 1000 -> ANDWF STATUS, f, ACCESS # 0001 0111 1101 1000 -> ANDWF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG & WREG; destREG = tmp; setResultFlags(tmp); @@ -743,7 +863,7 @@ A: "BANKED" is a=1 { } Z = 1; } -:COMF srcREG, D, A is op6=0x07 & srcREG & destREG & D & A { +:COMF srcREG, destREG, A is op6=0x07 & srcREG & destREG & A { # 0001 11da ffff ffff # 0001 1100 0000 0000 -> COMF DAT_DATA_0000, w, ACCESS # 0001 1101 0000 0000 -> COMF REG0x0, w, BANKED @@ -753,6 +873,8 @@ A: "BANKED" is a=1 { } # 0001 1111 0000 0000 -> COMF REG0x0, f, BANKED # 0001 1110 1101 1000 -> COMF STATUS, f, ACCESS # 0001 1111 1101 1000 -> COMF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = ~srcREG; destREG = tmp; setResultFlags(tmp); @@ -785,7 +907,7 @@ A: "BANKED" is a=1 { } if (srcREG < WREG) goto skipInst; } -:DECF srcREG, D, A is op6=0x01 & srcREG & destREG & D & A { +:DECF srcREG, destREG, A is op6=0x01 & srcREG & destREG & A { # 0000 01da ffff ffff # 0000 0100 0000 0000 -> DECF DAT_DATA_0000, w, ACCESS # 0000 0101 0000 0000 -> DECF REG0x0, w, BANKED @@ -795,6 +917,8 @@ A: "BANKED" is a=1 { } # 0000 0111 0000 0000 -> DECF REG0x0, f, BANKED # 0000 0110 1101 1000 -> DECF STATUS, f, ACCESS # 0000 0111 1101 1000 -> DECF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG; setSubtractFlags(tmp, 1); tmp = tmp - 1; @@ -802,7 +926,7 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:DECFSZ srcREG, D, A is op6=0x0b & srcREG & destREG & D & A & skipInst { +:DECFSZ srcREG, destREG, A is op6=0x0b & srcREG & destREG & A & skipInst { # 0010 11da ffff ffff # 0010 1100 0000 0000 -> DECFSZ DAT_DATA_0000, w, ACCESS # 0010 1101 0000 0000 -> DECFSZ REG0x0, w, BANKED @@ -812,12 +936,15 @@ A: "BANKED" is a=1 { } # 0010 1111 0000 0000 -> DECFSZ REG0x0, f, BANKED # 0010 1110 1101 1000 -> DECFSZ STATUS, f, ACCESS # 0010 1111 1101 1000 -> DECFSZ REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG - 1; destREG = tmp; if (tmp == 0) goto skipInst; } -:DCFSNZ srcREG, D, A is op6=0x13 & srcREG & destREG & D & A & skipInst { + +:DCFSNZ srcREG, destREG, A is op6=0x13 & srcREG & destREG & A & skipInst { # 0100 11da ffff ffff # 0100 1100 0000 0000 -> DCFSNZ DAT_DATA_0000, w, ACCESS # 0100 1101 0000 0000 -> DCFSNZ REG0x0, w, BANKED @@ -827,12 +954,15 @@ A: "BANKED" is a=1 { } # 0100 1111 0000 0000 -> DCFSNZ REG0x0, f, BANKED # 0100 1110 1101 1000 -> DCFSNZ STATUS, f, ACCESS # 0100 1111 1101 1000 -> DCFSNZ REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG - 1; destREG = tmp; if (tmp != 0) goto skipInst; } -:INCF srcREG, D, A is op6=0x0a & srcREG & destREG & D & A { + +:INCF srcREG, destREG, A is op6=0x0a & srcREG & destREG & A { # 0010 10da ffff ffff # 0010 1000 0000 0000 -> INCF DAT_DATA_0000, w, ACCESS # 0010 1001 0000 0000 -> INCF REG0x0, w, BANKED @@ -842,6 +972,8 @@ A: "BANKED" is a=1 { } # 0010 1011 0000 0000 -> INCF REG0x0, f, BANKED # 0010 1010 1101 1000 -> INCF STATUS, f, ACCESS # 0010 1011 1101 1000 -> INCF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG; # read once only! setAddFlags(tmp, 1); tmp = tmp + 1; @@ -849,7 +981,7 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:INCFSZ srcREG, D, A is op6=0x0f & srcREG & destREG & D & A & skipInst { +:INCFSZ srcREG, destREG, A is op6=0x0f & srcREG & destREG & A & skipInst { # 0011 11da ffff ffff # 0011 1100 0000 0000 -> INCFSZ DAT_DATA_0000, w, ACCESS # 0011 1101 0000 0000 -> INCFSZ REG0x0, w, BANKED @@ -859,12 +991,14 @@ A: "BANKED" is a=1 { } # 0011 1111 0000 0000 -> INCFSZ REG0x0, f, BANKED # 0011 1110 1101 1000 -> INCFSZ STATUS, f, ACCESS # 0011 1111 1101 1000 -> INCFSZ REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG + 1; destREG = tmp; if (tmp == 0) goto skipInst; } -:INFSNZ srcREG, D, A is op6=0x12 & srcREG & destREG & D & A & skipInst { +:INFSNZ srcREG, destREG, A is op6=0x12 & srcREG & destREG & A & skipInst { # 0100 10da ffff ffff # 0100 1000 0000 0000 -> INFSNZ DAT_DATA_0000, w, ACCESS # 0100 1001 0000 0000 -> INFSNZ REG0x0, w, BANKED @@ -874,12 +1008,14 @@ A: "BANKED" is a=1 { } # 0100 1011 0000 0000 -> INFSNZ REG0x0, f, BANKED # 0100 1010 1101 1000 -> INFSNZ STATUS, f, ACCESS # 0100 1011 1101 1000 -> INFSNZ REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG + 1; destREG = tmp; if (tmp != 0) goto skipInst; } -:IORWF srcREG, D, A is op6=0x04 & srcREG & destREG & D & A { +:IORWF srcREG, destREG, A is op6=0x04 & srcREG & destREG & A { # 0001 00da ffff ffff # 0001 0000 0000 0000 -> IORWF DAT_DATA_0000, w, ACCESS # 0001 0001 0000 0000 -> IORWF REG0x0, w, BANKED @@ -889,26 +1025,28 @@ A: "BANKED" is a=1 { } # 0001 0011 0000 0000 -> IORWF REG0x0, f, BANKED # 0001 0010 1101 1000 -> IORWF STATUS, f, ACCESS # 0001 0011 1101 1000 -> IORWF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG | WREG; destREG = tmp; setResultFlags(tmp); } -:MOVF srcREG, D, A is op6=0x14 & srcREG & destREG & D & A { +:MOVF srcREG, destREG, A is op6=0x14 & srcREG & destREG & A { # 0101 00da ffff ffff # 0101 0000 0000 0000 -> MOVF DAT_DATA_0000, w, ACCESS # 0101 0001 0000 0000 -> MOVF REG0x0, w, BANKED # 0101 0000 1101 1000 -> MOVF STATUS, w, ACCESS # 0101 0001 1101 1000 -> MOVF REG0xD8, w, BANKED + # 0101 0000 1110 1111 -> MOVF INDF0, w, ACCESS + # 0101 0000 1110 0111 -> MOVF INDF1, w, ACCESS + # 0101 0000 1101 1111 -> MOVF INDF2, w, ACCESS # 0101 0010 0000 0000 -> MOVF DAT_DATA_0000, f, ACCESS # 0101 0011 0000 0000 -> MOVF REG0x0, f, BANKED # 0101 0010 1101 1000 -> MOVF STATUS, f, ACCESS # 0101 0011 1101 1000 -> MOVF REG0xD8, f, BANKED - - # 0101 0000 1110 1111 -> MOVF INDF0, w, ACCESS - # 0101 0000 1110 0111 -> MOVF INDF1, w, ACCESS - # 0101 0000 1101 1111 -> MOVF INDF2, w, ACCESS - + build destREG; + build srcREG; tmp:1 = srcREG; destREG = tmp; setResultFlags(tmp); @@ -967,7 +1105,7 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:RLCF srcREG, D, A is op6=0x0d & srcREG & destREG & D & A { +:RLCF srcREG, destREG, A is op6=0x0d & srcREG & destREG & A { # 0011 01da ffff ffff # 0011 0100 0000 0000 -> RLCF DAT_DATA_0000, w, ACCESS # 0011 0101 0000 0000 -> RLCF REG0x0, w, BANKED @@ -977,6 +1115,8 @@ A: "BANKED" is a=1 { } # 0011 0111 0000 0000 -> RLCF REG0x0, f, BANKED # 0011 0110 1101 1000 -> RLCF STATUS, f, ACCESS # 0011 0111 1101 1000 -> RLCF REG0xD8, f, BANKED + build destREG; + build srcREG; local tmpC = C & 1; tmp:1 = srcREG; C = (tmp s< 0); @@ -985,7 +1125,7 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:RLNCF srcREG, D, A is op6=0x11 & srcREG & destREG & D & A { +:RLNCF srcREG, destREG, A is op6=0x11 & srcREG & destREG & A { # 0100 01da ffff ffff # 0100 0100 0000 0000 -> RLNCF DAT_DATA_0000, w, ACCESS # 0100 0101 0000 0000 -> RLNCF REG0x0, w, BANKED @@ -995,12 +1135,14 @@ A: "BANKED" is a=1 { } # 0100 0111 0000 0000 -> RLNCF REG0x0, f, BANKED # 0100 0110 1101 1000 -> RLNCF STATUS, f, ACCESS # 0100 0111 1101 1000 -> RLNCF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG << 1; destREG = tmp; setResultFlags(tmp); } -:RRCF srcREG, D, A is op6=0x0c & srcREG & destREG & D & A { +:RRCF srcREG, destREG, A is op6=0x0c & srcREG & destREG & A { # 0011 00da ffff ffff # 0011 0000 0000 0000 -> RRCF DAT_DATA_0000, w, ACCESS # 0011 0001 0000 0000 -> RRCF REG0x0, w, BANKED @@ -1010,6 +1152,8 @@ A: "BANKED" is a=1 { } # 0011 0011 0000 0000 -> RRCF REG0x0, f, BANKED # 0011 0010 1101 1000 -> RRCF STATUS, f, ACCESS # 0011 0011 1101 1000 -> RRCF REG0xD8, f, BANKED + build destREG; + build srcREG; local tmpC = C << 7; tmp:1 = srcREG; C = (tmp & 1); @@ -1018,16 +1162,14 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:RRNCF srcREG, D, A is op6=0x10 & srcREG & destREG & D & A { +:RRNCF srcREG, destREG, A is op6=0x10 & srcREG & destREG & A { # 0100 00da ffff ffff # 0100 0000 0000 0000 -> RRNCF DAT_DATA_0000, w, ACCESS # 0100 0001 0000 0000 -> RRNCF REG0x0, w, BANKED # 0100 0000 1101 1000 -> RRNCF STATUS, w, ACCESS # 0100 0001 1101 1000 -> RRNCF REG0xD8, w, BANKED - # 0100 0010 0000 0000 -> RRNCF DAT_DATA_0000, f, ACCESS - # 0100 0011 0000 0000 -> RRNCF REG0x0, f, BANKED - # 0100 0010 1101 1000 -> RRNCF STATUS, f, ACCESS - # 0100 0011 1101 1000 -> RRNCF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG >> 1; destREG = tmp; setResultFlags(tmp); @@ -1042,7 +1184,7 @@ A: "BANKED" is a=1 { } srcREG = 0xff; } -:SUBFWB srcREG, D, A is op6=0x15 & srcREG & destREG & D & A { +:SUBFWB srcREG, destREG, A is op6=0x15 & srcREG & destREG & A { # 0101 01da ffff ffff # 0101 0100 0000 0000 -> SUBFWB DAT_DATA_0000, w, ACCESS # 0101 0101 0000 0000 -> SUBFWB REG0x0, w, BANKED @@ -1052,6 +1194,8 @@ A: "BANKED" is a=1 { } # 0101 0111 0000 0000 -> SUBFWB REG0x0, f, BANKED # 0101 0110 1101 1000 -> SUBFWB STATUS, f, ACCESS # 0101 0111 1101 1000 -> SUBFWB REG0xD8, f, BANKED + build destREG; + build srcREG; local notC = ~(C & 1); tmp:1 = srcREG; setSubtractCFlags(WREG, tmp); @@ -1060,7 +1204,7 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:SUBWF srcREG, D, A is op6=0x17 & srcREG & destREG & D & A { +:SUBWF srcREG, destREG, A is op6=0x17 & srcREG & destREG & A { # 0101 11da ffff ffff # 0101 1100 0000 0000 -> SUBWF DAT_DATA_0000, w, ACCESS # 0101 1101 0000 0000 -> SUBWF REG0x0, w, BANKED @@ -1070,6 +1214,8 @@ A: "BANKED" is a=1 { } # 0101 1111 0000 0000 -> SUBWF REG0x0, f, BANKED # 0101 1110 1101 1000 -> SUBWF STATUS, f, ACCESS # 0101 1111 1101 1000 -> SUBWF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG; setSubtractFlags(tmp, WREG); tmp = tmp - WREG; @@ -1077,7 +1223,7 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:SUBWFB srcREG, D, A is op6=0x16 & srcREG & destREG & D & A { +:SUBWFB srcREG, destREG, A is op6=0x16 & srcREG & destREG & A { # 0101 10da ffff ffff # 0101 1000 0000 0000 -> SUBWFB DAT_DATA_0000, w, ACCESS # 0101 1001 0000 0000 -> SUBWFB REG0x0, w, BANKED @@ -1087,6 +1233,8 @@ A: "BANKED" is a=1 { } # 0101 1011 0000 0000 -> SUBWFB REG0x0, f, BANKED # 0101 1010 1101 1000 -> SUBWFB STATUS, f, ACCESS # 0101 1011 1101 1000 -> SUBWFB REG0xD8, f, BANKED + build destREG; + build srcREG; local notC = ~(C & 1); tmp:1 = srcREG; setSubtractCFlags(tmp, WREG); @@ -1095,7 +1243,7 @@ A: "BANKED" is a=1 { } setResultFlags(tmp); } -:SWAPF srcREG, D, A is op6=0x0e & srcREG & destREG & D & A { +:SWAPF srcREG, destREG, A is op6=0x0e & srcREG & destREG & A { # 0011 10da ffff ffff # 0011 1000 0000 0000 -> SWAPF DAT_DATA_0000, w, ACCESS # 0011 1001 0000 0000 -> SWAPF REG0x0, w, BANKED @@ -1105,8 +1253,10 @@ A: "BANKED" is a=1 { } # 0011 1011 0000 0000 -> SWAPF REG0x0, f, BANKED # 0011 1010 1101 1000 -> SWAPF STATUS, f, ACCESS # 0011 1011 1101 1000 -> SWAPF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = srcREG; - destREG = (tmp << 4) | (tmp >> 4); + destREG = (tmp << 4) | (tmp >> 4); } :TSTFSZ srcREG, A is op6=0x19 & d=0x1 & srcREG & A & skipInst { @@ -1118,7 +1268,7 @@ A: "BANKED" is a=1 { } if (srcREG == 0) goto skipInst; } -:XORWF srcREG, D, A is op6=0x06 & srcREG & destREG & D & A { +:XORWF srcREG, destREG, A is op6=0x06 & srcREG & destREG & A { # 0001 10da ffff ffff # 0001 1000 0000 0000 -> XORWF DAT_DATA_0000, w, ACCESS # 0001 1001 0000 0000 -> XORWF REG0x0, w, BANKED @@ -1128,6 +1278,8 @@ A: "BANKED" is a=1 { } # 0001 1011 0000 0000 -> XORWF REG0x0, f, BANKED # 0001 1010 1101 1000 -> XORWF STATUS, f, ACCESS # 0001 1011 1101 1000 -> XORWF REG0xD8, f, BANKED + build destREG; + build srcREG; tmp:1 = WREG ^ srcREG; destREG = tmp; setResultFlags(tmp); diff --git a/pypcode/processors/PowerPC/data/languages/altivec.sinc b/pypcode/processors/PowerPC/data/languages/altivec.sinc index 720a3df0..2acecf52 100644 --- a/pypcode/processors/PowerPC/data/languages/altivec.sinc +++ b/pypcode/processors/PowerPC/data/languages/altivec.sinc @@ -381,11 +381,10 @@ vaddubm_part2: is vrA_8_8 & vrA_8_9 & vrA_8_10 & vrA_8_11 & vrA_8_12 & vrA_8_13 vrD_32_3 = vrA_32_3 + vrB_32_3; } -# Collides with vadduws -# :vadduws vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=640 -# { # TODO definition -# vrD = vectorAddUnsignedWordSaturate(vrA,vrB); -# } +:vadduws vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=640 +{ # TODO definition + vrD = vectorAddUnsignedWordSaturate(vrA,vrB); +} :vand vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1028 { # TODO definition diff --git a/pypcode/processors/PowerPC/data/languages/ppc.ldefs.orig b/pypcode/processors/PowerPC/data/languages/ppc.ldefs.orig deleted file mode 100644 index f38a21c0..00000000 --- a/pypcode/processors/PowerPC/data/languages/ppc.ldefs.orig +++ /dev/null @@ -1,391 +0,0 @@ - - - - - PowerPC 32-bit big endian w/Altivec, G2 - - - - - - - - - - PowerPC 32-bit little endian w/Altivec, G2 - - - - - - - - PowerPC 64-bit big endian w/Altivec, G2 - - - - - - - - - - PowerPC 64-bit big endian w/Altivec and 32 bit addressing, G2 - - - - - - - - - - PowerPC 64-bit little endian w/Altivec and 32 bit addressing, G2 - - - - - - - - - PowerPC 64-bit little endian w/Altivec, G2 - - - - - - - - - PowerPC 4xx 32-bit big endian embedded core - - - - - - - - - PowerPC 4xx 32-bit little endian embedded core - - - - - - - - Freescale MPC8280 32-bit big endian family (PowerQUICC-III) - - - - - - - - - PowerQUICC-III 32-bit big endian family - - - - - - - - - PowerQUICC-III 32-bit little endian family - - - - - - - - PowerQUICC-III e500 32-bit big-endian family - - - - - - - - - - PowerQUICC-III e500 32-bit little-endian family - - - - - - - - PowerQUICC-III e500mc 32-bit big-endian family - - - - - - - - - PowerQUICC-III e500mc 32-bit little-endian family - - - - - - - Power ISA 3.0 Big Endian w/EVX and 32-bit Addressing - - - - - - - - - - Power ISA 3.0 Little Endian w/EVX and 32-bit Addressing - - - - - - - - - Power ISA 3.0 Big Endian w/Altivec and 32-bit Addressing - - - - - - - - - - Power ISA 3.0 Little Endian w/Altivec and 32-bit Addressing - - - - - - - - - Power ISA 3.0 Big Endian w/Altivec - - - - - - - - - Power ISA 3.0 Little Endian w/Altivec - - - - - - - - - Power ISA 3.0 Big Endian w/VLE, EVX and 32-bit Addressing - - - - - - - Power ISA 3.0 Big Endian w/VLE, Altivec and 32-bit Addressing - - - - - - diff --git a/pypcode/processors/PowerPC/data/languages/ppc_32.pspec b/pypcode/processors/PowerPC/data/languages/ppc_32.pspec index 260c1622..1dabc260 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_32.pspec +++ b/pypcode/processors/PowerPC/data/languages/ppc_32.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/PowerPC/data/languages/ppc_32_be.cspec b/pypcode/processors/PowerPC/data/languages/ppc_32_be.cspec deleted file mode 100644 index c855a0b5..00000000 --- a/pypcode/processors/PowerPC/data/languages/ppc_32_be.cspec +++ /dev/null @@ -1,127 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/pypcode/processors/PowerPC/data/languages/ppc_32_mpc8270.pspec b/pypcode/processors/PowerPC/data/languages/ppc_32_mpc8270.pspec index 6f223ab6..ade46bdd 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_32_mpc8270.pspec +++ b/pypcode/processors/PowerPC/data/languages/ppc_32_mpc8270.pspec @@ -5,6 +5,7 @@ + diff --git a/pypcode/processors/PowerPC/data/languages/ppc_64.pspec b/pypcode/processors/PowerPC/data/languages/ppc_64.pspec index d61b9f0b..5ddb3cdc 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_64.pspec +++ b/pypcode/processors/PowerPC/data/languages/ppc_64.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/PowerPC/data/languages/ppc_common.sinc b/pypcode/processors/PowerPC/data/languages/ppc_common.sinc index 828f4c26..e7f95807 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_common.sinc +++ b/pypcode/processors/PowerPC/data/languages/ppc_common.sinc @@ -1988,6 +1988,7 @@ dUI16PlusRAOrZeroAddress: val^"("^RA_OR_ZERO^")" is RA_OR_ZERO & UI_16_s8 [ val @ifdef BIT_64 dsPlusRaAddress: simm_ds(A) is SIMM_DS & A [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + A;export tmp;} dsPlusRaOrZeroAddress: simm_ds(RA_OR_ZERO) is SIMM_DS & RA_OR_ZERO [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + RA_OR_ZERO;export tmp;} +dqPlusRaOrZeroAddress: simm_ds(RA_OR_ZERO) is DQs & RA_OR_ZERO [simm_ds = DQs << 4;] {tmp:8 = simm_ds + RA_OR_ZERO;export tmp;} @endif diff --git a/pypcode/processors/PowerPC/data/languages/ppc_isa.sinc b/pypcode/processors/PowerPC/data/languages/ppc_isa.sinc index ce9a52cc..bfce7736 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_isa.sinc +++ b/pypcode/processors/PowerPC/data/languages/ppc_isa.sinc @@ -1609,8 +1609,8 @@ define pcodeop stdcixOp; # ISA-info: lq - Form "DQ" Page 751 Category "LSQ" # binutils: power4.d: +0: e0 83 00 00 lq r4,0\(r3\) # binutils: power4.d: +4: e0 83 00 00 lq r4,0\(r3\) -:lq RT,A,DQ is $(NOTVLE) & OP=56 & RT & Dp & A & DQ & BITS_0_3=0 & regp [regpset = Dp+1;] { - ea:$(REGISTER_SIZE) = A + sext(DQ:2 << 4); +:lq RT,dqPlusRaOrZeroAddress is $(NOTVLE) & OP=56 & RT & Dp & dqPlusRaOrZeroAddress & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = dqPlusRaOrZeroAddress; @if ENDIAN == "big" RT = *:$(REGISTER_SIZE) ea; regp = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)); @@ -1925,8 +1925,8 @@ define pcodeop stfdpOp; # binutils: power4.d: +58: f8 c7 ff f2 stq r6,-16\(r7\) # binutils: power4.d: +5c: f8 c7 80 02 stq r6,-32768\(r7\) # binutils: power4.d: +60: f8 c7 7f f2 stq r6,32752\(r7\) -:stq RS,RA_OR_ZERO,DS is $(NOTVLE) & OP=62 & RS & Dp & RA_OR_ZERO & DS & BITS_0_1=2 & regp [regpset = Dp+1;] { - ea:$(REGISTER_SIZE) = RA_OR_ZERO + sext(DS:2 << 2); +:stq RS,dsPlusRaOrZeroAddress is $(NOTVLE) & OP=62 & RS & Dp & dsPlusRaOrZeroAddress & BITS_0_1=2 & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = dsPlusRaOrZeroAddress; @if ENDIAN == "big" *:$(REGISTER_SIZE) ea = RS; *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = regp; diff --git a/pypcode/processors/RISCV/scripts/binutil.py b/pypcode/processors/RISCV/scripts/binutil.py index 8c1ec235..d54e0965 100644 --- a/pypcode/processors/RISCV/scripts/binutil.py +++ b/pypcode/processors/RISCV/scripts/binutil.py @@ -22,6 +22,8 @@ Data was copied from various files in binutils, a lot of it unused. """ +import sys +import re MATCH_SLLI_RV32=0x1013 MASK_SLLI_RV32=0xfe00707f @@ -2777,7 +2779,7 @@ def find_gaps(op): pattern = 0x0 for x in op.bitpattern: x = x.split('=')[0] - if x not in gap.keys(): + if not x in gap.keys(): print("GAP: %r" % x) exit(1) x = gap[x] diff --git a/pypcode/processors/Xtensa/data/languages/flix.sinc b/pypcode/processors/Xtensa/data/languages/flix.sinc index f012f839..c03e07bc 100644 --- a/pypcode/processors/Xtensa/data/languages/flix.sinc +++ b/pypcode/processors/Xtensa/data/languages/flix.sinc @@ -4,6 +4,7 @@ # 16 bytes. Customizable, if found they should be flagged. define pcodeop flix; -:FLIX u_4_23 is op0=0xe & u_4_23 { +# Care probably needs to be taken here with BE support if any FLIX instructions are ever defined +:FLIX flix_i20 is op0=0xe & flix_i20 { flix(); } \ No newline at end of file diff --git a/pypcode/processors/Xtensa/data/languages/xtensa.pspec b/pypcode/processors/Xtensa/data/languages/xtensa.pspec index 721b2e43..089d24b5 100644 --- a/pypcode/processors/Xtensa/data/languages/xtensa.pspec +++ b/pypcode/processors/Xtensa/data/languages/xtensa.pspec @@ -5,6 +5,7 @@ + diff --git a/pypcode/processors/Xtensa/data/languages/xtensaArch.sinc b/pypcode/processors/Xtensa/data/languages/xtensaArch.sinc index a8d8d82c..fa03ef39 100644 --- a/pypcode/processors/Xtensa/data/languages/xtensaArch.sinc +++ b/pypcode/processors/Xtensa/data/languages/xtensaArch.sinc @@ -108,6 +108,8 @@ define token insn(24) ar = (8,11) fr = (8,11) br = (8,11) + mw = (8,9) + mx = (10,10) as = (12,15) fs = (12,15) bs = (12,15) @@ -115,45 +117,42 @@ define token insn(24) at = (16,19) ft = (16,19) bt = (16,19) + my = (18,18) op0 = (20,23) - # Signed and unsigned immediates. Named [us]N_L.M, where u and s denote signedness, L and M the - # least and most significant bit of the immediate in the instruction word, and N the length - # (i.e. M-L+1). - u3_21_23 = (1,3) - u4_20_23 = (0,3) - s8_16_23 = (0,7) signed - u8_16_23 = (0,7) - u12_12_23 = (0,11) - s12_12_23 = (0,11) signed - u16_8_23 = (0,15) - s8_6_23 = (0,17) signed - u1_20 = (0,0) - u2_18_19 = (4,5) - u3_17_19 = (5,7) - u2_16_17 = (6,7) - u1_16 = (4,4) - u1_15_15 = (11,11) - u2_14_15 = (10,11) - u3_13_15 = (9,11) - u4_12_15 = (8,11) - m0m1_14_14 = (10,10) - u2_12_13 = (8,9) - mw_12_13 = (8,9) - u1_12 = (8,8) - u4_8_11 = (12,15) - u8_4_11 = (12,19) - s4_8_11 = (12,15) signed - u1_7_7 = (19,19) - u2_6_7 = (16,17) - u3_5_7 = (17,19) - u4_4_7 = (16,19) - s4_4_7 = (16,19) - m2m3_6_6 = (18,18) - u_4_23 = (0,19) - t2_4_5 = (16,17) - u2_4_5 = (18,19) - u1_4 = (16,16) + op2_1_3 = (1,3) + op2_0 = (0,0) + ri8_i8 = (0,7) + ri8_si8 = (0,7) signed + bri12_i12 = (0,11) + bri12_si12 = (0,11) signed + ri16_i16 = (0,15) + call_o18 = (0,17) signed + op1_1_3 = (5,7) + op1_0 = (4,4) + op_r_3 = (11,11) + op_r_2_2 = (10,11) + op_r_1_3 = (9,11) + op_r_0_2 = (8,9) + op_r_0 = (8,8) + op_r = (8,11) + op_s = (12,15) + op_st = (12,19) + op_st_i8 = (12,15) signed + op_t_3 = (19,19) + op_t_1_3 = (17,19) + op_t_0_2 = (16,17) + op_t = (16,19) + op_t_0 = (16,16) + op_t_si4 = (16,19) signed + + # If flix instructions are defined for a BE processor + # this will possibly need to be split for the operands + flix_i20 = (0,19) + + # Care needs to be taken with these for BE + bri8_n = (18,19) + bri8_m = (16,17) ; # little-endian -> big-endian 16-bit conversion chart @@ -167,14 +166,14 @@ define token narrowinsn(16) n_at = (8,11) n_op0 = (12,15) - n_u4_12_15 = (0,3) - n_s4_12_15 = (0,3) signed - n_u4_8_11 = (4,7) - n_u1_7 = (11,11) - n_u2_6_7 = (10,11) - n_u4_4_7 = (8,11) - n_s3_4_6 = (8,10) - n_u2_4_5 = (8,9) + ri6_i6_0_4 = (0,3) + ri6_si6_0_4 = (0,3) signed + n_op_t = (4,7) + n_op_s_3 = (11,11) + n_op_s_2_2 = (10,11) + n_op_s = (8,11) + n_op_s_0_3 = (8,10) + ri6_i6_4_2 = (8,9) ; @else @@ -182,9 +181,12 @@ define token narrowinsn(16) define token insn(24) # Named opcode/register fields. op2 = (20,23) + op1 = (16,19) ar = (12,15) fr = (12,15) br = (12,15) + mw = (12,13) + mx = (14,14) as = (8,11) fs = (8,11) bs = (8,11) @@ -192,46 +194,40 @@ define token insn(24) at = (4,7) ft = (4,7) bt = (4,7) - op1 = (16,19) + my = (6,6) op0 = (0,3) # Signed and unsigned immediates. Named [us]N_L_M, where u and s denote signedness, L and M the # least and most significant bit of the immediate in the instruction word, and N the length # (i.e. M-L+1). - u3_21_23 = (21,23) - u4_20_23 = (20,23) - s8_16_23 = (16,23) signed - u8_16_23 = (16,23) - u12_12_23 = (12,23) - s12_12_23 = (12,23) signed - u16_8_23 = (8,23) - s8_6_23 = (6,23) signed - u1_20 = (20,20) - u2_18_19 = (18,19) - u3_17_19 = (17,19) - u2_16_17 = (16,17) - u1_16 = (16,16) - u1_15_15 = (15,15) - u2_14_15 = (14,15) - u3_13_15 = (13,15) - u4_12_15 = (12,15) - m0m1_14_14 = (14,14) - u2_12_13 = (12,13) - mw_12_13 = (12,13) - u1_12 = (12,12) - u4_8_11 = (8,11) - u8_4_11 = (4,11) - s4_8_11 = (8,11) signed - u1_7_7 = (7,7) - u2_6_7 = (6,7) - u3_5_7 = (5,7) - u4_4_7 = (4,7) - s4_4_7 = (4,7) - m2m3_6_6 = (6,6) - u_4_23 = (4,23) - t2_4_5 = (4,5) - u2_4_5 = (4,5) - u1_4 = (4,4) + op2_1_3 = (21,23) + op2_0 = (20,20) + ri8_i8 = (16,23) + ri8_si8 = (16,23) signed + bri12_i12 = (12,23) + bri12_si12 = (12,23) signed + ri16_i16 = (8,23) + call_o18 = (6,23) signed + op1_1_3 = (17,19) + op1_0 = (16,16) + op_r_3 = (15,15) + op_r_2_2 = (14,15) + op_r_1_3 = (13,15) + op_r_0_2 = (12,13) + op_r_0 = (12,12) + op_r = (12,15) + op_s = (8,11) + op_st = (4,11) + op_st_i8 = (8,11) signed + op_t_3 = (7,7) + op_t_1_3 = (5,7) + op_t_0_2 = (4,5) + op_t_0 = (4,4) + op_t = (4,7) + op_t_si4 = (4,7) signed + flix_i20 = (4,23) + bri8_n = (4,5) + bri8_m = (6,7) ; # Narrow 16-bit instructions; fields are always prefixed with n_. @@ -241,14 +237,14 @@ define token narrowinsn(16) n_at = (4,7) n_op0 = (0, 3) - n_u4_12_15 = (12,15) - n_s4_12_15 = (12,15) signed - n_u4_8_11 = (8,11) - n_u1_7 = (7,7) - n_u2_6_7 = (6,7) - n_u4_4_7 = (4,7) - n_s3_4_6 = (4,6) - n_u2_4_5 = (4,5) + ri6_i6_0_4 = (12,15) + ri6_si6_0_4 = (12,15) signed + n_op_t = (8,11) + n_op_s_3 = (7,7) + n_op_s_2_2 = (6,7) + n_op_s = (4,7) + n_op_s_0_3 = (4,6) + ri6_i6_4_2 = (4,5) ; @endif diff --git a/pypcode/processors/Xtensa/data/languages/xtensaInstructions.sinc b/pypcode/processors/Xtensa/data/languages/xtensaInstructions.sinc index f7e2d391..f06e6193 100644 --- a/pypcode/processors/Xtensa/data/languages/xtensaInstructions.sinc +++ b/pypcode/processors/Xtensa/data/languages/xtensaInstructions.sinc @@ -29,8 +29,8 @@ } # ADDI - Add Immediate (RRI8), pg. 251. -:addi at, as, s8_16_23 is s8_16_23 & ar = 0b1100 & as & at & op0 = 0b0010 { - at = as + s8_16_23; +:addi at, as, ri8_si8 is ri8_si8 & ar = 0b1100 & as & at & op0 = 0b0010 { + at = as + ri8_si8; } # ADDI.N - Narrow Add Immediate (RRRN), pg. 252. @@ -38,27 +38,27 @@ n_ar = n_as + n_s4_4_7_nozero; } -# ADDMI - Add Immediate with Shift by 8, pg. 253. -:addmi at, as, s16_16_23_sb8 is s16_16_23_sb8 & ar = 0b1101 & as & at & op0 = 0b0010 { - at = as + s16_16_23_sb8; +# ADDMI - Add Immediate with Shift by 8 (RRI8), pg. 253. +:addmi at, as, ri8_si8_sh8 is ri8_si8_sh8 & ar = 0b1101 & as & at & op0 = 0b0010 { + at = as + ri8_si8_sh8; } -# ADDX2 - Add with Shift by 1, pg. 254. +# ADDX2 - Add with Shift by 1 (RRR), pg. 254. :addx2 ar, as, at is op2 = 0b1001 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 1) + at; } -# ADDX4 - Add with Shift by 2, pg. 255. +# ADDX4 - Add with Shift by 2 (RRR), pg. 255. :addx4 ar, as, at is op2 = 0b1010 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 2) + at; } -# ADDX8 - Add with Shift by 4, pg. 256. +# ADDX8 - Add with Shift by 4 (RRR), pg. 256. :addx8 ar, as, at is op2 = 0b1011 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 3) + at; } -# ALL4 - All 4 Booleans True, pg. 257. +# ALL4 - All 4 Booleans True (RRR), pg. 257. :all4 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1001 & bs & bt & op0 = 0 { local b = *[register]:1 &:4 bs+1; local c = *[register]:1 &:4 bs+2; @@ -66,7 +66,7 @@ bt = bs && b && c && d; } -# ALL8 - All 8 Booleans True, pg. 258. +# ALL8 - All 8 Booleans True (RRR), pg. 258. :all8 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1011 & bs & bt & op0 = 0 { local b = *[register]:1 &:4 bs+1; local c = *[register]:1 &:4 bs+2; @@ -78,22 +78,22 @@ bt = bs && b && c && d && e && f && g && h; } -# AND - Bitwise Logical And, pg. 259. +# AND - Bitwise Logical And (RRR), pg. 259. :and ar, as, at is op2 = 0b0001 & op1 = 0 & ar & as & at & op0 = 0 { ar = as & at; } -# ANDB - Boolean And, pg. 260. +# ANDB - Boolean And (RRR), pg. 260. :andb br, bs, bt is op2 = 0 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs && bt; } -# ANDBC - Boolean And with Complement, pg. 261. +# ANDBC - Boolean And with Complement (RRR), pg. 261. :andbc br, bs, bt is op2 = 0b0001 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs && !bt; } -# ANY4 - Any 4 Booleans True, pg. 262. +# ANY4 - Any 4 Booleans True (RRR), pg. 262. :any4 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1000 & bs & bt & op0 = 0 { local b = *[register]:1 &:4 bs+1; local c = *[register]:1 &:4 bs+2; @@ -101,7 +101,7 @@ bt = bs || b || c || d; } -# ANY8 - Any 8 Booleans True, pg. 263. +# ANY8 - Any 8 Booleans True (RRR), pg. 263. :any8 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1010 & bs & bt & op0 = 0 { local b = *[register]:1 &:4 bs+1; local c = *[register]:1 &:4 bs+2; @@ -113,16 +113,16 @@ bt = bs || b || c || d || e || f || g || h; } -# BALL - Branch if All Bits Set, pg. 264. -:ball srel_16_23, as, at is srel_16_23 & ar = 0b0100 & as & at & op0 = 0b0111 { +# BALL - Branch if All Bits Set (RRI8), pg. 264. +:ball ri8_srel, as, at is ri8_srel & ar = 0b0100 & as & at & op0 = 0b0111 { local test:4 = ~as & at; - if (test == 0) goto srel_16_23; + if (test == 0) goto ri8_srel; } -# BANY - Branch if Any Bit Set, pg. 265. -:bany srel_16_23, as, at, is srel_16_23 & ar = 0b1000 & as & at & op0 = 0b0111 { +# BANY - Branch if Any Bit Set (RRI8), pg. 265. +:bany ri8_srel, as, at, is ri8_srel & ar = 0b1000 & as & at & op0 = 0b0111 { local test:4 = as & at; - if (test != 0) goto srel_16_23; + if (test != 0) goto ri8_srel; } macro extract_bit(bit, result) { @@ -133,230 +133,230 @@ macro extract_bit(bit, result) { @endif } -# BBC - Branch if Bit Clear, pg. 266. -:bbc as, at, srel_16_23 is srel_16_23 & ar = 0b0101 & as & at & op0 = 0b0111 { +# BBC - Branch if Bit Clear (RRR), pg. 266. +:bbc as, at, ri8_srel is ri8_srel & ar = 0b0101 & as & at & op0 = 0b0111 { local bval:4 = 0; extract_bit(at[0,5], bval); bval = as & bval; if (bval == 0) - goto srel_16_23; + goto ri8_srel; } -# BBCI - Branch if Bit Clear immediate, pg. 267 -:bbci as, u5_4_7_12, srel_16_23 is srel_16_23 & u3_13_15 = 0b011 & as & u5_4_7_12 & op0 = 0b0111 { +# BBCI - Branch if Bit Clear immediate (RRI8), pg. 267 +:bbci as, u5_4_7_12, ri8_srel is ri8_srel & op_r_1_3 = 0b011 & as & u5_4_7_12 & op0 = 0b0111 { local bval; extract_bit(u5_4_7_12, bval); bval = as & bval; if (bval == 0) - goto srel_16_23; + goto ri8_srel; } -# BBS - Branch if Bit Set, pg. 269. -:bbs as, at, srel_16_23 is srel_16_23 & ar = 0b1101 & as & at & op0 = 0b0111 { +# BBS - Branch if Bit Set (RRI8), pg. 269. +:bbs as, at, ri8_srel is ri8_srel & ar = 0b1101 & as & at & op0 = 0b0111 { local bval; extract_bit(at[0,5], bval); bval = as & bval; if (bval != 0) - goto srel_16_23; + goto ri8_srel; } -# BBSI - Branch if Bit Set immediate, pg. 270. -:bbsi as, u5_4_7_12, srel_16_23 is srel_16_23 & u3_13_15 = 0b111 & as & u5_4_7_12 & op0 = 0b0111 { +# BBSI - Branch if Bit Set immediate (RRI8), pg. 270. +:bbsi as, u5_4_7_12, ri8_srel is ri8_srel & op_r_1_3 = 0b111 & as & u5_4_7_12 & op0 = 0b0111 { local bval; extract_bit(u5_4_7_12, bval); bval = as & bval; if (bval != 0) - goto srel_16_23; + goto ri8_srel; } -# BEQ - Branch if Equal, pg. 272. -:beq as, at, srel_16_23 is srel_16_23 & ar = 0b0001 & as & at & op0 = 0b0111 { +# BEQ - Branch if Equal (RRI8), pg. 272. +:beq as, at, ri8_srel is ri8_srel & ar = 0b0001 & as & at & op0 = 0b0111 { if (as == at) - goto srel_16_23; + goto ri8_srel; } -# BEQI - Branch if Equal Immediate, pg. 273. -:beqi as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0 & u2_4_5 = 0b10 & op0 = 0b0110 { +# BEQI - Branch if Equal Immediate (BRI8), pg. 273. +:beqi as, r_b4const, ri8_srel is ri8_srel & r_b4const & as & bri8_m = 0 & bri8_n = 0b10 & op0 = 0b0110 { if (as == r_b4const) - goto srel_16_23; + goto ri8_srel; } -# BEQZ - Branch if Equal Zero, pg. 274. -:beqz as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0 & u2_4_5 = 0b01 & op0 = 0b0110 { +# BEQZ - Branch if Equal Zero (BRI12), pg. 274. +:beqz as, bri12_srel is bri12_srel & as & bri8_m = 0 & bri8_n = 0b01 & op0 = 0b0110 { if (as == 0) - goto srel_12_23; + goto bri12_srel; } -# BEQZ.N - Narrow Branch if Equal Zero, pg. 275. -:beqz.n n_as, urel_12_15_4_5 is urel_12_15_4_5 & n_as & n_u2_6_7 = 0b10 & n_op0 = 0b1100 { +# BEQZ.N - Narrow Branch if Equal Zero (RI6), pg. 275. +:beqz.n n_as, ri6_rel is ri6_rel & n_as & n_op_s_2_2 = 0b10 & n_op0 = 0b1100 { if (n_as == 0) - goto urel_12_15_4_5; + goto ri6_rel; } -# BF - Branch if False, pg. 276. -:bf bs, srel_16_23 is srel_16_23 & ar = 0 & bs & at = 0b0111 & op0 = 0b0110 { +# BF - Branch if False (RRI8), pg. 276. +:bf bs, ri8_srel is ri8_srel & ar = 0 & bs & at = 0b0111 & op0 = 0b0110 { if (!bs) - goto srel_16_23; + goto ri8_srel; } -# BGE - Branch if Greater Than or Equal, pg. 277. -:bge as, at, srel_16_23 is srel_16_23 & ar = 0b1010 & as & at & op0 = 0b0111 { +# BGE - Branch if Greater Than or Equal (RRI8), pg. 277. +:bge as, at, ri8_srel is ri8_srel & ar = 0b1010 & as & at & op0 = 0b0111 { if (as s>= at) - goto srel_16_23; + goto ri8_srel; } -# BGEI - Branch if Greater Than or Equal Immediate, pg. 278. -:bgei as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0b11 & u2_4_5 = 0b10 & op0 = 0b0110 { +# BGEI - Branch if Greater Than or Equal Immediate (BRI8), pg. 278. +:bgei as, r_b4const, ri8_srel is ri8_srel & r_b4const & as & bri8_m = 0b11 & bri8_n = 0b10 & op0 = 0b0110 { if (as s>= r_b4const) - goto srel_16_23; + goto ri8_srel; } -# BGEU - Branch if Greater Than or Equal Unsigned, pg. 279. -:bgeu as, at, srel_16_23 is srel_16_23 & ar = 0b1011 & as & at & op0 = 0b0111 { +# BGEU - Branch if Greater Than or Equal Unsigned (RRI8), pg. 279. +:bgeu as, at, ri8_srel is ri8_srel & ar = 0b1011 & as & at & op0 = 0b0111 { if (as >= at) - goto srel_16_23; + goto ri8_srel; } -# BGEUI - Branch if Greater Than or Equal Unsigned Immediate, pg. 280. -:bgeui as, r_b4constu, srel_16_23 is srel_16_23 & r_b4constu & as & u2_6_7 = 0b11 & u2_4_5 = 0b11 & op0 = 0b0110 { +# BGEUI - Branch if Greater Than or Equal Unsigned Immediate (BRI8), pg. 280. +:bgeui as, r_b4constu, ri8_srel is ri8_srel & r_b4constu & as & bri8_m = 0b11 & bri8_n = 0b11 & op0 = 0b0110 { if (as >= r_b4constu) - goto srel_16_23; + goto ri8_srel; } -# BGEZ - Branch if Greater Than or Equal Zero, pg. 281. -:bgez as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0b11 & u2_4_5 = 0b01 & op0 = 0b0110 { +# BGEZ - Branch if Greater Than or Equal Zero (BRI12), pg. 281. +:bgez as, bri12_srel is bri12_srel & as & bri8_m = 0b11 & bri8_n = 0b01 & op0 = 0b0110 { if (as s>= 0) - goto srel_12_23; + goto bri12_srel; } -# BLT - Branch if Less Than, pg. 282. -:blt as, at, srel_16_23 is srel_16_23 & ar = 0b0010 & as & at & op0 = 0b0111 { +# BLT - Branch if Less Than (RRI8), pg. 282. +:blt as, at, ri8_srel is ri8_srel & ar = 0b0010 & as & at & op0 = 0b0111 { if (as s< at) - goto srel_16_23; + goto ri8_srel; } -# BLTI - Branch if Less Than Immediate, pg. 283. -:blti as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0b10 & u2_4_5 = 0b10 & op0 = 0b0110 { +# BLTI - Branch if Less Than Immediate (BRI8), pg. 283. +:blti as, r_b4const, ri8_srel is ri8_srel & r_b4const & as & bri8_m = 0b10 & bri8_n = 0b10 & op0 = 0b0110 { if (as s< r_b4const) - goto srel_16_23; + goto ri8_srel; } -# BLTU - Branch if Less Than Unsigned, pg. 284. -:bltu as, at, srel_16_23 is srel_16_23 & ar = 0b0011 & as & at & op0 = 0b0111 { +# BLTU - Branch if Less Than Unsigned (RRI8), pg. 284. +:bltu as, at, ri8_srel is ri8_srel & ar = 0b0011 & as & at & op0 = 0b0111 { if (as < at) - goto srel_16_23; + goto ri8_srel; } -# BLTUI - Branch if Less Than Unsigned Immediate, pg. 285. -:bltui as, r_b4constu, srel_16_23 is srel_16_23 & r_b4constu & as & u2_6_7 = 0b10 & u2_4_5 = 0b11 & op0 = 0b0110 { +# BLTUI - Branch if Less Than Unsigned Immediate (BRI8), pg. 285. +:bltui as, r_b4constu, ri8_srel is ri8_srel & r_b4constu & as & bri8_m = 0b10 & bri8_n = 0b11 & op0 = 0b0110 { if (as < r_b4constu) - goto srel_16_23; + goto ri8_srel; } -# BLTZ - Branch if Less Than Zero, pg. 286. -:bltz as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0b10 & u2_4_5 = 0b01 & op0 = 0b0110 { +# BLTZ - Branch if Less Than Zero (BRI12), pg. 286. +:bltz as, bri12_srel is bri12_srel & as & bri8_m = 0b10 & bri8_n = 0b01 & op0 = 0b0110 { if (as s< 0) - goto srel_12_23; + goto bri12_srel; } -# BNALL - Branch if Not-All Bits Set, pg. 287. -:bnall srel_16_23, as, at is srel_16_23 & ar = 0b1100 & as & at & op0 = 0b0111 { +# BNALL - Branch if Not-All Bits Set (RRI8), pg. 287. +:bnall ri8_srel, as, at is ri8_srel & ar = 0b1100 & as & at & op0 = 0b0111 { if ((~as & at) != 0) - goto srel_16_23; + goto ri8_srel; } -# BNE - Branch if Not Equal, pg. 288. -:bne as, at, srel_16_23 is srel_16_23 & ar = 0b1001 & as & at & op0 = 0b0111 { +# BNE - Branch if Not Equal (RRI8), pg. 288. +:bne as, at, ri8_srel is ri8_srel & ar = 0b1001 & as & at & op0 = 0b0111 { if (as != at) - goto srel_16_23; + goto ri8_srel; } -# BNEI - Branch if Not EquaL Immediate, pg. 289. -:bnei as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0b01 & u2_4_5 = 0b10 & op0 = 0b0110 { +# BNEI - Branch if Not EquaL Immediate (BRI8), pg. 289. +:bnei as, r_b4const, ri8_srel is ri8_srel & r_b4const & as & bri8_m = 0b01 & bri8_n = 0b10 & op0 = 0b0110 { if (as != r_b4const) - goto srel_16_23; + goto ri8_srel; } -# BNEZ - Branch if Not Equal Zero, pg. 290. -:bnez as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0b01 & u2_4_5 = 0b01 & op0 = 0b0110 { +# BNEZ - Branch if Not Equal Zero (BRI12), pg. 290. +:bnez as, bri12_srel is bri12_srel & as & bri8_m = 0b01 & bri8_n = 0b01 & op0 = 0b0110 { if (as != 0) - goto srel_12_23; + goto bri12_srel; } -# BNEZ.N - Narrow Branch if Not Equal Zero, pg. 291. -:bnez.n n_as, urel_12_15_4_5 is urel_12_15_4_5 & n_as & n_u2_6_7 = 0b11 & n_op0 = 0b1100 { +# BNEZ.N - Narrow Branch if Not Equal Zero (RI6), pg. 291. +:bnez.n n_as, ri6_rel is ri6_rel & n_as & n_op_s_2_2 = 0b11 & n_op0 = 0b1100 { if (n_as != 0) - goto urel_12_15_4_5; + goto ri6_rel; } -# BNONE - Branch if No Bit Set, pg. 292. -:bnone srel_16_23, as, at, is srel_16_23 & ar = 0 & as & at & op0 = 0b0111 { +# BNONE - Branch if No Bit Set (RRI8), pg. 292. +:bnone ri8_srel, as, at, is ri8_srel & ar = 0 & as & at & op0 = 0b0111 { if ((as & at) == 0) - goto srel_16_23; + goto ri8_srel; } -# BREAK - Breakpoint, pg. 293. -:break u4_8_11, u4_4_7 is op2 = 0 & op1 = 0 & ar = 0b0100 & u4_8_11 & u4_4_7 & op0 = 0 { +# BREAK - Breakpoint (RRR), pg. 293. +:break op_s, op_t is op2 = 0 & op1 = 0 & ar = 0b0100 & op_s & op_t & op0 = 0 { break_inst:4 = inst_start; - breakpoint(0x001000:4, break_inst, u4_8_11:1, u4_4_7:1); + breakpoint(0x001000:4, break_inst, op_s:1, op_t:1); } -# BREAK.N - Narrow Breakpoint, pg. 295. -:break.n n_u4_8_11 is n_ar = 0b1111 & n_u4_8_11 & n_at = 0b0010 & n_op0 = 0b1101 { +# BREAK.N - Narrow Breakpoint (RRRN), pg. 295. +:break.n n_op_t is n_ar = 0b1111 & n_op_t & n_at = 0b0010 & n_op0 = 0b1101 { break_inst:4 = inst_start; - breakpoint(0x010000:4, break_inst, n_u4_8_11:1, 0:1); + breakpoint(0x010000:4, break_inst, n_op_t:1, 0:1); } -# BT - Branch if True, pg. 296. -:bt bs, srel_16_23 is srel_16_23 & ar = 0b0001 & bs & at = 0b0111 & op0 = 0b0110 { +# BT - Branch if True (RRI8), pg. 296. +:bt bs, ri8_srel is ri8_srel & ar = 0b0001 & bs & at = 0b0111 & op0 = 0b0110 { if (bs) - goto srel_16_23; + goto ri8_srel; } -# CALL0 - Non-windowed Call, pg. 297. -:call0 srel_6_23_sb2 is srel_6_23_sb2 & u2_4_5 = 0 & op0 = 0b0101 { +# CALL0 - Non-windowed Call (CALL), pg. 297. +:call0 call_srel_sh2 is call_srel_sh2 & bri8_n = 0 & op0 = 0b0101 { $(PS_CALLINC) = 0; a0 = inst_next; - call srel_6_23_sb2; + call call_srel_sh2; } -# CALL4 - Call PC-relative, Rotate Window by 4, pg. 298. -:call4 srel_6_23_sb2 is srel_6_23_sb2 & Ret4 & u2_4_5 = 0b01 & op0 = 0b0101 { +# CALL4 - Call PC-relative, Rotate Window by 4 (CALL), pg. 298. +:call4 call_srel_sh2 is call_srel_sh2 & Ret4 & bri8_n = 0b01 & op0 = 0b0101 { $(PS_CALLINC) = 1; a4 = Ret4; swap4(); - call srel_6_23_sb2; + call call_srel_sh2; restore4(); } -# CALL8 - Call PC-relative, Rotate Window by 8, pg. 300. -:call8 srel_6_23_sb2 is srel_6_23_sb2 & Ret8 & u2_4_5 = 0b10 & op0 = 0b0101 { +# CALL8 - Call PC-relative, Rotate Window by 8 (CALL), pg. 300. +:call8 call_srel_sh2 is call_srel_sh2 & Ret8 & bri8_n = 0b10 & op0 = 0b0101 { $(PS_CALLINC) = 2; a8 = Ret8; swap8(); - call srel_6_23_sb2; + call call_srel_sh2; restore8(); } -# CALL12 - Call PC-relative, Rotate Window by 12, pg. 302. -:call12 srel_6_23_sb2 is srel_6_23_sb2 & Ret12 & u2_4_5 = 0b11 & op0 = 0b0101 { +# CALL12 - Call PC-relative, Rotate Window by 12 (CALL), pg. 302. +:call12 call_srel_sh2 is call_srel_sh2 & Ret12 & bri8_n = 0b11 & op0 = 0b0101 { $(PS_CALLINC) = 3; a12 = Ret12; swap12(); - call srel_6_23_sb2; + call call_srel_sh2; restore12(); } -# CALLX0 - Non-windowed Call Register, pg. 304. -:callx0 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6_7 = 0b11 & u2_4_5 = 0 & op0 = 0 { +# CALLX0 - Non-windowed Call Register (CALLX), pg. 304. +:callx0 as is op2 = 0 & op1 = 0 & ar = 0 & as & bri8_m = 0b11 & bri8_n = 0 & op0 = 0 { $(PS_CALLINC) = 0; local dst = as; a0 = inst_next; call [dst]; } -# CALLX4 - Call Register, Rotate Window by 4, pg. 305. -:callx4 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret4 & u2_6_7 = 0b11 & u2_4_5 = 0b01 & op0 = 0 { +# CALLX4 - Call Register, Rotate Window by 4 (CALLX), pg. 305. +:callx4 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret4 & bri8_m = 0b11 & bri8_n = 0b01 & op0 = 0 { $(PS_CALLINC) = 1; dest:4 = as; a4 = Ret4; @@ -365,8 +365,8 @@ macro extract_bit(bit, result) { restore4(); } -# CALLX8 - Call Register, Rotate Window by 8, pg. 307. -:callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret8 & u2_6_7 = 0b11 & u2_4_5 = 0b10 & op0 = 0 { +# CALLX8 - Call Register, Rotate Window by 8 (CALLX), pg. 307. +:callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret8 & bri8_m = 0b11 & bri8_n = 0b10 & op0 = 0 { $(PS_CALLINC) = 2; dest:4 = as; a8 = Ret8; @@ -375,8 +375,8 @@ macro extract_bit(bit, result) { restore8(); } -# CALLX12 - Call Register, Rotate Window by 12, pg. 308. -:callx12 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret12 & u2_6_7 = 0b11 & u2_4_5 = 0b11 & op0 = 0 { +# CALLX12 - Call Register, Rotate Window by 12 (CALLX), pg. 308. +:callx12 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret12 & bri8_m = 0b11 & bri8_n = 0b11 & op0 = 0 { $(PS_CALLINC) = 3; dest:4 = as; a12 = Ret12; @@ -385,13 +385,13 @@ macro extract_bit(bit, result) { restore12(); } -# CEIL.S - Ceiling Single to Fixed, pg. 311. -:ceil.s ar, fs, u4_4_7 is op2 = 0b1011 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# CEIL.S - Ceiling Single to Fixed (RRR), pg. 311. +:ceil.s ar, fs, op_t is op2 = 0b1011 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = 1 << op_t; ar = ceil(fs f* int2float(scale)); } -# CLAMPS - Signed Clamp, pg. 312. +# CLAMPS - Signed Clamp (RRR), pg. 312. :clamps ar, as, u5_4_7_plus7 is op2 = 0b0011 & op1 = 0b0011 & ar & as & u5_4_7_plus7 & op0 = 0 { # ar min(max(as, -2^{u5_4_7_plus7}), 2^{u5_4_7_plus7}-1) local x:4 = as; @@ -402,457 +402,457 @@ macro extract_bit(bit, result) { ar = (zext(mt) * max) + (zext(!mt) * (clamp-1)); } -# DHI - Data Cache Hit Invalidate, pg. 313. -:dhi as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0110 & op0 = 0b0010 { - dhi(as + u10_16_23_sb2); +# DHI - Data Cache Hit Invalidate (RRI8), pg. 313. +:dhi as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0110 & op0 = 0b0010 { + dhi(as + ri8_i8_sh2); } -# DHU - Data Cache Hit Unlock, pg. 315. +# DHU - Data Cache Hit Unlock (RRI4), pg. 315. :dhu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0010 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { dhu(as + u8_20_23_sb4); } -# DHWB - Data Cache Hit Writeback, pg. 317. -:dhwb as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0100 & op0 = 0b0010 { - dhwb(as + u10_16_23_sb2); +# DHWB - Data Cache Hit Writeback (RRI8), pg. 317. +:dhwb as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0100 & op0 = 0b0010 { + dhwb(as + ri8_i8_sh2); } -# DHWBI - Data Cache Hit Writeback Invalidate, pg. 319. -:dhwbi as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0101 & op0 = 0b0010 { - dhwbi(as + u10_16_23_sb2); +# DHWBI - Data Cache Hit Writeback Invalidate (RRI8), pg. 319. +:dhwbi as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0101 & op0 = 0b0010 { + dhwbi(as + ri8_i8_sh2); } -# DII - Data Cache Index Invalidate, pg. 321. -:dii as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0111 & op0 = 0b0010 { - dii(as + u10_16_23_sb2); +# DII - Data Cache Index Invalidate (RRI8), pg. 321. +:dii as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0111 & op0 = 0b0010 { + dii(as + ri8_i8_sh2); } -# DIU - Data Cache Index Unlock, pg. 323. +# DIU - Data Cache Index Unlock (RRI4), pg. 323. :diu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0011 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { diu(as + u8_20_23_sb4); } -# DIWB - Data Cache Index Write Back, pg. 325. +# DIWB - Data Cache Index Write Back (RRI4), pg. 325. :diwb as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0100 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { diwb(as + u8_20_23_sb4); } -# DIWBI - Data Cache Index Write Back Invalidate, pg. 327. +# DIWBI - Data Cache Index Write Back Invalidate (RRI4), pg. 327. :diwbi as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0101 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { diwbi(as + u8_20_23_sb4); } -# DPFL - Data Cache Prefetch and Lock, pg. 329. +# DPFL - Data Cache Prefetch and Lock (RRI4), pg. 329. :dpfl as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { dpfl(as + u8_20_23_sb4); } -# DPFR - Data Cache Prefetch for Read, pg. 331. -:dpfr as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0 & op0 = 0b0010 { - dpfr(as + u10_16_23_sb2); +# DPFR - Data Cache Prefetch for Read (RRI8), pg. 331. +:dpfr as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0 & op0 = 0b0010 { + dpfr(as + ri8_i8_sh2); } -# DPFRO - Data Cache Prefetch for Read Once, pg. 333. -:dpfro as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0010 & op0 = 0b0010 { - dpfro(as + u10_16_23_sb2); +# DPFRO - Data Cache Prefetch for Read Once (RRI8), pg. 333. +:dpfro as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0010 & op0 = 0b0010 { + dpfro(as + ri8_i8_sh2); } -# DPFW - Data Cache Prefetch for Write, pg. 335. -:dpfw as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0001 & op0 = 0b0010 { - dpfw(as + u10_16_23_sb2); +# DPFW - Data Cache Prefetch for Write (RRI8), pg. 335. +:dpfw as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0001 & op0 = 0b0010 { + dpfw(as + ri8_i8_sh2); } -# DPFWO - Data Cache Prefetch for Write Once, pg. 337. -:dpfwo as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0011 & op0 = 0b0010 { - dpfwo(as + u10_16_23_sb2); +# DPFWO - Data Cache Prefetch for Write Once (RRI8), pg. 337. +:dpfwo as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0011 & op0 = 0b0010 { + dpfwo(as + ri8_i8_sh2); } -# DSYNC - Load/Store Synchronize, pg. 339. +# DSYNC - Load/Store Synchronize (RRR), pg. 339. :dsync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b0011 & op0 = 0 { dsync(); } -# ENTRY - Subroutine Entry, pg. 340. -:entry as, u15_12_23_sb3 is u15_12_23_sb3 & as & u2_6_7 = 0b00 & u2_4_5 = 0b11 & op0 = 0b0110 { +# ENTRY - Subroutine Entry (BRI12), pg. 340. +:entry as, bri12_i12_sh3 is bri12_i12_sh3 & as & bri8_m = 0b00 & bri8_n = 0b11 & op0 = 0b0110 { local callSP = a1; callinc:1 = $(PS_CALLINC); rotateRegWindow(callinc); - as = callSP - zext(u15_12_23_sb3); + as = callSP - zext(bri12_i12_sh3); } -# ESYNC - Execute Synchronize, pg. 342. +# ESYNC - Execute Synchronize (RRR), pg. 342. :esync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b0010 & op0 = 0 { esync(); } -# EXCW - Exception Wait, pg. 343. +# EXCW - Exception Wait (RRR), pg. 343. :excw is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1000 & op0 = 0 { excw(); } -# EXTUI - Extract Unsigned Immediate, pg. 344. -:extui ar, at, u5_8_11_16, u5_20_23_plus1 is u5_20_23_plus1 & u3_17_19 = 0b010 & u5_8_11_16 & ar & at & op0 = 0 { +# EXTUI - Extract Unsigned Immediate (RRR), pg. 344. +:extui ar, at, u5_8_11_16, u5_20_23_plus1 is u5_20_23_plus1 & op1_1_3 = 0b010 & u5_8_11_16 & ar & at & op0 = 0 { local shifted:4 = at >> u5_8_11_16; local mask:4 = (1:4 << (u5_20_23_plus1))-1; ar = shifted & mask; } -# EXTW - External Wait, pg. 345. +# EXTW - External Wait (RRR), pg. 345. :extw is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1101 & op0 = 0 { extw(); } -# FLOAT.S - Convert Fixed to Single, pg. 346. -:float.s fr, as, u4_4_7 is op2 = 0b1100 & op1 = 0b1010 & fr & as & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# FLOAT.S - Convert Fixed to Single (RRR), pg. 346. +:float.s fr, as, op_t is op2 = 0b1100 & op1 = 0b1010 & fr & as & op_t & op0 = 0 { + local scale:4 = 1 << op_t; fr = int2float(as) f/ int2float(scale); } -# FLOOR.S - Floor Single to Fixed, pg. 347. -:floor.s ar, fs, u4_4_7 is op2 = 0b1010 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# FLOOR.S - Floor Single to Fixed (RRR), pg. 347. +:floor.s ar, fs, op_t is op2 = 0b1010 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = 1 << op_t; ar = floor(fs f* int2float(scale)); } -# IDTLB - Invalidate Data TLB Entry, pg. 348. +# IDTLB - Invalidate Data TLB Entry (RRR), pg. 348. :idtlb as is op2 = 0b0101 & op1 = 0 & ar = 0b1100 & as & at = 0 & op0 = 0 { idtlb(); } -# IHI - Instruction Cache Hit Invalidate, pg. 349. -:ihi as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b1110 & op0 = 0b0010 { - ihi(as + u10_16_23_sb2); +# IHI - Instruction Cache Hit Invalidate (RRI8), pg. 349. +:ihi as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b1110 & op0 = 0b0010 { + ihi(as + ri8_i8_sh2); } -# IHU - Instruction Cache Hit Unlock, pg. 351. +# IHU - Instruction Cache Hit Unlock (RRI4), pg. 351. :ihu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0010 & ar = 0b0111 & as & at = 0b1101 & op0 = 0b0010 { ihu(as + u8_20_23_sb4); } -# III - Instruction Cache Index Invalidate, pg. 353. -:iii as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b1111 & op0 = 0b0010 { - iii(as + u10_16_23_sb2); +# III - Instruction Cache Index Invalidate (RRI8), pg. 353. +:iii as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b1111 & op0 = 0b0010 { + iii(as + ri8_i8_sh2); } -# IITLB - Invalidate Instruction TLB Entry, pg. 355. +# IITLB - Invalidate Instruction TLB Entry (RRR), pg. 355. :iitlb as is op2 = 0b0101 & op1 = 0 & ar = 0b0100 & as & at = 0 & op0 = 0 { iitlb(as); } -# IIU - Instruction Cache Index Unlock, pg. 356. +# IIU - Instruction Cache Index Unlock (RRI4), pg. 356. :iiu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0011 & ar = 0b0111 & as & at = 0b1101 & op0 = 0b0010 { iiu(as + u8_20_23_sb4); } -# ILL - Illegal Instruction, pg. 358. +# ILL - Illegal Instruction (CALLX), pg. 358. :ill is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & at = 0 & op0 = 0 { ill(); goto inst_start; } -# ILL.N - Narrow Illegal Instruction, pg. 359. +# ILL.N - Narrow Illegal Instruction (RRRN), pg. 359. :ill.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0110 & n_op0 = 0b1101 { ill(); goto inst_start; } -# IPF - Instruction Cache Prefetch, pg. 360. -:ipf as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b1100 & op0 = 0b0010 { - ipf(as + u10_16_23_sb2); +# IPF - Instruction Cache Prefetch (RRI8), pg. 360. +:ipf as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b1100 & op0 = 0b0010 { + ipf(as + ri8_i8_sh2); } -# IPFL - Instruction Cache Prefetch and Lock, pg. 362. +# IPFL - Instruction Cache Prefetch and Lock (RRI4), pg. 362. :ipfl as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0 & ar = 0b0111 & as & at = 0b1101 & op0 = 0b0010 { ipfl(as + u8_20_23_sb4); } -# ISYNC - Instruction Fetch Synchronize, pg. 364. +# ISYNC - Instruction Fetch Synchronize (RRR), pg. 364. :isync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0 & op0 = 0 { isync(); } -# J - Unconditional Jump, pg. 366. -:j srel_6_23 is srel_6_23 & u2_4_5 = 0 & op0 = 0b0110 { - goto srel_6_23; +# J - Unconditional Jump (CALL), pg. 366. +:j call_srel is call_srel & bri8_n = 0 & op0 = 0b0110 { + goto call_srel; } # J.L is a macro. -# RET (JX A0) - Non-Windowed Return, pg. 478. -:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6_7 = 0b10 & u2_4_5 = 0b10 & op0 = 0 { +# RET (JX A0) - Non-Windowed Return (CALLX), pg. 478. +:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & bri8_m = 0b10 & bri8_n = 0b10 & op0 = 0 { return [a0]; } # The manual suggests that RET is equivalent to JX A0, yet RET has bit 5 unset, JX doesn’t. -:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6_7 = 0b10 & u2_4_5 = 0b00 & op0 = 0 { +:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & bri8_m = 0b10 & bri8_n = 0b00 & op0 = 0 { return [a0]; } -# JX - Uncoditional Jump Register, pg. 368. -:jx as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6_7 = 0b10 & u2_4_5 = 0b10 & op0 = 0 { +# JX - Uncoditional Jump Register (CALLX), pg. 368. +:jx as is op2 = 0 & op1 = 0 & ar = 0 & as & bri8_m = 0b10 & bri8_n = 0b10 & op0 = 0 { goto [as]; } -# L8UI - Load 8-bit Unsigned, pg. 369. -:l8ui at, as, u8_16_23 is u8_16_23 & ar = 0 & as & at & op0 = 0b0010 { - local addr:4 = as + zext(u8_16_23:1); +# L8UI - Load 8-bit Unsigned (RRI8), pg. 369. +:l8ui at, as, ri8_i8 is ri8_i8 & ar = 0 & as & at & op0 = 0b0010 { + local addr:4 = as + zext(ri8_i8:1); at = zext(*:1 addr); } -# L16SI - Load 16-bit Signed, pg. 370. +# L16SI - Load 16-bit Signed (RRI8), pg. 370. :l16si at, as, u9_16_23_sb1 is u9_16_23_sb1 & ar = 0b1001 & as & at & op0 = 0b0010 { local addr:4 = as + u9_16_23_sb1; at = sext(*:2 addr); } -# L16UI - Load 16-bit Unsigned, pg. 372. +# L16UI - Load 16-bit Unsigned (RRI8), pg. 372. :l16ui at, as, u9_16_23_sb1 is u9_16_23_sb1 & ar = 0b001 & as & at & op0 = 0b0010 { local addr:4 = as + u9_16_23_sb1; at = zext(*:2 addr); } -# L32AI - Load 32-bit Acquire, pg. 374. -:l32ai at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1011 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; +# L32AI - Load 32-bit Acquire (RRI8), pg. 374. +:l32ai at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1011 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; at = *:4 addr; acquire(addr); } -# L32E - Load 32-bit for Window Exceptions, pg. 376. +# L32E - Load 32-bit for Window Exceptions (RRI4), pg. 376. :l32e at, as, s5_12_15_oex is op2 = 0 & op1 = 0b1001 & s5_12_15_oex & as & at & op0 = 0 { ptr:4 = as + sext(s5_12_15_oex); at = *:4 ptr; } -# L32I - Load 32-bit, pg. 378. -:l32i at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0010 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; +# L32I - Load 32-bit (RRI8), pg. 378. +:l32i at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0010 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; at = *:4 addr; } -# L32I.N - Narrow Load 32-bit, pg. 380. +# L32I.N - Narrow Load 32-bit (RRRN), pg. 380. :l32i.n n_at, n_as, n_u6_12_15_sb2 is n_u6_12_15_sb2 & n_as & n_at & n_op0 = 0b1000 { local addr:4 = n_as + n_u6_12_15_sb2; n_at = *:4 addr; } -# L32R - Load 32-bit PC-relative, pg. 382. -:l32r at, srel_8_23_oex_sb2 is srel_8_23_oex_sb2 & at & op0 = 0b0001 { - at = srel_8_23_oex_sb2; +# L32R - Load 32-bit PC-relative (RI6), pg. 382. +:l32r at, srel_oex_sh2 is srel_oex_sh2 & at & op0 = 0b0001 { + at = srel_oex_sh2; } -# LDCT - Load Data Cache Tag, pg. 384. +# LDCT - Load Data Cache Tag (RRR), pg. 384. :ldct at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1000 & as & at & op0 = 0 { at = ldct(as); } -# LICT - Load Instruction Cache Tag, pg. 388. +# LICT - Load Instruction Cache Tag (RRR), pg. 388. :lict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0 & as & at & op0 = 0 { at = lict(as); } -# LICW - Load Instruction Cache Word, pg. 390. +# LICW - Load Instruction Cache Word (RRR), pg. 390. :licw at, as is op2 = 0b1111 & op1 = 0b0010 & ar = 0 & as & at & op0 = 0 { at = licw(as); } -# LSI - Load Single Immediate, pg. 398. -:lsi ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0 & as & ft & op0 = 0b0011 { - local addr:4 = as + u10_16_23_sb2; +# LSI - Load Single Immediate, (RRI8) pg. 398. +:lsi ft, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0 & as & ft & op0 = 0b0011 { + local addr:4 = as + ri8_i8_sh2; ft = *:4 addr; } -# LSIU - Load Single Immediate with Update, pg. 400. -:lsiu ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1000 & as & ft & op0 = 0b0011 { - local addr:4 = as + u10_16_23_sb2; +# LSIU - Load Single Immediate with Update (RRI8), pg. 400. +:lsiu ft, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1000 & as & ft & op0 = 0b0011 { + local addr:4 = as + ri8_i8_sh2; ft = *:4 addr; as = addr; } -# LSX - Load Single Indexed, pg. 402. +# LSX - Load Single Indexed (RRR), pg. 402. :lsx fr, as, at is op2 = 0 & op1 = 0b1000 & fr & as & at & op0 = 0 { local addr:4 = as+at; fr = *:4 addr; } -# LSXU - Load Single Indexed with Update, pg. 404. +# LSXU - Load Single Indexed with Update (RRR), pg. 404. :lsxu fr, as, at is op2 = 0b0001 & op1 = 0b1000 & fr & as & at & op0 = 0 { local addr:4 = as+at; fr = *:4 addr; as = addr; } -# MADD.S - Multiply and Add Single, pg. 406. +# MADD.S - Multiply and Add Single (RRR), pg. 406. :madd.s fr, fs, ft is op2 = 0b0100 & op1 = 0b1010 & fr & fs & ft & op0 = 0 { fr = fr f+ (fs f* ft); } -# MAX - Maximum Value, pg. 407. +# MAX - Maximum Value (RRR), pg. 407. :max ar, as, at is op2 = 0b0101 & op1 = 0b0011 & ar & as & at & op0 = 0 { test:1 = as s< at; ar = (zext(test) * at) + (zext(!test) * as); } -# MAXU - Maximum Value Unsigned, pg. 408. +# MAXU - Maximum Value Unsigned (RRR), pg. 408. :maxu ar, as, at is op2 = 0b0111 & op1 = 0b0011 & ar & as & at & op0 = 0 { test:1 = as < at; ar = (zext(test) * at) + (zext(!test) * as); } -# MEMW - Memory Wait, pg. 409. +# MEMW - Memory Wait (RRR), pg. 409. :memw is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1100 & op0 = 0 { memw(); } -# MIN - Minimum Value, pg. 410. +# MIN - Minimum Value (RRR), pg. 410. :min ar, as, at is op2 = 0b0100 & op1 = 0b0011 & ar & as & at & op0 = 0 { test:1 = as s< at; ar = (zext(test) * as) + (zext(!test) * at); } -# MINU - Minimum Value Unsigned, pg. 411. +# MINU - Minimum Value Unsigned (RRR), pg. 411. :minu ar, as, at is op2 = 0b0110 & op1 = 0b0011 & ar & as & at & op0 = 0 { test:1 = as < at; ar = (zext(test) * as) + (zext(!test) * at); } -# MOV.N - Narrow Move, pg. 413. +# MOV.N - Narrow Move (RRRN), pg. 413. :mov.n n_at, n_as is n_ar = 0 & n_as & n_at & n_op0 = 0b1101 { n_at = n_as; } -# MOV.S - Move Single, pg. 414. +# MOV.S - Move Single (RRR), pg. 414. :mov.s fr, fs is op2 = 0b1111 & op1 = 0b1010 & fr & fs & at = 0 & op0 = 0 { fr = fs; } -# MOVEQZ - Move if Equal to Zero, pg. 415. +# MOVEQZ - Move if Equal to Zero (RRR), pg. 415. :moveqz ar, as, at is op2 = 0b1000 & op1 = 0b0011 & ar & as & at & op0 = 0 { if (at != 0) goto ; ar = as; } -# MOVEQZ.S - Move Single if Equal to Zero, pg. 416. +# MOVEQZ.S - Move Single if Equal to Zero (RRR), pg. 416. :moveqz.s fr, fs, at is op2 = 0b1000 & op1 = 0b1011 & fr & fs & at & op0 = 0 { if (at != 0) goto ; fr = fs; } -# MOVF - Move if False, pg. 417. +# MOVF - Move if False (RRR), pg. 417. :movf ar, as, bt is op2 = 0b1100 & op1 = 0b0011 & ar & as & bt & op0 = 0 { if (bt) goto ; ar = as; } -# MOVF.S - Move Single if False, pg. 418. +# MOVF.S - Move Single if False (RRR), pg. 418. :movf.s fr, fs, bt is op2 = 0b1100 & op1 = 0b1011 & fr & fs & bt & op0 = 0 { if (bt)goto ; fr = fs; } -# MOVGEZ - Move if Greater Than or Equal to Zero, pg. 419. +# MOVGEZ - Move if Greater Than or Equal to Zero (RRR), pg. 419. :movgez ar, as, at is op2 = 0b1011 & op1 = 0b0011 & ar & as & at & op0 = 0 { if (at s< 0) goto ; ar = as; } -# MOVGEZ.S - Move Single if Greater Than or Equal to Zero, pg. 420. +# MOVGEZ.S - Move Single if Greater Than or Equal to Zero (RRR), pg. 420. :movgez.s fr, fs, at is op2 = 0b1011 & op1 = 0b1011 & fr & fs & at & op0 = 0 { if (at s< 0) goto ; fr = fs; } -# MOVI - Move Immediate, pg. 421. -:movi at, s16_16_23_8_11 is s16_16_23_8_11 & ar = 0b1010 & at & op0 = 0b0010 { - local val:4 = sext(s16_16_23_8_11); +# MOVI - Move Immediate (RRI8), pg. 421. +:movi at, movi_si16 is movi_si16 & ar = 0b1010 & at & op0 = 0b0010 { + local val:4 = sext(movi_si16); at = val; } -# MOVI.N - Narrow Move Immediate, pg. 422. -:movi.n n_as, n_s8_12_15_4_6_asymm is n_s8_12_15_4_6_asymm & n_as & n_u1_7 = 0 & n_op0 = 0b1100 { - local val:4 = sext(n_s8_12_15_4_6_asymm); +# MOVI.N - Narrow Move Immediate (RI7), pg. 422. +:movi.n n_as, movin_si8 is movin_si8 & n_as & n_op_s_3 = 0 & n_op0 = 0b1100 { + local val:4 = sext(movin_si8); n_as = val; } -# MOVLTZ - Move if Less Than Zero, pg. 423. +# MOVLTZ - Move if Less Than Zero (RRR), pg. 423. :movltz ar, as, at is op2 = 0b1010 & op1 = 0b0011 & ar & as & at & op0 = 0 { if (at s>= 0) goto ; ar = as; } -# MOVLTZ.S - Move Single if Less Than Zero, pg. 424. +# MOVLTZ.S - Move Single if Less Than Zero (RRR), pg. 424. :movltz.s fr, fs, at is op2 = 0b1010 & op1 = 0b1011 & fr & fs & at & op0 = 0 { if (at s>= 0) goto ; fr = fs; } -# MOVNEZ - Move if Not Equal to Zero, pg. 425. +# MOVNEZ - Move if Not Equal to Zero (RRR), pg. 425. :movnez ar, as, at is op2 = 0b1001 & op1 = 0b0011 & ar & as & at & op0 = 0 { if (at == 0) goto ; ar = as; } -# MOVNEZ.S - Move Single if Not Equal to Zero, pg. 426. +# MOVNEZ.S - Move Single if Not Equal to Zero (RRR), pg. 426. :movnez.s fr, fs, at is op2 = 0b1001 & op1 = 0b1011 & fr & fs & at & op0 = 0 { if (at == 0) goto ; fr = fs; } -# MOVSP - Move to Stack Pointer, pg. 427. +# MOVSP - Move to Stack Pointer (RRR), pg. 427. :movsp at, as is op2 = 0 & op1 = 0 & ar = 0b0001 & as & at & op0 = 0 { at = (zext(WindowStart == 0) * at) + (zext(WindowStart != 0) * as); } -# MOVT - Move if True, pg. 428. +# MOVT - Move if True (RRR), pg. 428. :movt ar, as, bt is op2 = 0b1101 & op1 = 0b0011 & ar & as & bt & op0 = 0 { if (!bt) goto ; ar = as; } -# MOVT.S - Move Single if True, pg. 429. +# MOVT.S - Move Single if True (RRR), pg. 429. :movt.s fr, fs, bt is op2 = 0b1101 & op1 = 0b1011 & fr & fs & bt & op0 = 0 { if (!bt) goto ; fr = fs; } -# MSUB.S - Multiply and Subtract Single, pg. 430. +# MSUB.S - Multiply and Subtract Single (RRR), pg. 430. :msub.s fr, fs, ft is op2 = 0b0101 & op1 = 0b1010 & fr & fs & ft & op0 = 0 { fr = fr f- (fs f* ft); } -# MUL.S - Multiply Single, pg. 435. +# MUL.S - Multiply Single (RRR), pg. 435. :mul.s fr, fs, ft is op2 = 0b0010 & op1 = 0b1010 & fr & fs & ft & op0 = 0 { fr = fs f* ft; } -# MUL16S - Multiply 16-bit Signed, pg. 436. +# MUL16S - Multiply 16-bit Signed (RRR), pg. 436. :mul16s ar, as, at is op2 = 0b1101 & op1 = 0b0001 & ar & as & at & op0 = 0 { ar = sext(as:2) * sext(at:2); } -# MUL16U - Multiply 16-bit Unsigned, pg. 437. +# MUL16U - Multiply 16-bit Unsigned (RRR), pg. 437. :mul16u ar, as, at is op2 = 0b1100 & op1 = 0b0001 & ar & as & at & op0 = 0 { ar = zext(as:2) * zext(at:2); } -# MULL - Multiply Low, pg. 450. +# MULL - Multiply Low (RRR), pg. 450. :mull ar, as, at is op2 = 0b1000 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as * at; } -# MULSH - Multiply Signed High, pg. 455. +# MULSH - Multiply Signed High (RRR), pg. 455. :mulsh ar, as, at is op2 = 0b1011 & op1 = 0b0010 & ar & as & at & op0 = 0 { local s64:8 = sext(as); local t64:8 = sext(at); @@ -860,7 +860,7 @@ macro extract_bit(bit, result) { ar = p(4); } -# MULUH - Multiply Unsigned High, pg. 456. +# MULUH - Multiply Unsigned High (RRR), pg. 456. :muluh ar, as, at is op2 = 0b1010 & op1 = 0b0010 & ar & as & at & op0 = 0 { local s64:8 = zext(as); local t64:8 = zext(at); @@ -868,214 +868,214 @@ macro extract_bit(bit, result) { ar = p(4); } -# NEG - Negate, pg. 457. +# NEG - Negate (RRR), pg. 457. :neg ar, at is op2 = 0b0110 & op1 = 0 & ar & as = 0 & at & op0 = 0 { ar = -at; } -# NEG.S - Negate Single, pg. 458. +# NEG.S - Negate Single (RRR), pg. 458. :neg.s fr, fs is op2 = 0b1111 & op1 = 0b1010 & fr & fs & at = 0b0110 & op0 = 0 { fr = 0 f- fs; } -# NOP - No Operation, pg. 459. +# NOP - No Operation (RRR), pg. 459. :nop is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1111 & op0 = 0 { } -# NOP.N - Narrow No Operation, pg. 460. +# NOP.N - Narrow No Operation (RRRN), pg. 460. :nop.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0011 & n_op0 = 0b1101 { } -# NSA - Normalization Shift Amount, pg. 461. +# NSA - Normalization Shift Amount (RRR), pg. 461. :nsa at, as is op2 = 0b0100 & op1 = 0 & ar = 0b1110 & as & at & op0 = 0 { at = lzcount(~as); } -# NSAU - Normalization Shift Amount Unsigned, pg. 462. (Count leading zeros) +# NSAU - Normalization Shift Amount Unsigned (RRR), pg. 462. (Count leading zeros) :nsau at, as is op2 = 0b0100 & op1 = 0 & ar = 0b1111 & as & at & op0 = 0 { at = lzcount(as); } -# OEQ.S - Compare Single Equal, pg. 463. +# OEQ.S - Compare Single Equal (RRR), pg. 463. :oeq.s br, fs, ft is op2 = 0b0010 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = !nan(fs) && !nan(ft) && fs f== ft; } -# OLE.S - Compare Single Ordered and Less Than or Equal, pg. 464 +# OLE.S - Compare Single Ordered and Less Than or Equal (RRR), pg. 464 :ole.s br, fs, ft is op2 = 0b0110 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = !nan(fs) && !nan(ft) && fs f<= ft; } -# OLT.S - Compare Single Ordered and Less Than, pg. 465. +# OLT.S - Compare Single Ordered and Less Than (RRR), pg. 465. :olt.s br, fs, ft is op2 = 0b0100 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = !nan(fs) && !nan(ft) && fs f< ft; } -# MOV - Move, pg. 412. Special case of OR as, at, at. +# MOV - Move (RRR), pg. 412. Special case of OR as, at, at. :mov ar, as is op2 = 0b0010 & op1 = 0 & ar & as & as = at & op0 = 0 { ar = as; } -# OR - Bitwise Logical Or, pg. 466. +# OR - Bitwise Logical Or (RRR), pg. 466. :or ar, as, at is op2 = 0b0010 & op1 = 0 & ar & as & at & op0 = 0 { ar = as | at; } -# ORB - Boolean Or, pg. 467. +# ORB - Boolean Or (RRR), pg. 467. :orb br, bs, bt is op2 = 0b0010 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs || bt; } -# ORBC - Boolean Or with Complement, pg. 468. +# ORBC - Boolean Or with Complement (RRR), pg. 468. :orbc br, bs, bt is op2 = 0b0011 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs || !bt; } -# PDTLB - Probe Data TLB, pg. 469. +# PDTLB - Probe Data TLB (RRR), pg. 469. :pdtlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1101 & as & at & op0 = 0 { at = pdtlb(as); } -# PITLB - Probe Instruction TLB, pg. 470. +# PITLB - Probe Instruction TLB (RRR), pg. 470. :pitlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0101 & as & at & op0 = 0 { at = pitlb(as); } -# QUOS - Quotient Signed, pg. 471. +# QUOS - Quotient Signed (RRR), pg. 471. :quos ar, as, at is op2 = 0b1101 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as s/ at; } -# QUOU - Quotient Unsigned, pg. 472. +# QUOU - Quotient Unsigned (RRR), pg. 472. :quou ar, as, at is op2 = 0b1100 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as / at; } -# RDTLB0 - Read Data TLB Virtual Entry, pg. 473. +# RDTLB0 - Read Data TLB Virtual Entry (RRR), pg. 473. :rdtlb0 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1011 & as & at & op0 = 0 { at = rdtlb0(as); } -# RDTLB1 - Read Data TLB Entry Translation, pg. 474. +# RDTLB1 - Read Data TLB Entry Translation (RRR), pg. 474. :rdtlb1 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1111 & as & at & op0 = 0 { at = rdtlb1(as); } -# REMS - Remainder Signed, pg. 475. +# REMS - Remainder Signed (RRR), pg. 475. :rems ar, as, at, is op2 = 0b1111 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as s% at; } -# REMU - Remainder Unsigned, pg. 476. +# REMU - Remainder Unsigned (RRR), pg. 476. :remu ar, as, at, is op2 = 0b1110 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as % at; } -# RER - Read External Register, pg. 477. +# RER - Read External Register (RRR), pg. 477. :rer as, at is op2 = 0b0100 & op1 = 0 & ar = 0b0110 & as & at & op0 = 0 { as = rer(at); } -# RET.N - Narrow Non-Windowed Return, pg. 479. +# RET.N - Narrow Non-Windowed Return (RRRN), pg. 479. :ret.n is n_ar = 0b1111 & n_as = 0 & n_at = 0 & n_op0 = 0b1101 { return [a0]; } -# RETW - Windowed Return, pg. 480. -:retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6_7 = 0b10 & u2_4_5 = 0b01 & op0 = 0 { +# RETW - Windowed Return (CALLX), pg. 480. +:retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & bri8_m = 0b10 & bri8_n = 0b01 & op0 = 0 { local addr:4 = (a0 & 0x3fffffff) | (inst_start & 0xc0000000); restoreRegWindow(); return [addr]; } -# RETW.N - Narrow Windowed Return, pg. 482. +# RETW.N - Narrow Windowed Return (RRRN), pg. 482. :retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 { local addr:4 = (a0 & 0x3fffffff) | (inst_start & 0xc0000000); restoreRegWindow(); return [addr]; } -# RFDD - Return from Debug and Dispatch, pg. 484. +# RFDD - Return from Debug and Dispatch (RRR), pg. 484. :rfdd is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1110 & (as = 0b0000 | as = 0b0001) & at = 0b0001 & op0 = 0 { local tmp:4 = rfdd(); return [tmp]; } -# RFDE _ Return From Double Exception, pg. 485. +# RFDE _ Return From Double Exception (RRR), pg. 485. :rfde is op2 = 0 & op1 = 0 & ar = 0b0011 & as =0b0010 & at = 0 & op0 = 0 { local tmp:4 = rfde(); return [tmp]; } -# RFDO - Return from Debug Operation, pg. 486. +# RFDO - Return from Debug Operation (RRR), pg. 486. :rfdo is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1110 & as = 0 & at = 0 & op0 = 0 { local tmp:4 = rfdo(); return [tmp]; } -# RFE - Return From Exception, pg. 487. +# RFE - Return From Exception (RRR), pg. 487. :rfe is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0 & at = 0 & op0 = 0 { local tmp:4 = rfe(); return [tmp]; } -rfi_epc: ptr is u4_8_11 [ ptr = $(EPC_BASE) + (4 * u4_8_11); ] { export *[register]:4 ptr; } -rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[register]:4 ptr; } +rfi_epc: ptr is op_s [ ptr = $(EPC_BASE) + (4 * op_s); ] { export *[register]:4 ptr; } +rfi_eps: ptr is op_s [ ptr = $(EPS_BASE) + (4 * op_s); ] { export *[register]:4 ptr; } -# RFI - Return from High-Priority Interrupt, pg. 488. -:rfi u4_8_11 is op2 = 0 & op1 = 0 & ar = 0b0011 & u4_8_11 & at = 0b0001 & op0 = 0 & rfi_epc & rfi_eps { +# RFI - Return from High-Priority Interrupt (RRR), pg. 488. +:rfi op_s is op2 = 0 & op1 = 0 & ar = 0b0011 & op_s & at = 0b0001 & op0 = 0 & rfi_epc & rfi_eps { PS = rfi_eps; return [rfi_epc]; } -# RFME - Return from Memory Error, pg. 489. +# RFME - Return from Memory Error (RRR), pg. 489. :rfme is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0 & at = 0b0010 & op0 = 0 { PS = MEPS; MESR[0,1] = 0; return [MEPC]; } -# RFR - Move FR to AR, pg. 490. +# RFR - Move FR to AR (RRR), pg. 490. :rfr ar, fs is op2 = 0b1111 & op1 = 0b1010 & ar & fs & at = 0b0100 & op0 = 0 { ar = fs; } -# RFUE - Return from User-Mode Exception, pg. 491. +# RFUE - Return from User-Mode Exception (RRR), pg. 491. :rfue is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0b0001 & at = 0 & op0 = 0 { local tmp:4 = rfue(); return [tmp]; } -# RFWO - Return from Window Overflow, pg. 492. +# RFWO - Return from Window Overflow (RRR), pg. 492. :rfwo is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0b0100 & at = 0 & op0 = 0 { $(PS_EXCM) = 0; rfwo(); return [EPC1]; } -# RFWU - Return from Window Underflow, pg. 493. +# RFWU - Return from Window Underflow (RRR), pg. 493. :rfwu is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0b0101 & at = 0 & op0 = 0 { $(PS_EXCM) = 0; rfwu(); return [EPC1]; } -# RITLB0 - Read Instruction TLB Virtual Entry, pg. 494. +# RITLB0 - Read Instruction TLB Virtual Entry (RRR), pg. 494. :ritlb0 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0011 & as & at & op0 = 0 { at = ritlb0(as); } -# RITLB1 - Read Instruction TLB Entry Translation, pg. 495. +# RITLB1 - Read Instruction TLB Entry Translation (RRR), pg. 495. :ritlb1 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0111 & as & at & op0 = 0 { at = ritlb1(as); } -# ROTW - Rotate Window, pg. 496. -:rotw s4_4_7 is op2 = 0b0100 & op1 = 0 & ar = 0b1000 & as = 0 & s4_4_7 & op0 = 0 { - WindowBase = WindowBase + s4_4_7; +# ROTW - Rotate Window (RRR), pg. 496. +:rotw op_t_si4 is op2 = 0b0100 & op1 = 0 & ar = 0b1000 & as = 0 & op_t_si4 & op0 = 0 { + WindowBase = WindowBase + op_t_si4; } -# ROUND.S - Round Single to Fixed, pg. 497. -:round.s ar, fs, u4_4_7 is op2 = 0b1000 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# ROUND.S - Round Single to Fixed (RRR), pg. 497. +:round.s ar, fs, op_t is op2 = 0b1000 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = 1 << op_t; local result = fs f* int2float(scale); isNan:1 = nan(result); if (isNan) goto ; @@ -1088,41 +1088,41 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist } -# RSIL - Read and Set Interrupt Level, pg. 498. -:rsil at, u4_8_11 is op2 = 0 & op1 = 0 & ar = 0b0110 & u4_8_11 & at & op0 = 0 { - at = rsil(u4_8_11:1); +# RSIL - Read and Set Interrupt Level (RRR), pg. 498. +:rsil at, op_s is op2 = 0 & op1 = 0 & ar = 0b0110 & op_s & at & op0 = 0 { + at = rsil(op_s:1); } -# RSR - Read Special Register, pg. 500. +# RSR - Read Special Register (RSR), pg. 500. :rsr at, sr is op0 = 0 & op1 = 0b0011 & sr & at & op0 = 0 { at = rsr(sr:1); } -# RSYNC - Register Read Synchronize, pg. 502. +# RSYNC - Register Read Synchronize (RRR), pg. 502. :rsync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b0001 & op0 = 0 { rsync(); } -# RUR - Read User Register, pg. 503. -:rur ar, u8_4_11 is op2 = 0b1110 & op1 = 0b0011 & ar & u8_4_11 & op0 = 0 { - ar = rur(u8_4_11:1); +# RUR - Read User Register (RRR), pg. 503. +:rur ar, op_st is op2 = 0b1110 & op1 = 0b0011 & ar & op_st & op0 = 0 { + ar = rur(op_st:1); } -# S8I - Store 8-bit, pg. 504. -:s8i at, as, u8_16_23 is u8_16_23 & ar = 0b0100 & as & at & op0 = 0b0010 { - local addr:4 = as + zext(u8_16_23:1); - *:1 addr = at:1; +# S8I - Store 8-bit (RRI8), pg. 504. +:s8i at, as, ri8_i8 is ri8_i8 & ar = 0b0100 & as & at & op0 = 0b0010 { + local addr:4 = as + zext(ri8_i8:1); + *:1 addr = at:1; } -# S16I - Store 16-bit, pg. 505. +# S16I - Store 16-bit (RRI8), pg. 505. :s16i at, as, u9_16_23_sb1 is u9_16_23_sb1 & ar = 0b0101 & as & at & op0 = 0b0010 { - local addr:4 = as + u9_16_23_sb1; - *:2 addr = at:2; + local addr:4 = as + u9_16_23_sb1; + *:2 addr = at:2; } -# S32C1I - Store 32-bit Compare Conditional, pg. 506 -:s32c1i at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1110 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; +# S32C1I - Store 32-bit Compare Conditional (RRI8), pg. 506 +:s32c1i at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1110 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; old:4 = *:4 addr; if (old != SCOMPARE1) goto ; *:4 addr = at; @@ -1130,86 +1130,87 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist at = old; } -# S32E - Store 32-bit for Window Exceptions, pg. 508. +# S32E - Store 32-bit for Window Exceptions (RRI4), pg. 508. :s32e at, as, s5_12_15_oex is op2 = 0b0100 & op1 = 0b1001 & s5_12_15_oex & as & at & op0 = 0 { ptr:4 = as + sext(s5_12_15_oex); *:4 ptr = at; } -# S32I - Store 32-bit, pg. 510. -:s32i at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0110 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; - *:4 addr = at; +# S32I - Store 32-bit (RRR), pg. 510. +:s32i at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0110 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; + *:4 addr = at; } -# S32I.N - Narrow Store 32-bit, pg. 512. +# S32I.N - Narrow Store 32-bit (RRRN), pg. 512. :s32i.n n_at, n_as, n_u6_12_15_sb2 is n_u6_12_15_sb2 & n_as & n_at & n_op0 = 0b1001 { - local addr:4 = n_as + n_u6_12_15_sb2; - *:4 addr = n_at; + local addr:4 = n_as + n_u6_12_15_sb2; + *:4 addr = n_at; } -# S32RI - Store 32-bit Release, pg. 514. -:s32ri at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1111 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; +# S32RI - Store 32-bit Release (RRI8), pg. 514. +:s32ri at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1111 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; release(addr); *:4 addr = at; } -# SDCT - Store Data Cache Tag, pg. 516. +# SDCT - Store Data Cache Tag (RRR), pg. 516. :sdct at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1001 & as & at & op0 = 0 { sdct(as, at); } -# SEXT - Sign Extend, pg. 518. -:sext ar, as, u5_4_7_plus7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u5_4_7_plus7 & op0 = 0 { +# SEXT - Sign Extend (RRR), pg. 518. +# quoting mnemonic to prevent it showing up as an error in the sleigh editor +:^"sext" ar, as, u5_4_7_plus7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u5_4_7_plus7 & op0 = 0 { local shift:4 = 31 - u5_4_7_plus7; local tmp:4 = as << shift; ar = tmp s>> shift; } -:sext ar, as, 7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 0 & op0 = 0 { +:^"sext" ar, as, 7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & op_t = 0 & op0 = 0 { ar = sext(as:1); } -:sext ar, as, 15 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 8 & op0 = 0 { +:^"sext" ar, as, 15 is op2 = 0b0010 & op1 = 0b0011 & ar & as & op_t = 8 & op0 = 0 { ar = sext(as:2); } -# SICT - Store Instruction Cache Tag, pg. 519. +# SICT - Store Instruction Cache Tag (RRR), pg. 519. :sict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0001 & as & at & op0 = 0 { sict(as, at); } -# SICW - Store Instruction Cache word, pg. 521. +# SICW - Store Instruction Cache word (RRR), pg. 521. :sicw at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0011 & as & at & op0 = 0 { sicw(as, at); } -# SIMCALL - Simulator Call, pg. 523. +# SIMCALL - Simulator Call (RRR), pg. 523. :simcall is op2 = 0 & op1 = 0 & ar = 0b0101 & as = 0b0001 & at = 0 & op0 = 0 { simcall(); } -# SLL - Shift Left Logical, pg. 524. +# SLL - Shift Left Logical (RRR), pg. 524. :sll ar, as is op2 = 0b1010 & op1 = 0b0001 & ar & as & at = 0 & op0 = 0 { local sa:4 = 32 - SAR; ar = as << sa; } -# SLLI - Shift Left Logical Immediate, pg. 525. -:slli ar, as, u5_4_7_20 is u3_21_23 = 0 & u5_4_7_20 & op1 = 0b0001 & ar & as & op0 = 0 { +# SLLI - Shift Left Logical Immediate (RRR), pg. 525. +:slli ar, as, u5_4_7_20 is op2_1_3 = 0 & u5_4_7_20 & op1 = 0b0001 & ar & as & op0 = 0 { ar = as << u5_4_7_20; } -# SRA - Shift Right Arithmetic, pg. 526. +# SRA - Shift Right Arithmetic (RRR), pg. 526. :sra ar, at is op2 = 0b1011 & op1 = 0b0001 & ar & as = 0 & at & op0 = 0 { - ar = at s>> SAR; + ar = at s>> SAR; } -# SRAI - Shift Right Arithmetic Immediate, pg. 527. -:srai ar, at, u5_8_11_20 is u3_21_23 = 0b001 & u5_8_11_20 & op1 = 0b0001 & ar & at & op0 = 0 { +# SRAI - Shift Right Arithmetic Immediate (RRR), pg. 527. +:srai ar, at, u5_8_11_20 is op2_1_3 = 0b001 & u5_8_11_20 & op1 = 0b0001 & ar & at & op0 = 0 { ar = at s>> u5_8_11_20; } -# SRC - Shift Right Combined, pg. 528. +# SRC - Shift Right Combined (RRR), pg. 528. :src ar, as, at is op2 = 0b1000 & op1 = 0b0001 & ar & as & at & op0 = 0 { local s64:8 = zext(as); local t64:8 = zext(at); @@ -1218,102 +1219,102 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ar = shifted:4; } -# SRL - Shift Right Logical, pg. 529. +# SRL - Shift Right Logical (RRR), pg. 529. :srl ar, at is op2 = 0b1001 & op1 = 0b0001 & ar & as = 0 & at & op0 = 0 { ar = at >> SAR; } -# SRLI - Shift Right Logical Immediate, pg. 530. -:srli ar, at, u4_8_11 is op2 = 0b0100 & op1 = 0b0001 & ar & u4_8_11 & at & op0 = 0 { - ar = at >> u4_8_11; +# SRLI - Shift Right Logical Immediate (RRR), pg. 530. +:srli ar, at, op_s is op2 = 0b0100 & op1 = 0b0001 & ar & op_s & at & op0 = 0 { + ar = at >> op_s; } -# SSA8B - Set Shift Amount for BE Byte Shift, pg. 531. +# SSA8B - Set Shift Amount for BE Byte Shift (RRR), pg. 531. :ssa8b as is op2 = 0b0100 & op1 = 0 & ar = 0b0011 & as & at = 0 & op0 = 0 { local lsa:4 = (as&3)*8; SAR = 32 - lsa; } -# SSA8L - Set Shift Amount for LE Byte Shift, pg. 532. +# SSA8L - Set Shift Amount for LE Byte Shift (RRR), pg. 532. :ssa8l as is op2 = 0b0100 & op1 = 0 & ar = 0b0010 & as & at = 0 & op0 = 0 { local rsa:4 = (as & 3)*8; SAR = rsa; } -# SSAI - Set Shift Amount Immediate, pg. 533. -:ssai u5_8_11_4 is op2 = 0b0100 & op1 = 0 & ar = 0b0100 & u5_8_11_4 & u3_5_7 = 0 & op0 = 0 { +# SSAI - Set Shift Amount Immediate (RRR), pg. 533. +:ssai u5_8_11_4 is op2 = 0b0100 & op1 = 0 & ar = 0b0100 & u5_8_11_4 & op_t_1_3 = 0 & op0 = 0 { SAR = u5_8_11_4; } -# SSI - Store Single Immediate, pg. 534. -:ssi ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0100 & as & ft & op0 = 0b0011 { - local addr:4 = as + u10_16_23_sb2; +# SSI - Store Single Immediate (RRI8), pg. 534. +:ssi ft, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0100 & as & ft & op0 = 0b0011 { + local addr:4 = as + ri8_i8_sh2; *:4 addr = ft; } -# SSIU - Store Single Immediate with Update, pg. 536. -:ssiu ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1100 & as & ft & op0 = 0b0011 { - local addr:4 = as + u10_16_23_sb2; +# SSIU - Store Single Immediate with Update (RRI8), pg. 536. +:ssiu ft, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1100 & as & ft & op0 = 0b0011 { + local addr:4 = as + ri8_i8_sh2; *:4 addr = ft; as = addr; } -# SSL - Set Shift Amount for Left Shift, pg. 538. +# SSL - Set Shift Amount for Left Shift (RRR), pg. 538. :ssl as is op2 = 0b0100 & op1 = 0 & ar = 0b0001 & as & at = 0 & op0 = 0 { SAR = 32 - (as & 0x1f); } -# SSR - Set Shift Amount for Right Shift, pg. 539. +# SSR - Set Shift Amount for Right Shift (RRR), pg. 539. :ssr as is op2 = 0b0100 & op1 = 0 & ar = 0 & as & at = 0 & op0 = 0 { SAR = (as & 0x1f); } -# SSX - Store Single Indexed, pg. 540. +# SSX - Store Single Indexed (RRR), pg. 540. :ssx fr, as, at is op2 = 0b0100 & op1 = 0b1000 & fr & as & at & op0 = 0 { local addr:4 = as+at; *:4 addr = fr; } -# SSXU - Store Single Indexed with Update, pg. 541. +# SSXU - Store Single Indexed with Update (RRR), pg. 541. :ssxu fr, as, at is op2 = 0b0101 & op1 = 0b1000 & fr & as & at & op0 = 0 { local addr:4 = as+at; *:4 addr = fr; as = addr; } -# SUB - Subtract, pg. 542. +# SUB - Subtract (RRR), pg. 542. :sub ar, as, at is op2 = 0b1100 & op1 = 0 & ar & as & at & op0 = 0 { ar = as - at; } -# SUB.S - Subtract Single, pg. 543. +# SUB.S - Subtract Single (RRR), pg. 543. :sub.s fr, fs, ft is op2 = 0b0001 & op1 = 0b1010 & fr & fs & ft & op0 = 0 { fr = fs f- ft; } -# SUBX2 - Subtract with Shift by 1, pg. 544. +# SUBX2 - Subtract with Shift by 1 (RRR), pg. 544. :subx2 ar, as, at is op2 = 0b1101 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 1) - at; } -# SUBX4 - Subtract with Shift by 2, pg. 545. +# SUBX4 - Subtract with Shift by 2 (RRR), pg. 545. :subx4 ar, as, at is op2 = 0b1110 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 2) - at; } -# SUBX8 - Subtract with Shift by 3, pg. 546. +# SUBX8 - Subtract with Shift by 3 (RRR), pg. 546. :subx8 ar, as, at is op2 = 0b1111 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 3) - at; } -# SYSCALL - System Call, pg. 547. +# SYSCALL - System Call (RRR), pg. 547. :syscall is op2 = 0 & op1 = 0 & ar = 0b0101 & as = 0 & at = 0 & op0 = 0 { syscall(); } -# TRUNC.S - Truncate Single to Fixed, pg. 548 -:trunc.s ar, fs, u4_4_7 is op2 = 0b1001 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# TRUNC.S - Truncate Single to Fixed (RRR), pg. 548 +:trunc.s ar, fs, op_t is op2 = 0b1001 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = 1 << op_t; local result = fs f* int2float(scale); isNan:1 = nan(result); if (isNan) goto ; @@ -1326,36 +1327,36 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist } -# UEQ.S - Compare Single Unordered or Equal, pg. 549. +# UEQ.S - Compare Single Unordered or Equal (RRR), pg. 549. :ueq.s br, fs, ft is op2 = 0b0011 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = nan(fs) || nan(ft) || fs f== ft; } -# UFLOAT.S - Convert Unsigned Fixed to Single, pg. 550. -:ufloat.s fr, as, u4_4_7 is op2 = 0b1101 & op1 = 0b1010 & fr & as & u4_4_7 & op0 = 0 { +# UFLOAT.S - Convert Unsigned Fixed to Single (RRR), pg. 550. +:ufloat.s fr, as, op_t is op2 = 0b1101 & op1 = 0b1010 & fr & as & op_t & op0 = 0 { local tmp:8 = zext(as); - local scale:4 = 1 << u4_4_7; + local scale:4 = 1 << op_t; fr = int2float(tmp) f/ int2float(scale); } -# ULE.S - Compare Single Unordered or Less Than or Equal, pg. 551. +# ULE.S - Compare Single Unordered or Less Than or Equal (RRR), pg. 551. :ule.s br, fs, ft is op2 = 0b0111 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = nan(fs) || nan(ft) || fs f<= ft; } -# ULT.S - Compare Single Unordered or Less Than, pg. 552. +# ULT.S - Compare Single Unordered or Less Than (RRR), pg. 552. :ult.s br, fs, ft is op2 = 0b0101 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = nan(fs) || nan(ft) || fs f< ft; } -# UN.S - Compare Single Unordered, pg. 554. +# UN.S - Compare Single Unordered (RRR), pg. 554. :un.s br, fs, ft is op2 = 0b0001 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = nan(fs) || nan(ft); } -# UTRUNC.S - Truncate Single to Fixed Unsigned, pg. 555. -:utrunc.s ar, fs, u4_4_7 is op2 = 0b1110 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = int2float(1:2 << u4_4_7:2); +# UTRUNC.S - Truncate Single to Fixed Unsigned (RRR), pg. 555. +:utrunc.s ar, fs, op_t is op2 = 0b1110 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = int2float(1:2 << op_t:2); local tmp:8 = trunc(fs f* scale); local posof = nan(fs) || (tmp >> 16) != 0; local negof = tmp s< 0; @@ -1363,73 +1364,73 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ar = zext(posof)*0xffffffff + zext(negof)*0x80000000 + zext(noof)*tmp:4; } -# WAITI - Wait Interrupt, pg. 556. -:waiti u4_8_11 is op2 = 0 & op1 = 0 & ar = 0b0111 & u4_8_11 & at = 0 & op0 = 0 { - waiti(u4_8_11:4); +# WAITI - Wait Interrupt (RRR), pg. 556. +:waiti op_s is op2 = 0 & op1 = 0 & ar = 0b0111 & op_s & at = 0 & op0 = 0 { + waiti(op_s:4); } -# WDTLB - Write Data TLB Entry, pg. 557. +# WDTLB - Write Data TLB Entry (RRR), pg. 557. :wdtlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1110 & as & at & op0 = 0 { wdtlb(as, at); } -# WER - Write External Register, pg. 558. +# WER - Write External Register (RRR), pg. 558. :wer as, at is op2 = 0b0100 & op1 = 0 & ar = 0b0111 & as & at & op0 = 0 { wer(as, at); } -# WFR - Move AR to FR, pg. 559. +# WFR - Move AR to FR (RRR), pg. 559. :wfr fr, as is op2 = 0b1111 & op1 = 0b1010 & fr & as & at = 0b0101 & op0 = 0 { fr = as; } -# WITLB - Write Instruction TLB Entry, pg. 560. +# WITLB - Write Instruction TLB Entry (RRR), pg. 560. :witlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0110 & as & at & op0 = 0 { witlb(as, at); } -# WSR - Write Special Register, pg. 561. +# WSR - Write Special Register (RRR), pg. 561. :wsr at, sr is op2 = 0b0001 & op1 = 0b0011 & sr & at & op0 = 0 { wsr(sr:1, at); } -# WUR - Write User Register, pg. 563. +# WUR - Write User Register (RSR), pg. 563. :wur at, sr is op2 = 0b1111 & op1 = 0b0011 & sr & at & op0 = 0 { wur(sr:1, at); } -# XOR - Bitwise Exclusive Or, pg. 564. +# XOR - Bitwise Exclusive Or (RRR), pg. 564. :xor ar, as, at is op2 = 0b0011 & op1 = 0 & ar & as & at & op0 = 0 { ar = as ^ at; } -# XORB - Boolean Exclusive Or, pg. 565. +# XORB - Boolean Exclusive Or (RRR), pg. 565. :xorb br, bs, bt is op2 = 0b0100 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs ^^ bt; } -# XSR - Exchange Special Register, pg. 566. +# XSR - Exchange Special Register (RSR), pg. 566. :xsr at, sr is op2 = 0b0110 & op1 = 0b0001 & sr & at & op0 = 0 { at = xsr(sr:1, at); } ## MAC16 option ## -# LDDEC - Load with Autodecrement, pg. 386. -:lddec "MAC16_REGS[" mw_12_13 "]", as is op2 = 0b1001 & op1 = 0 & u2_14_15 = 0 & mw_12_13 & as & at = 0 & op0 = 0b0100 { +# LDDEC - Load with Autodecrement (RRR), pg. 386. +:lddec "MAC16_REGS[" mw "]", as is op2 = 0b1001 & op1 = 0 & op_r_2_2 = 0 & mw & as & at = 0 & op0 = 0b0100 { local ptr:4 = as - 4; - mw_12_13 = *:4 ptr; + mw = *:4 ptr; as = ptr; } -# LDINC - Load with Autoincrement, pg. 387. -:ldinc "MAC16_REGS[" mw_12_13 "]", as is op2 = 0b1000 & op1 = 0 & u2_14_15 = 0 & mw_12_13 & as & at = 0 & op0 = 0b0100 { +# LDINC - Load with Autoincrement (RRR), pg. 387. +:ldinc "MAC16_REGS[" mw "]", as is op2 = 0b1000 & op1 = 0 & op_r_2_2 = 0 & mw & as & at = 0 & op0 = 0b0100 { local ptr:4 = as + 4; - mw_12_13 = *:4 ptr; + mw = *:4 ptr; as = ptr; } -# MUL.AA.* - Signed Multiply, pg. 431. +# MUL.AA.* - Signed Multiply (RRR), pg. 431. :mul.aa.ll as, at is op2 = 0x7 & op1 = 0x4 & ar = 0 & as & at & op0 = 0x4 { tm1:2 = as:2; tm2:2 = at:2; @@ -1461,104 +1462,104 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = sext(M1:2) * sext(M2:2); } -# MUL.AD.* - Signed Multiply, pg. 432. -:mul.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x4 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +# MUL.AD.* - Signed Multiply (RRR), pg. 432. +:mul.ad.ll as, my is op2 = 0x3 & op1 = 0x4 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as:2; - tm2:2 = m2m3_6_6:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x5 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.hl as, my is op2 = 0x3 & op1 = 0x5 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as(2); - tm2:2 = m2m3_6_6:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x6 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.lh as, my is op2 = 0x3 & op1 = 0x6 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as:2; - tm2:2 = m2m3_6_6(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x7 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.hh as, my is op2 = 0x3 & op1 = 0x7 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as(2); - tm2:2 = m2m3_6_6(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -# MUL.AD.* - Signed Multiply, pg. 433. -:mul.da.ll m0m1_14_14, at is op2 = 0x6 & at & op1 = 0x4 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; +# MUL.AD.* - Signed Multiply (RRR), pg. 433. +:mul.da.ll mx, at is op2 = 0x6 & at & op1 = 0x4 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op0 = 0x4 { + tm1:2 = mx:2; tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.da.hl m0m1_14_14, at is op2 = 0x6 & op1 = 0x5 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; +:mul.da.hl mx, at is op2 = 0x6 & op1 = 0x5 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx:2; tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.da.lh m0m1_14_14, at is op2 = 0x6 & op1 = 0x6 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); +:mul.da.lh mx, at is op2 = 0x6 & op1 = 0x6 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx(2); tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.da.hh m0m1_14_14, at is op2 = 0x6 & op1 = 0x7 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); +:mul.da.hh mx, at is op2 = 0x6 & op1 = 0x7 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx(2); tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -# MUL.AD.* - Signed Multiply, pg. 434. -:mul.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x4 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6:2; +# MUL.AD.* - Signed Multiply (RRR), pg. 434. +:mul.dd.ll mx, my is op2 = 0x2 & op1 = 0x4 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x5 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6:2; +:mul.dd.hl mx, my is op2 = 0x2 & op1 = 0x5 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx(2); + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x6 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6(2); +:mul.dd.lh mx, my is op2 = 0x2 & op1 = 0x6 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx:2; + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x7 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6(2); +:mul.dd.hh mx, my is op2 = 0x2 & op1 = 0x7 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -# MULA.AA.* - Signed Multiply, pg. 431. +# MULA.AA.* - Signed Multiply (RRR), pg. 431. :mula.aa.ll as, at is op2 = 0x7 & op1 = 0x8 & ar = 0 & as & at & op0 = 0x4 { tm1:2 = as:2; tm2:2 = at:2; @@ -1590,281 +1591,281 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x8 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.ll as, my is op2 = 0x3 & op1 = 0x8 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as:2; - tm2:2 = m2m3_6_6:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x9 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.hl as, my is op2 = 0x3 & op1 = 0x9 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as(2); - tm2:2 = m2m3_6_6:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xa & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.lh as, my is op2 = 0x3 & op1 = 0xa & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as:2; - tm2:2 = m2m3_6_6(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xb & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.hh as, my is op2 = 0x3 & op1 = 0xb & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as(2); - tm2:2 = m2m3_6_6(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.da.ll m0m1_14_14, at is op2 = 0x6 & at & op1 = 0x8 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; +:mula.da.ll mx, at is op2 = 0x6 & at & op1 = 0x8 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op0 = 0x4 { + tm1:2 = mx:2; tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.da.hl m0m1_14_14, at is op2 = 0x6 & op1 = 0x9 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; +:mula.da.hl mx, at is op2 = 0x6 & op1 = 0x9 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx:2; tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.da.lh m0m1_14_14, at is op2 = 0x6 & op1 = 0xa & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); +:mula.da.lh mx, at is op2 = 0x6 & op1 = 0xa & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx(2); tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.da.hh m0m1_14_14, at is op2 = 0x6 & op1 = 0xb & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); +:mula.da.hh mx, at is op2 = 0x6 & op1 = 0xb & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx(2); tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x8 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6:2; +:mula.dd.ll mx, my is op2 = 0x2 & op1 = 0x8 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x9 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6:2; +:mula.dd.hl mx, my is op2 = 0x2 & op1 = 0x9 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx(2); + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xa & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6(2); +:mula.dd.lh mx, my is op2 = 0x2 & op1 = 0xa & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx:2; + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xb & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6(2); +:mula.dd.hh mx, my is op2 = 0x2 & op1 = 0xb & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -# Signed Mult/Accum, Ld/Autodec MULA.DA.*.LDDEC, pg. 441. -:mula.da.ll.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & at & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 { +# Signed Mult/Accum, Ld/Autodec MULA.DA.*.LDDEC (RRR), pg. 441. +:mula.da.ll.lddec mw, as, mx, at is op2 = 0x5 & at & op1 = 0x8 & as & op_r_3 = 0 & mw & mx & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14:2; + tm1:2 = mx:2; tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hl.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.hl.lddec mw, as, mx, at is op2 = 0x5 & op1 = 0x9 & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14:2; + tm1:2 = mx:2; tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.lh.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.lh.lddec mw, as, mx, at is op2 = 0x5 & op1 = 0xa & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14(2); + tm1:2 = mx(2); tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hh.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.hh.lddec mw, as, mx, at is op2 = 0x5 & op1 = 0xb & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14(2); + tm1:2 = mx(2); tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -# Signed Mult/Accum, Ld/Autoinc MULA.DA.*.LDINC, pg. 443. -:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & at & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 { +# Signed Mult/Accum, Ld/Autoinc MULA.DA.*.LDINC (RRR), pg. 443. +:mula.da.ll.ldinc mw, as, mx, at is op2 = 0x4 & at & op1 = 0x8 & as & op_r_3 = 0 & mw & mx & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14:2; + tm1:2 = mx:2; tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.hl.ldinc mw, as, mx, at is op2 = 0x4 & op1 = 0x9 & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14:2; + tm1:2 = mx:2; tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.lh.ldinc mw, as, mx, at is op2 = 0x4 & op1 = 0xa & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14(2); + tm1:2 = mx(2); tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.hh.ldinc mw, as, mx, at is op2 = 0x4 & op1 = 0xb & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14(2); + tm1:2 = mx(2); tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -# Signed Mult/Accum, Ld/Autodec MULA.DD.*.LDDEC, pg. 446. -:mula.dd.ll.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 { +# Signed Mult/Accum, Ld/Autodec MULA.DD.*.LDDEC (RRR), pg. 446. +:mula.dd.ll.lddec mw, as, mx, my is op2 = 0x1 & op1 = 0x8 & as & op_r_3 = 0 & op_t_3 = 0 & op_t_0_2 = 0 & my & mw & mx & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6:2; + tm1:2 = mx:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.dd.hl.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.hl.lddec mw, as, mx, my is op2 = 0x1 & op1 = 0x9 & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6(2); + tm1:2 = mx:2; + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.dd.lh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.lh.lddec mw, as, mx, my is op2 = 0x1 & op1 = 0xa & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6:2; + tm1:2 = mx(2); + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.dd.hh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.hh.lddec mw, as, mx, my is op2 = 0x1 & op1 = 0xb & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6(2); + tm1:2 = mx(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -# Signed Mult/Accum, Ld/Autoinc MULA.DD.*.LDINC, pg. 448. -:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +# Signed Mult/Accum, Ld/Autoinc MULA.DD.*.LDINC (RRR), pg. 448. +:mula.da.ll.ldinc mw, as, mx, my is op2 = 0x0 & op1 = 0x8 & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6:2; + tm1:2 = mx:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.hl.ldinc mw, as, mx, my is op2 = 0x0 & op1 = 0x9 & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6(2); + tm1:2 = mx:2; + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.lh.ldinc mw, as, mx, my is op2 = 0x0 & op1 = 0xa & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6:2; + tm1:2 = mx(2); + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.hh.ldinc mw, as, mx, my is op2 = 0x0 & op1 = 0xb & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6(2); + tm1:2 = mx(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -# UMUL.AA.* - Unsigned Multiply, pg. 553. +# UMUL.AA.* - Unsigned Multiply (RRR), pg. 553. :umul.aa.ll as, at is op2 = 0x7 & op1 = 0x0 & ar = 0 & as & at & op0 = 0x4 { tm1:2 = as:2; tm2:2 = at:2; @@ -1898,9 +1899,9 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ## Loop Option ## -LoopOffset8: loc is u8_16_23 [ loc = inst_start + u8_16_23 + 4; ] { export *:4 loc; } +LoopOffset8: loc is ri8_i8 [ loc = inst_start + ri8_i8 + 4; ] { export *:4 loc; } -# LOOP - Loop, pg. 392. +# LOOP - Loop (BRI8), pg. 392. :loop as, LoopOffset8 is LoopOffset8 & ar = 8 & as & at = 0b0111 & op0 = 6 [ loopMode=1; loopEnd = 1; globalset(LoopOffset8, loopEnd); ] { LCOUNT = as - 1; @@ -1908,7 +1909,7 @@ LoopOffset8: loc is u8_16_23 [ loc = inst_start + u8_16_23 + 4; ] { export *:4 l LEND = &LoopOffset8; } -# LOOPGTZ - Loop if Greater Than Zero, pg. 394. +# LOOPGTZ - Loop if Greater Than Zero (BRI8), pg. 394. :loopgtz as, LoopOffset8 is LoopOffset8 & ar = 0b1010 & as & at = 0b0111 & op0 = 0b0110 [ loopMode=1; loopEnd = 1; globalset(LoopOffset8, loopEnd); ] { LCOUNT = as - 1; @@ -1917,7 +1918,7 @@ LoopOffset8: loc is u8_16_23 [ loc = inst_start + u8_16_23 + 4; ] { export *:4 l if (as s<= 0) goto LoopOffset8; } -# LOOPNEZ - Loop if Not Equal Zero, pg. 396. +# LOOPNEZ - Loop if Not Equal Zero (BRI8), pg. 396. :loopnez as, LoopOffset8 is LoopOffset8 & ar = 0b1001 & as & at = 0b0111 & op0 = 0b0110 [ loopMode=1; loopEnd = 1; globalset(LoopOffset8, loopEnd); ] { LCOUNT = as - 1; diff --git a/pypcode/processors/Xtensa/data/languages/xtensaMain.sinc b/pypcode/processors/Xtensa/data/languages/xtensaMain.sinc index 55a1e2e2..6aee9c3a 100644 --- a/pypcode/processors/Xtensa/data/languages/xtensaMain.sinc +++ b/pypcode/processors/Xtensa/data/languages/xtensaMain.sinc @@ -87,15 +87,15 @@ attach variables [ br bs bt ] [ # bits are named foo_LL.LM_ML.MM, where LL is the least significant bits of the least # singificant operand half, LM the most significant bits of the least significant operand half, etc. -attach variables [ mw_12_13 ] [ +attach variables [ mw ] [ M0 M1 M2 M3 ]; -attach variables [ m2m3_6_6 ] [ +attach variables [ my ] [ M2 M3 ]; -attach variables [ m0m1_14_14 ] [ +attach variables [ mx ] [ M0 M1 ]; @@ -184,62 +184,62 @@ define pcodeop xsr; # bits are named foo_LL_LM_ML_MM, where LL is the least significant bits of the least # singificant operand half, LM the most significant bits of the least significant operand half, etc. -srel_16_23: rel is s8_16_23 [ rel = inst_start + s8_16_23 + 4; ] { export *:4 rel; } +ri8_srel: rel is ri8_si8 [ rel = inst_start + ri8_si8 + 4; ] { export *:4 rel; } -srel_12_23: rel is s12_12_23 [ rel = inst_start + s12_12_23 + 4; ] { export *:4 rel; } +bri12_srel: rel is bri12_si12 [ rel = inst_start + bri12_si12 + 4; ] { export *:4 rel; } -srel_6_23: rel is s8_6_23 [ rel = inst_start + s8_6_23 + 4; ] { export *:4 rel; } - -urel_12_15_4_5: rel is n_u2_4_5 & n_u4_12_15 [ - rel = inst_start + ((n_u2_4_5 << 4) | n_u4_12_15) + 4; +ri6_rel: rel is ri6_i6_4_2 & ri6_i6_0_4 [ + rel = inst_start + ((ri6_i6_4_2 << 4) | ri6_i6_0_4) + 4; ] { export *:4 rel; } -srel_6_23_sb2: rel is s8_6_23 [ - rel = (inst_start & ~3) + ( s8_6_23 << 2 ) + 4; +call_srel: rel is call_o18 [ rel = inst_start + call_o18 + 4; ] { export *:4 rel; } + +call_srel_sh2: rel is call_o18 [ + rel = (inst_start & ~3) + ( call_o18 << 2 ) + 4; ] { export *:4 rel; } -srel_8_23_oex_sb2: rel is u16_8_23 [ - rel = ((inst_start + 3) & ~3) + ((u16_8_23 | 0xffff0000) << 2); +srel_oex_sh2: rel is ri16_i16 [ + rel = ((inst_start + 3) & ~3) + ((ri16_i16 | 0xffff0000) << 2); ] { export *:4 rel; } # Immediates split across the instruction. -u5_8_11_20: tmp is u1_20 & u4_8_11 [ tmp = (u1_20 << 4) | u4_8_11; ] { export *[const]:4 tmp; } -u5_4_7_20: tmp is u1_20 & u4_4_7 [ tmp = 32 - ((u1_20 << 4) | u4_4_7); ] { export *[const]:4 tmp; } -u5_8_11_16: tmp is u1_16 & u4_8_11 [ tmp = (u1_16 << 4) | u4_8_11; ] { export *[const]:4 tmp; } -u5_4_7_12: tmp is u1_12 & u4_4_7 [ tmp = (u1_12 << 4) | u4_4_7; ] { export *[const]:4 tmp; } -u5_8_11_4: tmp is u1_4 & u4_8_11 [ tmp = (u1_4 << 4) | u4_8_11; ] { export *[const]:4 tmp; } +u5_8_11_20: tmp is op2_0 & op_s [ tmp = (op2_0 << 4) | op_s; ] { export *[const]:4 tmp; } +u5_4_7_20: tmp is op2_0 & op_t [ tmp = 32 - ((op2_0 << 4) | op_t); ] { export *[const]:4 tmp; } +u5_8_11_16: tmp is op1_0 & op_s [ tmp = (op1_0 << 4) | op_s; ] { export *[const]:4 tmp; } +u5_4_7_12: tmp is op_r_0 & op_t [ tmp = (op_r_0 << 4) | op_t; ] { export *[const]:4 tmp; } +u5_8_11_4: tmp is op_t_0 & op_s [ tmp = (op_t_0 << 4) | op_s; ] { export *[const]:4 tmp; } # Signed 12-bit (extended to 16) immediate, used by MOVI. -s16_16_23_8_11: tmp is s4_8_11 & u8_16_23 [ - tmp = (s4_8_11 << 8) | u8_16_23; +movi_si16: tmp is op_st_i8 & ri8_i8 [ + tmp = (op_st_i8 << 8) | ri8_i8; ] { export *[const]:2 tmp; } # An “asymmetric” immediate from -32..95, used by MOVI.N. -n_s8_12_15_4_6_asymm: tmp is n_s3_4_6 & n_s4_12_15 [ - tmp = ((((n_s3_4_6 & 7) << 4) | (n_s4_12_15 & 15)) | - ((((n_s3_4_6 >> 2) & 1) & ((n_s3_4_6 >> 1) & 1)) << 7)); +movin_si8: tmp is n_op_s_0_3 & ri6_si6_0_4 [ + tmp = ((((n_op_s_0_3 & 7) << 4) | (ri6_si6_0_4 & 15)) | + ((((n_op_s_0_3 >> 2) & 1) & ((n_op_s_0_3 >> 1) & 1)) << 7)); ] { export *[const]:1 tmp; } # Immediates shifted or with offset. -s16_16_23_sb8: tmp is s8_16_23 [ tmp = s8_16_23 << 8; ] { export *[const]:4 tmp; } -u15_12_23_sb3: tmp is u12_12_23 [ tmp = u12_12_23 << 3; ] { export *[const]:4 tmp; } -u10_16_23_sb2: tmp is u8_16_23 [ tmp = u8_16_23 << 2; ] { export *[const]:4 tmp; } -u9_16_23_sb1: tmp is u8_16_23 [ tmp = u8_16_23 << 1; ] { export *[const]:4 tmp; } -u5_20_23_plus1: tmp is u4_20_23 [ tmp = u4_20_23 + 1; ] { export *[const]:4 tmp; } -u8_20_23_sb4: tmp is u4_20_23 [ tmp = u4_20_23 << 4; ] { export *[const]:4 tmp; } -u5_4_7_plus7: tmp is u4_4_7 [ tmp = u4_4_7 + 7; ] { export *[const]:4 tmp; } +ri8_si8_sh8: tmp is ri8_si8 [ tmp = ri8_si8 << 8; ] { export *[const]:4 tmp; } +bri12_i12_sh3: tmp is bri12_i12 [ tmp = bri12_i12 << 3; ] { export *[const]:4 tmp; } +ri8_i8_sh2: tmp is ri8_i8 [ tmp = ri8_i8 << 2; ] { export *[const]:4 tmp; } +u9_16_23_sb1: tmp is ri8_i8 [ tmp = ri8_i8 << 1; ] { export *[const]:4 tmp; } +u5_20_23_plus1: tmp is op2 [ tmp = op2 + 1; ] { export *[const]:4 tmp; } +u8_20_23_sb4: tmp is op2 [ tmp = op2 << 4; ] { export *[const]:4 tmp; } +u5_4_7_plus7: tmp is op_t [ tmp = op_t + 7; ] { export *[const]:4 tmp; } -n_u6_12_15_sb2: tmp is n_u4_12_15 [ tmp = n_u4_12_15 << 2; ] { export *[const]:4 tmp; } +n_u6_12_15_sb2: tmp is ri6_i6_0_4 [ tmp = ri6_i6_0_4 << 2; ] { export *[const]:4 tmp; } # One-extended. FIXME: Verify this. Only used by [LS]32E (window extension), which aren’t yet # implemented. -s5_12_15_oex: tmp is u4_12_15 [ tmp = (u4_12_15 << 2) - 64; ] { export *[const]:2 tmp; } +s5_12_15_oex: tmp is op_r [ tmp = (op_r << 2) - 64; ] { export *[const]:2 tmp; } # Some 4-bit immediates with mappings that can’t be (easily) expressed in a single disassembly action. # n_u4_4_7 with 0 being -1, used by ADDI.N. -n_s4_4_7_nozero: tmp is n_u4_4_7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; } -n_s4_4_7_nozero: tmp is n_u4_4_7 [ tmp = n_u4_4_7+0; ] { export *[const]:4 tmp; } +n_s4_4_7_nozero: tmp is n_op_s = 0 [ tmp = -1; ] { export *[const]:4 tmp; } +n_s4_4_7_nozero: tmp is n_op_s [ tmp = n_op_s+0; ] { export *[const]:4 tmp; } # B4CONST(ar) (Branch Immediate) encodings, pg. 41 f. r_b4const: tmp is ar = 0 [ tmp = 0xffffffff; ] { export *[const]:4 tmp; } diff --git a/pypcode/processors/Xtensa/data/languages/xtensa_depbits.sinc b/pypcode/processors/Xtensa/data/languages/xtensa_depbits.sinc index ccf79911..6cf3037e 100644 --- a/pypcode/processors/Xtensa/data/languages/xtensa_depbits.sinc +++ b/pypcode/processors/Xtensa/data/languages/xtensa_depbits.sinc @@ -2,9 +2,9 @@ # This is broken out because it collides with the floating point instructions. It is not included by default # DEPBITS - Add (RRR), pg. 394. -shiftimm: simm is u4_20_23 & u1_16 [ simm = u1_16 << 4 + u4_20_23; ] { export *[const]:4 simm; } -:depbits as, at, shiftimm, u4_12_15 is u3_17_19=0x5 & u4_12_15 & as & at & op0 = 0 & shiftimm { - mask:4 = (1 << u4_12_15) - 1; +shiftimm: simm is op2 & op1_0 [ simm = op1_0 << 4 + op2; ] { export *[const]:4 simm; } +:depbits as, at, shiftimm, u4_12_15 is op1_1_3=0x5 & op_r & as & at & op0 = 0 & shiftimm { + mask:4 = (1 << op_r) - 1; bits:4 = (as & mask) << shiftimm; mask = mask << shiftimm; at = (~mask & at) | bits; diff --git a/pypcode/processors/eBPF/data/languages/eBPF.sinc b/pypcode/processors/eBPF/data/languages/eBPF.sinc index 62a77a10..32cbc7ee 100644 --- a/pypcode/processors/eBPF/data/languages/eBPF.sinc +++ b/pypcode/processors/eBPF/data/languages/eBPF.sinc @@ -272,38 +272,38 @@ DST4: dst is dst { local tmp:4 = dst:4; export tmp; } # BPF_ADD: # BPF_STX | BPF_ATOMIC | BPF_W -:STXXADDW [dst + off], src is imm=0x0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) + src:4; } +:AADD32 [dst + off], src is imm=0x0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) + src:4; } # BPF_STX | BPF_ATOMIC | BPF_DW -:STXXADDDW [dst + off], src is imm=0x0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) + src; } +:AADD [dst + off], src is imm=0x0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) + src; } # BPF_OR: -:STXXADDW [dst + off], src is imm=0x40 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) | src:4; } +:AOR32 [dst + off], src is imm=0x40 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) | src:4; } -:STXXADDDW [dst + off], src is imm=0x40 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) | src; } +:AOR [dst + off], src is imm=0x40 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) | src; } # BPF_AND: -:STXXADDW [dst + off], src is imm=0x50 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) & src:4; } +:AAND32 [dst + off], src is imm=0x50 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) & src:4; } -:STXXADDDW [dst + off], src is imm=0x50 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) & src; } +:AAND [dst + off], src is imm=0x50 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) & src; } # BPF_XOR: -:STXXADDW [dst + off], src is imm=0xa0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) ^ src:4; } +:AXOR32 [dst + off], src is imm=0xa0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { *:4 (dst + off) = *:4 (dst + off) ^ src:4; } -:STXXADDDW [dst + off], src is imm=0xa0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) ^ src; } +:AXOR [dst + off], src is imm=0xa0 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { *:8 (dst + off) = *:8 (dst + off) ^ src; } # BPF_ADD | BPF_FETCH -> src = atomic_fetch_add(dst + off, src): -:STXXADDW [dst + off], src is imm=0x1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { +:AFADD32 [dst + off], src is imm=0x1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { local tmp:4 = *:4 (dst + off); *:4 (dst + off) = *:4 (dst + off) + src:4; src = zext(tmp); } -:STXXADDDW [dst + off], src is imm=0x1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { +:AFADD [dst + off], src is imm=0x1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { local tmp:8 = *:8 (dst + off); *:8 (dst + off) = *:8 (dst + off) + src; src = tmp; @@ -311,13 +311,13 @@ DST4: dst is dst { local tmp:4 = dst:4; export tmp; } # BPF_OR | BPF_FETCH -> src = atomic_fetch_or(dst + off, src): -:STXXADDW [dst + off], src is imm=0x41 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { +:AFOR32 [dst + off], src is imm=0x41 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { local tmp:4 = *:4 (dst + off); *:4 (dst + off) = *:4 (dst + off) | src:4; src = zext(tmp); } -:STXXADDDW [dst + off], src is imm=0x41 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { +:AFOR [dst + off], src is imm=0x41 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { local tmp:8 = *:8 (dst + off); *:8 (dst + off) = *:8 (dst + off) | src; src = tmp; @@ -325,13 +325,13 @@ DST4: dst is dst { local tmp:4 = dst:4; export tmp; } # BPF_AND | BPF_FETCH -> src = atomic_fetch_and(dst + off, src): -:STXXADDW [dst + off], src is imm=0x51 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { +:AFAND32 [dst + off], src is imm=0x51 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { local tmp:4 = *:4 (dst + off); *:4 (dst + off) = *:4 (dst + off) & src:4; src = zext(tmp); } -:STXXADDDW [dst + off], src is imm=0x51 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { +:AFAND [dst + off], src is imm=0x51 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { local tmp:8 = *:8 (dst + off); *:8 (dst + off) = *:8 (dst + off) & src; src = tmp; @@ -339,13 +339,13 @@ DST4: dst is dst { local tmp:4 = dst:4; export tmp; } # BPF_XOR | BPF_FETCH -> src = atomic_fetch_xor(dst + off, src): -:STXXADDW [dst + off], src is imm=0xa1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { +:AFXOR32 [dst + off], src is imm=0xa1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { local tmp:4 = *:4 (dst + off); *:4 (dst + off) = *:4 (dst + off) ^ src:4; src = zext(tmp); } -:STXXADDDW [dst + off], src is imm=0xa1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { +:AFXOR [dst + off], src is imm=0xa1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { local tmp:8 = *:8 (dst + off); *:8 (dst + off) = *:8 (dst + off) ^ src; src = tmp; @@ -353,13 +353,13 @@ DST4: dst is dst { local tmp:4 = dst:4; export tmp; } # BPF_XCHG -> src_reg = atomic_xchg(dst + off, src): -:STXXADDW [dst + off], src is imm=0xe1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { +:AXCHG32 [dst + off], src is imm=0xe1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { local tmp:4 = *:4 (dst + off); *:4 (dst + off) = src:4; src = zext(tmp); } -:STXXADDDW [dst + off], src is imm=0xe1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { +:AXCHG [dst + off], src is imm=0xe1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { local tmp:8 = *:8 (dst + off); *:8 (dst + off) = src; src = tmp; @@ -367,20 +367,21 @@ DST4: dst is dst { local tmp:4 = dst:4; export tmp; } # BPF_CMPXCHG -> R0 = atomic_cmpxchg(dst + off, R0, src): -:STXXADDW [dst + off], src is imm=0xf1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { +:ACMP32 [dst + off], src is imm=0xf1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x0 & op_insn_class=0x3 { local tmp:4 = *:4 (dst + off); - if (R0:4 == tmp) goto ; - R0 = zext(tmp); - + if (R0:4 != tmp) goto ; *:4 (dst + off) = src:4; + + R0 = zext(tmp); } -:STXXADDDW [dst + off], src is imm=0xf1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { +:ACMP [dst + off], src is imm=0xf1 & off & src & dst & op_ld_st_mode=0x6 & op_ld_st_size=0x3 & op_insn_class=0x3 { local tmp:8 = *:8 (dst + off); - if (R0 == tmp) goto ; - R0 = tmp; - - *:8 (dst + off) = src; + if (R0 != tmp) goto ; + *:8 (dst + off) = src; + goto inst_next; + + R0 = tmp; } #Jump instructions (BPF_JMP, BPF_JMP32) diff --git a/pypcode/processors/tricore/data/languages/tc172x.pspec b/pypcode/processors/tricore/data/languages/tc172x.pspec index 57dc6aee..e3350f00 100644 --- a/pypcode/processors/tricore/data/languages/tc172x.pspec +++ b/pypcode/processors/tricore/data/languages/tc172x.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/tricore/data/languages/tc176x.pspec b/pypcode/processors/tricore/data/languages/tc176x.pspec index e5d96cdc..7af25d21 100644 --- a/pypcode/processors/tricore/data/languages/tc176x.pspec +++ b/pypcode/processors/tricore/data/languages/tc176x.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/tricore/data/languages/tc29x.pspec b/pypcode/processors/tricore/data/languages/tc29x.pspec index 70d760bc..e0f7b5ac 100644 --- a/pypcode/processors/tricore/data/languages/tc29x.pspec +++ b/pypcode/processors/tricore/data/languages/tc29x.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/tricore/data/languages/tricore.ldefs b/pypcode/processors/tricore/data/languages/tricore.ldefs index 1c9a575a..273bb238 100644 --- a/pypcode/processors/tricore/data/languages/tricore.ldefs +++ b/pypcode/processors/tricore/data/languages/tricore.ldefs @@ -11,7 +11,7 @@ processorspec="tricore.pspec" manualindexfile="../manuals/tricore2.idx" id="tricore:LE:32:default"> - Siemens Tricore Embedded Processor + Infineon Tricore Embedded Processor @@ -24,7 +24,7 @@ processorspec="tc29x.pspec" manualindexfile="../manuals/tricore2.idx" id="tricore:LE:32:tc29x"> - Siemens Tricore Embedded Processor TC29x + Infineon Tricore Embedded Processor TC29x @@ -37,7 +37,7 @@ processorspec="tc172x.pspec" manualindexfile="../manuals/tricore.idx" id="tricore:LE:32:tc172x"> - Siemens Tricore Embedded Processor TC1724/TC1728 + Infineon Tricore Embedded Processor TC1724/TC1728 @@ -50,7 +50,7 @@ processorspec="tc176x.pspec" manualindexfile="../manuals/tricore.idx" id="tricore:LE:32:tc176x"> - Siemens Tricore Embedded Processor TC1762/TC1766 + Infineon Tricore Embedded Processor TC1762/TC1766 diff --git a/pypcode/processors/tricore/data/languages/tricore.pspec b/pypcode/processors/tricore/data/languages/tricore.pspec index 83522022..853d9d9a 100644 --- a/pypcode/processors/tricore/data/languages/tricore.pspec +++ b/pypcode/processors/tricore/data/languages/tricore.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/x86/data/languages/x86-16-real.pspec b/pypcode/processors/x86/data/languages/x86-16-real.pspec index ba7ff912..c8c6483d 100644 --- a/pypcode/processors/x86/data/languages/x86-16-real.pspec +++ b/pypcode/processors/x86/data/languages/x86-16-real.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/x86/data/languages/x86-16.pspec b/pypcode/processors/x86/data/languages/x86-16.pspec index ae2d69c7..9ac87bdc 100644 --- a/pypcode/processors/x86/data/languages/x86-16.pspec +++ b/pypcode/processors/x86/data/languages/x86-16.pspec @@ -5,6 +5,7 @@ + diff --git a/pypcode/processors/x86/data/languages/x86-64-compat32.pspec b/pypcode/processors/x86/data/languages/x86-64-compat32.pspec index 51ba63c8..be2b7738 100644 --- a/pypcode/processors/x86/data/languages/x86-64-compat32.pspec +++ b/pypcode/processors/x86/data/languages/x86-64-compat32.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/x86/data/languages/x86-64.pspec b/pypcode/processors/x86/data/languages/x86-64.pspec index 45df40cd..13cdbb84 100644 --- a/pypcode/processors/x86/data/languages/x86-64.pspec +++ b/pypcode/processors/x86/data/languages/x86-64.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/x86/data/languages/x86.opinion b/pypcode/processors/x86/data/languages/x86.opinion index c086a56d..4e5fc7a3 100644 --- a/pypcode/processors/x86/data/languages/x86.opinion +++ b/pypcode/processors/x86/data/languages/x86.opinion @@ -42,6 +42,12 @@ + + + + + + diff --git a/pypcode/processors/x86/data/languages/x86.pspec b/pypcode/processors/x86/data/languages/x86.pspec index b473a93b..a577b197 100644 --- a/pypcode/processors/x86/data/languages/x86.pspec +++ b/pypcode/processors/x86/data/languages/x86.pspec @@ -4,6 +4,7 @@ + diff --git a/pypcode/processors/x86/data/patterns/x86win_patterns.xml b/pypcode/processors/x86/data/patterns/x86win_patterns.xml index c048c9f3..909bc730 100644 --- a/pypcode/processors/x86/data/patterns/x86win_patterns.xml +++ b/pypcode/processors/x86/data/patterns/x86win_patterns.xml @@ -10,6 +10,7 @@ 0x558bec + 0x5589e5 0x83ec 0.....00 0x6aff68........64a100000000 0x568bf1 @@ -29,6 +30,7 @@ 0x53568bf0 0x56578bf9 0x56578bf1 + 0x55575653 diff --git a/pypcode/pypcode_native.cpp b/pypcode/pypcode_native.cpp index 9ed0a380..3ab6eebf 100644 --- a/pypcode/pypcode_native.cpp +++ b/pypcode/pypcode_native.cpp @@ -521,9 +521,10 @@ NB_MODULE(pypcode_native, m) .value("CPOOLREF", OpCode::CPUI_CPOOLREF, "Recover a value from the constant pool") .value("NEW", OpCode::CPUI_NEW, "Allocate a new object (new)") .value("INSERT", OpCode::CPUI_INSERT, "Insert a bit-range") - .value("EXTRACT", OpCode::CPUI_EXTRACT, "Extract a bit-range") + .value("ZPULL", OpCode::CPUI_ZPULL, "Extract an unsigned bit-range") .value("POPCOUNT", OpCode::CPUI_POPCOUNT, "Count the 1-bits") - .value("LZCOUNT", OpCode::CPUI_LZCOUNT, "Count the leading 0-bits"); + .value("LZCOUNT", OpCode::CPUI_LZCOUNT, "Count the leading 0-bits") + .value("SPULL", OpCode::CPUI_SPULL, "Extract a signed bit-range"); nb::class_(m, "PcodeOp", "Low-level representation of a single P-Code operation.") .def_ro("opcode", &PcodeOp::m_opcode, "opcode(self) -> OpCode\nOpcode for this operation.") diff --git a/pypcode/pypcode_native.pyi b/pypcode/pypcode_native.pyi index 7dac126f..b9198272 100644 --- a/pypcode/pypcode_native.pyi +++ b/pypcode/pypcode_native.pyi @@ -1,13 +1,7 @@ -from typing import Any, ClassVar, List, Optional - -__version__: str +from typing import Any, Callable, ClassVar TRANSLATE_FLAGS_BB_TERMINATING: int - -class BadDataError(Exception): ... -class DecoderError(Exception): ... -class LowlevelError(Exception): ... -class UnimplError(Exception): ... +__version__: str class AddrSpace: def __init__(self, *args, **kwargs) -> None: ... @@ -21,6 +15,34 @@ class Address: @property def space(self) -> AddrSpace: ... +class BadDataError(Exception): ... + +class Context: + def __init__(self, arg: str) -> None: ... + def disassemble( + self, buf: bytes, base_address: int = ..., offset: int = ..., max_bytes: int = ..., max_instructions: int = ... + ) -> Disassembly: ... + def getAllRegisters(self) -> dict[Varnode, str]: ... + def getRegisterName(self, space: AddrSpace, offset: int, size: int) -> str: ... + def reset(self) -> None: ... + def setVariableDefault(self, name: str, value: int) -> None: ... + def translate( + self, + buf: bytes, + base_address: int = ..., + offset: int = ..., + max_bytes: int = ..., + max_instructions: int = ..., + flags: int = ..., + ) -> Translation: ... + +class DecoderError(Exception): ... + +class Disassembly: + def __init__(self, *args, **kwargs) -> None: ... + @property + def instructions(self) -> list[Instruction]: ... + class Instruction: def __init__(self, *args, **kwargs) -> None: ... @property @@ -32,12 +54,10 @@ class Instruction: @property def mnem(self) -> str: ... -class Disassembly: - def __init__(self, *args, **kwargs) -> None: ... - @property - def instructions(self) -> List[Instruction]: ... +class LowlevelError(Exception): ... class OpCode: + __new__: ClassVar[Callable] = ... BOOL_AND: ClassVar[OpCode] = ... BOOL_NEGATE: ClassVar[OpCode] = ... BOOL_OR: ClassVar[OpCode] = ... @@ -51,7 +71,6 @@ class OpCode: CBRANCH: ClassVar[OpCode] = ... COPY: ClassVar[OpCode] = ... CPOOLREF: ClassVar[OpCode] = ... - EXTRACT: ClassVar[OpCode] = ... FLOAT_ABS: ClassVar[OpCode] = ... FLOAT_ADD: ClassVar[OpCode] = ... FLOAT_CEIL: ClassVar[OpCode] = ... @@ -100,17 +119,19 @@ class OpCode: INT_XOR: ClassVar[OpCode] = ... INT_ZEXT: ClassVar[OpCode] = ... LOAD: ClassVar[OpCode] = ... + LZCOUNT: ClassVar[OpCode] = ... MULTIEQUAL: ClassVar[OpCode] = ... NEW: ClassVar[OpCode] = ... PIECE: ClassVar[OpCode] = ... POPCOUNT: ClassVar[OpCode] = ... - LZCOUNT: ClassVar[OpCode] = ... PTRADD: ClassVar[OpCode] = ... PTRSUB: ClassVar[OpCode] = ... RETURN: ClassVar[OpCode] = ... SEGMENTOP: ClassVar[OpCode] = ... + SPULL: ClassVar[OpCode] = ... STORE: ClassVar[OpCode] = ... SUBPIECE: ClassVar[OpCode] = ... + ZPULL: ClassVar[OpCode] = ... __entries: ClassVar[dict] = ... __name__: Any @property @@ -128,52 +149,30 @@ class OpCode: def __lt__(self, other) -> Any: ... def __ne__(self, other) -> Any: ... -class Varnode: - def __init__(self) -> None: ... - def getRegisterName(self) -> str: ... - def getUserDefinedOpName(self) -> str: ... - def getSpaceFromConst(self) -> AddrSpace: ... - @property - def offset(self) -> int: ... - @property - def size(self) -> int: ... - @property - def space(self) -> AddrSpace: ... - class PcodeOp: def __init__(self, *args, **kwargs) -> None: ... @property - def inputs(self) -> List[Varnode]: ... + def inputs(self) -> list[Varnode]: ... @property def opcode(self) -> OpCode: ... @property - def output(self) -> Optional[Varnode]: ... + def output(self) -> Varnode | None: ... class Translation: def __init__(self, *args, **kwargs) -> None: ... @property - def ops(self) -> List[PcodeOp]: ... + def ops(self) -> list[PcodeOp]: ... -class Context: - def __init__(self, *args, **kwargs) -> None: ... - def disassemble( - self, - bytes: bytes, - base_address: int = ..., - offset: int = ..., - max_bytes: int = ..., - max_instructions: int = ..., - ) -> Disassembly: ... - def getAllRegisters(self) -> dict[Varnode, str]: ... - def getRegisterName(self, space: AddrSpace, offset: int, size: int) -> str: ... - def reset(self) -> None: ... - def setVariableDefault(self, name: str, value: int) -> None: ... - def translate( - self, - bytes: bytes, - base_address: int = ..., - offset: int = ..., - max_bytes: int = ..., - max_instructions: int = ..., - flags: int = ..., - ) -> Translation: ... +class UnimplError(Exception): ... + +class Varnode: + def __init__(self) -> None: ... + def getRegisterName(self) -> str: ... + def getSpaceFromConst(self) -> AddrSpace: ... + def getUserDefinedOpName(self) -> str: ... + @property + def offset(self) -> int: ... + @property + def size(self) -> int: ... + @property + def space(self) -> AddrSpace: ... diff --git a/pypcode/sleigh/Makefile b/pypcode/sleigh/Makefile index 5330c157..2fbdd477 100644 --- a/pypcode/sleigh/Makefile +++ b/pypcode/sleigh/Makefile @@ -83,7 +83,7 @@ DECCORE=capability architecture options graph cover block cast typeop database c variable varmap jumptable emulate emulateutil flow userop expression multiprecision \ funcdata funcdata_block funcdata_op funcdata_varnode unionresolve pcodeinject \ heritage prefersplit rangeutil ruleaction subflow blockaction merge double \ - transform constseq coreaction condexe override dynamic crc32 prettyprint \ + transform constseq bitfield coreaction condexe override dynamic crc32 prettyprint \ printlanguage printc printjava memstate opbehavior paramid signature $(COREEXT_NAMES) # Files used for any project that use the sleigh decoder SLEIGH= sleigh pcodeparse pcodecompile sleighbase slghsymbol \ diff --git a/pypcode/sleigh/address.cc b/pypcode/sleigh/address.cc index 9e8039d4..3a3d33a2 100644 --- a/pypcode/sleigh/address.cc +++ b/pypcode/sleigh/address.cc @@ -627,6 +627,246 @@ void RangeList::decode(Decoder &decoder) decoder.closeElement(elemId); } +BitRange::BitRange(const BitRange &op2,int4 off,int4 sz) + +{ + byteOffset = off; + byteSize = sz; + numBits = op2.numBits; + isBigEndian = op2.isBigEndian; + leastSigBit = translateLSB(op2); +} + +/// Both the byte container and the bit range are compared and must be equal to return 0. +/// \param op2 is the other bit range to compare with +/// \return -1, 0, or 1 to establish ordering the two ranges +int4 BitRange::compare(const BitRange &op2) const + +{ + if (byteOffset != op2.byteOffset) + return (byteOffset < op2.byteOffset) ? -1:1; + if (byteSize != op2.byteSize) + return (byteSize < op2.byteSize) ? -1 : 1; + if (leastSigBit != op2.leastSigBit) + return (leastSigBit < op2.leastSigBit) ? -1:1; + if (numBits != op2.numBits) + return (numBits < op2.numBits) ? -1:1; + return 0; +} + +/// The returned result is directly comparable with \b leastSigBit for determining order/overlap. +/// \param op2 is the other BitRange to translate into \b this frame +/// \return the translated value of op2.leastSigBit +int4 BitRange::translateLSB(const BitRange &op2) const + +{ + int4 op2Sig = op2.leastSigBit; + if (isBigEndian) { + int4 thisPos = byteOffset + byteSize; + int4 op2Pos = op2.byteOffset + op2.byteSize; + op2Sig += 8 * (thisPos - op2Pos); + } + else { + op2Sig += 8 * (op2.byteOffset - byteOffset); + } + return op2Sig; +} + +/// Return: +/// - -1 if \b this should come before (no intersection) +/// - 0 if \b this and op2 are the same bitrange +/// - 1 if \b this should come after (no intersection) +/// - 2 if \b this is contained in op2 +/// - 3 if op2 is contained in \b this +/// - 4 if partial overlap +/// +/// \param op2 is the other range to compare +/// \return the intersection code +int4 BitRange::overlapTest(const BitRange &op2) const + +{ + int4 op2Sig = translateLSB(op2); + int4 thisMost = leastSigBit + numBits; + int4 op2Most = op2Sig + op2.numBits; + if (isBigEndian) { + if (leastSigBit >= op2Most) return -1; + if (op2Sig >= thisMost) return 1; + } + else { + if (thisMost <= op2Sig) return -1; + if (op2Most <= leastSigBit) return 1; + } + // Reaching here we have some kind of intersection + if (leastSigBit == op2Sig && thisMost == op2Most) return 0; + if (op2Sig <= leastSigBit && op2Most >= thisMost) return 2; /// this contained in op2 + if (leastSigBit <= op2Sig && thisMost >= op2Most) return 3; /// op2 contained in this + return 4; +} + +/// The byte container for \b this does not change only \b leastSigBit and \b numBits. +/// If the intersection is empty, \b numBits is set to 0. +/// \param op2 is the bit range to intersect with \b this. +void BitRange::intersection(const BitRange &op2) + +{ + int4 op2Sig = translateLSB(op2); + int4 op2Most = op2Sig + op2.numBits; + int4 thisMost = leastSigBit + numBits; + if (op2Sig > leastSigBit) { + numBits -= (op2Sig - leastSigBit); + leastSigBit = op2Sig; + } + if (op2Most < thisMost) { + numBits -= (thisMost - op2Most); + } + if (numBits < 0) { + leastSigBit = 0; + numBits = 0; + } +} + +/// The range of bits is intersected with the 1-bits of the mask. The resulting +/// range is the minimal cover of the bits in the intersection. +/// \param mask is the mask to intersect with +void BitRange::intersectMask(uintb mask) + +{ + mask &= getMask(); + if (mask == 0) { + leastSigBit = 0; + numBits = 0; + return; + } + int4 newLeastSig = leastsigbit_set(mask); + int4 newMostSig = mostsigbit_set(mask) + 1; + int4 thisMost = leastSigBit + numBits; + if (newLeastSig > leastSigBit) { + numBits -= (newLeastSig - leastSigBit); + leastSigBit = newLeastSig; + } + if (newMostSig < thisMost) { + numBits -= (thisMost - newMostSig); + } +} + +/// The bit range is shifted to the left by the given amount. +/// \param leftShiftAmount is the amount to shift the range by +void BitRange::shift(int4 leftShiftAmount) + +{ + leastSigBit += leftShiftAmount; + int4 most = leastSigBit + numBits; + if (leastSigBit < 0) { + numBits += leastSigBit; + leastSigBit = 0; + } + else if (most > byteSize * 8) { + numBits -= (most - byteSize * 8); + } + if (numBits < 0) { + leastSigBit = 0; + numBits = 0; + } +} + +/// The number of bits may be affected. +/// \param num is the number of bytes to truncate +void BitRange::truncateMostSigBytes(int4 num) + +{ + if (isBigEndian) { + byteOffset += num; + } + byteSize -= num; + int4 maxOffset = leastSigBit + numBits; + if (maxOffset > byteSize * 8) + numBits -= (maxOffset - byteSize * 8); + if (numBits < 0) + numBits = 0; +} + +/// \param num is the number of bytes to truncate +void BitRange::truncateLeastSigBytes(int4 num) + +{ + if (!isBigEndian) + byteOffset += num; + byteSize -= num; + leastSigBit -= num * 8; + if (leastSigBit < 0) { + numBits = numBits + leastSigBit; + leastSigBit = 0; + if (numBits < 0) + numBits = 0; + } +} + +/// Only the container is affected, the bit range itself does not change. +/// \param num is the number of bytes to add +void BitRange::extendBytes(int4 num) + +{ + if (isBigEndian) + byteOffset -= num; + byteSize += num; +} + +/// The bit-mask is aligned with the byte container. +/// \return the bit-mask describing \b this range +uintb BitRange::getMask(void) const + +{ + uintb res; + if (numBits >= sizeof(uintb)*8) + res = 0; + else { + res = 1; + res <<= numBits; + } + res -= 1; + res <<= leastSigBit; + return res; +} + +/// \return \b true if the beginning and end of the range fall on byte boundaries +bool BitRange::isByteRange(void) const + +{ + if ((numBits & 7) != 0) return false; + if ((leastSigBit & 7) != 0) return false; + return true; +} + +/// \return \b true if the most significant bit of the field and the container are the same +bool BitRange::isMostSignificant(void) const + +{ + return 8*byteSize == leastSigBit + numBits; +} + +void BitRange::minimizeContainer(void) + +{ + int4 trunc = leastSigBit / 8; + if (isBigEndian) + byteSize -= trunc; + else + byteOffset += trunc; + leastSigBit &= 7; + int4 num = byteSize - ((leastSigBit + numBits + 7) / 8); + if (num > 0) { + if (isBigEndian) + byteOffset += num; + byteSize -= num; + } +} + +void BitRange::expandToMost(void) + +{ + numBits = 8*byteSize - leastSigBit; // Increase number of bits to maximum that still fits +} + #ifdef UINTB4 uintb uintbmasks[9] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; #else @@ -675,6 +915,22 @@ uintb sign_extend(uintb in,int4 sizein,int4 sizeout) return res; } +/// \param val is the value to extend +/// \param numbits is the number of bits in the value +/// \param size is the integer size in bytes +/// \return the extended value +uintb extend_signbit(uintb val,int4 numbits,int4 size) + +{ + if (numbits < size * 8) { + int4 sa = 8*sizeof(intb) - numbits; + intb sval = val; + val = (sval << sa) >> sa; + val &= calc_mask(size); + } + return val; +} + /// Swap the least significant \b size bytes in \b val /// \param val is a reference to the value to swap /// \param size is the number of bytes to swap diff --git a/pypcode/sleigh/address.hh b/pypcode/sleigh/address.hh index 45144daf..510432e5 100644 --- a/pypcode/sleigh/address.hh +++ b/pypcode/sleigh/address.hh @@ -253,6 +253,37 @@ public: void decode(Decoder &decoder); ///< Decode \b this RangeList from a \ element }; +/// \brief An endian aware range of bits contained in a contiguous set of bytes +class BitRange { +public: + int4 byteOffset; ///< Byte offset of the region containing the range + int4 byteSize; ///< Size of the region in bytes + int4 leastSigBit; ///< Least significant bit of the bit-range within its region + int4 numBits; ///< Number of bits in the range + bool isBigEndian; ///< Is the underlying encoding big endian + BitRange(void) { byteOffset = -1; byteSize = -1; leastSigBit = -1; numBits = -1; isBigEndian = false; } ///< Construct \e undefined range + BitRange(int4 bOff,int4 bSize,bool bigEndian) { + byteOffset = bOff; byteSize = bSize; leastSigBit = 0; numBits = bSize * 8; isBigEndian = bigEndian; } ///< Construct byte range + BitRange(const BitRange &op2,int4 off,int4 sz); ///< Constructor, copy range into new container + BitRange(int4 bOff,int4 bSize,int4 least,int4 num,bool bigEndian) { byteOffset = bOff; byteSize = bSize; leastSigBit = least; + numBits = num; isBigEndian = bigEndian; } ///< Constructor + bool empty(void) const { return (numBits <= 0); } ///< Return \b true if \b this is an empty bit range (zero bits) + int4 compare(const BitRange &op2) const; ///< Compare \b this with another as containers + int4 translateLSB(const BitRange &op2) const; ///< Translate the \b leastSigBit of the given range into \b this reference frame + int4 overlapTest(const BitRange &op2) const; ///< Characterize the type of overlap between \b this and another range + void intersection(const BitRange &op2); ///< Replace \b this with the intersection of \b this with another BitRange + void intersectMask(uintb mask); ///< Restrict \b this with a mask that lines up with the container + void shift(int4 leftShiftAmount); ///< Replace \b this with the shifted range + void truncateMostSigBytes(int4 num); ///< Truncate the most significant bytes in the byte container + void truncateLeastSigBytes(int4 num); ///< Truncate the least significant bytes in the byte container + void extendBytes(int4 num); ///< Add most significant bytes to the container + uintb getMask(void) const; ///< Get mask representing \b this range + bool isByteRange(void) const; ///< Return \b true if \b this bit range is also a byte range + bool isMostSignificant(void) const; ///< Return \b true if the bit range occupies the most significant bits of the container + void minimizeContainer(void); ///< Shrink the container to fit the bit range + void expandToMost(void); ///< Expand the bitrange until it includes the most significant bits of the container +}; + /// Precalculated masks indexed by size extern uintb uintbmasks[]; @@ -498,6 +529,18 @@ inline bool Range::contains(const Address &addr) const { /// \return a value appropriate for masking off the first \e size bytes inline uintb calc_mask(int4 size) { return uintbmasks[((uint4)size) < 8 ? size : 8]; } +/// \param size of the integer in bytes +/// \return largest unsigned integer value for given size +inline uintb calc_uint_max(int4 size) { return calc_mask(size); } + +/// \param size of the integer in bytes +/// \return largest signed integer value for given size +inline uintb calc_int_max(int4 size) { return calc_mask(size) >> 1; } + +/// \param size of the integer in bytes +/// \return smallest signed integer value for given size +inline uintb calc_int_min(int4 size) { return (uintb)1 << (size * 8 - 1); } + /// Perform a CPUI_INT_RIGHT on the given val /// \param val is the value to shift /// \param sa is the number of bits to shift @@ -565,6 +608,7 @@ extern bool signbit_negative(uintb val,int4 size); ///< Return true if the sign- extern uintb calc_mask(int4 size); ///< Calculate a mask for a given byte size extern uintb uintb_negate(uintb in,int4 size); ///< Negate the \e sized value extern uintb sign_extend(uintb in,int4 sizein,int4 sizeout); ///< Sign-extend a value between two byte sizes +extern uintb extend_signbit(uintb val,int4 numbits,int4 size); ///< Extend a signed value of given number of bits to a full integer extern void byte_swap(intb &val,int4 size); ///< Swap bytes in the given value diff --git a/pypcode/sleigh/error.hh b/pypcode/sleigh/error.hh index 1709ef7a..4f8e185d 100644 --- a/pypcode/sleigh/error.hh +++ b/pypcode/sleigh/error.hh @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,7 @@ using std::map; using std::set; using std::list; using std::vector; +using std::deque; using std::pair; using std::make_pair; using std::ostream; diff --git a/pypcode/sleigh/marshal.cc b/pypcode/sleigh/marshal.cc index 1c138774..f1a43d86 100644 --- a/pypcode/sleigh/marshal.cc +++ b/pypcode/sleigh/marshal.cc @@ -1268,6 +1268,6 @@ ElementId ELEM_VAL = ElementId("val",8); ElementId ELEM_VALUE = ElementId("value",9); ElementId ELEM_VOID = ElementId("void",10); -ElementId ELEM_UNKNOWN = ElementId("XMLunknown",289); // Number serves as next open index +ElementId ELEM_UNKNOWN = ElementId("XMLunknown",290); // Number serves as next open index } // End namespace ghidra diff --git a/pypcode/sleigh/opbehavior.cc b/pypcode/sleigh/opbehavior.cc index ab23e94b..2d989384 100644 --- a/pypcode/sleigh/opbehavior.cc +++ b/pypcode/sleigh/opbehavior.cc @@ -102,9 +102,10 @@ void OpBehavior::registerInstructions(vector &inst,const Translate inst[CPUI_CPOOLREF] = new OpBehavior(CPUI_CPOOLREF,false,true); inst[CPUI_NEW] = new OpBehavior(CPUI_NEW,false,true); inst[CPUI_INSERT] = new OpBehavior(CPUI_INSERT,false); - inst[CPUI_EXTRACT] = new OpBehavior(CPUI_EXTRACT,false); + inst[CPUI_ZPULL] = new OpBehavior(CPUI_ZPULL,false); inst[CPUI_POPCOUNT] = new OpBehaviorPopcount(); inst[CPUI_LZCOUNT] = new OpBehaviorLzcount(); + inst[CPUI_SPULL] = new OpBehavior(CPUI_SPULL,false); } /// \param sizeout is the size of the output in bytes diff --git a/pypcode/sleigh/opcodes.hh b/pypcode/sleigh/opcodes.hh index be25b55e..ab157b6f 100644 --- a/pypcode/sleigh/opcodes.hh +++ b/pypcode/sleigh/opcodes.hh @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -126,11 +126,12 @@ enum OpCode { CPUI_CPOOLREF = 68, ///< Recover a value from the \e constant \e pool CPUI_NEW = 69, ///< Allocate a new object (new) CPUI_INSERT = 70, ///< Insert a bit-range - CPUI_EXTRACT = 71, ///< Extract a bit-range + CPUI_ZPULL = 71, ///< Extract an unsigned bit-range CPUI_POPCOUNT = 72, ///< Count the 1-bits CPUI_LZCOUNT = 73, ///< Count the leading 0-bits + CPUI_SPULL = 74, ///< Extract a signed bit-range - CPUI_MAX = 74 ///< Value indicating the end of the op-code values + CPUI_MAX = 75 ///< Value indicating the end of the op-code values }; extern const char *get_opname(OpCode opc); ///< Convert an OpCode to the name as a string diff --git a/pypcode/sleigh/pcodeparse.cc b/pypcode/sleigh/pcodeparse.cc index db003130..61defeb2 100644 --- a/pypcode/sleigh/pcodeparse.cc +++ b/pypcode/sleigh/pcodeparse.cc @@ -1,23 +1,8 @@ -/* ### - * IP: GHIDRA - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* A Bison parser, made by GNU Bison 3.5.1. */ +/* A Bison parser, made by GNU Bison 3.8.2. */ /* Bison implementation for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2020 Free Software Foundation, + Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2021 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify @@ -31,7 +16,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License - along with this program. If not, see . */ + along with this program. If not, see . */ /* As a special exception, you may create a larger work that contains part or all of the Bison parser skeleton and distribute that work @@ -49,6 +34,10 @@ /* C LALR(1) parser skeleton written by Richard Stallman, by simplifying the original so-called "semantic" parser. */ +/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, + especially those whose name start with YY_ or yy_. They are + private implementation details that can be changed or removed. */ + /* All symbols defined below should begin with yy or YY, to avoid infringing on user name space. This should be done even for local variables, as they might otherwise be expanded by user macros. @@ -56,14 +45,11 @@ define necessary library symbols; they are noted "INFRINGES ON USER NAME SPACE" below. */ -/* Undocumented macros, especially those whose name start with YY_, - are private implementation details. Do not rely on them. */ - -/* Identify Bison output. */ -#define YYBISON 1 +/* Identify Bison output, and Bison version. */ +#define YYBISON 30802 -/* Bison version. */ -#define YYBISON_VERSION "3.5.1" +/* Bison version string. */ +#define YYBISON_VERSION "3.8.2" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -121,14 +107,6 @@ extern int pcodeerror(const char *str ); # endif # endif -/* Enabling verbose error messages. */ -#ifdef YYERROR_VERBOSE -# undef YYERROR_VERBOSE -# define YYERROR_VERBOSE 1 -#else -# define YYERROR_VERBOSE 0 -#endif - /* Debug traces. */ #ifndef PCODEDEBUG @@ -146,69 +124,74 @@ extern int pcodeerror(const char *str ); extern int pcodedebug; #endif -/* Token type. */ +/* Token kinds. */ #ifndef PCODETOKENTYPE # define PCODETOKENTYPE enum pcodetokentype { - OP_BOOL_OR = 258, - OP_BOOL_AND = 259, - OP_BOOL_XOR = 260, - OP_EQUAL = 261, - OP_NOTEQUAL = 262, - OP_FEQUAL = 263, - OP_FNOTEQUAL = 264, - OP_GREATEQUAL = 265, - OP_LESSEQUAL = 266, - OP_SLESS = 267, - OP_SGREATEQUAL = 268, - OP_SLESSEQUAL = 269, - OP_SGREAT = 270, - OP_FLESS = 271, - OP_FGREAT = 272, - OP_FLESSEQUAL = 273, - OP_FGREATEQUAL = 274, - OP_LEFT = 275, - OP_RIGHT = 276, - OP_SRIGHT = 277, - OP_FADD = 278, - OP_FSUB = 279, - OP_SDIV = 280, - OP_SREM = 281, - OP_FMULT = 282, - OP_FDIV = 283, - OP_ZEXT = 284, - OP_CARRY = 285, - OP_BORROW = 286, - OP_SEXT = 287, - OP_SCARRY = 288, - OP_SBORROW = 289, - OP_NAN = 290, - OP_ABS = 291, - OP_SQRT = 292, - OP_CEIL = 293, - OP_FLOOR = 294, - OP_ROUND = 295, - OP_INT2FLOAT = 296, - OP_FLOAT2FLOAT = 297, - OP_TRUNC = 298, - OP_NEW = 299, - BADINTEGER = 300, - GOTO_KEY = 301, - CALL_KEY = 302, - RETURN_KEY = 303, - IF_KEY = 304, - ENDOFSTREAM = 305, - LOCAL_KEY = 306, - INTEGER = 307, - STRING = 308, - SPACESYM = 309, - USEROPSYM = 310, - VARSYM = 311, - OPERANDSYM = 312, - JUMPSYM = 313, - LABELSYM = 314 + PCODEEMPTY = -2, + PCODEEOF = 0, /* "end of file" */ + PCODEerror = 256, /* error */ + PCODEUNDEF = 257, /* "invalid token" */ + OP_BOOL_OR = 258, /* OP_BOOL_OR */ + OP_BOOL_AND = 259, /* OP_BOOL_AND */ + OP_BOOL_XOR = 260, /* OP_BOOL_XOR */ + OP_EQUAL = 261, /* OP_EQUAL */ + OP_NOTEQUAL = 262, /* OP_NOTEQUAL */ + OP_FEQUAL = 263, /* OP_FEQUAL */ + OP_FNOTEQUAL = 264, /* OP_FNOTEQUAL */ + OP_GREATEQUAL = 265, /* OP_GREATEQUAL */ + OP_LESSEQUAL = 266, /* OP_LESSEQUAL */ + OP_SLESS = 267, /* OP_SLESS */ + OP_SGREATEQUAL = 268, /* OP_SGREATEQUAL */ + OP_SLESSEQUAL = 269, /* OP_SLESSEQUAL */ + OP_SGREAT = 270, /* OP_SGREAT */ + OP_FLESS = 271, /* OP_FLESS */ + OP_FGREAT = 272, /* OP_FGREAT */ + OP_FLESSEQUAL = 273, /* OP_FLESSEQUAL */ + OP_FGREATEQUAL = 274, /* OP_FGREATEQUAL */ + OP_LEFT = 275, /* OP_LEFT */ + OP_RIGHT = 276, /* OP_RIGHT */ + OP_SRIGHT = 277, /* OP_SRIGHT */ + OP_FADD = 278, /* OP_FADD */ + OP_FSUB = 279, /* OP_FSUB */ + OP_SDIV = 280, /* OP_SDIV */ + OP_SREM = 281, /* OP_SREM */ + OP_FMULT = 282, /* OP_FMULT */ + OP_FDIV = 283, /* OP_FDIV */ + OP_ZEXT = 284, /* OP_ZEXT */ + OP_CARRY = 285, /* OP_CARRY */ + OP_BORROW = 286, /* OP_BORROW */ + OP_SEXT = 287, /* OP_SEXT */ + OP_SCARRY = 288, /* OP_SCARRY */ + OP_SBORROW = 289, /* OP_SBORROW */ + OP_NAN = 290, /* OP_NAN */ + OP_ABS = 291, /* OP_ABS */ + OP_SQRT = 292, /* OP_SQRT */ + OP_CEIL = 293, /* OP_CEIL */ + OP_FLOOR = 294, /* OP_FLOOR */ + OP_ROUND = 295, /* OP_ROUND */ + OP_INT2FLOAT = 296, /* OP_INT2FLOAT */ + OP_FLOAT2FLOAT = 297, /* OP_FLOAT2FLOAT */ + OP_TRUNC = 298, /* OP_TRUNC */ + OP_NEW = 299, /* OP_NEW */ + BADINTEGER = 300, /* BADINTEGER */ + GOTO_KEY = 301, /* GOTO_KEY */ + CALL_KEY = 302, /* CALL_KEY */ + RETURN_KEY = 303, /* RETURN_KEY */ + IF_KEY = 304, /* IF_KEY */ + ENDOFSTREAM = 305, /* ENDOFSTREAM */ + LOCAL_KEY = 306, /* LOCAL_KEY */ + INTEGER = 307, /* INTEGER */ + STRING = 308, /* STRING */ + SPACESYM = 309, /* SPACESYM */ + USEROPSYM = 310, /* USEROPSYM */ + VARSYM = 311, /* VARSYM */ + OPERANDSYM = 312, /* OPERANDSYM */ + JUMPSYM = 313, /* JUMPSYM */ + LABELSYM = 314 /* LABELSYM */ }; + typedef enum pcodetokentype pcodetoken_kind_t; #endif /* Value type. */ @@ -242,10 +225,112 @@ typedef union PCODESTYPE PCODESTYPE; extern PCODESTYPE pcodelval; + int pcodeparse (void); +/* Symbol kind. */ +enum yysymbol_kind_t +{ + YYSYMBOL_YYEMPTY = -2, + YYSYMBOL_YYEOF = 0, /* "end of file" */ + YYSYMBOL_YYerror = 1, /* error */ + YYSYMBOL_YYUNDEF = 2, /* "invalid token" */ + YYSYMBOL_OP_BOOL_OR = 3, /* OP_BOOL_OR */ + YYSYMBOL_OP_BOOL_AND = 4, /* OP_BOOL_AND */ + YYSYMBOL_OP_BOOL_XOR = 5, /* OP_BOOL_XOR */ + YYSYMBOL_6_ = 6, /* '|' */ + YYSYMBOL_7_ = 7, /* ';' */ + YYSYMBOL_8_ = 8, /* '^' */ + YYSYMBOL_9_ = 9, /* '&' */ + YYSYMBOL_OP_EQUAL = 10, /* OP_EQUAL */ + YYSYMBOL_OP_NOTEQUAL = 11, /* OP_NOTEQUAL */ + YYSYMBOL_OP_FEQUAL = 12, /* OP_FEQUAL */ + YYSYMBOL_OP_FNOTEQUAL = 13, /* OP_FNOTEQUAL */ + YYSYMBOL_14_ = 14, /* '<' */ + YYSYMBOL_15_ = 15, /* '>' */ + YYSYMBOL_OP_GREATEQUAL = 16, /* OP_GREATEQUAL */ + YYSYMBOL_OP_LESSEQUAL = 17, /* OP_LESSEQUAL */ + YYSYMBOL_OP_SLESS = 18, /* OP_SLESS */ + YYSYMBOL_OP_SGREATEQUAL = 19, /* OP_SGREATEQUAL */ + YYSYMBOL_OP_SLESSEQUAL = 20, /* OP_SLESSEQUAL */ + YYSYMBOL_OP_SGREAT = 21, /* OP_SGREAT */ + YYSYMBOL_OP_FLESS = 22, /* OP_FLESS */ + YYSYMBOL_OP_FGREAT = 23, /* OP_FGREAT */ + YYSYMBOL_OP_FLESSEQUAL = 24, /* OP_FLESSEQUAL */ + YYSYMBOL_OP_FGREATEQUAL = 25, /* OP_FGREATEQUAL */ + YYSYMBOL_OP_LEFT = 26, /* OP_LEFT */ + YYSYMBOL_OP_RIGHT = 27, /* OP_RIGHT */ + YYSYMBOL_OP_SRIGHT = 28, /* OP_SRIGHT */ + YYSYMBOL_29_ = 29, /* '+' */ + YYSYMBOL_30_ = 30, /* '-' */ + YYSYMBOL_OP_FADD = 31, /* OP_FADD */ + YYSYMBOL_OP_FSUB = 32, /* OP_FSUB */ + YYSYMBOL_33_ = 33, /* '*' */ + YYSYMBOL_34_ = 34, /* '/' */ + YYSYMBOL_35_ = 35, /* '%' */ + YYSYMBOL_OP_SDIV = 36, /* OP_SDIV */ + YYSYMBOL_OP_SREM = 37, /* OP_SREM */ + YYSYMBOL_OP_FMULT = 38, /* OP_FMULT */ + YYSYMBOL_OP_FDIV = 39, /* OP_FDIV */ + YYSYMBOL_40_ = 40, /* '!' */ + YYSYMBOL_41_ = 41, /* '~' */ + YYSYMBOL_OP_ZEXT = 42, /* OP_ZEXT */ + YYSYMBOL_OP_CARRY = 43, /* OP_CARRY */ + YYSYMBOL_OP_BORROW = 44, /* OP_BORROW */ + YYSYMBOL_OP_SEXT = 45, /* OP_SEXT */ + YYSYMBOL_OP_SCARRY = 46, /* OP_SCARRY */ + YYSYMBOL_OP_SBORROW = 47, /* OP_SBORROW */ + YYSYMBOL_OP_NAN = 48, /* OP_NAN */ + YYSYMBOL_OP_ABS = 49, /* OP_ABS */ + YYSYMBOL_OP_SQRT = 50, /* OP_SQRT */ + YYSYMBOL_OP_CEIL = 51, /* OP_CEIL */ + YYSYMBOL_OP_FLOOR = 52, /* OP_FLOOR */ + YYSYMBOL_OP_ROUND = 53, /* OP_ROUND */ + YYSYMBOL_OP_INT2FLOAT = 54, /* OP_INT2FLOAT */ + YYSYMBOL_OP_FLOAT2FLOAT = 55, /* OP_FLOAT2FLOAT */ + YYSYMBOL_OP_TRUNC = 56, /* OP_TRUNC */ + YYSYMBOL_OP_NEW = 57, /* OP_NEW */ + YYSYMBOL_BADINTEGER = 58, /* BADINTEGER */ + YYSYMBOL_GOTO_KEY = 59, /* GOTO_KEY */ + YYSYMBOL_CALL_KEY = 60, /* CALL_KEY */ + YYSYMBOL_RETURN_KEY = 61, /* RETURN_KEY */ + YYSYMBOL_IF_KEY = 62, /* IF_KEY */ + YYSYMBOL_ENDOFSTREAM = 63, /* ENDOFSTREAM */ + YYSYMBOL_LOCAL_KEY = 64, /* LOCAL_KEY */ + YYSYMBOL_INTEGER = 65, /* INTEGER */ + YYSYMBOL_STRING = 66, /* STRING */ + YYSYMBOL_SPACESYM = 67, /* SPACESYM */ + YYSYMBOL_USEROPSYM = 68, /* USEROPSYM */ + YYSYMBOL_VARSYM = 69, /* VARSYM */ + YYSYMBOL_OPERANDSYM = 70, /* OPERANDSYM */ + YYSYMBOL_JUMPSYM = 71, /* JUMPSYM */ + YYSYMBOL_LABELSYM = 72, /* LABELSYM */ + YYSYMBOL_73_ = 73, /* ':' */ + YYSYMBOL_74_ = 74, /* '=' */ + YYSYMBOL_75_ = 75, /* '(' */ + YYSYMBOL_76_ = 76, /* ')' */ + YYSYMBOL_77_ = 77, /* '[' */ + YYSYMBOL_78_ = 78, /* ',' */ + YYSYMBOL_79_ = 79, /* ']' */ + YYSYMBOL_YYACCEPT = 80, /* $accept */ + YYSYMBOL_rtl = 81, /* rtl */ + YYSYMBOL_rtlmid = 82, /* rtlmid */ + YYSYMBOL_statement = 83, /* statement */ + YYSYMBOL_expr = 84, /* expr */ + YYSYMBOL_sizedstar = 85, /* sizedstar */ + YYSYMBOL_jumpdest = 86, /* jumpdest */ + YYSYMBOL_varnode = 87, /* varnode */ + YYSYMBOL_integervarnode = 88, /* integervarnode */ + YYSYMBOL_lhsvarnode = 89, /* lhsvarnode */ + YYSYMBOL_label = 90, /* label */ + YYSYMBOL_specificsymbol = 91, /* specificsymbol */ + YYSYMBOL_paramlist = 92 /* paramlist */ +}; +typedef enum yysymbol_kind_t yysymbol_kind_t; + + #ifdef short @@ -285,6 +370,18 @@ typedef int_least16_t yytype_int16; typedef short yytype_int16; #endif +/* Work around bug in HP-UX 11.23, which defines these macros + incorrectly for preprocessor constants. This workaround can likely + be removed in 2023, as HPE has promised support for HP-UX 11.23 + (aka HP-UX 11i v2) only through the end of 2022; see Table 2 of + . */ +#ifdef __hpux +# undef UINT_LEAST8_MAX +# undef UINT_LEAST16_MAX +# define UINT_LEAST8_MAX 255 +# define UINT_LEAST16_MAX 65535 +#endif + #if defined __UINT_LEAST8_MAX__ && __UINT_LEAST8_MAX__ <= __INT_MAX__ typedef __UINT_LEAST8_TYPE__ yytype_uint8; #elif (!defined __UINT_LEAST8_MAX__ && defined YY_STDINT_H \ @@ -344,6 +441,7 @@ typedef int yytype_uint16; #define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X)) + /* Stored state numbers (used for stacks). */ typedef yytype_int16 yy_state_t; @@ -362,6 +460,7 @@ typedef int yy_state_fast_t; # endif #endif + #ifndef YY_ATTRIBUTE_PURE # if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__) # define YY_ATTRIBUTE_PURE __attribute__ ((__pure__)) @@ -380,17 +479,23 @@ typedef int yy_state_fast_t; /* Suppress unused-variable warnings by "using" E. */ #if ! defined lint || defined __GNUC__ -# define YYUSE(E) ((void) (E)) +# define YY_USE(E) ((void) (E)) #else -# define YYUSE(E) /* empty */ +# define YY_USE(E) /* empty */ #endif -#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ /* Suppress an incorrect diagnostic about yylval being uninitialized. */ -# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ +#if defined __GNUC__ && ! defined __ICC && 406 <= __GNUC__ * 100 + __GNUC_MINOR__ +# if __GNUC__ * 100 + __GNUC_MINOR__ < 407 +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ + _Pragma ("GCC diagnostic push") \ + _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") +# else +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ _Pragma ("GCC diagnostic push") \ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") \ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") +# endif # define YY_IGNORE_MAYBE_UNINITIALIZED_END \ _Pragma ("GCC diagnostic pop") #else @@ -419,7 +524,7 @@ typedef int yy_state_fast_t; #define YY_ASSERT(E) ((void) (0 && (E))) -#if ! defined yyoverflow || YYERROR_VERBOSE +#if !defined yyoverflow /* The parser invokes alloca or malloc; define the necessary symbols. */ @@ -484,8 +589,7 @@ void free (void *); /* INFRINGES ON USER NAME SPACE */ # endif # endif # endif -#endif /* ! defined yyoverflow || YYERROR_VERBOSE */ - +#endif /* !defined yyoverflow */ #if (! defined yyoverflow \ && (! defined __cplusplus \ @@ -561,14 +665,16 @@ union yyalloc /* YYNSTATES -- Number of states. */ #define YYNSTATES 294 -#define YYUNDEFTOK 2 +/* YYMAXUTOK -- Last valid token kind. */ #define YYMAXUTOK 314 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM as returned by yylex, with out-of-bounds checking. */ -#define YYTRANSLATE(YYX) \ - (0 <= (YYX) && (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) +#define YYTRANSLATE(YYX) \ + (0 <= (YYX) && (YYX) <= YYMAXUTOK \ + ? YY_CAST (yysymbol_kind_t, yytranslate[YYX]) \ + : YYSYMBOL_YYUNDEF) /* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM as returned by yylex. */ @@ -609,7 +715,7 @@ static const yytype_int8 yytranslate[] = }; #if PCODEDEBUG - /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ +/* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { 0, 99, 99, 101, 102, 103, 104, 106, 107, 108, @@ -627,45 +733,42 @@ static const yytype_uint8 yyrline[] = }; #endif -#if PCODEDEBUG || YYERROR_VERBOSE || 0 +/** Accessing symbol of state STATE. */ +#define YY_ACCESSING_SYMBOL(State) YY_CAST (yysymbol_kind_t, yystos[State]) + +#if PCODEDEBUG || 0 +/* The user-facing name of the symbol whose (internal) number is + YYSYMBOL. No bounds checking. */ +static const char *yysymbol_name (yysymbol_kind_t yysymbol) YY_ATTRIBUTE_UNUSED; + /* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM. First, the terminals, then, starting at YYNTOKENS, nonterminals. */ static const char *const yytname[] = { - "$end", "error", "$undefined", "OP_BOOL_OR", "OP_BOOL_AND", - "OP_BOOL_XOR", "'|'", "';'", "'^'", "'&'", "OP_EQUAL", "OP_NOTEQUAL", - "OP_FEQUAL", "OP_FNOTEQUAL", "'<'", "'>'", "OP_GREATEQUAL", - "OP_LESSEQUAL", "OP_SLESS", "OP_SGREATEQUAL", "OP_SLESSEQUAL", - "OP_SGREAT", "OP_FLESS", "OP_FGREAT", "OP_FLESSEQUAL", "OP_FGREATEQUAL", - "OP_LEFT", "OP_RIGHT", "OP_SRIGHT", "'+'", "'-'", "OP_FADD", "OP_FSUB", - "'*'", "'/'", "'%'", "OP_SDIV", "OP_SREM", "OP_FMULT", "OP_FDIV", "'!'", - "'~'", "OP_ZEXT", "OP_CARRY", "OP_BORROW", "OP_SEXT", "OP_SCARRY", - "OP_SBORROW", "OP_NAN", "OP_ABS", "OP_SQRT", "OP_CEIL", "OP_FLOOR", - "OP_ROUND", "OP_INT2FLOAT", "OP_FLOAT2FLOAT", "OP_TRUNC", "OP_NEW", - "BADINTEGER", "GOTO_KEY", "CALL_KEY", "RETURN_KEY", "IF_KEY", - "ENDOFSTREAM", "LOCAL_KEY", "INTEGER", "STRING", "SPACESYM", "USEROPSYM", - "VARSYM", "OPERANDSYM", "JUMPSYM", "LABELSYM", "':'", "'='", "'('", - "')'", "'['", "','", "']'", "$accept", "rtl", "rtlmid", "statement", - "expr", "sizedstar", "jumpdest", "varnode", "integervarnode", - "lhsvarnode", "label", "specificsymbol", "paramlist", YY_NULLPTR + "\"end of file\"", "error", "\"invalid token\"", "OP_BOOL_OR", + "OP_BOOL_AND", "OP_BOOL_XOR", "'|'", "';'", "'^'", "'&'", "OP_EQUAL", + "OP_NOTEQUAL", "OP_FEQUAL", "OP_FNOTEQUAL", "'<'", "'>'", + "OP_GREATEQUAL", "OP_LESSEQUAL", "OP_SLESS", "OP_SGREATEQUAL", + "OP_SLESSEQUAL", "OP_SGREAT", "OP_FLESS", "OP_FGREAT", "OP_FLESSEQUAL", + "OP_FGREATEQUAL", "OP_LEFT", "OP_RIGHT", "OP_SRIGHT", "'+'", "'-'", + "OP_FADD", "OP_FSUB", "'*'", "'/'", "'%'", "OP_SDIV", "OP_SREM", + "OP_FMULT", "OP_FDIV", "'!'", "'~'", "OP_ZEXT", "OP_CARRY", "OP_BORROW", + "OP_SEXT", "OP_SCARRY", "OP_SBORROW", "OP_NAN", "OP_ABS", "OP_SQRT", + "OP_CEIL", "OP_FLOOR", "OP_ROUND", "OP_INT2FLOAT", "OP_FLOAT2FLOAT", + "OP_TRUNC", "OP_NEW", "BADINTEGER", "GOTO_KEY", "CALL_KEY", "RETURN_KEY", + "IF_KEY", "ENDOFSTREAM", "LOCAL_KEY", "INTEGER", "STRING", "SPACESYM", + "USEROPSYM", "VARSYM", "OPERANDSYM", "JUMPSYM", "LABELSYM", "':'", "'='", + "'('", "')'", "'['", "','", "']'", "$accept", "rtl", "rtlmid", + "statement", "expr", "sizedstar", "jumpdest", "varnode", + "integervarnode", "lhsvarnode", "label", "specificsymbol", "paramlist", YY_NULLPTR }; -#endif -# ifdef YYPRINT -/* YYTOKNUM[NUM] -- (External) token number corresponding to the - (internal) symbol number NUM (which must be that of a token). */ -static const yytype_int16 yytoknum[] = +static const char * +yysymbol_name (yysymbol_kind_t yysymbol) { - 0, 256, 257, 258, 259, 260, 124, 59, 94, 38, - 261, 262, 263, 264, 60, 62, 265, 266, 267, 268, - 269, 270, 271, 272, 273, 274, 275, 276, 277, 43, - 45, 278, 279, 42, 47, 37, 280, 281, 282, 283, - 33, 126, 284, 285, 286, 287, 288, 289, 290, 291, - 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, - 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, - 312, 313, 314, 58, 61, 40, 41, 91, 44, 93 -}; -# endif + return yytname[yysymbol]; +} +#endif #define YYPACT_NINF (-65) @@ -677,8 +780,8 @@ static const yytype_int16 yytoknum[] = #define yytable_value_is_error(Yyn) \ ((Yyn) == YYTABLE_NINF) - /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing - STATE-NUM. */ +/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing + STATE-NUM. */ static const yytype_int16 yypact[] = { -65, 32, 1720, -65, 308, -45, -23, -65, -6, 416, @@ -713,9 +816,9 @@ static const yytype_int16 yypact[] = -65, 1670, 2068, -65 }; - /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. - Performed when YYTABLE does not specify something else to do. Zero - means the default is an error. */ +/* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. + Performed when YYTABLE does not specify something else to do. Zero + means the default is an error. */ static const yytype_int8 yydefact[] = { 3, 0, 0, 1, 0, 0, 92, 103, 0, 0, @@ -750,23 +853,23 @@ static const yytype_int8 yydefact[] = 10, 0, 0, 15 }; - /* YYPGOTO[NTERM-NUM]. */ +/* YYPGOTO[NTERM-NUM]. */ static const yytype_int16 yypgoto[] = { -65, -65, -65, -65, -11, 348, -8, 1, 198, -65, 351, 0, 242 }; - /* YYDEFGOTO[NTERM-NUM]. */ -static const yytype_int16 yydefgoto[] = +/* YYDEFGOTO[NTERM-NUM]. */ +static const yytype_uint8 yydefgoto[] = { - -1, 1, 2, 20, 162, 68, 40, 69, 23, 24, + 0, 1, 2, 20, 162, 68, 40, 69, 23, 24, 41, 70, 163 }; - /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If - positive, shift that token. If negative, reduce the rule whose - number is the opposite. If YYTABLE_NINF, syntax error. */ +/* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If + positive, shift that token. If negative, reduce the rule whose + number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_int16 yytable[] = { 67, 43, 26, 22, 30, 29, 44, 4, 5, 73, @@ -1219,8 +1322,8 @@ static const yytype_int16 yycheck[] = 35, 36, 37, 38, 39 }; - /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing - symbol of state STATE-NUM. */ +/* YYSTOS[STATE-NUM] -- The symbol kind of the accessing symbol of + state STATE-NUM. */ static const yytype_int8 yystos[] = { 0, 81, 82, 0, 9, 14, 33, 58, 59, 60, @@ -1255,7 +1358,7 @@ static const yytype_int8 yystos[] = 7, 74, 84, 7 }; - /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ +/* YYR1[RULE-NUM] -- Symbol kind of the left-hand side of rule RULE-NUM. */ static const yytype_int8 yyr1[] = { 0, 80, 81, 82, 82, 82, 82, 83, 83, 83, @@ -1272,7 +1375,7 @@ static const yytype_int8 yyr1[] = 90, 91, 91, 91, 92, 92, 92 }; - /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ +/* YYR2[RULE-NUM] -- Number of symbols on the right-hand side of rule RULE-NUM. */ static const yytype_int8 yyr2[] = { 0, 2, 2, 0, 2, 4, 6, 4, 5, 4, @@ -1290,21 +1393,22 @@ static const yytype_int8 yyr2[] = }; +enum { YYENOMEM = -2 }; + #define yyerrok (yyerrstatus = 0) -#define yyclearin (yychar = YYEMPTY) -#define YYEMPTY (-2) -#define YYEOF 0 +#define yyclearin (yychar = PCODEEMPTY) #define YYACCEPT goto yyacceptlab #define YYABORT goto yyabortlab #define YYERROR goto yyerrorlab +#define YYNOMEM goto yyexhaustedlab #define YYRECOVERING() (!!yyerrstatus) #define YYBACKUP(Token, Value) \ do \ - if (yychar == YYEMPTY) \ + if (yychar == PCODEEMPTY) \ { \ yychar = (Token); \ yylval = (Value); \ @@ -1319,10 +1423,9 @@ static const yytype_int8 yyr2[] = } \ while (0) -/* Error token number */ -#define YYTERROR 1 -#define YYERRCODE 256 - +/* Backward compatibility with an undocumented macro. + Use PCODEerror or PCODEUNDEF. */ +#define YYERRCODE PCODEUNDEF /* Enable debugging if requested. */ @@ -1339,19 +1442,16 @@ do { \ YYFPRINTF Args; \ } while (0) -/* This macro is provided for backward compatibility. */ -#ifndef YY_LOCATION_PRINT -# define YY_LOCATION_PRINT(File, Loc) ((void) 0) -#endif -# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ + +# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) \ do { \ if (yydebug) \ { \ YYFPRINTF (stderr, "%s ", Title); \ yy_symbol_print (stderr, \ - Type, Value); \ + Kind, Value); \ YYFPRINTF (stderr, "\n"); \ } \ } while (0) @@ -1362,18 +1462,15 @@ do { \ `-----------------------------------*/ static void -yy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) +yy_symbol_value_print (FILE *yyo, + yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) { FILE *yyoutput = yyo; - YYUSE (yyoutput); + YY_USE (yyoutput); if (!yyvaluep) return; -# ifdef YYPRINT - if (yytype < YYNTOKENS) - YYPRINT (yyo, yytoknum[yytype], *yyvaluep); -# endif YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - YYUSE (yytype); + YY_USE (yykind); YY_IGNORE_MAYBE_UNINITIALIZED_END } @@ -1383,12 +1480,13 @@ yy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) `---------------------------*/ static void -yy_symbol_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) +yy_symbol_print (FILE *yyo, + yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) { YYFPRINTF (yyo, "%s %s (", - yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]); + yykind < YYNTOKENS ? "token" : "nterm", yysymbol_name (yykind)); - yy_symbol_value_print (yyo, yytype, yyvaluep); + yy_symbol_value_print (yyo, yykind, yyvaluep); YYFPRINTF (yyo, ")"); } @@ -1421,7 +1519,8 @@ do { \ `------------------------------------------------*/ static void -yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule) +yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, + int yyrule) { int yylno = yyrline[yyrule]; int yynrhs = yyr2[yyrule]; @@ -1433,9 +1532,8 @@ yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule) { YYFPRINTF (stderr, " $%d = ", yyi + 1); yy_symbol_print (stderr, - yystos[+yyssp[yyi + 1 - yynrhs]], - &yyvsp[(yyi + 1) - (yynrhs)] - ); + YY_ACCESSING_SYMBOL (+yyssp[yyi + 1 - yynrhs]), + &yyvsp[(yyi + 1) - (yynrhs)]); YYFPRINTF (stderr, "\n"); } } @@ -1450,8 +1548,8 @@ do { \ multiple parsers can coexist. */ int yydebug; #else /* !PCODEDEBUG */ -# define YYDPRINTF(Args) -# define YY_SYMBOL_PRINT(Title, Type, Value, Location) +# define YYDPRINTF(Args) ((void) 0) +# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) # define YY_STACK_PRINT(Bottom, Top) # define YY_REDUCE_PRINT(Rule) #endif /* !PCODEDEBUG */ @@ -1474,294 +1572,67 @@ int yydebug; #endif -#if YYERROR_VERBOSE - -# ifndef yystrlen -# if defined __GLIBC__ && defined _STRING_H -# define yystrlen(S) (YY_CAST (YYPTRDIFF_T, strlen (S))) -# else -/* Return the length of YYSTR. */ -static YYPTRDIFF_T -yystrlen (const char *yystr) -{ - YYPTRDIFF_T yylen; - for (yylen = 0; yystr[yylen]; yylen++) - continue; - return yylen; -} -# endif -# endif - -# ifndef yystpcpy -# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE -# define yystpcpy stpcpy -# else -/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in - YYDEST. */ -static char * -yystpcpy (char *yydest, const char *yysrc) -{ - char *yyd = yydest; - const char *yys = yysrc; - - while ((*yyd++ = *yys++) != '\0') - continue; - return yyd - 1; -} -# endif -# endif -# ifndef yytnamerr -/* Copy to YYRES the contents of YYSTR after stripping away unnecessary - quotes and backslashes, so that it's suitable for yyerror. The - heuristic is that double-quoting is unnecessary unless the string - contains an apostrophe, a comma, or backslash (other than - backslash-backslash). YYSTR is taken from yytname. If YYRES is - null, do not copy; instead, return the length of what the result - would have been. */ -static YYPTRDIFF_T -yytnamerr (char *yyres, const char *yystr) -{ - if (*yystr == '"') - { - YYPTRDIFF_T yyn = 0; - char const *yyp = yystr; - - for (;;) - switch (*++yyp) - { - case '\'': - case ',': - goto do_not_strip_quotes; - - case '\\': - if (*++yyp != '\\') - goto do_not_strip_quotes; - else - goto append; - - append: - default: - if (yyres) - yyres[yyn] = *yyp; - yyn++; - break; - - case '"': - if (yyres) - yyres[yyn] = '\0'; - return yyn; - } - do_not_strip_quotes: ; - } - if (yyres) - return yystpcpy (yyres, yystr) - yyres; - else - return yystrlen (yystr); -} -# endif - -/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message - about the unexpected token YYTOKEN for the state stack whose top is - YYSSP. - - Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is - not large enough to hold the message. In that case, also set - *YYMSG_ALLOC to the required number of bytes. Return 2 if the - required number of bytes is too large to store. */ -static int -yysyntax_error (YYPTRDIFF_T *yymsg_alloc, char **yymsg, - yy_state_t *yyssp, int yytoken) -{ - enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; - /* Internationalized format string. */ - const char *yyformat = YY_NULLPTR; - /* Arguments of yyformat: reported tokens (one for the "unexpected", - one per "expected"). */ - char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; - /* Actual size of YYARG. */ - int yycount = 0; - /* Cumulated lengths of YYARG. */ - YYPTRDIFF_T yysize = 0; - - /* There are many possibilities here to consider: - - If this state is a consistent state with a default action, then - the only way this function was invoked is if the default action - is an error action. In that case, don't check for expected - tokens because there are none. - - The only way there can be no lookahead present (in yychar) is if - this state is a consistent state with a default action. Thus, - detecting the absence of a lookahead is sufficient to determine - that there is no unexpected or expected token to report. In that - case, just report a simple "syntax error". - - Don't assume there isn't a lookahead just because this state is a - consistent state with a default action. There might have been a - previous inconsistent state, consistent state with a non-default - action, or user semantic action that manipulated yychar. - - Of course, the expected token list depends on states to have - correct lookahead information, and it depends on the parser not - to perform extra reductions after fetching a lookahead from the - scanner and before detecting a syntax error. Thus, state merging - (from LALR or IELR) and default reductions corrupt the expected - token list. However, the list is correct for canonical LR with - one exception: it will still contain any token that will not be - accepted due to an error action in a later state. - */ - if (yytoken != YYEMPTY) - { - int yyn = yypact[+*yyssp]; - YYPTRDIFF_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); - yysize = yysize0; - yyarg[yycount++] = yytname[yytoken]; - if (!yypact_value_is_default (yyn)) - { - /* Start YYX at -YYN if negative to avoid negative indexes in - YYCHECK. In other words, skip the first -YYN actions for - this state because they are default actions. */ - int yyxbegin = yyn < 0 ? -yyn : 0; - /* Stay within bounds of both yycheck and yytname. */ - int yychecklim = YYLAST - yyn + 1; - int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS; - int yyx; - - for (yyx = yyxbegin; yyx < yyxend; ++yyx) - if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR - && !yytable_value_is_error (yytable[yyx + yyn])) - { - if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM) - { - yycount = 1; - yysize = yysize0; - break; - } - yyarg[yycount++] = yytname[yyx]; - { - YYPTRDIFF_T yysize1 - = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); - if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) - yysize = yysize1; - else - return 2; - } - } - } - } - - switch (yycount) - { -# define YYCASE_(N, S) \ - case N: \ - yyformat = S; \ - break - default: /* Avoid compiler warnings. */ - YYCASE_(0, YY_("syntax error")); - YYCASE_(1, YY_("syntax error, unexpected %s")); - YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); - YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s")); - YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s")); - YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s")); -# undef YYCASE_ - } - - { - /* Don't count the "%s"s in the final size, but reserve room for - the terminator. */ - YYPTRDIFF_T yysize1 = yysize + (yystrlen (yyformat) - 2 * yycount) + 1; - if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) - yysize = yysize1; - else - return 2; - } - - if (*yymsg_alloc < yysize) - { - *yymsg_alloc = 2 * yysize; - if (! (yysize <= *yymsg_alloc - && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM)) - *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM; - return 1; - } - - /* Avoid sprintf, as that infringes on the user's name space. - Don't have undefined behavior even if the translation - produced a string with the wrong number of "%s"s. */ - { - char *yyp = *yymsg; - int yyi = 0; - while ((*yyp = *yyformat) != '\0') - if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount) - { - yyp += yytnamerr (yyp, yyarg[yyi++]); - yyformat += 2; - } - else - { - ++yyp; - ++yyformat; - } - } - return 0; -} -#endif /* YYERROR_VERBOSE */ /*-----------------------------------------------. | Release the memory associated to this symbol. | `-----------------------------------------------*/ static void -yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) +yydestruct (const char *yymsg, + yysymbol_kind_t yykind, YYSTYPE *yyvaluep) { - YYUSE (yyvaluep); + YY_USE (yyvaluep); if (!yymsg) yymsg = "Deleting"; - YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); + YY_SYMBOL_PRINT (yymsg, yykind, yyvaluep, yylocationp); YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - switch (yytype) + switch (yykind) { - case 65: /* INTEGER */ + case YYSYMBOL_INTEGER: /* INTEGER */ { delete ((*yyvaluep).i); } break; - case 66: /* STRING */ + case YYSYMBOL_STRING: /* STRING */ { delete ((*yyvaluep).str); } break; - case 82: /* rtlmid */ + case YYSYMBOL_rtlmid: /* rtlmid */ { delete ((*yyvaluep).sem); } break; - case 83: /* statement */ + case YYSYMBOL_statement: /* statement */ { if (((*yyvaluep).stmt) != (vector *)0) { for(int4 i=0;i<((*yyvaluep).stmt)->size();++i) delete (*((*yyvaluep).stmt))[i]; delete ((*yyvaluep).stmt);} } break; - case 84: /* expr */ + case YYSYMBOL_expr: /* expr */ { delete ((*yyvaluep).tree); } break; - case 85: /* sizedstar */ + case YYSYMBOL_sizedstar: /* sizedstar */ { delete ((*yyvaluep).starqual); } break; - case 86: /* jumpdest */ + case YYSYMBOL_jumpdest: /* jumpdest */ { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); } break; - case 87: /* varnode */ + case YYSYMBOL_varnode: /* varnode */ { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); } break; - case 88: /* integervarnode */ + case YYSYMBOL_integervarnode: /* integervarnode */ { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); } break; - case 89: /* lhsvarnode */ + case YYSYMBOL_lhsvarnode: /* lhsvarnode */ { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); } break; - case 92: /* paramlist */ + case YYSYMBOL_paramlist: /* paramlist */ { for(int4 i=0;i<((*yyvaluep).param)->size();++i) delete (*((*yyvaluep).param))[i]; delete ((*yyvaluep).param); } break; @@ -1772,9 +1643,7 @@ yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) } - - -/* The lookahead symbol. */ +/* Lookahead token kind. */ int yychar; /* The semantic value of the lookahead symbol. */ @@ -1783,6 +1652,8 @@ YYSTYPE yylval; int yynerrs; + + /*----------. | yyparse. | `----------*/ @@ -1790,43 +1661,36 @@ int yynerrs; int yyparse (void) { - yy_state_fast_t yystate; + yy_state_fast_t yystate = 0; /* Number of tokens to shift before error messages enabled. */ - int yyerrstatus; - - /* The stacks and their tools: - 'yyss': related to states. - 'yyvs': related to semantic values. + int yyerrstatus = 0; - Refer to the stacks through separate pointers, to allow yyoverflow + /* Refer to the stacks through separate pointers, to allow yyoverflow to reallocate them elsewhere. */ - /* The state stack. */ + /* Their size. */ + YYPTRDIFF_T yystacksize = YYINITDEPTH; + + /* The state stack: array, bottom, top. */ yy_state_t yyssa[YYINITDEPTH]; - yy_state_t *yyss; - yy_state_t *yyssp; + yy_state_t *yyss = yyssa; + yy_state_t *yyssp = yyss; - /* The semantic value stack. */ + /* The semantic value stack: array, bottom, top. */ YYSTYPE yyvsa[YYINITDEPTH]; - YYSTYPE *yyvs; - YYSTYPE *yyvsp; - - YYPTRDIFF_T yystacksize; + YYSTYPE *yyvs = yyvsa; + YYSTYPE *yyvsp = yyvs; int yyn; + /* The return value of yyparse. */ int yyresult; - /* Lookahead token as an internal (translated) token number. */ - int yytoken = 0; + /* Lookahead symbol kind. */ + yysymbol_kind_t yytoken = YYSYMBOL_YYEMPTY; /* The variables used to return semantic value and location from the action routines. */ YYSTYPE yyval; -#if YYERROR_VERBOSE - /* Buffer for error messages, and its allocated size. */ - char yymsgbuf[128]; - char *yymsg = yymsgbuf; - YYPTRDIFF_T yymsg_alloc = sizeof yymsgbuf; -#endif + #define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) @@ -1834,16 +1698,10 @@ yyparse (void) Keep to zero when no symbol should be popped. */ int yylen = 0; - yyssp = yyss = yyssa; - yyvsp = yyvs = yyvsa; - yystacksize = YYINITDEPTH; - YYDPRINTF ((stderr, "Starting parse\n")); - yystate = 0; - yyerrstatus = 0; - yynerrs = 0; - yychar = YYEMPTY; /* Cause a token to be read. */ + yychar = PCODEEMPTY; /* Cause a token to be read. */ + goto yysetstate; @@ -1865,10 +1723,11 @@ yyparse (void) YY_IGNORE_USELESS_CAST_BEGIN *yyssp = YY_CAST (yy_state_t, yystate); YY_IGNORE_USELESS_CAST_END + YY_STACK_PRINT (yyss, yyssp); if (yyss + yystacksize - 1 <= yyssp) #if !defined yyoverflow && !defined YYSTACK_RELOCATE - goto yyexhaustedlab; + YYNOMEM; #else { /* Get the current used size of the three stacks, in elements. */ @@ -1896,7 +1755,7 @@ yyparse (void) # else /* defined YYSTACK_RELOCATE */ /* Extend the stack our own way. */ if (YYMAXDEPTH <= yystacksize) - goto yyexhaustedlab; + YYNOMEM; yystacksize *= 2; if (YYMAXDEPTH < yystacksize) yystacksize = YYMAXDEPTH; @@ -1907,10 +1766,10 @@ yyparse (void) YY_CAST (union yyalloc *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize)))); if (! yyptr) - goto yyexhaustedlab; + YYNOMEM; YYSTACK_RELOCATE (yyss_alloc, yyss); YYSTACK_RELOCATE (yyvs_alloc, yyvs); -# undef YYSTACK_RELOCATE +# undef YYSTACK_RELOCATE if (yyss1 != yyssa) YYSTACK_FREE (yyss1); } @@ -1929,6 +1788,7 @@ yyparse (void) } #endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */ + if (yystate == YYFINAL) YYACCEPT; @@ -1949,18 +1809,29 @@ yyparse (void) /* Not known => get a lookahead token if don't already have one. */ - /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */ - if (yychar == YYEMPTY) + /* YYCHAR is either empty, or end-of-input, or a valid lookahead. */ + if (yychar == PCODEEMPTY) { - YYDPRINTF ((stderr, "Reading a token: ")); + YYDPRINTF ((stderr, "Reading a token\n")); yychar = yylex (); } - if (yychar <= YYEOF) + if (yychar <= PCODEEOF) { - yychar = yytoken = YYEOF; + yychar = PCODEEOF; + yytoken = YYSYMBOL_YYEOF; YYDPRINTF ((stderr, "Now at end of input.\n")); } + else if (yychar == PCODEerror) + { + /* The scanner already issued an error message, process directly + to error recovery. But do not keep the error token as + lookahead, it is too special and may lead us to an endless + loop in error recovery. */ + yychar = PCODEUNDEF; + yytoken = YYSYMBOL_YYerror; + goto yyerrlab1; + } else { yytoken = YYTRANSLATE (yychar); @@ -1994,7 +1865,7 @@ yyparse (void) YY_IGNORE_MAYBE_UNINITIALIZED_END /* Discard the shifted token. */ - yychar = YYEMPTY; + yychar = PCODEEMPTY; goto yynewstate; @@ -2029,463 +1900,463 @@ yyparse (void) YY_REDUCE_PRINT (yyn); switch (yyn) { - case 2: + case 2: /* rtl: rtlmid ENDOFSTREAM */ { pcode->setResult((yyvsp[-1].sem)); } break; - case 3: + case 3: /* rtlmid: %empty */ { (yyval.sem) = new ConstructTpl(); } break; - case 4: + case 4: /* rtlmid: rtlmid statement */ { (yyval.sem) = (yyvsp[-1].sem); if (!(yyval.sem)->addOpList(*(yyvsp[0].stmt))) { delete (yyvsp[0].stmt); yyerror("Multiple delayslot declarations"); YYERROR; } delete (yyvsp[0].stmt); } break; - case 5: + case 5: /* rtlmid: rtlmid LOCAL_KEY STRING ';' */ { (yyval.sem) = (yyvsp[-3].sem); pcode->newLocalDefinition((yyvsp[-1].str)); } break; - case 6: + case 6: /* rtlmid: rtlmid LOCAL_KEY STRING ':' INTEGER ';' */ { (yyval.sem) = (yyvsp[-5].sem); pcode->newLocalDefinition((yyvsp[-3].str),*(yyvsp[-1].i)); delete (yyvsp[-1].i); } break; - case 7: + case 7: /* statement: lhsvarnode '=' expr ';' */ { (yyvsp[-1].tree)->setOutput((yyvsp[-3].varnode)); (yyval.stmt) = ExprTree::toVector((yyvsp[-1].tree)); } break; - case 8: + case 8: /* statement: LOCAL_KEY STRING '=' expr ';' */ { (yyval.stmt) = pcode->newOutput(true,(yyvsp[-1].tree),(yyvsp[-3].str)); } break; - case 9: + case 9: /* statement: STRING '=' expr ';' */ { (yyval.stmt) = pcode->newOutput(false,(yyvsp[-1].tree),(yyvsp[-3].str)); } break; - case 10: + case 10: /* statement: LOCAL_KEY STRING ':' INTEGER '=' expr ';' */ { (yyval.stmt) = pcode->newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); } break; - case 11: + case 11: /* statement: STRING ':' INTEGER '=' expr ';' */ { (yyval.stmt) = pcode->newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); } break; - case 12: + case 12: /* statement: LOCAL_KEY specificsymbol '=' */ { (yyval.stmt) = (vector *)0; string errmsg = "Redefinition of symbol: "+(yyvsp[-1].specsym)->getName(); yyerror(errmsg.c_str()); YYERROR; } break; - case 13: + case 13: /* statement: sizedstar expr '=' expr ';' */ { (yyval.stmt) = pcode->createStore((yyvsp[-4].starqual),(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 14: + case 14: /* statement: USEROPSYM '(' paramlist ')' ';' */ { (yyval.stmt) = pcode->createUserOpNoOut((yyvsp[-4].useropsym),(yyvsp[-2].param)); } break; - case 15: + case 15: /* statement: lhsvarnode '[' INTEGER ',' INTEGER ']' '=' expr ';' */ { (yyval.stmt) = pcode->assignBitRange((yyvsp[-8].varnode),(uint4)*(yyvsp[-6].i),(uint4)*(yyvsp[-4].i),(yyvsp[-1].tree)); delete (yyvsp[-6].i), delete (yyvsp[-4].i); } break; - case 16: + case 16: /* statement: varnode ':' INTEGER '=' */ { (yyval.stmt) = (vector *)0; delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); yyerror("Illegal truncation on left-hand side of assignment"); YYERROR; } break; - case 17: + case 17: /* statement: varnode '(' INTEGER ')' */ { (yyval.stmt) = (vector *)0; delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); yyerror("Illegal subpiece on left-hand side of assignment"); YYERROR; } break; - case 18: + case 18: /* statement: GOTO_KEY jumpdest ';' */ { (yyval.stmt) = pcode->createOpNoOut(CPUI_BRANCH,new ExprTree((yyvsp[-1].varnode))); } break; - case 19: + case 19: /* statement: IF_KEY expr GOTO_KEY jumpdest ';' */ { (yyval.stmt) = pcode->createOpNoOut(CPUI_CBRANCH,new ExprTree((yyvsp[-1].varnode)),(yyvsp[-3].tree)); } break; - case 20: + case 20: /* statement: GOTO_KEY '[' expr ']' ';' */ { (yyval.stmt) = pcode->createOpNoOut(CPUI_BRANCHIND,(yyvsp[-2].tree)); } break; - case 21: + case 21: /* statement: CALL_KEY jumpdest ';' */ { (yyval.stmt) = pcode->createOpNoOut(CPUI_CALL,new ExprTree((yyvsp[-1].varnode))); } break; - case 22: + case 22: /* statement: CALL_KEY '[' expr ']' ';' */ { (yyval.stmt) = pcode->createOpNoOut(CPUI_CALLIND,(yyvsp[-2].tree)); } break; - case 23: + case 23: /* statement: RETURN_KEY ';' */ { (yyval.stmt) = (vector *)0; yyerror("Must specify an indirect parameter for return"); YYERROR; } break; - case 24: + case 24: /* statement: RETURN_KEY '[' expr ']' ';' */ { (yyval.stmt) = pcode->createOpNoOut(CPUI_RETURN,(yyvsp[-2].tree)); } break; - case 25: + case 25: /* statement: label */ { (yyval.stmt) = pcode->placeLabel( (yyvsp[0].labelsym) ); } break; - case 26: + case 26: /* expr: varnode */ { (yyval.tree) = new ExprTree((yyvsp[0].varnode)); } break; - case 27: + case 27: /* expr: sizedstar expr */ { (yyval.tree) = pcode->createLoad((yyvsp[-1].starqual),(yyvsp[0].tree)); } break; - case 28: + case 28: /* expr: '(' expr ')' */ { (yyval.tree) = (yyvsp[-1].tree); } break; - case 29: + case 29: /* expr: expr '+' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 30: + case 30: /* expr: expr '-' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 31: + case 31: /* expr: expr OP_EQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 32: + case 32: /* expr: expr OP_NOTEQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 33: + case 33: /* expr: expr '<' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 34: + case 34: /* expr: expr OP_GREATEQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 35: + case 35: /* expr: expr OP_LESSEQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 36: + case 36: /* expr: expr '>' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 37: + case 37: /* expr: expr OP_SLESS expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_SLESS,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 38: + case 38: /* expr: expr OP_SGREATEQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_SLESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 39: + case 39: /* expr: expr OP_SLESSEQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_SLESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 40: + case 40: /* expr: expr OP_SGREAT expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_SLESS,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 41: + case 41: /* expr: '-' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_2COMP,(yyvsp[0].tree)); } break; - case 42: + case 42: /* expr: '~' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_NEGATE,(yyvsp[0].tree)); } break; - case 43: + case 43: /* expr: expr '^' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 44: + case 44: /* expr: expr '&' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 45: + case 45: /* expr: expr '|' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 46: + case 46: /* expr: expr OP_LEFT expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_LEFT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 47: + case 47: /* expr: expr OP_RIGHT expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_RIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 48: + case 48: /* expr: expr OP_SRIGHT expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_SRIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 49: + case 49: /* expr: expr '*' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 50: + case 50: /* expr: expr '/' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 51: + case 51: /* expr: expr OP_SDIV expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_SDIV,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 52: + case 52: /* expr: expr '%' expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_REM,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 53: + case 53: /* expr: expr OP_SREM expr */ { (yyval.tree) = pcode->createOp(CPUI_INT_SREM,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 54: + case 54: /* expr: '!' expr */ { (yyval.tree) = pcode->createOp(CPUI_BOOL_NEGATE,(yyvsp[0].tree)); } break; - case 55: + case 55: /* expr: expr OP_BOOL_XOR expr */ { (yyval.tree) = pcode->createOp(CPUI_BOOL_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 56: + case 56: /* expr: expr OP_BOOL_AND expr */ { (yyval.tree) = pcode->createOp(CPUI_BOOL_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 57: + case 57: /* expr: expr OP_BOOL_OR expr */ { (yyval.tree) = pcode->createOp(CPUI_BOOL_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 58: + case 58: /* expr: expr OP_FEQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 59: + case 59: /* expr: expr OP_FNOTEQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 60: + case 60: /* expr: expr OP_FLESS expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 61: + case 61: /* expr: expr OP_FGREAT expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 62: + case 62: /* expr: expr OP_FLESSEQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 63: + case 63: /* expr: expr OP_FGREATEQUAL expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 64: + case 64: /* expr: expr OP_FADD expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 65: + case 65: /* expr: expr OP_FSUB expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 66: + case 66: /* expr: expr OP_FMULT expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 67: + case 67: /* expr: expr OP_FDIV expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 68: + case 68: /* expr: OP_FSUB expr */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_NEG,(yyvsp[0].tree)); } break; - case 69: + case 69: /* expr: OP_ABS '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_ABS,(yyvsp[-1].tree)); } break; - case 70: + case 70: /* expr: OP_SQRT '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_SQRT,(yyvsp[-1].tree)); } break; - case 71: + case 71: /* expr: OP_SEXT '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_INT_SEXT,(yyvsp[-1].tree)); } break; - case 72: + case 72: /* expr: OP_ZEXT '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_INT_ZEXT,(yyvsp[-1].tree)); } break; - case 73: + case 73: /* expr: OP_CARRY '(' expr ',' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_INT_CARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 74: + case 74: /* expr: OP_SCARRY '(' expr ',' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_INT_SCARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 75: + case 75: /* expr: OP_SBORROW '(' expr ',' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_INT_SBORROW,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 76: + case 76: /* expr: OP_FLOAT2FLOAT '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_FLOAT2FLOAT,(yyvsp[-1].tree)); } break; - case 77: + case 77: /* expr: OP_INT2FLOAT '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_INT2FLOAT,(yyvsp[-1].tree)); } break; - case 78: + case 78: /* expr: OP_NAN '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_NAN,(yyvsp[-1].tree)); } break; - case 79: + case 79: /* expr: OP_TRUNC '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_TRUNC,(yyvsp[-1].tree)); } break; - case 80: + case 80: /* expr: OP_CEIL '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_CEIL,(yyvsp[-1].tree)); } break; - case 81: + case 81: /* expr: OP_FLOOR '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_FLOOR,(yyvsp[-1].tree)); } break; - case 82: + case 82: /* expr: OP_ROUND '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_FLOAT_ROUND,(yyvsp[-1].tree)); } break; - case 83: + case 83: /* expr: OP_NEW '(' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_NEW,(yyvsp[-1].tree)); } break; - case 84: + case 84: /* expr: OP_NEW '(' expr ',' expr ')' */ { (yyval.tree) = pcode->createOp(CPUI_NEW,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 85: + case 85: /* expr: specificsymbol '(' integervarnode ')' */ { (yyval.tree) = pcode->createOp(CPUI_SUBPIECE,new ExprTree((yyvsp[-3].specsym)->getVarnode()),new ExprTree((yyvsp[-1].varnode))); } break; - case 86: + case 86: /* expr: specificsymbol ':' INTEGER */ { (yyval.tree) = pcode->createBitRange((yyvsp[-2].specsym),0,(uint4)(*(yyvsp[0].i) * 8)); delete (yyvsp[0].i); } break; - case 87: + case 87: /* expr: specificsymbol '[' INTEGER ',' INTEGER ']' */ { (yyval.tree) = pcode->createBitRange((yyvsp[-5].specsym),(uint4)*(yyvsp[-3].i),(uint4)*(yyvsp[-1].i)); delete (yyvsp[-3].i), delete (yyvsp[-1].i); } break; - case 88: + case 88: /* expr: USEROPSYM '(' paramlist ')' */ { (yyval.tree) = pcode->createUserOp((yyvsp[-3].useropsym),(yyvsp[-1].param)); } break; - case 89: + case 89: /* sizedstar: '*' '[' SPACESYM ']' ':' INTEGER */ { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl((yyvsp[-3].spacesym)->getSpace()); } break; - case 90: + case 90: /* sizedstar: '*' '[' SPACESYM ']' */ { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl((yyvsp[-1].spacesym)->getSpace()); } break; - case 91: + case 91: /* sizedstar: '*' ':' INTEGER */ { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl(pcode->getDefaultSpace()); } break; - case 92: + case 92: /* sizedstar: '*' */ { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl(pcode->getDefaultSpace()); } break; - case 93: + case 93: /* jumpdest: JUMPSYM */ { VarnodeTpl *sym = (yyvsp[0].specsym)->getVarnode(); (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),sym->getOffset(),ConstTpl(ConstTpl::j_curspace_size)); delete sym; } break; - case 94: + case 94: /* jumpdest: INTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::j_curspace_size)); delete (yyvsp[0].i); } break; - case 95: + case 95: /* jumpdest: BADINTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::j_curspace_size)); yyerror("Parsed integer is too big (overflow)"); } break; - case 96: + case 96: /* jumpdest: INTEGER '[' SPACESYM ']' */ { AddrSpace *spc = (yyvsp[-1].spacesym)->getSpace(); (yyval.varnode) = new VarnodeTpl(ConstTpl(spc),ConstTpl(ConstTpl::real,*(yyvsp[-3].i)),ConstTpl(ConstTpl::real,spc->getAddrSize())); delete (yyvsp[-3].i); } break; - case 97: + case 97: /* jumpdest: label */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::j_relative,(yyvsp[0].labelsym)->getIndex()),ConstTpl(ConstTpl::real,sizeof(uintm))); (yyvsp[0].labelsym)->incrementRefCount(); } break; - case 98: + case 98: /* jumpdest: STRING */ { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Unknown jump destination: "+*(yyvsp[0].str); delete (yyvsp[0].str); yyerror(errmsg.c_str()); YYERROR; } break; - case 99: + case 99: /* varnode: specificsymbol */ { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); } break; - case 100: + case 100: /* varnode: integervarnode */ { (yyval.varnode) = (yyvsp[0].varnode); } break; - case 101: + case 101: /* varnode: STRING */ { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Unknown varnode parameter: "+*(yyvsp[0].str); delete (yyvsp[0].str); yyerror(errmsg.c_str()); YYERROR; } break; - case 102: + case 102: /* integervarnode: INTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::real,0)); delete (yyvsp[0].i); } break; - case 103: + case 103: /* integervarnode: BADINTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::real,0)); yyerror("Parsed integer is too big (overflow)"); } break; - case 104: + case 104: /* integervarnode: INTEGER ':' INTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[-2].i)),ConstTpl(ConstTpl::real,*(yyvsp[0].i))); delete (yyvsp[-2].i); delete (yyvsp[0].i); } break; - case 105: + case 105: /* integervarnode: '&' varnode */ { (yyval.varnode) = pcode->addressOf((yyvsp[0].varnode),0); } break; - case 106: + case 106: /* integervarnode: '&' ':' INTEGER varnode */ { (yyval.varnode) = pcode->addressOf((yyvsp[0].varnode),*(yyvsp[-1].i)); delete (yyvsp[-1].i); } break; - case 107: + case 107: /* lhsvarnode: specificsymbol */ { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); } break; - case 108: + case 108: /* lhsvarnode: STRING */ { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Unknown assignment varnode: "+*(yyvsp[0].str); delete (yyvsp[0].str); yyerror(errmsg.c_str()); YYERROR; } break; - case 109: + case 109: /* label: '<' LABELSYM '>' */ { (yyval.labelsym) = (yyvsp[-1].labelsym); } break; - case 110: + case 110: /* label: '<' STRING '>' */ { (yyval.labelsym) = pcode->defineLabel( (yyvsp[-1].str) ); } break; - case 111: + case 111: /* specificsymbol: VARSYM */ { (yyval.specsym) = (yyvsp[0].varsym); } break; - case 112: + case 112: /* specificsymbol: OPERANDSYM */ { (yyval.specsym) = (yyvsp[0].operandsym); } break; - case 113: + case 113: /* specificsymbol: JUMPSYM */ { (yyval.specsym) = (yyvsp[0].specsym); } break; - case 114: + case 114: /* paramlist: %empty */ { (yyval.param) = new vector; } break; - case 115: + case 115: /* paramlist: expr */ { (yyval.param) = new vector; (yyval.param)->push_back((yyvsp[0].tree)); } break; - case 116: + case 116: /* paramlist: paramlist ',' expr */ { (yyval.param) = (yyvsp[-2].param); (yyval.param)->push_back((yyvsp[0].tree)); } break; @@ -2504,11 +2375,10 @@ yyparse (void) case of YYERROR or YYBACKUP, subsequent parser actions might lead to an incorrect destructor call or verbose syntax error message before the lookahead is translated. */ - YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); + YY_SYMBOL_PRINT ("-> $$ =", YY_CAST (yysymbol_kind_t, yyr1[yyn]), &yyval, &yyloc); YYPOPSTACK (yylen); yylen = 0; - YY_STACK_PRINT (yyss, yyssp); *++yyvsp = yyval; @@ -2532,66 +2402,30 @@ yyparse (void) yyerrlab: /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ - yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar); - + yytoken = yychar == PCODEEMPTY ? YYSYMBOL_YYEMPTY : YYTRANSLATE (yychar); /* If not already recovering from an error, report this error. */ if (!yyerrstatus) { ++yynerrs; -#if ! YYERROR_VERBOSE yyerror (YY_("syntax error")); -#else -# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \ - yyssp, yytoken) - { - char const *yymsgp = YY_("syntax error"); - int yysyntax_error_status; - yysyntax_error_status = YYSYNTAX_ERROR; - if (yysyntax_error_status == 0) - yymsgp = yymsg; - else if (yysyntax_error_status == 1) - { - if (yymsg != yymsgbuf) - YYSTACK_FREE (yymsg); - yymsg = YY_CAST (char *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, yymsg_alloc))); - if (!yymsg) - { - yymsg = yymsgbuf; - yymsg_alloc = sizeof yymsgbuf; - yysyntax_error_status = 2; - } - else - { - yysyntax_error_status = YYSYNTAX_ERROR; - yymsgp = yymsg; - } - } - yyerror (yymsgp); - if (yysyntax_error_status == 2) - goto yyexhaustedlab; - } -# undef YYSYNTAX_ERROR -#endif } - - if (yyerrstatus == 3) { /* If just tried and failed to reuse lookahead token after an error, discard it. */ - if (yychar <= YYEOF) + if (yychar <= PCODEEOF) { /* Return failure if at end of input. */ - if (yychar == YYEOF) + if (yychar == PCODEEOF) YYABORT; } else { yydestruct ("Error: discarding", yytoken, &yylval); - yychar = YYEMPTY; + yychar = PCODEEMPTY; } } @@ -2608,6 +2442,7 @@ yyparse (void) label yyerrorlab therefore never appears in user code. */ if (0) YYERROR; + ++yynerrs; /* Do not reclaim the symbols of the rule whose action triggered this YYERROR. */ @@ -2624,13 +2459,14 @@ yyparse (void) yyerrlab1: yyerrstatus = 3; /* Each real token shifted decrements this. */ + /* Pop stack until we find a state that shifts the error token. */ for (;;) { yyn = yypact[yystate]; if (!yypact_value_is_default (yyn)) { - yyn += YYTERROR; - if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) + yyn += YYSYMBOL_YYerror; + if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYSYMBOL_YYerror) { yyn = yytable[yyn]; if (0 < yyn) @@ -2644,7 +2480,7 @@ yyparse (void) yydestruct ("Error: popping", - yystos[yystate], yyvsp); + YY_ACCESSING_SYMBOL (yystate), yyvsp); YYPOPSTACK (1); yystate = *yyssp; YY_STACK_PRINT (yyss, yyssp); @@ -2656,7 +2492,7 @@ yyparse (void) /* Shift the error token. */ - YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp); + YY_SYMBOL_PRINT ("Shifting", YY_ACCESSING_SYMBOL (yyn), yyvsp, yylsp); yystate = yyn; goto yynewstate; @@ -2667,7 +2503,7 @@ yyparse (void) `-------------------------------------*/ yyacceptlab: yyresult = 0; - goto yyreturn; + goto yyreturnlab; /*-----------------------------------. @@ -2675,25 +2511,23 @@ yyparse (void) `-----------------------------------*/ yyabortlab: yyresult = 1; - goto yyreturn; + goto yyreturnlab; -#if !defined yyoverflow || YYERROR_VERBOSE -/*-------------------------------------------------. -| yyexhaustedlab -- memory exhaustion comes here. | -`-------------------------------------------------*/ +/*-----------------------------------------------------------. +| yyexhaustedlab -- YYNOMEM (memory exhaustion) comes here. | +`-----------------------------------------------------------*/ yyexhaustedlab: yyerror (YY_("memory exhausted")); yyresult = 2; - /* Fall through. */ -#endif + goto yyreturnlab; -/*-----------------------------------------------------. -| yyreturn -- parsing is finished, return the result. | -`-----------------------------------------------------*/ -yyreturn: - if (yychar != YYEMPTY) +/*----------------------------------------------------------. +| yyreturnlab -- parsing is finished, clean up and return. | +`----------------------------------------------------------*/ +yyreturnlab: + if (yychar != PCODEEMPTY) { /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ @@ -2708,21 +2542,19 @@ yyparse (void) while (yyssp != yyss) { yydestruct ("Cleanup: popping", - yystos[+*yyssp], yyvsp); + YY_ACCESSING_SYMBOL (+*yyssp), yyvsp); YYPOPSTACK (1); } #ifndef yyoverflow if (yyss != yyssa) YYSTACK_FREE (yyss); #endif -#if YYERROR_VERBOSE - if (yymsg != yymsgbuf) - YYSTACK_FREE (yymsg); -#endif + return yyresult; } + #define IDENTREC_SIZE 46 const IdentRec PcodeLexer::idents[]= { // Sorted list of identifiers { "!=", OP_NOTEQUAL }, diff --git a/pypcode/sleigh/sleigh.cc b/pypcode/sleigh/sleigh.cc index b72f116a..304a73b4 100644 --- a/pypcode/sleigh/sleigh.cc +++ b/pypcode/sleigh/sleigh.cc @@ -55,16 +55,16 @@ VarnodeData *PcodeCacher::expandPool(uint4 size) for(uint4 i=0;i::iterator diter=issued.begin();diter!=issued.end();++diter) { + VarnodeData *outvar = (*diter).outvar; if (outvar != (VarnodeData *)0) { outvar = newpool + (outvar - poolstart); - issued[i].outvar = outvar; + (*diter).outvar = outvar; } - VarnodeData *invar = issued[i].invar; + VarnodeData *invar = (*diter).invar; if (invar != (VarnodeData *)0) { invar = newpool + (invar - poolstart); - issued[i].invar = invar; + (*diter).invar = invar; } } list::iterator iter; @@ -139,7 +139,7 @@ void PcodeCacher::resolveRelatives(void) void PcodeCacher::emit(const Address &addr,PcodeEmit *emt) const { - vector::const_iterator iter; + deque::const_iterator iter; for(iter=issued.begin();iter!=issued.end();++iter) emt->dump(addr,(*iter).opc,(*iter).outvar,(*iter).invar,(*iter).isize); diff --git a/pypcode/sleigh/sleigh.hh b/pypcode/sleigh/sleigh.hh index 6b96ae09..8e89dc0d 100644 --- a/pypcode/sleigh/sleigh.hh +++ b/pypcode/sleigh/sleigh.hh @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -42,9 +42,9 @@ struct RelativeRecord { /// /// Raw data used by the emitter to produce a single PcodeOp struct PcodeData { - OpCode opc; ///< The op code VarnodeData *outvar; ///< Output Varnode data (or null) VarnodeData *invar; ///< Array of input Varnode data + OpCode opc; ///< The op code int4 isize; ///< Number of input Varnodes }; @@ -59,7 +59,7 @@ class PcodeCacher { VarnodeData *poolstart; ///< Start of the pool of VarnodeData objects VarnodeData *curpool; ///< First unused VarnodeData VarnodeData *endpool; ///< End of the pool of VarnodeData objects - vector issued; ///< P-code ops issued for the current instruction + deque issued; ///< P-code ops issued for the current instruction list label_refs; ///< References to labels vector labels; ///< Locations of labels VarnodeData *expandPool(uint4 size); ///< Expand the memory pool diff --git a/pypcode/sleigh/translate.cc b/pypcode/sleigh/translate.cc index ec235a46..98060c2b 100644 --- a/pypcode/sleigh/translate.cc +++ b/pypcode/sleigh/translate.cc @@ -915,6 +915,34 @@ void AddrSpaceManager::renormalizeJoinAddress(Address &addr,int4 size) addr = Address(newJoinRecord->unified.space,newJoinRecord->unified.offset); } +/// If only 1 piece remains, the VarnodeData of that piece is returned. +/// Otherwise a new JoinRecord is created and its unified VarnodeData is returned. +/// \param join is the JoinRecord to strip +/// \param index is the index of the piece to strip, which must be at the front or back +/// \return the VarnodeData corresponding to the remaining piece(s) +const VarnodeData &AddrSpaceManager::stripJoinPiece(JoinRecord *join,int4 index) + +{ + int4 start,end; + if (index == 0) { + start = 1; + end = join->numPieces()-1; + } + else if (index == join->numPieces() - 1) { + start = 0; + end = join->numPieces()-2; + } + else + throw LowlevelError("Stripping middle piece from JoinRecord"); + if (start == end) + return join->getPiece(start); + vector newPieces; + for(int4 i=start;i<=end;++i) + newPieces.push_back(join->getPiece(i)); + JoinRecord *newJoinRecord = findAddJoin(newPieces, 0); + return newJoinRecord->unified; +} + /// The string \e must contain a hexadecimal offset. The offset may be optionally prepended with "0x". /// The string may optionally start with the name of the address space to associate with the offset, followed /// by ':' to separate it from the offset. If the name is not present, the default data space is assumed. diff --git a/pypcode/sleigh/translate.hh b/pypcode/sleigh/translate.hh index 09daa800..5abc6550 100644 --- a/pypcode/sleigh/translate.hh +++ b/pypcode/sleigh/translate.hh @@ -281,6 +281,9 @@ public: /// \brief Make sure a possibly offset \e join address has a proper JoinRecord void renormalizeJoinAddress(Address &addr,int4 size); + /// \brief Create an Address by stripping a piece from a JoinRecord + const VarnodeData &stripJoinPiece(JoinRecord *join,int4 index); + /// \brief Parse a string with just an \e address \e space name and a hex offset Address parseAddressSimple(const string &val); }; diff --git a/scripts/sleigh_download.sh b/scripts/sleigh_download.sh index 0832098d..b92fb763 100755 --- a/scripts/sleigh_download.sh +++ b/scripts/sleigh_download.sh @@ -2,7 +2,7 @@ set -e set -x -TAG=12.0.2 +TAG=12.1 GHIDRA_SRC_DIR=ghidra_src_${TAG} git clone --depth=1 -b Ghidra_${TAG}_build https://github.com/NationalSecurityAgency/ghidra.git ${GHIDRA_SRC_DIR}