diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 6389d90e48035..591d48960d21d 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -1860,13 +1860,10 @@ arch/arm/src/common/stm32/stm32_start_m0_v1.c alin.jerpelea@sony.com acassis@gma arch/arm/src/common/stm32/stm32_start_m3m4_v1.c xiaoxiang@xiaomi.com avyhovanec@yahoo.com alin.jerpelea@sony.com raiden00@railab.me anjiahao@xiaomi.com arch/arm/src/common/stm32/stm32_syscfg.h alin.jerpelea@sony.com raiden00@railab.me paul-a.patience@polymtl.ca david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c kpberezenko@gmail.com macscomp@gmail.com anthony@vergeaero.com rajanjg89@gmail.com xiaoxiang@xiaomi.com +arch/arm/src/common/stm32/stm32_tim.c pn_bouteville@yahoo.fr 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com paul-a.patience@polymtl.ca anthony@vergeaero.com arch/arm/src/common/stm32/stm32_tim.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/common/stm32/stm32_tim_m0_v1.c pn_bouteville@yahoo.fr jukka.laitinen@iki.fi david_s5@nscdg.com dpo@certi.org.br raiden00@railab.me -arch/arm/src/common/stm32/stm32_tim_m0_v1.h pn_bouteville@yahoo.fr jukka.laitinen@iki.fi xiaoxiang@xiaomi.com dpo@certi.org.br wail.khemir@polymtl.ca -arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c wail.khemir@polymtl.ca paul-a.patience@polymtl.ca dpo@certi.org.br mark@mjs.pw walmis@gmail.com -arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c pn_bouteville@yahoo.fr 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com paul-a.patience@polymtl.ca anthony@vergeaero.com -arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h alin.jerpelea@sony.com pn_bouteville@yahoo.fr xiaoxiang@xiaomi.com wail.khemir@polymtl.ca raiden00@railab.me -arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c wail.khemir@polymtl.ca paul-a.patience@polymtl.ca mark@mjs.pw xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com +arch/arm/src/common/stm32/stm32_tim_clk.h raiden00@railab.me +arch/arm/src/common/stm32/stm32_tim_lowerhalf.c wail.khemir@polymtl.ca paul-a.patience@polymtl.ca dpo@certi.org.br mark@mjs.pw walmis@gmail.com arch/arm/src/common/stm32/stm32_timerisr_armv6m.c alin.jerpelea@sony.com acassis@gmail.com xiaoxiang@xiaomi.com raiden00@railab.me mark@mjs.pw arch/arm/src/common/stm32/stm32_timerisr_armv7m.c jpa@git.mail.kapsi.fi alin.jerpelea@sony.com huangqi3@xiaomi.com xiaoxiang@xiaomi.com mark@mjs.pw arch/arm/src/common/stm32/stm32_uart.h alin.jerpelea@sony.com raiden00@railab.me 407652334@qq.com zhangyuan21@xiaomi.com @@ -3909,7 +3906,7 @@ arch/arm/src/stm32f7/hardware/stm32_sai.h cuichaochao916@gmail.com alin.jerpelea arch/arm/src/stm32f7/hardware/stm32_sdmmc.h julian@oes.ch alin.jerpelea@sony.com arch/arm/src/stm32f7/hardware/stm32_spi.h alin.jerpelea@sony.com arch/arm/src/stm32f7/hardware/stm32_syscfg.h alin.jerpelea@sony.com -arch/arm/src/stm32f7/hardware/stm32_tim.h alin.jerpelea@sony.com +arch/arm/src/stm32f7/hardware/stm32f7_tim.h alin.jerpelea@sony.com arch/arm/src/stm32f7/hardware/stm32_uart.h alin.jerpelea@sony.com arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h alin.jerpelea@sony.com petro.karashchenko@gmail.com raiden00@railab.me arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dbgmcu.h alin.jerpelea@sony.com petro.karashchenko@gmail.com xiaoxiang@xiaomi.com @@ -4031,9 +4028,6 @@ arch/arm/src/stm32f7/stm32_spi.h 59230071+hartmannathan@users.noreply.github.com arch/arm/src/stm32f7/stm32_start.c xiaoxiang@xiaomi.com alin.jerpelea@sony.com raiden00@railab.me lipengfei28@xiaomi.com arch/arm/src/stm32f7/stm32_start.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com arch/arm/src/stm32f7/stm32_tickless.c walmis@gmail.com anthony@vergeaero.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com alin.jerpelea@sony.com -arch/arm/src/stm32f7/stm32_tim.c peter.kolesnikov@external.telekom.de david_s5@nscdg.com alin.jerpelea@sony.com walmis@gmail.com anthony@vergeaero.com -arch/arm/src/stm32f7/stm32_tim.h 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com walmis@gmail.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com -arch/arm/src/stm32f7/stm32_tim_lowerhalf.c walmis@gmail.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com petro.karashchenko@gmail.com alin.jerpelea@sony.com arch/arm/src/stm32f7/stm32_timerisr.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com mark@mjs.pw anthony@vergeaero.com arch/arm/src/stm32f7/stm32_uart.h David.Sidrane@NscDg.com alin.jerpelea@sony.com jussi.kivilinna@haltian.com david_s5@nscdg.com arch/arm/src/stm32f7/stm32_uid.c walmis@gmail.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com gustavo.nihei@espressif.com @@ -4107,7 +4101,7 @@ arch/arm/src/stm32h5/hardware/stm32_pwr.h kwilson@2g-eng.com alin.jerpelea@sony. arch/arm/src/stm32h5/hardware/stm32_qspi.h kwilson@2g-eng.com arch/arm/src/stm32h5/hardware/stm32_rcc.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/hardware/stm32_sbs.h tbennett@2g-eng.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com -arch/arm/src/stm32h5/hardware/stm32_tim.h tbennett@2g-eng.com kwilson@2g-eng.com 101105604+simbit18@users.noreply.github.com devel@sumpfralle.de +arch/arm/src/stm32h5/hardware/stm32h5_tim.h tbennett@2g-eng.com kwilson@2g-eng.com 101105604+simbit18@users.noreply.github.com devel@sumpfralle.de arch/arm/src/stm32h5/hardware/stm32_uart.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/hardware/stm32_usbfs.h kwilson@2g-eng.com arch/arm/src/stm32h5/hardware/stm32h56x_dmasigmap.h kwilson@2g-eng.com @@ -4159,9 +4153,6 @@ arch/arm/src/stm32h5/stm32_spi.c kwilson@2g-eng.com arch/arm/src/stm32h5/stm32_spi.h kwilson@2g-eng.com arch/arm/src/stm32h5/stm32_start.c tbennett@2g-eng.com jlange@2g-eng.com kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/stm32_start.h tbennett@2g-eng.com alin.jerpelea@sony.com -arch/arm/src/stm32h5/stm32_tim.c kwilson@2g-eng.com -arch/arm/src/stm32h5/stm32_tim.h kwilson@2g-eng.com -arch/arm/src/stm32h5/stm32_tim_lowerhalf.c kwilson@2g-eng.com arch/arm/src/stm32h5/stm32_timerisr.c tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/stm32_uart.h tbennett@2g-eng.com jlange@2g-eng.com kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/stm32_uid.c tbennett@2g-eng.com @@ -4200,7 +4191,7 @@ arch/arm/src/stm32h7/hardware/stm32_rtcc.h david.sidrane@nscdg.com alin.jerpelea arch/arm/src/stm32h7/hardware/stm32_sdmmc.h alin.jerpelea@sony.com raiden00@railab.me javiercasas@geotab.com po@lambdaconcept.com arch/arm/src/stm32h7/hardware/stm32_spi.h raiden00@railab.me alin.jerpelea@sony.com alexanderlunev@mail.ru javiercasas@geotab.com arch/arm/src/stm32h7/hardware/stm32_syscfg.h alin.jerpelea@sony.com raiden00@railab.me javiercasas@geotab.com lwazeh@gmail.com -arch/arm/src/stm32h7/hardware/stm32_tim.h raiden00pl@gmail.com alin.jerpelea@sony.com anthony@vergeaero.com dpo@certi.org.br +arch/arm/src/stm32h7/hardware/stm32h7_tim.h raiden00pl@gmail.com alin.jerpelea@sony.com anthony@vergeaero.com dpo@certi.org.br arch/arm/src/stm32h7/hardware/stm32_uart.h alin.jerpelea@sony.com raiden00@railab.me javiercasas@geotab.com lwazeh@gmail.com arch/arm/src/stm32h7/hardware/stm32_wdg.h jlange@2g-eng.com alin.jerpelea@sony.com petro.karashchenko@gmail.com arch/arm/src/stm32h7/hardware/stm32h7b3xx_flash.h javiercasas@geotab.com 101105604+simbit18@users.noreply.github.com alin.jerpelea@sony.com @@ -4301,9 +4292,6 @@ arch/arm/src/stm32h7/stm32_spi_slave.c jukka.laitinen@intel.com alin.jerpelea@so arch/arm/src/stm32h7/stm32_start.c simon@leitwert.ch xiaoxiang@xiaomi.com raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com arch/arm/src/stm32h7/stm32_start.h simon@leitwert.ch alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com arch/arm/src/stm32h7/stm32_tickless.c anthony@vergeaero.com xiaoxiang@xiaomi.com zhangyuan21@xiaomi.com gustavo.nihei@espressif.com alin.jerpelea@sony.com -arch/arm/src/stm32h7/stm32_tim.c jukka.laitinen@iki.fi anthony@vergeaero.com xiaoxiang@xiaomi.com alin.jerpelea@sony.com petro.karashchenko@gmail.com -arch/arm/src/stm32h7/stm32_tim.h jukka.laitinen@iki.fi alin.jerpelea@sony.com xiaoxiang@xiaomi.com anthony@vergeaero.com zapparello@ya.ru -arch/arm/src/stm32h7/stm32_tim_lowerhalf.c max.kriegleder@gmail.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com arch/arm/src/stm32h7/stm32_timerisr.c simon@leitwert.ch alin.jerpelea@sony.com raiden00pl@gmail.com xiaoxiang@xiaomi.com arch/arm/src/stm32h7/stm32_uart.h David.Sidrane@NscDg.com raiden00pl@gmail.com alin.jerpelea@sony.com abdelatif.guettouche@gmail.com markus.bernet@hexagon.com arch/arm/src/stm32h7/stm32_uid.c david.sidrane@nscdg.com alin.jerpelea@sony.com gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com @@ -4405,8 +4393,6 @@ arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap_legacy.h David.Sidrane@NscDg.co arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h alin.jerpelea@sony.com s.nikitenko@me.com juha.niskanen@haltian.com shen497@purdue.edu arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h alin.jerpelea@sony.com arch/arm/src/stm32l4/stm32l4.h sebastien@lorquet.fr alin.jerpelea@sony.com miha.vrhovnik@gmail.com pekka.ervasti@haltian.com -arch/arm/src/stm32l4/stm32l4_1wire.c juha.niskanen@haltian.com anjiahao@xiaomi.com abdelatif.guettouche@gmail.com xiaoxiang@xiaomi.com alin.jerpelea@sony.com -arch/arm/src/stm32l4/stm32l4_1wire.h juha.niskanen@haltian.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32l4/stm32l4_adc.c juha.niskanen@haltian.com danieloak@gmail.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com raiden00@railab.me arch/arm/src/stm32l4/stm32l4_adc.h danieloak@gmail.com juha.niskanen@haltian.com xiaoxiang@xiaomi.com alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com arch/arm/src/stm32l4/stm32l4_allocateheap.c sebastien@lorquet.fr juha.niskanen@haltian.com alin.jerpelea@sony.com dev@ziggurat29.com xiaoxiang@xiaomi.com @@ -4490,9 +4476,6 @@ arch/arm/src/stm32l4/stm32l4_spi.h sebastien@lorquet.fr alin.jerpelea@sony.com x arch/arm/src/stm32l4/stm32l4_start.c sebastien@lorquet.fr xiaoxiang@xiaomi.com alin.jerpelea@sony.com dev@ziggurat29.com arch/arm/src/stm32l4/stm32l4_start.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32l4/stm32l4_tickless.c dev@ziggurat29.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com sebastien@lorquet.fr -arch/arm/src/stm32l4/stm32l4_tim.c dev@ziggurat29.com sebastien@lorquet.fr danieloak@gmail.com godenfreemans@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32l4/stm32l4_tim.h dev@ziggurat29.com alin.jerpelea@sony.com godenfreemans@gmail.com danieloak@gmail.com xiaoxiang@xiaomi.com -arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c dev@ziggurat29.com sebastien@lorquet.fr mark@mjs.pw godenfreemans@gmail.com xiaoxiang@xiaomi.com arch/arm/src/stm32l4/stm32l4_timerisr.c sebastien@lorquet.fr alin.jerpelea@sony.com xiaoxiang@xiaomi.com mark@mjs.pw arch/arm/src/stm32l4/stm32l4_uart.h sebastien@lorquet.fr juha.niskanen@haltian.com alin.jerpelea@sony.com harri.luhtala@haltian.com jussi.kivilinna@haltian.com arch/arm/src/stm32l4/stm32l4_uid.c dev@ziggurat29.com alin.jerpelea@sony.com @@ -4557,9 +4540,6 @@ arch/arm/src/stm32l5/stm32l5_spi.c mijung@gmx.net alin.jerpelea@sony.com xiaoxia arch/arm/src/stm32l5/stm32l5_spi.h mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32l5/stm32l5_start.c mijung@gmx.net xiaoxiang@xiaomi.com alin.jerpelea@sony.com anjiahao@xiaomi.com raiden00@railab.me arch/arm/src/stm32l5/stm32l5_start.h mijung@gmx.net alin.jerpelea@sony.com -arch/arm/src/stm32l5/stm32l5_tim.c mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com anthony@vergeaero.com danieloak@gmail.com -arch/arm/src/stm32l5/stm32l5_tim.h mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com danieloak@gmail.com -arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com arch/arm/src/stm32l5/stm32l5_timerisr.c mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32l5/stm32l5_uart.h mijung@gmx.net alin.jerpelea@sony.com arch/arm/src/stm32l5/stm32l5_uid.c mijung@gmx.net alin.jerpelea@sony.com @@ -4579,7 +4559,7 @@ arch/arm/src/stm32u5/hardware/stm32_pinmap.h mijung@gmx.net cheshmedzhiev@gmail. arch/arm/src/stm32u5/hardware/stm32_pwr.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32u5/hardware/stm32_spi.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com arch/arm/src/stm32u5/hardware/stm32_syscfg.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32u5/hardware/stm32_tim.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com +arch/arm/src/stm32u5/hardware/stm32u5_tim.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32_uart.h mijung@gmx.net alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32u5xx_dbgmcu.h cheshmedzhiev@gmail.com alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h cheshmedzhiev@gmail.com devel@sumpfralle.de alin.jerpelea@sony.com @@ -4615,9 +4595,6 @@ arch/arm/src/stm32u5/stm32_spi.c mijung@gmx.net xiaoxiang@xiaomi.com anjiahao@xi arch/arm/src/stm32u5/stm32_spi.h mijung@gmx.net xiaoxiang@xiaomi.com alin.jerpelea@sony.com arch/arm/src/stm32u5/stm32_start.c mijung@gmx.net xiaoxiang@xiaomi.com anjiahao@xiaomi.com raiden00@railab.me cheshmedzhiev@gmail.com arch/arm/src/stm32u5/stm32_start.h mijung@gmx.net alin.jerpelea@sony.com -arch/arm/src/stm32u5/stm32_tim.c mijung@gmx.net xiaoxiang@xiaomi.com danieloak@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32u5/stm32_tim.h mijung@gmx.net xiaoxiang@xiaomi.com danieloak@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32u5/stm32_tim_lowerhalf.c mijung@gmx.net xiaoxiang@xiaomi.com alin.jerpelea@sony.com petro.karashchenko@gmail.com arch/arm/src/stm32u5/stm32_timerisr.c mijung@gmx.net xiaoxiang@xiaomi.com alin.jerpelea@sony.com arch/arm/src/stm32u5/stm32_uart.h mijung@gmx.net alin.jerpelea@sony.com cheshmedzhiev@gmail.com arch/arm/src/stm32u5/stm32_uid.c mijung@gmx.net alin.jerpelea@sony.com @@ -4644,7 +4621,6 @@ arch/arm/src/stm32wb/hardware/stm32wb_rcc.h s.nikitenko@me.com alin.jerpelea@son arch/arm/src/stm32wb/hardware/stm32wb_rtc.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wb_spi.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h s.nikitenko@me.com alin.jerpelea@sony.com -arch/arm/src/stm32wb/hardware/stm32wb_tim.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wb_uart.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap_legacy.h David.Sidrane@NscDg.com alin.jerpelea@sony.com @@ -4705,9 +4681,6 @@ arch/arm/src/stm32wb/stm32wb_spi.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_start.c s.nikitenko@me.com xiaoxiang@xiaomi.com anjiahao@xiaomi.com raiden00@railab.me yinshengkai@xiaomi.com arch/arm/src/stm32wb/stm32wb_start.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_tickless.c s.nikitenko@me.com zhangyuan21@xiaomi.com gustavo.nihei@espressif.com alin.jerpelea@sony.com -arch/arm/src/stm32wb/stm32wb_tim.c s.nikitenko@me.com alin.jerpelea@sony.com -arch/arm/src/stm32wb/stm32wb_tim.h s.nikitenko@me.com alin.jerpelea@sony.com -arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_timerisr.c s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_uart.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_uid.c s.nikitenko@me.com alin.jerpelea@sony.com @@ -4757,9 +4730,6 @@ arch/arm/src/stm32wl5/stm32wl5_spi.c 49699333+dependabot[bot]@users.noreply.gith arch/arm/src/stm32wl5/stm32wl5_spi.h 49699333+dependabot[bot]@users.noreply.github.com alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_start.c michal.lyszczek@bofc.pl xiaoxiang@xiaomi.com raiden00@railab.me yinshengkai@xiaomi.com alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_start.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com -arch/arm/src/stm32wl5/stm32wl5_tim.c michal.lyszczek@bofc.pl xiaoxiang@xiaomi.com danieloak@gmail.com alin.jerpelea@sony.com huangqi3@xiaomi.com -arch/arm/src/stm32wl5/stm32wl5_tim.h michal.lyszczek@bofc.pl xiaoxiang@xiaomi.com danieloak@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c michal.lyszczek@bofc.pl xiaoxiang@xiaomi.com alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_timerisr.c michal.lyszczek@bofc.pl alin.jerpelea@sony.com huangqi3@xiaomi.com arch/arm/src/stm32wl5/stm32wl5_uart.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_uid.c michal.lyszczek@bofc.pl alin.jerpelea@sony.com diff --git a/Documentation/guides/stm32_ports.rst b/Documentation/guides/stm32_ports.rst index 70d0d207e72c3..50b445c24144e 100644 --- a/Documentation/guides/stm32_ports.rst +++ b/Documentation/guides/stm32_ports.rst @@ -194,6 +194,47 @@ move to the matching family directory:: arch/arm/src/stm32 -> stm32f1, stm32f2, stm32f3, stm32f4, stm32g4, stm32l1 boards/arm/stm32 -> boards/arm/stm32{f1,f2,f3,f4,g4,l1} +Timer (TIM) IP cores +==================== + +All STM32 general-purpose and advanced-control timers share essentially one +register-compatible IP design. The ``STM32_HAVE_IP_TIMERS_*`` selectors only +distinguish minor register-map revisions, and they are largely upward +compatible - a more advanced version adds a few register bits and features but +keeps the same programming model: + +========== ================================= ================================= +IP core Selector Families +========== ================================= ================================= +M0_V1 ``STM32_HAVE_IP_TIMERS_M0_V1`` Cortex-M0 (C0, F0, G0, L0) +M3M4_V1 ``STM32_HAVE_IP_TIMERS_M3M4_V1`` F1, F2, F4, L1, F37x +M3M4_V2 ``STM32_HAVE_IP_TIMERS_M3M4_V2`` F30x, F33x +M3M4_V3 ``STM32_HAVE_IP_TIMERS_M3M4_V3`` G4 +========== ================================= ================================= + +Families with their own timer register driver (F7, H7, H5, L4, L5, U5, WB, +WL5) implement the same ``STM32_TIM_*`` programming model and are being folded +onto the common driver as their headers are normalized. + +The one functional difference that matters to a generic timer user is the +**counter width**. Every timer is 16-bit except TIM2 and TIM5, which are +32-bit on most families. Because counter width does not follow the IP-core +version (e.g. TIM2 is 16-bit on F1 but 32-bit on F4, both ``M3M4_V1``), it is +carried by its own capability flags rather than by the IP selector or a chip +``#ifdef``: + +============================ =================================================== +Capability flag Meaning +============================ =================================================== +``STM32_HAVE_TIM2_32BITS`` TIM2 is a 32-bit counter on this family. +``STM32_HAVE_TIM5_32BITS`` TIM5 is a 32-bit counter on this family. +============================ =================================================== + +These are prompt-less ``bool`` flags in ``Kconfig.have`` (the default is 16-bit) +that the chip Kconfig ``select``-s next to its timer IP-core selector. The +16-bit cases - TIM2 on STM32F10xx/STM32L15xx, TIM5 on STM32F10xx/STM32F30xx, +and every timer on the Cortex-M0 ``M0_V1`` IP - simply leave them unset. + Family peripheral inventory =========================== @@ -227,7 +268,7 @@ RCC to be done arch/arm/src/stm32c0/stm32_rcc.c RTC RTCC M0 not supported SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c SYSCFG to be done not supported -TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c +TIM v1 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v4 arch/arm/src/common/stm32/stm32_serial_m0_v4.c USB device not supported WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c @@ -255,7 +296,7 @@ RCC to be done arch/arm/src/stm32f0/stm32_rcc.c RTC RTCC M0 not supported SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c SYSCFG to be done not supported -TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c +TIM v1 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/common/stm32/stm32_serial_m0_v3.c USB device arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c @@ -285,7 +326,7 @@ RCC to be done arch/arm/src/stm32f1/stm32_rcc.c RTC counter arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c SDIO v1 arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c SPI/I2S v1 arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c -TIM v1 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +TIM v1 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v1 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c USB device/OTG FS arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -315,7 +356,7 @@ RNG v1 arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c RTC RTCC v1 arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c SDIO v1 arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c -TIM v1 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +TIM v1 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v2 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c USB OTG FS/HS arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -345,7 +386,7 @@ RTC RTCC v1 arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerh SDADC v1 arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c SPI/I2S v3 arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c SYSCFG v1 not supported -TIM v1 or v2 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +TIM v1 or v2 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c USB device arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -378,7 +419,7 @@ RNG v1 arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c RTC RTCC F4 arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c SDIO v1 arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c -TIM v1 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +TIM v1 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v2 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c USB OTG FS/HS arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -409,7 +450,7 @@ RCC to be done arch/arm/src/stm32g4/stm32_rcc.c RNG v1 arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c RTC RTCC v1 arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c SPI/I2S v3 arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c -TIM v3 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +TIM v3 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v4 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c USB device arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -441,12 +482,11 @@ RTC to be done arch/arm/src/stm32l4/stm32l4_rtc.c SAI to be done arch/arm/src/stm32l4/stm32l4_sai.c SDMMC to be done arch/arm/src/stm32l4/stm32l4_sdmmc.c SPI/I2S to be done arch/arm/src/stm32l4/stm32l4_spi.c -TIM to be done arch/arm/src/stm32l4/stm32l4_tim.c +TIM to be done arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32l4/stm32l4_serial.c USB OTG FS arch/arm/src/stm32l4/stm32l4_otgfsdev.c PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c PWM n/a arch/arm/src/stm32l4/stm32l4_pwm.c -QENCODER n/a arch/arm/src/stm32l4/stm32l4_qencoder.c USB host n/a arch/arm/src/stm32l4/stm32l4_otgfshost.c ============ ============ ============================================ @@ -476,7 +516,7 @@ RNG to be done arch/arm/src/stm32f7/stm32_rng.c RTC to be done arch/arm/src/stm32f7/stm32_rtc.c SDMMC to be done arch/arm/src/stm32f7/stm32_sdmmc.c SPI/I2S to be done arch/arm/src/stm32f7/stm32_i2s.c -TIM to be done arch/arm/src/stm32f7/stm32_tim.c +TIM to be done arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32f7/stm32_serial.c USB OTG FS/HS arch/arm/src/stm32f7/stm32_otgdev.c WWDG v1 not supported @@ -485,7 +525,6 @@ CAPTURE n/a arch/arm/src/stm32f7/stm32_capture.c FOC n/a arch/arm/src/stm32f7/stm32_foc.c PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c PWM n/a arch/arm/src/stm32f7/stm32_pwm.c -QENCODER n/a arch/arm/src/stm32f7/stm32_qencoder.c SAI n/a arch/arm/src/stm32f7/stm32_sai.c USB host n/a arch/arm/src/stm32f7/stm32_otghost.c ============ ============ ============================================ @@ -513,7 +552,7 @@ RNG v1 arch/arm/src/common/stm32/stm32_rng_m0_v1.c RTC RTCC M0 not supported SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c SYSCFG to be done not supported -TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c +TIM v1 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v4 arch/arm/src/common/stm32/stm32_serial_m0_v4.c USB device arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c @@ -541,7 +580,7 @@ OCTOSPI to be done arch/arm/src/stm32h5/stm32_qspi.c PWR to be done arch/arm/src/stm32h5/stm32_pwr.c RCC to be done arch/arm/src/stm32h5/stm32_rcc.c SPI/I2S to be done arch/arm/src/stm32h5/stm32_spi.c -TIM to be done arch/arm/src/stm32h5/stm32_tim.c +TIM to be done arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32h5/stm32_serial.c USB FS arch/arm/src/stm32h5/stm32_usbfs.c PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c @@ -579,7 +618,7 @@ RNG to be done arch/arm/src/stm32h7/stm32_rng.c RTC to be done arch/arm/src/stm32h7/stm32_rtc.c SDMMC to be done arch/arm/src/stm32h7/stm32_sdmmc.c SPI/I2S to be done arch/arm/src/stm32h7/stm32_spi.c -TIM to be done arch/arm/src/stm32h7/stm32_tim.c +TIM to be done arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v4 arch/arm/src/stm32h7/stm32_serial.c USB OTG FS/HS arch/arm/src/stm32h7/stm32_otgdev.c WWDG v1 arch/arm/src/stm32h7/stm32_wwdg.c @@ -589,7 +628,6 @@ CAPTURE n/a arch/arm/src/stm32h7/stm32_capture.c LPTIM n/a arch/arm/src/stm32h7/stm32_lptim.c PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c PWM n/a arch/arm/src/stm32h7/stm32_pwm.c -QENCODER n/a arch/arm/src/stm32h7/stm32_qencoder.c USB host n/a arch/arm/src/stm32h7/stm32_otghost.c ============ ============ ============================================ @@ -613,7 +651,7 @@ RCC to be done arch/arm/src/stm32l0/stm32_rcc.c RNG v1 arch/arm/src/common/stm32/stm32_rng_m0_v1.c RTC RTCC M0 not supported SPI/I2S v1 arch/arm/src/common/stm32/stm32_spi_m0_v1.c -TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c +TIM v1 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/common/stm32/stm32_serial_m0_v3.c USB device arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c @@ -642,7 +680,7 @@ RCC to be done arch/arm/src/stm32l1/stm32_rcc.c RTC RTCC L1 arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c SDIO v1 arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c SPI/I2S v1 arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c -TIM v1 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +TIM v1 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v2 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c USB device arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -670,7 +708,7 @@ RNG to be done not supported RTC to be done not supported SDMMC to be done not supported SPI/I2S to be done arch/arm/src/stm32l5/stm32l5_spi.c -TIM/LPTIM to be done arch/arm/src/stm32l5/stm32l5_tim.c +TIM/LPTIM to be done arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32l5/stm32l5_serial.c USB device not supported ============ ============ ======================================== @@ -723,7 +761,7 @@ SAES/AES to be done not supported SDMMC to be done not supported SPI/I2S to be done arch/arm/src/stm32u5/stm32_spi.c TAMP to be done not supported -TIM/LPTIM to be done arch/arm/src/stm32u5/stm32_tim.c +TIM/LPTIM to be done arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32u5/stm32_serial.c USB device not supported ============ ============ ====================================== @@ -749,7 +787,7 @@ RCC to be done arch/arm/src/stm32wb/stm32wb_rcc.c RNG to be done not supported RTC to be done arch/arm/src/stm32wb/stm32wb_rtc.c SPI/I2S to be done arch/arm/src/stm32wb/stm32wb_spi.c -TIM/LPTIM to be done arch/arm/src/stm32wb/stm32wb_tim.c +TIM/LPTIM to be done arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v4 arch/arm/src/stm32wb/stm32wb_serial.c USB device not supported ============ ============ ======================================== @@ -775,7 +813,7 @@ RCC to be done arch/arm/src/stm32wl5/stm32wl5_rcc.c RNG to be done not supported RTC to be done not supported SPI/I2S to be done arch/arm/src/stm32wl5/stm32wl5_spi.c -TIM/LPTIM to be done arch/arm/src/stm32wl5/stm32wl5_tim.c +TIM/LPTIM to be done arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32wl5/stm32wl5_serial.c USB to be done not supported ============ ============ ========================================== diff --git a/arch/arm/include/stm32c0/irq.h b/arch/arm/include/stm32c0/irq.h index aba16028025fb..6088325be6d9b 100644 --- a/arch/arm/include/stm32c0/irq.h +++ b/arch/arm/include/stm32c0/irq.h @@ -86,8 +86,8 @@ #define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ #define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ #define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ #define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ #define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ diff --git a/arch/arm/include/stm32f0/irq.h b/arch/arm/include/stm32f0/irq.h index c142f9068bef7..02cb919f01dc2 100644 --- a/arch/arm/include/stm32f0/irq.h +++ b/arch/arm/include/stm32f0/irq.h @@ -91,8 +91,8 @@ #define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ #define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ #define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ #define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ #define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ diff --git a/arch/arm/include/stm32g0/irq.h b/arch/arm/include/stm32g0/irq.h index 1edbcd2b85070..9eb1c521ac049 100644 --- a/arch/arm/include/stm32g0/irq.h +++ b/arch/arm/include/stm32g0/irq.h @@ -119,8 +119,8 @@ # define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ #endif -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ defined(CONFIG_ARCH_CHIP_STM32G070RB) diff --git a/arch/arm/include/stm32h5/stm32h5xx_irq.h b/arch/arm/include/stm32h5/stm32h5xx_irq.h index 5550c7e5b9934..d1bb041a24348 100644 --- a/arch/arm/include/stm32h5/stm32h5xx_irq.h +++ b/arch/arm/include/stm32h5/stm32h5xx_irq.h @@ -88,10 +88,10 @@ # define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ # define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ # define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -# define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ -# define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -# define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -# define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +# define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +# define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +# define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +# define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ # define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ # define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ # define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ @@ -112,10 +112,10 @@ # define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 62) /* 62: UART5 global interrupt */ # define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 63) /* 63: LPUART1 global interrupt */ # define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 64) /* 64: LPTIM1 global interrupt */ -# define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */ -# define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */ -# define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */ -# define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */ +# define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */ +# define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */ +# define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */ +# define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */ # define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */ # define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */ # define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */ diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index aab8d5531096e..5a0608d1ee379 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -247,6 +247,9 @@ # error STM32 H7 chip Family not identified #endif +#define STM32_NATIM 2 /* Advanced timers TIM1 and TIM8 */ +#define STM32_NBTIM 2 /* Basic timers TIM6 and TIM7 */ + /* TBD FPU Configuration */ #if defined(CONFIG_ARCH_HAVE_FPU) diff --git a/arch/arm/include/stm32l5/stm32l562xx_irq.h b/arch/arm/include/stm32l5/stm32l562xx_irq.h index 35e326d15b003..b60e9e852446f 100644 --- a/arch/arm/include/stm32l5/stm32l562xx_irq.h +++ b/arch/arm/include/stm32l5/stm32l562xx_irq.h @@ -91,20 +91,20 @@ #define STM32_IRQ_DAC (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ #define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ #define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ #define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ #define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ #define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ diff --git a/arch/arm/include/stm32n6/stm32n6xx_irq.h b/arch/arm/include/stm32n6/stm32n6xx_irq.h index ef186921d2791..71af964ef67ab 100644 --- a/arch/arm/include/stm32n6/stm32n6xx_irq.h +++ b/arch/arm/include/stm32n6/stm32n6xx_irq.h @@ -145,20 +145,20 @@ #define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 109) /* 109: I3C1 error interrupt */ #define STM32_IRQ_I3C2_EV (STM32_IRQ_FIRST + 110) /* 110: I3C2 event interrupt */ #define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 111) /* 111: I3C2 error interrupt */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 112) /* 112: TIM1 Break interrupt */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 113) /* 113: TIM1 Update interrupt */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 114) /* 114: TIM1 Trigger and Commutation interrupt */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 115) /* 115: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 112) /* 112: TIM1 Break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 113) /* 113: TIM1 Update interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 114) /* 114: TIM1 Trigger and Commutation interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 115) /* 115: TIM1 Capture Compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 116) /* 116: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 117) /* 117: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 118) /* 118: TIM4 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 119) /* 119: TIM5 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 120) /* 120: TIM6 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 121) /* 121: TIM7 global interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 122) /* 122: TIM8 Break interrupt */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 123) /* 123: TIM8 Update interrupt */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 124) /* 124: TIM8 Trigger and Commutation interrupt */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 125) /* 125: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 122) /* 122: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 123) /* 123: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 124) /* 124: TIM8 Trigger and Commutation interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 125) /* 125: TIM8 Capture Compare interrupt */ #define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 126) /* 126: TIM9 global interrupt */ #define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 127) /* 127: TIM10 global interrupt */ #define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 128) /* 128: TIM11 global interrupt */ diff --git a/arch/arm/include/stm32u5/stm32u5xx_irq.h b/arch/arm/include/stm32u5/stm32u5xx_irq.h index e29a074fde6a5..6e5d2b4f12a9a 100644 --- a/arch/arm/include/stm32u5/stm32u5xx_irq.h +++ b/arch/arm/include/stm32u5/stm32u5xx_irq.h @@ -90,28 +90,28 @@ #define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC1 global interrupt */ #define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1 Interrupt 0 */ #define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1 Interrupt 1 */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ #define STM32_IRQ_TIM1_TERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 transition error */ #define STM32_IRQ_TIM1_IERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 index error */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ #define STM32_IRQ_TIM1_DIR (STM32_IRQ_FIRST + 43) /* 43: TIM1 direction change interrupt */ #define STM32_IRQ_TIM1_IDX (STM32_IRQ_FIRST + 43) /* 43: TIM1 index */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ #define STM32_IRQ_TIM8_TERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 transition error */ #define STM32_IRQ_TIM8_IERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 index error */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ #define STM32_IRQ_TIM8_DIR (STM32_IRQ_FIRST + 53) /* 53: TIM8 direction change interrupt */ #define STM32_IRQ_TIM8_IDX (STM32_IRQ_FIRST + 53) /* 53: TIM8 index */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ #define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ #define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ #define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ diff --git a/arch/arm/include/stm32wb/chip.h b/arch/arm/include/stm32wb/chip.h index 6945832aab647..74d7d27c65b72 100644 --- a/arch/arm/include/stm32wb/chip.h +++ b/arch/arm/include/stm32wb/chip.h @@ -47,6 +47,8 @@ # define STM32_NGTIM16 0 /* No 16-bit general timers */ #endif +#define STM32_NGTIM (STM32_NGTIM16 + STM32_NGTIM32) + #if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_NDMA 2 /* DMA1-2 with 7 channels each */ # define STM32_NI2S 1 /* SAI1 (dual channel high quality audio) */ diff --git a/arch/arm/include/stm32wl5/chip.h b/arch/arm/include/stm32wl5/chip.h index 95761ec558f53..094bfd2829c63 100644 --- a/arch/arm/include/stm32wl5/chip.h +++ b/arch/arm/include/stm32wl5/chip.h @@ -44,6 +44,7 @@ # define STM32_NATIM 1 /* One advanced timer TIM1 */ # define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ # define STM32_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ +# define STM32_NBTIM 0 /* No basic timers */ # define STM32_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */ # define STM32_NRNG 1 /* Random number generator (RNG) */ # define STM32_NUSART 2 /* USART 1-2 */ diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index c2299ee530abf..8889d1eb1fc33 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -33,11 +33,35 @@ set(SRCS) list(APPEND SRCS stm32_waste.c) list(APPEND SRCS stm32_uid.c) +list(APPEND SRCS stm32_lsi.c) + +if(CONFIG_TIMER AND CONFIG_STM32_TIM) + list(APPEND SRCS stm32_tim_lowerhalf.c) +endif() + +if(CONFIG_STM32_TIM) + list(APPEND SRCS stm32_tim.c) +endif() + +if(CONFIG_STM32_FREERUN) + list(APPEND SRCS stm32_freerun.c) +endif() + +if(CONFIG_STM32_ONESHOT) + list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) +endif() +if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE) + list(APPEND SRCS stm32_qencoder.c) +endif() if(CONFIG_STM32_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() +if(CONFIG_STM32_1WIREDRIVER) + list(APPEND SRCS stm32_1wire_m3m4_v1.c) +endif() + if(CONFIG_STM32_COMMON_LEGACY) list( APPEND @@ -45,7 +69,6 @@ if(CONFIG_STM32_COMMON_LEGACY) stm32_allocateheap_m3m4_v1.c stm32_start_m3m4_v1.c stm32_lse_m3m4_v1.c - stm32_lsi_m3m4_v1.c stm32_irq_m3m4_v1.c stm32_capture_m3m4_v1.c) @@ -72,10 +95,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_sdio_m3m4_v1.c) endif() - if(CONFIG_STM32_HAVE_IP_TIMERS) - list(APPEND SRCS stm32_tim_m3m4_v1v2v3.c) - endif() - if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) list(APPEND SRCS stm32_ccm_m3m4_v1.c) endif() @@ -147,18 +166,6 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() endif() - if(CONFIG_TIMER AND CONFIG_STM32_HAVE_IP_TIMERS) - list(APPEND SRCS stm32_tim_m3m4_v1v2v3_lowerhalf.c) - endif() - - if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c) - endif() - - if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32_freerun_m3m4_v1.c) - endif() - if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) if(CONFIG_STM32_I2C_ALT) list(APPEND SRCS stm32_i2c_m3m4_v1_alt.c) @@ -261,10 +268,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_hrtim_m3m4_v1.c) endif() - if(CONFIG_STM32_1WIREDRIVER) - list(APPEND SRCS stm32_1wire_m3m4_v1.c) - endif() - if(CONFIG_STM32_HCIUART) list(APPEND SRCS stm32_hciuart_m3m4_v1.c) endif() @@ -289,10 +292,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c) endif() - if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE) - list(APPEND SRCS stm32_qencoder_m3m4_v1v2v3.c) - endif() - if(CONFIG_STM32_CAN AND CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can_m3m4_v1.c) @@ -356,7 +355,7 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() if(CONFIG_ARCH_CORTEXM0) - list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c stm32_lsi_m0_v1.c) + list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c) if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) list(APPEND SRCS stm32_gpio_m0_v1.c) @@ -462,10 +461,6 @@ if(CONFIG_ARCH_CORTEXM0) list(APPEND SRCS stm32_rng_m0_v1.c) endif() - if(CONFIG_STM32_TIM AND CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) - list(APPEND SRCS stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c) - endif() - if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) list(APPEND SRCS stm32_iwdg_m0_v1.c) endif() @@ -483,9 +478,6 @@ if(CONFIG_ARCH_CORTEXM0) endif() endif() - if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder_m0_v1.c) - endif() endif() if(CONFIG_SENSORS_HALL3PHASE) diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index d6cd3b31e073b..881d36fc21e00 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -1007,6 +1007,19 @@ config STM32_HAVE_TIM19 config STM32_HAVE_TIM20 bool +# Timer counter width. TIM2 and TIM5 are 32-bit on most families; these +# capability flags carry that per-family knowledge so the common timer +# lower-half driver does not need chip-line #ifdefs. A family whose TIM2 or +# TIM5 is 32-bit selects the matching flag from its chip Kconfig; every other +# timer (and the 16-bit STM32F10xx/STM32L15xx/STM32F30xx/Cortex-M0 lines) is +# left at the default 16-bit width. + +config STM32_HAVE_TIM2_32BITS + bool + +config STM32_HAVE_TIM5_32BITS + bool + config STM32_HAVE_LPTIM1 bool diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 686a84e4d731a..91a05f6543583 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -41,17 +41,38 @@ ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) CHIP_CSRCS += stm32_waste.c CHIP_CSRCS += stm32_uid.c +CHIP_CSRCS += stm32_lsi.c + +ifeq ($(CONFIG_TIMER)$(CONFIG_STM32_TIM),yy) +CHIP_CSRCS += stm32_tim_lowerhalf.c +endif +ifeq ($(CONFIG_STM32_TIM),y) +CHIP_CSRCS += stm32_tim.c +endif +ifeq ($(CONFIG_STM32_FREERUN),y) +CHIP_CSRCS += stm32_freerun.c +endif +ifeq ($(CONFIG_STM32_ONESHOT),y) +CHIP_CSRCS += stm32_oneshot.c +CHIP_CSRCS += stm32_oneshot_lowerhalf.c +endif +ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy) +CHIP_CSRCS += stm32_qencoder.c +endif ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) +CHIP_CSRCS += stm32_1wire_m3m4_v1.c +endif + ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c CHIP_CSRCS += stm32_start_m3m4_v1.c CHIP_CSRCS += stm32_lse_m3m4_v1.c -CHIP_CSRCS += stm32_lsi_m3m4_v1.c CHIP_CSRCS += stm32_irq_m3m4_v1.c ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ $(CONFIG_STM32_HAVE_IP_USART_V2) \ @@ -87,9 +108,6 @@ endif ifeq ($(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1),y) CHIP_CSRCS += stm32_sdio_m3m4_v1.c endif -ifeq ($(CONFIG_STM32_HAVE_IP_TIMERS),y) -CHIP_CSRCS += stm32_tim_m3m4_v1v2v3.c -endif ifeq ($(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1),y) CHIP_CSRCS += stm32_ccm_m3m4_v1.c endif @@ -148,18 +166,7 @@ CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c endif endif -ifeq ($(CONFIG_TIMER)$(CONFIG_STM32_HAVE_IP_TIMERS),yy) -CHIP_CSRCS += stm32_tim_m3m4_v1v2v3_lowerhalf.c -endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32_oneshot_m3m4_v1.c -CHIP_CSRCS += stm32_oneshot_m3m4_v1_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32_freerun_m3m4_v1.c -endif ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) ifeq ($(CONFIG_STM32_I2C_ALT),y) @@ -290,10 +297,6 @@ CHIP_CSRCS += stm32_hrtim_m3m4_v1.c endif endif -ifeq ($(CONFIG_STM32_1WIREDRIVER),y) -CHIP_CSRCS += stm32_1wire_m3m4_v1.c -endif - ifeq ($(CONFIG_STM32_HCIUART),y) CHIP_CSRCS += stm32_hciuart_m3m4_v1.c endif @@ -322,9 +325,6 @@ ifeq ($(CONFIG_STM32_CAP),y) CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c endif -ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy) -CHIP_CSRCS += stm32_qencoder_m3m4_v1v2v3.c -endif ifeq ($(CONFIG_STM32_CAN)$(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1),yy) ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) @@ -407,7 +407,6 @@ else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) CHIP_CSRCS += stm32_lowputc_usart_m0_v4.c endif CHIP_CSRCS += stm32_start_m0_v1.c -CHIP_CSRCS += stm32_lsi_m0_v1.c ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M0_V1),y) CHIP_CSRCS += stm32_gpio_m0_v1.c endif @@ -511,9 +510,6 @@ ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M0_V1),yy) CHIP_CSRCS += stm32_rng_m0_v1.c endif -ifeq ($(CONFIG_STM32_TIM)$(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1),yy) -CHIP_CSRCS += stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c -endif ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) CHIP_CSRCS += stm32_iwdg_m0_v1.c @@ -534,9 +530,6 @@ endif endif endif -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder_m0_v1.c -endif endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_rcc.h b/arch/arm/src/common/stm32/hardware/stm32_rcc.h deleted file mode 100644 index 308cd4d9df954..0000000000000 --- a/arch/arm/src/common/stm32/hardware/stm32_rcc.h +++ /dev/null @@ -1,69 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/hardware/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H -#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32F1) -# include "hardware/stm32f10xxx_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32F2) -# include "hardware/stm32f20xxx_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32F3) -# if defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F302X8) || \ - defined(CONFIG_STM32_STM32F302XC) || \ - defined(CONFIG_STM32_STM32F303XC) || \ - defined(CONFIG_STM32_STM32F303XE) -# include "hardware/stm32f30xxx_rcc.h" -# elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_rcc.h" -# elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_rcc.h" -# else -# error "Unsupported STM32F3 RCC" -# endif -#elif defined(CONFIG_ARCH_CHIP_STM32F4) -# include "hardware/stm32f40xxx_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G4) -# include "hardware/stm32g4xxxx_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L1) -# include "hardware/stm32l15xxx_rcc.h" -#else -# error "Unsupported STM32 RCC" -#endif - -#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/common/stm32/stm32_1wire.h b/arch/arm/src/common/stm32/stm32_1wire.h index 79f9f6d47e46f..d125a4c1b6960 100644 --- a/arch/arm/src/common/stm32/stm32_1wire.h +++ b/arch/arm/src/common/stm32/stm32_1wire.h @@ -31,8 +31,6 @@ #include -#include "stm32_uart.h" - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c index 595136c6c65d0..b5d0fad9b36e9 100644 --- a/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -45,16 +46,15 @@ #include #include #include +#include #include #include #include "arm_internal.h" -#include "stm32_rcc.h" +#include "chip.h" +#include "stm32.h" #include "stm32_1wire.h" -#include "stm32_rcc.h" - -#ifdef HAVE_1WIREDRIVER /**************************************************************************** * Pre-processor Definitions @@ -126,6 +126,9 @@ struct stm32_1wire_priv_s uint8_t *byte; /* Current byte */ uint8_t bit; /* Current bit */ volatile int result; /* Exchange result */ +#ifdef CONFIG_PM + struct pm_callback_s pm_cb; /* PM callbacks */ +#endif }; /* 1-Wire device, Instance */ @@ -166,6 +169,10 @@ static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, static int stm32_1wire_writebit(struct onewire_dev_s *dev, const uint8_t *bit); static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit); +#ifdef CONFIG_PM +static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif /**************************************************************************** * Private Data @@ -189,7 +196,10 @@ static struct stm32_1wire_priv_s stm32_1wire1_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -210,7 +220,10 @@ static struct stm32_1wire_priv_s stm32_1wire2_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -231,7 +244,10 @@ static struct stm32_1wire_priv_s stm32_1wire3_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -252,7 +268,10 @@ static struct stm32_1wire_priv_s stm32_1wire4_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -273,7 +292,10 @@ static struct stm32_1wire_priv_s stm32_1wire5_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -294,7 +316,10 @@ static struct stm32_1wire_priv_s stm32_1wire6_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -315,7 +340,10 @@ static struct stm32_1wire_priv_s stm32_1wire7_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -336,7 +364,10 @@ static struct stm32_1wire_priv_s stm32_1wire8_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -634,7 +665,11 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | - USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); + USART_CR1_PCE | USART_CR1_PS | USART_CR1_M +#ifdef USART_CR1_M1 + | USART_CR1_M1 +#endif + ); regval |= USART_CR1_RXNEIE; stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); @@ -937,7 +972,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) if ((sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) { -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#ifdef STM32_USART_ICR_OFFSET /* These errors are cleared by writing the corresponding bit to the * interrupt clear register (ICR). */ @@ -968,8 +1003,16 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) if ((sr & USART_SR_LBD) != 0) { +#ifdef STM32_USART_ICR_OFFSET + /* The LIN break flag is cleared by writing LBDCF to the interrupt + * clear register (ICR); the status register is read-only. + */ + + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF); +#else sr &= ~USART_SR_LBD; stm32_1wire_out(priv, STM32_USART_SR_OFFSET, sr); +#endif if (priv->msgs != NULL) { @@ -1143,6 +1186,78 @@ static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit) return stm32_1wire_process(priv, msgs, 1); } +/**************************************************************************** + * Name: stm32_1wire_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a + * warning that the system is about to enter into a new power state. The + * driver should begin whatever operations that may be required to enter + * power state. The driver may abort the state change mode by returning + * a non-zero value from the callback function. + * + * Input Parameters: + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state + * data at the end of the structure. + * domain - Identifies the activity domain of the state change + * pmstate - Identifies the new PM state + * + * Returned Value: + * 0 (OK) means the event was successfully processed and that the driver + * is prepared for the PM state change. Non-zero means that the driver + * is not prepared to perform the tasks needed achieve this power setting + * and will cause the state change to be aborted. NOTE: The prepare + * method will also be recalled when reverting from lower back to higher + * power consumption modes (say because another driver refused a lower + * power state change). Drivers are not permitted to return non-zero + * values when reverting back to higher power consumption modes! + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + struct stm32_1wire_priv_s *priv = + (struct stm32_1wire_priv_s *)((char *)cb - + offsetof(struct stm32_1wire_priv_s, pm_cb)); + + /* Logic to prepare for a reduced power state goes here. */ + + switch (pmstate) + { + case PM_NORMAL: + case PM_IDLE: + break; + + case PM_STANDBY: + case PM_SLEEP: + + /* Check if exclusive lock for 1-Wire bus is held. */ + + if (nxmutex_is_locked(&priv->lock)) + { + /* Exclusive lock is held, do not allow entry to deeper PM + * states. + */ + + return -EBUSY; + } + + break; + + default: + + /* Should not get here */ + + break; + } + + return OK; +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -1238,6 +1353,12 @@ struct onewire_dev_s *stm32_1wireinitialize(int port) if (priv->refs++ == 0) { stm32_1wire_init(priv); + +#ifdef CONFIG_PM + /* Register to receive power management callbacks */ + + DEBUGVERIFY(pm_register(&priv->pm_cb)); +#endif } nxmutex_unlock(&priv->lock); @@ -1282,6 +1403,13 @@ int stm32_1wireuninitialize(struct onewire_dev_s *dev) /* Disable power and other HW resource (GPIO's) */ stm32_1wire_deinit(priv); + +#ifdef CONFIG_PM + /* Unregister power management callbacks */ + + pm_unregister(&priv->pm_cb); +#endif + nxmutex_unlock(&priv->lock); /* Free instance */ @@ -1289,5 +1417,3 @@ int stm32_1wireuninitialize(struct onewire_dev_s *dev) kmm_free(dev); return OK; } - -#endif /* HAVE_1WIREDRIVER */ diff --git a/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_freerun.c similarity index 99% rename from arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c rename to arch/arm/src/common/stm32/stm32_freerun.c index e8122d5ef413c..9acf845613104 100644 --- a/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_freerun.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c + * arch/arm/src/common/stm32/stm32_freerun.c * * SPDX-License-Identifier: Apache-2.0 * @@ -298,4 +298,4 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) return OK; } -#endif /* CONFIG_STM32_ONESHOT */ +#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h index 026c6e2e7f310..d6580e8b3d323 100644 --- a/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h @@ -40,7 +40,7 @@ # include "hardware/stm32f33xxx_rcc.h" #elif defined(CONFIG_STM32_STM32G47XX) # include "hardware/stm32g47xxx_hrtim.h" -# include "hardware/stm32g4xxxx_rcc.h" +# include "hardware/stm32_rcc.h" #else # error #endif diff --git a/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c b/arch/arm/src/common/stm32/stm32_lsi.c similarity index 60% rename from arch/arm/src/common/stm32/stm32_lsi_m0_v1.c rename to arch/arm/src/common/stm32/stm32_lsi.c index 19aa04dd4f037..d9fcc98322f06 100644 --- a/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_lsi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_lsi_m0_v1.c + * arch/arm/src/common/stm32/stm32_lsi.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,22 +33,36 @@ * Pre-processor Definitions ****************************************************************************/ -/* STM32C0 uses the second CSR register for LSI. */ - -#ifdef CONFIG_ARCH_CHIP_STM32C0 -# define STM32_RCC_CSR STM32_RCC_CSR2 -# define RCC_CSR_LSION RCC_CSR2_LSION -# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY +/* The LSI enable/disable sequence is identical on every STM32, regardless of + * the CPU core. Only the register/bits that carry LSION/LSIRDY differ: + * + * - most families : RCC_CSR (LSION/LSIRDY) + * - STM32C0 : RCC_CSR2 (LSION/LSIRDY) + * - STM32WB : RCC_CSR (LSI1ON/LSI1RDY) + * - STM32H5/U5 : RCC_BDCR (LSION/LSIRDY) + * + * A single driver therefore serves all of them, selecting the register with + * the preprocessor below. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32H5) || defined(CONFIG_ARCH_CHIP_STM32U5) +# define STM32_RCC_LSI_REG STM32_RCC_BDCR +# define RCC_LSI_LSION RCC_BDCR_LSION +# define RCC_LSI_LSIRDY RCC_BDCR_LSIRDY +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# define STM32_RCC_LSI_REG STM32_RCC_CSR2 +# define RCC_LSI_LSION RCC_CSR2_LSION +# define RCC_LSI_LSIRDY RCC_CSR2_LSIRDY +#elif defined(CONFIG_ARCH_CHIP_STM32WB) +# define STM32_RCC_LSI_REG STM32_RCC_CSR +# define RCC_LSI_LSION RCC_CSR_LSI1ON +# define RCC_LSI_LSIRDY RCC_CSR_LSI1RDY +#else +# define STM32_RCC_LSI_REG STM32_RCC_CSR +# define RCC_LSI_LSION RCC_CSR_LSION +# define RCC_LSI_LSIRDY RCC_CSR_LSIRDY #endif -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -64,14 +78,14 @@ void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. + * bit in the controlling RCC register. */ - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_LSI_REG, 0, RCC_LSI_LSION); - /* Wait for the internal RC 40 kHz oscillator to be stable. */ + /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_LSI_REG) & RCC_LSI_LSIRDY) == 0); } /**************************************************************************** @@ -84,11 +98,11 @@ void stm32_rcc_enablelsi(void) void stm32_rcc_disablelsi(void) { - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. + /* Disable the Internal Low-Speed (LSI) RC Oscillator by resetting the + * LSION bit in the controlling RCC register. */ - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_LSI_REG, RCC_LSI_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c deleted file mode 100644 index 97ae757a001b7..0000000000000 --- a/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* STM32C0 uses the second CSR register for LSI. */ - -#ifdef CONFIG_ARCH_CHIP_STM32C0 -# define STM32_RCC_CSR STM32_RCC_CSR2 -# define RCC_CSR_LSION RCC_CSR2_LSION -# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal RC 40 kHz oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32h7/stm32_oneshot.c b/arch/arm/src/common/stm32/stm32_oneshot.c similarity index 84% rename from arch/arm/src/stm32h7/stm32_oneshot.c rename to arch/arm/src/common/stm32/stm32_oneshot.c index e1fc56718ec77..fa11cb6e2465b 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.c +++ b/arch/arm/src/common/stm32/stm32_oneshot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h7/stm32_oneshot.c + * arch/arm/src/common/stm32/stm32_oneshot.c * * SPDX-License-Identifier: Apache-2.0 * @@ -79,7 +79,7 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg) oneshot_handler_t oneshot_handler; void *oneshot_arg; - tmrinfo("Expired (Interrupt)...\n"); + tmrinfo("Expired...\n"); DEBUGASSERT(oneshot != NULL && oneshot->handler); /* The clock was stopped, but not disabled when the RC match occurred. @@ -185,14 +185,12 @@ int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, { uint32_t frequency; - tmrinfo("chan=%d resolution=%u usec, USEC_PER_SEC:%ld\n", chan, resolution, - USEC_PER_SEC); + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); DEBUGASSERT(oneshot && resolution > 0); /* Get the TC frequency the corresponds to the requested resolution */ frequency = USEC_PER_SEC / (uint32_t)resolution; - tmrinfo("frequency: %" PRIu32 "\n", frequency); oneshot->frequency = frequency; oneshot->tch = stm32_tim_init(chan); @@ -228,8 +226,6 @@ int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); - tmrinfo("frequency: %" PRIu32 ", USEC_PER_SEC: %ld\n", oneshot->frequency, - USEC_PER_SEC); *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * (uint64_t)USEC_PER_SEC; return OK; @@ -263,8 +259,8 @@ int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, uint64_t period; irqstate_t flags; - tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", handler, arg, - (intmax_t)ts->tv_sec, ts->tv_nsec); + tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", + handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); DEBUGASSERT(oneshot && handler && ts); DEBUGASSERT(oneshot->tch); @@ -356,6 +352,11 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts) { irqstate_t flags; + uint64_t usec; + uint64_t sec; + uint64_t nsec; + uint32_t count; + uint32_t period; /* Was the timer running? */ @@ -373,8 +374,22 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, return OK; } + /* Yes.. Get the timer counter and period registers and stop the counter. + * If the counter expires while we are doing this, the counter clock will + * be stopped, but the clock will not be disabled. + * + * The expected behavior is that the counter register will freezes at + * a value equal to the RC register when the timer expires. The counter + * should have values between 0 and RC in all other cased. + * + * REVISIT: This does not appear to be the case. + */ + tmrinfo("Cancelling...\n"); + count = STM32_TIM_GETCOUNTER(oneshot->tch); + period = oneshot->period; + /* Now we can disable the interrupt and stop the timer. */ STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); @@ -392,10 +407,49 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, if (ts) { - /* Not implemented */ + /* Yes.. then calculate and return the time remaining on the + * oneshot timer. + */ - ts->tv_sec = 0; - ts->tv_nsec = 0; + tmrinfo("period=%lu count=%lu\n", + (unsigned long)period, (unsigned long)count); + + /* REVISIT: I am not certain why the timer counter value sometimes + * exceeds RC. Might be a bug, or perhaps the counter does not stop + * in all cases. + */ + + if (count >= period) + { + /* No time remaining (?) */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + else + { + /* The total time remaining is the difference. Convert that + * to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / + oneshot->frequency; + + /* Return the time remaining in the correct form */ + + sec = usec / USEC_PER_SEC; + nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + ts->tv_sec = sec; + ts->tv_nsec = nsec; + } + + tmrinfo("remaining (%jd, %ld)\n", + (intmax_t)ts->tv_sec, ts->tv_nsec); } return OK; diff --git a/arch/arm/src/stm32h7/stm32_oneshot_lowerhalf.c b/arch/arm/src/common/stm32/stm32_oneshot_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32h7/stm32_oneshot_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_oneshot_lowerhalf.c index edec93ec7ecc5..d7aa7dd6d60c7 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_oneshot_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h7/stm32_oneshot_lowerhalf.c + * arch/arm/src/common/stm32/stm32_oneshot_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c deleted file mode 100644 index e8ba155e9daf7..0000000000000 --- a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c +++ /dev/null @@ -1,458 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "stm32_oneshot.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_oneshot_handler(int irg_num, void * context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Common timer interrupt callback. When any oneshot timer interrupt - * expires, this function will be called. It will forward the call to - * the next level up. - * - * Input Parameters: - * oneshot - The state associated with the expired timer - * - * Returned Value: - * Always returns OK - * - ****************************************************************************/ - -static int stm32_oneshot_handler(int irg_num, void * context, void *arg) -{ - struct stm32_oneshot_s * oneshot = (struct stm32_oneshot_s *) arg; - oneshot_handler_t oneshot_handler; - void *oneshot_arg; - - tmrinfo("Expired...\n"); - DEBUGASSERT(oneshot != NULL && oneshot->handler); - - /* The clock was stopped, but not disabled when the RC match occurred. - * Disable the TC now and disable any further interrupts. - */ - - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - - /* The timer is no longer running */ - - oneshot->running = false; - - /* Forward the event, clearing out any vestiges */ - - oneshot_handler = (oneshot_handler_t)oneshot->handler; - oneshot->handler = NULL; - oneshot_arg = (void *)oneshot->arg; - oneshot->arg = NULL; - - oneshot_handler(oneshot_arg); - return OK; -} - -/**************************************************************************** - * Name: stm32_allocate_handler - * - * Description: - * Allocate a timer callback handler for the oneshot instance. - * - * Input Parameters: - * oneshot - The state instance the new oneshot timer - * - * Returned Value: - * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. - * - ****************************************************************************/ - -static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) -{ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - int ret = -EBUSY; - int i; - - /* Search for an unused handler */ - - for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) - { - /* Is this handler available? */ - - if (g_oneshot[i] == NULL) - { - /* Yes... assign it to this oneshot */ - - g_oneshot[i] = oneshot; - oneshot->cbndx = i; - ret = OK; - break; - } - } - - return ret; - -#else - if (g_oneshot[0] == NULL) - { - g_oneshot[0] = oneshot; - return OK; - } - - return -EBUSY; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(oneshot && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - oneshot->frequency = frequency; - - oneshot->tch = stm32_tim_init(chan); - if (!oneshot->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(oneshot->tch, frequency); - - /* Initialize the remaining fields in the state structure. */ - - oneshot->chan = chan; - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - - /* Assign a callback handler to the oneshot */ - - return stm32_allocate_handler(oneshot); -} - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) -{ - DEBUGASSERT(oneshot != NULL && usec != NULL); - - *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * - (uint64_t)USEC_PER_SEC; - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts) -{ - uint64_t usec; - uint64_t period; - irqstate_t flags; - - tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", - handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); - DEBUGASSERT(oneshot && handler && ts); - DEBUGASSERT(oneshot->tch); - - /* Was the oneshot already running? */ - - flags = enter_critical_section(); - if (oneshot->running) - { - /* Yes.. then cancel it */ - - tmrinfo("Already running... cancelling\n"); - stm32_oneshot_cancel(oneshot, NULL); - } - - /* Save the new handler and its argument */ - - oneshot->handler = handler; - oneshot->arg = arg; - - /* Express the delay in microseconds */ - - usec = ts->tv_sec * USEC_PER_SEC + - (ts->tv_nsec / NSEC_PER_USEC); - - /* Get the timer counter frequency and determine the number of counts need - * to achieve the requested delay. - * - * frequency = ticks / second - * ticks = seconds * frequency - * = (usecs * frequency) / USEC_PER_SEC; - */ - - period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; - - tmrinfo("usec=%llu period=%08llx\n", usec, period); - DEBUGASSERT(period <= UINT32_MAX); - - /* Set up to receive the callback when the interrupt occurs */ - - STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); - - /* Set timer period */ - - oneshot->period = (uint32_t)period; - STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); - - /* Start the counter */ - - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); - - /* Enable interrupts. We should get the callback when the interrupt - * occurs. - */ - - oneshot->running = true; - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. ts may be zero in which case the time remaining - * is not returned. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts) -{ - irqstate_t flags; - uint64_t usec; - uint64_t sec; - uint64_t nsec; - uint32_t count; - uint32_t period; - - /* Was the timer running? */ - - flags = enter_critical_section(); - if (!oneshot->running) - { - /* No.. Just return zero timer remaining and successful cancellation. - * This function may execute at a high rate with no timer running - * (as when pre-emption is enabled and disabled). - */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - leave_critical_section(flags); - return OK; - } - - /* Yes.. Get the timer counter and period registers and stop the counter. - * If the counter expires while we are doing this, the counter clock will - * be stopped, but the clock will not be disabled. - * - * The expected behavior is that the counter register will freezes at - * a value equal to the RC register when the timer expires. The counter - * should have values between 0 and RC in all other cased. - * - * REVISIT: This does not appear to be the case. - */ - - tmrinfo("Cancelling...\n"); - - count = STM32_TIM_GETCOUNTER(oneshot->tch); - period = oneshot->period; - - /* Now we can disable the interrupt and stop the timer. */ - - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - leave_critical_section(flags); - - /* Did the caller provide us with a location to return the time - * remaining? - */ - - if (ts) - { - /* Yes.. then calculate and return the time remaining on the - * oneshot timer. - */ - - tmrinfo("period=%lu count=%lu\n", - (unsigned long)period, (unsigned long)count); - - /* REVISIT: I am not certain why the timer counter value sometimes - * exceeds RC. Might be a bug, or perhaps the counter does not stop - * in all cases. - */ - - if (count >= period) - { - /* No time remaining (?) */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - } - else - { - /* The total time remaining is the difference. Convert that - * to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / - oneshot->frequency; - - /* Return the time remaining in the correct form */ - - sec = usec / USEC_PER_SEC; - nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - ts->tv_sec = sec; - ts->tv_nsec = nsec; - } - - tmrinfo("remaining (%jd, %ld)\n", - (intmax_t)ts->tv_sec, ts->tv_nsec); - } - - return OK; -} - -#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c deleted file mode 100644 index 729adb4078c3e..0000000000000 --- a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c +++ /dev/null @@ -1,309 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_oneshot.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of the oneshot timer lower-half driver - */ - -struct stm32_oneshot_lowerhalf_s -{ - /* This is the part of the lower half driver that is visible to the upper- - * half client of the driver. This must be the first thing in this - * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. - */ - - struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ - - /* Private lower half data follows */ - - struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg); - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts); -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Lower half operations */ - -static const struct oneshot_operations_s g_oneshot_ops = -{ - .max_delay = stm32_max_delay, - .start = stm32_start, - .cancel = stm32_cancel, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Timer expiration handler - * - * Input Parameters: - * arg - Should be the same argument provided when stm32_oneshot_start() - * was called. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Perhaps the callback was nullified in a race condition with - * stm32_cancel? - */ - - oneshot_process_callback(&priv->lh); -} - -/**************************************************************************** - * Name: stm32_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the maximum delay. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - uint64_t usecs; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); - if (ret >= 0) - { - uint64_t sec = usecs / 1000000; - usecs -= 1000000 * sec; - - ts->tv_sec = sec; - ts->tv_nsec = usecs * 1000; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - - /* Save the callback information and start the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_start(&priv->oneshot, - stm32_oneshot_handler, priv, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * lower Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL); - - /* Cancel the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_cancel(&priv->oneshot, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: oneshot_initialize - * - * Description: - * Initialize the oneshot timer and return a oneshot lower half driver - * instance. - * - * Input Parameters: - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * On success, a non-NULL instance of the oneshot lower-half driver is - * returned. NULL is return on any failure. - * - ****************************************************************************/ - -struct oneshot_lowerhalf_s *oneshot_initialize(int chan, - uint16_t resolution) -{ - struct stm32_oneshot_lowerhalf_s *priv; - int ret; - - /* Allocate an instance of the lower half driver */ - - priv = (struct stm32_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); - - if (priv == NULL) - { - tmrerr("ERROR: Failed to initialized state structure\n"); - return NULL; - } - - /* Initialize the lower-half driver structure */ - - priv->lh.ops = &g_oneshot_ops; - - /* Initialize the contained STM32 oneshot timer */ - - ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); - kmm_free(priv); - return NULL; - } - - return &priv->lh; -} diff --git a/arch/arm/src/common/stm32/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount.c index 0927f3c4ee7b7..7af3d0fd0da83 100644 --- a/arch/arm/src/common/stm32/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount.c @@ -40,6 +40,7 @@ #include "chip.h" #include "stm32_pulsecount.h" #include "stm32.h" +#include "stm32_tim.h" /* Generalized pulse count support for all STM32 families */ @@ -269,7 +270,7 @@ static struct stm32_tim_s g_pulsecount1dev = .timid = 1, .timtype = TIMTYPE_TIM1, .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, - .irq = PULSECOUNT_TIM1_IRQ, + .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; @@ -320,7 +321,7 @@ static struct stm32_tim_s g_pulsecount8dev = .timid = 8, .timtype = TIMTYPE_TIM8, .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, - .irq = PULSECOUNT_TIM8_IRQ, + .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; diff --git a/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_qencoder.c similarity index 90% rename from arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c rename to arch/arm/src/common/stm32/stm32_qencoder.c index f5c4bea0d22a0..36759ca88fae8 100644 --- a/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c +++ b/arch/arm/src/common/stm32/stm32_qencoder.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c + * arch/arm/src/common/stm32/stm32_qencoder.c * * SPDX-License-Identifier: Apache-2.0 * @@ -42,8 +42,8 @@ #include "chip.h" #include "arm_internal.h" #include "stm32.h" -#include "stm32_gpio.h" #include "stm32_tim.h" +#include "stm32_tim_clk.h" #include "stm32_qencoder.h" #ifdef CONFIG_SENSORS_QENCODER @@ -57,49 +57,44 @@ #undef HAVE_32BIT_TIMERS #undef HAVE_16BIT_TIMERS -/* On the F1 series, all timers are 16-bit. */ - -#if defined(CONFIG_STM32_STM32F10XX) - -# define HAVE_16BIT_TIMERS 1 +/* The width in bits of each timer. TIM2 and TIM5 are 32-bit on the families + * that select STM32_HAVE_TIM2_32BITS / STM32_HAVE_TIM5_32BITS; every other + * quadrature-capable timer is 16-bit. + */ - /* The width in bits of each timer */ +#define TIM1_BITWIDTH 16 -# define TIM1_BITWIDTH 16 +#ifdef CONFIG_STM32_HAVE_TIM2_32BITS +# define TIM2_BITWIDTH 32 +#else # define TIM2_BITWIDTH 16 -# define TIM3_BITWIDTH 16 -# define TIM4_BITWIDTH 16 -# define TIM5_BITWIDTH 16 -# define TIM8_BITWIDTH 16 - -/* On the F2, F3, F4 and G4 series, TIM2 and TIM5 are 32-bit. - * All of the rest are 16-bit - */ +#endif -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) +#define TIM3_BITWIDTH 16 +#define TIM4_BITWIDTH 16 - /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ +#ifdef CONFIG_STM32_HAVE_TIM5_32BITS +# define TIM5_BITWIDTH 32 +#else +# define TIM5_BITWIDTH 16 +#endif -# if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) -# define HAVE_32BIT_TIMERS 1 -# endif +#define TIM8_BITWIDTH 16 - /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ +/* If an enabled quadrature timer is 32-bit, then we have 32-bit timers */ -# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) -# define HAVE_16BIT_TIMERS 1 -# endif +#if (defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 32) || \ + (defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 32) +# define HAVE_32BIT_TIMERS 1 +#endif - /* The width in bits of each timer */ +/* If an enabled quadrature timer is 16-bit, then we have 16-bit timers */ -# define TIM1_BITWIDTH 16 -# define TIM2_BITWIDTH 32 -# define TIM3_BITWIDTH 16 -# define TIM4_BITWIDTH 16 -# define TIM5_BITWIDTH 32 -# define TIM8_BITWIDTH 16 +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) || \ + (defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 16) || \ + (defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 16) +# define HAVE_16BIT_TIMERS 1 #endif /* Do we need to support mixed 16- and 32-bit timers */ @@ -172,85 +167,45 @@ #if defined(CONFIG_STM32_STM32F10XX) # define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_CNF_INFLOAT | \ GPIO_MODE_INPUT) -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) -# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) #else -# error "Unrecognized STM32 chip" +# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) #endif -/* RCC definitions */ - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX) - -# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST - -# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR -# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN -# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR -# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST - -# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR -# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN -# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR -# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST - -# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR -# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN -# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR -# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST - -# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR -# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN -# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR -# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST - -# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST - -#elif defined(CONFIG_STM32_STM32G4XXX) - -# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST - -# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR1 -# define TIMEN_TIM2 RCC_APB1ENR1_TIM2EN -# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM2 RCC_APB1RSTR1_TIM2RST - -# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR1 -# define TIMEN_TIM3 RCC_APB1ENR1_TIM3EN -# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM3 RCC_APB1RSTR1_TIM3RST - -# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR1 -# define TIMEN_TIM4 RCC_APB1ENR1_TIM4EN -# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM4 RCC_APB1RSTR1_TIM4RST - -# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR1 -# define TIMEN_TIM5 RCC_APB1ENR1_TIM5EN -# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM5 RCC_APB1RSTR1_TIM5RST - -# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST +/* RCC definitions + * + * The timer RCC clock-enable and reset register/bit are provided per family + * by the common stm32_tim_clk.h aliases. + */ -#else -# error "Unrecognized STM32 chip" -#endif +#define TIMRCCEN_TIM1 STM32_RCC_TIM1_EN_REG +#define TIMEN_TIM1 STM32_RCC_TIM1_EN +#define TIMRCCRST_TIM1 STM32_RCC_TIM1_RST_REG +#define TIMRST_TIM1 STM32_RCC_TIM1_RST + +#define TIMRCCEN_TIM2 STM32_RCC_TIM2_EN_REG +#define TIMEN_TIM2 STM32_RCC_TIM2_EN +#define TIMRCCRST_TIM2 STM32_RCC_TIM2_RST_REG +#define TIMRST_TIM2 STM32_RCC_TIM2_RST + +#define TIMRCCEN_TIM3 STM32_RCC_TIM3_EN_REG +#define TIMEN_TIM3 STM32_RCC_TIM3_EN +#define TIMRCCRST_TIM3 STM32_RCC_TIM3_RST_REG +#define TIMRST_TIM3 STM32_RCC_TIM3_RST + +#define TIMRCCEN_TIM4 STM32_RCC_TIM4_EN_REG +#define TIMEN_TIM4 STM32_RCC_TIM4_EN +#define TIMRCCRST_TIM4 STM32_RCC_TIM4_RST_REG +#define TIMRST_TIM4 STM32_RCC_TIM4_RST + +#define TIMRCCEN_TIM5 STM32_RCC_TIM5_EN_REG +#define TIMEN_TIM5 STM32_RCC_TIM5_EN +#define TIMRCCRST_TIM5 STM32_RCC_TIM5_RST_REG +#define TIMRST_TIM5 STM32_RCC_TIM5_RST + +#define TIMRCCEN_TIM8 STM32_RCC_TIM8_EN_REG +#define TIMEN_TIM8 STM32_RCC_TIM8_EN +#define TIMRCCRST_TIM8 STM32_RCC_TIM8_RST_REG +#define TIMRST_TIM8 STM32_RCC_TIM8_RST /* Debug ********************************************************************/ diff --git a/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c deleted file mode 100644 index e88ff33418d2b..0000000000000 --- a/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c +++ /dev/null @@ -1,1254 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" -#include "stm32_qencoder.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timers *******************************************************************/ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -# undef HAVE_32BIT_TIMERS -# undef HAVE_16BIT_TIMERS - -/* If TIM2 is enabled and is 32-bit, then we have 32-bit timers */ - -# if defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_32BIT) -# define HAVE_32BIT_TIMERS 1 -# endif - -/* If TIM1, TIM2 (16-bit variant), TIM3, or TIM4 are enabled, we have - * 16-bit timers - */ - -# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || \ - (defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_16BIT)) -# define HAVE_16BIT_TIMERS 1 -# endif - -/* The width in bits of each timer */ - -# define TIM1_BITWIDTH 16 -# ifdef HAVE_TIM2_16BIT -# define TIM2_BITWIDTH 16 -# else -# define TIM2_BITWIDTH 32 -# endif -# define TIM3_BITWIDTH 16 -# define TIM4_BITWIDTH 16 - -/* Do we need to support mixed 16- and 32-bit timers */ - -# undef HAVE_MIXEDWIDTH_TIMERS -# if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -# endif -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_FILTER -# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32_QENCODER_ICF -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Encoder pulses prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; - - bool inuse; /* True: The lower-half driver is in-use */ - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN - uint32_t index_pin; /* Index pin GPIO */ - bool index_use; /* True: Index pin is configured */ - int32_t index_offset; /* Index pin offset */ -#endif - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; /* Spinlock */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv, msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -static int stm32_qe_index_irq(int irq, void *context, void *arg); -#endif - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos); -static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = stm32_setposmax, - .reset = stm32_reset, - .setindex = stm32_setindex, - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1_BRK, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 - " CCMR2: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" - " ARR: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg32(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); - sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_QE) - if (priv->config->timid == 1) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - return &g_tim4lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_qe_index_irq - * - * Description: - * Common encoder index pin interrupt. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -static int stm32_qe_index_irq(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv; - bool valid = false; - - DEBUGASSERT(arg); - - priv = (struct stm32_lowerhalf_s *)arg; - - valid = stm32_gpioread(priv->index_pin); - - if (valid == true) - { - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, priv->index_offset); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require timer - * interrupts. - * - ****************************************************************************/ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. - * Nothing else is expected. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x0000ffff; - } - else - { - priv->position += (int32_t)0x0000ffff; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - uint16_t regval; - int ret; -#endif - - /* NOTE: - * Clocking should have been enabled in the low-level RCC logic at boot-up - */ - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) - * (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. */ - - stm32_putreg16(priv, - STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32_TIM1_QE) - if (priv->config->timid == 1) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN - priv->index_offset = 0; -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * should stop data collection, free any resources, disable timer hardware, - * and put the system into the lowest possible power usage state * - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM2RST; - break; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM3RST; - break; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM4RST; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32_dumpregs(priv, "After stop"); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. - * Interrupts are disabled to make this atomic (if possible) - */ - - flags = spin_lock_irqsave(&priv->lock); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - spin_unlock_irqrestore(&priv->lock, flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_setposmax - * - * Description: - * Set the maximum encoder position. - * - ****************************************************************************/ - -static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - DEBUGASSERT(lower && priv->inuse); - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_setindex - * - * Description: - * Set the index pin position - * - ****************************************************************************/ - -static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos) -{ -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - int ret = OK; - - sninfo("Set QE TIM%d the index pin position %" PRIx32 "\n", - priv->config->timid, pos); - DEBUGASSERT(lower && priv->inuse); - - if (priv->index_use == false) - { - snerr("ERROR: QE TIM%d index not registered\n", - priv->config->timid); - ret = -EPERM; - goto errout; - } - - priv->index_offset = pos; - -errout: - return ret; -#else - return -ENOTTY; -#endif -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the priv-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_init - * - * Description: - * Register the encoder index pin to a given Qencoder timer - * - * Input Parameters: - * tim - The qenco timer number - * gpio - gpio pin configuration - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qe_index_init(int tim, uint32_t gpio) -{ - struct stm32_lowerhalf_s *priv; - int ret = OK; - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - if (priv->inuse == false) - { - snerr("ERROR: TIM%d is not in-use\n", tim); - ret = -EINVAL; - } - - priv->index_pin = gpio; - stm32_configgpio(priv->index_pin); - - ret = stm32_gpiosetevent(gpio, true, false, true, - stm32_qe_index_irq, priv); - if (ret < 0) - { - snerr("ERROR: QE TIM%d failed register irq\n", tim); - goto errout; - } - - priv->index_use = true; - -errout: - return ret; -} -#endif diff --git a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_tim.c similarity index 81% rename from arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c rename to arch/arm/src/common/stm32/stm32_tim.c index 4f70e29770041..320cad25debe1 100644 --- a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +++ b/arch/arm/src/common/stm32/stm32_tim.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c + * arch/arm/src/common/stm32/stm32_tim.c * * SPDX-License-Identifier: Apache-2.0 * @@ -40,8 +40,8 @@ #include "chip.h" #include "arm_internal.h" #include "stm32.h" -#include "stm32_gpio.h" #include "stm32_tim.h" +#include "stm32_tim_clk.h" /**************************************************************************** * Pre-processor Definitions @@ -333,8 +333,13 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, + uint32_t freq); +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, uint32_t count); @@ -364,7 +369,10 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .disable = stm32_tim_disable, .setmode = stm32_tim_setmode, .setclock = stm32_tim_setclock, + .setfreq = stm32_tim_setfreq, + .getclock = stm32_tim_getclock, .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, .getcounter = stm32_tim_getcounter, .setcounter = stm32_tim_setcounter, .getwidth = stm32_tim_getwidth, @@ -376,6 +384,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .disableint = stm32_tim_disableint, .ackint = stm32_tim_ackint, .checkint = stm32_tim_checkint, + .dump_regs = stm32_tim_dumpregs, }; #ifdef CONFIG_STM32_TIM1 @@ -742,7 +751,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* Advanced registers require Main Output Enable */ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE -#ifdef STM32_TIM8_BASE +#ifdef CONFIG_STM32_HAVE_TIM8 || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE #endif ) @@ -899,6 +908,304 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) return prescaler; } +/**************************************************************************** + * Name: stm32_tim_getclock + ****************************************************************************/ + +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) +{ + uint32_t freqin; + int prescaler; + uint32_t reload; + uint32_t timclk; + + DEBUGASSERT(dev != NULL); + + /* Disable Timer? */ + + if (freq == 0) + { + stm32_tim_disable(dev); + return 0; + } + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + freqin = STM32_TIM1_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + freqin = STM32_TIM2_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + freqin = STM32_TIM3_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + freqin = STM32_TIM4_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + freqin = STM32_TIM5_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + freqin = STM32_TIM6_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + freqin = STM32_TIM7_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + freqin = STM32_TIM8_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case STM32_TIM9_BASE: + freqin = STM32_TIM9_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case STM32_TIM10_BASE: + freqin = STM32_TIM10_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case STM32_TIM11_BASE: + freqin = STM32_TIM11_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + freqin = STM32_TIM12_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + freqin = STM32_TIM13_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + freqin = STM32_TIM14_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + freqin = STM32_TIM15_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + freqin = STM32_TIM16_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + freqin = STM32_TIM17_CLKIN; + break; +#endif + default: + return -EINVAL; + } + + /* Pick the largest reload and smallest prescaler for the best accuracy */ + + prescaler = (freqin / freq + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + + if (prescaler > 65536) + { + prescaler = 65536; + } + + timclk = freqin / prescaler; + + reload = timclk / freq; + if (reload < 1) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); + stm32_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); + + return (timclk / reload); +} + +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) +{ + struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; + + ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DIER_OFFSET)); + ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", + stm32_getreg16(dev, STM32_GTIM_SR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR2_OFFSET)); + ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET), + stm32_getreg16(dev, STM32_GTIM_ARR_OFFSET)); + ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + stm32_getreg16(dev, STM32_GTIM_CCR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR3_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR4_OFFSET)); + +#if STM32_NATIM > 0 + if (priv->base == STM32_TIM1_BASE +#ifdef CONFIG_STM32_HAVE_TIM8 + || priv->base == STM32_TIM8_BASE +#endif + ) + { + ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + stm32_getreg16(dev, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); + } + else +#endif + { + ainfo(" DCR: %04x DMAR: %04x\n", + stm32_getreg16(dev, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); + } +} + +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) +{ + uint32_t freqin; + uint32_t prescaler; + + DEBUGASSERT(dev != NULL); + + /* Get the input clock frequency for this timer. These vary with + * different timer clock sources, MCU-specific timer configuration, and + * board-specific clock configuration. The correct input clock frequency + * must be defined in the board.h header file. + */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + freqin = STM32_TIM1_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + freqin = STM32_TIM2_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + freqin = STM32_TIM3_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + freqin = STM32_TIM4_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + freqin = STM32_TIM5_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + freqin = STM32_TIM6_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + freqin = STM32_TIM7_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + freqin = STM32_TIM8_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case STM32_TIM9_BASE: + freqin = STM32_TIM9_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case STM32_TIM10_BASE: + freqin = STM32_TIM10_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case STM32_TIM11_BASE: + freqin = STM32_TIM11_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + freqin = STM32_TIM12_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + freqin = STM32_TIM13_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + freqin = STM32_TIM14_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + freqin = STM32_TIM15_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + freqin = STM32_TIM16_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + freqin = STM32_TIM17_CLKIN; + break; +#endif + + default: + return 0; + } + + prescaler = stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET); + return freqin / (prescaler + 1); +} + /**************************************************************************** * Name: stm32_tim_setperiod ****************************************************************************/ @@ -910,6 +1217,16 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } +/**************************************************************************** + * Name: stm32_tim_getperiod + ****************************************************************************/ + +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + return stm32_getreg32(dev, STM32_GTIM_ARR_OFFSET); +} + /**************************************************************************** * Name: stm32_tim_getcounter ****************************************************************************/ @@ -1723,240 +2040,330 @@ static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ +/* RCC timer-clock gating: the register/bit per timer come from the + * per-family aliases in stm32_tim_rcc.h; the logic below is common. + */ -struct stm32_tim_dev_s *stm32_tim_init(int timer) +static void stm32_tim_enableclk(uint32_t base) { - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) + switch (base) { #ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_TIM1_EN_REG, STM32_RCC_TIM1_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_TIM2_EN_REG, STM32_RCC_TIM2_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_TIM3_EN_REG, STM32_RCC_TIM3_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_TIM4_EN_REG, STM32_RCC_TIM4_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_TIM5_EN_REG, STM32_RCC_TIM5_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_TIM6_EN_REG, STM32_RCC_TIM6_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_TIM7_EN_REG, STM32_RCC_TIM7_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_TIM8_EN_REG, STM32_RCC_TIM8_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM9 - case 9: - dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); + case STM32_TIM9_BASE: + modifyreg32(STM32_RCC_TIM9_EN_REG, STM32_RCC_TIM9_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM10 - case 10: - dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); + case STM32_TIM10_BASE: + modifyreg32(STM32_RCC_TIM10_EN_REG, STM32_RCC_TIM10_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM11 - case 11: - dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); + case STM32_TIM11_BASE: + modifyreg32(STM32_RCC_TIM11_EN_REG, STM32_RCC_TIM11_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); + case STM32_TIM12_BASE: + modifyreg32(STM32_RCC_TIM12_EN_REG, STM32_RCC_TIM12_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); + case STM32_TIM13_BASE: + modifyreg32(STM32_RCC_TIM13_EN_REG, STM32_RCC_TIM13_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); + case STM32_TIM14_BASE: + modifyreg32(STM32_RCC_TIM14_EN_REG, STM32_RCC_TIM14_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_TIM15_EN_REG, STM32_RCC_TIM15_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_TIM16_EN_REG, STM32_RCC_TIM16_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_TIM17_EN_REG, STM32_RCC_TIM17_EN, 0); break; #endif default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; + break; } - - stm32_tim_reset(dev); - - return dev; } -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) +static void stm32_tim_disableclk(uint32_t base) { - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) + switch (base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + modifyreg32(STM32_RCC_TIM1_EN_REG, 0, STM32_RCC_TIM1_EN); break; #endif #ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); + modifyreg32(STM32_RCC_TIM2_EN_REG, 0, STM32_RCC_TIM2_EN); break; #endif #ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); + modifyreg32(STM32_RCC_TIM3_EN_REG, 0, STM32_RCC_TIM3_EN); break; #endif #ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); + modifyreg32(STM32_RCC_TIM4_EN_REG, 0, STM32_RCC_TIM4_EN); break; #endif #ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); + modifyreg32(STM32_RCC_TIM5_EN_REG, 0, STM32_RCC_TIM5_EN); break; #endif #ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); + modifyreg32(STM32_RCC_TIM6_EN_REG, 0, STM32_RCC_TIM6_EN); break; #endif #ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); + modifyreg32(STM32_RCC_TIM7_EN_REG, 0, STM32_RCC_TIM7_EN); break; #endif #ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + modifyreg32(STM32_RCC_TIM8_EN_REG, 0, STM32_RCC_TIM8_EN); break; #endif #ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); + modifyreg32(STM32_RCC_TIM9_EN_REG, 0, STM32_RCC_TIM9_EN); break; #endif #ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); + modifyreg32(STM32_RCC_TIM10_EN_REG, 0, STM32_RCC_TIM10_EN); break; #endif #ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); + modifyreg32(STM32_RCC_TIM11_EN_REG, 0, STM32_RCC_TIM11_EN); break; #endif #ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); + modifyreg32(STM32_RCC_TIM12_EN_REG, 0, STM32_RCC_TIM12_EN); break; #endif #ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); + modifyreg32(STM32_RCC_TIM13_EN_REG, 0, STM32_RCC_TIM13_EN); break; #endif #ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); + modifyreg32(STM32_RCC_TIM14_EN_REG, 0, STM32_RCC_TIM14_EN); break; #endif #ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + modifyreg32(STM32_RCC_TIM15_EN_REG, 0, STM32_RCC_TIM15_EN); break; #endif #ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + modifyreg32(STM32_RCC_TIM16_EN_REG, 0, STM32_RCC_TIM16_EN); break; #endif #ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + modifyreg32(STM32_RCC_TIM17_EN_REG, 0, STM32_RCC_TIM17_EN); break; #endif default: - return -EINVAL; + break; + } +} + +/**************************************************************************** + * Name: stm32_tim_init + ****************************************************************************/ + +struct stm32_tim_dev_s *stm32_tim_init(int timer) +{ + struct stm32_tim_dev_s *dev = NULL; + + /* Get structure and enable power */ + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1 + case 1: + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case 2: + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case 3: + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case 4: + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case 5: + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case 6: + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case 7: + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case 8: + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case 9: + dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case 10: + dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case 11: + dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case 12: + dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case 13: + dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case 14: + dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case 15: + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case 16: + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case 17: + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; + break; +#endif + default: + return NULL; } + /* Is device already allocated */ + + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + { + return NULL; + } + + /* Enable the timer's RCC clock (family-specific) */ + + stm32_tim_enableclk(((struct stm32_tim_priv_s *)dev)->base); + + stm32_tim_reset(dev); + + return dev; +} + +/**************************************************************************** + * Name: stm32_tim_deinit + * + * TODO: Detach interrupts, and close down all TIM Channels + * + ****************************************************************************/ + +int stm32_tim_deinit(struct stm32_tim_dev_s * dev) +{ + DEBUGASSERT(dev != NULL); + + /* Disable the timer's RCC clock (family-specific) */ + + stm32_tim_disableclk(((struct stm32_tim_priv_s *)dev)->base); + /* Mark it as free */ ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; diff --git a/arch/arm/src/common/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim.h index 77d884e06727a..60c26af45edbf 100644 --- a/arch/arm/src/common/stm32/stm32_tim.h +++ b/arch/arm/src/common/stm32/stm32_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H -#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_H /**************************************************************************** * Included Files @@ -29,14 +29,204 @@ #include -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) -# include "stm32_tim_m0_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) -# include "stm32_tim_m3m4_v1v2v3.h" +#include "chip.h" + +/* This is the common STM32 timer API, shared by every family. The timer + * register layouts differ between families, so the concrete hardware header + * is selected here while the programming model below stays the same. + */ + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "hardware/stm32_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L4) +# include "hardware/stm32l4_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L5) +# include "hardware/stm32l5_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32WL5) +# include "hardware/stm32wl5_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F7) +# include "hardware/stm32f7_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32H7) +# include "hardware/stm32h7_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32H5) +# include "hardware/stm32h5_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32U5) +# include "hardware/stm32u5_tim.h" +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) +#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ #else -# error "Unsupported STM32 TIM" +#define EXTERN extern +#endif + +/* TIM Device Structure */ + +struct stm32_tim_dev_s +{ + struct stm32_tim_ops_s *ops; +}; + +/* TIM Modes of Operation */ + +typedef enum stm32_tim_mode_e +{ + STM32_TIM_MODE_UNUSED = -1, + + /* One of the following */ + + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, + + /* One of the following */ + + STM32_TIM_MODE_CK_INT = 0x0000, +} stm32_tim_mode_t; + +/* TIM Channel Modes */ + +typedef enum stm32_tim_channel_e +{ + STM32_TIM_CH_DISABLED = 0x00, + + /* Common configuration */ + + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, + + /* MODES: */ + + STM32_TIM_CH_MODE_MASK = 0x0e, + + /* Output Compare Modes */ + + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTTOGGLE = 0x08, /* Toggle TIM_CHx output on update event */ +} stm32_tim_channel_t; + +/* TIM Operations */ + +struct stm32_tim_ops_s +{ + /* Basic Timers */ + + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); + void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); + + /* General and Advanced Timers Adds */ + + int (*getwidth)(struct stm32_tim_dev_s *dev); + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + stm32_tim_channel_t mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, + uint32_t compare); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); + + /* Timer interrupts */ + + int (*setisr)(struct stm32_tim_dev_s *dev, + xcpt_t handler, void * arg, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); + + /* Debug */ + + void (*dump_regs)(struct stm32_tim_dev_s *dev); +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/* Power-up timer and get its structure */ + +struct stm32_tim_dev_s *stm32_tim_init(int timer); + +/* Power-down timer, mark it as unused */ + +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); + +/**************************************************************************** + * Name: stm32_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath - The full path to the timer device. + * This should be of the form /dev/timer0 + * timer - the timer number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int stm32_timer_initialize(const char *devpath, int timer); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} #endif -#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H */ +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_clk.h b/arch/arm/src/common/stm32/stm32_tim_clk.h new file mode 100644 index 0000000000000..b3484f2f79aad --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim_clk.h @@ -0,0 +1,483 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim_clk.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_CLK_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_CLK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Per-family RCC clock-enable and reset aliases for the common timer + * drivers. Only the timer RCC enable/reset register and bit differ between + * families; the timer input clock is provided uniformly by each board as + * STM32_TIMn_CLKIN. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32H7) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM2_EN RCC_APB1LENR_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM2_RST RCC_APB1LRSTR_TIM2RST +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM3_EN RCC_APB1LENR_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM3_RST RCC_APB1LRSTR_TIM3RST +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM4_EN RCC_APB1LENR_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM4_RST RCC_APB1LRSTR_TIM4RST +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM5_EN RCC_APB1LENR_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM5_RST RCC_APB1LRSTR_TIM5RST +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM6_EN RCC_APB1LENR_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM6_RST RCC_APB1LRSTR_TIM6RST +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM7_EN RCC_APB1LENR_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM7_RST RCC_APB1LRSTR_TIM7RST +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST +# define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM12_EN RCC_APB1LENR_TIM12EN +# define STM32_RCC_TIM12_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM12_RST RCC_APB1LRSTR_TIM12RST +# define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM13_EN RCC_APB1LENR_TIM13EN +# define STM32_RCC_TIM13_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM13_RST RCC_APB1LRSTR_TIM13RST +# define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM14_EN RCC_APB1LENR_TIM14EN +# define STM32_RCC_TIM14_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM14_RST RCC_APB1LRSTR_TIM14RST +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST +#elif defined(CONFIG_ARCH_CHIP_STM32F7) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM2_EN RCC_APB1ENR_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM2_RST RCC_APB1RSTR_TIM2RST +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM3_EN RCC_APB1ENR_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM3_RST RCC_APB1RSTR_TIM3RST +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM4_EN RCC_APB1ENR_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM4_RST RCC_APB1RSTR_TIM4RST +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM5_EN RCC_APB1ENR_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM5_RST RCC_APB1RSTR_TIM5RST +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM6_EN RCC_APB1ENR_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM6_RST RCC_APB1RSTR_TIM6RST +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM7_EN RCC_APB1ENR_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM7_RST RCC_APB1RSTR_TIM7RST +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST +# define STM32_RCC_TIM9_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM9_EN RCC_APB2ENR_TIM9EN +# define STM32_RCC_TIM9_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM9_RST RCC_APB2RSTR_TIM9RST +# define STM32_RCC_TIM10_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM10_EN RCC_APB2ENR_TIM10EN +# define STM32_RCC_TIM10_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM10_RST RCC_APB2RSTR_TIM10RST +# define STM32_RCC_TIM11_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM11_EN RCC_APB2ENR_TIM11EN +# define STM32_RCC_TIM11_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM11_RST RCC_APB2RSTR_TIM11RST +# define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM12_EN RCC_APB1ENR_TIM12EN +# define STM32_RCC_TIM12_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM12_RST RCC_APB1RSTR_TIM12RST +# define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM13_EN RCC_APB1ENR_TIM13EN +# define STM32_RCC_TIM13_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM13_RST RCC_APB1RSTR_TIM13RST +# define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM14_EN RCC_APB1ENR_TIM14EN +# define STM32_RCC_TIM14_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM14_RST RCC_APB1RSTR_TIM14RST +#elif defined(CONFIG_ARCH_CHIP_STM32H5) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM2_EN RCC_APB1LENR_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM2_RST RCC_APB1LRSTR_TIM2RST +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM3_EN RCC_APB1LENR_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM3_RST RCC_APB1LRSTR_TIM3RST +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM4_EN RCC_APB1LENR_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM4_RST RCC_APB1LRSTR_TIM4RST +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM5_EN RCC_APB1LENR_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM5_RST RCC_APB1LRSTR_TIM5RST +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM6_EN RCC_APB1LENR_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM6_RST RCC_APB1LRSTR_TIM6RST +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM7_EN RCC_APB1LENR_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM7_RST RCC_APB1LRSTR_TIM7RST +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST +# define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM12_EN RCC_APB1LENR_TIM12EN +# define STM32_RCC_TIM12_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM12_RST RCC_APB1LRSTR_TIM12RST +# define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM13_EN RCC_APB1LENR_TIM13EN +# define STM32_RCC_TIM13_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM13_RST RCC_APB1LRSTR_TIM13RST +# define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM14_EN RCC_APB1LENR_TIM14EN +# define STM32_RCC_TIM14_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM14_RST RCC_APB1LRSTR_TIM14RST +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST +#elif defined(CONFIG_ARCH_CHIP_STM32U5) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM3_RST RCC_APB1RSTR1_TIM3RST +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM4_RST RCC_APB1RSTR1_TIM4RST +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM5_RST RCC_APB1RSTR1_TIM5RST +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM6_RST RCC_APB1RSTR1_TIM6RST +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM7_RST RCC_APB1RSTR1_TIM7RST +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST +#elif defined(CONFIG_ARCH_CHIP_STM32L5) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM3_RST RCC_APB1RSTR1_TIM3RST +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM4_RST RCC_APB1RSTR1_TIM4RST +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM5_RST RCC_APB1RSTR1_TIM5RST +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM6_RST RCC_APB1RSTR1_TIM6RST +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM7_RST RCC_APB1RSTR1_TIM7RST +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST +#elif defined(CONFIG_ARCH_CHIP_STM32WL5) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM3_RST RCC_APB1RSTR1_TIM3RST +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM4_RST RCC_APB1RSTR1_TIM4RST +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM5_RST RCC_APB1RSTR1_TIM5RST +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM6_RST RCC_APB1RSTR1_TIM6RST +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM7_RST RCC_APB1RSTR1_TIM7RST +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST +#elif defined(CONFIG_ARCH_CHIP_STM32L4) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM3_RST RCC_APB1RSTR1_TIM3RST +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM4_RST RCC_APB1RSTR1_TIM4RST +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM5_RST RCC_APB1RSTR1_TIM5RST +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM6_RST RCC_APB1RSTR1_TIM6RST +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM7_RST RCC_APB1RSTR1_TIM7RST +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST +#elif defined(CONFIG_ARCH_CHIP_STM32WB) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST +#else /* Classic M3/M4 + M0: APB1ENR/APB2ENR */ +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM2_EN RCC_APB1ENR_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM2_RST RCC_APB1RSTR_TIM2RST +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM3_EN RCC_APB1ENR_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM3_RST RCC_APB1RSTR_TIM3RST +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM4_EN RCC_APB1ENR_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM4_RST RCC_APB1RSTR_TIM4RST +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM5_EN RCC_APB1ENR_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM5_RST RCC_APB1RSTR_TIM5RST +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM6_EN RCC_APB1ENR_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM6_RST RCC_APB1RSTR_TIM6RST +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM7_EN RCC_APB1ENR_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM7_RST RCC_APB1RSTR_TIM7RST +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST +# define STM32_RCC_TIM9_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM9_EN RCC_APB2ENR_TIM9EN +# define STM32_RCC_TIM9_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM9_RST RCC_APB2RSTR_TIM9RST +# define STM32_RCC_TIM10_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM10_EN RCC_APB2ENR_TIM10EN +# define STM32_RCC_TIM10_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM10_RST RCC_APB2RSTR_TIM10RST +# define STM32_RCC_TIM11_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM11_EN RCC_APB2ENR_TIM11EN +# define STM32_RCC_TIM11_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM11_RST RCC_APB2RSTR_TIM11RST +# define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM12_EN RCC_APB1ENR_TIM12EN +# define STM32_RCC_TIM12_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM12_RST RCC_APB1RSTR_TIM12RST +# define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM13_EN RCC_APB1ENR_TIM13EN +# define STM32_RCC_TIM13_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM13_RST RCC_APB1RSTR_TIM13RST +# define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM14_EN RCC_APB1ENR_TIM14EN +# define STM32_RCC_TIM14_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM14_RST RCC_APB1RSTR_TIM14RST +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_CLK_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_lowerhalf.c similarity index 89% rename from arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_tim_lowerhalf.c index 356a3e9e6c782..fab9090a6690f 100644 --- a/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_tim_lowerhalf.c @@ -1,11 +1,14 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c + * arch/arm/src/common/stm32/stm32_tim_lowerhalf.c * * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. + * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. + * SPDX-FileCopyrightText: 2016 Sebastien Lorquet All rights reserved. * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato * SPDX-FileContributor: Wail Khemir * SPDX-FileContributor: Paul Alexander Patience + * SPDX-FileContributor: Daniel Pereira Volpato * SPDX-FileContributor: dev@ziggurat29.com * SPDX-FileContributor: Sebastien Lorquet * @@ -65,19 +68,39 @@ defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* The timer counter width (16 or 32 bits). TIM2 and TIM5 are 32-bit on + * most families; the STM32_HAVE_TIMn_32BITS capability flags carry that + * per-family knowledge instead of chip-line #ifdefs. Every other timer is + * 16-bit. + */ + #define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 16 + +#ifdef CONFIG_STM32_HAVE_TIM2_32BITS +# define STM32_TIM2_RES 32 +#else +# define STM32_TIM2_RES 16 +#endif + #define STM32_TIM3_RES 16 #define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 16 + +#ifdef CONFIG_STM32_HAVE_TIM5_32BITS +# define STM32_TIM5_RES 32 +#else +# define STM32_TIM5_RES 16 +#endif + #define STM32_TIM6_RES 16 #define STM32_TIM7_RES 16 #define STM32_TIM8_RES 16 @@ -207,6 +230,30 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif +#ifdef CONFIG_STM32_TIM9 +static struct stm32_lowerhalf_s g_tim9_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM9_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM10 +static struct stm32_lowerhalf_s g_tim10_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM10_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM11 +static struct stm32_lowerhalf_s g_tim11_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM11_RES, +}; +#endif + #ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { @@ -276,7 +323,7 @@ static int stm32_timer_handler(int irq, void * context, void * arg) struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; uint32_t next_interval_us = 0; - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); + STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); if (lower->callback(&next_interval_us, lower->arg)) { @@ -321,7 +368,7 @@ static int stm32_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } priv->started = true; @@ -355,7 +402,7 @@ static int stm32_stop(struct timer_lowerhalf_s *lower) if (priv->started) { STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; @@ -438,8 +485,8 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, * Set a new timeout value (and reset the timer) * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * timeout - The new timeout value in microseconds. * * Returned Value: @@ -518,11 +565,11 @@ static void stm32_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } else { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } @@ -554,6 +601,7 @@ static void stm32_setcallback(struct timer_lowerhalf_s *lower, int stm32_timer_initialize(const char *devpath, int timer) { struct stm32_lowerhalf_s *lower; + void *drvr; tmrinfo("Init TIM%d\n", timer); @@ -599,6 +647,21 @@ int stm32_timer_initialize(const char *devpath, int timer) lower = &g_tim8_lowerhalf; break; #endif +#ifdef CONFIG_STM32_TIM9 + case 9: + lower = &g_tim9_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case 10: + lower = &g_tim10_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case 11: + lower = &g_tim11_lowerhalf; + break; +#endif #ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; @@ -649,8 +712,7 @@ int stm32_timer_initialize(const char *devpath, int timer) * REVISIT: The returned handle is discard here. */ - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); + drvr = timer_register(devpath, (struct timer_lowerhalf_s *)lower); if (drvr == NULL) { /* The actual cause of the failure may have been a failure to allocate diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c deleted file mode 100644 index 58255a4955e4b..0000000000000 --- a/arch/arm/src/common/stm32/stm32_tim_m0_v1.c +++ /dev/null @@ -1,1502 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m0_v1.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM - * may also be defined to indicate that the timer is intended to be used - * for pulsed output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined - * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer - * "n" is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined(CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined(CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32_TIM6_PWM) || defined(CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32_TIM7_PWM) || defined(CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined(CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM12_PWM) || defined(CONFIG_STM32_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) -# undef CONFIG_STM32_TIM12 -#endif - -#if defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) -# undef CONFIG_STM32_TIM13 -#endif - -#if defined(CONFIG_STM32_TIM14_PWM) || defined(CONFIG_STM32_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) -# undef CONFIG_STM32_TIM14 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined(CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ - defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) || \ - defined(GPIO_TIM1_CH5OUT) || defined(GPIO_TIM1_CH6OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ - defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) || defined(GPIO_TIM3_CH2OUT) || \ - defined(GPIO_TIM3_CH3OUT) || defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) || defined(GPIO_TIM4_CH2OUT) || \ - defined(GPIO_TIM4_CH3OUT) || defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) || defined(GPIO_TIM5_CH2OUT) || \ - defined(GPIO_TIM5_CH3OUT) || defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) || defined(GPIO_TIM8_CH2OUT) || \ - defined(GPIO_TIM8_CH3OUT) || defined(GPIO_TIM8_CH4OUT) || \ - defined(GPIO_TIM8_CH5OUT) || defined(GPIO_TIM8_CH6OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM12) -# if defined(GPIO_TIM12_CH1OUT) || defined(GPIO_TIM12_CH2OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM13) -# if defined(GPIO_TIM13_CH1OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM14) -# if defined(GPIO_TIM14_CH1OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) || defined(GPIO_TIM15_CH2OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -# endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - stm32_tim_channel_t mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, - uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, - void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = &stm32_tim_enable, - .disable = &stm32_tim_disable, - .setmode = &stm32_tim_setmode, - .setclock = &stm32_tim_setclock, - .getclock = &stm32_tim_getclock, - .setperiod = &stm32_tim_setperiod, - .getperiod = &stm32_tim_getperiod, - .getcounter = &stm32_tim_getcounter, - .getwidth = &stm32_tim_getwidth, - .setchannel = &stm32_tim_setchannel, - .setcompare = &stm32_tim_setcompare, - .getcapture = &stm32_tim_getcapture, - .setisr = &stm32_tim_setisr, - .enableint = &stm32_tim_enableint, - .disableint = &stm32_tim_disableint, - .ackint = &stm32_tim_ackint -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/* Reset timer into system default state, but do not affect output/input - * pins - */ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM6_GPIOCONFIG) || \ - defined(HAVE_TIM7_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM12_GPIOCONFIG) || defined(HAVE_TIM13_GPIOCONFIG) || \ - defined(HAVE_TIM14_GPIOCONFIG) || defined(HAVE_TIM15_GPIOCONFIG) || \ - defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - tmrinfo("Set clock=%" PRId32 "\n", freq); - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - tmrinfo(" timer freq=%" PRId32 "\n", freqin); - tmrinfo(" prescaler=%d\n", prescaler); - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - tmrinfo(" prescaler (adjusted)=%d\n", prescaler); - - /* PSC_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - uint32_t prescaler; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - prescaler = stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET); - clock = freqin / (prescaler + 1); - return clock; -} - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - tmrinfo("Set period=%" PRId32 "\n", period); - DEBUGASSERT(dev != NULL); - - /* ARR_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - -#ifdef HAVE_TIM2_32BIT - /* TIM2 is 16-bit on L0 */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) - { - return 32; - } -#endif - - /* All other timers are 16-bit */ - - return 16; -} - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); -} - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - tmrinfo("Set ISR\n"); - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1_BRK; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - - return OK; -} - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - - /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); -} - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - - /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); -} - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - /* SR_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - tmrinfo("Set mode=%d\n", mode); - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#ifdef STM32_TIM6_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE) - { - return -EINVAL; - } -#endif - -#ifdef STM32_TIM7_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - - /* CR1_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - - /* Advanced registers require Main Output Enable */ -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM8) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE -# if defined(CONFIG_STM32_TIM8) - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE -# endif - ) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif /* CONFIG_STM32_TIM1 || CONFIG_STM32_TIM8 */ - - return OK; -} - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - - /* CCER_OFFSET and CCMR1_OFFSET are the same for ATIM and GTIM */ - - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#ifdef STM32_TIM6_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE) - { - return -EINVAL; - } -#endif - -#ifdef STM32_TIM7_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -# if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -# if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -# if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -# if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -# if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -# if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -# if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -# if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - } - - return OK; -} - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM14EN); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/* TODO: Detach interrupts, and close down all TIM Channels */ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM14EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1.h b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h deleted file mode 100644 index 07c0ef1f7e592..0000000000000 --- a/arch/arm/src/common/stm32/stm32_tim_m0_v1.h +++ /dev/null @@ -1,233 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m0_v1.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H -#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* TODO external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC = open collector mode -#endif -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - int (*getwidth)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, - int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h deleted file mode 100644 index 9bd99fb862f29..0000000000000 --- a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h +++ /dev/null @@ -1,225 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H -#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, - - /* STM32_TIM_MODE_CK_INT_TRIG = 0x0400, */ - - /* STM32_TIM_MODE_CK_EXT = 0x0800, */ - - /* STM32_TIM_MODE_CK_EXT_TRIG = 0x0C00, */ - - /* Clock sources, OR'ed with CK_EXT */ - - /* STM32_TIM_MODE_CK_CHINVALID = 0x0000, */ - - /* STM32_TIM_MODE_CK_CH1 = 0x0001, */ - - /* STM32_TIM_MODE_CK_CH2 = 0x0002, */ - - /* STM32_TIM_MODE_CK_CH3 = 0x0003, */ - - /* STM32_TIM_MODE_CK_CH4 = 0x0004 */ - - /* Todo: external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ - - /* STM32_TIM_CH_OUTCOMPARE = 0x06, */ - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - /* STM32_TIM_CH_INCAPTURE = 0x10, */ - - /* STM32_TIM_CH_INPWM = 0x20 */ - - /* STM32_TIM_CH_DRIVE_OC -- open collector mode */ -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); - - /* General and Advanced Timers Adds */ - - int (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void * arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. - * This should be of the form /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c deleted file mode 100644 index 25d5b63192639..0000000000000 --- a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c +++ /dev/null @@ -1,588 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) -# define STM32_TIM2_RES 16 -#else -# define STM32_TIM2_RES 32 -#endif -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# define STM32_TIM5_RES 16 -#else -# define STM32_TIM5_RES 32 -#endif -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM9_RES 16 -#define STM32_TIM10_RES 16 -#define STM32_TIM11_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -static struct stm32_lowerhalf_s g_tim9_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM9_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -static struct stm32_lowerhalf_s g_tim10_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM10_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -static struct stm32_lowerhalf_s g_tim11_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM11_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - lower = &g_tim9_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - lower = &g_tim10_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - lower = &g_tim11_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h b/arch/arm/src/stm32c0/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32c0/hardware/stm32c0_rcc.h rename to arch/arm/src/stm32c0/hardware/stm32_rcc.h index 9784111a9b184..420831e39fc88 100644 --- a/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h +++ b/arch/arm/src/stm32c0/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32c0/hardware/stm32c0_rcc.h + * arch/arm/src/stm32c0/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H -#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -394,4 +394,4 @@ #define RCC_CSR2_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR2_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32c0/stm32.h b/arch/arm/src/stm32c0/stm32.h index b12ea4f456513..7d1c5ae34764f 100644 --- a/arch/arm/src/stm32c0/stm32.h +++ b/arch/arm/src/stm32c0/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h b/arch/arm/src/stm32f0/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32f0/hardware/stm32f0_rcc.h rename to arch/arm/src/stm32f0/hardware/stm32_rcc.h index 3bd0a3dab1763..8c257d1639776 100644 --- a/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/hardware/stm32f0_rcc.h + * arch/arm/src/stm32f0/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H -#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -391,4 +391,4 @@ #define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */ #define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f0/stm32.h b/arch/arm/src/stm32f0/stm32.h index bd3ce82e9d74e..fabdd48a6255b 100644 --- a/arch/arm/src/stm32f0/stm32.h +++ b/arch/arm/src/stm32f0/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h b/arch/arm/src/stm32f1/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h rename to arch/arm/src/stm32f1/hardware/stm32_rcc.h index 54828425c3c5e..87a2d7096caf2 100644 --- a/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h +++ b/arch/arm/src/stm32f1/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h + * arch/arm/src/stm32f1/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -471,4 +471,4 @@ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f1/stm32.h b/arch/arm/src/stm32f1/stm32.h index 5707089d7b890..8b2f3364b1878 100644 --- a/arch/arm/src/stm32f1/stm32.h +++ b/arch/arm/src/stm32f1/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32f2/Kconfig b/arch/arm/src/stm32f2/Kconfig index 4acec531bd634..f51fa6bde0680 100644 --- a/arch/arm/src/stm32f2/Kconfig +++ b/arch/arm/src/stm32f2/Kconfig @@ -167,6 +167,8 @@ config STM32_STM32F20XX select STM32_HAVE_IP_SPI_V2 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h b/arch/arm/src/stm32f2/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h rename to arch/arm/src/stm32f2/hardware/stm32_rcc.h index 31af35f07a1bf..b5d0597e006a2 100644 --- a/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h +++ b/arch/arm/src/stm32f2/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h + * arch/arm/src/stm32f2/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -503,4 +503,4 @@ #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */ #define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f2/stm32.h b/arch/arm/src/stm32f2/stm32.h index 9069ebcbca61e..6563efa5ae627 100644 --- a/arch/arm/src/stm32f2/stm32.h +++ b/arch/arm/src/stm32f2/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32f3/Kconfig b/arch/arm/src/stm32f3/Kconfig index f58b8ea18ff0a..934130b9514a1 100644 --- a/arch/arm/src/stm32f3/Kconfig +++ b/arch/arm/src/stm32f3/Kconfig @@ -449,6 +449,7 @@ config STM32_STM32F30XX select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS @@ -542,6 +543,7 @@ config STM32_STM32F33XX select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS @@ -586,6 +588,8 @@ config STM32_STM32F37XX select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM select STM32_HAVE_IP_CRYPTO_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_ADC_M3M4_V1_BASIC select STM32_HAVE_COMMON_FOC select STM32_HAVE_IP_DCMI_V1 diff --git a/arch/arm/src/stm32f3/hardware/stm32_rcc.h b/arch/arm/src/stm32f3/hardware/stm32_rcc.h new file mode 100644 index 0000000000000..6a18a3dea3f99 --- /dev/null +++ b/arch/arm/src/stm32f3/hardware/stm32_rcc.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/hardware/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F302X8) || \ + defined(CONFIG_STM32_STM32F302XC) || defined(CONFIG_STM32_STM32F303XC) || \ + defined(CONFIG_STM32_STM32F303XE) +# include "hardware/stm32f30xxx_rcc.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_rcc.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_rcc.h" +#else +# error "Unsupported STM32 F3 part" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f3/stm32.h b/arch/arm/src/stm32f3/stm32.h index f7eb0f45c819d..4999babf72256 100644 --- a/arch/arm/src/stm32f3/stm32.h +++ b/arch/arm/src/stm32f3/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig index 6d98f0577ac1e..1cc4bce80b43d 100644 --- a/arch/arm/src/stm32f4/Kconfig +++ b/arch/arm/src/stm32f4/Kconfig @@ -282,6 +282,8 @@ config STM32_STM32F4XXX select STM32_HAVE_IP_SPI_V2 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h b/arch/arm/src/stm32f4/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h rename to arch/arm/src/stm32f4/hardware/stm32_rcc.h index d4e56f3f29654..1fd8fa4670f6f 100644 --- a/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h +++ b/arch/arm/src/stm32f4/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h + * arch/arm/src/stm32f4/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -937,4 +937,4 @@ # define RCC_DCKCFGR2_SPDIFRXSEL_PLLI2S (1 << RCC_DCKCFGR2_SPDIFRXSEL_SHIFT) /* PLLI2S clock is selected as SPDIF-Rx clock */ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f4/stm32.h b/arch/arm/src/stm32f4/stm32.h index 56a9dbc8151a7..ec4aa1768ed7d 100644 --- a/arch/arm/src/stm32f4/stm32.h +++ b/arch/arm/src/stm32f4/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index 35b89101b155a..53178af169b42 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -85,10 +85,6 @@ if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_fmc.c) endif() -if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) - list(APPEND SRCS stm32_lsi.c) -endif() - if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() @@ -122,10 +118,6 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32_TIM) - list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) -endif() - if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() @@ -158,10 +150,6 @@ if(CONFIG_STM32_DMA2D) list(APPEND SRCS stm32_dma2d.c) endif() -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() - if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can.c) endif() diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 539914fbe7cdf..63821ed4b3247 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -653,9 +653,11 @@ config STM32_STM32F72XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -672,9 +674,11 @@ config STM32_STM32F73XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -691,9 +695,11 @@ config STM32_STM32F74XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -710,9 +716,11 @@ config STM32_STM32F75XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -729,9 +737,11 @@ config STM32_STM32F76XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -748,9 +758,11 @@ config STM32_STM32F77XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 30637c137f52f..aa7cec2c8e82e 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -84,10 +84,6 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) -CHIP_CSRCS += stm32_lsi.c -endif - ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif @@ -123,10 +119,6 @@ endif endif endif -ifeq ($(CONFIG_STM32_TIM),y) -CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c -endif - ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif @@ -159,9 +151,6 @@ ifeq ($(CONFIG_STM32_DMA2D),y) CHIP_CSRCS += stm32_dma2d.c endif -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder.c -endif ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) CHIP_CSRCS += stm32_can.c diff --git a/arch/arm/src/stm32f7/hardware/stm32_tim.h b/arch/arm/src/stm32f7/hardware/stm32f7_tim.h similarity index 97% rename from arch/arm/src/stm32f7/hardware/stm32_tim.h rename to arch/arm/src/stm32f7/hardware/stm32f7_tim.h index 6dfc200978cb5..41c96becc5e10 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f7_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f7/hardware/stm32_tim.h + * arch/arm/src/stm32f7/hardware/stm32f7_tim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f7/stm32.h b/arch/arm/src/stm32f7/stm32.h index 99c030c63377e..9f45242187e4b 100644 --- a/arch/arm/src/stm32f7/stm32.h +++ b/arch/arm/src/stm32f7/stm32.h @@ -52,7 +52,6 @@ #include "stm32_sdmmc.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_ethernet.h" diff --git a/arch/arm/src/stm32f7/stm32_capture.h b/arch/arm/src/stm32f7/stm32_capture.h index e5614788cb29c..3aca5ecbb70d9 100644 --- a/arch/arm/src/stm32f7/stm32_capture.h +++ b/arch/arm/src/stm32f7/stm32_capture.h @@ -31,7 +31,7 @@ #include "chip.h" #include -#include "hardware/stm32_tim.h" +#include "hardware/stm32f7_tim.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_lsi.c b/arch/arm/src/stm32f7/stm32_lsi.c deleted file mode 100644 index cc5e46b4fba92..0000000000000 --- a/arch/arm/src/stm32f7/stm32_lsi.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal RC 40 kHz oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 637833554eac9..7349eb00c9515 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -41,7 +41,7 @@ #ifdef CONFIG_STM32_PWM # include -# include "hardware/stm32_tim.h" +# include "hardware/stm32f7_tim.h" #endif /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_qencoder.c b/arch/arm/src/stm32f7/stm32_qencoder.c deleted file mode 100644 index fdf06b3bb0d4a..0000000000000 --- a/arch/arm/src/stm32f7/stm32_qencoder.c +++ /dev/null @@ -1,1183 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" -#include "stm32_qencoder.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timers *******************************************************************/ - -#undef HAVE_32BIT_TIMERS -#undef HAVE_16BIT_TIMERS - -/* On the F7 series, TIM2 and TIM5 are 32-bit. All of the rest are 16-bit */ - -/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ - -#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) -# define HAVE_32BIT_TIMERS 1 -#endif - -/* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) -# define HAVE_16BIT_TIMERS 1 -#endif - -/* The width in bits of each timer */ - -#define TIM1_BITWIDTH 16 -#define TIM2_BITWIDTH 32 -#define TIM3_BITWIDTH 16 -#define TIM4_BITWIDTH 16 -#define TIM5_BITWIDTH 32 -#define TIM8_BITWIDTH 16 - -/* Do we need to support mixed 16- and 32-bit timers */ - -#undef HAVE_MIXEDWIDTH_TIMERS -#if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_FILTER -# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32_QENCODER_ICF -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif -#ifdef CONFIG_STM32_STM32F10XX - uint16_t ti1cfg; /* TI1 input pin configuration (16-bit encoding) */ - uint16_t ti2cfg; /* TI2 input pin configuration (16-bit encoding) */ -#else - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ -#endif - uintptr_t regaddr; /* RCC clock enable register address */ - uint32_t enable; /* RCC clock enable bit */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Timer input clock prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; /* Lower half callback structure */ - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; /* static onfiguration */ - - bool inuse; /* True: The lower-half driver is in-use */ - -#ifdef HAVE_16BIT_TIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv,msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, - int32_t *pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = NULL, /* not supported yet */ - .reset = stm32_reset, - .setindex = NULL, /* not supported yet */ - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB2ENR, - .enable = RCC_APB2ENR_TIM1EN, - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1ENR, - .enable = RCC_APB1ENR_TIM2EN, - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1ENR, - .enable = RCC_APB1ENR_TIM3EN, - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1ENR, - .enable = RCC_APB1ENR_TIM4EN, - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM5_QE -static const struct stm32_qeconfig_s g_tim5config = -{ - .timid = 5, - .irq = STM32_IRQ_TIM5, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM5_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1ENR, - .enable = RCC_APB1ENR_TIM5EN, - .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32_TIM5_QEPSC, - .ti1cfg = GPIO_TIM5_CH1IN, - .ti2cfg = GPIO_TIM5_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim5lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim5config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM8_QE -static const struct stm32_qeconfig_s g_tim8config = -{ - .timid = 8, - .irq = STM32_IRQ_TIM8UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM8_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB2ENR, - .enable = RCC_APB2ENR_TIM8EN, - .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32_TIM8_QEPSC, - .ti1cfg = GPIO_TIM8_CH1IN, - .ti2cfg = GPIO_TIM8_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim8lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim8config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. This applies for the STM32 - * F7 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 (but - * works OK with the 16-bit TIM1,8 as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Write a value to a 32-bit timer register. This applies for the STM32 F7 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 (but - * works OK with the 16-bit TIM1,8 as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg16(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - return &g_tim4lower; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - return &g_tim5lower; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - return &g_tim8lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require timer - * interrupts. - * - ****************************************************************************/ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value + 1, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x00010000; - } - else - { - priv->position += (int32_t)0x00010000; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifdef HAVE_16BIT_TIMERS - uint16_t regval; - int ret; -#endif - - /* Enable clocking to the timer */ - - modifyreg32(priv->config->regaddr, 0, priv->config->enable); - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. - * - * If we are doing precise shaft positioning, each qe pulse is important. - * So the STM32 has direct config control on the pulse count prescaler. - * This input clock just limits the incoming pulse rate, which should be - * lower than the peripheral clock due to resynchronization, but it is the - * responsibility of the system designer to decide the correct prescaler - * value, because it has a direct influence on the encoder resolution. - */ - - stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1 and TIM8) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * should stop data collection, free any resources, disable timer hardware, - * and put the system into the lowest possible power usage state * - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM2RST; - break; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM3RST; - break; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM4RST; - break; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM5RST; - break; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM8RST; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32_dumpregs(priv, "After stop"); - - /* Disable clocking to the timer */ - - modifyreg32(priv->config->regaddr, priv->config->enable, 0); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. Interrupts are disabled to make this - * atomic (if possible) - */ - - flags = enter_critical_section(); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - leave_critical_section(flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. This function must be - * called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the upper-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#endif /* CONFIG_SENSORS_QENCODER */ diff --git a/arch/arm/src/stm32f7/stm32_qencoder.h b/arch/arm/src/stm32f7/stm32_qencoder.h deleted file mode 100644 index 40b2f6f92e148..0000000000000 --- a/arch/arm/src/stm32f7/stm32_qencoder.h +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32F7_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32F7_TIMn is defined - * then the CONFIG_STM32F7_TIMn_QE must also be defined to indicate that - * timer "n" is intended to be used for as a quadrature encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder - * (at least for the STM32 F7) - */ - -#undef CONFIG_STM32F7_TIM6_QE -#undef CONFIG_STM32F7_TIM7_QE -#undef CONFIG_STM32F7_TIM9_QE -#undef CONFIG_STM32F7_TIM10_QE -#undef CONFIG_STM32F7_TIM11_QE -#undef CONFIG_STM32F7_TIM12_QE -#undef CONFIG_STM32F7_TIM13_QE -#undef CONFIG_STM32F7_TIM14_QE - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic.. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. - * 'tim' must be an element of {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c deleted file mode 100644 index 6919283f9488b..0000000000000 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ /dev/null @@ -1,1572 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. - * Such special purposes include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32F7_TIMn is - * defined then CONFIG_STM32F7_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32F7_TIMn is defined - * then CONFIG_STM32F7_TIMn_DAC may also be defined to indicate that timer - * "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32F7_TIMn is defined then - * CONFIG_STM32F7_TIMn_QE may also be defined to indicate that timer - * "n" is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif -#if defined(CONFIG_STM32F7_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32F7_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif -#if defined(CONFIG_STM32F7_TIM7_PWM) || defined (CONFIG_STM32F7_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32F7_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif -#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32F7_TIM9_ADC) || \ - defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32F7_TIM9_QE) -# undef CONFIG_STM32_TIM9 -#endif -#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32F7_TIM10_ADC) || \ - defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32F7_TIM10_QE) -# undef CONFIG_STM32_TIM10 -#endif -#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32F7_TIM11_ADC) || \ - defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32F7_TIM11_QE) -# undef CONFIG_STM32_TIM11 -#endif -#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32F7_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32F7_TIM12_QE) -# undef CONFIG_STM32_TIM12 -#endif -#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32F7_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32F7_TIM13_QE) -# undef CONFIG_STM32_TIM13 -#endif -#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32F7_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32F7_TIM14_QE) -# undef CONFIG_STM32_TIM14 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif -#if defined(CONFIG_STM32_TIM9) -# if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\ - defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT) -# define HAVE_TIM9_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM10) -# if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\ - defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT) -# define HAVE_TIM10_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM11) -# if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\ - defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT) -# define HAVE_TIM11_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM12) -# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\ - defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM13) -# if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\ - defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM14) -# if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\ - defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, - uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, - clearbits, setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, - uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_getwidth - ****************************************************************************/ - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - /* Only TIM2 and TIM5 timers may be 32-bits in width - * - * Reference Table 2 of en.DM00042534.pdf - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { - /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */ - -#if defined(CONFIG_STM32_TIM2) - case STM32_TIM2_BASE: - return 32; -#endif - - /* TIM5 is 32-bits on all except F10x lines */ - -#if defined(CONFIG_STM32_TIM5) - case STM32_TIM5_BASE: - return 32; -#endif - - /* All others are 16-bit times */ - - default: - return 16; - } -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_setcounter - ****************************************************************************/ - -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count) -{ - DEBUGASSERT(dev != NULL); - - if (stm32_tim_getwidth(dev) > 16) - { - stm32_putreg32(dev, STM32_GTIM_CNT_OFFSET, count); - } - else - { - stm32_putreg16(dev, STM32_GTIM_CNT_OFFSET, (uint16_t)count); - } -} - -/* Reset timer into system default state, - * but do not affect output/input pins - */ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\ - defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\ - defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - freqin = STM32_TIM9_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - freqin = STM32_TIM10_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - freqin = STM32_TIM11_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - freqin = STM32_TIM12_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - freqin = STM32_TIM13_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_TIM14_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - vectorno = STM32_IRQ_TIM9; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - vectorno = STM32_IRQ_TIM10; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - vectorno = STM32_IRQ_TIM11; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - vectorno = STM32_IRQ_TIM12; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & source) ? 1 : 0; -} - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - - /* Our default: - * Interrupts are generated on compare, when counting down - */ - - val |= GTIM_CR1_CENTER1; - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - - return OK; -} - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - case STM32_TIM_CH_OUTTOGGLE: - ccmr_val = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -# if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -# if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -# if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -# if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -# if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -# if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif -# ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - switch (channel) - { -# if defined(GPIO_TIM9_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM9_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM9_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM9_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM9_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM9_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - switch (channel) - { -# if defined(GPIO_TIM10_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM10_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM10_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM10_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM10_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM10_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM10_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM10_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - switch (channel) - { -# if defined(GPIO_TIM11_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM11_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM11_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM11_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM11_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM11_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM11_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM11_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - switch (channel) - { -# if defined(GPIO_TIM12_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM12_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM12_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -# if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM13_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM13_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM13_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM13_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM13_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM13_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -# if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM14_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM14_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM14_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM14_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM14_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM14_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - } - - return OK; -} - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, - uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - default: - return -EINVAL; - } - - return OK; -} - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Advanced Functions - ****************************************************************************/ - -/* TODO: Advanced functions for the STM32_ATIM */ - -/**************************************************************************** - * Device Structures, Instantiation - ****************************************************************************/ - -struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setclock = stm32_tim_setclock, - .setperiod = stm32_tim_setperiod, - .getcounter = stm32_tim_getcounter, - .setcounter = stm32_tim_setcounter, - .getwidth = stm32_tim_getwidth, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -struct stm32_tim_priv_s stm32_tim9_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM9_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -struct stm32_tim_priv_s stm32_tim10_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM10_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -struct stm32_tim_priv_s stm32_tim11_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM11_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -/**************************************************************************** - * Public Function - Initialization - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/* TODO: Detach interrupts, and close down all TIM Channels */ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */ diff --git a/arch/arm/src/stm32f7/stm32_tim.h b/arch/arm/src/stm32f7/stm32_tim.h deleted file mode 100644 index e09b9b569b585..0000000000000 --- a/arch/arm/src/stm32f7/stm32_tim.h +++ /dev/null @@ -1,221 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F7_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, /* TODO: Not supported */ - STM32_TIM_MODE_CK_EXT = 0x0800, /* TODO: Not supported */ - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, /* TODO: Not supported */ -#endif - - /* Clock sources, OR'ed with CK_EXT */ -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, /* TODO: Not supported */ - STM32_TIM_MODE_CK_CH1 = 0x0001, /* TODO: Not supported */ - STM32_TIM_MODE_CK_CH2 = 0x0002, /* TODO: Not supported */ - STM32_TIM_MODE_CK_CH3 = 0x0003, /* TODO: Not supported */ - STM32_TIM_MODE_CK_CH4 = 0x0004 /* TODO: Not supported */ -#endif - - /* TODO: external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x0e, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, /* TODO: Not supported */ -#endif - STM32_TIM_CH_OUTTOGGLE = 0x08, - -#if 0 - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC /* -- open collector mode */ -#endif -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); - - /* General and Advanced Timers Adds */ - - int (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, - void * arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c deleted file mode 100644 index 1005d174f7569..0000000000000 --- a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,591 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) -# define STM32_TIM2_RES 16 -#else -# define STM32_TIM2_RES 32 -#endif - -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# define STM32_TIM5_RES 16 -#else -# define STM32_TIM5_RES 32 -#endif - -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM9_RES 16 -#define STM32_TIM10_RES 16 -#define STM32_TIM11_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -static struct stm32_lowerhalf_s g_tim9_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM9_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -static struct stm32_lowerhalf_s g_tim10_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM10_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -static struct stm32_lowerhalf_s g_tim11_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM11_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback. - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - lower = &g_tim9_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - lower = &g_tim10_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - lower = &g_tim11_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h b/arch/arm/src/stm32g0/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32g0/hardware/stm32g0_rcc.h rename to arch/arm/src/stm32g0/hardware/stm32_rcc.h index 3c5f8ca45217e..2f7100afd2302 100644 --- a/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h +++ b/arch/arm/src/stm32g0/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32g0/hardware/stm32g0_rcc.h + * arch/arm/src/stm32g0/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H -#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -363,4 +363,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32g0/stm32.h b/arch/arm/src/stm32g0/stm32.h index 243e25e7d3915..9e70f1bf95f02 100644 --- a/arch/arm/src/stm32g0/stm32.h +++ b/arch/arm/src/stm32g0/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig index 4638529bf1e01..0d24409442e05 100644 --- a/arch/arm/src/stm32g4/Kconfig +++ b/arch/arm/src/stm32g4/Kconfig @@ -131,6 +131,8 @@ config STM32_STM32G4XXX select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V3 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V4 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h b/arch/arm/src/stm32g4/hardware/stm32_rcc.h similarity index 98% rename from arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h rename to arch/arm/src/stm32g4/hardware/stm32_rcc.h index 0b4f2cb8c7613..8ae9536101728 100644 --- a/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h +++ b/arch/arm/src/stm32g4/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h + * arch/arm/src/stm32g4/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -692,5 +692,14 @@ #define RCC_APB1ENR_TIM3EN RCC_APB1ENR1_TIM3EN #define RCC_APB1ENR_TIM4EN RCC_APB1ENR1_TIM4EN #define RCC_APB1ENR_TIM5EN RCC_APB1ENR1_TIM5EN +#define RCC_APB1ENR_TIM6EN RCC_APB1ENR1_TIM6EN +#define RCC_APB1ENR_TIM7EN RCC_APB1ENR1_TIM7EN -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_RCC_H */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR1_TIM2RST +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR1_TIM3RST +#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR1_TIM4RST +#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR1_TIM5RST +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR1_TIM6RST +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR1_TIM7RST + +#endif /* __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32g4/stm32.h b/arch/arm/src/stm32g4/stm32.h index 07776d682753f..b87f810ac7d80 100644 --- a/arch/arm/src/stm32g4/stm32.h +++ b/arch/arm/src/stm32g4/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 249a64c3136a3..6f0bd554fa595 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -40,8 +40,7 @@ list( stm32_start.c stm32_pwr.c stm32_timerisr.c - stm32_lse.c - stm32_lsi.c) + stm32_lse.c) if(CONFIG_STM32_USART) list(APPEND SRCS stm32_serial.c) @@ -51,10 +50,6 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() - if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() @@ -83,10 +78,6 @@ if(CONFIG_STM32_QSPI1) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32_TIM) - list(APPEND SRCS stm32_tim.c) -endif() - if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32_hsi48.c) endif() diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index cdddeae584023..0c798a6cb17a1 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -65,9 +65,11 @@ config STM32_STM32H56XXX select STM32_HAVE_IP_CORDIC_M3M4_V1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index fd569978cb47f..734f3b3e25721 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -38,7 +38,7 @@ endif CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c CHIP_CSRCS += stm32_start.c stm32_pwr.c stm32_timerisr.c -CHIP_CSRCS += stm32_lse.c stm32_lsi.c +CHIP_CSRCS += stm32_lse.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c @@ -48,10 +48,6 @@ ifeq ($(CONFIG_STM32_USART),y) CHIP_CSRCS += stm32_serial.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif - ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif @@ -80,10 +76,6 @@ ifeq ($(CONFIG_STM32_QSPI1),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32_TIM),y) -CHIP_CSRCS += stm32_tim.c -endif - ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32_hsi48.c endif diff --git a/arch/arm/src/stm32h5/hardware/stm32_rcc.h b/arch/arm/src/stm32h5/hardware/stm32_rcc.h index cf8cc1fd0bd5f..eb2c965d7b5ff 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32_rcc.h @@ -28,13 +28,1219 @@ ****************************************************************************/ #include -#include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# include "hardware/stm32h5xxx_rcc.h" -#else -# error "Unsupported STM32 H5 rcc" -#endif +#if defined(CONFIG_STM32_STM32H5XXXX) -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RCC_H */ \ No newline at end of file +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_HSICFGR_OFFSET 0x0010 /* HSI Calibration Register */ +#define STM32_RCC_CRRCR_OFFSET 0x0014 /* RCC clock recovery RC register */ +#define STM32_RCC_CFGR1_OFFSET 0x001c /* RCC clock configuration register 1 */ +#define STM32_RCC_CFGR2_OFFSET 0x0020 /* RCC clock configuration register 2 */ +#define STM32_RCC_PLL1CFGR_OFFSET 0x0028 /* RCC PLL1 configuration register */ +#define STM32_RCC_PLL2CFGR_OFFSET 0x002c /* RCC PLL2 configuration register */ +#define STM32_RCC_PLL3CFGR_OFFSET 0x0030 /* RCC PLL3 configuration register */ +#define STM32_RCC_PLL1DIVR_OFFSET 0x0034 /* RCC PLL1 dividers register */ +#define STM32_RCC_PLL1FRACR_OFFSET 0x0038 /* RCC PLL1 fractional divider register */ +#define STM32_RCC_PLL2DIVR_OFFSET 0x003c /* RCC PLL2 dividers register */ +#define STM32_RCC_PLL2FRACR_OFFSET 0x0040 /* RCC PLL2 fractional divider register */ +#define STM32_RCC_PLL3DIVR_OFFSET 0x0044 /* RCC PLL3 dividers register */ +#define STM32_RCC_PLL3FRACR_OFFSET 0x0048 /* RCC PLL3 fractional divider register */ +#define STM32_RCC_CIER_OFFSET 0x0050 /* RCC clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x0054 /* RCC clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0058 /* RCC clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0060 /* RCC AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x0064 /* RCC AHB2 peripheral reset register 1 */ +#define STM32_RCC_AHB4RSTR_OFFSET 0x006c /* RCC AHB4 peripheral reset register*/ +#define STM32_RCC_APB1LRSTR_OFFSET 0x0074 /* RCC APB1 peripheral reset register 1 */ +#define STM32_RCC_APB1HRSTR_OFFSET 0x0078 /* RCC APB1 peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x007c /* RCC APB2 peripheral reset register */ +#define STM32_RCC_APB3RSTR_OFFSET 0x0080 /* RCC APB3 peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0088 /* RCC AHB1 peripheral clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x008c /* RCC AHB2 peripheral clock enable register */ +#define STM32_RCC_AHB4ENR_OFFSET 0x0094 /* RCC AHB4 peripheral clock enable register */ +#define STM32_RCC_APB1LENR_OFFSET 0x009c /* RCC APB1 peripheral clock enable register 1 */ +#define STM32_RCC_APB1HENR_OFFSET 0x00a0 /* RCC APB1 peripheral clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x00a4 /* RCC APB2 peripheral clock enable register */ +#define STM32_RCC_APB3ENR_OFFSET 0x00a8 /* RCC APB3 peripheral clock enable register */ +#define STM32_RCC_AHB1LPENR_OFFSET 0x00b0 /* RCC AHB1 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_AHB2LPENR_OFFSET 0x00b4 /* RCC AHB2 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_AHB4LPENR_OFFSET 0x00bc /* RCC AHB3 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_APB1LPENR1_OFFSET 0x00c4 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 */ +#define STM32_RCC_APB1LPENR2_OFFSET 0x00c8 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 */ +#define STM32_RCC_APB2LPENR_OFFSET 0x00cc /* RCC APB2 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_APB3LPENR_OFFSET 0x00d0 /* RCC APB3 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_CCIPR1_OFFSET 0x00d8 /* RCC peripherals independent clock configuration register 1 */ +#define STM32_RCC_CCIPR2_OFFSET 0x00dc /* RCC peripherals independent clock configuration register 2 */ +#define STM32_RCC_CCIPR3_OFFSET 0x00e0 /* RCC peripherals independent clock configuration register 3 */ +#define STM32_RCC_CCIPR4_OFFSET 0x00e4 /* RCC peripherals independent clock configuration register 5 */ +#define STM32_RCC_CCIPR5_OFFSET 0x00e8 /* RCC peripherals independent clock configuration register 5 */ +#define STM32_RCC_BDCR_OFFSET 0x00f0 /* RCC Backup domain control register */ +#define STM32_RCC_RSR_OFFSET 0x00f4 /* RCC control/status register */ /* TODO: CSR in U5 */ +#define STM32_RCC_SECCFGR_OFFSET 0x0110 /* RCC secure configuration register */ +#define STM32_RCC_PRIVCFGR_OFFSET 0x0114 /* RCC privilege configuration register */ + +/* Register Addresses *******************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_HSICFGR (STM32_RCC_BASE + STM32_RCC_HSICFGR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CFGR1 (STM32_RCC_BASE + STM32_RCC_CFGR1_OFFSET) +#define STM32_RCC_CFGR2 (STM32_RCC_BASE + STM32_RCC_CFGR2_OFFSET) +#define STM32_RCC_PLL1CFGR (STM32_RCC_BASE + STM32_RCC_PLL1CFGR_OFFSET) +#define STM32_RCC_PLL2CFGR (STM32_RCC_BASE + STM32_RCC_PLL2CFGR_OFFSET) +#define STM32_RCC_PLL3CFGR (STM32_RCC_BASE + STM32_RCC_PLL3CFGR_OFFSET) +#define STM32_RCC_PLL1DIVR (STM32_RCC_BASE + STM32_RCC_PLL1DIVR_OFFSET) +#define STM32_RCC_PLL1FRACR (STM32_RCC_BASE + STM32_RCC_PLL1FRACR_OFFSET) +#define STM32_RCC_PLL2DIVR (STM32_RCC_BASE + STM32_RCC_PLL2DIVR_OFFSET) +#define STM32_RCC_PLL2FRACR (STM32_RCC_BASE + STM32_RCC_PLL2FRACR_OFFSET) +#define STM32_RCC_PLL3DIVR (STM32_RCC_BASE + STM32_RCC_PLL3DIVR_OFFSET) +#define STM32_RCC_PLL3FRACR (STM32_RCC_BASE + STM32_RCC_PLL3FRACR_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB4RSTR (STM32_RCC_BASE + STM32_RCC_AHB4RSTR_OFFSET) +#define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) +#define STM32_RCC_APB1HRSTR (STM32_RCC_BASE + STM32_RCC_APB1HRSTR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB4ENR (STM32_RCC_BASE + STM32_RCC_AHB4ENR_OFFSET) +#define STM32_RCC_APB1LENR (STM32_RCC_BASE + STM32_RCC_APB1LENR_OFFSET) +#define STM32_RCC_APB1HENR (STM32_RCC_BASE + STM32_RCC_APB1HENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_APB3ENR (STM32_RCC_BASE + STM32_RCC_APB3ENR_OFFSET) +#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE + STM32_RCC_AHB1LPENR_OFFSET) +#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE + STM32_RCC_AHB2LPENR_OFFSET) +#define STM32_RCC_AHB4LPENR (STM32_RCC_BASE + STM32_RCC_AHB4LPENR_OFFSET) +#define STM32_RCC_APB1LPENR (STM32_RCC_BASE + STM32_RCC_APB1LPENR1_OFFSET) +#define STM32_RCC_APB1HPENR (STM32_RCC_BASE + STM32_RCC_APB1LPENR2_OFFSET) +#define STM32_RCC_APB2LPENR (STM32_RCC_BASE + STM32_RCC_APB2LPENR_OFFSET) +#define STM32_RCC_APB3LPENR (STM32_RCC_BASE + STM32_RCC_APB3LPENR_OFFSET) +#define STM32_RCC_CCIPR1 (STM32_RCC_BASE + STM32_RCC_CCIPR1_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CCIPR3 (STM32_RCC_BASE + STM32_RCC_CCIPR3_OFFSET) +#define STM32_RCC_CCIPR4 (STM32_RCC_BASE + STM32_RCC_CCIPR4_OFFSET) +#define STM32_RCC_CCIPR5 (STM32_RCC_BASE + STM32_RCC_CCIPR5_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_RSR (STM32_RCC_BASE + STM32_RCC_RSR_OFFSET) +#define STM32_RCC_SECCFGR (STM32_RCC_BASE + STM32_RCC_SECCFGR_OFFSET) +#define STM32_RCC_PRIVCFGR (STM32_RCC_BASE + STM32_RCC_PRIVCFGR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Clock control register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ +#define RCC_CR_HSIKERON (1 << 2) /* Bit 2: HSI clock enable in Stop mode */ +#define RCC_CR_HSIDIV_SHIFT (3) /* Bit [4:3] HSI Divider */ +#define RCC_CR_HSIDIV_MASK (0x3 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV(n) (((n) << RCC_CR_HSIDIV_SHIFT & RCC_CR_HSIDIV_MASK)) +#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI divider flag */ + +#define RCC_CR_CSION (1 << 8) /* Bit 8: CSI clock enable */ +#define RCC_CR_CSIRDY (1 << 9) /* Bit 9: CSI clock ready flag */ +#define RCC_CR_CSIKERON (1 << 10) /* Bit 10: CSI clock enable in Stop mode */ + +#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable */ +#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready flag */ + +#define RCC_CR_HSEON (1 << 16) /* Bit 16: HSE clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: HSE clock bypass */ +#define RCC_CR_HSECSSON (1 << 19) /* Bit 19: HSE clock security system enable */ +#define RCC_CR_HSEEXT (1 << 20) /* Bit 20: HSE external high speed clock + * type in bypass mode */ +#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: PLL1 enable */ +#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: PLL1 clock ready flag */ +#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: PLL2 enable */ +#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: PLL2 clock ready flag */ +#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: PLL3 enable */ +#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: PLL3 clock ready flag */ + +/* HSI Calibration register */ + +#define RCC_HSICFGR_HSITRIM_SHIFT (16) /* Bits 22-16: Internal High Speed clock trimming */ +#define RCC_HSICFGR_HSITRIM_MASK (0x7f << RCC_HSICFGR_HSITRIM_SHIFT) +#define RCC_HSICFGR_HSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ +#define RCC_HSICFGR_HSICAL_MASK (0xfff << RCC_HSICFGR_HSICAL_SHIFT) + +/* Clock Recovery RC register */ + +#define RCC_CRRCR_HSI48CAL_SHIFT (0) /* Bits 9-0: Internal RC 48MHz Clock Calibration */ +#define RCC_CRRCR_HSI48CAL_MASK (0x3ff << RCC_CRRCR_HSI48CAL_SHIFT) + +/* CSI Calibration register */ + +#define RCC_CSICFGR_CSITRIM_SHIFT (16) /* Bits 21-16: Internal High Speed clock trimming */ +#define RCC_CSICFGR_CSITRIM_MASK (0x3f << RCC_CSICFGR_CSITRIM_SHIFT) +#define RCC_CSICFGR_CSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ +#define RCC_CSICFGR_CSICAL_MASK (0xff << RCC_CSICFGR_CSICAL_SHIFT) + +/* Clock configuration register 1 */ + +#define RCC_CFGR1_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ +#define RCC_CFGR1_SW_MASK (3 << RCC_CFGR1_SW_SHIFT) +# define RCC_CFGR1_SW_MSI (0 << RCC_CFGR1_SW_SHIFT) /* 00: MSI selected as system clock */ +# define RCC_CFGR1_SW_HSI16 (1 << RCC_CFGR1_SW_SHIFT) /* 00: HSI16 selected as system clock */ +# define RCC_CFGR1_SW_HSE (2 << RCC_CFGR1_SW_SHIFT) /* 01: HSE selected as system clock */ +# define RCC_CFGR1_SW_PLL (3 << RCC_CFGR1_SW_SHIFT) /* 10: PLL selected as system clock */ + +#define RCC_CFGR1_SWS_SHIFT (3) /* Bits 3-4: System Clock Switch Status */ +#define RCC_CFGR1_SWS_MASK (3 << RCC_CFGR1_SWS_SHIFT) +# define RCC_CFGR1_SWS_MSI (0 << RCC_CFGR1_SWS_SHIFT) /* 00: MSI oscillator used as system clock */ +# define RCC_CFGR1_SWS_HSI16 (1 << RCC_CFGR1_SWS_SHIFT) /* 00: HSI16 oscillator used as system clock */ +# define RCC_CFGR1_SWS_HSE (2 << RCC_CFGR1_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ +# define RCC_CFGR1_SWS_PLL (3 << RCC_CFGR1_SWS_SHIFT) /* 10: PLL used as system clock */ + +#define RCC_CFGR1_STOPWUCK (1 << 6) /* System clock selection after a wakeup from system stop */ +#define RCC_CFGR1_STOPKERWUCK (1 << 7) /* Kernel clock selection after a wakeup from system stop */ + +#define RCC_CFGR1_RTCPRE_SHIFT (8) /* Bits 13-8: RTC prescaler */ +#define RCC_CFGR1_RTCPRE_MASK (0x3f << RCC_CFGR1_RTCPRE_SHIFT) +# define RCC_CFGR1_RTCPRE_HSE (0 << RCC_CFGR1_RTCPRE_SHIFT) /* 0xxx: HSE not divided */ +# define RCC_CFGR1_RTCPRE_HSEd2 (2 << RCC_CFGR1_RTCPRE_SHIFT) /* 10: HSE divided by 2 */ +# define RCC_CFGR1_RTCPRE_HSEd4 (4 << RCC_CFGR1_RTCPRE_SHIFT) /* 100: HSE divided by 4 */ +# define RCC_CFGR1_RTCPRE_HSEd8 (8 << RCC_CFGR1_RTCPRE_SHIFT) /* 1000: HSE divided by 8 */ +# define RCC_CFGR1_RTCPRE_HSEd16 (16 << RCC_CFGR1_RTCPRE_SHIFT) /* 10000: HSE divided by 16 */ +# define RCC_CFGR1_RTCPRE_HSEd32 (32 << RCC_CFGR1_RTCPRE_SHIFT) /* 100000: HSE divided by 32 */ +# define RCC_CFGR1_RTCPRE_HSEd63 (63 << RCC_CFGR1_RTCPRE_SHIFT) /* 111111: HSE divided by 63 */ + +#define RCC_CFGR1_TIMPRE (1 << 15) /* timers clocks prescaler selection */ + +#define RCC_CFGR1_MCO1PRE_SHIFT (18) /* Bits 21-18: MCO1 Prescaler */ +#define RCC_CFGR1_MCO1PRE_MASK (0xf << RCC_CFGR1_MCO1PRE_SHIFT) +# define RCC_CFGR1_MCO1PRE_MCO1 (0 << RCC_CFGR1_MCO1PRE_SHIFT) /* 0xx: MCO1 not divided */ +# define RCC_CFGR1_MCO1PRE_MCO1d2 (2 << RCC_CFGR1_MCO1PRE_SHIFT) /* 10: MCO1 divided by 2 */ +# define RCC_CFGR1_MCO1PRE_MCO1d4 (4 << RCC_CFGR1_MCO1PRE_SHIFT) /* 100: MCO1 divided by 4 */ +# define RCC_CFGR1_MCO1PRE_MCO1d8 (8 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1000: MCO1 divided by 8 */ +# define RCC_CFGR1_MCO1PRE_MCO1d15 (15 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1111: MCO1 divided by 15 */ + +#define RCC_CFGR1_MCO1SEL_SHIFT (22) /* Bits 24-22: Microcontroller Clock Output1 */ +#define RCC_CFGR1_MCO1SEL_MASK (0x7 << RCC_CFGR1_MCO1SEL_SHIFT) +# define RCC_CFGR1_MCO1SEL_HSI (0 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0000: HSI clock selected */ +# define RCC_CFGR1_MCO1SEL_LSE (1 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0001: LSE clock selected */ +# define RCC_CFGR1_MCO1SEL_HSE (2 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0010: HSE clock selected */ +# define RCC_CFGR1_MCO1SEL_PLL1 (3 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0011: Main PLL1 selected */ +# define RCC_CFGR1_MCO1SEL_HSI48 (4 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0100: HSI48 clock selected */ + +#define RCC_CFGR1_MCO2PRE_SHIFT (25) /* Bits 28-25: MCO2 Prescaler */ +#define RCC_CFGR1_MCO2PRE_MASK (0xf << RCC_CFGR1_MCO2PRE_SHIFT) +# define RCC_CFGR1_MCO2PRE_MCO2 (0 << RCC_CFGR1_MCO2PRE_SHIFT) /* 0xx: MCO2 not divided */ +# define RCC_CFGR1_MCO2PRE_MCO2d2 (2 << RCC_CFGR1_MCO2PRE_SHIFT) /* 10: MCO2 divided by 2 */ +# define RCC_CFGR1_MCO2PRE_MCO2d4 (4 << RCC_CFGR1_MCO2PRE_SHIFT) /* 100: MCO2 divided by 4 */ +# define RCC_CFGR1_MCO2PRE_MCO2d8 (8 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1000: MCO2 divided by 8 */ +# define RCC_CFGR1_MCO2PRE_MCO2d15 (15 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1111: MCO2 divided by 15 */ + +#define RCC_CFGR1_MCO2SEL_SHIFT (29) /* Bits 31-29: Microcontroller Clock Output1 */ +#define RCC_CFGR1_MCO2SEL_MASK (0x7 << RCC_CFGR1_MCO2SEL_SHIFT) +# define RCC_CFGR1_MCO2SEL_SYSCLLK (0 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0000: Main SYSCLLK selected */ +# define RCC_CFGR1_MCO2SEL_PLL2 (1 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0001: Main PLL2 selected */ +# define RCC_CFGR1_MCO2SEL_HSE (2 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0010: HSE clock selected */ +# define RCC_CFGR1_MCO2SEL_PLL1 (3 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0011: Main PLL1 selected */ +# define RCC_CFGR1_MCO2SEL_CSI (4 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0100: CSI clock selected */ +# define RCC_CFGR1_MCO2SEL_LSI (5 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0101: LSI clock selected */ + +/* Clock configuration register 2 */ + +#define RCC_CFGR2_HPRE_SHIFT (0) /* Bits 3-0: HPRE Prescaler */ +#define RCC_CFGR2_HPRE_MASK (0xf << RCC_CFGR2_HPRE_SHIFT) +# define RCC_CFGR2_HPRE_SYSCLK (0 << RCC_CFGR2_HPRE_SHIFT) /* 0xx: SYSCLK not divided */ +# define RCC_CFGR2_HPRE_SYSCLKd2 (8 << RCC_CFGR2_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR2_HPRE_SYSCLKd4 (9 << RCC_CFGR2_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR2_HPRE_SYSCLKd8 (10 << RCC_CFGR2_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ +# define RCC_CFGR2_HPRE_SYSCLKd16 (11 << RCC_CFGR2_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ +# define RCC_CFGR2_HPRE_SYSCLKd64 (12 << RCC_CFGR2_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ +# define RCC_CFGR2_HPRE_SYSCLKd128 (13 << RCC_CFGR2_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ +# define RCC_CFGR2_HPRE_SYSCLKd256 (14 << RCC_CFGR2_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ +# define RCC_CFGR2_HPRE_SYSCLKd512 (15 << RCC_CFGR2_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ + +#define RCC_CFGR2_PPRE1_SHIFT (4) /* Bits 6-4: PPRE1 Prescaler */ +#define RCC_CFGR2_PPRE1_MASK (0x7 << RCC_CFGR2_PPRE1_SHIFT) +# define RCC_CFGR2_PPRE1_HCLK1 (0 << RCC_CFGR2_PPRE1_SHIFT) /* 0xx: HCLK1 not divided */ +# define RCC_CFGR2_PPRE1_HCLK1d2 (4 << RCC_CFGR2_PPRE1_SHIFT) /* 100: HCLK1 divided by 2 */ +# define RCC_CFGR2_PPRE1_HCLK1d4 (5 << RCC_CFGR2_PPRE1_SHIFT) /* 101: HCLK1 divided by 4 */ +# define RCC_CFGR2_PPRE1_HCLK1d8 (6 << RCC_CFGR2_PPRE1_SHIFT) /* 110: HCLK1 divided by 8 */ +# define RCC_CFGR2_PPRE1_HCLK1d16 (7 << RCC_CFGR2_PPRE1_SHIFT) /* 111: HCLK1 divided by 16 */ + +#define RCC_CFGR2_PPRE2_SHIFT (8) /* Bits 10-8: PPRE2 Prescaler */ +#define RCC_CFGR2_PPRE2_MASK (0x7 << RCC_CFGR2_PPRE2_SHIFT) +# define RCC_CFGR2_PPRE2_HCLK1 (0 << RCC_CFGR2_PPRE2_SHIFT) /* 0xx: HCLK1 not divided */ +# define RCC_CFGR2_PPRE2_HCLK1d2 (4 << RCC_CFGR2_PPRE2_SHIFT) /* 1000: HCLK1 divided by 2 */ +# define RCC_CFGR2_PPRE2_HCLK1d4 (5 << RCC_CFGR2_PPRE2_SHIFT) /* 1001: HCLK1 divided by 4 */ +# define RCC_CFGR2_PPRE2_HCLK1d8 (6 << RCC_CFGR2_PPRE2_SHIFT) /* 1010: HCLK1 divided by 8 */ +# define RCC_CFGR2_PPRE2_HCLK1d16 (7 << RCC_CFGR2_PPRE2_SHIFT) /* 1011: HCLK1 divided by 16 */ + +#define RCC_CFGR2_PPRE3_SHIFT (12) /* Bits 14-12: PPRE3 Prescaler */ +#define RCC_CFGR2_PPRE3_MASK (0x7 << RCC_CFGR2_PPRE3_SHIFT) +# define RCC_CFGR2_PPRE3_HCLK1 (0 << RCC_CFGR2_PPRE3_SHIFT) /* 0xx: HCLK1 not divided */ +# define RCC_CFGR2_PPRE3_HCLK1d2 (4 << RCC_CFGR2_PPRE3_SHIFT) /* 100: HCLK1 divided by 2 */ +# define RCC_CFGR2_PPRE3_HCLK1d4 (5 << RCC_CFGR2_PPRE3_SHIFT) /* 101: HCLK1 divided by 4 */ +# define RCC_CFGR2_PPRE3_HCLK1d8 (6 << RCC_CFGR2_PPRE3_SHIFT) /* 110: HCLK1 divided by 8 */ +# define RCC_CFGR2_PPRE3_HCLK1d16 (7 << RCC_CFGR2_PPRE3_SHIFT) /* 111: HCLK1 divided by 16 */ + +#define RCC_CFGR2_AHB1DIS (1 << 16) /* AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS (1 << 17) /* AHB2 clock disable */ +#define RCC_CFGR2_AHB4DIS (1 << 19) /* AHB4 clock disable */ +#define RCC_CFGR2_APB1DIS (1 << 20) /* APB1 clock disable */ +#define RCC_CFGR2_APB2DIS (1 << 21) /* APB2 clock disable */ +#define RCC_CFGR2_APB3DIS (1 << 22) /* APB3 clock disable */ + +/* PLL1 configuration register */ + +#define RCC_PLL1CFGR_PLL1SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) + * entry clock source */ +#define RCC_PLL1CFGR_PLL1SRC_MASK (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) +# define RCC_PLL1CFGR_PLL1SRC_NONE (0 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 000: No clock sent to PLLs */ +# define RCC_PLL1CFGR_PLL1SRC_HSI (1 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 001: HSI selected as PLL source */ +# define RCC_PLL1CFGR_PLL1SRC_CSI (2 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 010: CSI selected as PLL source */ +# define RCC_PLL1CFGR_PLL1SRC_HSE (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 011: HSE selected as PLL source */ + +#define RCC_PLL1CFGR_PLL1RGE_SHIFT (2) /* Bit 3-2: */ +#define RCC_PLL1CFGR_PLL1RGE_MASK (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) +# define RCC_PLL1CFGR_PLL1RGE_1_2M (0 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ +# define RCC_PLL1CFGR_PLL1RGE_2_4M (1 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ +# define RCC_PLL1CFGR_PLL1RGE_4_8M (2 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ +# define RCC_PLL1CFGR_PLL1RGE_8_16M (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ + +#define RCC_PLL1CFGR_PLL1FRACEN (1 << 4) /* PLL1 Fractional Latch Enable */ +#define RCC_PLL1CFGR_PLL1VCOSEL (1 << 5) /* PLL1 VCO Selection */ + +#define RCC_PLL1CFGR_PLL1M_SHIFT (8) /* Bit 13-8: */ +#define RCC_PLL1CFGR_PLL1M_MASK (0x3f << RCC_PLL1CFGR_PLL1M_SHIFT) +# define RCC_PLL1CFGR_PLL1M(n) ((n) << RCC_PLL1CFGR_PLL1M_SHIFT) /* m = 1..63 */ + +#define RCC_PLL1CFGR_PLL1PEN (1 << 16) /* PLL1 DIVP divder output enable */ +#define RCC_PLL1CFGR_PLL1QEN (1 << 17) /* PLL1 DIVQ divder output enable */ +#define RCC_PLL1CFGR_PLL1REN (1 << 18) /* PLL1 DIVR divder output enable */ + +/* PLL2 configuration register */ + +#define RCC_PLL2CFGR_PLL2SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) + * entry clock source */ +#define RCC_PLL2CFGR_PLL2SRC_MASK (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) +# define RCC_PLL2CFGR_PLL2SRC_NONE (0 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 000: No clock sent to PLLs */ +# define RCC_PLL2CFGR_PLL2SRC_HSI (1 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 001: HSI selected as PLL source */ +# define RCC_PLL2CFGR_PLL2SRC_CSI (2 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 010: CSI selected as PLL source */ +# define RCC_PLL2CFGR_PLL2SRC_HSE (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 011: HSE selected as PLL source */ + +#define RCC_PLL2CFGR_PLL2RGE_SHIFT (2) /* Bit 3-2: */ +#define RCC_PLL2CFGR_PLL2RGE_MASK (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) +# define RCC_PLL2CFGR_PLL2RGE_1_2M (0 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ +# define RCC_PLL2CFGR_PLL2RGE_2_4M (1 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ +# define RCC_PLL2CFGR_PLL2RGE_4_8M (2 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz */ +# define RCC_PLL2CFGR_PLL2RGE_8_16M (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz */ + +#define RCC_PLL2CFGR_PLL2FRACEN (1 << 4) /* PLL2 Fractional Latch Enable */ +#define RCC_PLL2CFGR_PLL2VCOSEL (1 << 5) /* PLL2 VCO Selection */ + +#define RCC_PLL2CFGR_PLL2M_SHIFT (8) /* Bit 13-8: */ +#define RCC_PLL2CFGR_PLL2M_MASK (0x3f << RCC_PLL2CFGR_PLL2M_SHIFT) +# define RCC_PLL2CFGR_PLL2M(n) ((n) << RCC_PLL2CFGR_PLL2M_SHIFT) /* m = 1..63 */ + +#define RCC_PLL2CFGR_PLL2PEN (1 << 16) /* PLL2 DIVP divder output enable */ +#define RCC_PLL2CFGR_PLL2QEN (1 << 17) /* PLL2 DIVQ divder output enable */ +#define RCC_PLL2CFGR_PLL2REN (1 << 18) /* PLL2 DIVR divder output enable */ + +/* PLL3 configuration register */ + +#define RCC_PLL3CFGR_PLL3SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) + * entry clock source */ +#define RCC_PLL3CFGR_PLL3SRC_MASK (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) +# define RCC_PLL3CFGR_PLL3SRC_NONE (0 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 000: No clock sent to PLLs */ +# define RCC_PLL3CFGR_PLL3SRC_HSI (1 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 001: HSI selected as PLL source */ +# define RCC_PLL3CFGR_PLL3SRC_CSI (2 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 010: CSI selected as PLL source */ +# define RCC_PLL3CFGR_PLL3SRC_HSE (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 011: HSE selected as PLL source */ + +#define RCC_PLL3CFGR_PLL3RGE_SHIFT (2) /* Bit 3-2: */ +#define RCC_PLL3CFGR_PLL3RGE_MASK (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) +# define RCC_PLL3CFGR_PLL3RGE_1_2M (0 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ +# define RCC_PLL3CFGR_PLL3RGE_2_4M (1 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ +# define RCC_PLL3CFGR_PLL3RGE_4_8M (2 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ +# define RCC_PLL3CFGR_PLL3RGE_8_16M (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ + +#define RCC_PLL3CFGR_PLL3FRACEN (1 << 4) /* PLL3 Fractional Latch Enable */ +#define RCC_PLL3CFGR_PLL3VCOSEL (1 << 5) /* PLL3 VCO Selection */ + +#define RCC_PLL3CFGR_PLL3M_SHIFT (8) /* Bit 13-8: */ +#define RCC_PLL3CFGR_PLL3M_MASK (0x3f << RCC_PLL3CFGR_PLL3M_SHIFT) +# define RCC_PLL3CFGR_PLL3M(n) ((n) << RCC_PLL3CFGR_PLL3M_SHIFT) /* m = 1..63 */ + +#define RCC_PLL3CFGR_PLL3PEN (1 << 16) /* PLL3 DIVP divder output enable */ +#define RCC_PLL3CFGR_PLL3QEN (1 << 17) /* PLL3 DIVQ divder output enable */ +#define RCC_PLL3CFGR_PLL3REN (1 << 18) /* PLL3 DIVR divder output enable */ + +/* PLL1 dividers register */ + +#define RCC_PLL1DIVR_PLL1N_SHIFT (0) /* Bits 8-0: */ +#define RCC_PLL1DIVR_PLL1N_MASK (0x1ff << RCC_PLL1DIVR_PLL1N_SHIFT) +# define RCC_PLL1DIVR_PLL1N(n) ((n-1) << RCC_PLL1DIVR_PLL1N_SHIFT) /* m = 4..512 */ + +#define RCC_PLL1DIVR_PLL1P_SHIFT (9) /* Bits 15-9: */ +#define RCC_PLL1DIVR_PLL1P_MASK (0x7f << RCC_PLL1DIVR_PLL1P_SHIFT) +# define RCC_PLL1DIVR_PLL1P(n) ((n-1) << RCC_PLL1DIVR_PLL1P_SHIFT) /* m = 2..128 evens */ + +#define RCC_PLL1DIVR_PLL1Q_SHIFT (16) /* Bits 22-16: */ +#define RCC_PLL1DIVR_PLL1Q_MASK (0x7f << RCC_PLL1DIVR_PLL1Q_SHIFT) +# define RCC_PLL1DIVR_PLL1Q(n) ((n-1) << RCC_PLL1DIVR_PLL1Q_SHIFT) /* m = 1..128 */ + +#define RCC_PLL1DIVR_PLL1R_SHIFT (24) /* Bits 30-24: */ +#define RCC_PLL1DIVR_PLL1R_MASK (0x7f << RCC_PLL1DIVR_PLL1R_SHIFT) +# define RCC_PLL1DIVR_PLL1R(n) ((n-1) << RCC_PLL1DIVR_PLL1R_SHIFT) /* m = 1..128 */ + +/* PLL1 fractional divider register */ + +#define RCC_PLL1FRACR_PLL1FRACN_SHIFT (3) +#define RCC_PLL1FRACR_PLL1FRACN_MASK (0x1fff << RCC_PLL1FRACR_PLL1FRACN_SHIFT) +#define RCC_PLL1FRACR_PLL1FRACN(n) (n << RCC_PLL1FRACR_PLL1FRACN_SHIFT) /* m = 0..8192 */ + +/* PLL2 dividers register */ + +#define RCC_PLL2DIVR_PLL2N_SHIFT (0) /* Bits 8-0: */ +#define RCC_PLL2DIVR_PLL2N_MASK (0x1ff << RCC_PLL2DIVR_PLL2N_SHIFT) +# define RCC_PLL2DIVR_PLL2N(n) ((n-1) << RCC_PLL2DIVR_PLL2N_SHIFT) /* m = 4..512 */ + +#define RCC_PLL2DIVR_PLL2P_SHIFT (9) /* Bits 15-9: */ +#define RCC_PLL2DIVR_PLL2P_MASK (0x7f << RCC_PLL2DIVR_PLL2P_SHIFT) +# define RCC_PLL2DIVR_PLL2P(n) ((n-1) << RCC_PLL2DIVR_PLL2P_SHIFT) /* m = 2..128 evens */ + +#define RCC_PLL2DIVR_PLL2Q_SHIFT (16) /* Bits 22-16: */ +#define RCC_PLL2DIVR_PLL2Q_MASK (0x7f << RCC_PLL2DIVR_PLL2Q_SHIFT) +# define RCC_PLL2DIVR_PLL2Q(n) ((n-1) << RCC_PLL2DIVR_PLL2Q_SHIFT) /* m = 1..128 */ + +#define RCC_PLL2DIVR_PLL2R_SHIFT (24) /* Bits 30-24: */ +#define RCC_PLL2DIVR_PLL2R_MASK (0x7f << RCC_PLL2DIVR_PLL2R_SHIFT) +# define RCC_PLL2DIVR_PLL2R(n) ((n-1) << RCC_PLL2DIVR_PLL2R_SHIFT) /* m = 1..128 */ + +/* PLL2 fractional divider register */ + +#define RCC_PLL2FRACR_PLL2FRACN_SHIFT (3) +#define RCC_PLL2FRACR_PLL2FRACN_MASK (0x1fff << RCC_PLL2FRACR_PLL2FRACN_SHIFT) +#define RCC_PLL2FRACR_PLL2FRACN(n) (n << RCC_PLL2FRACR_PLL2FRACN_SHIFT) /* m = 0..8192 */ + +/* PLL3 dividers register */ + +#define RCC_PLL3DIVR_PLL3N_SHIFT (0) /* Bits 8-0: */ +#define RCC_PLL3DIVR_PLL3N_MASK (0x1ff << RCC_PLL3DIVR_PLL3N_SHIFT) +# define RCC_PLL3DIVR_PLL3N(n) ((n-1) << RCC_PLL3DIVR_PLL3N_SHIFT) /* m = 4..512 */ + +#define RCC_PLL3DIVR_PLL3P_SHIFT (9) /* Bits 15-9: */ +#define RCC_PLL3DIVR_PLL3P_MASK (0x7f << RCC_PLL3DIVR_PLL3P_SHIFT) +# define RCC_PLL3DIVR_PLL3P(n) ((n-1) << RCC_PLL3DIVR_PLL3P_SHIFT) /* m = 2..128 evens */ + +#define RCC_PLL3DIVR_PLL3Q_SHIFT (16) /* Bits 22-16: */ +#define RCC_PLL3DIVR_PLL3Q_MASK (0x7f << RCC_PLL3DIVR_PLL3Q_SHIFT) +# define RCC_PLL3DIVR_PLL3Q(n) ((n-1) << RCC_PLL3DIVR_PLL3Q_SHIFT) /* m = 1..128 */ + +#define RCC_PLL3DIVR_PLL3R_SHIFT (24) /* Bits 30-24: */ +#define RCC_PLL3DIVR_PLL3R_MASK (0x7f << RCC_PLL3DIVR_PLL3R_SHIFT) +# define RCC_PLL3DIVR_PLL3R(n) ((n-1) << RCC_PLL3DIVR_PLL3R_SHIFT) /* m = 1..128 */ + +/* PLL3 fractional divider register */ + +#define RCC_PLL3FRACR_PLL3FRACN_SHIFT (3) +#define RCC_PLL3FRACR_PLL3FRACN_MASK (0x1fff << RCC_PLL3FRACR_PLL3FRACN_SHIFT) +#define RCC_PLL3FRACR_PLL3FRACN(n) (n << RCC_PLL3FRACR_PLL3FRACN_SHIFT) /* m = 0..8192 */ + +/* Clock interrupt enable register */ + +#define RCC_CIER_LSIRDYIE (1 << 0) /* Bit 0: LSI Ready Interrupt Enable */ +#define RCC_CIER_LSERDYIE (1 << 1) /* Bit 1: LSE Ready Interrupt Enable */ +#define RCC_CIER_CSIRDYIE (1 << 2) /* Bit 2: CSI Ready Interrupt Enable */ +#define RCC_CIER_HSIRDYIE (1 << 3) /* Bit 3: HSI Ready Interrupt Enable */ +#define RCC_CIER_HSERDYIE (1 << 4) /* Bit 4: HSE Ready Interrupt Enable */ +#define RCC_CIER_HSI48RDYIE (1 << 5) /* Bit 5: HSI48 Ready Interrupt Enable */ +#define RCC_CIER_PLL1RDYIE (1 << 6) /* Bit 6: PLL1 Ready Interrupt Enable */ +#define RCC_CIER_PLL2RDYIE (1 << 7) /* Bit 7: PLL2 Ready Interrupt Enable */ +#define RCC_CIER_PLL3RDYIE (1 << 8) /* Bit 8: PLL3 Ready Interrupt Enable */ + +/* Clock interrupt flag register */ + +#define RCC_CIFR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ +#define RCC_CIFR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ +#define RCC_CIFR_CSIRDYF (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ +#define RCC_CIFR_HSIRDYF (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ +#define RCC_CIFR_HSERDYF (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ +#define RCC_CIFR_HSI48RDYF (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ +#define RCC_CIFR_PLL1RDYF (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ +#define RCC_CIFR_PLL2RDYF (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ +#define RCC_CIFR_PLL3RDYF (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ +#define RCC_CIFR_HSECSSF (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ + +/* Clock interrupt clear register */ + +#define RCC_CICR_LSIRDYC (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ +#define RCC_CICR_LSERDYC (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ +#define RCC_CICR_CSIRDYC (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ +#define RCC_CICR_HSIRDYC (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ +#define RCC_CICR_HSERDYC (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ +#define RCC_CICR_HSI48RDYC (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ +#define RCC_CICR_PLL1RDYC (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ +#define RCC_CICR_PLL2RDYC (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ +#define RCC_CICR_PLL3RDYC (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ +#define RCC_CICR_HSECSSC (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ + +/* AHB1 peripheral reset register */ + +#define RCC_AHB1RSTR_GPDMA1RST (1 << 0) /* Bit 0: GPDMA1 reset */ +#define RCC_AHB1RSTR_GPDMA2RST (1 << 1) /* Bit 1: GPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12: CRC reset */ +#define RCC_AHB1RSTR_CORDICRST (1 << 14) /* Bit 14: CORDIC reset */ +#define RCC_AHB1RSTR_FMACRST (1 << 15) /* Bit 15: FMAC reset */ +#define RCC_AHB1RSTR_RAMCFGRST (1 << 17) /* Bit 17: RAMCFG reset */ +#define RCC_AHB1RSTR_ETHRST (1 << 19) /* Bit 19: ETH reset */ + +/* AHB2 peripheral reset register */ + +#define RCC_AHB2RSTR_GPIORST(n) (1 << (n)) +#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */ +#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */ +#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */ +#define RCC_AHB2RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */ +#define RCC_AHB2RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */ +#define RCC_AHB2RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */ +#define RCC_AHB2RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ +#define RCC_AHB2RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ +#define RCC_AHB2RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */ +#define RCC_AHB2RSTR_ADCRST (1 << 10) /* Bit 10: ADC interface reset (common to all ADCs) */ +#define RCC_AHB2RSTR_DACRST (1 << 11) /* Bit 11: DAC Block reset */ +#define RCC_AHB2RSTR_DCMI_PSSIRST (1 << 12) /* Bit 12: Digital Camera Interface block reset */ +#define RCC_AHB2RSTR_AESRST (1 << 16) /* Bit 16: AES Cryptographic module reset */ +#define RCC_AHB2RSTR_HASHRST (1 << 17) /* Bit 17: HASH block reset */ +#define RCC_AHB2RSTR_RNGRST (1 << 18) /* Bit 18: Random number generator module reset */ +#define RCC_AHB2RSTR_PKARST (1 << 19) /* Bit 19: Public Key Accelerator module reset */ +#define RCC_AHB2RSTR_SAESRST (1 << 20) /* Bit 20: SAES block reset */ + +/* AHB4 peripheral reset register */ + +#define RCC_AHB4RSTR_OTFDEC1RST (1 << 7) /* Bit 0: OTFDEC1 block reset */ +#define RCC_AHB4RSTR_SDMMC1RST (1 << 11) /* Bit 11: SDMMC1RST blocks reset */ +#define RCC_AHB4RSTR_SDMMC2RST (1 << 12) /* Bit 12: SDMMC2RST blocks reset */ +#define RCC_AHB4RSTR_FMCRST (1 << 16) /* Bit 16: FMC block reset */ +#define RCC_AHB4RSTR_OSPI1RST (1 << 20) /* Bit 20: OCTOSPI1 block reset */ + +/* APB1 Peripheral reset register 1 */ + +#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */ +#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */ +#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */ +#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */ +#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* Bit 5: TIM12 reset */ +#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* Bit 5: TIM13 reset */ +#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* Bit 5: TIM14 reset */ +#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* Bit 14: SPI2 reset */ +#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* Bit 15: SPI3 reset */ +#define RCC_APB1LRSTR_USART2RST (1 << 17) /* Bit 17: USART2 reset */ +#define RCC_APB1LRSTR_USART3RST (1 << 18) /* Bit 18: USART3 reset */ +#define RCC_APB1LRSTR_UART4RST (1 << 19) /* Bit 19: UART4 reset */ +#define RCC_APB1LRSTR_UART5RST (1 << 20) /* Bit 20: UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* Bit 21: I2C1 reset */ +#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* Bit 22: I2C2 reset */ +#define RCC_APB1LRSTR_I3C1RST (1 << 23) /* Bit 23: I3C1 reset */ +#define RCC_APB1LRSTR_CRSRST (1 << 24) /* Bit 24: CRS reset */ +#define RCC_APB1LRSTR_USART6RST (1 << 25) /* Bit 25: USART6 reset */ +#define RCC_APB1LRSTR_USART10RST (1 << 26) /* Bit 26: USART10 reset */ +#define RCC_APB1LRSTR_USART11RST (1 << 27) /* Bit 27: USART11 reset */ +#define RCC_APB1LRSTR_CECRST (1 << 28) /* Bit 28: CEC reset */ +#define RCC_APB1LRSTR_UART7RST (1 << 30) /* Bit 30: UART7 reset */ +#define RCC_APB1LRSTR_UART8RST (1 << 31) /* Bit 31: UART8 reset */ + +/* APB1 Peripheral reset register 2 */ + +#define RCC_APB1HRSTR_UART9RST (1 << 0) /* Bit 0: UART9 reset */ +#define RCC_APB1HRSTR_UART12RST (1 << 1) /* Bit 1: UART12 reset */ +#define RCC_APB1HRSTR_DTSRST (1 << 3) /* Bit 3: DTS reset */ +#define RCC_APB1HRSTR_LPTIM2RST (1 << 5) /* Bit 5: Low-power Timer 2 reset */ +#define RCC_APB1HRSTR_FDCANRST (1 << 9) /* Bit 9: FDCAN reset */ +#define RCC_APB1HRSTR_UCPD1RST (1 << 23) /* Bit 23: UCPD1 reset */ + +/* APB2 Peripheral reset register */ + +#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 reset */ +#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */ +#define RCC_APB2RSTR_SPI4RST (1 << 19) /* Bit 19: SPI4 reset */ +#define RCC_APB2RSTR_SPI67RST (1 << 20) /* Bit 20: SPI6 reset */ +#define RCC_APB2RSTR_SAI1RST (1 << 21) /* Bit 21: SAI1 reset */ +#define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 22: SAI2 reset */ +#define RCC_APB2RSTR_USBRST (1 << 24) /* Bit 24: USB reset */ + +/* APB3 Peripheral reset register */ + +#define RCC_APB3RSTR_SPI5RST (1 << 5) /* Bit 5: SPI5 reset */ +#define RCC_APB3RSTR_LPUART1RST (1 << 6) /* Bit 6: LPUART1 reset */ +#define RCC_APB3RSTR_I2C3RST (1 << 7) /* Bit 7: I2C3 reset */ +#define RCC_APB3RSTR_I2C4RST (1 << 8) /* Bit 8: I2C4 reset */ +#define RCC_APB3RSTR_I3C2RST (1 << 9) /* Bit 9: I3C2 reset */ +#define RCC_APB3RSTR_LPTIM1RST (1 << 11) /* Bit 11: LPTIM1 reset */ +#define RCC_APB3RSTR_LPTIM3RST (1 << 12) /* Bit 12: LPTIM3 reset */ +#define RCC_APB3RSTR_LPTIM4RST (1 << 13) /* Bit 13: LPTIM4 reset */ +#define RCC_APB3RSTR_LPTIM5RST (1 << 14) /* Bit 14: LPTIM5 reset */ +#define RCC_APB3RSTR_LPTIM6RST (1 << 15) /* Bit 15: LPTIM6 reset */ +#define RCC_APB3RSTR_VREFRST (1 << 20) /* Bit 20: VREF reset */ + +/* AHB1 Peripheral Clock enable register */ + +#define RCC_AHB1ENR_GPDMA1EN (1 << 0) /* Bit 0: GPDMA1 clock enable */ +#define RCC_AHB1ENR_GPDMA2EN (1 << 1) /* Bit 1: GPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN (1 << 8) /* Bit 8: Flash Interface clock enable */ +#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN (1 << 14) /* Bit 14: CORDIC clock enable */ +#define RCC_AHB1ENR_FMACEN (1 << 15) /* Bit 15: FMAC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN (1 << 17) /* Bit 17: RAMCFG clock enable */ +#define RCC_AHB1ENR_ETHEN (1 << 19) /* Bit 19: ETH clock enable */ +#define RCC_AHB1ENR_ETHTXEN (1 << 20) /* Bit 20: ETH TX clock enable */ +#define RCC_AHB1ENR_ETHRXEN (1 << 21) /* Bit 21: ETH RX clock enable */ +#define RCC_AHB1ENR_TZSC1EN (1 << 24) /* Bit 24: TZSC1 clock enable */ +#define RCC_AHB1ENR_BKPRAMEN (1 << 28) /* Bit 28: BKPRAM clock enable */ +#define RCC_AHB1ENR_DCACHEEN (1 << 30) /* Bit 25: DCACHE clock enable */ +#define RCC_AHB1ENR_SRAM1EN (1 << 31) /* Bit 25: SRAM1 clock enable */ + +/* AHB2 Peripheral Clock enable register */ + +#define RCC_AHB2ENR_GPIOEN(n) (1 << (n)) +#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */ +#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */ +#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */ +#define RCC_AHB2ENR_GPIODEN (1 << 3) /* Bit 3: IO port D enable */ +#define RCC_AHB2ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E enable */ +#define RCC_AHB2ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F enable */ +#define RCC_AHB2ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G enable */ +#define RCC_AHB2ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H enable */ +#define RCC_AHB2ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I enable */ +#define RCC_AHB2ENR_ADCEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ +#define RCC_AHB2ENR_DAC1EN (1 << 11) /* Bit 11: DAC clock enable */ +#define RCC_AHB2ENR_DCMI_PSSIEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ +#define RCC_AHB2ENR_AESEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ +#define RCC_AHB2ENR_HASHEN (1 << 17) /* Bit 17: HASH module enable */ +#define RCC_AHB2ENR_RNGEN (1 << 18) /* Bit 18: Random number generator module enable */ +#define RCC_AHB2ENR_PKAEN (1 << 19) /* Bit 19: PKA clock enable */ +#define RCC_AHB2ENR_SAESEN (1 << 20) /* Bit 20: SAES clock enable */ +#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* Bit 30: SRAM2 clock enable */ +#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* Bit 30: SRAM2 clock enable */ + +/* AHB4 Peripheral Clock enable register */ + +#define RCC_AHB4ENR_OTFDEC1EN (1 << 7) /* Bit 7: On-the-fly decryption module clock enable */ +#define RCC_AHB4ENR_SDMMC1EN (1 << 11) /* Bit 11: SDMMC1 clock enable */ +#define RCC_AHB4ENR_SDMMC2EN (1 << 12) /* Bit 12: SDMMC2 clock enable */ +#define RCC_AHB4ENR_FMCEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ +#define RCC_AHB4ENR_OSPI1EN (1 << 20) /* Bit 20: OCTOSPI1 module enable */ + +/* APB1 Peripheral clock enable register 1 */ + +#define RCC_APB1LENR_TIM2EN (1 << 0) /* Bit 0: TIM2 clock enable */ +#define RCC_APB1LENR_TIM3EN (1 << 1) /* Bit 1: TIM3 clock enable */ +#define RCC_APB1LENR_TIM4EN (1 << 2) /* Bit 2: TIM4 clock enable */ +#define RCC_APB1LENR_TIM5EN (1 << 3) /* Bit 3: TIM5 clock enable */ +#define RCC_APB1LENR_TIM6EN (1 << 4) /* Bit 4: TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN (1 << 5) /* Bit 5: TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN (1 << 6) /* Bit 5: TIM12 clock enable */ +#define RCC_APB1LENR_TIM13EN (1 << 7) /* Bit 5: TIM13 clock enable */ +#define RCC_APB1LENR_TIM14EN (1 << 8) /* Bit 5: TIM14 clock enable */ +#define RCC_APB1LENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */ +#define RCC_APB1LENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */ +#define RCC_APB1LENR_USART2EN (1 << 17) /* Bit 17: USART2 clock enable */ +#define RCC_APB1LENR_USART3EN (1 << 18) /* Bit 18: USART3 clock enable */ +#define RCC_APB1LENR_UART4EN (1 << 19) /* Bit 19: UART4 clock enable */ +#define RCC_APB1LENR_UART5EN (1 << 20) /* Bit 20: UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */ +#define RCC_APB1LENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */ +#define RCC_APB1LENR_I3C1EN (1 << 23) /* Bit 23: I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN (1 << 24) /* Bit 24: CRS clock enable */ +#define RCC_APB1LENR_USART6EN (1 << 25) /* Bit 25: USART6 clock enable */ +#define RCC_APB1LENR_USART10EN (1 << 26) /* Bit 26: USART10 clock enable */ +#define RCC_APB1LENR_USART11EN (1 << 27) /* Bit 27: USART11 clock enable */ +#define RCC_APB1LENR_CECEN (1 << 28) /* Bit 28: CEC clock enable */ +#define RCC_APB1LENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */ +#define RCC_APB1LENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */ + +/* APB1 Peripheral clock enable register 2 */ + +#define RCC_APB1HENR_UART9EN (1 << 0) /* Bit 0: UART9 clock enable */ +#define RCC_APB1HENR_UART12EN (1 << 1) /* Bit 1: UART12 clock enable */ +#define RCC_APB1HENR_DTSEN (1 << 3) /* Bit 3: DTS clock enable */ +#define RCC_APB1HENR_LPTIM2EN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable */ +#define RCC_APB1HENR_FDCANEN (1 << 9) /* Bit 9: FDCAN clock enable */ +#define RCC_APB1HENR_UCPD1EN (1 << 23) /* Bit 23: UCPD1 clock enable */ + +/* APB2 Peripheral clock enable register */ + +#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 clock enable */ +#define RCC_APB2ENR_SPI4EN (1 << 19) /* Bit 19: SPI4 clock enable */ +#define RCC_APB2ENR_SPI67EN (1 << 20) /* Bit 20: SPI6 clock enable */ +#define RCC_APB2ENR_SAI1EN (1 << 21) /* Bit 21: SAI1 clock enable */ +#define RCC_APB2ENR_SAI2EN (1 << 22) /* Bit 22: SAI2 clock enable */ +#define RCC_APB2ENR_USBEN (1 << 24) /* Bit 24: USB clock enable */ + +/* APB3 Peripheral clock enable register */ + +#define RCC_APB3ENR_SBSEN (1 << 1) /* Bit 1: SBS clock enable */ +#define RCC_APB3ENR_SPI5EN (1 << 5) /* Bit 5: SPI5 clock enable */ +#define RCC_APB3ENR_LPUART1EN (1 << 6) /* Bit 6: LPUART1 clock enable */ +#define RCC_APB3ENR_I2C3EN (1 << 7) /* Bit 7: I2C3 clock enable */ +#define RCC_APB3ENR_I2C4EN (1 << 8) /* Bit 8: I2C4 clock enable */ +#define RCC_APB3ENR_I3C2EN (1 << 9) /* Bit 9: I3C2 clock enable */ +#define RCC_APB3ENR_LPTIM1EN (1 << 11) /* Bit 11: LPTIM1 clock enable */ +#define RCC_APB3ENR_LPTIM3EN (1 << 12) /* Bit 12: LPTIM3 clock enable */ +#define RCC_APB3ENR_LPTIM4EN (1 << 13) /* Bit 13: LPTIM4 clock enable */ +#define RCC_APB3ENR_LPTIM5EN (1 << 14) /* Bit 14: LPTIM5 clock enable */ +#define RCC_APB3ENR_LPTIM6EN (1 << 15) /* Bit 15: LPTIM6 clock enable */ +#define RCC_APB3ENR_VREFEN (1 << 20) /* Bit 20: VREF clock enable */ +#define RCC_APB3ENR_RTCAPBEN (1 << 21) /* Bit 21: RTCABP clock enable */ + +/* RCC AHB1 Sleep and Stop modes peripheral clock enable register */ + +#define RCC_AHB1LPENR_GPDMA1LPEN (1 << 0) /* Bit 0: GPDMA1 clock enable during sleep mode */ +#define RCC_AHB1LPENR_GPDMA2LPEN (1 << 1) /* Bit 1: GPDMA2 clock enable during sleep mode */ +#define RCC_AHB1LPENR_FLITFLPEN (1 << 8) /* Bit 8: Flash Interface clock enable during sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during sleep mode */ +#define RCC_AHB1LPENR_CORDICLPEN (1 << 14) /* Bit 14: CORDIC clock enable during sleep mode */ +#define RCC_AHB1LPENR_FMACLPEN (1 << 15) /* Bit 15: FMAC clock enable during sleep mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN (1 << 17) /* Bit 17: RAMCFG clock enable during sleep mode */ +#define RCC_AHB1LPENR_ETHLPEN (1 << 19) /* Bit 19: ETH clock enable during sleep mode */ +#define RCC_AHB1LPENR_ETHTXLPEN (1 << 20) /* Bit 20: ETH TX clock enable during sleep mode */ +#define RCC_AHB1LPENR_ETHRXLPEN (1 << 21) /* Bit 21: ETH RX clock enable during sleep mode */ +#define RCC_AHB1LPENR_TZSC1LPEN (1 << 24) /* Bit 24: TZSC1 clock enable during sleep mode */ +#define RCC_AHB1LPENR_BKPRAMLPEN (1 << 28) /* Bit 28: BKPRAM clock enable during sleep mode */ +#define RCC_AHB1LPENR_DCACHELPEN (1 << 30) /* Bit 25: DCACHE clock enable during sleep mode */ +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 31) /* Bit 25: SRAM1 clock enable during sleep mode */ + +/* RCC AHB2 low power mode peripheral clock enable register */ + +#define RCC_AHB2LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during sleep mode */ +#define RCC_AHB2LPENR_ADCLPEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ +#define RCC_AHB2LPENR_DAC1LPEN (1 << 11) /* Bit 11: DAC clock enable during sleep mode */ +#define RCC_AHB2LPENR_DCMI_PSSILPEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ +#define RCC_AHB2LPENR_AESLPEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ +#define RCC_AHB2LPENR_HASHLPEN (1 << 17) /* Bit 17: HASH module enable */ +#define RCC_AHB2LPENR_RNGLPEN (1 << 18) /* Bit 18: Random number generator module enable */ +#define RCC_AHB2LPENR_PKALPEN (1 << 19) /* Bit 19: PKA clock enable during sleep mode */ +#define RCC_AHB2LPENR_SAESLPEN (1 << 20) /* Bit 20: SAES clock enable during sleep mode */ +#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* Bit 30: SRAM2 clock enable during sleep mode */ +#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* Bit 30: SRAM2 clock enable during sleep mode */ + +/* RCC AHB4 low power mode peripheral clock enable register */ + +#define RCC_AHB4LPENR_OTFDEC1LPEN (1 << 7) /* Bit 7: OTFDEC1 clock enable during sleep mode */ +#define RCC_AHB4LPENR_SDMMC1LPEN (1 << 11) /* Bit 11: SDMMC1 clock enable during sleep mode */ +#define RCC_AHB4LPENR_SDMMC2LPEN (1 << 12) /* Bit 12: SDMMC2 clock enable during sleep mode */ +#define RCC_AHB4LPENR_FMCLPEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ +#define RCC_AHB4LPENR_OSPI1LPEN (1 << 20) /* Bit 20: OCTOSPI1 module clock enable during sleep mode */ + +/* APB1 Peripheral clock enable register 1 */ + +#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM3 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM4 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM5 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM6 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM7 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 clock enable during sleep mode */ +#define RCC_APB1LLPENR_WWDGLPEN (1 << 11) /* Bit 11: WWDG clock enable during sleep mode */ +#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI3 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* Bit 17: USART2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* Bit 18: USART3 clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* Bit 19: UART4 clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* Bit 20: UART5 clock enable during sleep mode */ +#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C1 clock enable during sleep mode */ +#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_I3C1LPEN (1 << 23) /* Bit 23: I3C1 clock enable during sleep mode */ +#define RCC_APB1LLPENR_CRSLPEN (1 << 24) /* Bit 24: CRS clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART6LPEN (1 << 25) /* Bit 25: USART6 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART10LPEN (1 << 26) /* Bit 26: USART10 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART11LPEN (1 << 27) /* Bit 27: USART11 clock enable during sleep mode */ +#define RCC_APB1LLPENR_CECLPEN (1 << 28) /* Bit 28: CEC clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* Bit 30: UART7 clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* Bit 31: UART8 clock enable during sleep mode */ + +/* APB1 Peripheral clock enable register 2 */ + +#define RCC_APB1HLPENR_UART9LPEN (1 << 0) /* Bit 0: UART9 clock enable during sleep mode */ +#define RCC_APB1HLPENR_UART12LPEN (1 << 1) /* Bit 1: UART12 clock enable during sleep mode */ +#define RCC_APB1HLPENR_DTSLPEN (1 << 3) /* Bit 3: DTS clock enable during sleep mode */ +#define RCC_APB1HLPENR_LPTIM2LPEN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable during sleep mode */ +#define RCC_APB1HLPENR_FDCANLPEN (1 << 9) /* Bit 9: FDCAN clock enable during sleep mode */ +#define RCC_APB1HLPENR_UCPD1LPEN (1 << 23) /* Bit 23: UCPD1 clock enable during sleep mode */ + +/* APB2 Peripheral clock enable register */ + +#define RCC_APB2LPENR_TIM1LPEN (1 << 11) /* Bit 11: TIM1 clock enable during sleep mode */ +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 13) /* Bit 13: TIM8 clock enable during sleep mode */ +#define RCC_APB2LPENR_USART1LPEN (1 << 14) /* Bit 14: USART1 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* Bit 16: TIM15 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* Bit 17: TIM16 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* Bit 18: TIM17 clock enable during sleep mode */ +#define RCC_APB2LPENR_SPI4LPEN (1 << 19) /* Bit 19: SPI4 clock enable during sleep mode */ +#define RCC_APB2LPENR_SPI67LPEN (1 << 20) /* Bit 20: SPI6 clock enable during sleep mode */ +#define RCC_APB2LPENR_SAI1LPEN (1 << 21) /* Bit 21: SAI1 clock enable during sleep mode */ +#define RCC_APB2LPENR_SAI2LPEN (1 << 22) /* Bit 22: SAI2 clock enable during sleep mode */ +#define RCC_APB2LPENR_USBLPEN (1 << 24) /* Bit 24: USB clock enable during sleep mode */ + +/* APB3 Peripheral clock enable register */ + +#define RCC_APB3LPENR_SBSLPEN (1 << 1) /* Bit 1: SBS clock enable during sleep mode */ +#define RCC_APB3LPENR_SPI5LPEN (1 << 5) /* Bit 5: SPI5 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPUART1LPEN (1 << 6) /* Bit 6: LPUART1 clock enable during sleep mode */ +#define RCC_APB3LPENR_I2C3LPEN (1 << 7) /* Bit 7: I2C3 clock enable during sleep mode */ +#define RCC_APB3LPENR_I2C4LPEN (1 << 8) /* Bit 8: I2C4 clock enable during sleep mode */ +#define RCC_APB3LPENR_I3C2LPEN (1 << 9) /* Bit 9: I3C2 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM1LPEN (1 << 11) /* Bit 11: LPTIM1 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM3LPEN (1 << 12) /* Bit 12: LPTIM3 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM4LPEN (1 << 13) /* Bit 13: LPTIM4 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM5LPEN (1 << 14) /* Bit 14: LPTIM5 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM6LPEN (1 << 15) /* Bit 15: LPTIM6 clock enable during sleep mode */ +#define RCC_APB3LPENR_VREFLPEN (1 << 20) /* Bit 20: VREF clock enable during sleep mode */ +#define RCC_APB3LPENR_RTCAPBLPEN (1 << 21) /* Bit 21: RTCABP clock enable during sleep mode */ + +/* Kernel Clock Configuration register 1 */ + +#define RCC_CCIPR1_USART1SEL_SHIFT (0) +#define RCC_CCIPR1_USART1SEL_MASK (7 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_PLL2QCK (1 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_PLL3QCK (2 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_HSIKERCK (3 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_CSIKERCK (4 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_LSECK (5 << RCC_CCIPR1_USART1SEL_SHIFT) + +#define RCC_CCIPR1_USART2SEL_SHIFT (3) +#define RCC_CCIPR1_USART2SEL_MASK (7 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_PLL2QCK (1 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_PLL3QCK (2 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_HSIKERCK (3 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_CSIKERCK (4 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_LSECK (5 << RCC_CCIPR1_USART2SEL_SHIFT) + +#define RCC_CCIPR1_USART3SEL_SHIFT (6) +#define RCC_CCIPR1_USART3SEL_MASK (7 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_PLL2QCK (1 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_PLL3QCK (2 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_HSIKERCK (3 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_CSIKERCK (4 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_LSECK (5 << RCC_CCIPR1_USART3SEL_SHIFT) + +#define RCC_CCIPR1_UART4SEL_SHIFT (9) +#define RCC_CCIPR1_UART4SEL_MASK (7 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_PLL2QCK (1 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_PLL3QCK (2 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_HSIKERCK (3 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_CSIKERCK (4 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_LSECK (5 << RCC_CCIPR1_UART4SEL_SHIFT) + +#define RCC_CCIPR1_UART5SEL_SHIFT (12) +#define RCC_CCIPR1_UART5SEL_MASK (7 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_PLL2QCK (1 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_PLL3QCK (2 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_HSIKERCK (3 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_CSIKERCK (4 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_LSECK (5 << RCC_CCIPR1_UART5SEL_SHIFT) + +#define RCC_CCIPR1_UART6SEL_SHIFT (15) +#define RCC_CCIPR1_UART6SEL_MASK (7 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_PLL2QCK (1 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_PLL3QCK (2 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_HSIKERCK (3 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_CSIKERCK (4 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_LSECK (5 << RCC_CCIPR1_UART6SEL_SHIFT) + +#define RCC_CCIPR1_UART7SEL_SHIFT (18) +#define RCC_CCIPR1_UART7SEL_MASK (7 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_PLL2QCK (1 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_PLL3QCK (2 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_HSIKERCK (3 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_CSIKERCK (4 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_LSECK (5 << RCC_CCIPR1_UART7SEL_SHIFT) + +#define RCC_CCIPR1_UART8SEL_SHIFT (21) +#define RCC_CCIPR1_UART8SEL_MASK (7 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_PLL2QCK (1 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_PLL3QCK (2 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_HSIKERCK (3 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_CSIKERCK (4 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_LSECK (5 << RCC_CCIPR1_UART8SEL_SHIFT) + +#define RCC_CCIPR1_UART9SEL_SHIFT (24) +#define RCC_CCIPR1_UART9SEL_MASK (7 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_PLL2QCK (1 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_PLL3QCK (2 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_HSIKERCK (3 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_CSIKERCK (4 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_LSECK (5 << RCC_CCIPR1_UART9SEL_SHIFT) + +#define RCC_CCIPR1_USART10SEL_SHIFT (27) +#define RCC_CCIPR1_USART10SEL_MASK (7 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_PLL2QCK (1 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_PLL3QCK (2 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_HSIKERCK (3 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_CSIKERCK (4 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_LSECK (5 << RCC_CCIPR1_USART10SEL_SHIFT) + +#define RCC_CCIPR1_TIMICSEL (1 << 31) + +/* Kernel Clock Configuration register 2 */ + +#define RCC_CCIPR2_USART11SEL_SHIFT (0) +#define RCC_CCIPR2_USART11SEL_MASK (7 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_PLL2QCK (1 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_PLL3QCK (2 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_HSIKERCK (3 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_CSIKERCK (4 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_LSECK (5 << RCC_CCIPR2_USART11SEL_SHIFT) + +#define RCC_CCIPR2_USART12SEL_SHIFT (4) +#define RCC_CCIPR2_USART12SEL_MASK (7 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_PLL2QCK (1 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_PLL3QCK (2 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_HSIKERCK (3 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_CSIKERCK (4 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_LSECK (5 << RCC_CCIPR2_USART12SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM1SEL_SHIFT (8) +#define RCC_CCIPR2_LPTIM1SEL_MASK (7 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_LSECK (5 << RCC_CCIPR2_LPTIM1SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM2SEL_SHIFT (12) +#define RCC_CCIPR2_LPTIM2SEL_MASK (7 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_RCCPCLK1 (0 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_LSECK (5 << RCC_CCIPR2_LPTIM2SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM3SEL_SHIFT (16) +#define RCC_CCIPR2_LPTIM3SEL_MASK (7 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_LSECK (5 << RCC_CCIPR2_LPTIM3SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM4SEL_SHIFT (20) +#define RCC_CCIPR2_LPTIM4SEL_MASK (7 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_LSECK (5 << RCC_CCIPR2_LPTIM4SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM5SEL_SHIFT (24) +#define RCC_CCIPR2_LPTIM5SEL_MASK (7 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_LSECK (5 << RCC_CCIPR2_LPTIM5SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM6SEL_SHIFT (28) +#define RCC_CCIPR2_LPTIM6SEL_MASK (7 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_LSECK (5 << RCC_CCIPR2_LPTIM6SEL_SHIFT) + +/* Kernel Clock Configuration register 3 */ + +#define RCC_CCIPR3_SPI1SEL_SHIFT (0) +#define RCC_CCIPR3_SPI1SEL_MASK (7 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PLL1QCK (0 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PLL2PCK (1 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PLL3PCK (2 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_AUDIOCK (3 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PERCK (4 << RCC_CCIPR3_SPI1SEL_SHIFT) + +#define RCC_CCIPR3_SPI2SEL_SHIFT (3) +#define RCC_CCIPR3_SPI2SEL_MASK (7 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PLL1QCK (0 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PLL2PCK (1 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PLL3PCK (2 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_AUDIOCK (3 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PERCK (4 << RCC_CCIPR3_SPI2SEL_SHIFT) + +#define RCC_CCIPR3_SPI3SEL_SHIFT (6) +#define RCC_CCIPR3_SPI3SEL_MASK (7 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PLL1QCK (0 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PLL2PCK (1 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PLL3PCK (2 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_AUDIOCK (3 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PERCK (4 << RCC_CCIPR3_SPI3SEL_SHIFT) + +#define RCC_CCIPR3_SPI4SEL_SHIFT (9) +#define RCC_CCIPR3_SPI4SEL_MASK (7 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_PLL2QCK (1 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_PLL3QCK (2 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_HSIKERCK (3 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_CSIKERCK (4 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_HSECK (5 << RCC_CCIPR3_SPI4SEL_SHIFT) + +#define RCC_CCIPR3_SPI5SEL_SHIFT (12) +#define RCC_CCIPR3_SPI5SEL_MASK (7 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_RCCPCLK3 (0 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_PLL2QCK (1 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_PLL3QCK (2 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_HSIKERCK (3 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_CSIKERCK (4 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_HSECK (5 << RCC_CCIPR3_SPI5SEL_SHIFT) + +#define RCC_CCIPR3_SPI6SEL_SHIFT (15) +#define RCC_CCIPR3_SPI6SEL_MASK (7 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_PLL2QCK (1 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_PLL3QCK (2 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_HSIKERCK (3 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_CSIKERCK (4 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_HSECK (5 << RCC_CCIPR3_SPI6SEL_SHIFT) + +#define RCC_CCIPR3_LPUART1SEL_SHIFT (24) +#define RCC_CCIPR3_LPUART1SEL_MASK (7 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_RCCPCLK3 (0 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_PLL2QCK (1 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_PLL3QCK (2 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_HSIKERCK (3 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_CSIKERCK (4 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_LSECK (5 << RCC_CCIPR3_LPUART1SEL_SHIFT) + +/* Kernel Clock Configuration register 4 */ + +#define RCC_CCIPR4_OCTOSPI1SEL_SHIFT (0) +#define RCC_CCIPR4_OCTOSPI1SEL_MASK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_RCCHCLK4 (0 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_PLL1QCK (1 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_PLL2RCK (2 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_PERCK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) + +#define RCC_CCIPR4_SYSTICKSEL_SHIFT (2) +#define RCC_CCIPR4_SYSTICKSEL_MASK (3 << RCC_CCIPR4_SYSTICKSEL_SHIFT) +# define RCC_CCIPR4_SYSTICKSEL_RCCHCLKd8 (0 << RCC_CCIPR4_SYSTICKSEL_SHIFT) +# define RCC_CCIPR4_SYSTICKSEL_LSIKERCK1 (1 << RCC_CCIPR4_SYSTICKSEL_SHIFT) +# define RCC_CCIPR4_SYSTICKSEL_LSICK1 (2 << RCC_CCIPR4_SYSTICKSEL_SHIFT) + +#define RCC_CCIPR4_USBSEL_SHIFT (4) +#define RCC_CCIPR4_USBSEL_MASK (3 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_NOCK (0 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_PLL1QCK (1 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_PLL3QCK (2 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_HSI48KERCK (3 << RCC_CCIPR4_USBSEL_SHIFT) + +#define RCC_CCIPR4_SDMMC1SEL (1 << 6) +#define RCC_CCIPR4_SDMMC2SEL (1 << 7) + +#define RCC_CCIPR4_I2C1SEL_SHIFT (16) +#define RCC_CCIPR4_I2C1SEL_MASK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_PLL3RCK (1 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_HSIKERCK (2 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_CSIKERCK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) + +#define RCC_CCIPR4_I2C2SEL_SHIFT (18) +#define RCC_CCIPR4_I2C2SEL_MASK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_PLL3RCK (1 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_HSIKERCK (2 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_CSIKERCK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) + +#define RCC_CCIPR4_I2C3SEL_SHIFT (20) +#define RCC_CCIPR4_I2C3SEL_MASK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_PLL3RCK (1 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_HSIKERCK (2 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_CSIKERCK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) + +#define RCC_CCIPR4_I2C4SEL_SHIFT (22) +#define RCC_CCIPR4_I2C4SEL_MASK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_PLL3RCK (1 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_HSIKERCK (2 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_CSIKERCK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) + +#define RCC_CCIPR4_I3C1SEL_SHIFT (24) +#define RCC_CCIPR4_I3C1SEL_MASK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_PLL3RCK (1 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_HSIKERCK (2 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_NOCK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) + +#define RCC_CCIPR4_I3C2SEL_SHIFT (24) +#define RCC_CCIPR4_I3C2SEL_MASK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_PLL3RCK (1 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_HSIKERCK (2 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_NOCK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) + +/* Kernel Clock Configuration register 5 */ + +#define RCC_CCIPR5_ADCDACSEL_SHIFT (0) +#define RCC_CCIPR5_ADCDACSEL_MASK (7 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_RCCHCLK (0 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_SYSCK (1 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_PLL2RCK (2 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_HSECK (3 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_HSEKERCK (4 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_CSIKERCK (5 << RCC_CCIPR5_ADCDACSEL_SHIFT) + +#define RCC_CCIPR5_DACSEL (1 << 3) + +#define RCC_CCIPR5_RNGSEL_SHIFT (4) +#define RCC_CCIPR5_RNGSEL_MASK (3 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_HSI48KERCK (0 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_PLL1QCK (1 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_LSECK (2 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_LSIKERCK (3 << RCC_CCIPR5_RNGSEL_SHIFT) + +#define RCC_CCIPR5_CECSEL_SHIFT (6) +#define RCC_CCIPR5_CECSEL_MASK (3 << RCC_CCIPR5_CECSEL_SHIFT) +# define RCC_CCIPR5_CECSEL_LSECK (0 << RCC_CCIPR5_CECSEL_SHIFT) +# define RCC_CCIPR5_CECSEL_LSIKERCK (1 << RCC_CCIPR5_CECSEL_SHIFT) +# define RCC_CCIPR5_CECSEL_CSIKERCKd122 (2 << RCC_CCIPR5_CECSEL_SHIFT) + +#define RCC_CCIPR5_FDCANSEL_SHIFT (8) +#define RCC_CCIPR5_FDCANSEL_MASK (3 << RCC_CCIPR5_FDCANSEL_SHIFT) +# define RCC_CCIPR5_FDCANSEL_HSECK (0 << RCC_CCIPR5_FDCANSEL_SHIFT) +# define RCC_CCIPR5_FDCANSEL_PLL1QCK (1 << RCC_CCIPR5_FDCANSEL_SHIFT) +# define RCC_CCIPR5_FDCANSEL_PLL2QCK (2 << RCC_CCIPR5_FDCANSEL_SHIFT) + +#define RCC_CCIPR5_SAI1SEL_SHIFT (16) +#define RCC_CCIPR5_SAI1SEL_MASK (7 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PLL1QCK (0 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PLL2PCK (1 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PLL3PCK (2 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PERCK (4 << RCC_CCIPR5_SAI1SEL_SHIFT) + +#define RCC_CCIPR5_SAI2SEL_SHIFT (19) +#define RCC_CCIPR5_SAI2SEL_MASK (7 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PLL1QCK (0 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PLL2PCK (1 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PLL3PCK (2 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PERCK (4 << RCC_CCIPR5_SAI2SEL_SHIFT) + +#define RCC_CCIPR5_CKPERSEL_SHIFT (30) +#define RCC_CCIPR5_CKPERSEL_MASK (3 << RCC_CCIPR5_CKPERSEL_SHIFT) +# define RCC_CCIPR5_CKPERSEL_HSIKERCK (0 << RCC_CCIPR5_CKPERSEL_SHIFT) +# define RCC_CCIPR5_CKPERSEL_CSIKERCK (1 << RCC_CCIPR5_CKPERSEL_SHIFT) +# define RCC_CCIPR5_CKPERSEL_HSECK (2 << RCC_CCIPR5_CKPERSEL_SHIFT) + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ + +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE oscillator drive capability */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) +# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */ +# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */ +# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/ +# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */ + +#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */ +#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */ +#define RCC_BDCR_LSEEXT (1 << 7) /* Bit 7: LSE external clock type in bypass mode */ + +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 32 used as RTC clock */ + +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_VSWRST (1 << 16) /* Bit 16: VSwitch domain software reset */ +#define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */ +#define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */ +# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */ +# define RCC_BDCR_LSCOSEL_LSE RCC_BDCR_LSCOSEL /* LSE selected */ + +#define RCC_BDCR_LSION (1 << 26) /* Bit 26: LSI Oscillator Enable */ +#define RCC_BDCR_LSIRDY (1 << 27) /* Bit 27: LSI Oscillator Ready */ + +/* Reset status register */ + +#define RCC_RSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */ +#define RCC_RSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ +#define RCC_RSR_BORRSTF (1 << 27) /* Bit 27: BOR reset flag */ +#define RCC_RSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ +#define RCC_RSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ +#define RCC_RSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ + +/* Secure Configuration Register */ + +#define RCC_SECCFGR_HSISEC (1 << 0) /* HSI clock configuration and status bits security */ +#define RCC_SECCFGR_HSESEC (1 << 1) /* HSE clock configuration and status bits security */ +#define RCC_SECCFGR_CSISEC (1 << 2) /* CSI clock configuration and status bits security */ +#define RCC_SECCFGR_LSISEC (1 << 3) /* LSI clock configuration and status bits security */ +#define RCC_SECCFGR_LSESEC (1 << 4) /* LSE clock configuration and status bits security */ +#define RCC_SECCFGR_SYSCLKSEC (1 << 5) /* SYSCLK configuration and status bits security */ +#define RCC_SECCFGR_PRESCSEC (1 << 6) /* PRESC configuration and status bits security */ +#define RCC_SECCFGR_PLL1SEC (1 << 7) /* PLL1 configuration and status bits security */ +#define RCC_SECCFGR_PLL2SEC (1 << 8) /* PLL2 configuration and status bits security */ +#define RCC_SECCFGR_PLL3SEC (1 << 9) /* PLL3 configuration and status bits security */ +#define RCC_SECCFGR_HSI48SEC (1 << 11) /* HSI48 configuration and status bits security */ +#define RCC_SECCFGR_RMVRST (1 << 12) /* Remove Reset flag security */ +#define RCC_SECCFGR_CKPERSELSEC (1 << 13) /* PER_CK selection security */ + +/* Privilege Configuration Register */ + +#define RCC_PRIVCFGR_SPRIV (1 << 0) /* Secure functions privilege configuration */ +#define RCC_PRIVCFGR_NSPRIV (1 << 1) /* Non-secure functions privilege configuration */ + +#endif /* CONFIG_STM32_STM32H562XX */ +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32_tim.h b/arch/arm/src/stm32h5/hardware/stm32h5_tim.h similarity index 99% rename from arch/arm/src/stm32h5/hardware/stm32_tim.h rename to arch/arm/src/stm32h5/hardware/stm32h5_tim.h index 58b92a9174859..a0b617810d172 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32_tim.h + * arch/arm/src/stm32h5/hardware/stm32h5_tim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h deleted file mode 100644 index eafd85eb2e392..0000000000000 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h +++ /dev/null @@ -1,1246 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_RCC_H -#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#if defined(CONFIG_STM32_STM32H5XXXX) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32_RCC_HSICFGR_OFFSET 0x0010 /* HSI Calibration Register */ -#define STM32_RCC_CRRCR_OFFSET 0x0014 /* RCC clock recovery RC register */ -#define STM32_RCC_CFGR1_OFFSET 0x001c /* RCC clock configuration register 1 */ -#define STM32_RCC_CFGR2_OFFSET 0x0020 /* RCC clock configuration register 2 */ -#define STM32_RCC_PLL1CFGR_OFFSET 0x0028 /* RCC PLL1 configuration register */ -#define STM32_RCC_PLL2CFGR_OFFSET 0x002c /* RCC PLL2 configuration register */ -#define STM32_RCC_PLL3CFGR_OFFSET 0x0030 /* RCC PLL3 configuration register */ -#define STM32_RCC_PLL1DIVR_OFFSET 0x0034 /* RCC PLL1 dividers register */ -#define STM32_RCC_PLL1FRACR_OFFSET 0x0038 /* RCC PLL1 fractional divider register */ -#define STM32_RCC_PLL2DIVR_OFFSET 0x003c /* RCC PLL2 dividers register */ -#define STM32_RCC_PLL2FRACR_OFFSET 0x0040 /* RCC PLL2 fractional divider register */ -#define STM32_RCC_PLL3DIVR_OFFSET 0x0044 /* RCC PLL3 dividers register */ -#define STM32_RCC_PLL3FRACR_OFFSET 0x0048 /* RCC PLL3 fractional divider register */ -#define STM32_RCC_CIER_OFFSET 0x0050 /* RCC clock interrupt enable register */ -#define STM32_RCC_CIFR_OFFSET 0x0054 /* RCC clock interrupt flag register */ -#define STM32_RCC_CICR_OFFSET 0x0058 /* RCC clock interrupt clear register */ -#define STM32_RCC_AHB1RSTR_OFFSET 0x0060 /* RCC AHB1 peripheral reset register */ -#define STM32_RCC_AHB2RSTR_OFFSET 0x0064 /* RCC AHB2 peripheral reset register 1 */ -#define STM32_RCC_AHB4RSTR_OFFSET 0x006c /* RCC AHB4 peripheral reset register*/ -#define STM32_RCC_APB1LRSTR_OFFSET 0x0074 /* RCC APB1 peripheral reset register 1 */ -#define STM32_RCC_APB1HRSTR_OFFSET 0x0078 /* RCC APB1 peripheral reset register 2 */ -#define STM32_RCC_APB2RSTR_OFFSET 0x007c /* RCC APB2 peripheral reset register */ -#define STM32_RCC_APB3RSTR_OFFSET 0x0080 /* RCC APB3 peripheral reset register */ -#define STM32_RCC_AHB1ENR_OFFSET 0x0088 /* RCC AHB1 peripheral clock enable register */ -#define STM32_RCC_AHB2ENR_OFFSET 0x008c /* RCC AHB2 peripheral clock enable register */ -#define STM32_RCC_AHB4ENR_OFFSET 0x0094 /* RCC AHB4 peripheral clock enable register */ -#define STM32_RCC_APB1LENR_OFFSET 0x009c /* RCC APB1 peripheral clock enable register 1 */ -#define STM32_RCC_APB1HENR_OFFSET 0x00a0 /* RCC APB1 peripheral clock enable register 2 */ -#define STM32_RCC_APB2ENR_OFFSET 0x00a4 /* RCC APB2 peripheral clock enable register */ -#define STM32_RCC_APB3ENR_OFFSET 0x00a8 /* RCC APB3 peripheral clock enable register */ -#define STM32_RCC_AHB1LPENR_OFFSET 0x00b0 /* RCC AHB1 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_AHB2LPENR_OFFSET 0x00b4 /* RCC AHB2 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_AHB4LPENR_OFFSET 0x00bc /* RCC AHB3 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_APB1LPENR1_OFFSET 0x00c4 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 */ -#define STM32_RCC_APB1LPENR2_OFFSET 0x00c8 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 */ -#define STM32_RCC_APB2LPENR_OFFSET 0x00cc /* RCC APB2 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_APB3LPENR_OFFSET 0x00d0 /* RCC APB3 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_CCIPR1_OFFSET 0x00d8 /* RCC peripherals independent clock configuration register 1 */ -#define STM32_RCC_CCIPR2_OFFSET 0x00dc /* RCC peripherals independent clock configuration register 2 */ -#define STM32_RCC_CCIPR3_OFFSET 0x00e0 /* RCC peripherals independent clock configuration register 3 */ -#define STM32_RCC_CCIPR4_OFFSET 0x00e4 /* RCC peripherals independent clock configuration register 5 */ -#define STM32_RCC_CCIPR5_OFFSET 0x00e8 /* RCC peripherals independent clock configuration register 5 */ -#define STM32_RCC_BDCR_OFFSET 0x00f0 /* RCC Backup domain control register */ -#define STM32_RCC_RSR_OFFSET 0x00f4 /* RCC control/status register */ /* TODO: CSR in U5 */ -#define STM32_RCC_SECCFGR_OFFSET 0x0110 /* RCC secure configuration register */ -#define STM32_RCC_PRIVCFGR_OFFSET 0x0114 /* RCC privilege configuration register */ - -/* Register Addresses *******************************************************/ - -#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) -#define STM32_RCC_HSICFGR (STM32_RCC_BASE + STM32_RCC_HSICFGR_OFFSET) -#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) -#define STM32_RCC_CFGR1 (STM32_RCC_BASE + STM32_RCC_CFGR1_OFFSET) -#define STM32_RCC_CFGR2 (STM32_RCC_BASE + STM32_RCC_CFGR2_OFFSET) -#define STM32_RCC_PLL1CFGR (STM32_RCC_BASE + STM32_RCC_PLL1CFGR_OFFSET) -#define STM32_RCC_PLL2CFGR (STM32_RCC_BASE + STM32_RCC_PLL2CFGR_OFFSET) -#define STM32_RCC_PLL3CFGR (STM32_RCC_BASE + STM32_RCC_PLL3CFGR_OFFSET) -#define STM32_RCC_PLL1DIVR (STM32_RCC_BASE + STM32_RCC_PLL1DIVR_OFFSET) -#define STM32_RCC_PLL1FRACR (STM32_RCC_BASE + STM32_RCC_PLL1FRACR_OFFSET) -#define STM32_RCC_PLL2DIVR (STM32_RCC_BASE + STM32_RCC_PLL2DIVR_OFFSET) -#define STM32_RCC_PLL2FRACR (STM32_RCC_BASE + STM32_RCC_PLL2FRACR_OFFSET) -#define STM32_RCC_PLL3DIVR (STM32_RCC_BASE + STM32_RCC_PLL3DIVR_OFFSET) -#define STM32_RCC_PLL3FRACR (STM32_RCC_BASE + STM32_RCC_PLL3FRACR_OFFSET) -#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) -#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) -#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) -#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) -#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) -#define STM32_RCC_AHB4RSTR (STM32_RCC_BASE + STM32_RCC_AHB4RSTR_OFFSET) -#define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) -#define STM32_RCC_APB1HRSTR (STM32_RCC_BASE + STM32_RCC_APB1HRSTR_OFFSET) -#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) -#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) -#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) -#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) -#define STM32_RCC_AHB4ENR (STM32_RCC_BASE + STM32_RCC_AHB4ENR_OFFSET) -#define STM32_RCC_APB1LENR (STM32_RCC_BASE + STM32_RCC_APB1LENR_OFFSET) -#define STM32_RCC_APB1HENR (STM32_RCC_BASE + STM32_RCC_APB1HENR_OFFSET) -#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) -#define STM32_RCC_APB3ENR (STM32_RCC_BASE + STM32_RCC_APB3ENR_OFFSET) -#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE + STM32_RCC_AHB1LPENR_OFFSET) -#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE + STM32_RCC_AHB2LPENR_OFFSET) -#define STM32_RCC_AHB4LPENR (STM32_RCC_BASE + STM32_RCC_AHB4LPENR_OFFSET) -#define STM32_RCC_APB1LPENR (STM32_RCC_BASE + STM32_RCC_APB1LPENR1_OFFSET) -#define STM32_RCC_APB1HPENR (STM32_RCC_BASE + STM32_RCC_APB1LPENR2_OFFSET) -#define STM32_RCC_APB2LPENR (STM32_RCC_BASE + STM32_RCC_APB2LPENR_OFFSET) -#define STM32_RCC_APB3LPENR (STM32_RCC_BASE + STM32_RCC_APB3LPENR_OFFSET) -#define STM32_RCC_CCIPR1 (STM32_RCC_BASE + STM32_RCC_CCIPR1_OFFSET) -#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET) -#define STM32_RCC_CCIPR3 (STM32_RCC_BASE + STM32_RCC_CCIPR3_OFFSET) -#define STM32_RCC_CCIPR4 (STM32_RCC_BASE + STM32_RCC_CCIPR4_OFFSET) -#define STM32_RCC_CCIPR5 (STM32_RCC_BASE + STM32_RCC_CCIPR5_OFFSET) -#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) -#define STM32_RCC_RSR (STM32_RCC_BASE + STM32_RCC_RSR_OFFSET) -#define STM32_RCC_SECCFGR (STM32_RCC_BASE + STM32_RCC_SECCFGR_OFFSET) -#define STM32_RCC_PRIVCFGR (STM32_RCC_BASE + STM32_RCC_PRIVCFGR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Clock control register */ - -#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ -#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ -#define RCC_CR_HSIKERON (1 << 2) /* Bit 2: HSI clock enable in Stop mode */ -#define RCC_CR_HSIDIV_SHIFT (3) /* Bit [4:3] HSI Divider */ -#define RCC_CR_HSIDIV_MASK (0x3 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV(n) (((n) << RCC_CR_HSIDIV_SHIFT & RCC_CR_HSIDIV_MASK)) -#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI divider flag */ - -#define RCC_CR_CSION (1 << 8) /* Bit 8: CSI clock enable */ -#define RCC_CR_CSIRDY (1 << 9) /* Bit 9: CSI clock ready flag */ -#define RCC_CR_CSIKERON (1 << 10) /* Bit 10: CSI clock enable in Stop mode */ - -#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable */ -#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready flag */ - -#define RCC_CR_HSEON (1 << 16) /* Bit 16: HSE clock enable */ -#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */ -#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: HSE clock bypass */ -#define RCC_CR_HSECSSON (1 << 19) /* Bit 19: HSE clock security system enable */ -#define RCC_CR_HSEEXT (1 << 20) /* Bit 20: HSE external high speed clock - * type in bypass mode */ -#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: PLL1 enable */ -#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: PLL1 clock ready flag */ -#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: PLL2 enable */ -#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: PLL2 clock ready flag */ -#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: PLL3 enable */ -#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: PLL3 clock ready flag */ - -/* HSI Calibration register */ - -#define RCC_HSICFGR_HSITRIM_SHIFT (16) /* Bits 22-16: Internal High Speed clock trimming */ -#define RCC_HSICFGR_HSITRIM_MASK (0x7f << RCC_HSICFGR_HSITRIM_SHIFT) -#define RCC_HSICFGR_HSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ -#define RCC_HSICFGR_HSICAL_MASK (0xfff << RCC_HSICFGR_HSICAL_SHIFT) - -/* Clock Recovery RC register */ - -#define RCC_CRRCR_HSI48CAL_SHIFT (0) /* Bits 9-0: Internal RC 48MHz Clock Calibration */ -#define RCC_CRRCR_HSI48CAL_MASK (0x3ff << RCC_CRRCR_HSI48CAL_SHIFT) - -/* CSI Calibration register */ - -#define RCC_CSICFGR_CSITRIM_SHIFT (16) /* Bits 21-16: Internal High Speed clock trimming */ -#define RCC_CSICFGR_CSITRIM_MASK (0x3f << RCC_CSICFGR_CSITRIM_SHIFT) -#define RCC_CSICFGR_CSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ -#define RCC_CSICFGR_CSICAL_MASK (0xff << RCC_CSICFGR_CSICAL_SHIFT) - -/* Clock configuration register 1 */ - -#define RCC_CFGR1_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ -#define RCC_CFGR1_SW_MASK (3 << RCC_CFGR1_SW_SHIFT) -# define RCC_CFGR1_SW_MSI (0 << RCC_CFGR1_SW_SHIFT) /* 00: MSI selected as system clock */ -# define RCC_CFGR1_SW_HSI16 (1 << RCC_CFGR1_SW_SHIFT) /* 00: HSI16 selected as system clock */ -# define RCC_CFGR1_SW_HSE (2 << RCC_CFGR1_SW_SHIFT) /* 01: HSE selected as system clock */ -# define RCC_CFGR1_SW_PLL (3 << RCC_CFGR1_SW_SHIFT) /* 10: PLL selected as system clock */ - -#define RCC_CFGR1_SWS_SHIFT (3) /* Bits 3-4: System Clock Switch Status */ -#define RCC_CFGR1_SWS_MASK (3 << RCC_CFGR1_SWS_SHIFT) -# define RCC_CFGR1_SWS_MSI (0 << RCC_CFGR1_SWS_SHIFT) /* 00: MSI oscillator used as system clock */ -# define RCC_CFGR1_SWS_HSI16 (1 << RCC_CFGR1_SWS_SHIFT) /* 00: HSI16 oscillator used as system clock */ -# define RCC_CFGR1_SWS_HSE (2 << RCC_CFGR1_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ -# define RCC_CFGR1_SWS_PLL (3 << RCC_CFGR1_SWS_SHIFT) /* 10: PLL used as system clock */ - -#define RCC_CFGR1_STOPWUCK (1 << 6) /* System clock selection after a wakeup from system stop */ -#define RCC_CFGR1_STOPKERWUCK (1 << 7) /* Kernel clock selection after a wakeup from system stop */ - -#define RCC_CFGR1_RTCPRE_SHIFT (8) /* Bits 13-8: RTC prescaler */ -#define RCC_CFGR1_RTCPRE_MASK (0x3f << RCC_CFGR1_RTCPRE_SHIFT) -# define RCC_CFGR1_RTCPRE_HSE (0 << RCC_CFGR1_RTCPRE_SHIFT) /* 0xxx: HSE not divided */ -# define RCC_CFGR1_RTCPRE_HSEd2 (2 << RCC_CFGR1_RTCPRE_SHIFT) /* 10: HSE divided by 2 */ -# define RCC_CFGR1_RTCPRE_HSEd4 (4 << RCC_CFGR1_RTCPRE_SHIFT) /* 100: HSE divided by 4 */ -# define RCC_CFGR1_RTCPRE_HSEd8 (8 << RCC_CFGR1_RTCPRE_SHIFT) /* 1000: HSE divided by 8 */ -# define RCC_CFGR1_RTCPRE_HSEd16 (16 << RCC_CFGR1_RTCPRE_SHIFT) /* 10000: HSE divided by 16 */ -# define RCC_CFGR1_RTCPRE_HSEd32 (32 << RCC_CFGR1_RTCPRE_SHIFT) /* 100000: HSE divided by 32 */ -# define RCC_CFGR1_RTCPRE_HSEd63 (63 << RCC_CFGR1_RTCPRE_SHIFT) /* 111111: HSE divided by 63 */ - -#define RCC_CFGR1_TIMPRE (1 << 15) /* timers clocks prescaler selection */ - -#define RCC_CFGR1_MCO1PRE_SHIFT (18) /* Bits 21-18: MCO1 Prescaler */ -#define RCC_CFGR1_MCO1PRE_MASK (0xf << RCC_CFGR1_MCO1PRE_SHIFT) -# define RCC_CFGR1_MCO1PRE_MCO1 (0 << RCC_CFGR1_MCO1PRE_SHIFT) /* 0xx: MCO1 not divided */ -# define RCC_CFGR1_MCO1PRE_MCO1d2 (2 << RCC_CFGR1_MCO1PRE_SHIFT) /* 10: MCO1 divided by 2 */ -# define RCC_CFGR1_MCO1PRE_MCO1d4 (4 << RCC_CFGR1_MCO1PRE_SHIFT) /* 100: MCO1 divided by 4 */ -# define RCC_CFGR1_MCO1PRE_MCO1d8 (8 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1000: MCO1 divided by 8 */ -# define RCC_CFGR1_MCO1PRE_MCO1d15 (15 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1111: MCO1 divided by 15 */ - -#define RCC_CFGR1_MCO1SEL_SHIFT (22) /* Bits 24-22: Microcontroller Clock Output1 */ -#define RCC_CFGR1_MCO1SEL_MASK (0x7 << RCC_CFGR1_MCO1SEL_SHIFT) -# define RCC_CFGR1_MCO1SEL_HSI (0 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0000: HSI clock selected */ -# define RCC_CFGR1_MCO1SEL_LSE (1 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0001: LSE clock selected */ -# define RCC_CFGR1_MCO1SEL_HSE (2 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0010: HSE clock selected */ -# define RCC_CFGR1_MCO1SEL_PLL1 (3 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0011: Main PLL1 selected */ -# define RCC_CFGR1_MCO1SEL_HSI48 (4 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0100: HSI48 clock selected */ - -#define RCC_CFGR1_MCO2PRE_SHIFT (25) /* Bits 28-25: MCO2 Prescaler */ -#define RCC_CFGR1_MCO2PRE_MASK (0xf << RCC_CFGR1_MCO2PRE_SHIFT) -# define RCC_CFGR1_MCO2PRE_MCO2 (0 << RCC_CFGR1_MCO2PRE_SHIFT) /* 0xx: MCO2 not divided */ -# define RCC_CFGR1_MCO2PRE_MCO2d2 (2 << RCC_CFGR1_MCO2PRE_SHIFT) /* 10: MCO2 divided by 2 */ -# define RCC_CFGR1_MCO2PRE_MCO2d4 (4 << RCC_CFGR1_MCO2PRE_SHIFT) /* 100: MCO2 divided by 4 */ -# define RCC_CFGR1_MCO2PRE_MCO2d8 (8 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1000: MCO2 divided by 8 */ -# define RCC_CFGR1_MCO2PRE_MCO2d15 (15 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1111: MCO2 divided by 15 */ - -#define RCC_CFGR1_MCO2SEL_SHIFT (29) /* Bits 31-29: Microcontroller Clock Output1 */ -#define RCC_CFGR1_MCO2SEL_MASK (0x7 << RCC_CFGR1_MCO2SEL_SHIFT) -# define RCC_CFGR1_MCO2SEL_SYSCLLK (0 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0000: Main SYSCLLK selected */ -# define RCC_CFGR1_MCO2SEL_PLL2 (1 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0001: Main PLL2 selected */ -# define RCC_CFGR1_MCO2SEL_HSE (2 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0010: HSE clock selected */ -# define RCC_CFGR1_MCO2SEL_PLL1 (3 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0011: Main PLL1 selected */ -# define RCC_CFGR1_MCO2SEL_CSI (4 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0100: CSI clock selected */ -# define RCC_CFGR1_MCO2SEL_LSI (5 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0101: LSI clock selected */ - -/* Clock configuration register 2 */ - -#define RCC_CFGR2_HPRE_SHIFT (0) /* Bits 3-0: HPRE Prescaler */ -#define RCC_CFGR2_HPRE_MASK (0xf << RCC_CFGR2_HPRE_SHIFT) -# define RCC_CFGR2_HPRE_SYSCLK (0 << RCC_CFGR2_HPRE_SHIFT) /* 0xx: SYSCLK not divided */ -# define RCC_CFGR2_HPRE_SYSCLKd2 (8 << RCC_CFGR2_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR2_HPRE_SYSCLKd4 (9 << RCC_CFGR2_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ -# define RCC_CFGR2_HPRE_SYSCLKd8 (10 << RCC_CFGR2_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ -# define RCC_CFGR2_HPRE_SYSCLKd16 (11 << RCC_CFGR2_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ -# define RCC_CFGR2_HPRE_SYSCLKd64 (12 << RCC_CFGR2_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ -# define RCC_CFGR2_HPRE_SYSCLKd128 (13 << RCC_CFGR2_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ -# define RCC_CFGR2_HPRE_SYSCLKd256 (14 << RCC_CFGR2_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ -# define RCC_CFGR2_HPRE_SYSCLKd512 (15 << RCC_CFGR2_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ - -#define RCC_CFGR2_PPRE1_SHIFT (4) /* Bits 6-4: PPRE1 Prescaler */ -#define RCC_CFGR2_PPRE1_MASK (0x7 << RCC_CFGR2_PPRE1_SHIFT) -# define RCC_CFGR2_PPRE1_HCLK1 (0 << RCC_CFGR2_PPRE1_SHIFT) /* 0xx: HCLK1 not divided */ -# define RCC_CFGR2_PPRE1_HCLK1d2 (4 << RCC_CFGR2_PPRE1_SHIFT) /* 100: HCLK1 divided by 2 */ -# define RCC_CFGR2_PPRE1_HCLK1d4 (5 << RCC_CFGR2_PPRE1_SHIFT) /* 101: HCLK1 divided by 4 */ -# define RCC_CFGR2_PPRE1_HCLK1d8 (6 << RCC_CFGR2_PPRE1_SHIFT) /* 110: HCLK1 divided by 8 */ -# define RCC_CFGR2_PPRE1_HCLK1d16 (7 << RCC_CFGR2_PPRE1_SHIFT) /* 111: HCLK1 divided by 16 */ - -#define RCC_CFGR2_PPRE2_SHIFT (8) /* Bits 10-8: PPRE2 Prescaler */ -#define RCC_CFGR2_PPRE2_MASK (0x7 << RCC_CFGR2_PPRE2_SHIFT) -# define RCC_CFGR2_PPRE2_HCLK1 (0 << RCC_CFGR2_PPRE2_SHIFT) /* 0xx: HCLK1 not divided */ -# define RCC_CFGR2_PPRE2_HCLK1d2 (4 << RCC_CFGR2_PPRE2_SHIFT) /* 1000: HCLK1 divided by 2 */ -# define RCC_CFGR2_PPRE2_HCLK1d4 (5 << RCC_CFGR2_PPRE2_SHIFT) /* 1001: HCLK1 divided by 4 */ -# define RCC_CFGR2_PPRE2_HCLK1d8 (6 << RCC_CFGR2_PPRE2_SHIFT) /* 1010: HCLK1 divided by 8 */ -# define RCC_CFGR2_PPRE2_HCLK1d16 (7 << RCC_CFGR2_PPRE2_SHIFT) /* 1011: HCLK1 divided by 16 */ - -#define RCC_CFGR2_PPRE3_SHIFT (12) /* Bits 14-12: PPRE3 Prescaler */ -#define RCC_CFGR2_PPRE3_MASK (0x7 << RCC_CFGR2_PPRE3_SHIFT) -# define RCC_CFGR2_PPRE3_HCLK1 (0 << RCC_CFGR2_PPRE3_SHIFT) /* 0xx: HCLK1 not divided */ -# define RCC_CFGR2_PPRE3_HCLK1d2 (4 << RCC_CFGR2_PPRE3_SHIFT) /* 100: HCLK1 divided by 2 */ -# define RCC_CFGR2_PPRE3_HCLK1d4 (5 << RCC_CFGR2_PPRE3_SHIFT) /* 101: HCLK1 divided by 4 */ -# define RCC_CFGR2_PPRE3_HCLK1d8 (6 << RCC_CFGR2_PPRE3_SHIFT) /* 110: HCLK1 divided by 8 */ -# define RCC_CFGR2_PPRE3_HCLK1d16 (7 << RCC_CFGR2_PPRE3_SHIFT) /* 111: HCLK1 divided by 16 */ - -#define RCC_CFGR2_AHB1DIS (1 << 16) /* AHB1 clock disable */ -#define RCC_CFGR2_AHB2DIS (1 << 17) /* AHB2 clock disable */ -#define RCC_CFGR2_AHB4DIS (1 << 19) /* AHB4 clock disable */ -#define RCC_CFGR2_APB1DIS (1 << 20) /* APB1 clock disable */ -#define RCC_CFGR2_APB2DIS (1 << 21) /* APB2 clock disable */ -#define RCC_CFGR2_APB3DIS (1 << 22) /* APB3 clock disable */ - -/* PLL1 configuration register */ - -#define RCC_PLL1CFGR_PLL1SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) - * entry clock source */ -#define RCC_PLL1CFGR_PLL1SRC_MASK (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) -# define RCC_PLL1CFGR_PLL1SRC_NONE (0 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 000: No clock sent to PLLs */ -# define RCC_PLL1CFGR_PLL1SRC_HSI (1 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 001: HSI selected as PLL source */ -# define RCC_PLL1CFGR_PLL1SRC_CSI (2 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 010: CSI selected as PLL source */ -# define RCC_PLL1CFGR_PLL1SRC_HSE (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 011: HSE selected as PLL source */ - -#define RCC_PLL1CFGR_PLL1RGE_SHIFT (2) /* Bit 3-2: */ -#define RCC_PLL1CFGR_PLL1RGE_MASK (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) -# define RCC_PLL1CFGR_PLL1RGE_1_2M (0 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ -# define RCC_PLL1CFGR_PLL1RGE_2_4M (1 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ -# define RCC_PLL1CFGR_PLL1RGE_4_8M (2 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ -# define RCC_PLL1CFGR_PLL1RGE_8_16M (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ - -#define RCC_PLL1CFGR_PLL1FRACEN (1 << 4) /* PLL1 Fractional Latch Enable */ -#define RCC_PLL1CFGR_PLL1VCOSEL (1 << 5) /* PLL1 VCO Selection */ - -#define RCC_PLL1CFGR_PLL1M_SHIFT (8) /* Bit 13-8: */ -#define RCC_PLL1CFGR_PLL1M_MASK (0x3f << RCC_PLL1CFGR_PLL1M_SHIFT) -# define RCC_PLL1CFGR_PLL1M(n) ((n) << RCC_PLL1CFGR_PLL1M_SHIFT) /* m = 1..63 */ - -#define RCC_PLL1CFGR_PLL1PEN (1 << 16) /* PLL1 DIVP divder output enable */ -#define RCC_PLL1CFGR_PLL1QEN (1 << 17) /* PLL1 DIVQ divder output enable */ -#define RCC_PLL1CFGR_PLL1REN (1 << 18) /* PLL1 DIVR divder output enable */ - -/* PLL2 configuration register */ - -#define RCC_PLL2CFGR_PLL2SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) - * entry clock source */ -#define RCC_PLL2CFGR_PLL2SRC_MASK (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) -# define RCC_PLL2CFGR_PLL2SRC_NONE (0 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 000: No clock sent to PLLs */ -# define RCC_PLL2CFGR_PLL2SRC_HSI (1 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 001: HSI selected as PLL source */ -# define RCC_PLL2CFGR_PLL2SRC_CSI (2 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 010: CSI selected as PLL source */ -# define RCC_PLL2CFGR_PLL2SRC_HSE (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 011: HSE selected as PLL source */ - -#define RCC_PLL2CFGR_PLL2RGE_SHIFT (2) /* Bit 3-2: */ -#define RCC_PLL2CFGR_PLL2RGE_MASK (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) -# define RCC_PLL2CFGR_PLL2RGE_1_2M (0 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ -# define RCC_PLL2CFGR_PLL2RGE_2_4M (1 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ -# define RCC_PLL2CFGR_PLL2RGE_4_8M (2 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz */ -# define RCC_PLL2CFGR_PLL2RGE_8_16M (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz */ - -#define RCC_PLL2CFGR_PLL2FRACEN (1 << 4) /* PLL2 Fractional Latch Enable */ -#define RCC_PLL2CFGR_PLL2VCOSEL (1 << 5) /* PLL2 VCO Selection */ - -#define RCC_PLL2CFGR_PLL2M_SHIFT (8) /* Bit 13-8: */ -#define RCC_PLL2CFGR_PLL2M_MASK (0x3f << RCC_PLL2CFGR_PLL2M_SHIFT) -# define RCC_PLL2CFGR_PLL2M(n) ((n) << RCC_PLL2CFGR_PLL2M_SHIFT) /* m = 1..63 */ - -#define RCC_PLL2CFGR_PLL2PEN (1 << 16) /* PLL2 DIVP divder output enable */ -#define RCC_PLL2CFGR_PLL2QEN (1 << 17) /* PLL2 DIVQ divder output enable */ -#define RCC_PLL2CFGR_PLL2REN (1 << 18) /* PLL2 DIVR divder output enable */ - -/* PLL3 configuration register */ - -#define RCC_PLL3CFGR_PLL3SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) - * entry clock source */ -#define RCC_PLL3CFGR_PLL3SRC_MASK (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) -# define RCC_PLL3CFGR_PLL3SRC_NONE (0 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 000: No clock sent to PLLs */ -# define RCC_PLL3CFGR_PLL3SRC_HSI (1 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 001: HSI selected as PLL source */ -# define RCC_PLL3CFGR_PLL3SRC_CSI (2 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 010: CSI selected as PLL source */ -# define RCC_PLL3CFGR_PLL3SRC_HSE (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 011: HSE selected as PLL source */ - -#define RCC_PLL3CFGR_PLL3RGE_SHIFT (2) /* Bit 3-2: */ -#define RCC_PLL3CFGR_PLL3RGE_MASK (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) -# define RCC_PLL3CFGR_PLL3RGE_1_2M (0 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ -# define RCC_PLL3CFGR_PLL3RGE_2_4M (1 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ -# define RCC_PLL3CFGR_PLL3RGE_4_8M (2 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ -# define RCC_PLL3CFGR_PLL3RGE_8_16M (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ - -#define RCC_PLL3CFGR_PLL3FRACEN (1 << 4) /* PLL3 Fractional Latch Enable */ -#define RCC_PLL3CFGR_PLL3VCOSEL (1 << 5) /* PLL3 VCO Selection */ - -#define RCC_PLL3CFGR_PLL3M_SHIFT (8) /* Bit 13-8: */ -#define RCC_PLL3CFGR_PLL3M_MASK (0x3f << RCC_PLL3CFGR_PLL3M_SHIFT) -# define RCC_PLL3CFGR_PLL3M(n) ((n) << RCC_PLL3CFGR_PLL3M_SHIFT) /* m = 1..63 */ - -#define RCC_PLL3CFGR_PLL3PEN (1 << 16) /* PLL3 DIVP divder output enable */ -#define RCC_PLL3CFGR_PLL3QEN (1 << 17) /* PLL3 DIVQ divder output enable */ -#define RCC_PLL3CFGR_PLL3REN (1 << 18) /* PLL3 DIVR divder output enable */ - -/* PLL1 dividers register */ - -#define RCC_PLL1DIVR_PLL1N_SHIFT (0) /* Bits 8-0: */ -#define RCC_PLL1DIVR_PLL1N_MASK (0x1ff << RCC_PLL1DIVR_PLL1N_SHIFT) -# define RCC_PLL1DIVR_PLL1N(n) ((n-1) << RCC_PLL1DIVR_PLL1N_SHIFT) /* m = 4..512 */ - -#define RCC_PLL1DIVR_PLL1P_SHIFT (9) /* Bits 15-9: */ -#define RCC_PLL1DIVR_PLL1P_MASK (0x7f << RCC_PLL1DIVR_PLL1P_SHIFT) -# define RCC_PLL1DIVR_PLL1P(n) ((n-1) << RCC_PLL1DIVR_PLL1P_SHIFT) /* m = 2..128 evens */ - -#define RCC_PLL1DIVR_PLL1Q_SHIFT (16) /* Bits 22-16: */ -#define RCC_PLL1DIVR_PLL1Q_MASK (0x7f << RCC_PLL1DIVR_PLL1Q_SHIFT) -# define RCC_PLL1DIVR_PLL1Q(n) ((n-1) << RCC_PLL1DIVR_PLL1Q_SHIFT) /* m = 1..128 */ - -#define RCC_PLL1DIVR_PLL1R_SHIFT (24) /* Bits 30-24: */ -#define RCC_PLL1DIVR_PLL1R_MASK (0x7f << RCC_PLL1DIVR_PLL1R_SHIFT) -# define RCC_PLL1DIVR_PLL1R(n) ((n-1) << RCC_PLL1DIVR_PLL1R_SHIFT) /* m = 1..128 */ - -/* PLL1 fractional divider register */ - -#define RCC_PLL1FRACR_PLL1FRACN_SHIFT (3) -#define RCC_PLL1FRACR_PLL1FRACN_MASK (0x1fff << RCC_PLL1FRACR_PLL1FRACN_SHIFT) -#define RCC_PLL1FRACR_PLL1FRACN(n) (n << RCC_PLL1FRACR_PLL1FRACN_SHIFT) /* m = 0..8192 */ - -/* PLL2 dividers register */ - -#define RCC_PLL2DIVR_PLL2N_SHIFT (0) /* Bits 8-0: */ -#define RCC_PLL2DIVR_PLL2N_MASK (0x1ff << RCC_PLL2DIVR_PLL2N_SHIFT) -# define RCC_PLL2DIVR_PLL2N(n) ((n-1) << RCC_PLL2DIVR_PLL2N_SHIFT) /* m = 4..512 */ - -#define RCC_PLL2DIVR_PLL2P_SHIFT (9) /* Bits 15-9: */ -#define RCC_PLL2DIVR_PLL2P_MASK (0x7f << RCC_PLL2DIVR_PLL2P_SHIFT) -# define RCC_PLL2DIVR_PLL2P(n) ((n-1) << RCC_PLL2DIVR_PLL2P_SHIFT) /* m = 2..128 evens */ - -#define RCC_PLL2DIVR_PLL2Q_SHIFT (16) /* Bits 22-16: */ -#define RCC_PLL2DIVR_PLL2Q_MASK (0x7f << RCC_PLL2DIVR_PLL2Q_SHIFT) -# define RCC_PLL2DIVR_PLL2Q(n) ((n-1) << RCC_PLL2DIVR_PLL2Q_SHIFT) /* m = 1..128 */ - -#define RCC_PLL2DIVR_PLL2R_SHIFT (24) /* Bits 30-24: */ -#define RCC_PLL2DIVR_PLL2R_MASK (0x7f << RCC_PLL2DIVR_PLL2R_SHIFT) -# define RCC_PLL2DIVR_PLL2R(n) ((n-1) << RCC_PLL2DIVR_PLL2R_SHIFT) /* m = 1..128 */ - -/* PLL2 fractional divider register */ - -#define RCC_PLL2FRACR_PLL2FRACN_SHIFT (3) -#define RCC_PLL2FRACR_PLL2FRACN_MASK (0x1fff << RCC_PLL2FRACR_PLL2FRACN_SHIFT) -#define RCC_PLL2FRACR_PLL2FRACN(n) (n << RCC_PLL2FRACR_PLL2FRACN_SHIFT) /* m = 0..8192 */ - -/* PLL3 dividers register */ - -#define RCC_PLL3DIVR_PLL3N_SHIFT (0) /* Bits 8-0: */ -#define RCC_PLL3DIVR_PLL3N_MASK (0x1ff << RCC_PLL3DIVR_PLL3N_SHIFT) -# define RCC_PLL3DIVR_PLL3N(n) ((n-1) << RCC_PLL3DIVR_PLL3N_SHIFT) /* m = 4..512 */ - -#define RCC_PLL3DIVR_PLL3P_SHIFT (9) /* Bits 15-9: */ -#define RCC_PLL3DIVR_PLL3P_MASK (0x7f << RCC_PLL3DIVR_PLL3P_SHIFT) -# define RCC_PLL3DIVR_PLL3P(n) ((n-1) << RCC_PLL3DIVR_PLL3P_SHIFT) /* m = 2..128 evens */ - -#define RCC_PLL3DIVR_PLL3Q_SHIFT (16) /* Bits 22-16: */ -#define RCC_PLL3DIVR_PLL3Q_MASK (0x7f << RCC_PLL3DIVR_PLL3Q_SHIFT) -# define RCC_PLL3DIVR_PLL3Q(n) ((n-1) << RCC_PLL3DIVR_PLL3Q_SHIFT) /* m = 1..128 */ - -#define RCC_PLL3DIVR_PLL3R_SHIFT (24) /* Bits 30-24: */ -#define RCC_PLL3DIVR_PLL3R_MASK (0x7f << RCC_PLL3DIVR_PLL3R_SHIFT) -# define RCC_PLL3DIVR_PLL3R(n) ((n-1) << RCC_PLL3DIVR_PLL3R_SHIFT) /* m = 1..128 */ - -/* PLL3 fractional divider register */ - -#define RCC_PLL3FRACR_PLL3FRACN_SHIFT (3) -#define RCC_PLL3FRACR_PLL3FRACN_MASK (0x1fff << RCC_PLL3FRACR_PLL3FRACN_SHIFT) -#define RCC_PLL3FRACR_PLL3FRACN(n) (n << RCC_PLL3FRACR_PLL3FRACN_SHIFT) /* m = 0..8192 */ - -/* Clock interrupt enable register */ - -#define RCC_CIER_LSIRDYIE (1 << 0) /* Bit 0: LSI Ready Interrupt Enable */ -#define RCC_CIER_LSERDYIE (1 << 1) /* Bit 1: LSE Ready Interrupt Enable */ -#define RCC_CIER_CSIRDYIE (1 << 2) /* Bit 2: CSI Ready Interrupt Enable */ -#define RCC_CIER_HSIRDYIE (1 << 3) /* Bit 3: HSI Ready Interrupt Enable */ -#define RCC_CIER_HSERDYIE (1 << 4) /* Bit 4: HSE Ready Interrupt Enable */ -#define RCC_CIER_HSI48RDYIE (1 << 5) /* Bit 5: HSI48 Ready Interrupt Enable */ -#define RCC_CIER_PLL1RDYIE (1 << 6) /* Bit 6: PLL1 Ready Interrupt Enable */ -#define RCC_CIER_PLL2RDYIE (1 << 7) /* Bit 7: PLL2 Ready Interrupt Enable */ -#define RCC_CIER_PLL3RDYIE (1 << 8) /* Bit 8: PLL3 Ready Interrupt Enable */ - -/* Clock interrupt flag register */ - -#define RCC_CIFR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ -#define RCC_CIFR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ -#define RCC_CIFR_CSIRDYF (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ -#define RCC_CIFR_HSIRDYF (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ -#define RCC_CIFR_HSERDYF (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ -#define RCC_CIFR_HSI48RDYF (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ -#define RCC_CIFR_PLL1RDYF (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ -#define RCC_CIFR_PLL2RDYF (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ -#define RCC_CIFR_PLL3RDYF (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ -#define RCC_CIFR_HSECSSF (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ - -/* Clock interrupt clear register */ - -#define RCC_CICR_LSIRDYC (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ -#define RCC_CICR_LSERDYC (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ -#define RCC_CICR_CSIRDYC (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ -#define RCC_CICR_HSIRDYC (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ -#define RCC_CICR_HSERDYC (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ -#define RCC_CICR_HSI48RDYC (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ -#define RCC_CICR_PLL1RDYC (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ -#define RCC_CICR_PLL2RDYC (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ -#define RCC_CICR_PLL3RDYC (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ -#define RCC_CICR_HSECSSC (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ - -/* AHB1 peripheral reset register */ - -#define RCC_AHB1RSTR_GPDMA1RST (1 << 0) /* Bit 0: GPDMA1 reset */ -#define RCC_AHB1RSTR_GPDMA2RST (1 << 1) /* Bit 1: GPDMA2 reset */ -#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12: CRC reset */ -#define RCC_AHB1RSTR_CORDICRST (1 << 14) /* Bit 14: CORDIC reset */ -#define RCC_AHB1RSTR_FMACRST (1 << 15) /* Bit 15: FMAC reset */ -#define RCC_AHB1RSTR_RAMCFGRST (1 << 17) /* Bit 17: RAMCFG reset */ -#define RCC_AHB1RSTR_ETHRST (1 << 19) /* Bit 19: ETH reset */ - -/* AHB2 peripheral reset register */ - -#define RCC_AHB2RSTR_GPIORST(n) (1 << (n)) -#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */ -#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */ -#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */ -#define RCC_AHB2RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */ -#define RCC_AHB2RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */ -#define RCC_AHB2RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */ -#define RCC_AHB2RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ -#define RCC_AHB2RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ -#define RCC_AHB2RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */ -#define RCC_AHB2RSTR_ADCRST (1 << 10) /* Bit 10: ADC interface reset (common to all ADCs) */ -#define RCC_AHB2RSTR_DACRST (1 << 11) /* Bit 11: DAC Block reset */ -#define RCC_AHB2RSTR_DCMI_PSSIRST (1 << 12) /* Bit 12: Digital Camera Interface block reset */ -#define RCC_AHB2RSTR_AESRST (1 << 16) /* Bit 16: AES Cryptographic module reset */ -#define RCC_AHB2RSTR_HASHRST (1 << 17) /* Bit 17: HASH block reset */ -#define RCC_AHB2RSTR_RNGRST (1 << 18) /* Bit 18: Random number generator module reset */ -#define RCC_AHB2RSTR_PKARST (1 << 19) /* Bit 19: Public Key Accelerator module reset */ -#define RCC_AHB2RSTR_SAESRST (1 << 20) /* Bit 20: SAES block reset */ - -/* AHB4 peripheral reset register */ - -#define RCC_AHB4RSTR_OTFDEC1RST (1 << 7) /* Bit 0: OTFDEC1 block reset */ -#define RCC_AHB4RSTR_SDMMC1RST (1 << 11) /* Bit 11: SDMMC1RST blocks reset */ -#define RCC_AHB4RSTR_SDMMC2RST (1 << 12) /* Bit 12: SDMMC2RST blocks reset */ -#define RCC_AHB4RSTR_FMCRST (1 << 16) /* Bit 16: FMC block reset */ -#define RCC_AHB4RSTR_OSPI1RST (1 << 20) /* Bit 20: OCTOSPI1 block reset */ - -/* APB1 Peripheral reset register 1 */ - -#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */ -#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */ -#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */ -#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */ -#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */ -#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */ -#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* Bit 5: TIM12 reset */ -#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* Bit 5: TIM13 reset */ -#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* Bit 5: TIM14 reset */ -#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* Bit 14: SPI2 reset */ -#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* Bit 15: SPI3 reset */ -#define RCC_APB1LRSTR_USART2RST (1 << 17) /* Bit 17: USART2 reset */ -#define RCC_APB1LRSTR_USART3RST (1 << 18) /* Bit 18: USART3 reset */ -#define RCC_APB1LRSTR_UART4RST (1 << 19) /* Bit 19: UART4 reset */ -#define RCC_APB1LRSTR_UART5RST (1 << 20) /* Bit 20: UART5 reset */ -#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* Bit 21: I2C1 reset */ -#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* Bit 22: I2C2 reset */ -#define RCC_APB1LRSTR_I3C1RST (1 << 23) /* Bit 23: I3C1 reset */ -#define RCC_APB1LRSTR_CRSRST (1 << 24) /* Bit 24: CRS reset */ -#define RCC_APB1LRSTR_USART6RST (1 << 25) /* Bit 25: USART6 reset */ -#define RCC_APB1LRSTR_USART10RST (1 << 26) /* Bit 26: USART10 reset */ -#define RCC_APB1LRSTR_USART11RST (1 << 27) /* Bit 27: USART11 reset */ -#define RCC_APB1LRSTR_CECRST (1 << 28) /* Bit 28: CEC reset */ -#define RCC_APB1LRSTR_UART7RST (1 << 30) /* Bit 30: UART7 reset */ -#define RCC_APB1LRSTR_UART8RST (1 << 31) /* Bit 31: UART8 reset */ - -/* APB1 Peripheral reset register 2 */ - -#define RCC_APB1HRSTR_UART9RST (1 << 0) /* Bit 0: UART9 reset */ -#define RCC_APB1HRSTR_UART12RST (1 << 1) /* Bit 1: UART12 reset */ -#define RCC_APB1HRSTR_DTSRST (1 << 3) /* Bit 3: DTS reset */ -#define RCC_APB1HRSTR_LPTIM2RST (1 << 5) /* Bit 5: Low-power Timer 2 reset */ -#define RCC_APB1HRSTR_FDCANRST (1 << 9) /* Bit 9: FDCAN reset */ -#define RCC_APB1HRSTR_UCPD1RST (1 << 23) /* Bit 23: UCPD1 reset */ - -/* APB2 Peripheral reset register */ - -#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 reset */ -#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ -#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 reset */ -#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ -#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ -#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */ -#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */ -#define RCC_APB2RSTR_SPI4RST (1 << 19) /* Bit 19: SPI4 reset */ -#define RCC_APB2RSTR_SPI67RST (1 << 20) /* Bit 20: SPI6 reset */ -#define RCC_APB2RSTR_SAI1RST (1 << 21) /* Bit 21: SAI1 reset */ -#define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 22: SAI2 reset */ -#define RCC_APB2RSTR_USBRST (1 << 24) /* Bit 24: USB reset */ - -/* APB3 Peripheral reset register */ - -#define RCC_APB3RSTR_SPI5RST (1 << 5) /* Bit 5: SPI5 reset */ -#define RCC_APB3RSTR_LPUART1RST (1 << 6) /* Bit 6: LPUART1 reset */ -#define RCC_APB3RSTR_I2C3RST (1 << 7) /* Bit 7: I2C3 reset */ -#define RCC_APB3RSTR_I2C4RST (1 << 8) /* Bit 8: I2C4 reset */ -#define RCC_APB3RSTR_I3C2RST (1 << 9) /* Bit 9: I3C2 reset */ -#define RCC_APB3RSTR_LPTIM1RST (1 << 11) /* Bit 11: LPTIM1 reset */ -#define RCC_APB3RSTR_LPTIM3RST (1 << 12) /* Bit 12: LPTIM3 reset */ -#define RCC_APB3RSTR_LPTIM4RST (1 << 13) /* Bit 13: LPTIM4 reset */ -#define RCC_APB3RSTR_LPTIM5RST (1 << 14) /* Bit 14: LPTIM5 reset */ -#define RCC_APB3RSTR_LPTIM6RST (1 << 15) /* Bit 15: LPTIM6 reset */ -#define RCC_APB3RSTR_VREFRST (1 << 20) /* Bit 20: VREF reset */ - -/* AHB1 Peripheral Clock enable register */ - -#define RCC_AHB1ENR_GPDMA1EN (1 << 0) /* Bit 0: GPDMA1 clock enable */ -#define RCC_AHB1ENR_GPDMA2EN (1 << 1) /* Bit 1: GPDMA2 clock enable */ -#define RCC_AHB1ENR_FLASHEN (1 << 8) /* Bit 8: Flash Interface clock enable */ -#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ -#define RCC_AHB1ENR_CORDICEN (1 << 14) /* Bit 14: CORDIC clock enable */ -#define RCC_AHB1ENR_FMACEN (1 << 15) /* Bit 15: FMAC clock enable */ -#define RCC_AHB1ENR_RAMCFGEN (1 << 17) /* Bit 17: RAMCFG clock enable */ -#define RCC_AHB1ENR_ETHEN (1 << 19) /* Bit 19: ETH clock enable */ -#define RCC_AHB1ENR_ETHTXEN (1 << 20) /* Bit 20: ETH TX clock enable */ -#define RCC_AHB1ENR_ETHRXEN (1 << 21) /* Bit 21: ETH RX clock enable */ -#define RCC_AHB1ENR_TZSC1EN (1 << 24) /* Bit 24: TZSC1 clock enable */ -#define RCC_AHB1ENR_BKPRAMEN (1 << 28) /* Bit 28: BKPRAM clock enable */ -#define RCC_AHB1ENR_DCACHEEN (1 << 30) /* Bit 25: DCACHE clock enable */ -#define RCC_AHB1ENR_SRAM1EN (1 << 31) /* Bit 25: SRAM1 clock enable */ - -/* AHB2 Peripheral Clock enable register */ - -#define RCC_AHB2ENR_GPIOEN(n) (1 << (n)) -#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */ -#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */ -#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */ -#define RCC_AHB2ENR_GPIODEN (1 << 3) /* Bit 3: IO port D enable */ -#define RCC_AHB2ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E enable */ -#define RCC_AHB2ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F enable */ -#define RCC_AHB2ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G enable */ -#define RCC_AHB2ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H enable */ -#define RCC_AHB2ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I enable */ -#define RCC_AHB2ENR_ADCEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ -#define RCC_AHB2ENR_DAC1EN (1 << 11) /* Bit 11: DAC clock enable */ -#define RCC_AHB2ENR_DCMI_PSSIEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ -#define RCC_AHB2ENR_AESEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ -#define RCC_AHB2ENR_HASHEN (1 << 17) /* Bit 17: HASH module enable */ -#define RCC_AHB2ENR_RNGEN (1 << 18) /* Bit 18: Random number generator module enable */ -#define RCC_AHB2ENR_PKAEN (1 << 19) /* Bit 19: PKA clock enable */ -#define RCC_AHB2ENR_SAESEN (1 << 20) /* Bit 20: SAES clock enable */ -#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* Bit 30: SRAM2 clock enable */ -#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* Bit 30: SRAM2 clock enable */ - -/* AHB4 Peripheral Clock enable register */ - -#define RCC_AHB4ENR_OTFDEC1EN (1 << 7) /* Bit 7: On-the-fly decryption module clock enable */ -#define RCC_AHB4ENR_SDMMC1EN (1 << 11) /* Bit 11: SDMMC1 clock enable */ -#define RCC_AHB4ENR_SDMMC2EN (1 << 12) /* Bit 12: SDMMC2 clock enable */ -#define RCC_AHB4ENR_FMCEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ -#define RCC_AHB4ENR_OSPI1EN (1 << 20) /* Bit 20: OCTOSPI1 module enable */ - -/* APB1 Peripheral clock enable register 1 */ - -#define RCC_APB1LENR_TIM2EN (1 << 0) /* Bit 0: TIM2 clock enable */ -#define RCC_APB1LENR_TIM3EN (1 << 1) /* Bit 1: TIM3 clock enable */ -#define RCC_APB1LENR_TIM4EN (1 << 2) /* Bit 2: TIM4 clock enable */ -#define RCC_APB1LENR_TIM5EN (1 << 3) /* Bit 3: TIM5 clock enable */ -#define RCC_APB1LENR_TIM6EN (1 << 4) /* Bit 4: TIM6 clock enable */ -#define RCC_APB1LENR_TIM7EN (1 << 5) /* Bit 5: TIM7 clock enable */ -#define RCC_APB1LENR_TIM12EN (1 << 6) /* Bit 5: TIM12 clock enable */ -#define RCC_APB1LENR_TIM13EN (1 << 7) /* Bit 5: TIM13 clock enable */ -#define RCC_APB1LENR_TIM14EN (1 << 8) /* Bit 5: TIM14 clock enable */ -#define RCC_APB1LENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */ -#define RCC_APB1LENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */ -#define RCC_APB1LENR_USART2EN (1 << 17) /* Bit 17: USART2 clock enable */ -#define RCC_APB1LENR_USART3EN (1 << 18) /* Bit 18: USART3 clock enable */ -#define RCC_APB1LENR_UART4EN (1 << 19) /* Bit 19: UART4 clock enable */ -#define RCC_APB1LENR_UART5EN (1 << 20) /* Bit 20: UART5 clock enable */ -#define RCC_APB1LENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */ -#define RCC_APB1LENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */ -#define RCC_APB1LENR_I3C1EN (1 << 23) /* Bit 23: I3C1 clock enable */ -#define RCC_APB1LENR_CRSEN (1 << 24) /* Bit 24: CRS clock enable */ -#define RCC_APB1LENR_USART6EN (1 << 25) /* Bit 25: USART6 clock enable */ -#define RCC_APB1LENR_USART10EN (1 << 26) /* Bit 26: USART10 clock enable */ -#define RCC_APB1LENR_USART11EN (1 << 27) /* Bit 27: USART11 clock enable */ -#define RCC_APB1LENR_CECEN (1 << 28) /* Bit 28: CEC clock enable */ -#define RCC_APB1LENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */ -#define RCC_APB1LENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */ - -/* APB1 Peripheral clock enable register 2 */ - -#define RCC_APB1HENR_UART9EN (1 << 0) /* Bit 0: UART9 clock enable */ -#define RCC_APB1HENR_UART12EN (1 << 1) /* Bit 1: UART12 clock enable */ -#define RCC_APB1HENR_DTSEN (1 << 3) /* Bit 3: DTS clock enable */ -#define RCC_APB1HENR_LPTIM2EN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable */ -#define RCC_APB1HENR_FDCANEN (1 << 9) /* Bit 9: FDCAN clock enable */ -#define RCC_APB1HENR_UCPD1EN (1 << 23) /* Bit 23: UCPD1 clock enable */ - -/* APB2 Peripheral clock enable register */ - -#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 clock enable */ -#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */ -#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 clock enable */ -#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */ -#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 clock enable */ -#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 clock enable */ -#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 clock enable */ -#define RCC_APB2ENR_SPI4EN (1 << 19) /* Bit 19: SPI4 clock enable */ -#define RCC_APB2ENR_SPI67EN (1 << 20) /* Bit 20: SPI6 clock enable */ -#define RCC_APB2ENR_SAI1EN (1 << 21) /* Bit 21: SAI1 clock enable */ -#define RCC_APB2ENR_SAI2EN (1 << 22) /* Bit 22: SAI2 clock enable */ -#define RCC_APB2ENR_USBEN (1 << 24) /* Bit 24: USB clock enable */ - -/* APB3 Peripheral clock enable register */ - -#define RCC_APB3ENR_SBSEN (1 << 1) /* Bit 1: SBS clock enable */ -#define RCC_APB3ENR_SPI5EN (1 << 5) /* Bit 5: SPI5 clock enable */ -#define RCC_APB3ENR_LPUART1EN (1 << 6) /* Bit 6: LPUART1 clock enable */ -#define RCC_APB3ENR_I2C3EN (1 << 7) /* Bit 7: I2C3 clock enable */ -#define RCC_APB3ENR_I2C4EN (1 << 8) /* Bit 8: I2C4 clock enable */ -#define RCC_APB3ENR_I3C2EN (1 << 9) /* Bit 9: I3C2 clock enable */ -#define RCC_APB3ENR_LPTIM1EN (1 << 11) /* Bit 11: LPTIM1 clock enable */ -#define RCC_APB3ENR_LPTIM3EN (1 << 12) /* Bit 12: LPTIM3 clock enable */ -#define RCC_APB3ENR_LPTIM4EN (1 << 13) /* Bit 13: LPTIM4 clock enable */ -#define RCC_APB3ENR_LPTIM5EN (1 << 14) /* Bit 14: LPTIM5 clock enable */ -#define RCC_APB3ENR_LPTIM6EN (1 << 15) /* Bit 15: LPTIM6 clock enable */ -#define RCC_APB3ENR_VREFEN (1 << 20) /* Bit 20: VREF clock enable */ -#define RCC_APB3ENR_RTCAPBEN (1 << 21) /* Bit 21: RTCABP clock enable */ - -/* RCC AHB1 Sleep and Stop modes peripheral clock enable register */ - -#define RCC_AHB1LPENR_GPDMA1LPEN (1 << 0) /* Bit 0: GPDMA1 clock enable during sleep mode */ -#define RCC_AHB1LPENR_GPDMA2LPEN (1 << 1) /* Bit 1: GPDMA2 clock enable during sleep mode */ -#define RCC_AHB1LPENR_FLITFLPEN (1 << 8) /* Bit 8: Flash Interface clock enable during sleep mode */ -#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during sleep mode */ -#define RCC_AHB1LPENR_CORDICLPEN (1 << 14) /* Bit 14: CORDIC clock enable during sleep mode */ -#define RCC_AHB1LPENR_FMACLPEN (1 << 15) /* Bit 15: FMAC clock enable during sleep mode */ -#define RCC_AHB1LPENR_RAMCFGLPEN (1 << 17) /* Bit 17: RAMCFG clock enable during sleep mode */ -#define RCC_AHB1LPENR_ETHLPEN (1 << 19) /* Bit 19: ETH clock enable during sleep mode */ -#define RCC_AHB1LPENR_ETHTXLPEN (1 << 20) /* Bit 20: ETH TX clock enable during sleep mode */ -#define RCC_AHB1LPENR_ETHRXLPEN (1 << 21) /* Bit 21: ETH RX clock enable during sleep mode */ -#define RCC_AHB1LPENR_TZSC1LPEN (1 << 24) /* Bit 24: TZSC1 clock enable during sleep mode */ -#define RCC_AHB1LPENR_BKPRAMLPEN (1 << 28) /* Bit 28: BKPRAM clock enable during sleep mode */ -#define RCC_AHB1LPENR_DCACHELPEN (1 << 30) /* Bit 25: DCACHE clock enable during sleep mode */ -#define RCC_AHB1LPENR_SRAM1LPEN (1 << 31) /* Bit 25: SRAM1 clock enable during sleep mode */ - -/* RCC AHB2 low power mode peripheral clock enable register */ - -#define RCC_AHB2LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during sleep mode */ -#define RCC_AHB2LPENR_ADCLPEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ -#define RCC_AHB2LPENR_DAC1LPEN (1 << 11) /* Bit 11: DAC clock enable during sleep mode */ -#define RCC_AHB2LPENR_DCMI_PSSILPEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ -#define RCC_AHB2LPENR_AESLPEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ -#define RCC_AHB2LPENR_HASHLPEN (1 << 17) /* Bit 17: HASH module enable */ -#define RCC_AHB2LPENR_RNGLPEN (1 << 18) /* Bit 18: Random number generator module enable */ -#define RCC_AHB2LPENR_PKALPEN (1 << 19) /* Bit 19: PKA clock enable during sleep mode */ -#define RCC_AHB2LPENR_SAESLPEN (1 << 20) /* Bit 20: SAES clock enable during sleep mode */ -#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* Bit 30: SRAM2 clock enable during sleep mode */ -#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* Bit 30: SRAM2 clock enable during sleep mode */ - -/* RCC AHB4 low power mode peripheral clock enable register */ - -#define RCC_AHB4LPENR_OTFDEC1LPEN (1 << 7) /* Bit 7: OTFDEC1 clock enable during sleep mode */ -#define RCC_AHB4LPENR_SDMMC1LPEN (1 << 11) /* Bit 11: SDMMC1 clock enable during sleep mode */ -#define RCC_AHB4LPENR_SDMMC2LPEN (1 << 12) /* Bit 12: SDMMC2 clock enable during sleep mode */ -#define RCC_AHB4LPENR_FMCLPEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ -#define RCC_AHB4LPENR_OSPI1LPEN (1 << 20) /* Bit 20: OCTOSPI1 module clock enable during sleep mode */ - -/* APB1 Peripheral clock enable register 1 */ - -#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM2 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM3 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM4 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM5 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM6 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM7 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 clock enable during sleep mode */ -#define RCC_APB1LLPENR_WWDGLPEN (1 << 11) /* Bit 11: WWDG clock enable during sleep mode */ -#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI2 clock enable during sleep mode */ -#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI3 clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* Bit 17: USART2 clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* Bit 18: USART3 clock enable during sleep mode */ -#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* Bit 19: UART4 clock enable during sleep mode */ -#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* Bit 20: UART5 clock enable during sleep mode */ -#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C1 clock enable during sleep mode */ -#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C2 clock enable during sleep mode */ -#define RCC_APB1LLPENR_I3C1LPEN (1 << 23) /* Bit 23: I3C1 clock enable during sleep mode */ -#define RCC_APB1LLPENR_CRSLPEN (1 << 24) /* Bit 24: CRS clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART6LPEN (1 << 25) /* Bit 25: USART6 clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART10LPEN (1 << 26) /* Bit 26: USART10 clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART11LPEN (1 << 27) /* Bit 27: USART11 clock enable during sleep mode */ -#define RCC_APB1LLPENR_CECLPEN (1 << 28) /* Bit 28: CEC clock enable during sleep mode */ -#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* Bit 30: UART7 clock enable during sleep mode */ -#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* Bit 31: UART8 clock enable during sleep mode */ - -/* APB1 Peripheral clock enable register 2 */ - -#define RCC_APB1HLPENR_UART9LPEN (1 << 0) /* Bit 0: UART9 clock enable during sleep mode */ -#define RCC_APB1HLPENR_UART12LPEN (1 << 1) /* Bit 1: UART12 clock enable during sleep mode */ -#define RCC_APB1HLPENR_DTSLPEN (1 << 3) /* Bit 3: DTS clock enable during sleep mode */ -#define RCC_APB1HLPENR_LPTIM2LPEN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable during sleep mode */ -#define RCC_APB1HLPENR_FDCANLPEN (1 << 9) /* Bit 9: FDCAN clock enable during sleep mode */ -#define RCC_APB1HLPENR_UCPD1LPEN (1 << 23) /* Bit 23: UCPD1 clock enable during sleep mode */ - -/* APB2 Peripheral clock enable register */ - -#define RCC_APB2LPENR_TIM1LPEN (1 << 11) /* Bit 11: TIM1 clock enable during sleep mode */ -#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during sleep mode */ -#define RCC_APB2LPENR_TIM8LPEN (1 << 13) /* Bit 13: TIM8 clock enable during sleep mode */ -#define RCC_APB2LPENR_USART1LPEN (1 << 14) /* Bit 14: USART1 clock enable during sleep mode */ -#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* Bit 16: TIM15 clock enable during sleep mode */ -#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* Bit 17: TIM16 clock enable during sleep mode */ -#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* Bit 18: TIM17 clock enable during sleep mode */ -#define RCC_APB2LPENR_SPI4LPEN (1 << 19) /* Bit 19: SPI4 clock enable during sleep mode */ -#define RCC_APB2LPENR_SPI67LPEN (1 << 20) /* Bit 20: SPI6 clock enable during sleep mode */ -#define RCC_APB2LPENR_SAI1LPEN (1 << 21) /* Bit 21: SAI1 clock enable during sleep mode */ -#define RCC_APB2LPENR_SAI2LPEN (1 << 22) /* Bit 22: SAI2 clock enable during sleep mode */ -#define RCC_APB2LPENR_USBLPEN (1 << 24) /* Bit 24: USB clock enable during sleep mode */ - -/* APB3 Peripheral clock enable register */ - -#define RCC_APB3LPENR_SBSLPEN (1 << 1) /* Bit 1: SBS clock enable during sleep mode */ -#define RCC_APB3LPENR_SPI5LPEN (1 << 5) /* Bit 5: SPI5 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPUART1LPEN (1 << 6) /* Bit 6: LPUART1 clock enable during sleep mode */ -#define RCC_APB3LPENR_I2C3LPEN (1 << 7) /* Bit 7: I2C3 clock enable during sleep mode */ -#define RCC_APB3LPENR_I2C4LPEN (1 << 8) /* Bit 8: I2C4 clock enable during sleep mode */ -#define RCC_APB3LPENR_I3C2LPEN (1 << 9) /* Bit 9: I3C2 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM1LPEN (1 << 11) /* Bit 11: LPTIM1 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM3LPEN (1 << 12) /* Bit 12: LPTIM3 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM4LPEN (1 << 13) /* Bit 13: LPTIM4 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM5LPEN (1 << 14) /* Bit 14: LPTIM5 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM6LPEN (1 << 15) /* Bit 15: LPTIM6 clock enable during sleep mode */ -#define RCC_APB3LPENR_VREFLPEN (1 << 20) /* Bit 20: VREF clock enable during sleep mode */ -#define RCC_APB3LPENR_RTCAPBLPEN (1 << 21) /* Bit 21: RTCABP clock enable during sleep mode */ - -/* Kernel Clock Configuration register 1 */ - -#define RCC_CCIPR1_USART1SEL_SHIFT (0) -#define RCC_CCIPR1_USART1SEL_MASK (7 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_PLL2QCK (1 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_PLL3QCK (2 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_HSIKERCK (3 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_CSIKERCK (4 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_LSECK (5 << RCC_CCIPR1_USART1SEL_SHIFT) - -#define RCC_CCIPR1_USART2SEL_SHIFT (3) -#define RCC_CCIPR1_USART2SEL_MASK (7 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_PLL2QCK (1 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_PLL3QCK (2 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_HSIKERCK (3 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_CSIKERCK (4 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_LSECK (5 << RCC_CCIPR1_USART2SEL_SHIFT) - -#define RCC_CCIPR1_USART3SEL_SHIFT (6) -#define RCC_CCIPR1_USART3SEL_MASK (7 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_PLL2QCK (1 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_PLL3QCK (2 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_HSIKERCK (3 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_CSIKERCK (4 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_LSECK (5 << RCC_CCIPR1_USART3SEL_SHIFT) - -#define RCC_CCIPR1_UART4SEL_SHIFT (9) -#define RCC_CCIPR1_UART4SEL_MASK (7 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_PLL2QCK (1 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_PLL3QCK (2 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_HSIKERCK (3 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_CSIKERCK (4 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_LSECK (5 << RCC_CCIPR1_UART4SEL_SHIFT) - -#define RCC_CCIPR1_UART5SEL_SHIFT (12) -#define RCC_CCIPR1_UART5SEL_MASK (7 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_PLL2QCK (1 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_PLL3QCK (2 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_HSIKERCK (3 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_CSIKERCK (4 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_LSECK (5 << RCC_CCIPR1_UART5SEL_SHIFT) - -#define RCC_CCIPR1_UART6SEL_SHIFT (15) -#define RCC_CCIPR1_UART6SEL_MASK (7 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_PLL2QCK (1 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_PLL3QCK (2 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_HSIKERCK (3 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_CSIKERCK (4 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_LSECK (5 << RCC_CCIPR1_UART6SEL_SHIFT) - -#define RCC_CCIPR1_UART7SEL_SHIFT (18) -#define RCC_CCIPR1_UART7SEL_MASK (7 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_PLL2QCK (1 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_PLL3QCK (2 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_HSIKERCK (3 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_CSIKERCK (4 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_LSECK (5 << RCC_CCIPR1_UART7SEL_SHIFT) - -#define RCC_CCIPR1_UART8SEL_SHIFT (21) -#define RCC_CCIPR1_UART8SEL_MASK (7 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_PLL2QCK (1 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_PLL3QCK (2 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_HSIKERCK (3 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_CSIKERCK (4 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_LSECK (5 << RCC_CCIPR1_UART8SEL_SHIFT) - -#define RCC_CCIPR1_UART9SEL_SHIFT (24) -#define RCC_CCIPR1_UART9SEL_MASK (7 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_PLL2QCK (1 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_PLL3QCK (2 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_HSIKERCK (3 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_CSIKERCK (4 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_LSECK (5 << RCC_CCIPR1_UART9SEL_SHIFT) - -#define RCC_CCIPR1_USART10SEL_SHIFT (27) -#define RCC_CCIPR1_USART10SEL_MASK (7 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_PLL2QCK (1 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_PLL3QCK (2 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_HSIKERCK (3 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_CSIKERCK (4 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_LSECK (5 << RCC_CCIPR1_USART10SEL_SHIFT) - -#define RCC_CCIPR1_TIMICSEL (1 << 31) - -/* Kernel Clock Configuration register 2 */ - -#define RCC_CCIPR2_USART11SEL_SHIFT (0) -#define RCC_CCIPR2_USART11SEL_MASK (7 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_PLL2QCK (1 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_PLL3QCK (2 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_HSIKERCK (3 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_CSIKERCK (4 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_LSECK (5 << RCC_CCIPR2_USART11SEL_SHIFT) - -#define RCC_CCIPR2_USART12SEL_SHIFT (4) -#define RCC_CCIPR2_USART12SEL_MASK (7 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_PLL2QCK (1 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_PLL3QCK (2 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_HSIKERCK (3 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_CSIKERCK (4 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_LSECK (5 << RCC_CCIPR2_USART12SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM1SEL_SHIFT (8) -#define RCC_CCIPR2_LPTIM1SEL_MASK (7 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_LSECK (5 << RCC_CCIPR2_LPTIM1SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM2SEL_SHIFT (12) -#define RCC_CCIPR2_LPTIM2SEL_MASK (7 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_RCCPCLK1 (0 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_LSECK (5 << RCC_CCIPR2_LPTIM2SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM3SEL_SHIFT (16) -#define RCC_CCIPR2_LPTIM3SEL_MASK (7 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_LSECK (5 << RCC_CCIPR2_LPTIM3SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM4SEL_SHIFT (20) -#define RCC_CCIPR2_LPTIM4SEL_MASK (7 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_LSECK (5 << RCC_CCIPR2_LPTIM4SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM5SEL_SHIFT (24) -#define RCC_CCIPR2_LPTIM5SEL_MASK (7 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_LSECK (5 << RCC_CCIPR2_LPTIM5SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM6SEL_SHIFT (28) -#define RCC_CCIPR2_LPTIM6SEL_MASK (7 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_LSECK (5 << RCC_CCIPR2_LPTIM6SEL_SHIFT) - -/* Kernel Clock Configuration register 3 */ - -#define RCC_CCIPR3_SPI1SEL_SHIFT (0) -#define RCC_CCIPR3_SPI1SEL_MASK (7 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_PLL1QCK (0 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_PLL2PCK (1 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_PLL3PCK (2 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_AUDIOCK (3 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_PERCK (4 << RCC_CCIPR3_SPI1SEL_SHIFT) - -#define RCC_CCIPR3_SPI2SEL_SHIFT (3) -#define RCC_CCIPR3_SPI2SEL_MASK (7 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_PLL1QCK (0 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_PLL2PCK (1 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_PLL3PCK (2 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_AUDIOCK (3 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_PERCK (4 << RCC_CCIPR3_SPI2SEL_SHIFT) - -#define RCC_CCIPR3_SPI3SEL_SHIFT (6) -#define RCC_CCIPR3_SPI3SEL_MASK (7 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_PLL1QCK (0 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_PLL2PCK (1 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_PLL3PCK (2 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_AUDIOCK (3 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_PERCK (4 << RCC_CCIPR3_SPI3SEL_SHIFT) - -#define RCC_CCIPR3_SPI4SEL_SHIFT (9) -#define RCC_CCIPR3_SPI4SEL_MASK (7 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_PLL2QCK (1 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_PLL3QCK (2 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_HSIKERCK (3 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_CSIKERCK (4 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_HSECK (5 << RCC_CCIPR3_SPI4SEL_SHIFT) - -#define RCC_CCIPR3_SPI5SEL_SHIFT (12) -#define RCC_CCIPR3_SPI5SEL_MASK (7 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_RCCPCLK3 (0 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_PLL2QCK (1 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_PLL3QCK (2 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_HSIKERCK (3 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_CSIKERCK (4 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_HSECK (5 << RCC_CCIPR3_SPI5SEL_SHIFT) - -#define RCC_CCIPR3_SPI6SEL_SHIFT (15) -#define RCC_CCIPR3_SPI6SEL_MASK (7 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_PLL2QCK (1 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_PLL3QCK (2 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_HSIKERCK (3 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_CSIKERCK (4 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_HSECK (5 << RCC_CCIPR3_SPI6SEL_SHIFT) - -#define RCC_CCIPR3_LPUART1SEL_SHIFT (24) -#define RCC_CCIPR3_LPUART1SEL_MASK (7 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_RCCPCLK3 (0 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_PLL2QCK (1 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_PLL3QCK (2 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_HSIKERCK (3 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_CSIKERCK (4 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_LSECK (5 << RCC_CCIPR3_LPUART1SEL_SHIFT) - -/* Kernel Clock Configuration register 4 */ - -#define RCC_CCIPR4_OCTOSPI1SEL_SHIFT (0) -#define RCC_CCIPR4_OCTOSPI1SEL_MASK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) -# define RCC_CCIPR4_OCTOSPI1SEL_RCCHCLK4 (0 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) -# define RCC_CCIPR4_OCTOSPI1SEL_PLL1QCK (1 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) -# define RCC_CCIPR4_OCTOSPI1SEL_PLL2RCK (2 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) -# define RCC_CCIPR4_OCTOSPI1SEL_PERCK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) - -#define RCC_CCIPR4_SYSTICKSEL_SHIFT (2) -#define RCC_CCIPR4_SYSTICKSEL_MASK (3 << RCC_CCIPR4_SYSTICKSEL_SHIFT) -# define RCC_CCIPR4_SYSTICKSEL_RCCHCLKd8 (0 << RCC_CCIPR4_SYSTICKSEL_SHIFT) -# define RCC_CCIPR4_SYSTICKSEL_LSIKERCK1 (1 << RCC_CCIPR4_SYSTICKSEL_SHIFT) -# define RCC_CCIPR4_SYSTICKSEL_LSICK1 (2 << RCC_CCIPR4_SYSTICKSEL_SHIFT) - -#define RCC_CCIPR4_USBSEL_SHIFT (4) -#define RCC_CCIPR4_USBSEL_MASK (3 << RCC_CCIPR4_USBSEL_SHIFT) -# define RCC_CCIPR4_USBSEL_NOCK (0 << RCC_CCIPR4_USBSEL_SHIFT) -# define RCC_CCIPR4_USBSEL_PLL1QCK (1 << RCC_CCIPR4_USBSEL_SHIFT) -# define RCC_CCIPR4_USBSEL_PLL3QCK (2 << RCC_CCIPR4_USBSEL_SHIFT) -# define RCC_CCIPR4_USBSEL_HSI48KERCK (3 << RCC_CCIPR4_USBSEL_SHIFT) - -#define RCC_CCIPR4_SDMMC1SEL (1 << 6) -#define RCC_CCIPR4_SDMMC2SEL (1 << 7) - -#define RCC_CCIPR4_I2C1SEL_SHIFT (16) -#define RCC_CCIPR4_I2C1SEL_MASK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) -# define RCC_CCIPR4_I2C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C1SEL_SHIFT) -# define RCC_CCIPR4_I2C1SEL_PLL3RCK (1 << RCC_CCIPR4_I2C1SEL_SHIFT) -# define RCC_CCIPR4_I2C1SEL_HSIKERCK (2 << RCC_CCIPR4_I2C1SEL_SHIFT) -# define RCC_CCIPR4_I2C1SEL_CSIKERCK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) - -#define RCC_CCIPR4_I2C2SEL_SHIFT (18) -#define RCC_CCIPR4_I2C2SEL_MASK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) -# define RCC_CCIPR4_I2C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C2SEL_SHIFT) -# define RCC_CCIPR4_I2C2SEL_PLL3RCK (1 << RCC_CCIPR4_I2C2SEL_SHIFT) -# define RCC_CCIPR4_I2C2SEL_HSIKERCK (2 << RCC_CCIPR4_I2C2SEL_SHIFT) -# define RCC_CCIPR4_I2C2SEL_CSIKERCK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) - -#define RCC_CCIPR4_I2C3SEL_SHIFT (20) -#define RCC_CCIPR4_I2C3SEL_MASK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) -# define RCC_CCIPR4_I2C3SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C3SEL_SHIFT) -# define RCC_CCIPR4_I2C3SEL_PLL3RCK (1 << RCC_CCIPR4_I2C3SEL_SHIFT) -# define RCC_CCIPR4_I2C3SEL_HSIKERCK (2 << RCC_CCIPR4_I2C3SEL_SHIFT) -# define RCC_CCIPR4_I2C3SEL_CSIKERCK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) - -#define RCC_CCIPR4_I2C4SEL_SHIFT (22) -#define RCC_CCIPR4_I2C4SEL_MASK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) -# define RCC_CCIPR4_I2C4SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C4SEL_SHIFT) -# define RCC_CCIPR4_I2C4SEL_PLL3RCK (1 << RCC_CCIPR4_I2C4SEL_SHIFT) -# define RCC_CCIPR4_I2C4SEL_HSIKERCK (2 << RCC_CCIPR4_I2C4SEL_SHIFT) -# define RCC_CCIPR4_I2C4SEL_CSIKERCK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) - -#define RCC_CCIPR4_I3C1SEL_SHIFT (24) -#define RCC_CCIPR4_I3C1SEL_MASK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) -# define RCC_CCIPR4_I3C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C1SEL_SHIFT) -# define RCC_CCIPR4_I3C1SEL_PLL3RCK (1 << RCC_CCIPR4_I3C1SEL_SHIFT) -# define RCC_CCIPR4_I3C1SEL_HSIKERCK (2 << RCC_CCIPR4_I3C1SEL_SHIFT) -# define RCC_CCIPR4_I3C1SEL_NOCK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) - -#define RCC_CCIPR4_I3C2SEL_SHIFT (24) -#define RCC_CCIPR4_I3C2SEL_MASK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) -# define RCC_CCIPR4_I3C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C2SEL_SHIFT) -# define RCC_CCIPR4_I3C2SEL_PLL3RCK (1 << RCC_CCIPR4_I3C2SEL_SHIFT) -# define RCC_CCIPR4_I3C2SEL_HSIKERCK (2 << RCC_CCIPR4_I3C2SEL_SHIFT) -# define RCC_CCIPR4_I3C2SEL_NOCK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) - -/* Kernel Clock Configuration register 5 */ - -#define RCC_CCIPR5_ADCDACSEL_SHIFT (0) -#define RCC_CCIPR5_ADCDACSEL_MASK (7 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_RCCHCLK (0 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_SYSCK (1 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_PLL2RCK (2 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_HSECK (3 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_HSEKERCK (4 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_CSIKERCK (5 << RCC_CCIPR5_ADCDACSEL_SHIFT) - -#define RCC_CCIPR5_DACSEL (1 << 3) - -#define RCC_CCIPR5_RNGSEL_SHIFT (4) -#define RCC_CCIPR5_RNGSEL_MASK (3 << RCC_CCIPR5_RNGSEL_SHIFT) -# define RCC_CCIPR5_RNGSEL_HSI48KERCK (0 << RCC_CCIPR5_RNGSEL_SHIFT) -# define RCC_CCIPR5_RNGSEL_PLL1QCK (1 << RCC_CCIPR5_RNGSEL_SHIFT) -# define RCC_CCIPR5_RNGSEL_LSECK (2 << RCC_CCIPR5_RNGSEL_SHIFT) -# define RCC_CCIPR5_RNGSEL_LSIKERCK (3 << RCC_CCIPR5_RNGSEL_SHIFT) - -#define RCC_CCIPR5_CECSEL_SHIFT (6) -#define RCC_CCIPR5_CECSEL_MASK (3 << RCC_CCIPR5_CECSEL_SHIFT) -# define RCC_CCIPR5_CECSEL_LSECK (0 << RCC_CCIPR5_CECSEL_SHIFT) -# define RCC_CCIPR5_CECSEL_LSIKERCK (1 << RCC_CCIPR5_CECSEL_SHIFT) -# define RCC_CCIPR5_CECSEL_CSIKERCKd122 (2 << RCC_CCIPR5_CECSEL_SHIFT) - -#define RCC_CCIPR5_FDCANSEL_SHIFT (8) -#define RCC_CCIPR5_FDCANSEL_MASK (3 << RCC_CCIPR5_FDCANSEL_SHIFT) -# define RCC_CCIPR5_FDCANSEL_HSECK (0 << RCC_CCIPR5_FDCANSEL_SHIFT) -# define RCC_CCIPR5_FDCANSEL_PLL1QCK (1 << RCC_CCIPR5_FDCANSEL_SHIFT) -# define RCC_CCIPR5_FDCANSEL_PLL2QCK (2 << RCC_CCIPR5_FDCANSEL_SHIFT) - -#define RCC_CCIPR5_SAI1SEL_SHIFT (16) -#define RCC_CCIPR5_SAI1SEL_MASK (7 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_PLL1QCK (0 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_PLL2PCK (1 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_PLL3PCK (2 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_PERCK (4 << RCC_CCIPR5_SAI1SEL_SHIFT) - -#define RCC_CCIPR5_SAI2SEL_SHIFT (19) -#define RCC_CCIPR5_SAI2SEL_MASK (7 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_PLL1QCK (0 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_PLL2PCK (1 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_PLL3PCK (2 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_PERCK (4 << RCC_CCIPR5_SAI2SEL_SHIFT) - -#define RCC_CCIPR5_CKPERSEL_SHIFT (30) -#define RCC_CCIPR5_CKPERSEL_MASK (3 << RCC_CCIPR5_CKPERSEL_SHIFT) -# define RCC_CCIPR5_CKPERSEL_HSIKERCK (0 << RCC_CCIPR5_CKPERSEL_SHIFT) -# define RCC_CCIPR5_CKPERSEL_CSIKERCK (1 << RCC_CCIPR5_CKPERSEL_SHIFT) -# define RCC_CCIPR5_CKPERSEL_HSECK (2 << RCC_CCIPR5_CKPERSEL_SHIFT) - -/* Backup domain control register */ - -#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ - -#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE oscillator drive capability */ -#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) -# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */ -# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */ -# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/ -# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */ - -#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */ -#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */ -#define RCC_BDCR_LSEEXT (1 << 7) /* Bit 7: LSE external clock type in bypass mode */ - -#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ -#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) -# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ -# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ -# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ -# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 32 used as RTC clock */ - -#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ -#define RCC_BDCR_VSWRST (1 << 16) /* Bit 16: VSwitch domain software reset */ -#define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */ -#define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */ -# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */ -# define RCC_BDCR_LSCOSEL_LSE RCC_BDCR_LSCOSEL /* LSE selected */ - -#define RCC_BDCR_LSION (1 << 26) /* Bit 26: LSI Oscillator Enable */ -#define RCC_BDCR_LSIRDY (1 << 27) /* Bit 27: LSI Oscillator Ready */ - -/* Reset status register */ - -#define RCC_RSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */ -#define RCC_RSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ -#define RCC_RSR_BORRSTF (1 << 27) /* Bit 27: BOR reset flag */ -#define RCC_RSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ -#define RCC_RSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ -#define RCC_RSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ -#define RCC_RSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ - -/* Secure Configuration Register */ - -#define RCC_SECCFGR_HSISEC (1 << 0) /* HSI clock configuration and status bits security */ -#define RCC_SECCFGR_HSESEC (1 << 1) /* HSE clock configuration and status bits security */ -#define RCC_SECCFGR_CSISEC (1 << 2) /* CSI clock configuration and status bits security */ -#define RCC_SECCFGR_LSISEC (1 << 3) /* LSI clock configuration and status bits security */ -#define RCC_SECCFGR_LSESEC (1 << 4) /* LSE clock configuration and status bits security */ -#define RCC_SECCFGR_SYSCLKSEC (1 << 5) /* SYSCLK configuration and status bits security */ -#define RCC_SECCFGR_PRESCSEC (1 << 6) /* PRESC configuration and status bits security */ -#define RCC_SECCFGR_PLL1SEC (1 << 7) /* PLL1 configuration and status bits security */ -#define RCC_SECCFGR_PLL2SEC (1 << 8) /* PLL2 configuration and status bits security */ -#define RCC_SECCFGR_PLL3SEC (1 << 9) /* PLL3 configuration and status bits security */ -#define RCC_SECCFGR_HSI48SEC (1 << 11) /* HSI48 configuration and status bits security */ -#define RCC_SECCFGR_RMVRST (1 << 12) /* Remove Reset flag security */ -#define RCC_SECCFGR_CKPERSELSEC (1 << 13) /* PER_CK selection security */ - -/* Privilege Configuration Register */ - -#define RCC_PRIVCFGR_SPRIV (1 << 0) /* Secure functions privilege configuration */ -#define RCC_PRIVCFGR_NSPRIV (1 << 1) /* Non-secure functions privilege configuration */ - -#endif /* CONFIG_STM32H5_STM32H562XX */ -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_RCC_H */ diff --git a/arch/arm/src/stm32h5/stm32.h b/arch/arm/src/stm32h5/stm32.h index 25d810170aae5..7011cf4f5d2ee 100644 --- a/arch/arm/src/stm32h5/stm32.h +++ b/arch/arm/src/stm32h5/stm32.h @@ -47,7 +47,6 @@ #include "stm32_lowputc.h" #include "stm32_pwr.h" #include "stm32_rcc.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_usbfs.h" diff --git a/arch/arm/src/stm32h5/stm32_lsi.c b/arch/arm/src/stm32h5/stm32_lsi.c deleted file mode 100644 index 463f05cd51c20..0000000000000 --- a/arch/arm/src/stm32h5/stm32_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_BDCR) & RCC_BDCR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32h5/stm32_pwm.h b/arch/arm/src/stm32h5/stm32_pwm.h index bfbe59529fa69..0fa086998972f 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.h +++ b/arch/arm/src/stm32h5/stm32_pwm.h @@ -41,7 +41,7 @@ #ifdef CONFIG_STM32_PWM # include -# include "hardware/stm32_tim.h" +# include "hardware/stm32h5_tim.h" #endif /**************************************************************************** diff --git a/arch/arm/src/stm32h5/stm32_tim.c b/arch/arm/src/stm32h5/stm32_tim.c deleted file mode 100644 index 56f70ffdb93f8..0000000000000 --- a/arch/arm/src/stm32h5/stm32_tim.c +++ /dev/null @@ -1,1553 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32H5_TIMn is defined then the CONFIG_STM32H5_TIMn_PWM may - * also be defined to indicate that the timer is intended to be used for - * pulsed output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32H5_TIMn is - * defined then CONFIG_STM32H5_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32H5_TIMn is defined - * then CONFIG_STM32H5_TIMn_DAC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32H5_TIMn is defined then - * CONFIG_STM32H5_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32H5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32H5_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32H5_TIM7_PWM) || defined (CONFIG_STM32H5_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32H5_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32H5_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32H5_TIM12_QE) -# undef CONFIG_STM32_TIM12 -#endif - -#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32H5_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32H5_TIM13_QE) -# undef CONFIG_STM32_TIM13 -#endif - -#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32H5_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32H5_TIM14_QE) -# undef CONFIG_STM32_TIM14 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32H5_TIM15_DAC) || defined(CONFIG_STM32H5_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32H5_TIM16_ADC) || \ - defined(CONFIG_STM32H5_TIM16_DAC) || defined(CONFIG_STM32H5_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32H5_TIM17_ADC) || \ - defined(CONFIG_STM32H5_TIM17_DAC) || defined(CONFIG_STM32H5_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ - defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ - defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM12) -# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM13) -# if defined(GPIO_TIM13_CH1OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM14) -# if defined(GPIO_TIM14_CH1OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -# endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Timer methods */ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count); -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - stm32_tim_channel_t mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = &stm32_tim_enable, - .disable = &stm32_tim_disable, - .setmode = &stm32_tim_setmode, - .setclock = &stm32_tim_setclock, - .setperiod = &stm32_tim_setperiod, - .getcounter = &stm32_tim_getcounter, - .setcounter = &stm32_tim_setcounter, - .getwidth = &stm32_tim_getwidth, - .setchannel = &stm32_tim_setchannel, - .setcompare = &stm32_tim_setcompare, - .getcapture = &stm32_tim_getcapture, - .setisr = &stm32_tim_setisr, - .enableint = &stm32_tim_enableint, - .disableint = &stm32_tim_disableint, - .ackint = &stm32_tim_ackint, - .checkint = &stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_getwidth - ****************************************************************************/ - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - /* Only TIM2 and TIM5 timers may be 32-bits in width */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#if defined(CONFIG_STM32_TIM2) - case STM32_TIM2_BASE: - return 32; -#endif - -#if defined(CONFIG_STM32_TIM5) - case STM32_TIM5_BASE: - return 32; -#endif - - /* All others are 16-bit times */ - - default: - return 16; - } -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_BTIM_CNT_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_setcounter - ****************************************************************************/ - -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count) -{ - DEBUGASSERT(dev != NULL); - - if (stm32_tim_getwidth(dev) > 16) - { - stm32_putreg32(dev, STM32_BTIM_CNT_OFFSET, count); - } - else - { - stm32_putreg16(dev, STM32_BTIM_CNT_OFFSET, (uint16_t)count); - } -} - -/* Reset timer into system default state, but do not affect output/input - * pins - */ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\ - defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\ - defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM6_GPIOCONFIG)||\ - defined(HAVE_TIM7_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)||\ - defined(HAVE_TIM12_GPIOCONFIG)||defined(HAVE_TIM13_GPIOCONFIG)||\ - defined(HAVE_TIM14_GPIOCONFIG)||defined(HAVE_TIM15_GPIOCONFIG)||\ - defined(HAVE_TIM16_GPIOCONFIG)||defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - freqin = STM32_TIM12_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - freqin = STM32_TIM13_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1_UP; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8_UP; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - vectorno = STM32_IRQ_TIM12; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - - return OK; -} - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); -} - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); -} - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET); - return (regval & source) ? 1 : 0; -} - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - - return OK; -} - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~(3 << GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTTOGGLE: - ccmr_val = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT); - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -# if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -# if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -# if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -# if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -# if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -# if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM8_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM8_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - switch (channel) - { -# if defined(GPIO_TIM12_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -# if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -# if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -# if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -# if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -# if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - } - - return OK; -} - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/* TODO: Detach interrupts, and close down all TIM Channels */ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h5/stm32_tim.h b/arch/arm/src/stm32h5/stm32_tim.h deleted file mode 100644 index b571fcb7159ba..0000000000000 --- a/arch/arm/src/stm32h5/stm32_tim.h +++ /dev/null @@ -1,223 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32H5_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, - - /* Clock sources, OR'ed with CK_EXT */ - - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x0e, - - /* Output Compare Modes */ - - /* Enable standard PWM mode, active high when counter < compare */ - - STM32_TIM_CH_OUTPWM = 0x04, - - /* Toggle TIM_CHx output on UEV */ - - STM32_TIM_CH_OUTTOGGLE = 0x08, -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC - open collector mode -#endif -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); - - /* General and Advanced Timers Adds */ - - int (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, - int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32H5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c deleted file mode 100644 index d0a77244157be..0000000000000 --- a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,586 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2023 Max Kriegleder. All rights reserved. - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * SPDX-FileContributor: Max Kriegleder - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index e368b9141076b..e6a3bf78ba7a0 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -58,7 +58,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_pinmap.h" #include "hardware/stm32_usbfs.h" -#include "hardware/stm32h5xxx_rcc.h" +#include "hardware/stm32_rcc.h" #include "hardware/stm32h5xxx_pwr.h" #include "stm32_usbdrdhost.h" diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index 7965169017968..52f8ba0b7e869 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -56,10 +56,6 @@ else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) -endif() - if(CONFIG_ARM_MPU) list(APPEND SRCS stm32_mpuinit.c) endif() @@ -96,10 +92,6 @@ if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) - list(APPEND SRCS stm32_lsi.c) -endif() - if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() @@ -141,10 +133,6 @@ if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() - if(CONFIG_STM32_TIMX_CAP) list(APPEND SRCS stm32_capture.c) endif() @@ -172,10 +160,6 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32_TIM) - list(APPEND SRCS stm32_tim.c) -endif() - if(CONFIG_STM32_LPTIM) list(APPEND SRCS stm32_lptim.c) endif() @@ -192,10 +176,6 @@ if(CONFIG_MDIO_BUS) list(APPEND SRCS stm32_mdio.c) endif() -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() - if(CONFIG_PM) list(APPEND SRCS stm32_pmsleep.c stm32_pmstandby.c stm32_pmstop.c) if(NOT CONFIG_ARCH_CUSTOM_PMINIT) diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 90ec8b7febf03..4a380948d71e9 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -529,9 +529,11 @@ config STM32_STM32H7X0XX select STM32_HAVE_FDCAN2 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -560,9 +562,11 @@ config STM32_STM32H7X3XX select STM32_HAVE_FDCAN2 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -589,9 +593,11 @@ config STM32_STM32H7B3XX select ARCH_HAVE_DPFPU select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -620,9 +626,11 @@ config STM32_STM32H7X5XX select STM32_HAVE_FDCAN2 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -651,9 +659,11 @@ config STM32_STM32H7X7XX select ARCH_HAVE_DPFPU select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index e1f6fd958b949..dc6d469a85924 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -55,10 +55,6 @@ else CHIP_CSRCS += stm32_timerisr.c endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c -endif - ifeq ($(CONFIG_ARM_MPU),y) CHIP_CSRCS += stm32_mpuinit.c endif @@ -95,10 +91,6 @@ ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif -ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) -CHIP_CSRCS += stm32_lsi.c -endif - ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif @@ -140,10 +132,6 @@ ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif - ifeq ($(CONFIG_STM32_TIMX_CAP),y) CHIP_CSRCS += stm32_capture.c endif @@ -171,10 +159,6 @@ endif endif endif -ifeq ($(CONFIG_STM32_TIM),y) -CHIP_CSRCS += stm32_tim.c -endif - ifeq ($(CONFIG_STM32_LPTIM),y) CHIP_CSRCS += stm32_lptim.c endif @@ -191,9 +175,6 @@ ifeq ($(CONFIG_MDIO_BUS),y) CHIP_CSRCS += stm32_mdio.c endif -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder.c -endif ifeq ($(CONFIG_PM),y) CHIP_CSRCS += stm32_pmsleep.c stm32_pmstandby.c stm32_pmstop.c diff --git a/arch/arm/src/stm32h7/hardware/stm32_rcc.h b/arch/arm/src/stm32h7/hardware/stm32_rcc.h index 67ef3c5d180ed..293ccdca13679 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_rcc.h @@ -28,20 +28,1134 @@ ****************************************************************************/ #include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32H7X0XX) -# include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32_STM32H7X3XX) -# include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32_STM32H7B3XX) -# include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32_STM32H7X5XX) -# include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32_STM32H7X7XX) -# include "hardware/stm32h7x3xx_rcc.h" -#else -# error "Unsupported STM32 H7 part" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* TODO: Complete comments */ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 +#define STM32_RCC_CRRCR_OFFSET 0x0008 +#define STM32_RCC_CFGR_OFFSET 0x0010 /* Clock configuration register */ +#define STM32_RCC_D1CFGR_OFFSET 0x0018 +#define STM32_RCC_D2CFGR_OFFSET 0x001c +#define STM32_RCC_D3CFGR_OFFSET 0x0020 +#define STM32_RCC_PLLCKSELR_OFFSET 0x0028 +#define STM32_RCC_PLLCFGR_OFFSET 0x002c +#define STM32_RCC_PLL1DIVR_OFFSET 0x0030 +#define STM32_RCC_PLL1FRACR_OFFSET 0x0034 +#define STM32_RCC_PLL2DIVR_OFFSET 0x0038 +#define STM32_RCC_PLL2FRACR_OFFSET 0x003c +#define STM32_RCC_PLL3DIVR_OFFSET 0x0040 +#define STM32_RCC_PLL3FRACR_OFFSET 0x0044 +#define STM32_RCC_D1CCIPR_OFFSET 0x004c /* Domain 1 Kernel Clock configuration register */ +#define STM32_RCC_D2CCIP1R_OFFSET 0x0050 /* Domain 2 Kernel Clock configuration register 1 */ +#define STM32_RCC_D2CCIP2R_OFFSET 0x0054 /* Domain 2 Kernel Clock configuration register 2 */ +#define STM32_RCC_D3CCIPR_OFFSET 0x0058 /* Domain 3 Kernel Clock configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0060 /* Clock Source Interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x0064 /* Clock Source Interrupt Flag register */ +#define STM32_RCC_CICR_OFFSET 0x0068 /* Clock Source Interrupt Clear register */ +#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup Domain Control register */ +#define STM32_RCC_CSR_OFFSET 0x0074 /* Clock Control and Status register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0080 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x0084 /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x007c /* AHB3 peripheral reset register */ +#define STM32_RCC_AHB4RSTR_OFFSET 0x0088 /* AHB4 peripheral reset register */ +#define STM32_RCC_APB1LRSTR_OFFSET 0x0090 /* APB1 L Peripheral reset register */ +#define STM32_RCC_APB1HRSTR_OFFSET 0x0094 /* APB1 H Peripheral reset register */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0098 /* APB2 Peripheral reset register */ +#define STM32_RCC_APB3RSTR_OFFSET 0x008c /* APB3 Peripheral reset register */ +#define STM32_RCC_APB4RSTR_OFFSET 0x009c /* APB4 Peripheral reset register */ +#define STM32_RCC_GCR_OFFSET 0x00a0 /* RCC Global Control register */ +#define STM32_RCC_D3AMR_OFFSET 0x00a8 /* D3 Autonomous mode register */ +#define STM32_RCC_RSR_OFFSET 0x00d0 /* RCC Reset Status register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x00d8 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x00dc /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x00d4 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_AHB4ENR_OFFSET 0x00e0 /* AHB4 Peripheral Clock enable register */ +#define STM32_RCC_APB1LENR_OFFSET 0x00e8 /* APB1 L Peripheral Clock enable register */ +#define STM32_RCC_APB1HENR_OFFSET 0x00ec /* APB1 H Peripheral Clock enable register */ +#define STM32_RCC_APB2ENR_OFFSET 0x00f0 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_APB3ENR_OFFSET 0x00e4 /* APB3 Peripheral Clock enable register */ +#define STM32_RCC_APB4ENR_OFFSET 0x00f4 /* APB4 Peripheral Clock enable register */ +#define STM32_RCC_AHB1LPENR_OFFSET 0x0100 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2LPENR_OFFSET 0x0104 /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3LPENR_OFFSET 0x00fc /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB4LPENR_OFFSET 0x0108 /* RCC AHB4 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1LLPENR_OFFSET 0x0110 /* RCC APB1 L low power mode peripheral clock enable register */ +#define STM32_RCC_APB1HLPENR_OFFSET 0x0114 /* RCC APB1 H low power mode peripheral clock enable register */ +#define STM32_RCC_APB2LPENR_OFFSET 0x0118 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_APB3LPENR_OFFSET 0x010c /* RCC APB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB4LPENR_OFFSET 0x011c /* RCC APB4 low power mode peripheral clock enable register */ + +/* Register Addresses *******************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_D1CFGR (STM32_RCC_BASE + STM32_RCC_D1CFGR_OFFSET) +#define STM32_RCC_D2CFGR (STM32_RCC_BASE + STM32_RCC_D2CFGR_OFFSET) +#define STM32_RCC_D3CFGR (STM32_RCC_BASE + STM32_RCC_D3CFGR_OFFSET) +#define STM32_RCC_PLLCKSELR (STM32_RCC_BASE + STM32_RCC_PLLCKSELR_OFFSET) +#define STM32_RCC_PLLCFGR (STM32_RCC_BASE + STM32_RCC_PLLCFGR_OFFSET) +#define STM32_RCC_PLL1DIVR (STM32_RCC_BASE + STM32_RCC_PLL1DIVR_OFFSET) +#define STM32_RCC_PLL1FRACR (STM32_RCC_BASE + STM32_RCC_PLL1FRACR_OFFSET) +#define STM32_RCC_PLL2DIVR (STM32_RCC_BASE + STM32_RCC_PLL2DIVR_OFFSET) +#define STM32_RCC_PLL2FRACR (STM32_RCC_BASE + STM32_RCC_PLL2FRACR_OFFSET) +#define STM32_RCC_PLL3DIVR (STM32_RCC_BASE + STM32_RCC_PLL3DIVR_OFFSET) +#define STM32_RCC_PLL3FRACR (STM32_RCC_BASE + STM32_RCC_PLL3FRACR_OFFSET) +#define STM32_RCC_D1CCIPR (STM32_RCC_BASE + STM32_RCC_D1CCIPR_OFFSET) +#define STM32_RCC_D2CCIP1R (STM32_RCC_BASE + STM32_RCC_D2CCIP1R_OFFSET) +#define STM32_RCC_D2CCIP2R (STM32_RCC_BASE + STM32_RCC_D2CCIP2R_OFFSET) +#define STM32_RCC_D3CCIPR (STM32_RCC_BASE + STM32_RCC_D3CCIPR_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_AHB4RSTR (STM32_RCC_BASE + STM32_RCC_AHB4RSTR_OFFSET) +#define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) +#define STM32_RCC_APB1HRSTR (STM32_RCC_BASE + STM32_RCC_APB1HRSTR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) +#define STM32_RCC_APB4RSTR (STM32_RCC_BASE + STM32_RCC_APB4RSTR_OFFSET) +#define STM32_RCC_GCR (STM32_RCC_BASE + STM32_RCC_GCR_OFFSET) +#define STM32_RCC_D3AMR (STM32_RCC_BASE + STM32_RCC_D3AMR_OFFSET) +#define STM32_RCC_RSR (STM32_RCC_BASE + STM32_RCC_RSR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_AHB4ENR (STM32_RCC_BASE + STM32_RCC_AHB4ENR_OFFSET) +#define STM32_RCC_APB1LENR (STM32_RCC_BASE + STM32_RCC_APB1LENR_OFFSET) +#define STM32_RCC_APB1HENR (STM32_RCC_BASE + STM32_RCC_APB1HENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_APB3ENR (STM32_RCC_BASE + STM32_RCC_APB3ENR_OFFSET) +#define STM32_RCC_APB4ENR (STM32_RCC_BASE + STM32_RCC_APB4ENR_OFFSET) +#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE + STM32_RCC_AHB1LPENR_OFFSET) +#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE + STM32_RCC_AHB2LPENR_OFFSET) +#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE + STM32_RCC_AHB3LPENR_OFFSET) +#define STM32_RCC_AHB4LPENR (STM32_RCC_BASE + STM32_RCC_AHB4LPENR_OFFSET) +#define STM32_RCC_APB1LLPENR (STM32_RCC_BASE + STM32_RCC_APB1LLPENR_OFFSET) +#define STM32_RCC_APB1HLPENR (STM32_RCC_BASE + STM32_RCC_APB1HLPENR_OFFSET) +#define STM32_RCC_APB2LPENR (STM32_RCC_BASE + STM32_RCC_APB2LPENR_OFFSET) +#define STM32_RCC_APB3LPENR (STM32_RCC_BASE + STM32_RCC_APB3LPENR_OFFSET) +#define STM32_RCC_APB4LPENR (STM32_RCC_BASE + STM32_RCC_APB4LPENR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Source Control Register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIKERON (1 << 1) /* Bit 1: Internal High Speed clock enable for some IPs Kernel ?? */ +#define RCC_CR_HSIRDY (1 << 2) /* Bit 2: Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_SHIFT (3) /* Bits 3-4: HSI clock divider */ +#define RCC_CR_HSIDIV_MASK (3 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_1 (0 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_2 (1 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_4 (2 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_8 (3 << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI Divider flag */ + /* Bit 6: Reserved */ +#define RCC_CR_CSION (1 << 7) /* Bit 7: The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY (1 << 8) /* Bit 8: The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON (1 << 9) /* Bit 9: Internal RC 4MHz oscillator clock enable for some IPs Kernel */ + /* Bits 10-11: Reserved */ +#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready */ +#define RCC_CR_D1CKRDY (1 << 14) /* Bit 14: D1 domain clocks ready flag */ +#define RCC_CR_D2CKRDY (1 << 15) /* Bit 15: D2 domain clocks ready flag */ +#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ +#define RCC_CR_CSSHSEON (1 << 19) /* Bit 19: HSE Clock security System enable */ + /* Bits 20-23: Reserved */ +#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: System PLL1 clock enable */ +#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: System PLL1 clock ready */ +#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: System PLL2 clock enable */ +#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: System PLL2 clock ready */ +#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: System PLL3 clock enable */ +#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: System PLL3 clock ready */ + /* Bits 30-31: Reserved */ + +/* Internal Clock Source Calibration Register */ + +/* HSICAL configuration */ + +#define RCC_ICSCR_HSICAL_SHIFT (0ul) +#define RCC_ICSCR_HSICAL_MASK (0xFFFul << RCC_ICSCR_HSICAL_SHIFT) +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_MASK /* HSICAL[11:0] bits */ + +/* HSITRIM configuration */ + +#define RCC_ICSCR_HSITRIM_SHIFT (12ul) +#define RCC_ICSCR_HSITRIM_MASK (0x3Ful << RCC_ICSCR_HSITRIM_SHIFT) +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_MASK /* HSITRIM[5:0] bits */ + +/* CSICAL configuration */ + +#define RCC_ICSCR_CSICAL_SHIFT (18ul) +#define RCC_ICSCR_CSICAL_MASK (0xFFul << RCC_ICSCR_CSICAL_SHIFT) +#define RCC_ICSCR_CSICAL RCC_ICSCR_CSICAL_MASK /* CSICAL[7:0] bits */ + +/* CSITRIM configuration */ + +#define RCC_ICSCR_CSITRIM_SHIFT (26ul) +#define RCC_ICSCR_CSITRIM_MASK (0x1Ful << RCC_ICSCR_CSITRIM_SHIFT) +#define RCC_ICSCR_CSITRIM RCC_ICSCR_CSITRIM_MASK /* CSITRIM[4:0] bits */ + +/* Clock Recovery RC Register */ + +/* HSI48CAL configuration */ + +#define RCC_CRRCR_HSI48CAL_SHIFT (0ul) +#define RCC_CRRCR_HSI48CAL_MASK (0x3FFul << RCC_CRRCR_HSI48CAL_SHIFT) +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_MASK /* HSI48CAL[9:0] bits */ + +/* Clock Configuration Register (CFGR) */ + +#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */ +#define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT) +# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selection as system clock */ +# define RCC_CFGR_SW_CSI (1 << RCC_CFGR_SW_SHIFT) /* 001: CSI selection as system clock */ +# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 010: HSE selection as system clock */ +# define RCC_CFGR_SW_PLL1 (3 << RCC_CFGR_SW_SHIFT) /* 011: PLL1 selection as system clock */ +#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */ +#define RCC_CFGR_SWS_MASK (7 << RCC_CFGR_SWS_SHIFT) +# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI used as system clock */ +# define RCC_CFGR_SWS_CSI (1 << RCC_CFGR_SWS_SHIFT) /* 001: CSI used as system clock */ +# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 010: HSE used as system clock */ +# define RCC_CFGR_SWS_PLL1 (3 << RCC_CFGR_SWS_SHIFT) /* 011: PLL1 used as system clock */ +#define RCC_CFGR_STOPWUCK (1 << 6) /* Bit 6: Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK (1 << 7) /* Bit 7: Kernel Clock Selection after a Wake Up from STOP */ +#define RCC_CFGR_RTCPRE_SHIFT (8) /* Bits 8-13: HSE division factor for RTC clock */ +#define RCC_CFGR_RTCPRE_MASK (0x3f << RCC_CFGR_RTCPRE_SHIFT) +# define RCC_CFGR_RTCPRE(x) (((uint32_t)(x)) << RCC_CFGR_RTCPRE_SHIFT) +#define RCC_CFGR_HRTIMSEL (1 << 14) /* Bit 14: HRTIM TImer clock prescaler */ +#define RCC_CFGR_TIMPRE (1 << 15) /* Timers clocks prescaler */ +#define RCC_CFGR_MCO1PRE_SHIFT (18) /* Bits 18-21: MCO1 prescaler */ +#define RCC_CFGR_MCO1PRE_MASK (0xf << RCC_CFGR_MCO1PRE_SHIFT) +# define RCC_CFGR_MCO1PRE(x) (((uint32_t)(x)) << 18) +#define RCC_CFGR_MCO1_SHIFT (22) /* Bits 22-24: Microcontroller Clock Output 1 */ +#define RCC_CFGR_MCO1_MASK (7 << RCC_CFGR_MCO1_SHIFT) +# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */ +# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */ +# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */ +# define RCC_CFGR_MCO1_PLL1Q (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */ +# define RCC_CFGR_MCO1_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */ +#define RCC_CFGR_MCO2PRE_SHIFT (25) /* Bits 25-28: MCO2 prescaler */ +#define RCC_CFGR_MCO2PRE_MASK (0xf << RCC_CFGR_MCO2PRE_SHIFT) +# define RCC_CFGR_MCO2PRE(x) (((uint32_t)(x)) << RCC_CFGR_MCO2PRE_SHIFT) +#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */ +#define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO2_SHIFT) +# define RCC_CFGR_MCO2_SYS (0 << RCC_CFGR_MCO2_SHIFT) /* 000: HSI clock selected */ +# define RCC_CFGR_MCO2_PLL2P (1 << RCC_CFGR_MCO2_SHIFT) /* 001: PLL2 peripheral clock selected */ +# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 010: HSE oscillator clock selected */ +# define RCC_CFGR_MCO2_PLL1P (3 << RCC_CFGR_MCO2_SHIFT) /* 011: PLL1 peripheral clock selected */ +# define RCC_CFGR_MCO2_CSI (4 << RCC_CFGR_MCO2_SHIFT) /* 100: CSI clock selected */ +# define RCC_CFGR_MCO2_LSI (5 << RCC_CFGR_MCO2_SHIFT) /* 101: LSI clock selected */ + +/* Bit definitions for RCC_D1CFGR */ + +#define RCC_D1CFGR_HPRE_SHIFT (0) /* Bits 0-3: D1 domain AHB prescaler */ +#define RCC_D1CFGR_HPRE_MASK (15 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLK (0 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd2 (8 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd4 (9 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd8 (10 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd16 (11 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd64 (12 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd128 (13 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd256 (14 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd512 (15 << RCC_D1CFGR_HPRE_SHIFT) + +#define RCC_D1CFGR_D1PPRE_SHIFT (4) /* Bits 4-6: D1 domain APB3 prescaler */ +#define RCC_D1CFGR_D1PPRE_MASK (7 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLK (0 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd2 (4 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd4 (5 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd8 (6 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd16 (7 << RCC_D1CFGR_D1PPRE_SHIFT) + /* Bit 7: Reserved */ +#define RCC_D1CFGR_D1CPRE_SHIFT (8) /* Bits 8-11: D1 domain Core prescaler */ +#define RCC_D1CFGR_D1CPRE_MASK (15 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLK (0 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd2 (8 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd4 (9 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd8 (10 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd16 (11 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd64 (12 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd128 (13 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd256 (14 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd512 (15 << RCC_D1CFGR_D1CPRE_SHIFT) + /* Bits 12-31: Reserved */ + +/* Bit definitions for RCC_D2CFGR */ + + /* Bits 0-3: Reserved */ +#define RCC_D2CFGR_D2PPRE1_SHIFT (4) /* Bits 4-6: D2 domain APB1 prescaler */ +#define RCC_D2CFGR_D2PPRE1_MASK (7 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLK (0 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd2 (4 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd4 (5 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd8 (6 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd16 (7 << RCC_D2CFGR_D2PPRE1_SHIFT) + /* Bit 7: Reserved */ +#define RCC_D2CFGR_D2PPRE2_SHIFT (8) /* Bits 8-10: D2 domain APB2 prescaler */ +#define RCC_D2CFGR_D2PPRE2_MASK (7 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLK (0 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd2 (4 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd4 (5 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd8 (6 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd16 (7 << RCC_D2CFGR_D2PPRE2_SHIFT) + /* Bits 11-31: Reserved */ + +/* Bit definitions for RCC_D3CFGR */ + + /* Bits 0-3: Reserved */ +#define RCC_D3CFGR_D3PPRE_SHIFT (4) /* Bits 4-6: D3 domain APB4 prescaler */ +#define RCC_D3CFGR_D3PPRE_MASK (7 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLK (0 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd2 (4 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd4 (5 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd8 (6 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd16 (7 << RCC_D3CFGR_D3PPRE_SHIFT) + /* Bits 7-31: Reserved */ + +/* Bit definitions for RCC_PLLCKSELR register */ + +#define RCC_PLLCKSELR_PLLSRC_SHIFT (0) /* Bit 0: */ +#define RCC_PLLCKSELR_PLLSRC_MASK (0x3 << RCC_PLLCKSELR_PLLSRC_SHIFT) +#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_MASK + +#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /* HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_CSI ((uint32_t)0x00000001) /* CSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSE ((uint32_t)0x00000002) /* HSE source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_NONE ((uint32_t)0x00000003) /* No source clock selected */ + +#define RCC_PLLCKSELR_DIVM1_SHIFT (4ul) +#define RCC_PLLCKSELR_DIVM1(x) ((x) << RCC_PLLCKSELR_DIVM1_SHIFT) /* Prescaler for PLL1: 1 - 63, 0 = disabled */ +#define RCC_PLLCKSELR_DIVM2_SHIFT (12ul) +#define RCC_PLLCKSELR_DIVM2(x) ((x) << RCC_PLLCKSELR_DIVM2_SHIFT) /* Prescaler for PLL2: 1 - 63, 0 = disabled */ +#define RCC_PLLCKSELR_DIVM3_SHIFT (20ul) +#define RCC_PLLCKSELR_DIVM3(x) ((x) << RCC_PLLCKSELR_DIVM3_SHIFT) /* Prescaler for PLL3: 1 - 63, 0 = disabled */ + +/* Bit definition for RCC_PLLCFGR register */ + +#define RCC_PLLCFGR_RESET ((uint32_t)0x01FF0000) + +#define RCC_PLLCFGR_PLL1FRACEN_SHIFT (0ul) +#define RCC_PLLCFGR_PLL1FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL1FRACEN_SHIFT) +#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_MASK /* Fractional latch enable */ +#define RCC_PLLCFGR_PLL1VCOSEL_SHIFT (1ul) +#define RCC_PLLCFGR_PLL1VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL1VCOSEL_SHIFT) +#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ +#define RCC_PLLCFGR_PLL1VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ +#define RCC_PLLCFGR_PLL1VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ +#define RCC_PLLCFGR_PLL1RGE_SHIFT (2ul) +#define RCC_PLLCFGR_PLL1RGE_MASK (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) +#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_MASK +#define RCC_PLLCFGR_PLL1RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ +#define RCC_PLLCFGR_PLL1RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ +#define RCC_PLLCFGR_PLL1RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ +#define RCC_PLLCFGR_PLL1RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ + +#define RCC_PLLCFGR_PLL2FRACEN_SHIFT (4ul) +#define RCC_PLLCFGR_PLL2FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL2FRACEN_SHIFT) +#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_MASK /* Fractional latch enable */ +#define RCC_PLLCFGR_PLL2VCOSEL_SHIFT (5ul) +#define RCC_PLLCFGR_PLL2VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL2VCOSEL_SHIFT) +#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ +#define RCC_PLLCFGR_PLL2VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ +#define RCC_PLLCFGR_PLL2VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ +#define RCC_PLLCFGR_PLL2RGE_SHIFT (6ul) +#define RCC_PLLCFGR_PLL2RGE_MASK (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) +#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_MASK +#define RCC_PLLCFGR_PLL2RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ +#define RCC_PLLCFGR_PLL2RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ +#define RCC_PLLCFGR_PLL2RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ +#define RCC_PLLCFGR_PLL2RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ + +#define RCC_PLLCFGR_PLL3FRACEN_SHIFT (8ul) +#define RCC_PLLCFGR_PLL3FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL3FRACEN_SHIFT) +#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_MASK /* Fractional latch enable */ +#define RCC_PLLCFGR_PLL3VCOSEL_SHIFT (9ul) +#define RCC_PLLCFGR_PLL3VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL3VCOSEL_SHIFT) +#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ +#define RCC_PLLCFGR_PLL3VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ +#define RCC_PLLCFGR_PLL3VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ +#define RCC_PLLCFGR_PLL3RGE_SHIFT (10ul) +#define RCC_PLLCFGR_PLL3RGE_MASK (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) +#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_MASK +#define RCC_PLLCFGR_PLL3RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ +#define RCC_PLLCFGR_PLL3RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ +#define RCC_PLLCFGR_PLL3RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ +#define RCC_PLLCFGR_PLL3RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ + +#define RCC_PLLCFGR_DIVP1EN_SHIFT (16ul) +#define RCC_PLLCFGR_DIVP1EN_MASK (0x1ul << RCC_PLLCFGR_DIVP1EN_SHIFT) +#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_MASK +#define RCC_PLLCFGR_DIVQ1EN_SHIFT (17ul) +#define RCC_PLLCFGR_DIVQ1EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ1EN_SHIFT) +#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_MASK +#define RCC_PLLCFGR_DIVR1EN_SHIFT (18ul) +#define RCC_PLLCFGR_DIVR1EN_MASK (0x1ul << RCC_PLLCFGR_DIVR1EN_SHIFT) +#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_MASK + +#define RCC_PLLCFGR_DIVP2EN_SHIFT (19ul) +#define RCC_PLLCFGR_DIVP2EN_MASK (0x1ul << RCC_PLLCFGR_DIVP2EN_SHIFT) +#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_MASK +#define RCC_PLLCFGR_DIVQ2EN_SHIFT (20ul) +#define RCC_PLLCFGR_DIVQ2EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ2EN_SHIFT) +#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_MASK +#define RCC_PLLCFGR_DIVR2EN_SHIFT (21ul) +#define RCC_PLLCFGR_DIVR2EN_MASK (0x1ul << RCC_PLLCFGR_DIVR2EN_SHIFT) +#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_MASK + +#define RCC_PLLCFGR_DIVP3EN_SHIFT (22ul) +#define RCC_PLLCFGR_DIVP3EN_MASK (0x1ul << RCC_PLLCFGR_DIVP3EN_SHIFT) +#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_MASK +#define RCC_PLLCFGR_DIVQ3EN_SHIFT (23ul) +#define RCC_PLLCFGR_DIVQ3EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ3EN_SHIFT) +#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_MASK +#define RCC_PLLCFGR_DIVR3EN_SHIFT (24ul) +#define RCC_PLLCFGR_DIVR3EN_MASK (0x1ul << RCC_PLLCFGR_DIVR3EN_SHIFT) +#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_MASK + +/* Bit definitions for RCC_PLL1DIVR register */ + +#define RCC_PLL1DIVR_N1_SHIFT (0ul) +#define RCC_PLL1DIVR_N1(x) (((x) - 1) << RCC_PLL1DIVR_N1_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ +#define RCC_PLL1DIVR_P1_SHIFT (9ul) +#define RCC_PLL1DIVR_P1(x) (((x) - 1) << RCC_PLL1DIVR_P1_SHIFT) /* DIVP division factor: 2 - 128, must be even */ +#define RCC_PLL1DIVR_Q1_SHIFT (16ul) +#define RCC_PLL1DIVR_Q1(x) (((x) - 1) << RCC_PLL1DIVR_Q1_SHIFT) /* DIVQ division factor: 2 - 128 */ +#define RCC_PLL1DIVR_R1_SHIFT (24ul) +#define RCC_PLL1DIVR_R1(x) (((x) - 1) << RCC_PLL1DIVR_R1_SHIFT) /* DIVR division factor: 2 - 128 */ + +/* Bit definitions for RCC_PLL1FRACR register */ + +#define RCC_PLL1FRACR_FRACN1_SHIFT (3ul) +#define RCC_PLL1FRACR_FRACN1_MASK (0x1FFFul << RCC_PLL1FRACR_FRACN1_SHIFT) +#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_MASK + +/* Bit definitions for RCC_PLL2DIVR register */ + +#define RCC_PLL2DIVR_N2_SHIFT (0ul) +#define RCC_PLL2DIVR_N2(x) (((x) - 1) << RCC_PLL2DIVR_N2_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ +#define RCC_PLL2DIVR_P2_SHIFT (9ul) +#define RCC_PLL2DIVR_P2(x) (((x) - 1) << RCC_PLL2DIVR_P2_SHIFT) /* DIVP division factor: 2 - 128 */ +#define RCC_PLL2DIVR_Q2_SHIFT (16ul) +#define RCC_PLL2DIVR_Q2(x) (((x) - 1) << RCC_PLL2DIVR_Q2_SHIFT) /* DIVQ division factor: 2 - 128 */ +#define RCC_PLL2DIVR_R2_SHIFT (24ul) +#define RCC_PLL2DIVR_R2(x) (((x) - 1) << RCC_PLL2DIVR_R2_SHIFT) /* DIVR division factor: 2 - 128 */ + +/* Bit definitions for RCC_PLL2FRACR register */ + +#define RCC_PLL2FRACR_FRACN2_SHIFT (3ul) +#define RCC_PLL2FRACR_FRACN2_MASK (0x1FFFul << RCC_PLL2FRACR_FRACN2_SHIFT) +#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_MASK + +/* Bit definitions for RCC_PLL3DIVR register */ + +#define RCC_PLL3DIVR_N3_SHIFT (0ul) +#define RCC_PLL3DIVR_N3(x) (((x) - 1) << RCC_PLL3DIVR_N3_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ +#define RCC_PLL3DIVR_P3_SHIFT (9ul) +#define RCC_PLL3DIVR_P3(x) (((x) - 1) << RCC_PLL3DIVR_P3_SHIFT) /* DIVP division factor: 2 - 128 */ +#define RCC_PLL3DIVR_Q3_SHIFT (16ul) +#define RCC_PLL3DIVR_Q3(x) (((x) - 1) << RCC_PLL3DIVR_Q3_SHIFT) /* DIVQ division factor: 2 - 128 */ +#define RCC_PLL3DIVR_R3_SHIFT (24ul) +#define RCC_PLL3DIVR_R3(x) (((x) - 1) << RCC_PLL3DIVR_R3_SHIFT) /* DIVR division factor: 2 - 128 */ + +/* Bit definitions for RCC_PLL3FRACR register */ + +#define RCC_PLL3FRACR_FRACN3_SHIFT (3ul) +#define RCC_PLL3FRACR_FRACN3_MASK (0x1FFFul << RCC_PLL3FRACR_FRACN3_SHIFT) +#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_MASK + +/* Bit definitions for RCC_D1CCIPR register */ + +#define RCC_D1CCIPR_FMCSEL_SHIFT (0) /* Bits 0-1: */ +#define RCC_D1CCIPR_FMCSEL_MASK (3 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_HCLK (0 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_PLL1 (1 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_PLL2 (2 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_PER (3 << RCC_D1CCIPR_FMCSEL_SHIFT) + /* Bits 2-3: Reserved */ +#define RCC_D1CCIPR_QSPISEL_SHIFT (4) /* Bits 4-5: */ +#define RCC_D1CCIPR_QSPISEL_MASK (3 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_HCLK (0 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_PLL1 (1 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_PLL2 (2 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_PER (3 << RCC_D1CCIPR_QSPISEL_SHIFT) + /* Bits 6-15: Reserved */ +#define RCC_D1CCIPR_SDMMC_SHIFT (16) /* Bit 16: */ +#define RCC_D1CCIPR_SDMMC_MASK (1 << RCC_D1CCIPR_SDMMC_SHIFT) +# define RCC_D1CCIPR_SDMMC_PLL1 (0 << RCC_D1CCIPR_SDMMC_SHIFT) +# define RCC_D1CCIPR_SDMMC_PLL2 (1 << RCC_D1CCIPR_SDMMC_SHIFT) + /* Bits 17-27: Reserved */ +#define RCC_D1CCIPR_CKPERSEL_SHIFT (28) /* Bits 28-29: */ +#define RCC_D1CCIPR_CKPERSEL_MASK (3 << RCC_D1CCIPR_CKPERSEL_SHIFT) +# define RCC_D1CCIPR_CKPERSEL_HSI (0 << RCC_D1CCIPR_CKPERSEL_SHIFT) +# define RCC_D1CCIPR_CKPERSEL_CSI (1 << RCC_D1CCIPR_CKPERSEL_SHIFT) +# define RCC_D1CCIPR_CKPERSEL_HSE (2 << RCC_D1CCIPR_CKPERSEL_SHIFT) + /* Bits 30-31: Reserved */ + +/* Bit definitions for RCC_D2CCIP1R register */ + +#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */ +#define RCC_D2CCIP1R_SAI1SEL_MASK (7 << RCC_D2CCIP1R_SAI1SEL_MASK) +# define RCC_D2CCIP1R_SAI1SEL_PLL1 (0 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_PLL2 (1 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_PLL3 (2 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_PER (4 << RCC_D2CCIP1R_SAI1SEL_SHIFT) + /* Bits 3-5: Reserved */ +#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */ +#define RCC_D2CCIP1R_SAI23SEL_MASK (7 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PLL1 (0 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PLL2 (1 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PLL3 (2 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PER (4 << RCC_D2CCIP1R_SAI23SEL_SHIFT) + /* Bits 9-11: Reserved */ +#define RCC_D2CCIP1R_SPI123SEL_SHIFT (12) /* Bits 12-14 */ +#define RCC_D2CCIP1R_SPI123SEL_MASK (7 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PLL1 (0 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PLL2 (1 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PLL3 (2 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PER (4 << RCC_D2CCIP1R_SPI123SEL_SHIFT) + /* Bit 15: Reserved */ +#define RCC_D2CCIP1R_SPI45SEL_SHIFT (16) /* Bits 16-18 */ +#define RCC_D2CCIP1R_SPI45SEL_MASK (7 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_APB (0 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_PLL2 (1 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_PLL3 (2 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_HSI (3 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_CSI (4 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_HSE (5 << RCC_D2CCIP1R_SPI45SEL_SHIFT) + /* Bit 19: Reserved */ +#define RCC_D2CCIP1R_SPDIFSEL_SHIFT (20) /* Bits 20-21 */ +#define RCC_D2CCIP1R_SPDIFSEL_MASK (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_PLL1 (0 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_PLL2 (1 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_PLL3 (2 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_HSI (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) + /* Bits 22-23: Reserved */ +#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT (24) /* Bit 24 */ +#define RCC_D2CCIP1R_DFSDM1SEL_MASK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) +# define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 (0 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) +# define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) + /* Bits 25-27: Reserved */ +#define RCC_D2CCIP1R_FDCANSEL_SHIFT (28) /* Bits 28-29 */ +#define RCC_D2CCIP1R_FDCANSEL_MASK (3 << RCC_D2CCIP1R_FDCANSEL_SHIFT) +# define RCC_D2CCIP1R_FDCANSEL_HSE (0 << RCC_D2CCIP1R_FDCANSEL_SHIFT) +# define RCC_D2CCIP1R_FDCANSEL_PLL1 (1 << RCC_D2CCIP1R_FDCANSEL_SHIFT) +# define RCC_D2CCIP1R_FDCANSEL_PLL2 (2 << RCC_D2CCIP1R_FDCANSEL_SHIFT) + /* Bit 30: Reserved */ +#define RCC_D2CCIP1R_SWPSEL_SHIFT (31) /* Bit 31 */ +#define RCC_D2CCIP1R_SWPSEL_MASK (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) +# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) +# define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) + +/* Bit definitions for RCC_D2CCIP2R register */ + +#define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */ +# define RCC_D2CCIP2R_USART234578SEL_MASK (7 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_RCC (0 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_PLL2 (1 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_PLL3 (2 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_HSI (3 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_CSI (4 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_LSE (5 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +#define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */ +# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_RCC (0 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_PLL2 (1 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_PLL3 (2 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_HSI (3 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_CSI (4 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_LSE (5 << RCC_D2CCIP2R_USART16SEL_SHIFT) + /* Bits 6-7: Reserved */ +#define RCC_D2CCIP2R_RNGSEL_SHIFT (8) /* Bits 8-9 */ +# define RCC_D2CCIP2R_RNGSEL_MASK (3 << RCC_D2CCIP2R_RNGSEL_SHIFT) + /* Bits 10-11: Reserved */ +#define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */ +#define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) + /* Bits 14-19: Reserved */ +#define RCC_D2CCIP2R_USBSEL_SHIFT (20) /* Bits 20-21 */ +# define RCC_D2CCIP2R_USBSEL_MASK (3 << RCC_D2CCIP2R_USBSEL_SHIFT) +# define RCC_D2CCIP2R_USBSEL_DISABLE (0 << RCC_D2CCIP2R_USBSEL_SHIFT) +# define RCC_D2CCIP2R_USBSEL_PLL1 (1 << RCC_D2CCIP2R_USBSEL_SHIFT) +# define RCC_D2CCIP2R_USBSEL_PLL3 (2 << RCC_D2CCIP2R_USBSEL_SHIFT) +# define RCC_D2CCIP2R_USBSEL_HSI48 (3 << RCC_D2CCIP2R_USBSEL_SHIFT) +#define RCC_D2CCIP2R_CECSEL_SHIFT (22) /* Bits 22-23 */ +# define RCC_D2CCIP2R_CECSEL_MASK (3 << RCC_D2CCIP2R_CECSEL_SHIFT) + /* Bits 24-27: Reserved */ +#define RCC_D2CCIP2R_LPTIM1SEL_SHIFT (28) /* Bits 28-30 */ +# define RCC_D2CCIP2R_LPTIM1SEL_MASK (3 << RCC_D2CCIP2R_LPTIM1SEL_SHIFT) + /* Bit 31: Reserved */ + +/* Bit definitions for RCC_D3CCIPR register */ + +#define RCC_D3CCIPR_LPUART1SEL_SHIFT (0) /* Bits 0-2: LPUART1 kernel clock source selection */ +#define RCC_D3CCIPR_LPUART1SEL_MASK (7 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_PCLK (0 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_PLL2 (1 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_PLL3 (2 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_HSI (3 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_CSI (4 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_LSE (5 << RCC_D3CCIPR_LPUART1SEL_SHIFT) + /* Bits 3-7: Reserved */ +#define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9: I2C4 kernel clock source selection */ +#define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) +#define RCC_D3CCIPR_LPTIM2SEL_SHIFT (10) /* Bits 10-12: LPTIM2 kernel clock source selection */ +#define RCC_D3CCIPR_LPTIM2SEL_MASK (7 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_LSE (3 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_LSI (4 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PER (5 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +#define RCC_D3CCIPR_LPTIM345SEL_SHIFT (13) /* Bits 13-15: LPTIM3,4,5 kernel clock source selection */ +#define RCC_D3CCIPR_LPTIM345SEL_MASK (7 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_LSE (3 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_LSI (4 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PER (5 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +#define RCC_D3CCIPR_ADCSEL_SHIFT (16) /* Bits 16-17: SAR ADC kernel clock source selection */ +#define RCC_D3CCIPR_ADCSEL_MASK (3 << RCC_D3CCIPR_ADCSEL_SHIFT) +# define RCC_D3CCIPR_ADCSEL_PLL2 (0 << RCC_D3CCIPR_ADCSEL_SHIFT) +# define RCC_D3CCIPR_ADCSEL_PLL3 (1 << RCC_D3CCIPR_ADCSEL_SHIFT) +# define RCC_D3CCIPR_ADCSEL_PER (2 << RCC_D3CCIPR_ADCSEL_SHIFT) + /* Bits 18-20: Reserved */ +#define RCC_D3CCIPR_SAI4ASEL_SHIFT (21) /* Bits 21-23: Sub-Block A of SAI4 kernel clock source selection */ +#define RCC_D3CCIPR_SAI4ASEL_MASK (7 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PLL1 (0 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PLL2 (1 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PLL3 (2 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PER (4 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +#define RCC_D3CCIPR_SAI4BSEL_SHIFT (24) /* Bits 24-26: Sub-Block B of SAI4 kernel clock source selection */ +#define RCC_D3CCIPR_SAI4BSEL_MASK (7 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PLL1 (0 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PLL2 (1 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PLL3 (2 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PER (4 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +#define RCC_D3CCIPR_SPI6SEL_SHIFT (28) /* Bits 28-30: SPI6 kernel clock source selection */ +#define RCC_D3CCIPR_SPI6SEL_MASK (7 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_PCLK4 (0 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_PLL2 (1 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_PLL3 (2 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_HSI (3 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_CSI (4 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_HSE (5 << RCC_D3CCIPR_SPI6SEL_SHIFT) + /* Bit 31: Reserved */ + +/* TODO: CIER */ + +/* TODO: CIFR */ + +/* TODO: CICR */ + +/* TODO: BDCR */ + +/* Bit definitions for RCC_CSR register */ + +#define RCC_CSR_LSION (1 << 0) /* RCC CSR: LSION */ +#define RCC_CSR_LSIRDY (1 << 1) /* RCC CSR: LSIRDY */ + +/* AHB3 peripheral reset register */ + +#define RCC_AHB3RSTR_MDMARST (1 << 0) /* RCC AHB3RSTR: MDMARST */ +#define RCC_AHB3RSTR_DMA2DRST (1 << 4) /* RCC AHB3RSTR: DMA2DRST */ +#define RCC_AHB3RSTR_JPGDECRST (1 << 5) /* RCC AHB3RSTR: JPGDECRST */ +#define RCC_AHB3RSTR_FMCRST (1 << 12) /* RCC AHB3RSTR: FMCRST */ +#define RCC_AHB3RSTR_QSPIRST (1 << 14) /* RCC AHB3RSTR: QSPIRST */ +#define RCC_AHB3RSTR_SDMMC1RST (1 << 16) /* RCC AHB3RSTR: SDMMC1RST */ +#define RCC_AHB3RSTR_CPURST (1 << 31) /* RCC AHB3RSTR: CPURST */ + +/* AHB1 peripheral reset register */ + +#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* RCC AHB1RSTR: DMA1RST */ +#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* RCC AHB1RSTR: DMA2RST */ +#define RCC_AHB1RSTR_ADC12RST (1 << 5) /* RCC AHB1RSTR: ADC12RST */ + /* Bits 6-14: Reserved */ +#define RCC_AHB1RSTR_ETH1MACRST (1 << 15) /* RCC AHB1RSTR: ETH1MACRST */ + /* Bits 16-24: Reserved */ +#define RCC_AHB1RSTR_OTGHSRST (1 << 25) /* RCC AHB1RSTR: OTGHSRST */ + /* Bit 26: Reserved */ +#define RCC_AHB1RSTR_OTGFSRST (1 << 27) /* RCC AHB1RSTR: OTGFSRST */ + /* Bits 28-31: Reserved */ + +/* AHB2 peripheral reset register */ + +#define RCC_AHB2RSTR_CAMITFRST (1 << 0) /* RCC AHB2RSTR: CAMITFRST */ + /* Bits 1-3: Reserved */ +#define RCC_AHB2RSTR_CRYPTRST (1 << 4) /* RCC AHB2RSTR: CRYPTRST */ +#define RCC_AHB2RSTR_HASHRST (1 << 5) /* RCC AHB2RSTR: HASHRST */ +#define RCC_AHB2RSTR_RNGRST (1 << 6) /* RCC AHB2RSTR: RNGRST */ + /* Bits 7-8: Reserved */ +#define RCC_AHB2RSTR_SDMMC2RST (1 << 9) /* RCC AHB2RSTR: SDMMC2RST */ + /* Bits 10-31: Reserved */ + +/* AHB4 peripheral reset register */ + +#define RCC_AHB4RSTR_GPIOARST (1 << 0) /* RCC AHB4RSTR: GPIOARST */ +#define RCC_AHB4RSTR_GPIOBRST (1 << 1) /* RCC AHB4RSTR: GPIOBRST */ +#define RCC_AHB4RSTR_GPIOCRST (1 << 2) /* RCC AHB4RSTR: GPIOCRST */ +#define RCC_AHB4RSTR_GPIODRST (1 << 3) /* RCC AHB4RSTR: GPIODRST */ +#define RCC_AHB4RSTR_GPIOERST (1 << 4) /* RCC AHB4RSTR: GPIOERST */ +#define RCC_AHB4RSTR_GPIOFRST (1 << 5) /* RCC AHB4RSTR: GPIOFRST */ +#define RCC_AHB4RSTR_GPIOGRST (1 << 6) /* RCC AHB4RSTR: GPIOGRST */ +#define RCC_AHB4RSTR_GPIOHRST (1 << 7) /* RCC AHB4RSTR: GPIOHRST */ +#define RCC_AHB4RSTR_GPIOIRST (1 << 8) /* RCC AHB4RSTR: GPIOIRST */ +#define RCC_AHB4RSTR_GPIOJRST (1 << 9) /* RCC AHB4RSTR: GPIOJRST */ +#define RCC_AHB4RSTR_GPIOKRST (1 << 10) /* RCC AHB4RSTR: GPIOKRST */ + /* Bits 11-18: Reserved */ +#define RCC_AHB4RSTR_CRCRST (1 << 19) /* RCC AHB4RSTR: CRCRST */ + /* Bit 20: Reserved */ +#define RCC_AHB4RSTR_BDMARST (1 << 21) /* RCC AHB4RSTR: BDMARST */ + /* Bits 22-23: Reserved */ +#define RCC_AHB4RSTR_ADC3RST (1 << 24) /* RCC AHB4RSTR: ADC3RST */ +#define RCC_AHB4RSTR_HSEMRST (1 << 25) /* RCC AHB4RSTR: HSEMRST */ + /* Bits 26-31: Reserved */ + +/* APB3 peripheral reset register */ + + /* Bits 0-2: Reserved */ +#define RCC_APB3RSTR_LTDCRST (1 << 3) /* RCC APB3RSTR: LTDCRST */ + /* Bits 4-31: Reserved */ + +/* APB3 L peripheral reset register */ + +#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* RCC APB1LRSTR: TIM2RST */ +#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* RCC APB1LRSTR: TIM3RST */ +#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* RCC APB1LRSTR: TIM4RST */ +#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* RCC APB1LRSTR: TIM5RST */ +#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* RCC APB1LRSTR: TIM6RST */ +#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* RCC APB1LRSTR: TIM7RST */ +#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* RCC APB1LRSTR: TIM12RST */ +#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* RCC APB1LRSTR: TIM13RST */ +#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* RCC APB1LRSTR: TIM14RST */ +#define RCC_APB1LRSTR_LPTIM1RST (1 << 9) /* RCC APB1LRSTR: LPTIM1RST */ + /* Bits 10-13: Reserved */ +#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* RCC APB1LRSTR: SPI2RST */ +#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* RCC APB1LRSTR: SPI3RST */ +#define RCC_APB1LRSTR_SPDIFRXRST (1 << 16) /* RCC APB1LRSTR: SPDIFRXRST */ +#define RCC_APB1LRSTR_USART2RST (1 << 17) /* RCC APB1LRSTR: USART2RST */ +#define RCC_APB1LRSTR_USART3RST (1 << 18) /* RCC APB1LRSTR: USART3RST */ +#define RCC_APB1LRSTR_UART4RST (1 << 19) /* RCC APB1LRSTR: UART4RST */ +#define RCC_APB1LRSTR_UART5RST (1 << 20) /* RCC APB1LRSTR: UART5RST */ +#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* RCC APB1LRSTR: I2C1RST */ +#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* RCC APB1LRSTR: I2C2RST */ +#define RCC_APB1LRSTR_I2C3RST (1 << 23) /* RCC APB1LRSTR: I2C3RST */ + /* Bits 24-26: Reserved */ +#define RCC_APB1LRSTR_HDMICECRST (1 << 27) /* RCC APB1LRSTR: HDMICECRST */ + /* Bit 28: Reserved */ +#define RCC_APB1LRSTR_DAC1RST (1 << 29) /* RCC APB1LRSTR: DAC1RST */ +#define RCC_APB1LRSTR_UART7RST (1 << 30) /* RCC APB1LRSTR: UART7RST */ +#define RCC_APB1LRSTR_UART8RST (1 << 31) /* RCC APB1LRSTR: UART8RST */ + +/* APB1 H peripheral reset register */ + + /* Bit 0: Reserved */ +#define RCC_APB1HRSTR_CRSRST (1 << 1) /* RCC APB1HRSTR: CRSRST */ +#define RCC_APB1HRSTR_SWPRST (1 << 2) /* RCC APB1HRSTR: SWPRST */ + +/* Bit 3: Reserved */ + +#define RCC_APB1HRSTR_OPAMPRST (1 << 4) /* RCC APB1HRSTR: OPAMPRST*/ +#define RCC_APB1HRSTR_MDIOSRST (1 << 5) /* RCC APB1HRSTR: MDIOSRST */ + /* Bits 6-7: Reserved */ +#define RCC_APB1HRSTR_FDCANRST (1 << 8) /* RCC APB1HRSTR: FDCANRST*/ + +/* Bits 9-31: Reserved */ + +/* APB2 peripheral reset register */ + +#define RCC_APB2RSTR_TIM1RST (1 << 0) /* RCC APB2RSTR: TIM1RST */ +#define RCC_APB2RSTR_TIM8RST (1 << 1) /* RCC APB2RSTR: TIM8RST */ +#define RCC_APB2RSTR_USART1RST (1 << 4) /* RCC APB2RSTR: USART1RST */ +#define RCC_APB2RSTR_USART6RST (1 << 5) /* RCC APB2RSTR: USART6RST */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* RCC APB2RSTR: SPI1RST */ +#define RCC_APB2RSTR_SPI4RST (1 << 13) /* RCC APB2RSTR: SPI4RST */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* RCC APB2RSTR: TIM15RST */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* RCC APB2RSTR: TIM16RST */ +#define RCC_APB2RSTR_TIM17RST (1 << 18) /* RCC APB2RSTR: TIM17RST */ +#define RCC_APB2RSTR_SPI5RST (1 << 20) /* RCC APB2RSTR: SPI5RST */ +#define RCC_APB2RSTR_SAI1RST (1 << 22) /* RCC APB2RSTR: SAI1RST */ +#define RCC_APB2RSTR_SAI2RST (1 << 23) /* RCC APB2RSTR: SAI2RST */ +#define RCC_APB2RSTR_SAI3RST (1 << 24) /* RCC APB2RSTR: SAI3RST */ +#define RCC_APB2RSTR_DFSDM1RST (1 << 28) /* RCC APB2RSTR: DFSDM1RST */ +#define RCC_APB2RSTR_HRTIMRST (1 << 29) /* RCC APB2RSTR: HRTIMRST */ + +/* APB4 peripheral reset register */ + +#define RCC_APB4RSTR_SYSCFGRST (1 << 1) /* RCC APB4RSTR: SYSCFGRST */ +#define RCC_APB4RSTR_LPUART1RST (1 << 3) /* RCC APB4RSTR: LPUART1RST */ +#define RCC_APB4RSTR_SPI6RST (1 << 5) /* RCC APB4RSTR: SPI6RST */ +#define RCC_APB4RSTR_I2C4RST (1 << 7) /* RCC APB4RSTR: I2C4RST */ +#define RCC_APB4RSTR_LPTIM2RST (1 << 9) /* RCC APB4RSTR: LPTIM2RST */ +#define RCC_APB4RSTR_LPTIM3RST (1 << 10) /* RCC APB4RSTR: LPTIM3RST */ +#define RCC_APB4RSTR_LPTIM4RST (1 << 11) /* RCC APB4RSTR: LPTIM4RST */ +#define RCC_APB4RSTR_LPTIM5RST (1 << 12) /* RCC APB4RSTR: LPTIM5RST */ +#define RCC_APB4RSTR_COMP12RST (1 << 14) /* RCC APB4RSTR: COMP12RST */ +#define RCC_APB4RSTR_VREFRST (1 << 15) /* RCC APB4RSTR: VREFRST */ +#define RCC_APB4RSTR_SAI4RST (1 << 21) /* RCC APB4RSTR: SAI4RST */ + +/* RCC Global Control register */ + +#define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ +#ifdef CONFIG_STM32_HAVE_CM4 +# define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */ +#endif +#ifdef CONFIG_STM32_HAVE_CM4 +# define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */ +# define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */ #endif +/* TODO: D3 Autonomous mode register */ + +/* RCC Reset Status register */ + + /* Bits 0-15: Reserved */ +#define RCC_RSR_RMVF (1 << 16) /* Bit 16: Remove reset flag */ +#define RCC_RSR_CPURSTF (1 << 17) /* Bit 17: CPU reset flag */ + /* Bit 18: Reserved */ +#define RCC_RSR_D1RSTF (1 << 19) /* Bit 19: D1 domain power switch reset flag */ +#define RCC_RSR_D2RSTF (1 << 20) /* Bit 20: D2 domain power switch reset flag */ +#define RCC_RSR_BORRSTF (1 << 21) /* Bit 21: BOR reset flag */ +#define RCC_RSR_PINRSTF (1 << 22) /* Bit 22: Pin reset flag */ +#define RCC_RSR_PORRSTF (1 << 23) /* Bit 23: POR/PDR reset flag */ +#define RCC_RSR_SFTRSTF (1 << 24) /* Bit 24: System reset from CPU flag */ + /* Bit 25: Reserved */ +#define RCC_RSR_IWDG1RSTF (1 << 26) /* Bit 26: Independent watchdog reset flag */ + /* Bit 27: Reserved */ +#define RCC_RSR_WWDG1RSTF (1 << 28) /* Bit 28: Window watchdog reset flag */ + /* Bit 29: Reserved */ +#define RCC_RSR_LPWRRSTF (1 << 30) /* Bit 30: Reset due to illegal D1 DStandby or CPU Cstop flag */ + /* Bit 31: Reserved */ + +/* AHB3 Peripheral Clock enable register */ + +#define RCC_AHB3ENR_MDMAEN (1 << 0) /* RCC AHB3ENR: MDMAEN */ +#define RCC_AHB3ENR_DMA2DEN (1 << 4) /* RCC AHB3ENR: DMA2DEN */ +#define RCC_AHB3ENR_JPGDECEN (1 << 5) /* RCC AHB3ENR: JPGDECEN */ +#define RCC_AHB3ENR_FMCEN (1 << 12) /* RCC AHB3ENR: FMCEN */ +#define RCC_AHB3ENR_QSPIEN (1 << 14) /* RCC AHB3ENR: QSPIEN */ +#define RCC_AHB3ENR_SDMMC1EN (1 << 16) /* RCC AHB3ENR: SDMMC1EN */ + +/* AHB1 Peripheral Clock enable register */ + +#define RCC_AHB1ENR_DMA1EN (1 << 0) /* RCC AHB1ENR: DMA1EN */ +#define RCC_AHB1ENR_DMA2EN (1 << 1) /* RCC AHB1ENR: DMA2EN */ +#define RCC_AHB1ENR_ADC12EN (1 << 5) /* RCC AHB1ENR: ADC12EN */ +#define RCC_AHB1ENR_ETH1MACEN (1 << 15) /* RCC AHB1ENR: ETH1MACEN */ +#define RCC_AHB1ENR_ETH1TXEN (1 << 16) /* RCC AHB1ENR: ETH1TXEN */ +#define RCC_AHB1ENR_ETH1RXEN (1 << 17) /* RCC AHB1ENR: ETH1RXEN */ +#define RCC_AHB1ENR_OTGHSEN (1 << 25) /* RCC AHB1ENR: OTGHSEN */ +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 26) /* RCC AHB1ENR: OTGHSULPIEN */ +#define RCC_AHB1ENR_OTGFSEN (1 << 27) /* RCC AHB1ENR: OTGFSEN */ + +/* AHB2 Peripheral Clock enable register */ + +#define RCC_AHB2ENR_CAMITFEN (1 << 0) /* RCC AHB2ENR: CAMITFEN */ +#define RCC_AHB2ENR_CRYPTEN (1 << 4) /* RCC AHB2ENR: CRYPTEN */ +#define RCC_AHB2ENR_HASHEN (1 << 5) /* RCC AHB2ENR: HASHEN */ +#define RCC_AHB2ENR_RNGEN (1 << 6) /* RCC AHB2ENR: RNGEN */ +#define RCC_AHB2ENR_SDMMC2EN (1 << 9) /* RCC AHB2ENR: SDMMC2EN */ +#define RCC_AHB2ENR_SRAM1EN (1 << 29) /* RCC AHB2ENR: SRAM1EN */ +#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* RCC AHB2ENR: SRAM2EN */ +#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* RCC AHB2ENR: SRAM3EN */ + +/* AHB4 Peripheral Clock enable register */ + +#define RCC_AHB4ENR_GPIOAEN (1 << 0) /* RCC AHB4ENR: GPIOAEN */ +#define RCC_AHB4ENR_GPIOBEN (1 << 1) /* RCC AHB4ENR: GPIOBEN */ +#define RCC_AHB4ENR_GPIOCEN (1 << 2) /* RCC AHB4ENR: GPIOCEN */ +#define RCC_AHB4ENR_GPIODEN (1 << 3) /* RCC AHB4ENR: GPIODEN */ +#define RCC_AHB4ENR_GPIOEEN (1 << 4) /* RCC AHB4ENR: GPIOEEN */ +#define RCC_AHB4ENR_GPIOFEN (1 << 5) /* RCC AHB4ENR: GPIOFEN */ +#define RCC_AHB4ENR_GPIOGEN (1 << 6) /* RCC AHB4ENR: GPIOGEN */ +#define RCC_AHB4ENR_GPIOHEN (1 << 7) /* RCC AHB4ENR: GPIOHEN */ +#define RCC_AHB4ENR_GPIOIEN (1 << 8) /* RCC AHB4ENR: GPIOIEN */ +#define RCC_AHB4ENR_GPIOJEN (1 << 9) /* RCC AHB4ENR: GPIOJEN */ +#define RCC_AHB4ENR_GPIOKEN (1 << 10) /* RCC AHB4ENR: GPIOKEN */ +#define RCC_AHB4ENR_CRCEN (1 << 19) /* RCC AHB4ENR: CRCEN */ +#define RCC_AHB4ENR_BDMAEN (1 << 21) /* RCC AHB4ENR: BDMAEN and DMAMUX2 */ +#define RCC_AHB4ENR_ADC3EN (1 << 24) /* RCC AHB4ENR: ADC3EN */ +#define RCC_AHB4ENR_HSEMEN (1 << 25) /* RCC AHB4ENR: HSEMEN */ +#define RCC_AHB4ENR_BKPSRAMEN (1 << 28) /* RCC AHB4ENR: BKPRAMEN */ + +/* APB3 Peripheral Clock enable register */ + +#define RCC_APB3ENR_LTDCEN (1 << 3) /* RCC APB3ENR: LTDCEN */ +#define RCC_APB3ENR_WWDG1EN (1 << 6) /* RCC APB3ENR: WWDG1EN */ + +/* APB1 L Peripheral Clock enable register */ + +#define RCC_APB1LENR_TIM2EN (1 << 0) /* RCC APB1LENR: TIM2EN */ +#define RCC_APB1LENR_TIM3EN (1 << 1) /* RCC APB1LENR: TIM3EN */ +#define RCC_APB1LENR_TIM4EN (1 << 2) /* RCC APB1LENR: TIM4EN */ +#define RCC_APB1LENR_TIM5EN (1 << 3) /* RCC APB1LENR: TIM5EN */ +#define RCC_APB1LENR_TIM6EN (1 << 4) /* RCC APB1LENR: TIM6EN */ +#define RCC_APB1LENR_TIM7EN (1 << 5) /* RCC APB1LENR: TIM7EN */ +#define RCC_APB1LENR_TIM12EN (1 << 6) /* RCC APB1LENR: TIM12EN */ +#define RCC_APB1LENR_TIM13EN (1 << 7) /* RCC APB1LENR: TIM13EN */ +#define RCC_APB1LENR_TIM14EN (1 << 8) /* RCC APB1LENR: TIM14EN */ +#define RCC_APB1LENR_LPTIM1EN (1 << 9) /* RCC APB1LENR: LPTIM1EN */ + /* Bits 10-13: Reserved */ +#define RCC_APB1LENR_SPI2EN (1 << 14) /* RCC APB1LENR: SPI2EN */ +#define RCC_APB1LENR_SPI3EN (1 << 15) /* RCC APB1LENR: SPI3EN */ +#define RCC_APB1LENR_SPDIFRXEN (1 << 16) /* RCC APB1LENR: SPDIFRXEN */ +#define RCC_APB1LENR_USART2EN (1 << 17) /* RCC APB1LENR: USART2EN */ +#define RCC_APB1LENR_USART3EN (1 << 18) /* RCC APB1LENR: USART3EN */ +#define RCC_APB1LENR_UART4EN (1 << 19) /* RCC APB1LENR: UART4EN */ +#define RCC_APB1LENR_UART5EN (1 << 20) /* RCC APB1LENR: UART5EN */ +#define RCC_APB1LENR_I2C1EN (1 << 21) /* RCC APB1LENR: I2C1EN */ +#define RCC_APB1LENR_I2C2EN (1 << 22) /* RCC APB1LENR: I2C2EN */ +#define RCC_APB1LENR_I2C3EN (1 << 23) /* RCC APB1LENR: I2C3EN */ + /* Bits 24-25: Reserved */ +#define RCC_APB1LENR_HDMICECEN (1 << 27) /* RCC APB1LENR: HDMICECEN */ + /* Bit 28: Reserved */ +#define RCC_APB1LENR_DAC1EN (1 << 29) /* RCC APB1LENR: DAC1EN */ +#define RCC_APB1LENR_UART7EN (1 << 30) /* RCC APB1LENR: UART7EN */ +#define RCC_APB1LENR_UART8EN (1 << 31) /* RCC APB1LENR: UART8EN */ + +/* APB1 H Peripheral Clock enable register */ + + /* Bit 0: Reserved */ +#define RCC_APB1HENR_CRSEN (1 << 1) /* RCC APB1HENR: CRSEN */ +#define RCC_APB1HENR_SWPEN (1 << 2) /* RCC APB1HENR: SWPEN */ + /* Bit 3: Reserved */ +#define RCC_APB1HENR_OPAMPEN (1 << 4) /* RCC APB1HENR: OPAMPEN */ +#define RCC_APB1HENR_MDIOSEN (1 << 5) /* RCC APB1HENR: MDIOSEN */ + /* Bits 6-7: Reserved */ +#define RCC_APB1HENR_FDCANEN (1 << 8) /* RCC APB1HENR: FDCANEN */ + /* Bits 9-31: Reserved */ + +/* APB2 Peripheral Clock enable register */ + +#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: RCC APB2ENR: TIM1EN */ +#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: RCC APB2ENR: TIM8EN */ + /* Bits 2-3: Reserved */ +#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: RCC APB2ENR: USART1EN */ +#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: RCC APB2ENR: USART6EN */ + /* Bits 6-11: Reserved */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: RCC APB2ENR: SPI1EN */ +#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: RCC APB2ENR: SPI4EN */ + /* Bits 14-15: Reserved */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: RCC APB2ENR: TIM15EN */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: RCC APB2ENR: TIM16EN */ +#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: RCC APB2ENR: TIM17EN */ +#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: RCC APB2ENR: SPI5EN */ + /* Bit 21: Reserved */ +#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: RCC APB2ENR: SAI1EN */ +#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: RCC APB2ENR: SAI2EN */ +#define RCC_APB2ENR_SAI3EN (1 << 24) /* Bit 24: RCC APB2ENR: SAI3EN */ + /* Bits 25-27: Reserved */ +#define RCC_APB2ENR_DFSDM1EN (1 << 28) /* Bit 28: RCC APB2ENR: DFSDM1EN */ +#define RCC_APB2ENR_HRTIMEN (1 << 29) /* Bit 29: RCC APB2ENR: HRTIMEN */ + /* Bits 30-31: Reserved */ + +/* APB4 Peripheral Clock enable register */ + + /* Bit 0: Reserved */ +#define RCC_APB4ENR_SYSCFGEN (1 << 1) /* Bit 1: RCC APB4ENR: SYSCFGEN */ + /* Bit 2: Reserved */ +#define RCC_APB4ENR_LPUART1EN (1 << 3) /* Bit 3: RCC APB4ENR: LPUART1EN */ + /* Bit 4: Reserved */ +#define RCC_APB4ENR_SPI6EN (1 << 5) /* Bit 5: RCC APB4ENR: SPI6EN */ + /* Bit 6: Reserved */ +#define RCC_APB4ENR_I2C4EN (1 << 7) /* Bit 7: RCC APB4ENR: I2C4EN */ + /* Bit 8: Reserved */ +#define RCC_APB4ENR_LPTIM2EN (1 << 9) /* Bit 9: RCC APB4ENR: LPTIM2EN */ +#define RCC_APB4ENR_LPTIM3EN (1 << 10) /* Bit 10: RCC APB4ENR: LPTIM3EN */ +#define RCC_APB4ENR_LPTIM4EN (1 << 11) /* Bit 11: RCC APB4ENR: LPTIM4EN */ +#define RCC_APB4ENR_LPTIM5EN (1 << 12) /* Bit 12: RCC APB4ENR: LPTIM5EN */ + /* Bit 13: Reserved */ +#define RCC_APB4ENR_COMP12EN (1 << 14) /* Bit 14: RCC APB4ENR: COMP12EN */ +#define RCC_APB4ENR_VREFEN (1 << 15) /* Bit 15: RCC APB4ENR: VREFEN */ +#define RCC_APB4ENR_RTCAPBEN (1 << 16) /* Bit 16: RCC APB4ENR: RTCAPBEN */ + /* Bits 17-20: Reserved */ +#define RCC_APB4ENR_SAI4EN (1 << 21) /* Bit 21: RCC APB4ENR: SAI4EN */ + /* Bit2 22-31: Reserved */ + +/* AHB3 low power mode peripheral clock enable register */ + +#define RCC_AHB3LPENR_MDMALPEN (1 << 0) /* RCC AHB3LPENR: MDMALPEN */ +#define RCC_AHB3LPENR_DMA2DLPEN (1 << 4) /* RCC AHB3LPENR: DMA2DLPEN */ +#define RCC_AHB3LPENR_JPGDECLPEN (1 << 5) /* RCC AHB3LPENR: JPGDECLPEN */ +#define RCC_AHB3LPENR_FLITFLPEN (1 << 8) /* RCC AHB3LPENR: FLITFLPEN */ +#define RCC_AHB3LPENR_FMCLPEN (1 << 12) /* RCC AHB3LPENR: FMCLPEN */ +#define RCC_AHB3LPENR_QSPILPEN (1 << 14) /* RCC AHB3LPENR: QSPILPEN */ +#define RCC_AHB3LPENR_SDMMC1LPEN (1 << 16) /* RCC AHB3LPENR: SDMMC1LPEN */ +#define RCC_AHB3LPENR_D1DTCM1LPEN (1 << 28) /* RCC AHB3LPENR: D1DTCM1LPEN */ +#define RCC_AHB3LPENR_DTCM2LPEN (1 << 29) /* RCC AHB3LPENR: DTCM2LPEN */ +#define RCC_AHB3LPENR_ITCMLPEN (1 << 30) /* RCC AHB3LPENR: ITCMLPEN */ +#define RCC_AHB3LPENR_AXISRAMLPEN (1 << 31) /* RCC AHB3LPENR: AXISRAMLPEN */ + +/* AHB1 low power mode peripheral clock enable register */ + +#define RCC_AHB1LPENR_DMA1LPEN (1 << 0) /* RCC AHB1LPENR: DMA1LPEN */ +#define RCC_AHB1LPENR_DMA2LPEN (1 << 1) /* RCC AHB1LPENR: DMA2LPEN */ +#define RCC_AHB1LPENR_ADC12LPEN (1 << 5) /* RCC AHB1LPENR: ADC12LPEN */ +#define RCC_AHB1LPENR_ETH1MACLPEN (1 << 15) /* RCC AHB1LPENR: ETH1MACLPEN */ +#define RCC_AHB1LPENR_ETH1TXLPEN (1 << 16) /* RCC AHB1LPENR: ETH1TXLPEN */ +#define RCC_AHB1LPENR_ETH1RXLPEN (1 << 17) /* RCC AHB1LPENR: ETH1RXLPEN */ +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 25) /* RCC AHB1LPENR: OTGHSLPEN */ +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 26) /* RCC AHB1LPENR: OTGHSULPILPEN */ +#define RCC_AHB1LPENR_OTGFSLPEN (1 << 27) /* RCC AHB1LPENR: OTGFSLPEN */ + +/* AHB2 low power mode peripheral clock enable register */ + +#define RCC_AHB2LPENR_CAMITFLPEN (1 << 0) /* RCC AHB2LPENR: CAMITFLPEN */ +#define RCC_AHB2LPENR_CRYPTLPEN (1 << 4) /* RCC AHB2LPENR: CRYPTLPEN */ +#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* RCC AHB2LPENR: HASHLPEN */ +#define RCC_AHB2LPENR_SDMMC2LPEN (1 << 6) /* RCC AHB2LPENR: SDMMC2LPEN */ +#define RCC_AHB2LPENR_RNGLPEN (1 << 9) /* RCC AHB2LPENR: RNGLPEN */ +#define RCC_AHB2LPENR_SRAM1LPEN (1 << 29) /* RCC AHB2LPENR: SRAM1LPEN */ +#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* RCC AHB2LPENR: SRAM2LPEN */ +#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* RCC AHB2LPENR: SRAM3LPEN */ + +/* AHB4 low power mode peripheral clock enable register */ + +#define RCC_AHB4LPENR_GPIOALPEN (1 << 0) /* RCC AHB4LPENR: GPIOALPEN */ +#define RCC_AHB4LPENR_GPIOBLPEN (1 << 1) /* RCC AHB4LPENR: GPIOBLPEN */ +#define RCC_AHB4LPENR_GPIOCLPEN (1 << 2) /* RCC AHB4LPENR: GPIOCLPEN */ +#define RCC_AHB4LPENR_GPIODLPEN (1 << 3) /* RCC AHB4LPENR: GPIODLPEN */ +#define RCC_AHB4LPENR_GPIOELPEN (1 << 4) /* RCC AHB4LPENR: GPIOELPEN */ +#define RCC_AHB4LPENR_GPIOFLPEN (1 << 5) /* RCC AHB4LPENR: GPIOFLPEN */ +#define RCC_AHB4LPENR_GPIOGLPEN (1 << 6) /* RCC AHB4LPENR: GPIOGLPEN */ +#define RCC_AHB4LPENR_GPIOHLPEN (1 << 7) /* RCC AHB4LPENR: GPIOHLPEN */ +#define RCC_AHB4LPENR_GPIOILPEN (1 << 8) /* RCC AHB4LPENR: GPIOILPEN */ +#define RCC_AHB4LPENR_GPIOJLPEN (1 << 9) /* RCC AHB4LPENR: GPIOJLPEN */ +#define RCC_AHB4LPENR_GPIOKLPEN (1 << 10) /* RCC AHB4LPENR: GPIOKLPEN */ +#define RCC_AHB4LPENR_CRCLPEN (1 << 19) /* RCC AHB4LPENR: CRCLPEN */ +#define RCC_AHB4LPENR_BDMALPEN (1 << 21) /* RCC AHB4LPENR: BDMALPEN */ +#define RCC_AHB4LPENR_ADC3LPEN (1 << 24) /* RCC AHB4LPENR: ADC3LPEN */ +#define RCC_AHB4LPENR_BKPRAMLPEN (1 << 28) /* RCC AHB4LPENR: BKPRAMLPEN */ +#define RCC_AHB4LPENR_SRAM4LPEN (1 << 29) /* RCC AHB4LPENR: SRAM4LPEN */ + +/* APB3 low power mode peripheral clock enable register */ + +#define RCC_APB3LPENR_LTDCLPEN (1 << 3) /* RCC APB3LPENR: LTDCLPEN */ +#define RCC_APB3LPENR_WWDG1LPEN (1 << 6) /* RCC APB3LPENR: WWDG1LPEN */ + +/* APB1 L low power mode peripheral clock enable register */ + +#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* RCC APB1LLPENR: TIM2LPEN */ +#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* RCC APB1LLPENR: TIM3LPEN */ +#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* RCC APB1LLPENR: TIM4LPEN */ +#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* RCC APB1LLPENR: TIM5LPEN */ +#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* RCC APB1LLPENR: TIM6LPEN */ +#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* RCC APB1LLPENR: TIM7LPEN */ +#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* RCC APB1LLPENR: TIM12LPEN */ +#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* RCC APB1LLPENR: TIM13LPEN */ +#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* RCC APB1LLPENR: TIM14LPEN */ +#define RCC_APB1LLPENR_LPTIM1LPEN (1 << 9) /* RCC APB1LLPENR: LPTIM1LPEN */ +#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* RCC APB1LLPENR: SPI2LPEN */ +#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* RCC APB1LLPENR: SPI3LPEN */ +#define RCC_APB1LLPENR_SPDIFRXLPEN (1 << 16) /* RCC APB1LLPENR: SPDIFRXLPEN */ +#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* RCC APB1LLPENR: USART2LPEN */ +#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* RCC APB1LLPENR: USART3LPEN */ +#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* RCC APB1LLPENR: UART4LPEN */ +#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* RCC APB1LLPENR: UART5LPEN */ +#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* RCC APB1LLPENR: I2C1LPEN */ +#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* RCC APB1LLPENR: I2C2LPEN */ +#define RCC_APB1LLPENR_I2C3LPEN (1 << 23) /* RCC APB1LLPENR: I2C3LPEN */ +#define RCC_APB1LLPENR_HDMICECLPEN (1 << 27) /* RCC APB1LLPENR: HDMICECLPEN */ +#define RCC_APB1LLPENR_DAC1LPEN (1 << 29) /* RCC APB1LLPENR: DAC1LPEN */ +#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* RCC APB1LLPENR: UART7LPEN */ +#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* RCC APB1LLPENR: UART8LPEN */ + +/* APB1 H low power mode peripheral clock enable register */ + +#define RCC_APB1HLPENR_CRSLPEN (1 << 1) /* RCC APB1HLPENR: CRSLPEN */ +#define RCC_APB1HLPENR_SWPLPEN (1 << 2) /* RCC APB1HLPENR: SWPLPEN */ +#define RCC_APB1HLPENR_OPAMPLPEN (1 << 4) /* RCC APB1HLPENR: OPAMPLPEN */ +#define RCC_APB1HLPENR_MDIOSLPEN (1 << 5) /* RCC APB1HLPENR: MDIOSLPEN */ +#define RCC_APB1HLPENR_FDCANLPEN (1 << 8) /* RCC APB1HLPENR: FDCANLPEN */ + +/* APB2 low power mode peripheral clock enable register */ + +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* RCC APB2LPENR: TIM1LPEN */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* RCC APB2LPENR: TIM8LPEN */ +#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* RCC APB2LPENR: USART1LPEN */ +#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* RCC APB2LPENR: USART6LPEN */ +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* RCC APB2LPENR: SPI1LPEN */ +#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* RCC APB2LPENR: SPI4LPEN */ +#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* RCC APB2LPENR: TIM15LPEN */ +#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* RCC APB2LPENR: TIM16LPEN */ +#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* RCC APB2LPENR: TIM17LPEN */ +#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* RCC APB2LPENR: SPI5LPEN */ +#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* RCC APB2LPENR: SAI1LPEN */ +#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* RCC APB2LPENR: SAI2LPEN */ +#define RCC_APB2LPENR_SAI3LPEN (1 << 24) /* RCC APB2LPENR: SAI3LPEN */ +#define RCC_APB2LPENR_DFSDM1LPEN (1 << 28) /* RCC APB2LPENR: DFSDM1LPEN */ +#define RCC_APB2LPENR_HRTIMLPEN (1 << 29) /* RCC APB2LPENR: HRTIMLPEN */ + +/* APB4 low power mode peripheral clock enable register */ + +#define RCC_APB4LPENR_SYSCFGLPEN (1 << 1) /* RCC APB4LPENR: SYSCFGLPEN */ +#define RCC_APB4LPENR_LPUART1LPEN (1 << 3) /* RCC APB4LPENR: LPUART1LPEN */ +#define RCC_APB4LPENR_SPI6LPEN (1 << 5) /* RCC APB4LPENR: SPI6LPEN */ +#define RCC_APB4LPENR_I2C4LPEN (1 << 7) /* RCC APB4LPENR: I2C4LPEN */ +#define RCC_APB4LPENR_LPTIM2LPEN (1 << 9) /* RCC APB4LPENR: LPTIM2LPEN */ +#define RCC_APB4LPENR_LPTIM3LPEN (1 << 10) /* RCC APB4LPENR: LPTIM3LPEN */ +#define RCC_APB4LPENR_LPTIM4LPEN (1 << 11) /* RCC APB4LPENR: LPTIM4LPEN */ +#define RCC_APB4LPENR_LPTIM5LPEN (1 << 12) /* RCC APB4LPENR: LPTIM5LPEN */ +#define RCC_APB4LPENR_COMP12LPEN (1 << 14) /* RCC APB4LPENR: COMP12LPEN */ +#define RCC_APB4LPENR_VREFLPEN (1 << 15) /* RCC APB4LPENR: VREFLPEN */ +#define RCC_APB4LPENR_RTCAPBLPEN (1 << 16) /* RCC APB4LPENR: RTCAPBLPEN */ +#define RCC_APB4LPENR_SAI4LPEN (1 << 21) /* RCC APB4LPENR: SAI4LPEN */ + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator Drive selection */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) /* See errata ES0392 Rev 7. 2.2.14 */ +# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Low driving capability */ +# define RCC_BDCR_LSEDRV_MEDHI_Y (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium high driving capability rev y */ +# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium high driving capability */ +# define RCC_BDCR_LSEDRV_MEDLO_Y (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium low driving capability rev y */ +# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium low driving capability */ +# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High driving capability */ +#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: LSE clock security system enable */ +#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: LSE clock security system failure detection */ + /* Bit 7: Reserved */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ + /* Bits 10-15: Reserved */ +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ + /* Bits 17-31: Reserved */ + #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_tim.h b/arch/arm/src/stm32h7/hardware/stm32h7_tim.h similarity index 99% rename from arch/arm/src/stm32h7/hardware/stm32_tim.h rename to arch/arm/src/stm32h7/hardware/stm32h7_tim.h index d50bedadd0830..790157d0a0412 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h7/hardware/stm32_tim.h + * arch/arm/src/stm32h7/hardware/stm32h7_tim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h deleted file mode 100644 index 308dc30f621db..0000000000000 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ /dev/null @@ -1,1161 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H -#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* TODO: Complete comments */ - -#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32_RCC_ICSCR_OFFSET 0x0004 -#define STM32_RCC_CRRCR_OFFSET 0x0008 -#define STM32_RCC_CFGR_OFFSET 0x0010 /* Clock configuration register */ -#define STM32_RCC_D1CFGR_OFFSET 0x0018 -#define STM32_RCC_D2CFGR_OFFSET 0x001c -#define STM32_RCC_D3CFGR_OFFSET 0x0020 -#define STM32_RCC_PLLCKSELR_OFFSET 0x0028 -#define STM32_RCC_PLLCFGR_OFFSET 0x002c -#define STM32_RCC_PLL1DIVR_OFFSET 0x0030 -#define STM32_RCC_PLL1FRACR_OFFSET 0x0034 -#define STM32_RCC_PLL2DIVR_OFFSET 0x0038 -#define STM32_RCC_PLL2FRACR_OFFSET 0x003c -#define STM32_RCC_PLL3DIVR_OFFSET 0x0040 -#define STM32_RCC_PLL3FRACR_OFFSET 0x0044 -#define STM32_RCC_D1CCIPR_OFFSET 0x004c /* Domain 1 Kernel Clock configuration register */ -#define STM32_RCC_D2CCIP1R_OFFSET 0x0050 /* Domain 2 Kernel Clock configuration register 1 */ -#define STM32_RCC_D2CCIP2R_OFFSET 0x0054 /* Domain 2 Kernel Clock configuration register 2 */ -#define STM32_RCC_D3CCIPR_OFFSET 0x0058 /* Domain 3 Kernel Clock configuration register */ -#define STM32_RCC_CIER_OFFSET 0x0060 /* Clock Source Interrupt enable register */ -#define STM32_RCC_CIFR_OFFSET 0x0064 /* Clock Source Interrupt Flag register */ -#define STM32_RCC_CICR_OFFSET 0x0068 /* Clock Source Interrupt Clear register */ -#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup Domain Control register */ -#define STM32_RCC_CSR_OFFSET 0x0074 /* Clock Control and Status register */ -#define STM32_RCC_AHB1RSTR_OFFSET 0x0080 /* AHB1 peripheral reset register */ -#define STM32_RCC_AHB2RSTR_OFFSET 0x0084 /* AHB2 peripheral reset register */ -#define STM32_RCC_AHB3RSTR_OFFSET 0x007c /* AHB3 peripheral reset register */ -#define STM32_RCC_AHB4RSTR_OFFSET 0x0088 /* AHB4 peripheral reset register */ -#define STM32_RCC_APB1LRSTR_OFFSET 0x0090 /* APB1 L Peripheral reset register */ -#define STM32_RCC_APB1HRSTR_OFFSET 0x0094 /* APB1 H Peripheral reset register */ -#define STM32_RCC_APB2RSTR_OFFSET 0x0098 /* APB2 Peripheral reset register */ -#define STM32_RCC_APB3RSTR_OFFSET 0x008c /* APB3 Peripheral reset register */ -#define STM32_RCC_APB4RSTR_OFFSET 0x009c /* APB4 Peripheral reset register */ -#define STM32_RCC_GCR_OFFSET 0x00a0 /* RCC Global Control register */ -#define STM32_RCC_D3AMR_OFFSET 0x00a8 /* D3 Autonomous mode register */ -#define STM32_RCC_RSR_OFFSET 0x00d0 /* RCC Reset Status register */ -#define STM32_RCC_AHB1ENR_OFFSET 0x00d8 /* AHB1 Peripheral Clock enable register */ -#define STM32_RCC_AHB2ENR_OFFSET 0x00dc /* AHB2 Peripheral Clock enable register */ -#define STM32_RCC_AHB3ENR_OFFSET 0x00d4 /* AHB3 Peripheral Clock enable register */ -#define STM32_RCC_AHB4ENR_OFFSET 0x00e0 /* AHB4 Peripheral Clock enable register */ -#define STM32_RCC_APB1LENR_OFFSET 0x00e8 /* APB1 L Peripheral Clock enable register */ -#define STM32_RCC_APB1HENR_OFFSET 0x00ec /* APB1 H Peripheral Clock enable register */ -#define STM32_RCC_APB2ENR_OFFSET 0x00f0 /* APB2 Peripheral Clock enable register */ -#define STM32_RCC_APB3ENR_OFFSET 0x00e4 /* APB3 Peripheral Clock enable register */ -#define STM32_RCC_APB4ENR_OFFSET 0x00f4 /* APB4 Peripheral Clock enable register */ -#define STM32_RCC_AHB1LPENR_OFFSET 0x0100 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32_RCC_AHB2LPENR_OFFSET 0x0104 /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32_RCC_AHB3LPENR_OFFSET 0x00fc /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32_RCC_AHB4LPENR_OFFSET 0x0108 /* RCC AHB4 low power mode peripheral clock enable register */ -#define STM32_RCC_APB1LLPENR_OFFSET 0x0110 /* RCC APB1 L low power mode peripheral clock enable register */ -#define STM32_RCC_APB1HLPENR_OFFSET 0x0114 /* RCC APB1 H low power mode peripheral clock enable register */ -#define STM32_RCC_APB2LPENR_OFFSET 0x0118 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32_RCC_APB3LPENR_OFFSET 0x010c /* RCC APB3 low power mode peripheral clock enable register */ -#define STM32_RCC_APB4LPENR_OFFSET 0x011c /* RCC APB4 low power mode peripheral clock enable register */ - -/* Register Addresses *******************************************************/ - -#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) -#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) -#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) -#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) -#define STM32_RCC_D1CFGR (STM32_RCC_BASE + STM32_RCC_D1CFGR_OFFSET) -#define STM32_RCC_D2CFGR (STM32_RCC_BASE + STM32_RCC_D2CFGR_OFFSET) -#define STM32_RCC_D3CFGR (STM32_RCC_BASE + STM32_RCC_D3CFGR_OFFSET) -#define STM32_RCC_PLLCKSELR (STM32_RCC_BASE + STM32_RCC_PLLCKSELR_OFFSET) -#define STM32_RCC_PLLCFGR (STM32_RCC_BASE + STM32_RCC_PLLCFGR_OFFSET) -#define STM32_RCC_PLL1DIVR (STM32_RCC_BASE + STM32_RCC_PLL1DIVR_OFFSET) -#define STM32_RCC_PLL1FRACR (STM32_RCC_BASE + STM32_RCC_PLL1FRACR_OFFSET) -#define STM32_RCC_PLL2DIVR (STM32_RCC_BASE + STM32_RCC_PLL2DIVR_OFFSET) -#define STM32_RCC_PLL2FRACR (STM32_RCC_BASE + STM32_RCC_PLL2FRACR_OFFSET) -#define STM32_RCC_PLL3DIVR (STM32_RCC_BASE + STM32_RCC_PLL3DIVR_OFFSET) -#define STM32_RCC_PLL3FRACR (STM32_RCC_BASE + STM32_RCC_PLL3FRACR_OFFSET) -#define STM32_RCC_D1CCIPR (STM32_RCC_BASE + STM32_RCC_D1CCIPR_OFFSET) -#define STM32_RCC_D2CCIP1R (STM32_RCC_BASE + STM32_RCC_D2CCIP1R_OFFSET) -#define STM32_RCC_D2CCIP2R (STM32_RCC_BASE + STM32_RCC_D2CCIP2R_OFFSET) -#define STM32_RCC_D3CCIPR (STM32_RCC_BASE + STM32_RCC_D3CCIPR_OFFSET) -#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) -#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) -#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) -#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) -#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) -#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) -#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) -#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) -#define STM32_RCC_AHB4RSTR (STM32_RCC_BASE + STM32_RCC_AHB4RSTR_OFFSET) -#define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) -#define STM32_RCC_APB1HRSTR (STM32_RCC_BASE + STM32_RCC_APB1HRSTR_OFFSET) -#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) -#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) -#define STM32_RCC_APB4RSTR (STM32_RCC_BASE + STM32_RCC_APB4RSTR_OFFSET) -#define STM32_RCC_GCR (STM32_RCC_BASE + STM32_RCC_GCR_OFFSET) -#define STM32_RCC_D3AMR (STM32_RCC_BASE + STM32_RCC_D3AMR_OFFSET) -#define STM32_RCC_RSR (STM32_RCC_BASE + STM32_RCC_RSR_OFFSET) -#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) -#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) -#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) -#define STM32_RCC_AHB4ENR (STM32_RCC_BASE + STM32_RCC_AHB4ENR_OFFSET) -#define STM32_RCC_APB1LENR (STM32_RCC_BASE + STM32_RCC_APB1LENR_OFFSET) -#define STM32_RCC_APB1HENR (STM32_RCC_BASE + STM32_RCC_APB1HENR_OFFSET) -#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) -#define STM32_RCC_APB3ENR (STM32_RCC_BASE + STM32_RCC_APB3ENR_OFFSET) -#define STM32_RCC_APB4ENR (STM32_RCC_BASE + STM32_RCC_APB4ENR_OFFSET) -#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE + STM32_RCC_AHB1LPENR_OFFSET) -#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE + STM32_RCC_AHB2LPENR_OFFSET) -#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE + STM32_RCC_AHB3LPENR_OFFSET) -#define STM32_RCC_AHB4LPENR (STM32_RCC_BASE + STM32_RCC_AHB4LPENR_OFFSET) -#define STM32_RCC_APB1LLPENR (STM32_RCC_BASE + STM32_RCC_APB1LLPENR_OFFSET) -#define STM32_RCC_APB1HLPENR (STM32_RCC_BASE + STM32_RCC_APB1HLPENR_OFFSET) -#define STM32_RCC_APB2LPENR (STM32_RCC_BASE + STM32_RCC_APB2LPENR_OFFSET) -#define STM32_RCC_APB3LPENR (STM32_RCC_BASE + STM32_RCC_APB3LPENR_OFFSET) -#define STM32_RCC_APB4LPENR (STM32_RCC_BASE + STM32_RCC_APB4LPENR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Source Control Register */ - -#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ -#define RCC_CR_HSIKERON (1 << 1) /* Bit 1: Internal High Speed clock enable for some IPs Kernel ?? */ -#define RCC_CR_HSIRDY (1 << 2) /* Bit 2: Internal High Speed clock ready flag */ -#define RCC_CR_HSIDIV_SHIFT (3) /* Bits 3-4: HSI clock divider */ -#define RCC_CR_HSIDIV_MASK (3 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV_1 (0 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV_2 (1 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV_4 (2 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV_8 (3 << RCC_CR_HSIDIV_SHIFT) -#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI Divider flag */ - /* Bit 6: Reserved */ -#define RCC_CR_CSION (1 << 7) /* Bit 7: The Internal RC 4MHz oscillator clock enable */ -#define RCC_CR_CSIRDY (1 << 8) /* Bit 8: The Internal RC 4MHz oscillator clock ready */ -#define RCC_CR_CSIKERON (1 << 9) /* Bit 9: Internal RC 4MHz oscillator clock enable for some IPs Kernel */ - /* Bits 10-11: Reserved */ -#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable clock enable */ -#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready */ -#define RCC_CR_D1CKRDY (1 << 14) /* Bit 14: D1 domain clocks ready flag */ -#define RCC_CR_D2CKRDY (1 << 15) /* Bit 15: D2 domain clocks ready flag */ -#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ -#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready */ -#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ -#define RCC_CR_CSSHSEON (1 << 19) /* Bit 19: HSE Clock security System enable */ - /* Bits 20-23: Reserved */ -#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: System PLL1 clock enable */ -#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: System PLL1 clock ready */ -#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: System PLL2 clock enable */ -#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: System PLL2 clock ready */ -#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: System PLL3 clock enable */ -#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: System PLL3 clock ready */ - /* Bits 30-31: Reserved */ - -/* Internal Clock Source Calibration Register */ - -/* HSICAL configuration */ - -#define RCC_ICSCR_HSICAL_SHIFT (0ul) -#define RCC_ICSCR_HSICAL_MASK (0xFFFul << RCC_ICSCR_HSICAL_SHIFT) -#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_MASK /* HSICAL[11:0] bits */ - -/* HSITRIM configuration */ - -#define RCC_ICSCR_HSITRIM_SHIFT (12ul) -#define RCC_ICSCR_HSITRIM_MASK (0x3Ful << RCC_ICSCR_HSITRIM_SHIFT) -#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_MASK /* HSITRIM[5:0] bits */ - -/* CSICAL configuration */ - -#define RCC_ICSCR_CSICAL_SHIFT (18ul) -#define RCC_ICSCR_CSICAL_MASK (0xFFul << RCC_ICSCR_CSICAL_SHIFT) -#define RCC_ICSCR_CSICAL RCC_ICSCR_CSICAL_MASK /* CSICAL[7:0] bits */ - -/* CSITRIM configuration */ - -#define RCC_ICSCR_CSITRIM_SHIFT (26ul) -#define RCC_ICSCR_CSITRIM_MASK (0x1Ful << RCC_ICSCR_CSITRIM_SHIFT) -#define RCC_ICSCR_CSITRIM RCC_ICSCR_CSITRIM_MASK /* CSITRIM[4:0] bits */ - -/* Clock Recovery RC Register */ - -/* HSI48CAL configuration */ - -#define RCC_CRRCR_HSI48CAL_SHIFT (0ul) -#define RCC_CRRCR_HSI48CAL_MASK (0x3FFul << RCC_CRRCR_HSI48CAL_SHIFT) -#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_MASK /* HSI48CAL[9:0] bits */ - -/* Clock Configuration Register (CFGR) */ - -#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */ -#define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT) -# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selection as system clock */ -# define RCC_CFGR_SW_CSI (1 << RCC_CFGR_SW_SHIFT) /* 001: CSI selection as system clock */ -# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 010: HSE selection as system clock */ -# define RCC_CFGR_SW_PLL1 (3 << RCC_CFGR_SW_SHIFT) /* 011: PLL1 selection as system clock */ -#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */ -#define RCC_CFGR_SWS_MASK (7 << RCC_CFGR_SWS_SHIFT) -# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI used as system clock */ -# define RCC_CFGR_SWS_CSI (1 << RCC_CFGR_SWS_SHIFT) /* 001: CSI used as system clock */ -# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 010: HSE used as system clock */ -# define RCC_CFGR_SWS_PLL1 (3 << RCC_CFGR_SWS_SHIFT) /* 011: PLL1 used as system clock */ -#define RCC_CFGR_STOPWUCK (1 << 6) /* Bit 6: Wake Up from stop and CSS backup clock selection */ -#define RCC_CFGR_STOPKERWUCK (1 << 7) /* Bit 7: Kernel Clock Selection after a Wake Up from STOP */ -#define RCC_CFGR_RTCPRE_SHIFT (8) /* Bits 8-13: HSE division factor for RTC clock */ -#define RCC_CFGR_RTCPRE_MASK (0x3f << RCC_CFGR_RTCPRE_SHIFT) -# define RCC_CFGR_RTCPRE(x) (((uint32_t)(x)) << RCC_CFGR_RTCPRE_SHIFT) -#define RCC_CFGR_HRTIMSEL (1 << 14) /* Bit 14: HRTIM TImer clock prescaler */ -#define RCC_CFGR_TIMPRE (1 << 15) /* Timers clocks prescaler */ -#define RCC_CFGR_MCO1PRE_SHIFT (18) /* Bits 18-21: MCO1 prescaler */ -#define RCC_CFGR_MCO1PRE_MASK (0xf << RCC_CFGR_MCO1PRE_SHIFT) -# define RCC_CFGR_MCO1PRE(x) (((uint32_t)(x)) << 18) -#define RCC_CFGR_MCO1_SHIFT (22) /* Bits 22-24: Microcontroller Clock Output 1 */ -#define RCC_CFGR_MCO1_MASK (7 << RCC_CFGR_MCO1_SHIFT) -# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */ -# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */ -# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */ -# define RCC_CFGR_MCO1_PLL1Q (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */ -# define RCC_CFGR_MCO1_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */ -#define RCC_CFGR_MCO2PRE_SHIFT (25) /* Bits 25-28: MCO2 prescaler */ -#define RCC_CFGR_MCO2PRE_MASK (0xf << RCC_CFGR_MCO2PRE_SHIFT) -# define RCC_CFGR_MCO2PRE(x) (((uint32_t)(x)) << RCC_CFGR_MCO2PRE_SHIFT) -#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */ -#define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO2_SHIFT) -# define RCC_CFGR_MCO2_SYS (0 << RCC_CFGR_MCO2_SHIFT) /* 000: HSI clock selected */ -# define RCC_CFGR_MCO2_PLL2P (1 << RCC_CFGR_MCO2_SHIFT) /* 001: PLL2 peripheral clock selected */ -# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 010: HSE oscillator clock selected */ -# define RCC_CFGR_MCO2_PLL1P (3 << RCC_CFGR_MCO2_SHIFT) /* 011: PLL1 peripheral clock selected */ -# define RCC_CFGR_MCO2_CSI (4 << RCC_CFGR_MCO2_SHIFT) /* 100: CSI clock selected */ -# define RCC_CFGR_MCO2_LSI (5 << RCC_CFGR_MCO2_SHIFT) /* 101: LSI clock selected */ - -/* Bit definitions for RCC_D1CFGR */ - -#define RCC_D1CFGR_HPRE_SHIFT (0) /* Bits 0-3: D1 domain AHB prescaler */ -#define RCC_D1CFGR_HPRE_MASK (15 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLK (0 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd2 (8 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd4 (9 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd8 (10 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd16 (11 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd64 (12 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd128 (13 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd256 (14 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd512 (15 << RCC_D1CFGR_HPRE_SHIFT) - -#define RCC_D1CFGR_D1PPRE_SHIFT (4) /* Bits 4-6: D1 domain APB3 prescaler */ -#define RCC_D1CFGR_D1PPRE_MASK (7 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLK (0 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLKd2 (4 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLKd4 (5 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLKd8 (6 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLKd16 (7 << RCC_D1CFGR_D1PPRE_SHIFT) - /* Bit 7: Reserved */ -#define RCC_D1CFGR_D1CPRE_SHIFT (8) /* Bits 8-11: D1 domain Core prescaler */ -#define RCC_D1CFGR_D1CPRE_MASK (15 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLK (0 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd2 (8 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd4 (9 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd8 (10 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd16 (11 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd64 (12 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd128 (13 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd256 (14 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd512 (15 << RCC_D1CFGR_D1CPRE_SHIFT) - /* Bits 12-31: Reserved */ - -/* Bit definitions for RCC_D2CFGR */ - - /* Bits 0-3: Reserved */ -#define RCC_D2CFGR_D2PPRE1_SHIFT (4) /* Bits 4-6: D2 domain APB1 prescaler */ -#define RCC_D2CFGR_D2PPRE1_MASK (7 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLK (0 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLKd2 (4 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLKd4 (5 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLKd8 (6 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLKd16 (7 << RCC_D2CFGR_D2PPRE1_SHIFT) - /* Bit 7: Reserved */ -#define RCC_D2CFGR_D2PPRE2_SHIFT (8) /* Bits 8-10: D2 domain APB2 prescaler */ -#define RCC_D2CFGR_D2PPRE2_MASK (7 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLK (0 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLKd2 (4 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLKd4 (5 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLKd8 (6 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLKd16 (7 << RCC_D2CFGR_D2PPRE2_SHIFT) - /* Bits 11-31: Reserved */ - -/* Bit definitions for RCC_D3CFGR */ - - /* Bits 0-3: Reserved */ -#define RCC_D3CFGR_D3PPRE_SHIFT (4) /* Bits 4-6: D3 domain APB4 prescaler */ -#define RCC_D3CFGR_D3PPRE_MASK (7 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLK (0 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLKd2 (4 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLKd4 (5 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLKd8 (6 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLKd16 (7 << RCC_D3CFGR_D3PPRE_SHIFT) - /* Bits 7-31: Reserved */ - -/* Bit definitions for RCC_PLLCKSELR register */ - -#define RCC_PLLCKSELR_PLLSRC_SHIFT (0) /* Bit 0: */ -#define RCC_PLLCKSELR_PLLSRC_MASK (0x3 << RCC_PLLCKSELR_PLLSRC_SHIFT) -#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_MASK - -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /* HSI source clock selected */ -#define RCC_PLLCKSELR_PLLSRC_CSI ((uint32_t)0x00000001) /* CSI source clock selected */ -#define RCC_PLLCKSELR_PLLSRC_HSE ((uint32_t)0x00000002) /* HSE source clock selected */ -#define RCC_PLLCKSELR_PLLSRC_NONE ((uint32_t)0x00000003) /* No source clock selected */ - -#define RCC_PLLCKSELR_DIVM1_SHIFT (4ul) -#define RCC_PLLCKSELR_DIVM1(x) ((x) << RCC_PLLCKSELR_DIVM1_SHIFT) /* Prescaler for PLL1: 1 - 63, 0 = disabled */ -#define RCC_PLLCKSELR_DIVM2_SHIFT (12ul) -#define RCC_PLLCKSELR_DIVM2(x) ((x) << RCC_PLLCKSELR_DIVM2_SHIFT) /* Prescaler for PLL2: 1 - 63, 0 = disabled */ -#define RCC_PLLCKSELR_DIVM3_SHIFT (20ul) -#define RCC_PLLCKSELR_DIVM3(x) ((x) << RCC_PLLCKSELR_DIVM3_SHIFT) /* Prescaler for PLL3: 1 - 63, 0 = disabled */ - -/* Bit definition for RCC_PLLCFGR register */ - -#define RCC_PLLCFGR_RESET ((uint32_t)0x01FF0000) - -#define RCC_PLLCFGR_PLL1FRACEN_SHIFT (0ul) -#define RCC_PLLCFGR_PLL1FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL1FRACEN_SHIFT) -#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_MASK /* Fractional latch enable */ -#define RCC_PLLCFGR_PLL1VCOSEL_SHIFT (1ul) -#define RCC_PLLCFGR_PLL1VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL1VCOSEL_SHIFT) -#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ -#define RCC_PLLCFGR_PLL1VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ -#define RCC_PLLCFGR_PLL1VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ -#define RCC_PLLCFGR_PLL1RGE_SHIFT (2ul) -#define RCC_PLLCFGR_PLL1RGE_MASK (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) -#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_MASK -#define RCC_PLLCFGR_PLL1RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ -#define RCC_PLLCFGR_PLL1RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ -#define RCC_PLLCFGR_PLL1RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ -#define RCC_PLLCFGR_PLL1RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ - -#define RCC_PLLCFGR_PLL2FRACEN_SHIFT (4ul) -#define RCC_PLLCFGR_PLL2FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL2FRACEN_SHIFT) -#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_MASK /* Fractional latch enable */ -#define RCC_PLLCFGR_PLL2VCOSEL_SHIFT (5ul) -#define RCC_PLLCFGR_PLL2VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL2VCOSEL_SHIFT) -#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ -#define RCC_PLLCFGR_PLL2VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ -#define RCC_PLLCFGR_PLL2VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ -#define RCC_PLLCFGR_PLL2RGE_SHIFT (6ul) -#define RCC_PLLCFGR_PLL2RGE_MASK (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) -#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_MASK -#define RCC_PLLCFGR_PLL2RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ -#define RCC_PLLCFGR_PLL2RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ -#define RCC_PLLCFGR_PLL2RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ -#define RCC_PLLCFGR_PLL2RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ - -#define RCC_PLLCFGR_PLL3FRACEN_SHIFT (8ul) -#define RCC_PLLCFGR_PLL3FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL3FRACEN_SHIFT) -#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_MASK /* Fractional latch enable */ -#define RCC_PLLCFGR_PLL3VCOSEL_SHIFT (9ul) -#define RCC_PLLCFGR_PLL3VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL3VCOSEL_SHIFT) -#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ -#define RCC_PLLCFGR_PLL3VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ -#define RCC_PLLCFGR_PLL3VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ -#define RCC_PLLCFGR_PLL3RGE_SHIFT (10ul) -#define RCC_PLLCFGR_PLL3RGE_MASK (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) -#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_MASK -#define RCC_PLLCFGR_PLL3RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ -#define RCC_PLLCFGR_PLL3RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ -#define RCC_PLLCFGR_PLL3RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ -#define RCC_PLLCFGR_PLL3RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ - -#define RCC_PLLCFGR_DIVP1EN_SHIFT (16ul) -#define RCC_PLLCFGR_DIVP1EN_MASK (0x1ul << RCC_PLLCFGR_DIVP1EN_SHIFT) -#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_MASK -#define RCC_PLLCFGR_DIVQ1EN_SHIFT (17ul) -#define RCC_PLLCFGR_DIVQ1EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ1EN_SHIFT) -#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_MASK -#define RCC_PLLCFGR_DIVR1EN_SHIFT (18ul) -#define RCC_PLLCFGR_DIVR1EN_MASK (0x1ul << RCC_PLLCFGR_DIVR1EN_SHIFT) -#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_MASK - -#define RCC_PLLCFGR_DIVP2EN_SHIFT (19ul) -#define RCC_PLLCFGR_DIVP2EN_MASK (0x1ul << RCC_PLLCFGR_DIVP2EN_SHIFT) -#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_MASK -#define RCC_PLLCFGR_DIVQ2EN_SHIFT (20ul) -#define RCC_PLLCFGR_DIVQ2EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ2EN_SHIFT) -#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_MASK -#define RCC_PLLCFGR_DIVR2EN_SHIFT (21ul) -#define RCC_PLLCFGR_DIVR2EN_MASK (0x1ul << RCC_PLLCFGR_DIVR2EN_SHIFT) -#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_MASK - -#define RCC_PLLCFGR_DIVP3EN_SHIFT (22ul) -#define RCC_PLLCFGR_DIVP3EN_MASK (0x1ul << RCC_PLLCFGR_DIVP3EN_SHIFT) -#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_MASK -#define RCC_PLLCFGR_DIVQ3EN_SHIFT (23ul) -#define RCC_PLLCFGR_DIVQ3EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ3EN_SHIFT) -#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_MASK -#define RCC_PLLCFGR_DIVR3EN_SHIFT (24ul) -#define RCC_PLLCFGR_DIVR3EN_MASK (0x1ul << RCC_PLLCFGR_DIVR3EN_SHIFT) -#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_MASK - -/* Bit definitions for RCC_PLL1DIVR register */ - -#define RCC_PLL1DIVR_N1_SHIFT (0ul) -#define RCC_PLL1DIVR_N1(x) (((x) - 1) << RCC_PLL1DIVR_N1_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ -#define RCC_PLL1DIVR_P1_SHIFT (9ul) -#define RCC_PLL1DIVR_P1(x) (((x) - 1) << RCC_PLL1DIVR_P1_SHIFT) /* DIVP division factor: 2 - 128, must be even */ -#define RCC_PLL1DIVR_Q1_SHIFT (16ul) -#define RCC_PLL1DIVR_Q1(x) (((x) - 1) << RCC_PLL1DIVR_Q1_SHIFT) /* DIVQ division factor: 2 - 128 */ -#define RCC_PLL1DIVR_R1_SHIFT (24ul) -#define RCC_PLL1DIVR_R1(x) (((x) - 1) << RCC_PLL1DIVR_R1_SHIFT) /* DIVR division factor: 2 - 128 */ - -/* Bit definitions for RCC_PLL1FRACR register */ - -#define RCC_PLL1FRACR_FRACN1_SHIFT (3ul) -#define RCC_PLL1FRACR_FRACN1_MASK (0x1FFFul << RCC_PLL1FRACR_FRACN1_SHIFT) -#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_MASK - -/* Bit definitions for RCC_PLL2DIVR register */ - -#define RCC_PLL2DIVR_N2_SHIFT (0ul) -#define RCC_PLL2DIVR_N2(x) (((x) - 1) << RCC_PLL2DIVR_N2_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ -#define RCC_PLL2DIVR_P2_SHIFT (9ul) -#define RCC_PLL2DIVR_P2(x) (((x) - 1) << RCC_PLL2DIVR_P2_SHIFT) /* DIVP division factor: 2 - 128 */ -#define RCC_PLL2DIVR_Q2_SHIFT (16ul) -#define RCC_PLL2DIVR_Q2(x) (((x) - 1) << RCC_PLL2DIVR_Q2_SHIFT) /* DIVQ division factor: 2 - 128 */ -#define RCC_PLL2DIVR_R2_SHIFT (24ul) -#define RCC_PLL2DIVR_R2(x) (((x) - 1) << RCC_PLL2DIVR_R2_SHIFT) /* DIVR division factor: 2 - 128 */ - -/* Bit definitions for RCC_PLL2FRACR register */ - -#define RCC_PLL2FRACR_FRACN2_SHIFT (3ul) -#define RCC_PLL2FRACR_FRACN2_MASK (0x1FFFul << RCC_PLL2FRACR_FRACN2_SHIFT) -#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_MASK - -/* Bit definitions for RCC_PLL3DIVR register */ - -#define RCC_PLL3DIVR_N3_SHIFT (0ul) -#define RCC_PLL3DIVR_N3(x) (((x) - 1) << RCC_PLL3DIVR_N3_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ -#define RCC_PLL3DIVR_P3_SHIFT (9ul) -#define RCC_PLL3DIVR_P3(x) (((x) - 1) << RCC_PLL3DIVR_P3_SHIFT) /* DIVP division factor: 2 - 128 */ -#define RCC_PLL3DIVR_Q3_SHIFT (16ul) -#define RCC_PLL3DIVR_Q3(x) (((x) - 1) << RCC_PLL3DIVR_Q3_SHIFT) /* DIVQ division factor: 2 - 128 */ -#define RCC_PLL3DIVR_R3_SHIFT (24ul) -#define RCC_PLL3DIVR_R3(x) (((x) - 1) << RCC_PLL3DIVR_R3_SHIFT) /* DIVR division factor: 2 - 128 */ - -/* Bit definitions for RCC_PLL3FRACR register */ - -#define RCC_PLL3FRACR_FRACN3_SHIFT (3ul) -#define RCC_PLL3FRACR_FRACN3_MASK (0x1FFFul << RCC_PLL3FRACR_FRACN3_SHIFT) -#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_MASK - -/* Bit definitions for RCC_D1CCIPR register */ - -#define RCC_D1CCIPR_FMCSEL_SHIFT (0) /* Bits 0-1: */ -#define RCC_D1CCIPR_FMCSEL_MASK (3 << RCC_D1CCIPR_FMCSEL_SHIFT) -# define RCC_D1CCIPR_FMCSEL_HCLK (0 << RCC_D1CCIPR_FMCSEL_SHIFT) -# define RCC_D1CCIPR_FMCSEL_PLL1 (1 << RCC_D1CCIPR_FMCSEL_SHIFT) -# define RCC_D1CCIPR_FMCSEL_PLL2 (2 << RCC_D1CCIPR_FMCSEL_SHIFT) -# define RCC_D1CCIPR_FMCSEL_PER (3 << RCC_D1CCIPR_FMCSEL_SHIFT) - /* Bits 2-3: Reserved */ -#define RCC_D1CCIPR_QSPISEL_SHIFT (4) /* Bits 4-5: */ -#define RCC_D1CCIPR_QSPISEL_MASK (3 << RCC_D1CCIPR_QSPISEL_SHIFT) -# define RCC_D1CCIPR_QSPISEL_HCLK (0 << RCC_D1CCIPR_QSPISEL_SHIFT) -# define RCC_D1CCIPR_QSPISEL_PLL1 (1 << RCC_D1CCIPR_QSPISEL_SHIFT) -# define RCC_D1CCIPR_QSPISEL_PLL2 (2 << RCC_D1CCIPR_QSPISEL_SHIFT) -# define RCC_D1CCIPR_QSPISEL_PER (3 << RCC_D1CCIPR_QSPISEL_SHIFT) - /* Bits 6-15: Reserved */ -#define RCC_D1CCIPR_SDMMC_SHIFT (16) /* Bit 16: */ -#define RCC_D1CCIPR_SDMMC_MASK (1 << RCC_D1CCIPR_SDMMC_SHIFT) -# define RCC_D1CCIPR_SDMMC_PLL1 (0 << RCC_D1CCIPR_SDMMC_SHIFT) -# define RCC_D1CCIPR_SDMMC_PLL2 (1 << RCC_D1CCIPR_SDMMC_SHIFT) - /* Bits 17-27: Reserved */ -#define RCC_D1CCIPR_CKPERSEL_SHIFT (28) /* Bits 28-29: */ -#define RCC_D1CCIPR_CKPERSEL_MASK (3 << RCC_D1CCIPR_CKPERSEL_SHIFT) -# define RCC_D1CCIPR_CKPERSEL_HSI (0 << RCC_D1CCIPR_CKPERSEL_SHIFT) -# define RCC_D1CCIPR_CKPERSEL_CSI (1 << RCC_D1CCIPR_CKPERSEL_SHIFT) -# define RCC_D1CCIPR_CKPERSEL_HSE (2 << RCC_D1CCIPR_CKPERSEL_SHIFT) - /* Bits 30-31: Reserved */ - -/* Bit definitions for RCC_D2CCIP1R register */ - -#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */ -#define RCC_D2CCIP1R_SAI1SEL_MASK (7 << RCC_D2CCIP1R_SAI1SEL_MASK) -# define RCC_D2CCIP1R_SAI1SEL_PLL1 (0 << RCC_D2CCIP1R_SAI1SEL_SHIFT) -# define RCC_D2CCIP1R_SAI1SEL_PLL2 (1 << RCC_D2CCIP1R_SAI1SEL_SHIFT) -# define RCC_D2CCIP1R_SAI1SEL_PLL3 (2 << RCC_D2CCIP1R_SAI1SEL_SHIFT) -# define RCC_D2CCIP1R_SAI1SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI1SEL_SHIFT) -# define RCC_D2CCIP1R_SAI1SEL_PER (4 << RCC_D2CCIP1R_SAI1SEL_SHIFT) - /* Bits 3-5: Reserved */ -#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */ -#define RCC_D2CCIP1R_SAI23SEL_MASK (7 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_PLL1 (0 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_PLL2 (1 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_PLL3 (2 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_PER (4 << RCC_D2CCIP1R_SAI23SEL_SHIFT) - /* Bits 9-11: Reserved */ -#define RCC_D2CCIP1R_SPI123SEL_SHIFT (12) /* Bits 12-14 */ -#define RCC_D2CCIP1R_SPI123SEL_MASK (7 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_PLL1 (0 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_PLL2 (1 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_PLL3 (2 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_PER (4 << RCC_D2CCIP1R_SPI123SEL_SHIFT) - /* Bit 15: Reserved */ -#define RCC_D2CCIP1R_SPI45SEL_SHIFT (16) /* Bits 16-18 */ -#define RCC_D2CCIP1R_SPI45SEL_MASK (7 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_APB (0 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_PLL2 (1 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_PLL3 (2 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_HSI (3 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_CSI (4 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_HSE (5 << RCC_D2CCIP1R_SPI45SEL_SHIFT) - /* Bit 19: Reserved */ -#define RCC_D2CCIP1R_SPDIFSEL_SHIFT (20) /* Bits 20-21 */ -#define RCC_D2CCIP1R_SPDIFSEL_MASK (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) -# define RCC_D2CCIP1R_SPDIFSEL_PLL1 (0 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) -# define RCC_D2CCIP1R_SPDIFSEL_PLL2 (1 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) -# define RCC_D2CCIP1R_SPDIFSEL_PLL3 (2 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) -# define RCC_D2CCIP1R_SPDIFSEL_HSI (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) - /* Bits 22-23: Reserved */ -#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT (24) /* Bit 24 */ -#define RCC_D2CCIP1R_DFSDM1SEL_MASK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) -# define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 (0 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) -# define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) - /* Bits 25-27: Reserved */ -#define RCC_D2CCIP1R_FDCANSEL_SHIFT (28) /* Bits 28-29 */ -#define RCC_D2CCIP1R_FDCANSEL_MASK (3 << RCC_D2CCIP1R_FDCANSEL_SHIFT) -# define RCC_D2CCIP1R_FDCANSEL_HSE (0 << RCC_D2CCIP1R_FDCANSEL_SHIFT) -# define RCC_D2CCIP1R_FDCANSEL_PLL1 (1 << RCC_D2CCIP1R_FDCANSEL_SHIFT) -# define RCC_D2CCIP1R_FDCANSEL_PLL2 (2 << RCC_D2CCIP1R_FDCANSEL_SHIFT) - /* Bit 30: Reserved */ -#define RCC_D2CCIP1R_SWPSEL_SHIFT (31) /* Bit 31 */ -#define RCC_D2CCIP1R_SWPSEL_MASK (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) -# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) -# define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) - -/* Bit definitions for RCC_D2CCIP2R register */ - -#define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */ -# define RCC_D2CCIP2R_USART234578SEL_MASK (7 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_RCC (0 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_PLL2 (1 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_PLL3 (2 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_HSI (3 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_CSI (4 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_LSE (5 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -#define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */ -# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_RCC (0 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_PLL2 (1 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_PLL3 (2 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_HSI (3 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_CSI (4 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_LSE (5 << RCC_D2CCIP2R_USART16SEL_SHIFT) - /* Bits 6-7: Reserved */ -#define RCC_D2CCIP2R_RNGSEL_SHIFT (8) /* Bits 8-9 */ -# define RCC_D2CCIP2R_RNGSEL_MASK (3 << RCC_D2CCIP2R_RNGSEL_SHIFT) - /* Bits 10-11: Reserved */ -#define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */ -#define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) -# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) -# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) -# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) -# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) - /* Bits 14-19: Reserved */ -#define RCC_D2CCIP2R_USBSEL_SHIFT (20) /* Bits 20-21 */ -# define RCC_D2CCIP2R_USBSEL_MASK (3 << RCC_D2CCIP2R_USBSEL_SHIFT) -# define RCC_D2CCIP2R_USBSEL_DISABLE (0 << RCC_D2CCIP2R_USBSEL_SHIFT) -# define RCC_D2CCIP2R_USBSEL_PLL1 (1 << RCC_D2CCIP2R_USBSEL_SHIFT) -# define RCC_D2CCIP2R_USBSEL_PLL3 (2 << RCC_D2CCIP2R_USBSEL_SHIFT) -# define RCC_D2CCIP2R_USBSEL_HSI48 (3 << RCC_D2CCIP2R_USBSEL_SHIFT) -#define RCC_D2CCIP2R_CECSEL_SHIFT (22) /* Bits 22-23 */ -# define RCC_D2CCIP2R_CECSEL_MASK (3 << RCC_D2CCIP2R_CECSEL_SHIFT) - /* Bits 24-27: Reserved */ -#define RCC_D2CCIP2R_LPTIM1SEL_SHIFT (28) /* Bits 28-30 */ -# define RCC_D2CCIP2R_LPTIM1SEL_MASK (3 << RCC_D2CCIP2R_LPTIM1SEL_SHIFT) - /* Bit 31: Reserved */ - -/* Bit definitions for RCC_D3CCIPR register */ - -#define RCC_D3CCIPR_LPUART1SEL_SHIFT (0) /* Bits 0-2: LPUART1 kernel clock source selection */ -#define RCC_D3CCIPR_LPUART1SEL_MASK (7 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_PCLK (0 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_PLL2 (1 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_PLL3 (2 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_HSI (3 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_CSI (4 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_LSE (5 << RCC_D3CCIPR_LPUART1SEL_SHIFT) - /* Bits 3-7: Reserved */ -#define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9: I2C4 kernel clock source selection */ -#define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) -#define RCC_D3CCIPR_LPTIM2SEL_SHIFT (10) /* Bits 10-12: LPTIM2 kernel clock source selection */ -#define RCC_D3CCIPR_LPTIM2SEL_MASK (7 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_LSE (3 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_LSI (4 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_PER (5 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -#define RCC_D3CCIPR_LPTIM345SEL_SHIFT (13) /* Bits 13-15: LPTIM3,4,5 kernel clock source selection */ -#define RCC_D3CCIPR_LPTIM345SEL_MASK (7 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_LSE (3 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_LSI (4 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_PER (5 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -#define RCC_D3CCIPR_ADCSEL_SHIFT (16) /* Bits 16-17: SAR ADC kernel clock source selection */ -#define RCC_D3CCIPR_ADCSEL_MASK (3 << RCC_D3CCIPR_ADCSEL_SHIFT) -# define RCC_D3CCIPR_ADCSEL_PLL2 (0 << RCC_D3CCIPR_ADCSEL_SHIFT) -# define RCC_D3CCIPR_ADCSEL_PLL3 (1 << RCC_D3CCIPR_ADCSEL_SHIFT) -# define RCC_D3CCIPR_ADCSEL_PER (2 << RCC_D3CCIPR_ADCSEL_SHIFT) - /* Bits 18-20: Reserved */ -#define RCC_D3CCIPR_SAI4ASEL_SHIFT (21) /* Bits 21-23: Sub-Block A of SAI4 kernel clock source selection */ -#define RCC_D3CCIPR_SAI4ASEL_MASK (7 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_PLL1 (0 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_PLL2 (1 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_PLL3 (2 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_PER (4 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -#define RCC_D3CCIPR_SAI4BSEL_SHIFT (24) /* Bits 24-26: Sub-Block B of SAI4 kernel clock source selection */ -#define RCC_D3CCIPR_SAI4BSEL_MASK (7 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_PLL1 (0 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_PLL2 (1 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_PLL3 (2 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_PER (4 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -#define RCC_D3CCIPR_SPI6SEL_SHIFT (28) /* Bits 28-30: SPI6 kernel clock source selection */ -#define RCC_D3CCIPR_SPI6SEL_MASK (7 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_PCLK4 (0 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_PLL2 (1 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_PLL3 (2 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_HSI (3 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_CSI (4 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_HSE (5 << RCC_D3CCIPR_SPI6SEL_SHIFT) - /* Bit 31: Reserved */ - -/* TODO: CIER */ - -/* TODO: CIFR */ - -/* TODO: CICR */ - -/* TODO: BDCR */ - -/* Bit definitions for RCC_CSR register */ - -#define RCC_CSR_LSION (1 << 0) /* RCC CSR: LSION */ -#define RCC_CSR_LSIRDY (1 << 1) /* RCC CSR: LSIRDY */ - -/* AHB3 peripheral reset register */ - -#define RCC_AHB3RSTR_MDMARST (1 << 0) /* RCC AHB3RSTR: MDMARST */ -#define RCC_AHB3RSTR_DMA2DRST (1 << 4) /* RCC AHB3RSTR: DMA2DRST */ -#define RCC_AHB3RSTR_JPGDECRST (1 << 5) /* RCC AHB3RSTR: JPGDECRST */ -#define RCC_AHB3RSTR_FMCRST (1 << 12) /* RCC AHB3RSTR: FMCRST */ -#define RCC_AHB3RSTR_QSPIRST (1 << 14) /* RCC AHB3RSTR: QSPIRST */ -#define RCC_AHB3RSTR_SDMMC1RST (1 << 16) /* RCC AHB3RSTR: SDMMC1RST */ -#define RCC_AHB3RSTR_CPURST (1 << 31) /* RCC AHB3RSTR: CPURST */ - -/* AHB1 peripheral reset register */ - -#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* RCC AHB1RSTR: DMA1RST */ -#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* RCC AHB1RSTR: DMA2RST */ -#define RCC_AHB1RSTR_ADC12RST (1 << 5) /* RCC AHB1RSTR: ADC12RST */ - /* Bits 6-14: Reserved */ -#define RCC_AHB1RSTR_ETH1MACRST (1 << 15) /* RCC AHB1RSTR: ETH1MACRST */ - /* Bits 16-24: Reserved */ -#define RCC_AHB1RSTR_OTGHSRST (1 << 25) /* RCC AHB1RSTR: OTGHSRST */ - /* Bit 26: Reserved */ -#define RCC_AHB1RSTR_OTGFSRST (1 << 27) /* RCC AHB1RSTR: OTGFSRST */ - /* Bits 28-31: Reserved */ - -/* AHB2 peripheral reset register */ - -#define RCC_AHB2RSTR_CAMITFRST (1 << 0) /* RCC AHB2RSTR: CAMITFRST */ - /* Bits 1-3: Reserved */ -#define RCC_AHB2RSTR_CRYPTRST (1 << 4) /* RCC AHB2RSTR: CRYPTRST */ -#define RCC_AHB2RSTR_HASHRST (1 << 5) /* RCC AHB2RSTR: HASHRST */ -#define RCC_AHB2RSTR_RNGRST (1 << 6) /* RCC AHB2RSTR: RNGRST */ - /* Bits 7-8: Reserved */ -#define RCC_AHB2RSTR_SDMMC2RST (1 << 9) /* RCC AHB2RSTR: SDMMC2RST */ - /* Bits 10-31: Reserved */ - -/* AHB4 peripheral reset register */ - -#define RCC_AHB4RSTR_GPIOARST (1 << 0) /* RCC AHB4RSTR: GPIOARST */ -#define RCC_AHB4RSTR_GPIOBRST (1 << 1) /* RCC AHB4RSTR: GPIOBRST */ -#define RCC_AHB4RSTR_GPIOCRST (1 << 2) /* RCC AHB4RSTR: GPIOCRST */ -#define RCC_AHB4RSTR_GPIODRST (1 << 3) /* RCC AHB4RSTR: GPIODRST */ -#define RCC_AHB4RSTR_GPIOERST (1 << 4) /* RCC AHB4RSTR: GPIOERST */ -#define RCC_AHB4RSTR_GPIOFRST (1 << 5) /* RCC AHB4RSTR: GPIOFRST */ -#define RCC_AHB4RSTR_GPIOGRST (1 << 6) /* RCC AHB4RSTR: GPIOGRST */ -#define RCC_AHB4RSTR_GPIOHRST (1 << 7) /* RCC AHB4RSTR: GPIOHRST */ -#define RCC_AHB4RSTR_GPIOIRST (1 << 8) /* RCC AHB4RSTR: GPIOIRST */ -#define RCC_AHB4RSTR_GPIOJRST (1 << 9) /* RCC AHB4RSTR: GPIOJRST */ -#define RCC_AHB4RSTR_GPIOKRST (1 << 10) /* RCC AHB4RSTR: GPIOKRST */ - /* Bits 11-18: Reserved */ -#define RCC_AHB4RSTR_CRCRST (1 << 19) /* RCC AHB4RSTR: CRCRST */ - /* Bit 20: Reserved */ -#define RCC_AHB4RSTR_BDMARST (1 << 21) /* RCC AHB4RSTR: BDMARST */ - /* Bits 22-23: Reserved */ -#define RCC_AHB4RSTR_ADC3RST (1 << 24) /* RCC AHB4RSTR: ADC3RST */ -#define RCC_AHB4RSTR_HSEMRST (1 << 25) /* RCC AHB4RSTR: HSEMRST */ - /* Bits 26-31: Reserved */ - -/* APB3 peripheral reset register */ - - /* Bits 0-2: Reserved */ -#define RCC_APB3RSTR_LTDCRST (1 << 3) /* RCC APB3RSTR: LTDCRST */ - /* Bits 4-31: Reserved */ - -/* APB3 L peripheral reset register */ - -#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* RCC APB1LRSTR: TIM2RST */ -#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* RCC APB1LRSTR: TIM3RST */ -#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* RCC APB1LRSTR: TIM4RST */ -#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* RCC APB1LRSTR: TIM5RST */ -#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* RCC APB1LRSTR: TIM6RST */ -#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* RCC APB1LRSTR: TIM7RST */ -#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* RCC APB1LRSTR: TIM12RST */ -#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* RCC APB1LRSTR: TIM13RST */ -#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* RCC APB1LRSTR: TIM14RST */ -#define RCC_APB1LRSTR_LPTIM1RST (1 << 9) /* RCC APB1LRSTR: LPTIM1RST */ - /* Bits 10-13: Reserved */ -#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* RCC APB1LRSTR: SPI2RST */ -#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* RCC APB1LRSTR: SPI3RST */ -#define RCC_APB1LRSTR_SPDIFRXRST (1 << 16) /* RCC APB1LRSTR: SPDIFRXRST */ -#define RCC_APB1LRSTR_USART2RST (1 << 17) /* RCC APB1LRSTR: USART2RST */ -#define RCC_APB1LRSTR_USART3RST (1 << 18) /* RCC APB1LRSTR: USART3RST */ -#define RCC_APB1LRSTR_UART4RST (1 << 19) /* RCC APB1LRSTR: UART4RST */ -#define RCC_APB1LRSTR_UART5RST (1 << 20) /* RCC APB1LRSTR: UART5RST */ -#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* RCC APB1LRSTR: I2C1RST */ -#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* RCC APB1LRSTR: I2C2RST */ -#define RCC_APB1LRSTR_I2C3RST (1 << 23) /* RCC APB1LRSTR: I2C3RST */ - /* Bits 24-26: Reserved */ -#define RCC_APB1LRSTR_HDMICECRST (1 << 27) /* RCC APB1LRSTR: HDMICECRST */ - /* Bit 28: Reserved */ -#define RCC_APB1LRSTR_DAC1RST (1 << 29) /* RCC APB1LRSTR: DAC1RST */ -#define RCC_APB1LRSTR_UART7RST (1 << 30) /* RCC APB1LRSTR: UART7RST */ -#define RCC_APB1LRSTR_UART8RST (1 << 31) /* RCC APB1LRSTR: UART8RST */ - -/* APB1 H peripheral reset register */ - - /* Bit 0: Reserved */ -#define RCC_APB1HRSTR_CRSRST (1 << 1) /* RCC APB1HRSTR: CRSRST */ -#define RCC_APB1HRSTR_SWPRST (1 << 2) /* RCC APB1HRSTR: SWPRST */ - -/* Bit 3: Reserved */ - -#define RCC_APB1HRSTR_OPAMPRST (1 << 4) /* RCC APB1HRSTR: OPAMPRST*/ -#define RCC_APB1HRSTR_MDIOSRST (1 << 5) /* RCC APB1HRSTR: MDIOSRST */ - /* Bits 6-7: Reserved */ -#define RCC_APB1HRSTR_FDCANRST (1 << 8) /* RCC APB1HRSTR: FDCANRST*/ - -/* Bits 9-31: Reserved */ - -/* APB2 peripheral reset register */ - -#define RCC_APB2RSTR_TIM1RST (1 << 0) /* RCC APB2RSTR: TIM1RST */ -#define RCC_APB2RSTR_TIM8RST (1 << 1) /* RCC APB2RSTR: TIM8RST */ -#define RCC_APB2RSTR_USART1RST (1 << 4) /* RCC APB2RSTR: USART1RST */ -#define RCC_APB2RSTR_USART6RST (1 << 5) /* RCC APB2RSTR: USART6RST */ -#define RCC_APB2RSTR_SPI1RST (1 << 12) /* RCC APB2RSTR: SPI1RST */ -#define RCC_APB2RSTR_SPI4RST (1 << 13) /* RCC APB2RSTR: SPI4RST */ -#define RCC_APB2RSTR_TIM15RST (1 << 16) /* RCC APB2RSTR: TIM15RST */ -#define RCC_APB2RSTR_TIM16RST (1 << 17) /* RCC APB2RSTR: TIM16RST */ -#define RCC_APB2RSTR_TIM17RST (1 << 18) /* RCC APB2RSTR: TIM17RST */ -#define RCC_APB2RSTR_SPI5RST (1 << 20) /* RCC APB2RSTR: SPI5RST */ -#define RCC_APB2RSTR_SAI1RST (1 << 22) /* RCC APB2RSTR: SAI1RST */ -#define RCC_APB2RSTR_SAI2RST (1 << 23) /* RCC APB2RSTR: SAI2RST */ -#define RCC_APB2RSTR_SAI3RST (1 << 24) /* RCC APB2RSTR: SAI3RST */ -#define RCC_APB2RSTR_DFSDM1RST (1 << 28) /* RCC APB2RSTR: DFSDM1RST */ -#define RCC_APB2RSTR_HRTIMRST (1 << 29) /* RCC APB2RSTR: HRTIMRST */ - -/* APB4 peripheral reset register */ - -#define RCC_APB4RSTR_SYSCFGRST (1 << 1) /* RCC APB4RSTR: SYSCFGRST */ -#define RCC_APB4RSTR_LPUART1RST (1 << 3) /* RCC APB4RSTR: LPUART1RST */ -#define RCC_APB4RSTR_SPI6RST (1 << 5) /* RCC APB4RSTR: SPI6RST */ -#define RCC_APB4RSTR_I2C4RST (1 << 7) /* RCC APB4RSTR: I2C4RST */ -#define RCC_APB4RSTR_LPTIM2RST (1 << 9) /* RCC APB4RSTR: LPTIM2RST */ -#define RCC_APB4RSTR_LPTIM3RST (1 << 10) /* RCC APB4RSTR: LPTIM3RST */ -#define RCC_APB4RSTR_LPTIM4RST (1 << 11) /* RCC APB4RSTR: LPTIM4RST */ -#define RCC_APB4RSTR_LPTIM5RST (1 << 12) /* RCC APB4RSTR: LPTIM5RST */ -#define RCC_APB4RSTR_COMP12RST (1 << 14) /* RCC APB4RSTR: COMP12RST */ -#define RCC_APB4RSTR_VREFRST (1 << 15) /* RCC APB4RSTR: VREFRST */ -#define RCC_APB4RSTR_SAI4RST (1 << 21) /* RCC APB4RSTR: SAI4RST */ - -/* RCC Global Control register */ - -#define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ -#ifdef CONFIG_STM32_HAVE_CM4 -# define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */ -#endif -#ifdef CONFIG_STM32_HAVE_CM4 -# define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */ -# define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */ -#endif - -/* TODO: D3 Autonomous mode register */ - -/* RCC Reset Status register */ - - /* Bits 0-15: Reserved */ -#define RCC_RSR_RMVF (1 << 16) /* Bit 16: Remove reset flag */ -#define RCC_RSR_CPURSTF (1 << 17) /* Bit 17: CPU reset flag */ - /* Bit 18: Reserved */ -#define RCC_RSR_D1RSTF (1 << 19) /* Bit 19: D1 domain power switch reset flag */ -#define RCC_RSR_D2RSTF (1 << 20) /* Bit 20: D2 domain power switch reset flag */ -#define RCC_RSR_BORRSTF (1 << 21) /* Bit 21: BOR reset flag */ -#define RCC_RSR_PINRSTF (1 << 22) /* Bit 22: Pin reset flag */ -#define RCC_RSR_PORRSTF (1 << 23) /* Bit 23: POR/PDR reset flag */ -#define RCC_RSR_SFTRSTF (1 << 24) /* Bit 24: System reset from CPU flag */ - /* Bit 25: Reserved */ -#define RCC_RSR_IWDG1RSTF (1 << 26) /* Bit 26: Independent watchdog reset flag */ - /* Bit 27: Reserved */ -#define RCC_RSR_WWDG1RSTF (1 << 28) /* Bit 28: Window watchdog reset flag */ - /* Bit 29: Reserved */ -#define RCC_RSR_LPWRRSTF (1 << 30) /* Bit 30: Reset due to illegal D1 DStandby or CPU Cstop flag */ - /* Bit 31: Reserved */ - -/* AHB3 Peripheral Clock enable register */ - -#define RCC_AHB3ENR_MDMAEN (1 << 0) /* RCC AHB3ENR: MDMAEN */ -#define RCC_AHB3ENR_DMA2DEN (1 << 4) /* RCC AHB3ENR: DMA2DEN */ -#define RCC_AHB3ENR_JPGDECEN (1 << 5) /* RCC AHB3ENR: JPGDECEN */ -#define RCC_AHB3ENR_FMCEN (1 << 12) /* RCC AHB3ENR: FMCEN */ -#define RCC_AHB3ENR_QSPIEN (1 << 14) /* RCC AHB3ENR: QSPIEN */ -#define RCC_AHB3ENR_SDMMC1EN (1 << 16) /* RCC AHB3ENR: SDMMC1EN */ - -/* AHB1 Peripheral Clock enable register */ - -#define RCC_AHB1ENR_DMA1EN (1 << 0) /* RCC AHB1ENR: DMA1EN */ -#define RCC_AHB1ENR_DMA2EN (1 << 1) /* RCC AHB1ENR: DMA2EN */ -#define RCC_AHB1ENR_ADC12EN (1 << 5) /* RCC AHB1ENR: ADC12EN */ -#define RCC_AHB1ENR_ETH1MACEN (1 << 15) /* RCC AHB1ENR: ETH1MACEN */ -#define RCC_AHB1ENR_ETH1TXEN (1 << 16) /* RCC AHB1ENR: ETH1TXEN */ -#define RCC_AHB1ENR_ETH1RXEN (1 << 17) /* RCC AHB1ENR: ETH1RXEN */ -#define RCC_AHB1ENR_OTGHSEN (1 << 25) /* RCC AHB1ENR: OTGHSEN */ -#define RCC_AHB1ENR_OTGHSULPIEN (1 << 26) /* RCC AHB1ENR: OTGHSULPIEN */ -#define RCC_AHB1ENR_OTGFSEN (1 << 27) /* RCC AHB1ENR: OTGFSEN */ - -/* AHB2 Peripheral Clock enable register */ - -#define RCC_AHB2ENR_CAMITFEN (1 << 0) /* RCC AHB2ENR: CAMITFEN */ -#define RCC_AHB2ENR_CRYPTEN (1 << 4) /* RCC AHB2ENR: CRYPTEN */ -#define RCC_AHB2ENR_HASHEN (1 << 5) /* RCC AHB2ENR: HASHEN */ -#define RCC_AHB2ENR_RNGEN (1 << 6) /* RCC AHB2ENR: RNGEN */ -#define RCC_AHB2ENR_SDMMC2EN (1 << 9) /* RCC AHB2ENR: SDMMC2EN */ -#define RCC_AHB2ENR_SRAM1EN (1 << 29) /* RCC AHB2ENR: SRAM1EN */ -#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* RCC AHB2ENR: SRAM2EN */ -#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* RCC AHB2ENR: SRAM3EN */ - -/* AHB4 Peripheral Clock enable register */ - -#define RCC_AHB4ENR_GPIOAEN (1 << 0) /* RCC AHB4ENR: GPIOAEN */ -#define RCC_AHB4ENR_GPIOBEN (1 << 1) /* RCC AHB4ENR: GPIOBEN */ -#define RCC_AHB4ENR_GPIOCEN (1 << 2) /* RCC AHB4ENR: GPIOCEN */ -#define RCC_AHB4ENR_GPIODEN (1 << 3) /* RCC AHB4ENR: GPIODEN */ -#define RCC_AHB4ENR_GPIOEEN (1 << 4) /* RCC AHB4ENR: GPIOEEN */ -#define RCC_AHB4ENR_GPIOFEN (1 << 5) /* RCC AHB4ENR: GPIOFEN */ -#define RCC_AHB4ENR_GPIOGEN (1 << 6) /* RCC AHB4ENR: GPIOGEN */ -#define RCC_AHB4ENR_GPIOHEN (1 << 7) /* RCC AHB4ENR: GPIOHEN */ -#define RCC_AHB4ENR_GPIOIEN (1 << 8) /* RCC AHB4ENR: GPIOIEN */ -#define RCC_AHB4ENR_GPIOJEN (1 << 9) /* RCC AHB4ENR: GPIOJEN */ -#define RCC_AHB4ENR_GPIOKEN (1 << 10) /* RCC AHB4ENR: GPIOKEN */ -#define RCC_AHB4ENR_CRCEN (1 << 19) /* RCC AHB4ENR: CRCEN */ -#define RCC_AHB4ENR_BDMAEN (1 << 21) /* RCC AHB4ENR: BDMAEN and DMAMUX2 */ -#define RCC_AHB4ENR_ADC3EN (1 << 24) /* RCC AHB4ENR: ADC3EN */ -#define RCC_AHB4ENR_HSEMEN (1 << 25) /* RCC AHB4ENR: HSEMEN */ -#define RCC_AHB4ENR_BKPSRAMEN (1 << 28) /* RCC AHB4ENR: BKPRAMEN */ - -/* APB3 Peripheral Clock enable register */ - -#define RCC_APB3ENR_LTDCEN (1 << 3) /* RCC APB3ENR: LTDCEN */ -#define RCC_APB3ENR_WWDG1EN (1 << 6) /* RCC APB3ENR: WWDG1EN */ - -/* APB1 L Peripheral Clock enable register */ - -#define RCC_APB1LENR_TIM2EN (1 << 0) /* RCC APB1LENR: TIM2EN */ -#define RCC_APB1LENR_TIM3EN (1 << 1) /* RCC APB1LENR: TIM3EN */ -#define RCC_APB1LENR_TIM4EN (1 << 2) /* RCC APB1LENR: TIM4EN */ -#define RCC_APB1LENR_TIM5EN (1 << 3) /* RCC APB1LENR: TIM5EN */ -#define RCC_APB1LENR_TIM6EN (1 << 4) /* RCC APB1LENR: TIM6EN */ -#define RCC_APB1LENR_TIM7EN (1 << 5) /* RCC APB1LENR: TIM7EN */ -#define RCC_APB1LENR_TIM12EN (1 << 6) /* RCC APB1LENR: TIM12EN */ -#define RCC_APB1LENR_TIM13EN (1 << 7) /* RCC APB1LENR: TIM13EN */ -#define RCC_APB1LENR_TIM14EN (1 << 8) /* RCC APB1LENR: TIM14EN */ -#define RCC_APB1LENR_LPTIM1EN (1 << 9) /* RCC APB1LENR: LPTIM1EN */ - /* Bits 10-13: Reserved */ -#define RCC_APB1LENR_SPI2EN (1 << 14) /* RCC APB1LENR: SPI2EN */ -#define RCC_APB1LENR_SPI3EN (1 << 15) /* RCC APB1LENR: SPI3EN */ -#define RCC_APB1LENR_SPDIFRXEN (1 << 16) /* RCC APB1LENR: SPDIFRXEN */ -#define RCC_APB1LENR_USART2EN (1 << 17) /* RCC APB1LENR: USART2EN */ -#define RCC_APB1LENR_USART3EN (1 << 18) /* RCC APB1LENR: USART3EN */ -#define RCC_APB1LENR_UART4EN (1 << 19) /* RCC APB1LENR: UART4EN */ -#define RCC_APB1LENR_UART5EN (1 << 20) /* RCC APB1LENR: UART5EN */ -#define RCC_APB1LENR_I2C1EN (1 << 21) /* RCC APB1LENR: I2C1EN */ -#define RCC_APB1LENR_I2C2EN (1 << 22) /* RCC APB1LENR: I2C2EN */ -#define RCC_APB1LENR_I2C3EN (1 << 23) /* RCC APB1LENR: I2C3EN */ - /* Bits 24-25: Reserved */ -#define RCC_APB1LENR_HDMICECEN (1 << 27) /* RCC APB1LENR: HDMICECEN */ - /* Bit 28: Reserved */ -#define RCC_APB1LENR_DAC1EN (1 << 29) /* RCC APB1LENR: DAC1EN */ -#define RCC_APB1LENR_UART7EN (1 << 30) /* RCC APB1LENR: UART7EN */ -#define RCC_APB1LENR_UART8EN (1 << 31) /* RCC APB1LENR: UART8EN */ - -/* APB1 H Peripheral Clock enable register */ - - /* Bit 0: Reserved */ -#define RCC_APB1HENR_CRSEN (1 << 1) /* RCC APB1HENR: CRSEN */ -#define RCC_APB1HENR_SWPEN (1 << 2) /* RCC APB1HENR: SWPEN */ - /* Bit 3: Reserved */ -#define RCC_APB1HENR_OPAMPEN (1 << 4) /* RCC APB1HENR: OPAMPEN */ -#define RCC_APB1HENR_MDIOSEN (1 << 5) /* RCC APB1HENR: MDIOSEN */ - /* Bits 6-7: Reserved */ -#define RCC_APB1HENR_FDCANEN (1 << 8) /* RCC APB1HENR: FDCANEN */ - /* Bits 9-31: Reserved */ - -/* APB2 Peripheral Clock enable register */ - -#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: RCC APB2ENR: TIM1EN */ -#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: RCC APB2ENR: TIM8EN */ - /* Bits 2-3: Reserved */ -#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: RCC APB2ENR: USART1EN */ -#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: RCC APB2ENR: USART6EN */ - /* Bits 6-11: Reserved */ -#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: RCC APB2ENR: SPI1EN */ -#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: RCC APB2ENR: SPI4EN */ - /* Bits 14-15: Reserved */ -#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: RCC APB2ENR: TIM15EN */ -#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: RCC APB2ENR: TIM16EN */ -#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: RCC APB2ENR: TIM17EN */ -#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: RCC APB2ENR: SPI5EN */ - /* Bit 21: Reserved */ -#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: RCC APB2ENR: SAI1EN */ -#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: RCC APB2ENR: SAI2EN */ -#define RCC_APB2ENR_SAI3EN (1 << 24) /* Bit 24: RCC APB2ENR: SAI3EN */ - /* Bits 25-27: Reserved */ -#define RCC_APB2ENR_DFSDM1EN (1 << 28) /* Bit 28: RCC APB2ENR: DFSDM1EN */ -#define RCC_APB2ENR_HRTIMEN (1 << 29) /* Bit 29: RCC APB2ENR: HRTIMEN */ - /* Bits 30-31: Reserved */ - -/* APB4 Peripheral Clock enable register */ - - /* Bit 0: Reserved */ -#define RCC_APB4ENR_SYSCFGEN (1 << 1) /* Bit 1: RCC APB4ENR: SYSCFGEN */ - /* Bit 2: Reserved */ -#define RCC_APB4ENR_LPUART1EN (1 << 3) /* Bit 3: RCC APB4ENR: LPUART1EN */ - /* Bit 4: Reserved */ -#define RCC_APB4ENR_SPI6EN (1 << 5) /* Bit 5: RCC APB4ENR: SPI6EN */ - /* Bit 6: Reserved */ -#define RCC_APB4ENR_I2C4EN (1 << 7) /* Bit 7: RCC APB4ENR: I2C4EN */ - /* Bit 8: Reserved */ -#define RCC_APB4ENR_LPTIM2EN (1 << 9) /* Bit 9: RCC APB4ENR: LPTIM2EN */ -#define RCC_APB4ENR_LPTIM3EN (1 << 10) /* Bit 10: RCC APB4ENR: LPTIM3EN */ -#define RCC_APB4ENR_LPTIM4EN (1 << 11) /* Bit 11: RCC APB4ENR: LPTIM4EN */ -#define RCC_APB4ENR_LPTIM5EN (1 << 12) /* Bit 12: RCC APB4ENR: LPTIM5EN */ - /* Bit 13: Reserved */ -#define RCC_APB4ENR_COMP12EN (1 << 14) /* Bit 14: RCC APB4ENR: COMP12EN */ -#define RCC_APB4ENR_VREFEN (1 << 15) /* Bit 15: RCC APB4ENR: VREFEN */ -#define RCC_APB4ENR_RTCAPBEN (1 << 16) /* Bit 16: RCC APB4ENR: RTCAPBEN */ - /* Bits 17-20: Reserved */ -#define RCC_APB4ENR_SAI4EN (1 << 21) /* Bit 21: RCC APB4ENR: SAI4EN */ - /* Bit2 22-31: Reserved */ - -/* AHB3 low power mode peripheral clock enable register */ - -#define RCC_AHB3LPENR_MDMALPEN (1 << 0) /* RCC AHB3LPENR: MDMALPEN */ -#define RCC_AHB3LPENR_DMA2DLPEN (1 << 4) /* RCC AHB3LPENR: DMA2DLPEN */ -#define RCC_AHB3LPENR_JPGDECLPEN (1 << 5) /* RCC AHB3LPENR: JPGDECLPEN */ -#define RCC_AHB3LPENR_FLITFLPEN (1 << 8) /* RCC AHB3LPENR: FLITFLPEN */ -#define RCC_AHB3LPENR_FMCLPEN (1 << 12) /* RCC AHB3LPENR: FMCLPEN */ -#define RCC_AHB3LPENR_QSPILPEN (1 << 14) /* RCC AHB3LPENR: QSPILPEN */ -#define RCC_AHB3LPENR_SDMMC1LPEN (1 << 16) /* RCC AHB3LPENR: SDMMC1LPEN */ -#define RCC_AHB3LPENR_D1DTCM1LPEN (1 << 28) /* RCC AHB3LPENR: D1DTCM1LPEN */ -#define RCC_AHB3LPENR_DTCM2LPEN (1 << 29) /* RCC AHB3LPENR: DTCM2LPEN */ -#define RCC_AHB3LPENR_ITCMLPEN (1 << 30) /* RCC AHB3LPENR: ITCMLPEN */ -#define RCC_AHB3LPENR_AXISRAMLPEN (1 << 31) /* RCC AHB3LPENR: AXISRAMLPEN */ - -/* AHB1 low power mode peripheral clock enable register */ - -#define RCC_AHB1LPENR_DMA1LPEN (1 << 0) /* RCC AHB1LPENR: DMA1LPEN */ -#define RCC_AHB1LPENR_DMA2LPEN (1 << 1) /* RCC AHB1LPENR: DMA2LPEN */ -#define RCC_AHB1LPENR_ADC12LPEN (1 << 5) /* RCC AHB1LPENR: ADC12LPEN */ -#define RCC_AHB1LPENR_ETH1MACLPEN (1 << 15) /* RCC AHB1LPENR: ETH1MACLPEN */ -#define RCC_AHB1LPENR_ETH1TXLPEN (1 << 16) /* RCC AHB1LPENR: ETH1TXLPEN */ -#define RCC_AHB1LPENR_ETH1RXLPEN (1 << 17) /* RCC AHB1LPENR: ETH1RXLPEN */ -#define RCC_AHB1LPENR_OTGHSLPEN (1 << 25) /* RCC AHB1LPENR: OTGHSLPEN */ -#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 26) /* RCC AHB1LPENR: OTGHSULPILPEN */ -#define RCC_AHB1LPENR_OTGFSLPEN (1 << 27) /* RCC AHB1LPENR: OTGFSLPEN */ - -/* AHB2 low power mode peripheral clock enable register */ - -#define RCC_AHB2LPENR_CAMITFLPEN (1 << 0) /* RCC AHB2LPENR: CAMITFLPEN */ -#define RCC_AHB2LPENR_CRYPTLPEN (1 << 4) /* RCC AHB2LPENR: CRYPTLPEN */ -#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* RCC AHB2LPENR: HASHLPEN */ -#define RCC_AHB2LPENR_SDMMC2LPEN (1 << 6) /* RCC AHB2LPENR: SDMMC2LPEN */ -#define RCC_AHB2LPENR_RNGLPEN (1 << 9) /* RCC AHB2LPENR: RNGLPEN */ -#define RCC_AHB2LPENR_SRAM1LPEN (1 << 29) /* RCC AHB2LPENR: SRAM1LPEN */ -#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* RCC AHB2LPENR: SRAM2LPEN */ -#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* RCC AHB2LPENR: SRAM3LPEN */ - -/* AHB4 low power mode peripheral clock enable register */ - -#define RCC_AHB4LPENR_GPIOALPEN (1 << 0) /* RCC AHB4LPENR: GPIOALPEN */ -#define RCC_AHB4LPENR_GPIOBLPEN (1 << 1) /* RCC AHB4LPENR: GPIOBLPEN */ -#define RCC_AHB4LPENR_GPIOCLPEN (1 << 2) /* RCC AHB4LPENR: GPIOCLPEN */ -#define RCC_AHB4LPENR_GPIODLPEN (1 << 3) /* RCC AHB4LPENR: GPIODLPEN */ -#define RCC_AHB4LPENR_GPIOELPEN (1 << 4) /* RCC AHB4LPENR: GPIOELPEN */ -#define RCC_AHB4LPENR_GPIOFLPEN (1 << 5) /* RCC AHB4LPENR: GPIOFLPEN */ -#define RCC_AHB4LPENR_GPIOGLPEN (1 << 6) /* RCC AHB4LPENR: GPIOGLPEN */ -#define RCC_AHB4LPENR_GPIOHLPEN (1 << 7) /* RCC AHB4LPENR: GPIOHLPEN */ -#define RCC_AHB4LPENR_GPIOILPEN (1 << 8) /* RCC AHB4LPENR: GPIOILPEN */ -#define RCC_AHB4LPENR_GPIOJLPEN (1 << 9) /* RCC AHB4LPENR: GPIOJLPEN */ -#define RCC_AHB4LPENR_GPIOKLPEN (1 << 10) /* RCC AHB4LPENR: GPIOKLPEN */ -#define RCC_AHB4LPENR_CRCLPEN (1 << 19) /* RCC AHB4LPENR: CRCLPEN */ -#define RCC_AHB4LPENR_BDMALPEN (1 << 21) /* RCC AHB4LPENR: BDMALPEN */ -#define RCC_AHB4LPENR_ADC3LPEN (1 << 24) /* RCC AHB4LPENR: ADC3LPEN */ -#define RCC_AHB4LPENR_BKPRAMLPEN (1 << 28) /* RCC AHB4LPENR: BKPRAMLPEN */ -#define RCC_AHB4LPENR_SRAM4LPEN (1 << 29) /* RCC AHB4LPENR: SRAM4LPEN */ - -/* APB3 low power mode peripheral clock enable register */ - -#define RCC_APB3LPENR_LTDCLPEN (1 << 3) /* RCC APB3LPENR: LTDCLPEN */ -#define RCC_APB3LPENR_WWDG1LPEN (1 << 6) /* RCC APB3LPENR: WWDG1LPEN */ - -/* APB1 L low power mode peripheral clock enable register */ - -#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* RCC APB1LLPENR: TIM2LPEN */ -#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* RCC APB1LLPENR: TIM3LPEN */ -#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* RCC APB1LLPENR: TIM4LPEN */ -#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* RCC APB1LLPENR: TIM5LPEN */ -#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* RCC APB1LLPENR: TIM6LPEN */ -#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* RCC APB1LLPENR: TIM7LPEN */ -#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* RCC APB1LLPENR: TIM12LPEN */ -#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* RCC APB1LLPENR: TIM13LPEN */ -#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* RCC APB1LLPENR: TIM14LPEN */ -#define RCC_APB1LLPENR_LPTIM1LPEN (1 << 9) /* RCC APB1LLPENR: LPTIM1LPEN */ -#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* RCC APB1LLPENR: SPI2LPEN */ -#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* RCC APB1LLPENR: SPI3LPEN */ -#define RCC_APB1LLPENR_SPDIFRXLPEN (1 << 16) /* RCC APB1LLPENR: SPDIFRXLPEN */ -#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* RCC APB1LLPENR: USART2LPEN */ -#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* RCC APB1LLPENR: USART3LPEN */ -#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* RCC APB1LLPENR: UART4LPEN */ -#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* RCC APB1LLPENR: UART5LPEN */ -#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* RCC APB1LLPENR: I2C1LPEN */ -#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* RCC APB1LLPENR: I2C2LPEN */ -#define RCC_APB1LLPENR_I2C3LPEN (1 << 23) /* RCC APB1LLPENR: I2C3LPEN */ -#define RCC_APB1LLPENR_HDMICECLPEN (1 << 27) /* RCC APB1LLPENR: HDMICECLPEN */ -#define RCC_APB1LLPENR_DAC1LPEN (1 << 29) /* RCC APB1LLPENR: DAC1LPEN */ -#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* RCC APB1LLPENR: UART7LPEN */ -#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* RCC APB1LLPENR: UART8LPEN */ - -/* APB1 H low power mode peripheral clock enable register */ - -#define RCC_APB1HLPENR_CRSLPEN (1 << 1) /* RCC APB1HLPENR: CRSLPEN */ -#define RCC_APB1HLPENR_SWPLPEN (1 << 2) /* RCC APB1HLPENR: SWPLPEN */ -#define RCC_APB1HLPENR_OPAMPLPEN (1 << 4) /* RCC APB1HLPENR: OPAMPLPEN */ -#define RCC_APB1HLPENR_MDIOSLPEN (1 << 5) /* RCC APB1HLPENR: MDIOSLPEN */ -#define RCC_APB1HLPENR_FDCANLPEN (1 << 8) /* RCC APB1HLPENR: FDCANLPEN */ - -/* APB2 low power mode peripheral clock enable register */ - -#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* RCC APB2LPENR: TIM1LPEN */ -#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* RCC APB2LPENR: TIM8LPEN */ -#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* RCC APB2LPENR: USART1LPEN */ -#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* RCC APB2LPENR: USART6LPEN */ -#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* RCC APB2LPENR: SPI1LPEN */ -#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* RCC APB2LPENR: SPI4LPEN */ -#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* RCC APB2LPENR: TIM15LPEN */ -#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* RCC APB2LPENR: TIM16LPEN */ -#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* RCC APB2LPENR: TIM17LPEN */ -#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* RCC APB2LPENR: SPI5LPEN */ -#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* RCC APB2LPENR: SAI1LPEN */ -#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* RCC APB2LPENR: SAI2LPEN */ -#define RCC_APB2LPENR_SAI3LPEN (1 << 24) /* RCC APB2LPENR: SAI3LPEN */ -#define RCC_APB2LPENR_DFSDM1LPEN (1 << 28) /* RCC APB2LPENR: DFSDM1LPEN */ -#define RCC_APB2LPENR_HRTIMLPEN (1 << 29) /* RCC APB2LPENR: HRTIMLPEN */ - -/* APB4 low power mode peripheral clock enable register */ - -#define RCC_APB4LPENR_SYSCFGLPEN (1 << 1) /* RCC APB4LPENR: SYSCFGLPEN */ -#define RCC_APB4LPENR_LPUART1LPEN (1 << 3) /* RCC APB4LPENR: LPUART1LPEN */ -#define RCC_APB4LPENR_SPI6LPEN (1 << 5) /* RCC APB4LPENR: SPI6LPEN */ -#define RCC_APB4LPENR_I2C4LPEN (1 << 7) /* RCC APB4LPENR: I2C4LPEN */ -#define RCC_APB4LPENR_LPTIM2LPEN (1 << 9) /* RCC APB4LPENR: LPTIM2LPEN */ -#define RCC_APB4LPENR_LPTIM3LPEN (1 << 10) /* RCC APB4LPENR: LPTIM3LPEN */ -#define RCC_APB4LPENR_LPTIM4LPEN (1 << 11) /* RCC APB4LPENR: LPTIM4LPEN */ -#define RCC_APB4LPENR_LPTIM5LPEN (1 << 12) /* RCC APB4LPENR: LPTIM5LPEN */ -#define RCC_APB4LPENR_COMP12LPEN (1 << 14) /* RCC APB4LPENR: COMP12LPEN */ -#define RCC_APB4LPENR_VREFLPEN (1 << 15) /* RCC APB4LPENR: VREFLPEN */ -#define RCC_APB4LPENR_RTCAPBLPEN (1 << 16) /* RCC APB4LPENR: RTCAPBLPEN */ -#define RCC_APB4LPENR_SAI4LPEN (1 << 21) /* RCC APB4LPENR: SAI4LPEN */ - -/* Backup domain control register */ - -#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ -#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator Drive selection */ -#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) /* See errata ES0392 Rev 7. 2.2.14 */ -# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Low driving capability */ -# define RCC_BDCR_LSEDRV_MEDHI_Y (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium high driving capability rev y */ -# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium high driving capability */ -# define RCC_BDCR_LSEDRV_MEDLO_Y (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium low driving capability rev y */ -# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium low driving capability */ -# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High driving capability */ -#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: LSE clock security system enable */ -#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: LSE clock security system failure detection */ - /* Bit 7: Reserved */ -#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ -#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) -# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ -# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ -# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ -# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ - /* Bits 10-15: Reserved */ -#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ -#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ - /* Bits 17-31: Reserved */ - -#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H */ diff --git a/arch/arm/src/stm32h7/stm32.h b/arch/arm/src/stm32h7/stm32.h index a6d99c1774357..fa614de2da3d9 100644 --- a/arch/arm/src/stm32h7/stm32.h +++ b/arch/arm/src/stm32h7/stm32.h @@ -43,7 +43,6 @@ #include "stm32_i2c.h" #include "stm32_spi.h" #include "stm32_rcc.h" -#include "stm32_tim.h" #include "stm32_lowputc.h" #endif /* __ARCH_ARM_SRC_STM32H7_STM32_H */ diff --git a/arch/arm/src/stm32h7/stm32_capture.h b/arch/arm/src/stm32h7/stm32_capture.h index 89d09b5c5f4e9..b11ec5c1416e1 100644 --- a/arch/arm/src/stm32h7/stm32_capture.h +++ b/arch/arm/src/stm32h7/stm32_capture.h @@ -31,7 +31,7 @@ #include "chip.h" #include -#include "hardware/stm32_tim.h" +#include "hardware/stm32h7_tim.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32h7/stm32_lsi.c b/arch/arm/src/stm32h7/stm32_lsi.c deleted file mode 100644 index abfa0c0d8ded2..0000000000000 --- a/arch/arm/src/stm32h7/stm32_lsi.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal RC 40 kHz oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32h7/stm32_oneshot.h b/arch/arm/src/stm32h7/stm32_oneshot.h deleted file mode 100644 index f16523985ff1f..0000000000000 --- a/arch/arm/src/stm32h7/stm32_oneshot.h +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H -#define __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The client - * should not access the contents of this structure directly since the - * contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32h7/stm32_pwm.h b/arch/arm/src/stm32h7/stm32_pwm.h index 8cb724fca0299..132f99aae865c 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.h +++ b/arch/arm/src/stm32h7/stm32_pwm.h @@ -41,7 +41,7 @@ #ifdef CONFIG_STM32_PWM # include -# include "hardware/stm32_tim.h" +# include "hardware/stm32h7_tim.h" #endif /**************************************************************************** diff --git a/arch/arm/src/stm32h7/stm32_qencoder.c b/arch/arm/src/stm32h7/stm32_qencoder.c deleted file mode 100644 index d3d29deb35cb7..0000000000000 --- a/arch/arm/src/stm32h7/stm32_qencoder.c +++ /dev/null @@ -1,1184 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" -#include "stm32_qencoder.h" -#include "stm32_rcc.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timers *******************************************************************/ - -#undef HAVE_32BIT_TIMERS -#undef HAVE_16BIT_TIMERS - -/* On the H7 series, TIM2 and TIM5 are 32-bit. All of the rest are 16-bit */ - -/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ - -#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) -# define HAVE_32BIT_TIMERS 1 -#endif - -/* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) -# define HAVE_16BIT_TIMERS 1 -#endif - -/* The width in bits of each timer */ - -#define TIM1_BITWIDTH 16 -#define TIM2_BITWIDTH 32 -#define TIM3_BITWIDTH 16 -#define TIM4_BITWIDTH 16 -#define TIM5_BITWIDTH 32 -#define TIM8_BITWIDTH 16 - -/* Do we need to support mixed 16- and 32-bit timers */ - -#undef HAVE_MIXEDWIDTH_TIMERS -#if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_FILTER -# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32_QENCODER_ICF -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif -#ifdef CONFIG_STM32_STM32F10XX - uint16_t ti1cfg; /* TI1 input pin configuration (16-bit encoding) */ - uint16_t ti2cfg; /* TI2 input pin configuration (16-bit encoding) */ -#else - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ -#endif - uintptr_t regaddr; /* RCC clock enable register address */ - uint32_t enable; /* RCC clock enable bit */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Timer input clock prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; /* Lower half callback structure */ - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; /* static onfiguration */ - - bool inuse; /* True: The lower-half driver is in-use */ - -#ifdef HAVE_16BIT_TIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv,msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, - int32_t *pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = NULL, /* not supported yet */ - .reset = stm32_reset, - .setindex = NULL, /* not supported yet */ - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB2ENR, - .enable = RCC_APB2ENR_TIM1EN, - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1LENR, - .enable = RCC_APB1LENR_TIM2EN, - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1LENR, - .enable = RCC_APB1LENR_TIM3EN, - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1LENR, - .enable = RCC_APB1LENR_TIM4EN, - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM5_QE -static const struct stm32_qeconfig_s g_tim5config = -{ - .timid = 5, - .irq = STM32_IRQ_TIM5, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM5_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1LENR, - .enable = RCC_APB1LENR_TIM5EN, - .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32_TIM5_QEPSC, - .ti1cfg = GPIO_TIM5_CH1IN, - .ti2cfg = GPIO_TIM5_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim5lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim5config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM8_QE -static const struct stm32_qeconfig_s g_tim8config = -{ - .timid = 8, - .irq = STM32_IRQ_TIM8UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM8_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB2ENR, - .enable = RCC_APB2ENR_TIM8EN, - .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32_TIM8_QEPSC, - .ti1cfg = GPIO_TIM8_CH1IN, - .ti2cfg = GPIO_TIM8_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim8lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim8config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. This applies for the - * STM32 H7 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers - * TIM2-5 (but works OK with the 16-bit TIM1,8 as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Write a value to a 32-bit timer register. This applies for the - * STM32 H7 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers - * TIM2-5 (but works OK with the 16-bit TIM1,8 as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg16(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - return &g_tim4lower; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - return &g_tim5lower; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - return &g_tim8lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require - * timer interrupts. - * - ****************************************************************************/ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value + 1, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x00010000; - } - else - { - priv->position += (int32_t)0x00010000; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifdef HAVE_16BIT_TIMERS - uint16_t regval; - int ret; -#endif - - /* Enable clocking to the timer */ - - modifyreg32(priv->config->regaddr, 0, priv->config->enable); - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. - * - * If we are doing precise shaft positioning, each qe pulse is important. - * So the STM32 has direct config control on the pulse count prescaler. - * This input clock just limits the incoming pulse rate, which should be - * lower than the peripheral clock due to resynchronization, but it is the - * responsibility of the system designer to decide the correct prescaler - * value, because it has a direct influence on the encoder resolution. - */ - - stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1 and TIM8) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half - * driver should stop data collection, free any resources, disable timer - * hardware, and put the system into the lowest possible power usage - * state - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - regaddr = STM32_RCC_APB1LRSTR; - resetbit = RCC_APB1LRSTR_TIM2RST; - break; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - regaddr = STM32_RCC_APB1LRSTR; - resetbit = RCC_APB1LRSTR_TIM3RST; - break; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - regaddr = STM32_RCC_APB1LRSTR; - resetbit = RCC_APB1LRSTR_TIM4RST; - break; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - regaddr = STM32_RCC_APB1LRSTR; - resetbit = RCC_APB1LRSTR_TIM5RST; - break; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM8RST; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32_dumpregs(priv, "After stop"); - - /* Disable clocking to the timer */ - - modifyreg32(priv->config->regaddr, priv->config->enable, 0); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. Interrupts are disabled to make this - * atomic (if possible) - */ - - flags = enter_critical_section(); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - leave_critical_section(flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. This function must be - * called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the upper-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#endif /* CONFIG_SENSORS_QENCODER */ diff --git a/arch/arm/src/stm32h7/stm32_qencoder.h b/arch/arm/src/stm32h7/stm32_qencoder.h deleted file mode 100644 index 0af33dc2c71a3..0000000000000 --- a/arch/arm/src/stm32h7/stm32_qencoder.h +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32H7_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32H7_TIMn is defined - * then the CONFIG_STM32H7_TIMn_QE must also be defined to indicate that - * timer "n" is intended to be used for as a quadrature encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder - * (at least for the STM32 H7) - */ - -#undef CONFIG_STM32H7_TIM6_QE -#undef CONFIG_STM32H7_TIM7_QE -#undef CONFIG_STM32H7_TIM9_QE -#undef CONFIG_STM32H7_TIM10_QE -#undef CONFIG_STM32H7_TIM11_QE -#undef CONFIG_STM32H7_TIM12_QE -#undef CONFIG_STM32H7_TIM13_QE -#undef CONFIG_STM32H7_TIM14_QE - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. This function must be - * called from board-specific logic.. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32H7_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c deleted file mode 100644 index e43019938ec26..0000000000000 --- a/arch/arm/src/stm32h7/stm32_tim.c +++ /dev/null @@ -1,1558 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32H7_TIMn is defined then the CONFIG_STM32H7_TIMn_PWM may - * also be defined to indicate that the timer is intended to be used for - * pulsed output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32H7_TIMn is - * defined then CONFIG_STM32H7_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32H7_TIMn is defined - * then CONFIG_STM32H7_TIMn_DAC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32H7_TIMn is defined then - * CONFIG_STM32H7_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32H7_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32H7_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32H7_TIM7_PWM) || defined (CONFIG_STM32H7_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32H7_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32H7_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32H7_TIM12_QE) -# undef CONFIG_STM32_TIM12 -#endif - -#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32H7_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32H7_TIM13_QE) -# undef CONFIG_STM32_TIM13 -#endif - -#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32H7_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32H7_TIM14_QE) -# undef CONFIG_STM32_TIM14 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32H7_TIM15_DAC) || defined(CONFIG_STM32H7_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32H7_TIM16_ADC) || \ - defined(CONFIG_STM32H7_TIM16_DAC) || defined(CONFIG_STM32H7_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32H7_TIM17_ADC) || \ - defined(CONFIG_STM32H7_TIM17_DAC) || defined(CONFIG_STM32H7_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ - defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ - defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM12) -# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM13) -# if defined(GPIO_TIM13_CH1OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM14) -# if defined(GPIO_TIM14_CH1OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -# endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count); -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - stm32_tim_channel_t mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = &stm32_tim_enable, - .disable = &stm32_tim_disable, - .setmode = &stm32_tim_setmode, - .setclock = &stm32_tim_setclock, - .setperiod = &stm32_tim_setperiod, - .getcounter = &stm32_tim_getcounter, - .setcounter = &stm32_tim_setcounter, - .getwidth = &stm32_tim_getwidth, - .setchannel = &stm32_tim_setchannel, - .setcompare = &stm32_tim_setcompare, - .getcapture = &stm32_tim_getcapture, - .setisr = &stm32_tim_setisr, - .enableint = &stm32_tim_enableint, - .disableint = &stm32_tim_disableint, - .ackint = &stm32_tim_ackint, - .checkint = &stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_getwidth - ****************************************************************************/ - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - /* Only TIM2 and TIM5 timers may be 32-bits in width */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#if defined(CONFIG_STM32_TIM2) - case STM32_TIM2_BASE: - return 32; -#endif - -#if defined(CONFIG_STM32_TIM5) - case STM32_TIM5_BASE: - return 32; -#endif - - /* All others are 16-bit times */ - - default: - return 16; - } -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_BTIM_CNT_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_setcounter - ****************************************************************************/ - -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count) -{ - DEBUGASSERT(dev != NULL); - - if (stm32_tim_getwidth(dev) > 16) - { - stm32_putreg32(dev, STM32_BTIM_CNT_OFFSET, count); - } - else - { - stm32_putreg16(dev, STM32_BTIM_CNT_OFFSET, (uint16_t)count); - } -} - -/* Reset timer into system default state, but do not affect output/input - * pins - */ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\ - defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\ - defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM6_GPIOCONFIG)||\ - defined(HAVE_TIM7_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)||\ - defined(HAVE_TIM12_GPIOCONFIG)||defined(HAVE_TIM13_GPIOCONFIG)||\ - defined(HAVE_TIM14_GPIOCONFIG)||defined(HAVE_TIM15_GPIOCONFIG)||\ - defined(HAVE_TIM16_GPIOCONFIG)||defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - freqin = STM32_TIM12_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - freqin = STM32_TIM13_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - vectorno = STM32_IRQ_TIM12; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - - return OK; -} - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); -} - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); -} - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET); - return (regval & source) ? 1 : 0; -} - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - - return OK; -} - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~(3 << GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTTOGGLE: - ccmr_val = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT); - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -# if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -# if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -# if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -# if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -# if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -# if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM8_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM8_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - switch (channel) - { -# if defined(GPIO_TIM12_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -# if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -# if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -# if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -# if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -# if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - } - - return OK; -} - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/* TODO: Detach interrupts, and close down all TIM Channels */ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h7/stm32_tim.h b/arch/arm/src/stm32h7/stm32_tim.h deleted file mode 100644 index 245386f9f0544..0000000000000 --- a/arch/arm/src/stm32h7/stm32_tim.h +++ /dev/null @@ -1,223 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32H7_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, - - /* Clock sources, OR'ed with CK_EXT */ - - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x0e, - - /* Output Compare Modes */ - - /* Enable standard PWM mode, active high when counter < compare */ - - STM32_TIM_CH_OUTPWM = 0x04, - - /* Toggle TIM_CHx output on UEV */ - - STM32_TIM_CH_OUTTOGGLE = 0x08, -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC - open collector mode -#endif -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); - - /* General and Advanced Timers Adds */ - - int (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, - int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32H7_STM32_TIM_H */ diff --git a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c deleted file mode 100644 index cc5e18737e5a7..0000000000000 --- a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,582 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2023 Max Kriegleder. All rights reserved. - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * SPDX-FileContributor: Max Kriegleder - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM9_RES 16 -#define STM32_TIM10_RES 16 -#define STM32_TIM11_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -static struct stm32_lowerhalf_s g_tim9_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM9_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -static struct stm32_lowerhalf_s g_tim10_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM10_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -static struct stm32_lowerhalf_s g_tim11_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM11_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - lower = &g_tim9_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - lower = &g_tim10_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - lower = &g_tim11_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32l0/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32l0/hardware/stm32l0_rcc.h rename to arch/arm/src/stm32l0/hardware/stm32_rcc.h index 1b924ce687016..8d4ccc91a9f53 100644 --- a/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h +++ b/arch/arm/src/stm32l0/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l0/hardware/stm32l0_rcc.h + * arch/arm/src/stm32l0/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H -#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -538,4 +538,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l0/stm32.h b/arch/arm/src/stm32l0/stm32.h index 5b77af6b01b83..cdcdb2d4aa714 100644 --- a/arch/arm/src/stm32l0/stm32.h +++ b/arch/arm/src/stm32l0/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32l1/Kconfig b/arch/arm/src/stm32l1/Kconfig index ca2b98efd0435..82680c89c65fe 100644 --- a/arch/arm/src/stm32l1/Kconfig +++ b/arch/arm/src/stm32l1/Kconfig @@ -296,6 +296,7 @@ config STM32_STM32L15XX select STM32_HAVE_IP_SPI_V1 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h b/arch/arm/src/stm32l1/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h rename to arch/arm/src/stm32l1/hardware/stm32_rcc.h index c557971f1a356..50690b0bc4536 100644 --- a/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h +++ b/arch/arm/src/stm32l1/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h + * arch/arm/src/stm32l1/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -459,4 +459,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l1/stm32.h b/arch/arm/src/stm32l1/stm32.h index 2aed55b33cac0..5d8b38a25598c 100644 --- a/arch/arm/src/stm32l1/stm32.h +++ b/arch/arm/src/stm32l1/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 0d2406e409557..d05274df91a5f 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -36,9 +36,7 @@ list( stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c - stm32l4_lsi.c stm32l4_pwr.c - stm32l4_tim.c stm32l4_flash.c stm32l4_dfumode.c) @@ -46,24 +44,12 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32l4_idle.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32l4_tim_lowerhalf.c) -endif() - if(NOT CONFIG_SCHED_TICKLESS) list(APPEND SRCS stm32l4_timerisr.c) else() list(APPEND SRCS stm32l4_tickless.c) endif() -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c) -endif() - -if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32l4_freerun.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32l4_userspace.c stm32l4_mpuinit.c) endif() @@ -162,10 +148,6 @@ if(CONFIG_STM32_PWM) list(APPEND SRCS stm32l4_pwm.c) endif() -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32l4_qencoder.c) -endif() - if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32l4_qspi.c) endif() @@ -186,10 +168,6 @@ if(CONFIG_STM32_SDMMC1) list(APPEND SRCS stm32l4_sdmmc.c) endif() -if(CONFIG_STM32_1WIREDRIVER) - list(APPEND SRCS stm32l4_1wire.c) -endif() - target_sources(arch PRIVATE ${SRCS}) add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 05f0c30113518..791a7a2417462 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -620,6 +620,7 @@ config STM32_STM32L4X3 select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 @@ -642,6 +643,7 @@ config STM32_STM32L4X5 select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 @@ -658,6 +660,7 @@ config STM32_STM32L4X5 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 select STM32_HAVE_TIM17 @@ -679,6 +682,7 @@ config STM32_STM32L4X6 select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 @@ -695,6 +699,7 @@ config STM32_STM32L4X6 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 select STM32_HAVE_TIM17 @@ -716,6 +721,7 @@ config STM32_STM32L4XR select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 @@ -730,6 +736,7 @@ config STM32_STM32L4XR select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 select STM32_HAVE_TIM17 @@ -841,6 +848,7 @@ config STM32_STM32L471XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index d62701c5fc459..f6c621cc181c5 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -33,32 +33,20 @@ include common/stm32/Make.defs CHIP_CSRCS += stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c CHIP_CSRCS += stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c -CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_lsi.c -CHIP_CSRCS += stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c +CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c +CHIP_CSRCS += stm32l4_pwr.c stm32l4_flash.c CHIP_CSRCS += stm32l4_dfumode.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32l4_idle.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32l4_tim_lowerhalf.c -endif - ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32l4_timerisr.c else CHIP_CSRCS += stm32l4_tickless.c endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32l4_freerun.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32l4_userspace.c stm32l4_mpuinit.c endif @@ -158,9 +146,6 @@ ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32l4_qencoder.c -endif ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32l4_qspi.c @@ -181,7 +166,3 @@ endif ifeq ($(CONFIG_STM32_SDMMC1),y) CHIP_CSRCS += stm32l4_sdmmc.c endif - -ifeq ($(CONFIG_STM32_1WIREDRIVER),y) -CHIP_CSRCS += stm32l4_1wire.c -endif diff --git a/arch/arm/src/stm32l4/hardware/stm32_rcc.h b/arch/arm/src/stm32l4/hardware/stm32_rcc.h new file mode 100644 index 0000000000000..25063763b4114 --- /dev/null +++ b/arch/arm/src/stm32l4/hardware/stm32_rcc.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/hardware/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32L4X3) +# include "hardware/stm32l4x3xx_rcc.h" +#elif defined(CONFIG_STM32_STM32L4X5) +# include "hardware/stm32l4x5xx_rcc.h" +#elif defined(CONFIG_STM32_STM32L4X6) +# include "hardware/stm32l4x6xx_rcc.h" +#elif defined(CONFIG_STM32_STM32L4XR) +# include "hardware/stm32l4xrxx_rcc.h" +#else +# error "Unsupported STM32L4 chip" +#endif + +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h index d2d43e82eb0c6..bbba36cd34c1d 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h @@ -296,6 +296,26 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ #define USART_TDR_MASK (0xff << USART_TDR_SHIFT) +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 drivers keep working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_CR1_M USART_CR1_M0 + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32.h b/arch/arm/src/stm32l4/stm32.h index 30d93ed49fdf9..fb6b13c399607 100644 --- a/arch/arm/src/stm32l4/stm32.h +++ b/arch/arm/src/stm32l4/stm32.h @@ -52,7 +52,6 @@ #include "stm32l4_rtc.h" #include "stm32l4_sdmmc.h" #include "stm32l4_spi.h" -#include "stm32l4_tim.h" #include "stm32l4_uart.h" #include "stm32l4_usbdev.h" #include "stm32l4_wdg.h" diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c deleted file mode 100644 index d22c0e8d5a9e4..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ /dev/null @@ -1,1271 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_1wire.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Links: - * https://www.maximintegrated.com/en/app-notes/index.mvp/id/214 - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32l4_rcc.h" -#include "stm32l4_gpio.h" -#include "stm32l4_1wire.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BUS_TIMEOUT 5 /* tv_sec */ - -#define RESET_BAUD 9600 -#define RESET_TX 0xF0 -#define TIMESLOT_BAUD 115200 -#define READ_TX 0xFF -#define READ_RX1 0xFF -#define WRITE_TX0 0x00 -#define WRITE_TX1 0xFF - -#define PIN_OPENDRAIN(gpio) ((gpio) | GPIO_OPENDRAIN) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* 1-Wire bus task */ - -enum stm32_1wire_msg_e -{ - ONEWIRETASK_NONE = 0, - ONEWIRETASK_RESET, - ONEWIRETASK_WRITE, - ONEWIRETASK_READ, - ONEWIRETASK_WRITEBIT, - ONEWIRETASK_READBIT -}; - -struct stm32_1wire_msg_s -{ - enum stm32_1wire_msg_e task; /* Task */ - uint8_t *buffer; /* Task buffer */ - int buflen; /* Buffer length */ -}; - -/* 1-Wire device hardware configuration */ - -struct stm32_1wire_config_s -{ - const uint32_t usartbase; /* Base address of USART registers */ - const uint32_t apbclock; /* PCLK 1 or 2 frequency */ - const uint32_t data_pin; /* GPIO configuration for DATA */ - const uint8_t irq; /* IRQ associated with this USART */ -}; - -/* 1-Wire device Private Data */ - -struct stm32_1wire_priv_s -{ - const struct stm32_1wire_config_s *config; /* Port configuration */ - volatile int refs; /* Reference count */ - mutex_t lock; /* Mutual exclusion mutex */ - sem_t sem_isr; /* Interrupt wait semaphore */ - int baud; /* Baud rate */ - const struct stm32_1wire_msg_s *msgs; /* Messages data */ - uint8_t *byte; /* Current byte */ - uint8_t bit; /* Current bit */ - volatile int result; /* Exchange result */ -#ifdef CONFIG_PM - struct pm_callback_s pm_cb; /* PM callbacks */ -#endif -}; - -/* 1-Wire device, Instance */ - -struct stm32_1wire_inst_s -{ - const struct onewire_ops_s *ops; /* Standard 1-Wire operations */ - struct stm32_1wire_priv_s *priv; /* Common driver private data structure */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, - int offset); -static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, - int offset, uint32_t value); -static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv); -static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch); -static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv); -static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, - bool on); -static int stm32_1wire_init(struct stm32_1wire_priv_s *priv); -static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv); -static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, - const struct stm32_1wire_msg_s *msgs, - int count); -static int stm32_1wire_isr(int irq, void *context, void *arg); -static int stm32_1wire_reset(struct onewire_dev_s *dev); -static int stm32_1wire_write(struct onewire_dev_s *dev, - const uint8_t *buffer, int buflen); -static int stm32_1wire_read(struct onewire_dev_s *dev, uint8_t *buffer, - int buflen); -static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, - const uint8_t *txbuffer, int txbuflen, - uint8_t *rxbuffer, int rxbuflen); -static int stm32_1wire_writebit(struct onewire_dev_s *dev, - const uint8_t *bit); -static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit); -#ifdef CONFIG_PM -static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* 1-Wire device structures */ - -#ifdef CONFIG_STM32_USART1_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire1_config = -{ - .usartbase = STM32_USART1_BASE, - .apbclock = STM32_PCLK2_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), - .irq = STM32_IRQ_USART1, -}; - -static struct stm32_1wire_priv_s stm32_1wire1_priv = -{ - .config = &stm32_1wire1_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -#ifdef CONFIG_STM32_USART2_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire2_config = -{ - .usartbase = STM32_USART2_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), - .irq = STM32_IRQ_USART2, -}; - -static struct stm32_1wire_priv_s stm32_1wire2_priv = -{ - .config = &stm32_1wire2_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -#ifdef CONFIG_STM32_USART3_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire3_config = -{ - .usartbase = STM32_USART3_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), - .irq = STM32_IRQ_USART3, -}; - -static struct stm32_1wire_priv_s stm32_1wire3_priv = -{ - .config = &stm32_1wire3_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -#ifdef CONFIG_STM32_UART4_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire4_config = -{ - .usartbase = STM32_UART4_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), - .irq = STM32_IRQ_UART4, -}; - -static struct stm32_1wire_priv_s stm32_1wire4_priv = -{ - .config = &stm32_1wire4_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -#ifdef CONFIG_STM32_UART5_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire5_config = -{ - .usartbase = STM32_UART5_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), - .irq = STM32_IRQ_UART5, -}; - -static struct stm32_1wire_priv_s stm32_1wire5_priv = -{ - .config = &stm32_1wire5_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -/* Device Structures, Instantiation */ - -static const struct onewire_ops_s stm32_1wire_ops = -{ - .reset = stm32_1wire_reset, - .write = stm32_1wire_write, - .read = stm32_1wire_read, - .exchange = stm32_1wire_exchange, - .writebit = stm32_1wire_writebit, - .readbit = stm32_1wire_readbit -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_1wire_in - ****************************************************************************/ - -static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, - int offset) -{ - return getreg32(priv->config->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32_1wire_out - ****************************************************************************/ - -static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, - int offset, uint32_t value) -{ - putreg32(value, priv->config->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32_1wire_recv - * - * Description: - * This method will recv one byte on the USART - * - ****************************************************************************/ - -static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) -{ - return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; -} - -/**************************************************************************** - * Name: stm32_1wire_send - * - * Description: - * This method will send one byte on the USART - * - ****************************************************************************/ - -static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) -{ - stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); -} - -/**************************************************************************** - * Name: stm32_1wire_set_baud - * - * Description: - * Set the serial line baud. - * - ****************************************************************************/ - -static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) -{ - /* This first implementation is for U[S]ARTs that support oversampling - * by 8 in additional to the standard oversampling by 16. - */ - - uint32_t usartdiv8; - uint32_t cr1; - uint32_t brr; - bool enabled; - - /* If UART was enabled (UE was set), temporarily disable it - * for baud changing. - */ - - cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - - enabled = cr1 & USART_CR1_UE; - if (enabled) - { - cr1 &= ~USART_CR1_UE; - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); - } - - /* In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / usartdiv8 - * usartdiv8 = 2 * fCK / baud - */ - - usartdiv8 = ((priv->config->apbclock << 1) + (priv->baud >> 1)) / - priv->baud; - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / usartdiv16 - * usartdiv16 = fCK / baud - * = 2 * usartdiv8 - */ - - /* Use oversample by 8 only if the divisor is small. But what is small? */ - - if (usartdiv8 > 100) - { - /* Use usartdiv16 */ - - brr = (usartdiv8 + 1) >> 1; - - /* Clear oversampling by 8 to enable oversampling by 16 */ - - cr1 &= ~USART_CR1_OVER8; - } - else - { - DEBUGASSERT(usartdiv8 >= 8); - - /* Perform mysterious operations on bits 0-3 */ - - brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); - - /* Set oversampling by 8 */ - - cr1 |= USART_CR1_OVER8; - } - - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); - stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); - - if (enabled) - { - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_UE); - } -} - -/**************************************************************************** - * Name: stm32_1wire_set_apb_clock - * - * Description: - * Enable or disable APB clock for the USART peripheral - * - * Input Parameters: - * priv - A reference to the 1-Wire driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, - bool on) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t rcc_en; - uint32_t regaddr; - - /* Determine which USART to configure */ - - switch (config->usartbase) - { - default: - return; - -#ifdef CONFIG_STM32_USART1_1WIREDRIVER - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif - -#ifdef CONFIG_STM32_USART2_1WIREDRIVER - case STM32_USART2_BASE: - rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif - -#ifdef CONFIG_STM32_USART3_1WIREDRIVER - case STM32_USART3_BASE: - rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif - -#ifdef CONFIG_STM32_UART4_1WIREDRIVER - case STM32_UART4_BASE: - rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif - -#ifdef CONFIG_STM32_UART5_1WIREDRIVER - case STM32_UART5_BASE: - rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif - } - - /* Enable/disable APB 1/2 clock for USART */ - - if (on) - { - modifyreg32(regaddr, 0, rcc_en); - } - else - { - modifyreg32(regaddr, rcc_en, 0); - } -} - -/**************************************************************************** - * Name: stm32_1wire_init - * - * Description: - * Setup the 1-Wire hardware, ready for operation with defaults - * - ****************************************************************************/ - -static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t regval; - int ret; - - /* Enable USART APB1/2 clock */ - - stm32_1wire_set_apb_clock(priv, true); - - /* Configure CR2 - * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits - * Set LBDIE - */ - - regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | - USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); - regval |= USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure CR1 - * Clear TE, REm, all interrupt enable bits, PCE, PS and M - * Set RXNEIE - */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | - USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); - regval |= USART_CR1_RXNEIE; - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure CR3 - * Clear CTSE, RTSE, and all interrupt enable bits - * Set ONEBIT, HDSEL and EIE - */ - - regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | - USART_CR3_EIE); - regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); - - /* Set baud rate */ - - priv->baud = RESET_BAUD; - stm32_1wire_set_baud(priv); - - /* Enable Rx, Tx, and the USART */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure pins for USART use */ - - stm32_configgpio(config->data_pin); - - ret = irq_attach(config->irq, stm32_1wire_isr, priv); - if (ret == OK) - { - up_enable_irq(config->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_1wire_deinit - * - * Description: - * Shutdown the 1-Wire hardware - * - ****************************************************************************/ - -static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t regval; - - up_disable_irq(config->irq); - irq_detach(config->irq); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(config->data_pin); - - /* Disable RXNEIE, Rx, Tx, and the USART */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Clear LBDIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); - regval &= ~USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); - - /* Clear ONEBIT, HDSEL and EIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); - - /* Disable USART APB1/2 clock */ - - stm32_1wire_set_apb_clock(priv, false); - - return OK; -} - -/**************************************************************************** - * Name: stm32_1wire_exec - * - * Description: - * Execute 1-Wire task - ****************************************************************************/ - -static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, - const struct stm32_1wire_msg_s *msgs, - int count) -{ - irqstate_t irqs; - int index; - int ret; - - /* Lock out other clients */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - priv->result = ERROR; - - for (index = 0; index < count; index++) - { - switch (msgs[index].task) - { - case ONEWIRETASK_NONE: - priv->result = OK; - break; - - case ONEWIRETASK_RESET: - - /* Set baud rate */ - - priv->baud = RESET_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = &msgs[index]; - stm32_1wire_send(priv, RESET_TX); - leave_critical_section(irqs); - - /* Wait. Break on timeout if TX line closed to GND */ - - nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); - break; - - case ONEWIRETASK_WRITE: - case ONEWIRETASK_WRITEBIT: - - /* Set baud rate */ - - priv->baud = TIMESLOT_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = &msgs[index]; - priv->byte = priv->msgs->buffer; - priv->bit = 0; - stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? - WRITE_TX1 : WRITE_TX0); - leave_critical_section(irqs); - - /* Wait. Break on timeout if TX line closed to GND */ - - nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); - break; - - case ONEWIRETASK_READ: - case ONEWIRETASK_READBIT: - - /* Set baud rate */ - - priv->baud = TIMESLOT_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = &msgs[index]; - priv->byte = priv->msgs->buffer; - priv->bit = 0; - stm32_1wire_send(priv, READ_TX); - leave_critical_section(irqs); - - /* Wait. Break on timeout if TX line closed to GND */ - - nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); - break; - } - - if (priv->result != OK) /* break if error */ - { - break; - } - } - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = NULL; - ret = priv->result; - leave_critical_section(irqs); - - /* Release the port for reuse by other clients */ - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_1wire_isr - * - * Description: - * Common Interrupt Service Routine - ****************************************************************************/ - -static int stm32_1wire_isr(int irq, void *context, void *arg) -{ - struct stm32_1wire_priv_s *priv = (struct stm32_1wire_priv_s *)arg; - uint32_t sr; - uint32_t dr; - - DEBUGASSERT(priv != NULL); - - /* Get the masked USART status word. */ - - sr = stm32_1wire_in(priv, STM32_USART_ISR_OFFSET); - - /* Receive loop */ - - if ((sr & USART_ISR_RXNE) != 0) - { - dr = stm32_1wire_recv(priv); - - if (priv->msgs != NULL) - { - switch (priv->msgs->task) - { - case ONEWIRETASK_NONE: - break; - - case ONEWIRETASK_RESET: - priv->msgs = NULL; - priv->result = (dr != RESET_TX) ? OK : -ENODEV; /* if read RESET_TX then no slave */ - nxsem_post(&priv->sem_isr); - break; - - case ONEWIRETASK_WRITE: - if (++priv->bit >= 8) - { - priv->bit = 0; - - /* Done? */ - - if (++priv->byte >= - (priv->msgs->buffer + priv->msgs->buflen)) - { - priv->msgs = NULL; - priv->result = OK; - nxsem_post(&priv->sem_isr); - break; - } - } - - /* Send next bit */ - - stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? - WRITE_TX1 : WRITE_TX0); - break; - - case ONEWIRETASK_READ: - if (dr == READ_RX1) - { - *priv->byte |= (1 << priv->bit); - } - else - { - *priv->byte &= ~(1 << priv->bit); - } - - if (++priv->bit >= 8) - { - priv->bit = 0; - if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ - { - priv->msgs = NULL; - priv->result = OK; - nxsem_post(&priv->sem_isr); - break; - } - } - - /* Recv next bit */ - - stm32_1wire_send(priv, READ_TX); - break; - - case ONEWIRETASK_READBIT: - *priv->byte = (dr == READ_RX1) ? 1 : 0; - - /* Fall through */ - - case ONEWIRETASK_WRITEBIT: - priv->msgs = NULL; - priv->result = OK; - nxsem_post(&priv->sem_isr); - break; - } - } - } - - /* Bounce check. */ - - if ((sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) - { - /* These errors are cleared by writing the corresponding bit to the - * interrupt clear register (ICR). - */ - - stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, - (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); - - if (priv->msgs != NULL) - { - priv->msgs = NULL; - priv->result = ERROR; - nxsem_post(&priv->sem_isr); - } - } - - /* Bounce check. LIN break detection */ - - if ((sr & USART_ISR_LBDF) != 0) - { - stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF); - - if (priv->msgs != NULL) - { - priv->msgs = NULL; - priv->result = ERROR; - nxsem_post(&priv->sem_isr); - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_1wire_reset - * - * Description: - * 1-Wire reset pulse and presence detect. - * - ****************************************************************************/ - -static int stm32_1wire_reset(struct onewire_dev_s *dev) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_RESET - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_write - * - * Description: - * Write 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_write(struct onewire_dev_s *dev, - const uint8_t *buffer, - int buflen) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_WRITE, - [0].buffer = (uint8_t *)buffer, - [0].buflen = buflen - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_read - * - * Description: - * Read 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_read(struct onewire_dev_s *dev, uint8_t *buffer, - int buflen) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_READ, - [0].buffer = buffer, - [0].buflen = buflen - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_exchange - * - * Description: - * 1-Wire reset pulse and presence detect, - * Write 1-Wire data, - * Read 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, - const uint8_t *txbuffer, int txbuflen, - uint8_t *rxbuffer, int rxbuflen) -{ - int result = ERROR; - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - - if (reset) - { - const struct stm32_1wire_msg_s msgs[3] = - { - [0].task = ONEWIRETASK_RESET, - - [1].task = ONEWIRETASK_WRITE, - [1].buffer = (uint8_t *)txbuffer, - [1].buflen = txbuflen, - - [2].task = ONEWIRETASK_READ, - [2].buffer = rxbuffer, - [2].buflen = rxbuflen - }; - - result = stm32_1wire_process(priv, msgs, 3); - } - else - { - const struct stm32_1wire_msg_s msgs[2] = - { - [0].task = ONEWIRETASK_WRITE, - [0].buffer = (uint8_t *)txbuffer, - [0].buflen = txbuflen, - - [1].task = ONEWIRETASK_READ, - [1].buffer = rxbuffer, - [1].buflen = rxbuflen - }; - - result = stm32_1wire_process(priv, msgs, 2); - } - - return result; -} - -/**************************************************************************** - * Name: stm32_1wire_writebit - * - * Description: - * Write one bit of 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_writebit(struct onewire_dev_s *dev, - const uint8_t *bit) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_WRITEBIT, - [0].buffer = (uint8_t *)bit, - [0].buflen = 1 - }; - - DEBUGASSERT(*bit == 0 || *bit == 1); - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_readbit - * - * Description: - * Sample one bit of 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_READBIT, - [0].buffer = bit, - [0].buflen = 1 - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a - * warning that the system is about to enter into a new power state. The - * driver should begin whatever operations that may be required to enter - * power state. The driver may abort the state change mode by returning - * a non-zero value from the callback function. - * - * Input Parameters: - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state - * data at the end of the structure. - * domain - Identifies the activity domain of the state change - * pmstate - Identifies the new PM state - * - * Returned Value: - * 0 (OK) means the event was successfully processed and that the driver - * is prepared for the PM state change. Non-zero means that the driver - * is not prepared to perform the tasks needed achieve this power setting - * and will cause the state change to be aborted. NOTE: The prepare - * method will also be recalled when reverting from lower back to higher - * power consumption modes (say because another driver refused a lower - * power state change). Drivers are not permitted to return non-zero - * values when reverting back to higher power consumption modes! - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - struct stm32_1wire_priv_s *priv = - (struct stm32_1wire_priv_s *)((char *)cb - - offsetof(struct stm32_1wire_priv_s, pm_cb)); - - /* Logic to prepare for a reduced power state goes here. */ - - switch (pmstate) - { - case PM_NORMAL: - case PM_IDLE: - break; - - case PM_STANDBY: - case PM_SLEEP: - - /* Check if exclusive lock for 1-Wire bus is held. */ - - if (nxmutex_is_locked(&priv->lock)) - { - /* Exclusive lock is held, do not allow entry to deeper PM - * states. - */ - - return -EBUSY; - } - - break; - - default: - - /* Should not get here */ - - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_1wireinitialize - * - * Description: - * Initialize the selected 1-Wire port. And return a unique instance of - * struct onewire_dev_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple 1-Wire interfaces) - * - * Returned Value: - * Valid 1-Wire device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct onewire_dev_s *stm32_1wireinitialize(int port) -{ - struct stm32_1wire_priv_s *priv = NULL; /* Private data of device with multiple instances */ - struct stm32_1wire_inst_s *inst = NULL; /* Device, single instance */ - - /* Get 1-Wire private structure */ - - switch (port) - { -#ifdef CONFIG_STM32_USART1_1WIREDRIVER - case 1: - priv = &stm32_1wire1_priv; - break; -#endif - -#ifdef CONFIG_STM32_USART2_1WIREDRIVER - case 2: - priv = &stm32_1wire2_priv; - break; -#endif - -#ifdef CONFIG_STM32_USART3_1WIREDRIVER - case 3: - priv = &stm32_1wire3_priv; - break; -#endif - -#ifdef CONFIG_STM32_UART4_1WIREDRIVER - case 4: - priv = &stm32_1wire4_priv; - break; -#endif - -#ifdef CONFIG_STM32_UART5_1WIREDRIVER - case 5: - priv = &stm32_1wire5_priv; - break; -#endif - - default: - return NULL; - } - - /* Allocate instance */ - - inst = kmm_malloc(sizeof(*inst)); - if (inst == NULL) - { - return NULL; - } - - /* Initialize instance */ - - inst->ops = &stm32_1wire_ops; - inst->priv = priv; - - /* Initialize private data for the first time, increment reference count, - * power-up hardware and configure GPIOs. - */ - - nxmutex_lock(&priv->lock); - if (priv->refs++ == 0) - { - stm32_1wire_init(priv); - -#ifdef CONFIG_PM - /* Register to receive power management callbacks */ - - DEBUGVERIFY(pm_register(&priv->pm_cb)); -#endif - } - - nxmutex_unlock(&priv->lock); - return (struct onewire_dev_s *)inst; -} - -/**************************************************************************** - * Name: stm32_1wireuninitialize - * - * Description: - * De-initialize the selected 1-Wire port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_1wireinitialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_1wireuninitialize(struct onewire_dev_s *dev) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - - DEBUGASSERT(priv != NULL); - - /* Decrement reference count and check for underflow */ - - if (priv->refs == 0) - { - return ERROR; - } - - nxmutex_lock(&priv->lock); - if (--priv->refs) - { - nxmutex_unlock(&priv->lock); - kmm_free(priv); - return OK; - } - -#ifdef CONFIG_PM - /* Unregister power management callbacks */ - - pm_unregister(&priv->pm_cb); -#endif - - /* Disable power and other HW resource (GPIO's) */ - - stm32_1wire_deinit(priv); - nxmutex_unlock(&priv->lock); - - /* Free instance */ - - kmm_free(dev); - return OK; -} diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.h b/arch/arm/src/stm32l4/stm32l4_1wire.h deleted file mode 100644 index f76918de269c2..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_1wire.h +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_1wire.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32l4_uart.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_1wireinitialize - * - * Description: - * Initialize the selected 1-Wire port. And return a unique instance of - * struct struct onewire_dev_s. This function may be called to obtain - * multiple instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple 1-Wire interfaces) - * - * Returned Value: - * Valid 1-Wire device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct onewire_dev_s *stm32_1wireinitialize(int port); - -/**************************************************************************** - * Name: stm32_1wireuninitialize - * - * Description: - * De-initialize the selected 1-Wire port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_1wireinitialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_1wireuninitialize(struct onewire_dev_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index c1e4c5730a293..a2200f11bb95a 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -46,7 +46,7 @@ #include "chip.h" #include "stm32l4_rcc.h" -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "stm32l4_dma.h" #include "stm32l4_adc.h" diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index f6d25a49c6de8..b70b4b9d420ef 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -44,6 +44,7 @@ #include "stm32l4_dac.h" #include "stm32l4_rcc.h" #include "stm32l4_dma.h" +#include "hardware/stm32l4_tim.h" #ifdef CONFIG_DAC diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c index 82472993748af..b186b6bff4c6c 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c @@ -43,7 +43,7 @@ #include "chip.h" #include "stm32l4_rcc.h" -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "stm32l4_dma.h" #include "stm32l4_dfsdm.h" diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index ae4dbd6729f01..0cc7ec2b191a1 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -93,27 +93,27 @@ # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM1_BASE # define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN -#elif defined(CONFIG_STM32L4_TIM3_DFSDM) +#elif defined(CONFIG_STM32_TIM3_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM3_BASE # define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN -#elif defined(CONFIG_STM32L4_TIM4_DFSDM) +#elif defined(CONFIG_STM32_TIM4_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM4_BASE # define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN -#elif defined(CONFIG_STM32L4_TIM6_DFSDM) +#elif defined(CONFIG_STM32_TIM6_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM6_BASE # define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN -#elif defined(CONFIG_STM32L4_TIM7_DFSDM) +#elif defined(CONFIG_STM32_TIM7_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM7_BASE # define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM7_CLKIN -#elif defined(CONFIG_STM32L4_TIM8_DFSDM) +#elif defined(CONFIG_STM32_TIM8_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM8_BASE # define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN -#elif defined(CONFIG_STM32L4_TIM16_DFSDM) +#elif defined(CONFIG_STM32_TIM16_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM16_BASE # define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM16_CLKIN diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c deleted file mode 100644 index c768b6237e352..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ /dev/null @@ -1,275 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_freerun.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "stm32l4_freerun.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_handler - * - * Description: - * Timer interrupt callback. When the freerun timer counter overflows, - * this interrupt will occur. We will just increment an overflow count. - * - * Input Parameters: - * tch - The handle that represents the timer state - * arg - An opaque argument provided when the interrupt was registered - * sr - The value of the timer interrupt status register at the time - * that the interrupt occurred. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int stm32_freerun_handler(int irq, void *context, void *arg) -{ - struct stm32_freerun_s *freerun = - (struct stm32_freerun_s *)arg; - - DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); - freerun->overflow++; - - STM32_TIM_ACKINT(freerun->tch, 0); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, - int chan, - uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(freerun != NULL && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - freerun->frequency = frequency; - - freerun->tch = stm32_tim_init(chan); - if (!freerun->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(freerun->tch, frequency); - - /* Initialize the remaining fields in the state structure and return - * success. - */ - - freerun->chan = chan; - freerun->overflow = 0; - - /* Set up to receive the callback when the counter overflow occurs */ - - STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); - - /* Set timer period */ - - STM32_TIM_SETPERIOD(freerun->tch, UINT32_MAX); - - /* Start the counter */ - - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); - STM32_TIM_ACKINT(freerun->tch, 0); - STM32_TIM_ENABLEINT(freerun->tch, 0); - - return OK; -} - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time from the free-running - * timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts) -{ - uint64_t usec; - uint32_t counter; - uint32_t verify; - uint32_t overflow; - uint32_t sec; - int pending; - irqstate_t flags; - - DEBUGASSERT(freerun && freerun->tch && ts); - - /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32_tc_getpending() will reset the pending - * interrupt status. If we do not handle the overflow here then, it will - * be lost. - */ - - flags = enter_critical_section(); - - overflow = freerun->overflow; - counter = STM32_TIM_GETCOUNTER(freerun->tch); - pending = STM32_TIM_CHECKINT(freerun->tch, 0); - verify = STM32_TIM_GETCOUNTER(freerun->tch); - - /* If an interrupt was pending before we re-enabled interrupts, - * then the overflow needs to be incremented. - */ - - if (pending) - { - STM32_TIM_ACKINT(freerun->tch, 0); - - /* Increment the overflow count and use the value of the - * guaranteed to be AFTER the overflow occurred. - */ - - overflow++; - counter = verify; - - /* Update freerun overflow counter. */ - - freerun->overflow = overflow; - } - - leave_critical_section(flags); - - tmrinfo("counter=%lu (%lu) overflow=%lu, pending=%i\n", - (unsigned long)counter, (unsigned long)verify, - (unsigned long)overflow, pending); - tmrinfo("frequency=%u\n", freerun->frequency); - - /* Convert the whole thing to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = ((((uint64_t)overflow << 32) + (uint64_t)counter) * USEC_PER_SEC) / - freerun->frequency; - - /* And return the value of the timer */ - - sec = (uint32_t)(usec / USEC_PER_SEC); - ts->tv_sec = sec; - ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - tmrinfo("usec=%llu ts=(%jd, %ld)\n", - usec, (intmax_t)ts->tv_sec, ts->tv_nsec); - - return OK; -} - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) -{ - DEBUGASSERT(freerun && freerun->tch); - - /* Now we can disable the timer interrupt and disable the timer. */ - - STM32_TIM_DISABLEINT(freerun->tch, 0); - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); - - /* Free the timer */ - - stm32_tim_deinit(freerun->tch); - freerun->tch = NULL; - - return OK; -} - -#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h deleted file mode 100644 index c1aeacf7afdcb..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ /dev/null @@ -1,144 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_freerun.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "stm32l4_tim.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* The freerun client must allocate an instance of this structure and called - * stm32_freerun_initialize() before using the freerun facilities. The - * client should not access the contents of this structure directly since the - * contents are subject to change. - */ - -struct stm32_freerun_s -{ - uint8_t chan; /* The timer/counter in use */ - uint32_t overflow; /* Timer counter overflow */ - struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ - uint32_t frequency; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts); - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_lsi.c b/arch/arm/src/stm32l4/stm32l4_lsi.c deleted file mode 100644 index ae42b876ca25d..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32l4_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c deleted file mode 100644 index ebacd10a6096c..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ /dev/null @@ -1,460 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_oneshot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "stm32l4_oneshot.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_oneshot_handler(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Common timer interrupt callback. When any oneshot timer interrupt - * expires, this function will be called. It will forward the call to - * the next level up. - * - * Input Parameters: - * oneshot - The state associated with the expired timer - * - * Returned Value: - * Always returns OK - * - ****************************************************************************/ - -static int stm32_oneshot_handler(int irq, void *context, void *arg) -{ - struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *) arg; - oneshot_handler_t oneshot_handler; - void *oneshot_arg; - - tmrinfo("Expired...\n"); - DEBUGASSERT(oneshot != NULL && oneshot->handler); - - /* The clock was stopped, but not disabled when the RC match occurred. - * Disable the TC now and disable any further interrupts. - */ - - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_DISABLEINT(oneshot->tch, 0); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_ACKINT(oneshot->tch, 0); - - /* The timer is no longer running */ - - oneshot->running = false; - - /* Forward the event, clearing out any vestiges */ - - oneshot_handler = (oneshot_handler_t)oneshot->handler; - oneshot->handler = NULL; - oneshot_arg = (void *)oneshot->arg; - oneshot->arg = NULL; - - oneshot_handler(oneshot_arg); - return OK; -} - -/**************************************************************************** - * Name: stm32_allocate_handler - * - * Description: - * Allocate a timer callback handler for the oneshot instance. - * - * Input Parameters: - * oneshot - The state instance the new oneshot timer - * - * Returned Value: - * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. - * - ****************************************************************************/ - -static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) -{ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - int ret = -EBUSY; - int i; - - /* Search for an unused handler */ - - for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) - { - /* Is this handler available? */ - - if (g_oneshot[i] == NULL) - { - /* Yes... assign it to this oneshot */ - - g_oneshot[i] = oneshot; - oneshot->cbndx = i; - ret = OK; - break; - } - } - - return ret; - -#else - if (g_oneshot[0] == NULL) - { - g_oneshot[0] = oneshot; - return OK; - } - - return -EBUSY; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, - int chan, uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(oneshot && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - oneshot->frequency = frequency; - - oneshot->tch = stm32_tim_init(chan); - if (!oneshot->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(oneshot->tch, frequency); - - /* Initialize the remaining fields in the state structure. */ - - oneshot->chan = chan; - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - - /* Assign a callback handler to the oneshot */ - - return stm32_allocate_handler(oneshot); -} - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, - uint64_t *usec) -{ - DEBUGASSERT(oneshot != NULL && usec != NULL); - - *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * - (uint64_t)USEC_PER_SEC; - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts) -{ - uint64_t usec; - uint64_t period; - irqstate_t flags; - - tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", - handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); - DEBUGASSERT(oneshot && handler && ts); - DEBUGASSERT(oneshot->tch); - - /* Was the oneshot already running? */ - - flags = enter_critical_section(); - if (oneshot->running) - { - /* Yes.. then cancel it */ - - tmrinfo("Already running... cancelling\n"); - stm32_oneshot_cancel(oneshot, NULL); - } - - /* Save the new handler and its argument */ - - oneshot->handler = handler; - oneshot->arg = arg; - - /* Express the delay in microseconds */ - - usec = ts->tv_sec * USEC_PER_SEC + - (ts->tv_nsec / NSEC_PER_USEC); - - /* Get the timer counter frequency and determine the number of counts need - * to achieve the requested delay. - * - * frequency = ticks / second - * ticks = seconds * frequency - * = (usecs * frequency) / USEC_PER_SEC; - */ - - period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; - - tmrinfo("usec=%llu period=%08llx\n", usec, period); - DEBUGASSERT(period > 0); - DEBUGASSERT(period <= UINT32_MAX); - - /* Set up to receive the callback when the interrupt occurs */ - - STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); - - /* Set timer period */ - - oneshot->period = (uint32_t)period; - STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); - - /* Start the counter */ - - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - - STM32_TIM_ACKINT(oneshot->tch, 0); - STM32_TIM_ENABLEINT(oneshot->tch, 0); - - /* Enable interrupts. We should get the callback when the interrupt - * occurs. - */ - - oneshot->running = true; - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. ts may be zero in which case the time remaining - * is not returned. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts) -{ - irqstate_t flags; - uint64_t usec; - uint64_t sec; - uint64_t nsec; - uint32_t count; - uint32_t period; - - /* Was the timer running? */ - - flags = enter_critical_section(); - if (!oneshot->running) - { - /* No.. Just return zero timer remaining and successful cancellation. - * This function may execute at a high rate with no timer running - * (as when pre-emption is enabled and disabled). - */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - leave_critical_section(flags); - return OK; - } - - /* Yes.. Get the timer counter and period registers and stop the counter. - * If the counter expires while we are doing this, the counter clock will - * be stopped, but the clock will not be disabled. - * - * The expected behavior is that the counter register will freezes at - * a value equal to the RC register when the timer expires. The counter - * should have values between 0 and RC in all other cased. - * - * REVISIT: This does not appear to be the case. - */ - - tmrinfo("Cancelling...\n"); - - count = STM32_TIM_GETCOUNTER(oneshot->tch); - period = oneshot->period; - - /* Now we can disable the interrupt and stop the timer. */ - - STM32_TIM_DISABLEINT(oneshot->tch, 0); - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - leave_critical_section(flags); - - /* Did the caller provide us with a location to return the time - * remaining? - */ - - if (ts) - { - /* Yes.. then calculate and return the time remaining on the - * oneshot timer. - */ - - tmrinfo("period=%lu count=%lu\n", - (unsigned long)period, (unsigned long)count); - - /* REVISIT: I am not certain why the timer counter value sometimes - * exceeds RC. Might be a bug, or perhaps the counter does not stop - * in all cases. - */ - - if (count >= period) - { - /* No time remaining (?) */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - } - else - { - /* The total time remaining is the difference. Convert that - * to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / - oneshot->frequency; - - /* Return the time remaining in the correct form */ - - sec = usec / USEC_PER_SEC; - nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - ts->tv_sec = sec; - ts->tv_nsec = nsec; - } - - tmrinfo("remaining (%jd, %ld)\n", - (intmax_t)ts->tv_sec, ts->tv_nsec); - } - - return OK; -} - -#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h deleted file mode 100644 index d8e77479d2080..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32l4_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, - uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c deleted file mode 100644 index 12474e6080762..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c +++ /dev/null @@ -1,310 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32l4_oneshot.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of the oneshot timer lower-half - * driver - */ - -struct stm32_oneshot_lowerhalf_s -{ - /* This is the part of the lower half driver that is visible to the upper- - * half client of the driver. This must be the first thing in this - * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. - */ - - struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ - - /* Private lower half data follows */ - - struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg); - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts); -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Lower half operations */ - -static const struct oneshot_operations_s g_oneshot_ops = -{ - .max_delay = stm32_max_delay, - .start = stm32_start, - .cancel = stm32_cancel, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Timer expiration handler - * - * Input Parameters: - * arg - Should be the same argument provided when stm32_oneshot_start() - * was called. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Perhaps the callback was nullified in a race condition with - * stm32_cancel? - */ - - oneshot_process_callback(&priv->lh); -} - -/**************************************************************************** - * Name: stm32_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the maximum delay. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - uint64_t usecs; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); - if (ret >= 0) - { - uint64_t sec = usecs / 1000000; - usecs -= 1000000 * sec; - - ts->tv_sec = sec; - ts->tv_nsec = usecs * 1000; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - - /* Save the callback information and start the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_start(&priv->oneshot, - stm32_oneshot_handler, priv, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * lower Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL); - - /* Cancel the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_cancel(&priv->oneshot, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: oneshot_initialize - * - * Description: - * Initialize the oneshot timer and return a oneshot lower half driver - * instance. - * - * Input Parameters: - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * On success, a non-NULL instance of the oneshot lower-half driver is - * returned. NULL is return on any failure. - * - ****************************************************************************/ - -struct oneshot_lowerhalf_s *oneshot_initialize(int chan, - uint16_t resolution) -{ - struct stm32_oneshot_lowerhalf_s *priv; - int ret; - - /* Allocate an instance of the lower half driver */ - - priv = (struct stm32_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); - - if (priv == NULL) - { - tmrerr("ERROR: Failed to initialized state structure\n"); - return NULL; - } - - /* Initialize the lower-half driver structure */ - - priv->lh.ops = &g_oneshot_ops; - - /* Initialize the contained STM32 oneshot timer */ - - ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); - kmm_free(priv); - return NULL; - } - - return &priv->lh; -} diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c deleted file mode 100644 index 18ca8468adf45..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ /dev/null @@ -1,1189 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32l4_gpio.h" -#include "stm32l4_tim.h" -#include "stm32l4_qencoder.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Timers *******************************************************************/ - -#undef HAVE_32BIT_TIMERS -#undef HAVE_16BIT_TIMERS - -/* On the L4 series, TIM2 and TIM5 are 32-bit. All of the rest are 16-bit */ - -/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ - -#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) -# define HAVE_32BIT_TIMERS 1 -#endif - -/* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) -# define HAVE_16BIT_TIMERS 1 -#endif - -/* The width in bits of each timer */ - -#define TIM1_BITWIDTH 16 -#define TIM2_BITWIDTH 32 -#define TIM3_BITWIDTH 16 -#define TIM4_BITWIDTH 16 -#define TIM5_BITWIDTH 32 -#define TIM8_BITWIDTH 16 - -/* Do we need to support mixed 16- and 32-bit timers */ - -#undef HAVE_MIXEDWIDTH_TIMERS -#if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_FILTER -# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32_QENCODER_ICF -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Encoder pulses prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; /* Lower half callback structure */ - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; /* static onfiguration */ - - bool inuse; /* True: The lower-half driver is in-use */ - -#ifdef HAVE_16BIT_TIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; /* Spinlock */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, - int offset, uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, - int offset, uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv,msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, - int32_t *pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = NULL, /* not supported yet */ - .reset = stm32_reset, - .setindex = NULL, /* not supported yet */ - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM5_QE -static const struct stm32_qeconfig_s g_tim5config = -{ - .timid = 5, - .irq = STM32_IRQ_TIM5, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM5_BITWIDTH, -#endif - .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32_TIM5_QEPSC, - .ti1cfg = GPIO_TIM5_CH1IN, - .ti2cfg = GPIO_TIM5_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim5lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim5config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM8_QE -static const struct stm32_qeconfig_s g_tim8config = -{ - .timid = 8, - .irq = STM32_IRQ_TIM8UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM8_BITWIDTH, -#endif - .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32_TIM8_QEPSC, - .ti1cfg = GPIO_TIM8_CH1IN, - .ti2cfg = GPIO_TIM8_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim8lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim8config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, - int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, - int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, - int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 - " CCMR2: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" - " ARR: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg32(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); - sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - return &g_tim4lower; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - return &g_tim5lower; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - return &g_tim8lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require timer - * interrupts. - * - ****************************************************************************/ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. - * Nothing else is expected. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x0000ffff; - } - else - { - priv->position += (int32_t)0x0000ffff; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifdef HAVE_16BIT_TIMERS - uint16_t regval; - int ret; -#endif - - /* NOTE: - * Clocking should have been enabled in the low-level RCC logic at boot-up - */ - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) - * (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. - * - * Previously, and still in the stm32fx driver, the clock input value - * (CLKIN) was based on the peripheral clock (PCLK) and a multiplier. - * These CLKIN values are provided in the board.h file. - * The prescaler value is then that CLKIN value divided by the configured - * CLKOUT value (minus one). - * - * It was determined that this configuration makes no sense for a qencoder. - * If we are doing precise shaft positioning, each qe pulse is important. - * So the STM32L4 has direct config control on the pulse count prescaler, - * instead of deriving this value from an obscure "output" setting AND the - * timer input clock. This input clock just limits the incoming pulse rate, - * which should be lower than the peripheral clock due to - * resynchronization, but it is the responsibility of the system designer - * to decide the correct prescaler value, because it has a direct influence - * on the encoder resolution. - */ - - stm32_putreg16(priv, - STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1 and TIM8) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * should stop data collection, free any resources, disable timer hardware, - * and put the system into the lowest possible power usage state * - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - regaddr = STM32_RCC_APB1RSTR1; - resetbit = RCC_APB1RSTR1_TIM2RST; - break; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - regaddr = STM32_RCC_APB1RSTR1; - resetbit = RCC_APB1RSTR1_TIM3RST; - break; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - regaddr = STM32_RCC_APB1RSTR1; - resetbit = RCC_APB1RSTR1_TIM4RST; - break; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - regaddr = STM32_RCC_APB1RSTR1; - resetbit = RCC_APB1RSTR1_TIM5RST; - break; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM8RST; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32_dumpregs(priv, "After stop"); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, - int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. - * Interrupts are disabled to make this atomic (if possible) - */ - - flags = spin_lock_irqsave(&priv->lock); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - spin_unlock_irqrestore(&priv->lock, flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, - int cmd, unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the priv-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#endif /* CONFIG_SENSORS_QENCODER */ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h deleted file mode 100644 index 4b07b1fd42a00..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.h +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32L4_TIMn is defined - * then the CONFIG_STM32L4_TIMn_QE must also be defined to indicate that - * timer "n" is intended to be used for as a quadrature encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder - */ - -#undef CONFIG_STM32L4_TIM6_QE -#undef CONFIG_STM32L4_TIM7_QE -#undef CONFIG_STM32L4_TIM9_QE -#undef CONFIG_STM32L4_TIM10_QE -#undef CONFIG_STM32L4_TIM11_QE -#undef CONFIG_STM32L4_TIM12_QE -#undef CONFIG_STM32L4_TIM13_QE -#undef CONFIG_STM32L4_TIM14_QE - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic.. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. - * 'tim' must be an element of {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index b316142dab8c2..e6917ba10f445 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -44,6 +44,17 @@ # error "Unsupported STM32L4 chip" #endif +/* Compatibility with the single APB1ENR clock-enable register of F1/F2/F4. + * This part splits APB1ENR into APB1ENR1/APB1ENR2; alias the legacy APB1ENR + * USART clock-enable names so the shared M3/M4 drivers keep working. + */ + +#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 +#define RCC_APB1ENR_USART2EN RCC_APB1ENR1_USART2EN +#define RCC_APB1ENR_USART3EN RCC_APB1ENR1_USART3EN +#define RCC_APB1ENR_UART4EN RCC_APB1ENR1_UART4EN +#define RCC_APB1ENR_UART5EN RCC_APB1ENR1_UART5EN + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_tickless.c b/arch/arm/src/stm32l4/stm32l4_tickless.c index 541399ba03829..a10568f71076e 100644 --- a/arch/arm/src/stm32l4/stm32l4_tickless.c +++ b/arch/arm/src/stm32l4/stm32l4_tickless.c @@ -78,8 +78,8 @@ #include #include -#include "stm32l4_oneshot.h" -#include "stm32l4_freerun.h" +#include "stm32_oneshot.h" +#include "stm32_freerun.h" #ifdef CONFIG_SCHED_TICKLESS diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c deleted file mode 100644 index 9fadfeef70735..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ /dev/null @@ -1,1912 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32l4_gpio.h" -#include "stm32l4_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. - * Such special purposes include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32L4_TIMn is defined then the CONFIG_STM32L4_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32L4_TIMn is - * defined then CONFIG_STM32L4_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_DAC may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32L4_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32L4_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32L4_TIM7_PWM) || defined (CONFIG_STM32L4_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32L4_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32L4_TIM15_DAC) || defined(CONFIG_STM32L4_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32L4_TIM16_ADC) || \ - defined(CONFIG_STM32L4_TIM16_DAC) || defined(CONFIG_STM32L4_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32L4_TIM17_ADC) || \ - defined(CONFIG_STM32L4_TIM17_DAC) || defined(CONFIG_STM32L4_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ - defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ - defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ - defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif -static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, - uint32_t freq); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setfreq = stm32_tim_setfreq, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, - .dump_regs = stm32_tim_dumpregs, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the STM32 - * F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the STM32 - * F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - /* TODO: - * Add support for input capture and bipolar dual outputs for TIM8 - */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_dumpregs - ****************************************************************************/ - -static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) -{ - struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; - - ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CR2_OFFSET), - stm32_getreg16(dev, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(dev, STM32_GTIM_DIER_OFFSET) - ); - ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32_getreg16(dev, STM32_GTIM_SR_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) - ); - ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET), - stm32_getreg16(dev, STM32_GTIM_ARR_OFFSET) - ); - ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32_getreg16(dev, STM32_GTIM_CCR1_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCR2_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCR3_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCR4_OFFSET) - ); - - if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) - { - ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(dev, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(dev, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(dev, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); - } - else - { - ainfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(dev, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); - } -} - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - break; - - case STM32_TIM_MODE_UP: - val &= ~GTIM_CR1_DIR; - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: - * Interrupts are generated on compare, when counting down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setfreq - ****************************************************************************/ - -static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - uint32_t reload; - uint32_t timclk; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - * - * Calculate optimal values for the timer prescaler and for the timer - * reload register. If freq is the desired frequency, then - * - * reload = timclk / freq - * reload = (pclck / prescaler) / freq - * - * There are many solutions to do this, but the best solution will be the - * one that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= prescaler <= 65536 - * 1 <= reload <= 65535 - * - * So ( prescaler = pclck / 65535 / freq ) would be optimal. - */ - - prescaler = (freqin / freq + 65534) / 65535; - - /* We need to decrement value for '1', but only if that will not to - * cause underflow. - */ - - if (prescaler < 1) - { - awarn("WARNING: Prescaler underflowed.\n"); - prescaler = 1; - } - - /* Check for overflow as well. */ - - if (prescaler > 65536) - { - awarn("WARNING: Prescaler overflowed.\n"); - prescaler = 65536; - } - - timclk = freqin / prescaler; - - reload = timclk / freq; - if (reload < 1) - { - awarn("WARNING: Reload value underflowed.\n"); - reload = 1; - } - else if (reload > 65535) - { - awarn("WARNING: Reload value overflowed.\n"); - reload = 65535; - } - - /* Set the reload and prescaler values */ - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); - stm32_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); - - return (timclk / reload); -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); - - /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. - * reset it it result when not TIM2 or TIM5. - */ - -#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: -#endif - return counter; - - default: - return counter & 0x0000ffff; - } -#else - return counter & 0x0000ffff; -#endif -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 3) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -#if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -#if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -#if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -#if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -#if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & GTIM_SR_UIF) ? 1 : 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h deleted file mode 100644 index dbb4ffe1096bb..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ /dev/null @@ -1,231 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32l4_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active - * high when counter < compare - */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - -#if 0 - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC = open collector mode -#endif -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); - - /* Debug */ - - void (*dump_regs)(struct stm32_tim_dev_s *dev); -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c deleted file mode 100644 index 1c60f9abcf5e6..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ /dev/null @@ -1,626 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileCopyrightText: 2016 Sebastien Lorquet All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * SPDX-FileContributor: dev@ziggurat29.com - * SPDX-FileContributor: Sebastien Lorquet - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32l4_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = - (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, 0); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower- half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32l5/CMakeLists.txt b/arch/arm/src/stm32l5/CMakeLists.txt index cfd801d08ab3e..dfd692b4daf4a 100644 --- a/arch/arm/src/stm32l5/CMakeLists.txt +++ b/arch/arm/src/stm32l5/CMakeLists.txt @@ -35,9 +35,7 @@ list( stm32l5_start.c stm32l5_spi.c stm32l5_lse.c - stm32l5_lsi.c stm32l5_pwr.c - stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c) @@ -45,10 +43,6 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32l5_idle.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32l5_tim_lowerhalf.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32l5_userspace.c stm32l5_mpuinit.c) endif() diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index b01e736c4c8f7..48988f3a2b3ae 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -36,17 +36,13 @@ CHIP_ASRCS = CHIP_CSRCS += stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c CHIP_CSRCS += stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c -CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c -CHIP_CSRCS += stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c +CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c +CHIP_CSRCS += stm32l5_pwr.c stm32l5_flash.c stm32l5_timerisr.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32l5_idle.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32l5_tim_lowerhalf.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32l5_userspace.c stm32l5_mpuinit.c endif diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h b/arch/arm/src/stm32l5/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h rename to arch/arm/src/stm32l5/hardware/stm32_rcc.h index 64d4f7215e239..e9e15bb3f62e4 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h +++ b/arch/arm/src/stm32l5/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h + * arch/arm/src/stm32l5/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_RCC_H /**************************************************************************** * Included Files @@ -866,4 +866,4 @@ # define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT) #endif /* CONFIG_STM32_STM32L562XX */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l5/stm32.h b/arch/arm/src/stm32l5/stm32.h index da1a85b295cdc..719d814abf159 100644 --- a/arch/arm/src/stm32l5/stm32.h +++ b/arch/arm/src/stm32l5/stm32.h @@ -43,7 +43,6 @@ #include "stm32l5_pwr.h" #include "stm32l5_rcc.h" #include "stm32l5_spi.h" -#include "stm32l5_tim.h" #include "stm32l5_uart.h" #include "stm32l5_lowputc.h" diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c deleted file mode 100644 index 6d57b07aac4ae..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32l5_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index bfb2c42d2ae21..c994aa25f25c9 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -33,7 +33,7 @@ #include "chip.h" #if defined(CONFIG_STM32_STM32L562XX) -# include "hardware/stm32l562xx_rcc.h" +# include "hardware/stm32_rcc.h" #else # error "Unsupported STM32L5 chip" #endif diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c deleted file mode 100644 index 0a335f83fe84b..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ /dev/null @@ -1,1695 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32l5_gpio.h" -#include "stm32l5_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32L5_TIMn is defined then the CONFIG_STM32L5_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32L5_TIMn is - * defined then CONFIG_STM32L5_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32L5_TIMn is defined then - * CONFIG_STM32L5_TIMn_DAC may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32L5_TIMn is defined then - * CONFIG_STM32L5_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32L5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32L5_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32L5_TIM7_PWM) || defined (CONFIG_STM32L5_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32L5_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32L5_TIM15_DAC) || defined(CONFIG_STM32L5_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32L5_TIM16_ADC) || \ - defined(CONFIG_STM32L5_TIM16_DAC) || defined(CONFIG_STM32L5_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32L5_TIM17_ADC) || \ - defined(CONFIG_STM32L5_TIM17_DAC) || defined(CONFIG_STM32L5_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ - defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ - defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ - defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the - * STM32L5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the - * STM32L5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); - - /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. - * reset it it result when not TIM2 or TIM5. - */ - -#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: -#endif - return counter; - - default: - return counter & 0x0000ffff; - } -#else - return counter & 0x0000ffff; -#endif -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -#if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -#if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -#if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -#if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -#if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & GTIM_SR_UIF) ? 1 : 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h deleted file mode 100644 index 5a787e122f085..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ /dev/null @@ -1,222 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_TIM_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32l5_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - -#if 0 - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC = open collector mode -#endif -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_TIM_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c deleted file mode 100644 index 789b50c7bdc61..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ /dev/null @@ -1,607 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32l5_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = - (struct stm32_lowerhalf_s *)arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, 0); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32u5/CMakeLists.txt b/arch/arm/src/stm32u5/CMakeLists.txt index 70f5a875c1306..c247cb91bfc3a 100644 --- a/arch/arm/src/stm32u5/CMakeLists.txt +++ b/arch/arm/src/stm32u5/CMakeLists.txt @@ -32,10 +32,8 @@ set(SRCS stm32_start.c stm32_spi.c stm32_lse.c - stm32_lsi.c stm32u5xx_rcc.c stm32_pwr.c - stm32_tim.c stm32_flash.c stm32_timerisr.c) @@ -43,10 +41,6 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) endif() diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 95e927f8b46e0..e167ca164c3a3 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -115,6 +115,8 @@ config STM32_STM32U5A5XX select STM32_HAVE_FDCAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -145,6 +147,8 @@ config STM32_STM32U585XX select STM32_HAVE_FDCAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 diff --git a/arch/arm/src/stm32u5/Make.defs b/arch/arm/src/stm32u5/Make.defs index a884bf0cbf33a..11afa0aff67df 100644 --- a/arch/arm/src/stm32u5/Make.defs +++ b/arch/arm/src/stm32u5/Make.defs @@ -36,17 +36,13 @@ CHIP_ASRCS = CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_i2c.c CHIP_CSRCS += stm32_serial.c stm32_start.c -CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32_lsi.c stm32u5xx_rcc.c -CHIP_CSRCS += stm32_pwr.c stm32_tim.c stm32_flash.c stm32_timerisr.c +CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32u5xx_rcc.c +CHIP_CSRCS += stm32_pwr.c stm32_flash.c stm32_timerisr.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c endif diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h b/arch/arm/src/stm32u5/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h rename to arch/arm/src/stm32u5/hardware/stm32_rcc.h index 3e5ca6181a38c..8b658da402b77 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h +++ b/arch/arm/src/stm32u5/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h + * arch/arm/src/stm32u5/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5xx_RCC_H -#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5xx_RCC_H +#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_RCC_H /**************************************************************************** * Included Files diff --git a/arch/arm/src/stm32u5/hardware/stm32_tim.h b/arch/arm/src/stm32u5/hardware/stm32u5_tim.h similarity index 99% rename from arch/arm/src/stm32u5/hardware/stm32_tim.h rename to arch/arm/src/stm32u5/hardware/stm32u5_tim.h index e180a60d773a3..1ffca4e83683b 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32u5/hardware/stm32_tim.h + * arch/arm/src/stm32u5/hardware/stm32u5_tim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32u5/stm32.h b/arch/arm/src/stm32u5/stm32.h index b53e091765453..35fef1862fb72 100644 --- a/arch/arm/src/stm32u5/stm32.h +++ b/arch/arm/src/stm32u5/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" diff --git a/arch/arm/src/stm32u5/stm32_lsi.c b/arch/arm/src/stm32u5/stm32_lsi.c deleted file mode 100644 index 34e53e22ac4a2..0000000000000 --- a/arch/arm/src/stm32u5/stm32_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC BDCR register. - */ - - modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_BDCR) & RCC_BDCR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Disable the Internal Low-Speed (LSI) RC Oscillator by resetting the - * LSION bit the RCC BDCR register. - */ - - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32u5/stm32_rcc.h b/arch/arm/src/stm32u5/stm32_rcc.h index ae75e4a235666..7354a096ab031 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.h +++ b/arch/arm/src/stm32u5/stm32_rcc.h @@ -33,7 +33,7 @@ #include "chip.h" #if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) -# include "hardware/stm32u5xx_rcc.h" +# include "hardware/stm32_rcc.h" #else # error "Unsupported STM32U5 chip" #endif diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c deleted file mode 100644 index 3f1b5472cd085..0000000000000 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ /dev/null @@ -1,1695 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32U5_TIMn is defined then the CONFIG_STM32U5_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32U5_TIMn is - * defined then CONFIG_STM32U5_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32U5_TIMn is defined then - * CONFIG_STM32U5_TIMn_DAC may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32U5_TIMn is defined then - * CONFIG_STM32U5_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32U5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32U5_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32U5_TIM7_PWM) || defined (CONFIG_STM32U5_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32U5_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32U5_TIM15_DAC) || defined(CONFIG_STM32U5_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32U5_TIM16_ADC) || \ - defined(CONFIG_STM32U5_TIM16_DAC) || defined(CONFIG_STM32U5_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32U5_TIM17_ADC) || \ - defined(CONFIG_STM32U5_TIM17_DAC) || defined(CONFIG_STM32U5_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ - defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ - defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ - defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the - * STM32U5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the - * STM32U5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); - - /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. - * reset it it result when not TIM2 or TIM5. - */ - -#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: -#endif - return counter; - - default: - return counter & 0x0000ffff; - } -#else - return counter & 0x0000ffff; -#endif -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -#if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -#if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -#if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -#if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -#if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & GTIM_SR_UIF) ? 1 : 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32u5/stm32_tim.h b/arch/arm/src/stm32u5/stm32_tim.h deleted file mode 100644 index f61751552dd49..0000000000000 --- a/arch/arm/src/stm32u5/stm32_tim.h +++ /dev/null @@ -1,216 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32U5_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32U5_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32U5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c deleted file mode 100644 index a564a8af52538..0000000000000 --- a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,607 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = - (struct stm32_lowerhalf_s *)arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, 0); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index 03f9157eed58e..5670aff03817e 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -34,9 +34,7 @@ set(SRCS stm32wb_i2c.c stm32wb_start.c stm32wb_rcc_lse.c - stm32wb_rcc_lsi.c stm32wb_pwr.c - stm32wb_tim.c stm32wb_flash.c) if(NOT CONFIG_ARCH_IDLE_CUSTOM) @@ -44,7 +42,7 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) endif() if(CONFIG_TIMER) - list(APPEND SRCS stm32wb_tim_lowerhalf.c) + endif() if(NOT CONFIG_SCHED_TICKLESS) @@ -53,14 +51,6 @@ else() list(APPEND SRCS stm32wb_tickless.c) endif() -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c) -endif() - -if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32wb_freerun.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32wb_userspace.c stm32wb_mpuinit.c) endif() diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index 70a74724de2b0..7926dbd91daba 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -170,6 +170,7 @@ config STM32_STM32WB10 bool default n select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TSC @@ -178,6 +179,7 @@ config STM32_STM32WB15 bool default n select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TSC select STM32_HAVE_LPUART @@ -189,6 +191,7 @@ config STM32_STM32WB30 default n select STM32_HAVE_HSI48 select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 @@ -199,6 +202,7 @@ config STM32_STM32WB50 default n select STM32_HAVE_HSI48 select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 @@ -210,6 +214,7 @@ config STM32_STM32WB35 select STM32_HAVE_HSI48 select STM32_HAVE_DMA2 select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 @@ -227,6 +232,7 @@ config STM32_STM32WB55 select STM32_HAVE_HSI48 select STM32_HAVE_DMA2 select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index 5a4bdcdb88e24..33bd782620d9c 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -33,8 +33,8 @@ include common/stm32/Make.defs CHIP_CSRCS += stm32wb_allocateheap.c stm32wb_exti_gpio.c stm32wb_gpio.c CHIP_CSRCS += stm32wb_irq.c stm32wb_lowputc.c stm32wb_rcc.c stm32wb_spi.c CHIP_CSRCS += stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c -CHIP_CSRCS += stm32wb_rcc_lse.c stm32wb_rcc_lsi.c -CHIP_CSRCS += stm32wb_pwr.c stm32wb_tim.c +CHIP_CSRCS += stm32wb_rcc_lse.c +CHIP_CSRCS += stm32wb_pwr.c CHIP_CSRCS += stm32wb_flash.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) @@ -42,7 +42,6 @@ CHIP_CSRCS += stm32wb_idle.c endif ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32wb_tim_lowerhalf.c endif ifneq ($(CONFIG_SCHED_TICKLESS),y) @@ -51,14 +50,6 @@ else CHIP_CSRCS += stm32wb_tickless.c endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32wb_freerun.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32wb_userspace.c stm32wb_mpuinit.c endif diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h b/arch/arm/src/stm32wb/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32wb/hardware/stm32wb_rcc.h rename to arch/arm/src/stm32wb/hardware/stm32_rcc.h index 568d362051d6f..bd39b2e35ce88 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wb/hardware/stm32wb_rcc.h + * arch/arm/src/stm32wb/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h deleted file mode 100644 index 447d8bdf78441..0000000000000 --- a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h +++ /dev/null @@ -1,1387 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/hardware/stm32wb_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ -#define STM32_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ -#define STM32_TIM_SR_OFFSET 0x0010 /* Status register */ -#define STM32_TIM_EGR_OFFSET 0x0014 /* Event generation register */ -#define STM32_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ -#define STM32_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ -#define STM32_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32_TIM_CNT_OFFSET 0x0024 /* Counter */ -#define STM32_TIM_PSC_OFFSET 0x0028 /* Prescaler */ -#define STM32_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ -#define STM32_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ -#define STM32_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ -#define STM32_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ -#define STM32_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ -#define STM32_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ -#define STM32_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ -#define STM32_TIM_DCR_OFFSET 0x0048 /* DMA control register */ -#define STM32_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ -#define STM32_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ -#define STM32_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ -#define STM32_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ -#define STM32_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ -#define STM32_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ -#define STM32_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ - -/* Register Addresses *******************************************************/ - -/* Advanced Timer TIM1 */ - -#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_TIM_CR1_OFFSET) -#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_TIM_CR2_OFFSET) -#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_TIM_SMCR_OFFSET) -#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_TIM_DIER_OFFSET) -#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_TIM_SR_OFFSET) -#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_TIM_EGR_OFFSET) -#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_TIM_CCMR1_OFFSET) -#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_TIM_CCMR2_OFFSET) -#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_TIM_CCER_OFFSET) -#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_TIM_CNT_OFFSET) -#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_TIM_PSC_OFFSET) -#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_TIM_ARR_OFFSET) -#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_TIM_RCR_OFFSET) -#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_TIM_CCR1_OFFSET) -#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_TIM_CCR2_OFFSET) -#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_TIM_CCR3_OFFSET) -#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_TIM_CCR4_OFFSET) -#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_TIM_BDTR_OFFSET) -#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_TIM_DCR_OFFSET) -#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_TIM_DMAR_OFFSET) -#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_TIM_OR1_OFFSET) -#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_TIM_CCMR3_OFFSET) -#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_TIM_CCR5_OFFSET) -#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_TIM_CCR6_OFFSET) -#define STM32_TIM1_AF1 (STM32_TIM1_BASE + STM32_TIM_AF1_OFFSET) -#define STM32_TIM1_AF2 (STM32_TIM1_BASE + STM32_TIM_AF2_OFFSET) -#define STM32_TIM1_TISEL (STM32_TIM1_BASE + STM32_TIM_TISEL_OFFSET) - -/* General 32-bit Timer TIM2 */ - -#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_TIM_CR1_OFFSET) -#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_TIM_CR2_OFFSET) -#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_TIM_SMCR_OFFSET) -#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_TIM_DIER_OFFSET) -#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_TIM_SR_OFFSET) -#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_TIM_EGR_OFFSET) -#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_TIM_CCMR1_OFFSET) -#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_TIM_CCMR2_OFFSET) -#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_TIM_CCER_OFFSET) -#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_TIM_CNT_OFFSET) -#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_TIM_PSC_OFFSET) -#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_TIM_ARR_OFFSET) -#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_TIM_CCR1_OFFSET) -#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_TIM_CCR2_OFFSET) -#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_TIM_CCR3_OFFSET) -#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_TIM_CCR4_OFFSET) -#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_TIM_DCR_OFFSET) -#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_TIM_DMAR_OFFSET) -#define STM32_TIM2_OR1 (STM32_TIM2_BASE + STM32_TIM_OR1_OFFSET) -#define STM32_TIM2_AF1 (STM32_TIM2_BASE + STM32_TIM_AF1_OFFSET) -#define STM32_TIM2_TISEL (STM32_TIM2_BASE + STM32_TIM_TISEL_OFFSET) - -/* General Timers TIM16/TIM17 */ - -#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_TIM_CR1_OFFSET) -#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_TIM_CR2_OFFSET) -#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_TIM_DIER_OFFSET) -#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_TIM_SR_OFFSET) -#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_TIM_EGR_OFFSET) -#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_TIM_CCMR1_OFFSET) -#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_TIM_CCER_OFFSET) -#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_TIM_CNT_OFFSET) -#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_TIM_PSC_OFFSET) -#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_TIM_ARR_OFFSET) -#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_TIM_RCR_OFFSET) -#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_TIM_CCR1_OFFSET) -#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_TIM_BDTR_OFFSET) -#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_TIM_DCR_OFFSET) -#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_TIM_DMAR_OFFSET) -#define STM32_TIM16_OR1 (STM32_TIM16_BASE + STM32_TIM_OR1_OFFSET) -#define STM32_TIM16_AF1 (STM32_TIM16_BASE + STM32_TIM_AF1_OFFSET) -#define STM32_TIM16_TISEL (STM32_TIM16_BASE + STM32_TIM_TISEL_OFFSET) - -#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_TIM_CR1_OFFSET) -#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_TIM_CR2_OFFSET) -#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_TIM_DIER_OFFSET) -#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_TIM_SR_OFFSET) -#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_TIM_EGR_OFFSET) -#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_TIM_CCMR1_OFFSET) -#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_TIM_CCER_OFFSET) -#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_TIM_CNT_OFFSET) -#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_TIM_PSC_OFFSET) -#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_TIM_ARR_OFFSET) -#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_TIM_RCR_OFFSET) -#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_TIM_CCR1_OFFSET) -#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_TIM_BDTR_OFFSET) -#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_TIM_DCR_OFFSET) -#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_TIM_DMAR_OFFSET) -#define STM32_TIM17_OR1 (STM32_TIM17_BASE + STM32_TIM_OR1_OFFSET) -#define STM32_TIM17_AF1 (STM32_TIM17_BASE + STM32_TIM_AF1_OFFSET) -#define STM32_TIM17_TISEL (STM32_TIM17_BASE + STM32_TIM_TISEL_OFFSET) - -/* Register Value Constants *************************************************/ - -/* Digital Filter options */ - -#define STM32_DF_NOFILT (0x0) /* 0000: No filter */ -#define STM32_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ -#define STM32_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ -#define STM32_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ -#define STM32_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ -#define STM32_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ -#define STM32_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ -#define STM32_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ -#define STM32_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ -#define STM32_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ -#define STM32_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ -#define STM32_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ -#define STM32_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ -#define STM32_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ -#define STM32_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ -#define STM32_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define TIM1_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define TIM1_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define TIM1_CR1_URS (1 << 2) /* Bit 2: Update request source */ -# define TIM1_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */ -# define TIM1_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */ - -#define TIM1_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define TIM1_CR1_DIR (1 << 4) /* Bit 4: Counter direction */ -# define TIM1_CR1_DIR_UP (0 << 4) /* 0: Upcounter mode */ -# define TIM1_CR1_DIR_DOWN (1 << 4) /* 1: Downcounter mode */ - -#define TIM1_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */ -#define TIM1_CR1_CMS_MASK (0x3 << TIM1_CR1_CMS_SHIFT) -# define TIM1_CR1_CMS_EDGE (0x0 << TIM1_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define TIM1_CR1_CMS_CNTR1 (0x1 << TIM1_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define TIM1_CR1_CMS_CNTR2 (0x2 << TIM1_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define TIM1_CR1_CMS_CNTR3 (0x3 << TIM1_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ - -#define TIM1_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define TIM1_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define TIM1_CR1_CKD_MASK (0x3 << TIM1_CR1_CKD_SHIFT) -# define TIM1_CR1_CKD_TCKINT (0x0 << TIM1_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define TIM1_CR1_CKD_2TCKINT (0x1 << TIM1_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define TIM1_CR1_CKD_4TCKINT (0x2 << TIM1_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -#define TIM1_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */ - -#define TIM2_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define TIM2_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define TIM2_CR1_URS (1 << 2) /* Bit 2: Update request source */ -# define TIM2_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */ -# define TIM2_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */ - -#define TIM2_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define TIM2_CR1_DIR (1 << 4) /* Bit 4: Counter direction */ -# define TIM2_CR1_DIR_UP (0 << 4) /* 0: Upcounter mode */ -# define TIM2_CR1_DIR_DOWN (1 << 4) /* 1: Downcounter mode */ - -#define TIM2_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */ -#define TIM2_CR1_CMS_MASK (0x3 << TIM2_CR1_CMS_SHIFT) -# define TIM2_CR1_CMS_EDGE (0x0 << TIM2_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define TIM2_CR1_CMS_CNTR1 (0x1 << TIM2_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define TIM2_CR1_CMS_CNTR2 (0x2 << TIM2_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define TIM2_CR1_CMS_CNTR3 (0x3 << TIM2_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ - -#define TIM2_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define TIM2_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define TIM2_CR1_CKD_MASK (0x3 << TIM2_CR1_CKD_SHIFT) -# define TIM2_CR1_CKD_TCKINT (0x0 << TIM2_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define TIM2_CR1_CKD_2TCKINT (0x1 << TIM2_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define TIM2_CR1_CKD_4TCKINT (0x2 << TIM2_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -#define TIM2_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */ - -#define TIM16_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define TIM16_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define TIM16_CR1_URS (1 << 2) /* Bit 2: Update request source */ -# define TIM16_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */ -# define TIM16_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */ - -#define TIM16_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define TIM16_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define TIM16_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define TIM16_CR1_CKD_MASK (0x3 << TIM16_CR1_CKD_SHIFT) -# define TIM16_CR1_CKD_TCKINT (0x0 << TIM16_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define TIM16_CR1_CKD_2TCKINT (0x1 << TIM16_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define TIM16_CR1_CKD_4TCKINT (0x2 << TIM16_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -#define TIM16_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */ - -#define TIM17_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define TIM17_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define TIM17_CR1_URS (1 << 2) /* Bit 2: Update request source */ -# define TIM17_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */ -# define TIM17_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */ - -#define TIM17_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define TIM17_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define TIM17_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define TIM17_CR1_CKD_MASK (0x3 << TIM17_CR1_CKD_SHIFT) -# define TIM17_CR1_CKD_TCKINT (0x0 << TIM17_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define TIM17_CR1_CKD_2TCKINT (0x1 << TIM17_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define TIM17_CR1_CKD_4TCKINT (0x2 << TIM17_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -#define TIM17_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */ - -/* Control register 2 */ - -#define TIM1_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare preloaded control (enable bit) */ -#define TIM1_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare control Update selection */ -# define TIM1_CR2_CCUS_COMG (0 << 2) /* 0: updated by setting COMG bit only */ -# define TIM1_CR2_CCUS_COMG_TRGI (1 << 2) /* 1: updated by setting COMG or TRGI rising edge */ - -#define TIM1_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */ -# define TIM1_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */ -# define TIM1_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */ - -#define TIM1_CR2_MMS_SHIFT (4) /* Bits 4-6: Master mode selection */ -#define TIM1_CR2_MMS_MASK (0x7 << TIM1_CR2_MMS_SHIFT) -# define TIM1_CR2_MMS_RESET (0x0 << TIM1_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ -# define TIM1_CR2_MMS_ENABLE (0x1 << TIM1_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ -# define TIM1_CR2_MMS_UPDATE (0x2 << TIM1_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ -# define TIM1_CR2_MMS_COMPP (0x3 << TIM1_CR2_MMS_SHIFT) /* 011: Compare Pulse - CC1IF flag */ -# define TIM1_CR2_MMS_OC1REF (0x4 << TIM1_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ -# define TIM1_CR2_MMS_OC2REF (0x5 << TIM1_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ -# define TIM1_CR2_MMS_OC3REF (0x6 << TIM1_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ -# define TIM1_CR2_MMS_OC4REF (0x7 << TIM1_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ - -#define TIM1_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ -# define TIM1_CR2_TI1S_CH1 (0 << 7) /* 0: CH1 pin connected to TI1 input */ -# define TIM1_CR2_TI1S_CH1CH2CH3 (1 << 7) /* 1: CH1, CH2, CH3 pins connected to TI1 input (XOR logic) */ - -#define TIM1_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define TIM1_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ -#define TIM1_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ -#define TIM1_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ -#define TIM1_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ -#define TIM1_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ -#define TIM1_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define TIM1_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ -#define TIM1_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ -#define TIM1_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ -#define TIM1_CR2_MMS2_MASK (0xf << TIM1_CR2_MMS2_SHIFT) -# define TIM1_CR2_MMS2_RESET (0x0 << TIM1_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ -# define TIM1_CR2_MMS2_ENABLE (0x1 << TIM1_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ -# define TIM1_CR2_MMS2_UPDATE (0x2 << TIM1_CR2_MMS2_SHIFT) /* 0010: Update event is TRGO2 */ -# define TIM1_CR2_MMS2_COMPP (0x3 << TIM1_CR2_MMS2_SHIFT) /* 0011: Compare Pulse - CC1IF flag */ -# define TIM1_CR2_MMS2_OC1REF (0x4 << TIM1_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC2REF (0x5 << TIM1_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC3REF (0x6 << TIM1_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC4REF (0x7 << TIM1_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC5REF (0x8 << TIM1_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC6REF (0x9 << TIM1_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ -# define TIM1_CR2_MMS2_CMPOC4 (0xa << TIM1_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ -# define TIM1_CR2_MMS2_CMPOC6 (0xb << TIM1_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ -# define TIM1_CR2_MMS2_CMPOC4R6R (0xc << TIM1_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ -# define TIM1_CR2_MMS2_CMPOC4R6F (0xd << TIM1_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ -# define TIM1_CR2_MMS2_CMPOC5R6R (0xe << TIM1_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ -# define TIM1_CR2_MMS2_CMPOC5R6F (0xf << TIM1_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ - -#define TIM2_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */ -# define TIM2_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */ -# define TIM2_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */ - -#define TIM2_CR2_MMS_SHIFT (4) /* Bits 4-6: Master mode selection */ -#define TIM2_CR2_MMS_MASK (0x7 << TIM2_CR2_MMS_SHIFT) -# define TIM2_CR2_MMS_RESET (0x0 << TIM2_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ -# define TIM2_CR2_MMS_ENABLE (0x1 << TIM2_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ -# define TIM2_CR2_MMS_UPDATE (0x2 << TIM2_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ -# define TIM2_CR2_MMS_COMPP (0x3 << TIM2_CR2_MMS_SHIFT) /* 011: Compare Pulse - CC1IF flag */ -# define TIM2_CR2_MMS_OC1REF (0x4 << TIM2_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ -# define TIM2_CR2_MMS_OC2REF (0x5 << TIM2_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ -# define TIM2_CR2_MMS_OC3REF (0x6 << TIM2_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ -# define TIM2_CR2_MMS_OC4REF (0x7 << TIM2_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ - -#define TIM2_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ -# define TIM2_CR2_TI1S_CH1 (0 << 7) /* 0: CH1 pin connected to TI1 input */ -# define TIM2_CR2_TI1S_CH1CH2CH3 (1 << 7) /* 1: CH1, CH2, CH3 pins connected to TI1 input (XOR logic) */ - -#define TIM16_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare preloaded control (enable bit) */ -#define TIM16_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare control Update selection */ -# define TIM16_CR2_CCUS_COMG (0 << 2) /* 0: updated by setting COMG bit only */ -# define TIM16_CR2_CCUS_COMG_TRGI (1 << 2) /* 1: updated by setting COMG or TRGI rising edge */ - -#define TIM16_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */ -# define TIM16_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */ -# define TIM16_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */ - -#define TIM16_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define TIM16_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ - -#define TIM17_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare preloaded control (enable bit) */ -#define TIM17_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare control Update selection */ -# define TIM17_CR2_CCUS_COMG (0 << 2) /* 0: updated by setting COMG bit only */ -# define TIM17_CR2_CCUS_COMG_TRGI (1 << 2) /* 1: updated by setting COMG or TRGI rising edge */ - -#define TIM17_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */ -# define TIM17_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */ -# define TIM17_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */ - -#define TIM17_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define TIM17_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ - -/* Slave mode control register */ - -#define TIM1_SMCR_SMS_LO_SHIFT (0) /* Bits 0-2: Slave mode selection, bits [2:0] */ -#define TIM1_SMCR_SMS_HI_SHIFT (16) /* Bit 16: Slave mode selection, bits [3] */ -#define TIM1_SMCR_SMS_BITS(h,l) (((h) << TIM1_SMCR_SMS_HI_SHIFT) | ((l) << TIM1_SMCR_SMS_LO_SHIFT)) -#define TIM1_SMCR_SMS_MASK TIM1_SMCR_SMS_BITS(0x1, 0x7) -# define TIM1_SMCR_DISAB TIM1_SMCR_SMS_BITS(0x0, 0x0) /* 0,000: Slave mode disabled */ -# define TIM1_SMCR_ENCMD1 TIM1_SMCR_SMS_BITS(0x0, 0x1) /* 0,001: Encoder mode 1 */ -# define TIM1_SMCR_ENCMD2 TIM1_SMCR_SMS_BITS(0x0, 0x2) /* 0,010: Encoder mode 2 */ -# define TIM1_SMCR_ENCMD3 TIM1_SMCR_SMS_BITS(0x0, 0x3) /* 0,011: Encoder mode 3 */ -# define TIM1_SMCR_RESET TIM1_SMCR_SMS_BITS(0x0, 0x4) /* 0,100: Reset Mode */ -# define TIM1_SMCR_GATED TIM1_SMCR_SMS_BITS(0x0, 0x5) /* 0,101: Gated Mode */ -# define TIM1_SMCR_TRIGGER TIM1_SMCR_SMS_BITS(0x0, 0x6) /* 0,110: Trigger Mode */ -# define TIM1_SMCR_EXTCLK1 TIM1_SMCR_SMS_BITS(0x0, 0x7) /* 0,111: External Clock Mode 1 */ -# define TIM1_SMCR_SMS_COMBINED TIM1_SMCR_SMS_BITS(0x1, 0x0) /* 1,000: Combined Reset and Trigger mode */ - -#define TIM1_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ -# define TIM1_SMCR_OCCS_CLR (0 << 3) /* 0: OCREF clear triggered by CLR input */ -# define TIM1_SMCR_OCCS_ETRF (1 << 3) /* 1: OCREF clear triggered by ETRF */ - -#define TIM1_SMCR_TS_LO_SHIFT (4) /* Bits 4-6: Trigger selection, bits [2:0] */ -#define TIM1_SMCR_TS_HI_SHIFT (20) /* Bits 20-21: Trigger selection, bits [1:0] */ -#define TIM1_SMCR_TS_BITS(h,l) (((h) << TIM1_SMCR_TS_HI_SHIFT) | ((l) << TIM1_SMCR_TS_LO_SHIFT)) -#define TIM1_SMCR_TS_MASK TIM1_SMCR_TS_BITS(0x3, 0x7) -# define TIM1_SMCR_ITR0 TIM1_SMCR_TS_BITS(0x0, 0x0) /* 00,000: Internal trigger 0 (ITR0) */ -# define TIM1_SMCR_ITR1 TIM1_SMCR_TS_BITS(0x0, 0x1) /* 00,001: Internal trigger 1 (ITR1) */ -# define TIM1_SMCR_ITR2 TIM1_SMCR_TS_BITS(0x0, 0x2) /* 00,010: Internal trigger 2 (ITR2) */ -# define TIM1_SMCR_ITR3 TIM1_SMCR_TS_BITS(0x0, 0x3) /* 00,011: Internal trigger 3 (ITR3) */ -# define TIM1_SMCR_T1FED TIM1_SMCR_TS_BITS(0x0, 0x4) /* 00,100: TI1 Edge detector (TI1F_ED) */ -# define TIM1_SMCR_TI1FP1 TIM1_SMCR_TS_BITS(0x0, 0x5) /* 00,101: Filtered timer input 1 (TI1FP1) */ -# define TIM1_SMCR_T12FP2 TIM1_SMCR_TS_BITS(0x0, 0x6) /* 00,110: Filtered timer input 2 (TI2FP2) */ -# define TIM1_SMCR_ETRF TIM1_SMCR_TS_BITS(0x0, 0x7) /* 00,111: External trigger input (ETRF) */ - -#define TIM1_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define TIM1_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define TIM1_SMCR_ETF_MASK (0xf << TIM1_SMCR_ETF_SHIFT) -# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define TIM1_SMCR_ETPS_MASK (0x3 << TIM1_SMCR_ETPS_SHIFT) -# define TIM1_SMCR_PSCOFF (0x0 << TIM1_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define TIM1_SMCR_ETRPd2 (0x1 << TIM1_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define TIM1_SMCR_ETRPd4 (0x2 << TIM1_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define TIM1_SMCR_ETRPd8 (0x3 << TIM1_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ - -#define TIM1_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define TIM1_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -# define TIM1_SMCR_ETP_HIGH (0 << 15) /* 0: ETR is non-inverted, active at high level or rising edge */ -# define TIM1_SMCR_ETP_LOW (1 << 15) /* 1: ETR is inverted, active at low level or falling edge */ - -#define TIM2_SMCR_SMS_LO_SHIFT (0) /* Bits 0-2: Slave mode selection, bits [2:0] */ -#define TIM2_SMCR_SMS_HI_SHIFT (16) /* Bit 16: Slave mode selection, bits [3] */ -#define TIM2_SMCR_SMS_BITS(h,l) (((h) << TIM2_SMCR_SMS_HI_SHIFT) | ((l) << TIM2_SMCR_SMS_LO_SHIFT)) -#define TIM2_SMCR_SMS_MASK TIM2_SMCR_SMS_BITS(0x1, 0x7) -# define TIM2_SMCR_DISAB TIM2_SMCR_SMS_BITS(0x0, 0x0) /* 0,000: Slave mode disabled */ -# define TIM2_SMCR_ENCMD1 TIM2_SMCR_SMS_BITS(0x0, 0x1) /* 0,001: Encoder mode 1 */ -# define TIM2_SMCR_ENCMD2 TIM2_SMCR_SMS_BITS(0x0, 0x2) /* 0,010: Encoder mode 2 */ -# define TIM2_SMCR_ENCMD3 TIM2_SMCR_SMS_BITS(0x0, 0x3) /* 0,011: Encoder mode 3 */ -# define TIM2_SMCR_RESET TIM2_SMCR_SMS_BITS(0x0, 0x4) /* 0,100: Reset Mode */ -# define TIM2_SMCR_GATED TIM2_SMCR_SMS_BITS(0x0, 0x5) /* 0,101: Gated Mode */ -# define TIM2_SMCR_TRIGGER TIM2_SMCR_SMS_BITS(0x0, 0x6) /* 0,110: Trigger Mode */ -# define TIM2_SMCR_EXTCLK1 TIM2_SMCR_SMS_BITS(0x0, 0x7) /* 0,111: External Clock Mode 1 */ -# define TIM2_SMCR_SMS_COMBINED TIM2_SMCR_SMS_BITS(0x1, 0x0) /* 1,000: Combined Reset and Trigger mode */ - -#define TIM2_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ -# define TIM2_SMCR_OCCS_CLR (0 << 3) /* 0: OCREF clear triggered by CLR input */ -# define TIM2_SMCR_OCCS_ETRF (1 << 3) /* 1: OCREF clear triggered by ETRF */ - -#define TIM2_SMCR_TS_LO_SHIFT (4) /* Bits 4-6: Trigger selection, bits [2:0] */ -#define TIM2_SMCR_TS_HI_SHIFT (20) /* Bits 20-21: Trigger selection, bits [1:0] */ -#define TIM2_SMCR_TS_BITS(h,l) (((h) << TIM2_SMCR_TS_HI_SHIFT) | ((l) << TIM2_SMCR_TS_LO_SHIFT)) -#define TIM2_SMCR_TS_MASK TIM2_SMCR_TS_BITS(0x3, 0x7) -# define TIM2_SMCR_ITR0 TIM2_SMCR_TS_BITS(0x0, 0x0) /* 00,000: Internal trigger 0 (ITR0) */ -# define TIM2_SMCR_ITR1 TIM2_SMCR_TS_BITS(0x0, 0x1) /* 00,001: Internal trigger 1 (ITR1) */ -# define TIM2_SMCR_ITR2 TIM2_SMCR_TS_BITS(0x0, 0x2) /* 00,010: Internal trigger 2 (ITR2) */ -# define TIM2_SMCR_ITR3 TIM2_SMCR_TS_BITS(0x0, 0x3) /* 00,011: Internal trigger 3 (ITR3) */ -# define TIM2_SMCR_T1FED TIM2_SMCR_TS_BITS(0x0, 0x4) /* 00,100: TI1 Edge detector (TI1F_ED) */ -# define TIM2_SMCR_TI1FP1 TIM2_SMCR_TS_BITS(0x0, 0x5) /* 00,101: Filtered timer Input 1 (TI1FP1) */ -# define TIM2_SMCR_T12FP2 TIM2_SMCR_TS_BITS(0x0, 0x6) /* 00,110: Filtered timer Input 2 (TI2FP2) */ -# define TIM2_SMCR_ETRF TIM2_SMCR_TS_BITS(0x0, 0x7) /* 00,111: External trigger input (ETRF) */ -# define TIM2_SMCR_ITR4 TIM2_SMCR_TS_BITS(0x1, 0x0) /* 01,000: Internal trigger 4 (ITR4) */ -# define TIM2_SMCR_ITR5 TIM2_SMCR_TS_BITS(0x1, 0x1) /* 01,001: Internal trigger 5 (ITR5) */ -# define TIM2_SMCR_ITR6 TIM2_SMCR_TS_BITS(0x1, 0x2) /* 01,010: Internal trigger 6 (ITR6) */ -# define TIM2_SMCR_ITR7 TIM2_SMCR_TS_BITS(0x1, 0x3) /* 01,011: Internal trigger 7 (ITR7) */ -# define TIM2_SMCR_ITR8 TIM2_SMCR_TS_BITS(0x1, 0x4) /* 01,100: Internal trigger 8 (ITR8) */ - -#define TIM2_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define TIM2_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define TIM2_SMCR_ETF_MASK (0xf << TIM2_SMCR_ETF_SHIFT) -# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define TIM2_SMCR_ETPS_MASK (0x3 << TIM2_SMCR_ETPS_SHIFT) -# define TIM2_SMCR_PSCOFF (0x0 << TIM2_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define TIM2_SMCR_ETRPd2 (0x1 << TIM2_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define TIM2_SMCR_ETRPd4 (0x2 << TIM2_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define TIM2_SMCR_ETRPd8 (0x3 << TIM2_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ - -#define TIM2_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define TIM2_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -# define TIM2_SMCR_ETP_HIGH (0 << 15) /* 0: ETR is non-inverted, active at high level or rising edge */ -# define TIM2_SMCR_ETP_LOW (1 << 15) /* 1: ETR is inverted, active at low level or falling edge */ - -/* Timer DMA / Interrupt enable register */ - -#define TIM1_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define TIM1_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define TIM1_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define TIM1_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define TIM1_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ -#define TIM1_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define TIM1_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ -#define TIM1_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define TIM1_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define TIM1_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define TIM1_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define TIM1_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define TIM1_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ -#define TIM1_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ -#define TIM1_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ - -#define TIM2_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define TIM2_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define TIM2_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define TIM2_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define TIM2_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ -#define TIM2_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ -#define TIM2_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define TIM2_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define TIM2_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define TIM2_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define TIM2_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ - -#define TIM16_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define TIM16_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define TIM16_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define TIM16_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define TIM16_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define TIM16_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ - -#define TIM17_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define TIM17_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define TIM17_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define TIM17_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define TIM17_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define TIM17_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ - -/* Status register */ - -#define TIM1_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define TIM1_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define TIM1_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ -#define TIM1_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ -#define TIM1_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ -#define TIM1_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define TIM1_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ -#define TIM1_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#define TIM1_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ -#define TIM1_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define TIM1_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define TIM1_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define TIM1_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ -#define TIM1_SR_SBIF (1 << 13) /* Bit 13: System break interrupt Flag */ -#define TIM1_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ -#define TIM1_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ - -#define TIM2_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define TIM2_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define TIM2_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ -#define TIM2_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ -#define TIM2_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ -#define TIM2_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ -#define TIM2_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define TIM2_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define TIM2_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define TIM2_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ - -#define TIM16_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define TIM16_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define TIM16_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define TIM16_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#define TIM16_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ - -#define TIM17_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define TIM17_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define TIM17_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define TIM17_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#define TIM17_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ - -/* Event generation register */ - -#define TIM1_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define TIM1_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define TIM1_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define TIM1_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define TIM1_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ -#define TIM1_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define TIM1_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ -#define TIM1_EGR_BG (1 << 7) /* Bit 7: Break Generation */ -#define TIM1_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ - -#define TIM2_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define TIM2_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define TIM2_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define TIM2_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define TIM2_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ -#define TIM2_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ - -#define TIM16_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define TIM16_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define TIM16_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define TIM16_EGR_BG (1 << 7) /* Bit 7: Break Generation */ - -#define TIM17_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define TIM17_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define TIM17_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define TIM17_EGR_BG (1 << 7) /* Bit 7: Break Generation */ - -/* Capture/compare mode registers - capture/compare mode selection */ - -#define TIM1_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define TIM1_CCMR1_CC1S_MASK (0x3 << TIM1_CCMR1_CC1S_SHIFT) -# define TIM1_CCMR1_CC1S_CCOUT (0x0 << TIM1_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */ -# define TIM1_CCMR1_CC1S_CCIN1 (0x1 << TIM1_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */ -# define TIM1_CCMR1_CC1S_CCIN2 (0x2 << TIM1_CCMR1_CC1S_SHIFT) /* 10: CC1 channel input, IC1 is TI2 */ -# define TIM1_CCMR1_CC1S_CCINTRC (0x3 << TIM1_CCMR1_CC1S_SHIFT) /* 11: CC1 channel input, IC1 is TRC */ - -#define TIM1_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define TIM1_CCMR1_CC2S_MASK (0x3 << TIM1_CCMR1_CC2S_SHIFT) -# define TIM1_CCMR1_CC2S_CCOUT (0x0 << TIM1_CCMR1_CC2S_SHIFT) /* 00: CC2 channel output */ -# define TIM1_CCMR1_CC2S_CCIN1 (0x1 << TIM1_CCMR1_CC2S_SHIFT) /* 01: CC2 channel input, IC2 is TI2 */ -# define TIM1_CCMR1_CC2S_CCIN2 (0x2 << TIM1_CCMR1_CC2S_SHIFT) /* 10: CC2 channel input, IC2 is TI1 */ -# define TIM1_CCMR1_CC2S_CCINTRC (0x3 << TIM1_CCMR1_CC2S_SHIFT) /* 11: CC2 channel input, IC2 is TRC */ - -#define TIM1_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */ -#define TIM1_CCMR2_CC3S_MASK (0x3 << TIM1_CCMR2_CC3S_SHIFT) -# define TIM1_CCMR2_CC3S_CCOUT (0x0 << TIM1_CCMR2_CC3S_SHIFT) /* 00: CC3 channel output */ -# define TIM1_CCMR2_CC3S_CCIN1 (0x1 << TIM1_CCMR2_CC3S_SHIFT) /* 01: CC3 channel input, IC3 is TI3 */ -# define TIM1_CCMR2_CC3S_CCIN2 (0x2 << TIM1_CCMR2_CC3S_SHIFT) /* 10: CC3 channel input, IC3 is TI4 */ -# define TIM1_CCMR2_CC3S_CCINTRC (0x3 << TIM1_CCMR2_CC3S_SHIFT) /* 11: CC3 channel input, IC3 is TRC */ - -#define TIM1_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */ -#define TIM1_CCMR2_CC4S_MASK (0x3 << TIM1_CCMR2_CC4S_SHIFT) -# define TIM1_CCMR2_CC4S_CCOUT (0x0 << TIM1_CCMR2_CC4S_SHIFT) /* 00: CC4 channel output */ -# define TIM1_CCMR2_CC4S_CCIN1 (0x1 << TIM1_CCMR2_CC4S_SHIFT) /* 01: CC4 channel input, IC4 is TI4 */ -# define TIM1_CCMR2_CC4S_CCIN2 (0x2 << TIM1_CCMR2_CC4S_SHIFT) /* 10: CC4 channel input, IC4 is TI3 */ -# define TIM1_CCMR2_CC4S_CCINTRC (0x3 << TIM1_CCMR2_CC4S_SHIFT) /* 11: CC4 channel input, IC4 is TRC */ - -#define TIM2_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define TIM2_CCMR1_CC1S_MASK (0x3 << TIM2_CCMR1_CC1S_SHIFT) -# define TIM2_CCMR1_CC1S_CCOUT (0x0 << TIM2_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */ -# define TIM2_CCMR1_CC1S_CCIN1 (0x1 << TIM2_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */ -# define TIM2_CCMR1_CC1S_CCIN2 (0x2 << TIM2_CCMR1_CC1S_SHIFT) /* 10: CC1 channel input, IC1 is TI2 */ -# define TIM2_CCMR1_CC1S_CCINTRC (0x3 << TIM2_CCMR1_CC1S_SHIFT) /* 11: CC1 channel input, IC1 is TRC */ - -#define TIM2_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define TIM2_CCMR1_CC2S_MASK (0x3 << TIM2_CCMR1_CC2S_SHIFT) -# define TIM2_CCMR1_CC2S_CCOUT (0x0 << TIM2_CCMR1_CC2S_SHIFT) /* 00: CC2 channel output */ -# define TIM2_CCMR1_CC2S_CCIN1 (0x1 << TIM2_CCMR1_CC2S_SHIFT) /* 01: CC2 channel input, IC2 is TI2 */ -# define TIM2_CCMR1_CC2S_CCIN2 (0x2 << TIM2_CCMR1_CC2S_SHIFT) /* 10: CC2 channel input, IC2 is TI1 */ -# define TIM2_CCMR1_CC2S_CCINTRC (0x3 << TIM2_CCMR1_CC2S_SHIFT) /* 11: CC2 channel input, IC2 is TRC */ - -#define TIM2_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */ -#define TIM2_CCMR2_CC3S_MASK (0x3 << TIM2_CCMR2_CC3S_SHIFT) -# define TIM2_CCMR2_CC3S_CCOUT (0x0 << TIM2_CCMR2_CC3S_SHIFT) /* 00: CC3 channel output */ -# define TIM2_CCMR2_CC3S_CCIN1 (0x1 << TIM2_CCMR2_CC3S_SHIFT) /* 01: CC3 channel input, IC3 is TI3 */ -# define TIM2_CCMR2_CC3S_CCIN2 (0x2 << TIM2_CCMR2_CC3S_SHIFT) /* 10: CC3 channel input, IC3 is TI4 */ -# define TIM2_CCMR2_CC3S_CCINTRC (0x3 << TIM2_CCMR2_CC3S_SHIFT) /* 11: CC3 channel input, IC3 is TRC */ - -#define TIM2_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */ -#define TIM2_CCMR2_CC4S_MASK (0x3 << TIM2_CCMR2_CC4S_SHIFT) -# define TIM2_CCMR2_CC4S_CCOUT (0x0 << TIM2_CCMR2_CC4S_SHIFT) /* 00: CC4 channel output */ -# define TIM2_CCMR2_CC4S_CCIN1 (0x1 << TIM2_CCMR2_CC4S_SHIFT) /* 01: CC4 channel input, IC4 is TI4 */ -# define TIM2_CCMR2_CC4S_CCIN2 (0x2 << TIM2_CCMR2_CC4S_SHIFT) /* 10: CC4 channel input, IC4 is TI3 */ -# define TIM2_CCMR2_CC4S_CCINTRC (0x3 << TIM2_CCMR2_CC4S_SHIFT) /* 11: CC4 channel input, IC4 is TRC */ - -#define TIM16_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define TIM16_CCMR1_CC1S_MASK (0x3 << TIM16_CCMR1_CC1S_SHIFT) -# define TIM16_CCMR1_CC1S_CCOUT (0x0 << TIM16_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */ -# define TIM16_CCMR1_CC1S_CCIN1 (0x1 << TIM16_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */ - -#define TIM17_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define TIM17_CCMR1_CC1S_MASK (0x3 << TIM17_CCMR1_CC1S_SHIFT) -# define TIM17_CCMR1_CC1S_CCOUT (0x0 << TIM17_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */ -# define TIM17_CCMR1_CC1S_CCIN1 (0x1 << TIM17_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */ - -/* Capture/compare mode registers - Output compare mode */ - -#define TIM1_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define TIM1_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define TIM1_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */ -#define TIM1_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */ -#define TIM1_CCMR1_OC1M_BITS(h,l) (((h) << TIM1_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM1_CCMR1_OC1M_LO_SHIFT)) -#define TIM1_CCMR1_OC1M_MASK TIM1_CCMR1_OC1M_BITS(0x1, 0x7) -# define TIM1_CCMR1_OC1M_FRZN TIM1_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR1_OC1M_CHACT TIM1_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */ -# define TIM1_CCMR1_OC1M_CHINACT TIM1_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */ -# define TIM1_CCMR1_OC1M_OCREFTOG TIM1_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */ -# define TIM1_CCMR1_OC1M_OCREFLO TIM1_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */ -# define TIM1_CCMR1_OC1M_OCREFHI TIM1_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */ -# define TIM1_CCMR1_OC1M_PWM1 TIM1_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR1_OC1M_PWM2 TIM1_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR1_OC1M_OPM1 TIM1_CCMR1_OC1M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR1_OC1M_OPM2 TIM1_CCMR1_OC1M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR1_OC1M_COMBINED1 TIM1_CCMR1_OC1M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR1_OC1M_COMBINED2 TIM1_CCMR1_OC1M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR1_OC1M_ASYMM1 TIM1_CCMR1_OC1M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR1_OC1M_ASYMM2 TIM1_CCMR1_OC1M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1 Clear Enable */ - -#define TIM1_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define TIM1_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define TIM1_CCMR1_OC2M_LO_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode, bits [2:0] */ -#define TIM1_CCMR1_OC2M_HI_SHIFT (24) /* Bit 24: Output Compare 2 Mode, bits [3] */ -#define TIM1_CCMR1_OC2M_BITS(h,l) (((h) << TIM1_CCMR1_OC2M_HI_SHIFT) | ((l) << TIM1_CCMR1_OC2M_LO_SHIFT)) -#define TIM1_CCMR1_OC2M_MASK TIM1_CCMR1_OC2M_BITS(0x1, 0x7) -# define TIM1_CCMR1_OC2M_FRZN TIM1_CCMR1_OC2M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR1_OC2M_CHACT TIM1_CCMR1_OC2M_BITS(0x0, 0x1) /* 0,001: Channel 2 active on match */ -# define TIM1_CCMR1_OC2M_CHINACT TIM1_CCMR1_OC2M_BITS(0x0, 0x2) /* 0,010: Channel 2 inactive on match */ -# define TIM1_CCMR1_OC2M_OCREFTOG TIM1_CCMR1_OC2M_BITS(0x0, 0x3) /* 0,011: OC2REF toggle TIM_CNT=TIM_CCR2 */ -# define TIM1_CCMR1_OC2M_OCREFLO TIM1_CCMR1_OC2M_BITS(0x0, 0x4) /* 0,100: OC2REF forced low */ -# define TIM1_CCMR1_OC2M_OCREFHI TIM1_CCMR1_OC2M_BITS(0x0, 0x5) /* 0,101: OC2REF forced high */ -# define TIM1_CCMR1_OC2M_PWM1 TIM1_CCMR1_OC2M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR1_OC2M_PWM2 TIM1_CCMR1_OC2M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR1_OC2M_OPM1 TIM1_CCMR1_OC2M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR1_OC2M_OPM2 TIM1_CCMR1_OC2M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR1_OC2M_COMBINED1 TIM1_CCMR1_OC2M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR1_OC2M_COMBINED2 TIM1_CCMR1_OC2M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR1_OC2M_ASYMM1 TIM1_CCMR1_OC2M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR1_OC2M_ASYMM2 TIM1_CCMR1_OC2M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ - -#define TIM1_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define TIM1_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define TIM1_CCMR2_OC3M_LO_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode, bits [2:0] */ -#define TIM1_CCMR2_OC3M_HI_SHIFT (16) /* Bit 16: Output Compare 3 Mode, bits [3] */ -#define TIM1_CCMR2_OC3M_BITS(h,l) (((h) << TIM1_CCMR2_OC3M_HI_SHIFT) | ((l) << TIM1_CCMR2_OC3M_LO_SHIFT)) -#define TIM1_CCMR2_OC3M_MASK TIM1_CCMR2_OC3M_BITS(0x1, 0x7) -# define TIM1_CCMR2_OC3M_FRZN TIM1_CCMR2_OC3M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR2_OC3M_CHACT TIM1_CCMR2_OC3M_BITS(0x0, 0x1) /* 0,001: Channel 3 active on match */ -# define TIM1_CCMR2_OC3M_CHINACT TIM1_CCMR2_OC3M_BITS(0x0, 0x2) /* 0,010: Channel 3 inactive on match */ -# define TIM1_CCMR2_OC3M_OCREFTOG TIM1_CCMR2_OC3M_BITS(0x0, 0x3) /* 0,011: OC3REF toggle TIM_CNT=TIM_CCR3 */ -# define TIM1_CCMR2_OC3M_OCREFLO TIM1_CCMR2_OC3M_BITS(0x0, 0x4) /* 0,100: OC3REF forced low */ -# define TIM1_CCMR2_OC3M_OCREFHI TIM1_CCMR2_OC3M_BITS(0x0, 0x5) /* 0,101: OC3REF forced high */ -# define TIM1_CCMR2_OC3M_PWM1 TIM1_CCMR2_OC3M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR2_OC3M_PWM2 TIM1_CCMR2_OC3M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR2_OC3M_OPM1 TIM1_CCMR2_OC3M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR2_OC3M_OPM2 TIM1_CCMR2_OC3M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR2_OC3M_COMBINED1 TIM1_CCMR2_OC3M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR2_OC3M_COMBINED2 TIM1_CCMR2_OC3M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR2_OC3M_ASYMM1 TIM1_CCMR2_OC3M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR2_OC3M_ASYMM2 TIM1_CCMR2_OC3M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ - -#define TIM1_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define TIM1_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define TIM1_CCMR2_OC4M_LO_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode, bits [2:0] */ -#define TIM1_CCMR2_OC4M_HI_SHIFT (24) /* Bit 24: Output Compare 4 Mode, bits [3] */ -#define TIM1_CCMR2_OC4M_BITS(h,l) (((h) << TIM1_CCMR2_OC4M_HI_SHIFT) | ((l) << TIM1_CCMR2_OC4M_LO_SHIFT)) -#define TIM1_CCMR2_OC4M_MASK TIM1_CCMR2_OC4M_BITS(0x1, 0x7) -# define TIM1_CCMR2_OC4M_FRZN TIM1_CCMR2_OC4M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR2_OC4M_CHACT TIM1_CCMR2_OC4M_BITS(0x0, 0x1) /* 0,001: Channel 4 active on match */ -# define TIM1_CCMR2_OC4M_CHINACT TIM1_CCMR2_OC4M_BITS(0x0, 0x2) /* 0,010: Channel 4 inactive on match */ -# define TIM1_CCMR2_OC4M_OCREFTOG TIM1_CCMR2_OC4M_BITS(0x0, 0x3) /* 0,011: OC4REF toggle TIM_CNT=TIM_CCR4 */ -# define TIM1_CCMR2_OC4M_OCREFLO TIM1_CCMR2_OC4M_BITS(0x0, 0x4) /* 0,100: OC4REF forced low */ -# define TIM1_CCMR2_OC4M_OCREFHI TIM1_CCMR2_OC4M_BITS(0x0, 0x5) /* 0,101: OC4REF forced high */ -# define TIM1_CCMR2_OC4M_PWM1 TIM1_CCMR2_OC4M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR2_OC4M_PWM2 TIM1_CCMR2_OC4M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR2_OC4M_OPM1 TIM1_CCMR2_OC4M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR2_OC4M_OPM2 TIM1_CCMR2_OC4M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR2_OC4M_COMBINED1 TIM1_CCMR2_OC4M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR2_OC4M_COMBINED2 TIM1_CCMR2_OC4M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR2_OC4M_ASYMM1 TIM1_CCMR2_OC4M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR2_OC4M_ASYMM2 TIM1_CCMR2_OC4M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ - -#define TIM1_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ -#define TIM1_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ -#define TIM1_CCMR3_OC5M_LO_SHIFT (4) /* Bits 4-6: Output Compare 5 Mode, bits [2:0] */ -#define TIM1_CCMR3_OC5M_HI_SHIFT (16) /* Bit 16: Output Compare 5 Mode, bits [3] */ -#define TIM1_CCMR3_OC5M_BITS(h,l) (((h) << TIM1_CCMR3_OC5M_HI_SHIFT) | ((l) << TIM1_CCMR3_OC5M_LO_SHIFT)) -#define TIM1_CCMR3_OC5M_MASK TIM1_CCMR3_OC5M_BITS(0x1, 0x7) -# define TIM1_CCMR3_OC5M_FRZN TIM1_CCMR3_OC5M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR3_OC5M_CHACT TIM1_CCMR3_OC5M_BITS(0x0, 0x1) /* 0,001: Channel 5 active on match */ -# define TIM1_CCMR3_OC5M_CHINACT TIM1_CCMR3_OC5M_BITS(0x0, 0x2) /* 0,010: Channel 5 inactive on match */ -# define TIM1_CCMR3_OC5M_OCREFTOG TIM1_CCMR3_OC5M_BITS(0x0, 0x3) /* 0,011: OC5REF toggle TIM_CNT=TIM_CCR5 */ -# define TIM1_CCMR3_OC5M_OCREFLO TIM1_CCMR3_OC5M_BITS(0x0, 0x4) /* 0,100: OC5REF forced low */ -# define TIM1_CCMR3_OC5M_OCREFHI TIM1_CCMR3_OC5M_BITS(0x0, 0x5) /* 0,101: OC5REF forced high */ -# define TIM1_CCMR3_OC5M_PWM1 TIM1_CCMR3_OC5M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR3_OC5M_PWM2 TIM1_CCMR3_OC5M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR3_OC5M_OPM1 TIM1_CCMR3_OC5M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR3_OC5M_OPM2 TIM1_CCMR3_OC5M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR3_OC5M_COMBINED1 TIM1_CCMR3_OC5M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR3_OC5M_COMBINED2 TIM1_CCMR3_OC5M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR3_OC5M_ASYMM1 TIM1_CCMR3_OC5M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR3_OC5M_ASYMM2 TIM1_CCMR3_OC5M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ - -#define TIM1_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ -#define TIM1_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ -#define TIM1_CCMR3_OC6M_LO_SHIFT (12) /* Bits 12-14: Output Compare 6 Mode, bits [2:0] */ -#define TIM1_CCMR3_OC6M_HI_SHIFT (24) /* Bit 24: Output Compare 6 Mode, bits [3] */ -#define TIM1_CCMR3_OC6M_BITS(h,l) (((h) << TIM1_CCMR3_OC6M_HI_SHIFT) | ((l) << TIM1_CCMR3_OC6M_LO_SHIFT)) -#define TIM1_CCMR3_OC6M_MASK TIM1_CCMR3_OC6M_BITS(0x1, 0x7) -# define TIM1_CCMR3_OC6M_FRZN TIM1_CCMR3_OC6M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR3_OC6M_CHACT TIM1_CCMR3_OC6M_BITS(0x0, 0x1) /* 0,001: Channel 6 active on match */ -# define TIM1_CCMR3_OC6M_CHINACT TIM1_CCMR3_OC6M_BITS(0x0, 0x2) /* 0,010: Channel 6 inactive on match */ -# define TIM1_CCMR3_OC6M_OCREFTOG TIM1_CCMR3_OC6M_BITS(0x0, 0x3) /* 0,011: OC6REF toggle TIM_CNT=TIM_CCR6 */ -# define TIM1_CCMR3_OC6M_OCREFLO TIM1_CCMR3_OC6M_BITS(0x0, 0x4) /* 0,100: OC6REF forced low */ -# define TIM1_CCMR3_OC6M_OCREFHI TIM1_CCMR3_OC6M_BITS(0x0, 0x5) /* 0,101: OC6REF forced high */ -# define TIM1_CCMR3_OC6M_PWM1 TIM1_CCMR3_OC6M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR3_OC6M_PWM2 TIM1_CCMR3_OC6M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR3_OC6M_OPM1 TIM1_CCMR3_OC6M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR3_OC6M_OPM2 TIM1_CCMR3_OC6M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR3_OC6M_COMBINED1 TIM1_CCMR3_OC6M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR3_OC6M_COMBINED2 TIM1_CCMR3_OC6M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR3_OC6M_ASYMM1 TIM1_CCMR3_OC6M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR3_OC6M_ASYMM2 TIM1_CCMR3_OC6M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 6 Clear Enable */ - -#define TIM2_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define TIM2_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define TIM2_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */ -#define TIM2_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */ -#define TIM2_CCMR1_OC1M_BITS(h,l) (((h) << TIM2_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM2_CCMR1_OC1M_LO_SHIFT)) -#define TIM2_CCMR1_OC1M_MASK TIM2_CCMR1_OC1M_BITS(0x1, 0x7) -# define TIM2_CCMR1_OC1M_FRZN TIM2_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM2_CCMR1_OC1M_CHACT TIM2_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */ -# define TIM2_CCMR1_OC1M_CHINACT TIM2_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */ -# define TIM2_CCMR1_OC1M_OCREFTOG TIM2_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */ -# define TIM2_CCMR1_OC1M_OCREFLO TIM2_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */ -# define TIM2_CCMR1_OC1M_OCREFHI TIM2_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */ -# define TIM2_CCMR1_OC1M_PWM1 TIM2_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM2_CCMR1_OC1M_PWM2 TIM2_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM2_CCMR1_OC1M_OPM1 TIM2_CCMR1_OC1M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM2_CCMR1_OC1M_OPM2 TIM2_CCMR1_OC1M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM2_CCMR1_OC1M_COMBINED1 TIM2_CCMR1_OC1M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM2_CCMR1_OC1M_COMBINED2 TIM2_CCMR1_OC1M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM2_CCMR1_OC1M_ASYMM1 TIM2_CCMR1_OC1M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM2_CCMR1_OC1M_ASYMM2 TIM2_CCMR1_OC1M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM2_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1 Clear Enable */ - -#define TIM2_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define TIM2_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define TIM2_CCMR1_OC2M_LO_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode, bits [2:0] */ -#define TIM2_CCMR1_OC2M_HI_SHIFT (24) /* Bit 24: Output Compare 2 Mode, bits [3] */ -#define TIM2_CCMR1_OC2M_BITS(h,l) (((h) << TIM2_CCMR1_OC2M_HI_SHIFT) | ((l) << TIM2_CCMR1_OC2M_LO_SHIFT)) -#define TIM2_CCMR1_OC2M_MASK TIM2_CCMR1_OC2M_BITS(0x1, 0x7) -# define TIM2_CCMR1_OC2M_FRZN TIM2_CCMR1_OC2M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM2_CCMR1_OC2M_CHACT TIM2_CCMR1_OC2M_BITS(0x0, 0x1) /* 0,001: Channel 2 active on match */ -# define TIM2_CCMR1_OC2M_CHINACT TIM2_CCMR1_OC2M_BITS(0x0, 0x2) /* 0,010: Channel 2 inactive on match */ -# define TIM2_CCMR1_OC2M_OCREFTOG TIM2_CCMR1_OC2M_BITS(0x0, 0x3) /* 0,011: OC2REF toggle TIM_CNT=TIM_CCR2 */ -# define TIM2_CCMR1_OC2M_OCREFLO TIM2_CCMR1_OC2M_BITS(0x0, 0x4) /* 0,100: OC2REF forced low */ -# define TIM2_CCMR1_OC2M_OCREFHI TIM2_CCMR1_OC2M_BITS(0x0, 0x5) /* 0,101: OC2REF forced high */ -# define TIM2_CCMR1_OC2M_PWM1 TIM2_CCMR1_OC2M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM2_CCMR1_OC2M_PWM2 TIM2_CCMR1_OC2M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM2_CCMR1_OC2M_OPM1 TIM2_CCMR1_OC2M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM2_CCMR1_OC2M_OPM2 TIM2_CCMR1_OC2M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM2_CCMR1_OC2M_COMBINED1 TIM2_CCMR1_OC2M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM2_CCMR1_OC2M_COMBINED2 TIM2_CCMR1_OC2M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM2_CCMR1_OC2M_ASYMM1 TIM2_CCMR1_OC2M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM2_CCMR1_OC2M_ASYMM2 TIM2_CCMR1_OC2M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM2_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ - -#define TIM2_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define TIM2_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define TIM2_CCMR2_OC3M_LO_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode, bits [2:0] */ -#define TIM2_CCMR2_OC3M_HI_SHIFT (16) /* Bit 16: Output Compare 3 Mode, bits [3] */ -#define TIM2_CCMR2_OC3M_BITS(h,l) (((h) << TIM2_CCMR2_OC3M_HI_SHIFT) | ((l) << TIM2_CCMR2_OC3M_LO_SHIFT)) -#define TIM2_CCMR2_OC3M_MASK TIM2_CCMR2_OC3M_BITS(0x1, 0x7) -# define TIM2_CCMR2_OC3M_FRZN TIM2_CCMR2_OC3M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM2_CCMR2_OC3M_CHACT TIM2_CCMR2_OC3M_BITS(0x0, 0x1) /* 0,001: Channel 3 active on match */ -# define TIM2_CCMR2_OC3M_CHINACT TIM2_CCMR2_OC3M_BITS(0x0, 0x2) /* 0,010: Channel 3 inactive on match */ -# define TIM2_CCMR2_OC3M_OCREFTOG TIM2_CCMR2_OC3M_BITS(0x0, 0x3) /* 0,011: OC3REF toggle TIM_CNT=TIM_CCR3 */ -# define TIM2_CCMR2_OC3M_OCREFLO TIM2_CCMR2_OC3M_BITS(0x0, 0x4) /* 0,100: OC3REF forced low */ -# define TIM2_CCMR2_OC3M_OCREFHI TIM2_CCMR2_OC3M_BITS(0x0, 0x5) /* 0,101: OC3REF forced high */ -# define TIM2_CCMR2_OC3M_PWM1 TIM2_CCMR2_OC3M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM2_CCMR2_OC3M_PWM2 TIM2_CCMR2_OC3M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM2_CCMR2_OC3M_OPM1 TIM2_CCMR2_OC3M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM2_CCMR2_OC3M_OPM2 TIM2_CCMR2_OC3M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM2_CCMR2_OC3M_COMBINED1 TIM2_CCMR2_OC3M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM2_CCMR2_OC3M_COMBINED2 TIM2_CCMR2_OC3M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM2_CCMR2_OC3M_ASYMM1 TIM2_CCMR2_OC3M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM2_CCMR2_OC3M_ASYMM2 TIM2_CCMR2_OC3M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM2_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ - -#define TIM2_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define TIM2_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define TIM2_CCMR2_OC4M_LO_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode, bits [2:0] */ -#define TIM2_CCMR2_OC4M_HI_SHIFT (24) /* Bit 24: Output Compare 4 Mode, bits [3] */ -#define TIM2_CCMR2_OC4M_BITS(h,l) (((h) << TIM2_CCMR2_OC4M_HI_SHIFT) | ((l) << TIM2_CCMR2_OC4M_LO_SHIFT)) -#define TIM2_CCMR2_OC4M_MASK TIM2_CCMR2_OC4M_BITS(0x1, 0x7) -# define TIM2_CCMR2_OC4M_FRZN TIM2_CCMR2_OC4M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM2_CCMR2_OC4M_CHACT TIM2_CCMR2_OC4M_BITS(0x0, 0x1) /* 0,001: Channel 4 active on match */ -# define TIM2_CCMR2_OC4M_CHINACT TIM2_CCMR2_OC4M_BITS(0x0, 0x2) /* 0,010: Channel 4 inactive on match */ -# define TIM2_CCMR2_OC4M_OCREFTOG TIM2_CCMR2_OC4M_BITS(0x0, 0x3) /* 0,011: OC4REF toggle TIM_CNT=TIM_CCR4 */ -# define TIM2_CCMR2_OC4M_OCREFLO TIM2_CCMR2_OC4M_BITS(0x0, 0x4) /* 0,100: OC4REF forced low */ -# define TIM2_CCMR2_OC4M_OCREFHI TIM2_CCMR2_OC4M_BITS(0x0, 0x5) /* 0,101: OC4REF forced high */ -# define TIM2_CCMR2_OC4M_PWM1 TIM2_CCMR2_OC4M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM2_CCMR2_OC4M_PWM2 TIM2_CCMR2_OC4M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM2_CCMR2_OC4M_OPM1 TIM2_CCMR2_OC4M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM2_CCMR2_OC4M_OPM2 TIM2_CCMR2_OC4M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM2_CCMR2_OC4M_COMBINED1 TIM2_CCMR2_OC4M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM2_CCMR2_OC4M_COMBINED2 TIM2_CCMR2_OC4M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM2_CCMR2_OC4M_ASYMM1 TIM2_CCMR2_OC4M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM2_CCMR2_OC4M_ASYMM2 TIM2_CCMR2_OC4M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM2_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ - -#define TIM16_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define TIM16_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define TIM16_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */ -#define TIM16_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */ -#define TIM16_CCMR1_OC1M_BITS(h,l) (((h) << TIM16_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM16_CCMR1_OC1M_LO_SHIFT)) -#define TIM16_CCMR1_OC1M_MASK TIM16_CCMR1_OC1M_BITS(0x1, 0x7) -# define TIM16_CCMR1_OC1M_FRZN TIM16_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM16_CCMR1_OC1M_CHACT TIM16_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */ -# define TIM16_CCMR1_OC1M_CHINACT TIM16_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */ -# define TIM16_CCMR1_OC1M_OCREFTOG TIM16_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */ -# define TIM16_CCMR1_OC1M_OCREFLO TIM16_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */ -# define TIM16_CCMR1_OC1M_OCREFHI TIM16_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */ -# define TIM16_CCMR1_OC1M_PWM1 TIM16_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM16_CCMR1_OC1M_PWM2 TIM16_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ - -#define TIM17_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define TIM17_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define TIM17_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */ -#define TIM17_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */ -#define TIM17_CCMR1_OC1M_BITS(h,l) (((h) << TIM17_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM17_CCMR1_OC1M_LO_SHIFT)) -#define TIM17_CCMR1_OC1M_MASK TIM17_CCMR1_OC1M_BITS(0x1, 0x7) -# define TIM17_CCMR1_OC1M_FRZN TIM17_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM17_CCMR1_OC1M_CHACT TIM17_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */ -# define TIM17_CCMR1_OC1M_CHINACT TIM17_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */ -# define TIM17_CCMR1_OC1M_OCREFTOG TIM17_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */ -# define TIM17_CCMR1_OC1M_OCREFLO TIM17_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */ -# define TIM17_CCMR1_OC1M_OCREFHI TIM17_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */ -# define TIM17_CCMR1_OC1M_PWM1 TIM17_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM17_CCMR1_OC1M_PWM2 TIM17_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ - -/* Capture/compare mode registers -- Input Capture mode */ - -#define TIM1_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define TIM1_CCMR1_IC1PSC_MASK (0x3 << TIM1_CCMR1_IC1PSC_SHIFT) -# define TIM1_CCMR1_IC1PSC_NOPSC (0x0 << TIM1_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM1_CCMR1_IC1PSC_EVERY2 (0x1 << TIM1_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM1_CCMR1_IC1PSC_EVERY4 (0x2 << TIM1_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM1_CCMR1_IC1PSC_EVERY8 (0x3 << TIM1_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM1_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define TIM1_CCMR1_IC1F_MASK (0xf << TIM1_CCMR1_IC1F_SHIFT) -# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ -#define TIM1_CCMR1_IC2PSC_MASK (0x3 << TIM1_CCMR1_IC2PSC_SHIFT) -# define TIM1_CCMR1_IC2PSC_NOPSC (0x0 << TIM1_CCMR1_IC2PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM1_CCMR1_IC2PSC_EVERY2 (0x1 << TIM1_CCMR1_IC2PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM1_CCMR1_IC2PSC_EVERY4 (0x2 << TIM1_CCMR1_IC2PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM1_CCMR1_IC2PSC_EVERY8 (0x3 << TIM1_CCMR1_IC2PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM1_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ -#define TIM1_CCMR1_IC2F_MASK (0xf << TIM1_CCMR1_IC2F_SHIFT) -# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ -#define TIM1_CCMR2_IC3PSC_MASK (0x3 << TIM1_CCMR2_IC3PSC_SHIFT) -# define TIM1_CCMR2_IC3PSC_NOPSC (0x0 << TIM1_CCMR2_IC3PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM1_CCMR2_IC3PSC_EVERY2 (0x1 << TIM1_CCMR2_IC3PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM1_CCMR2_IC3PSC_EVERY4 (0x2 << TIM1_CCMR2_IC3PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM1_CCMR2_IC3PSC_EVERY8 (0x3 << TIM1_CCMR2_IC3PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM1_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ -#define TIM1_CCMR2_IC3F_MASK (0xf << TIM1_CCMR2_IC3F_SHIFT) -# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ -#define TIM1_CCMR2_IC4PSC_MASK (0x3 << TIM1_CCMR2_IC4PSC_SHIFT) -# define TIM1_CCMR2_IC4PSC_NOPSC (0x0 << TIM1_CCMR2_IC4PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM1_CCMR2_IC4PSC_EVERY2 (0x1 << TIM1_CCMR2_IC4PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM1_CCMR2_IC4PSC_EVERY4 (0x2 << TIM1_CCMR2_IC4PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM1_CCMR2_IC4PSC_EVERY8 (0x3 << TIM1_CCMR2_IC4PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM1_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ -#define TIM1_CCMR2_IC4F_MASK (0xf << TIM1_CCMR2_IC4F_SHIFT) -# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define TIM2_CCMR1_IC1PSC_MASK (0x3 << TIM2_CCMR1_IC1PSC_SHIFT) -# define TIM2_CCMR1_IC1PSC_NOPSC (0x0 << TIM2_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM2_CCMR1_IC1PSC_EVERY2 (0x1 << TIM2_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM2_CCMR1_IC1PSC_EVERY4 (0x2 << TIM2_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM2_CCMR1_IC1PSC_EVERY8 (0x3 << TIM2_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM2_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define TIM2_CCMR1_IC1F_MASK (0xf << TIM2_CCMR1_IC1F_SHIFT) -# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ -#define TIM2_CCMR1_IC2PSC_MASK (0x3 << TIM2_CCMR1_IC2PSC_SHIFT) -# define TIM2_CCMR1_IC2PSC_NOPSC (0x0 << TIM2_CCMR1_IC2PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM2_CCMR1_IC2PSC_EVERY2 (0x1 << TIM2_CCMR1_IC2PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM2_CCMR1_IC2PSC_EVERY4 (0x2 << TIM2_CCMR1_IC2PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM2_CCMR1_IC2PSC_EVERY8 (0x3 << TIM2_CCMR1_IC2PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM2_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ -#define TIM2_CCMR1_IC2F_MASK (0xf << TIM2_CCMR1_IC2F_SHIFT) -# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ -#define TIM2_CCMR2_IC3PSC_MASK (0x3 << TIM2_CCMR2_IC3PSC_SHIFT) -# define TIM2_CCMR2_IC3PSC_NOPSC (0x0 << TIM2_CCMR2_IC3PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM2_CCMR2_IC3PSC_EVERY2 (0x1 << TIM2_CCMR2_IC3PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM2_CCMR2_IC3PSC_EVERY4 (0x2 << TIM2_CCMR2_IC3PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM2_CCMR2_IC3PSC_EVERY8 (0x3 << TIM2_CCMR2_IC3PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM2_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ -#define TIM2_CCMR2_IC3F_MASK (0xf << TIM2_CCMR2_IC3F_SHIFT) -# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ -#define TIM2_CCMR2_IC4PSC_MASK (0x3 << TIM2_CCMR2_IC4PSC_SHIFT) -# define TIM2_CCMR2_IC4PSC_NOPSC (0x0 << TIM2_CCMR2_IC4PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM2_CCMR2_IC4PSC_EVERY2 (0x1 << TIM2_CCMR2_IC4PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM2_CCMR2_IC4PSC_EVERY4 (0x2 << TIM2_CCMR2_IC4PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM2_CCMR2_IC4PSC_EVERY8 (0x3 << TIM2_CCMR2_IC4PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM2_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ -#define TIM2_CCMR2_IC4F_MASK (0xf << TIM2_CCMR2_IC4F_SHIFT) -# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM16_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define TIM16_CCMR1_IC1PSC_MASK (0x3 << TIM16_CCMR1_IC1PSC_SHIFT) -# define TIM16_CCMR1_IC1PSC_NOPSC (0x0 << TIM16_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM16_CCMR1_IC1PSC_EVERY2 (0x1 << TIM16_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM16_CCMR1_IC1PSC_EVERY4 (0x2 << TIM16_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM16_CCMR1_IC1PSC_EVERY8 (0x3 << TIM16_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM16_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define TIM16_CCMR1_IC1F_MASK (0xf << TIM16_CCMR1_IC1F_SHIFT) -# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM17_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define TIM17_CCMR1_IC1PSC_MASK (0x3 << TIM17_CCMR1_IC1PSC_SHIFT) -# define TIM17_CCMR1_IC1PSC_NOPSC (0x0 << TIM17_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM17_CCMR1_IC1PSC_EVERY2 (0x1 << TIM17_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM17_CCMR1_IC1PSC_EVERY4 (0x2 << TIM17_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM17_CCMR1_IC1PSC_EVERY8 (0x3 << TIM17_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM17_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define TIM17_CCMR1_IC1F_MASK (0xf << TIM17_CCMR1_IC1F_SHIFT) -# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -/* Capture/compare enable register */ - -#define TIM1_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define TIM1_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define TIM1_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable */ -#define TIM1_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */ -#define TIM1_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ -#define TIM1_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity */ -#define TIM1_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable */ -#define TIM1_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 complementary output polarity */ -#define TIM1_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ -#define TIM1_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output polarity */ -#define TIM1_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable */ -#define TIM1_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 complementary output polarity */ -#define TIM1_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ -#define TIM1_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output polarity */ -#define TIM1_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 complementary output polarity */ -#define TIM1_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ -#define TIM1_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output polarity */ -#define TIM1_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ -#define TIM1_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output polarity */ - -#define TIM2_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define TIM2_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define TIM2_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */ -#define TIM2_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ -#define TIM2_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity */ -#define TIM2_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 complementary output polarity */ -#define TIM2_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ -#define TIM2_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output polarity */ -#define TIM2_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 complementary output polarity */ -#define TIM2_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ -#define TIM2_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output polarity */ -#define TIM2_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 complementary output polarity */ - -#define TIM16_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define TIM16_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define TIM16_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable */ -#define TIM16_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */ - -#define TIM17_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define TIM17_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define TIM17_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable */ -#define TIM17_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */ - -/* Counter register */ - -#define TIM1_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define TIM1_CNT_MASK (0xffff << TIM1_CNT_SHIFT) -#define TIM1_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ - -#define TIM2_CNT_SHIFT (0) /* Bits 0-32: Timer counter value, UIFREMAP = 0 */ - /* Bits 0-31: Timer counter value, UIFREMAP = 1 */ -#define TIM2_CNT_MASK (0xffffffff << TIM2_CNT_SHIFT) -#define TIM2_CNT_MASK31 (0x7fffffff << TIM2_CNT_SHIFT) - -#define TIM2_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy, if UIFREMAP = 1 */ - -#define TIM16_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define TIM16_CNT_MASK (0xffff << TIM16_CNT_SHIFT) -#define TIM16_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ - -#define TIM17_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define TIM17_CNT_MASK (0xffff << TIM17_CNT_SHIFT) -#define TIM17_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ - -/* Prescaler register */ - -#define TIM1_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */ -#define TIM1_PSC_MASK (0xffff << TIM1_PSC_SHIFT) - -#define TIM2_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */ -#define TIM2_PSC_MASK (0xffff << TIM2_PSC_SHIFT) - -#define TIM16_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */ -#define TIM16_PSC_MASK (0xffff << TIM16_PSC_SHIFT) - -#define TIM17_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */ -#define TIM17_PSC_MASK (0xffff << TIM17_PSC_SHIFT) - -/* Auto-reload register */ - -#define TIM1_ARR_SHIFT (0) /* Bits 0-15: Timer auto-reload value */ -#define TIM1_ARR_MASK (0xffff << TIM1_ARR_SHIFT) - -#define TIM2_ARR_SHIFT (0) /* Bits 0-31: Timer auto-reload value */ -#define TIM2_ARR_MASK (0xffffffff << TIM2_ARR_SHIFT) - -#define TIM16_ARR_SHIFT (0) /* Bits 0-15: Timer auto-reload value */ -#define TIM16_ARR_MASK (0xffff << TIM16_ARR_SHIFT) - -#define TIM17_ARR_SHIFT (0) /* Bits 0-15: Timer auto-reload value */ -#define TIM17_ARR_MASK (0xffff << TIM17_ARR_SHIFT) - -/* Repetition counter register */ - -#define TIM1_RCR_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ -#define TIM1_RCR_MASK (0xffff << TIM1_RCR_SHIFT) - -#define TIM16_RCR_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ -#define TIM16_RCR_MASK (0xff << TIM16_RCR_SHIFT) - -#define TIM17_RCR_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ -#define TIM17_RCR_MASK (0xff << TIM17_RCR_SHIFT) - -/* Capture/compare registers */ - -#define TIM1_CCR1_SHIFT (0) /* Bits 0-15: Capture/Compare 1 value */ -#define TIM1_CCR1_MASK (0xffff << TIM1_CCR1_SHIFT) -#define TIM1_CCR2_SHIFT (0) /* Bits 0-15: Capture/Compare 2 value */ -#define TIM1_CCR2_MASK (0xffff << TIM1_CCR2_SHIFT) -#define TIM1_CCR3_SHIFT (0) /* Bits 0-15: Capture/Compare 3 value */ -#define TIM1_CCR3_MASK (0xffff << TIM1_CCR3_SHIFT) -#define TIM1_CCR4_SHIFT (0) /* Bits 0-15: Capture/Compare 4 value */ -#define TIM1_CCR4_MASK (0xffff << TIM1_CCR4_SHIFT) -#define TIM1_CCR5_SHIFT (0) /* Bits 0-15: Capture/Compare 5 value */ -#define TIM1_CCR5_MASK (0xffff << TIM1_CCR5_SHIFT) -#define TIM1_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ -#define TIM1_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ -#define TIM1_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ -#define TIM1_CCR6_SHIFT (0) /* Bits 0-15: Capture/Compare 6 value */ -#define TIM1_CCR6_MASK (0xffff << TIM1_CCR6_SHIFT) - -#define TIM2_CCR1_SHIFT (0) /* Bits 0-31: Capture/Compare 1 value */ -#define TIM2_CCR1_MASK (0xffffffff << TIM2_CCR1_SHIFT) -#define TIM2_CCR2_SHIFT (0) /* Bits 0-31: Capture/Compare 2 value */ -#define TIM2_CCR2_MASK (0xffffffff << TIM2_CCR2_SHIFT) -#define TIM2_CCR3_SHIFT (0) /* Bits 0-31: Capture/Compare 3 value */ -#define TIM2_CCR3_MASK (0xffffffff << TIM2_CCR3_SHIFT) -#define TIM2_CCR4_SHIFT (0) /* Bits 0-31: Capture/Compare 4 value */ -#define TIM2_CCR4_MASK (0xffffffff << TIM2_CCR4_SHIFT) - -#define TIM16_CCR1_SHIFT (0) /* Bits 0-15: Capture/Compare 1 value */ -#define TIM16_CCR1_MASK (0xffff << TIM16_CCR1_SHIFT) - -#define TIM17_CCR1_SHIFT (0) /* Bits 0-15: Capture/Compare 1 value */ -#define TIM17_CCR1_MASK (0xffff << TIM17_CCR1_SHIFT) - -/* Break and dead-time register */ - -#define TIM1_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define TIM1_BDTR_DTG_MASK (0xff << TIM1_BDTR_DTG_SHIFT) -#define TIM1_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define TIM1_BDTR_LOCK_MASK (0x3 << TIM1_BDTR_LOCK_SHIFT) -# define TIM1_BDTR_LOCKOFF (0x0 << TIM1_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define TIM1_BDTR_LOCK1 (0x1 << TIM1_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define TIM1_BDTR_LOCK2 (0x2 << TIM1_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define TIM1_BDTR_LOCK3 (0x3 << TIM1_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ - -#define TIM1_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define TIM1_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define TIM1_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define TIM1_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define TIM1_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define TIM1_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define TIM1_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -#define TIM1_BDTR_BKF_MASK (0xf << TIM1_BDTR_BKF_SHIFT) -# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ -#define TIM1_BDTR_BK2F_MASK (0xf << TIM1_BDTR_BK2F_SHIFT) -# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ -#define TIM1_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ -#define TIM1_BDTR_BKDSRM (1 << 26) /* Bit 26: Break Disarm */ -#define TIM1_BDTR_BK2DSRM (1 << 27) /* Bit 27: Break 2 Disarm */ -#define TIM1_BDTR_BKBID (1 << 28) /* Bit 28: Break Bidirectional */ -#define TIM1_BDTR_BK2BID (1 << 29) /* Bit 29: Break 2 Bidirectional */ - -#define TIM16_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define TIM16_BDTR_DTG_MASK (0xff << TIM16_BDTR_DTG_SHIFT) -#define TIM16_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define TIM16_BDTR_LOCK_MASK (0x3 << TIM16_BDTR_LOCK_SHIFT) -# define TIM16_BDTR_LOCKOFF (0x0 << TIM16_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define TIM16_BDTR_LOCK1 (0x1 << TIM16_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define TIM16_BDTR_LOCK2 (0x2 << TIM16_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define TIM16_BDTR_LOCK3 (0x3 << TIM16_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ - -#define TIM16_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define TIM16_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define TIM16_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define TIM16_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define TIM16_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define TIM16_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define TIM16_BDTR_BKDSRM (1 << 26) /* Bit 26: Break Disarm */ -#define TIM16_BDTR_BKBID (1 << 28) /* Bit 28: Break Bidirectional */ - -#define TIM17_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define TIM17_BDTR_DTG_MASK (0xff << TIM17_BDTR_DTG_SHIFT) -#define TIM17_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define TIM17_BDTR_LOCK_MASK (0x3 << TIM17_BDTR_LOCK_SHIFT) -# define TIM17_BDTR_LOCKOFF (0x0 << TIM17_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define TIM17_BDTR_LOCK1 (0x1 << TIM17_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define TIM17_BDTR_LOCK2 (0x2 << TIM17_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define TIM17_BDTR_LOCK3 (0x3 << TIM17_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ - -#define TIM17_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define TIM17_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define TIM17_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define TIM17_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define TIM17_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define TIM17_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define TIM17_BDTR_BKDSRM (1 << 26) /* Bit 26: Break Disarm */ -#define TIM17_BDTR_BKBID (1 << 28) /* Bit 28: Break Bidirectional */ - -/* DMA control register */ - -#define TIM1_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define TIM1_DCR_DBA_MASK (0x1f << TIM1_DCR_DBA_SHIFT) -#define TIM1_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define TIM1_DCR_DBL_MASK (0x1f << TIM1_DCR_DBL_SHIFT) -# define TIM1_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -#define TIM2_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define TIM2_DCR_DBA_MASK (0x1f << TIM2_DCR_DBA_SHIFT) -#define TIM2_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define TIM2_DCR_DBL_MASK (0x1f << TIM2_DCR_DBL_SHIFT) -# define TIM2_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -#define TIM16_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define TIM16_DCR_DBA_MASK (0x1f << TIM16_DCR_DBA_SHIFT) -#define TIM16_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define TIM16_DCR_DBL_MASK (0x1f << TIM16_DCR_DBL_SHIFT) -# define TIM16_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -#define TIM17_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define TIM17_DCR_DBA_MASK (0x1f << TIM17_DCR_DBA_SHIFT) -#define TIM17_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define TIM17_DCR_DBL_MASK (0x1f << TIM17_DCR_DBL_SHIFT) -# define TIM17_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -/* DMA address register */ - -#define TIM1_DMAR_SHIFT (0) /* Bits 0-31: DMA register for burst accesses */ -#define TIM1_DMAR_MASK (0xffffffff << TIM1_DMAR_SHIFT) - -#define TIM2_DMAR_SHIFT (0) /* Bits 0-15: DMA register for burst accesses */ -#define TIM2_DMAR_MASK (0xffff << TIM2_DMAR_SHIFT) - -#define TIM16_DMAR_SHIFT (0) /* Bits 0-15: DMA register for burst accesses */ -#define TIM16_DMAR_MASK (0xffff << TIM16_DMAR_SHIFT) - -#define TIM17_DMAR_SHIFT (0) /* Bits 0-15: DMA register for burst accesses */ -#define TIM17_DMAR_MASK (0xffff << TIM17_DMAR_SHIFT) - -/* Option register 1 */ - -#define TIM1_OR1_ETR_ADC_RMP_SHIFT (0) /* Bits 0-1: TIM1 ETR to ADC AWD remap */ -#define TIM1_OR1_ETR_ADC_RMP_MASK (0x3 << TIM1_OR1_ETR_ADC_RMP_SHIFT) -# define TIM1_OR1_ETR_ADC_RMP_NC (0x0 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 00: ETR not connected to ADC AWD */ -# define TIM1_OR1_ETR_ADC_RMP_AWD1 (0x1 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 01: ETR connected to ADC AWD1 */ -# define TIM1_OR1_ETR_ADC_RMP_AWD2 (0x2 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 10: ETR connected to ADC AWD2 */ -# define TIM1_OR1_ETR_ADC_RMP_AWD3 (0x3 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 11: ETR connected to ADC AWD3 */ - -#define TIM1_OR1_TI1_RMP (1 << 4) /* Bit 4: Input capture 1 remap */ -# define TIM1_OR1_TI1_RMP_IO (0 << 4) /* 0: TIM1 Input capture 1 is connected to I/O */ -# define TIM1_OR1_TI1_RMP_CMP1OUT (1 << 4) /* 1: TIM1 Input capture 1 is connected to COMP1 output */ - -#define TIM2_OR1_ITR_RMP (1 << 0) /* Bit 0: Internal trigger remap */ -# define TIM2_OR1_ITR_RMP_NC (0 << 0) /* 0: TIM2 Internal trigger ITR2 is not connected */ -# define TIM2_OR1_ITR_RMP_USB_SOF (1 << 0) /* 1: TIM2 Internal trigger ITR2 is connected to USB SOF */ - -#define TIM2_OR1_ETR_RMP (1 << 1) /* Bit 1: External trigger 1 remap */ -# define TIM2_OR1_ETR_RMP_GPIO (0 << 1) /* 0: TIM2 ETR2 is connected to GPIO */ -# define TIM2_OR1_ETR_RMP_LSE (1 << 1) /* 1: LSE internal clock is connected to TIM2 ETR */ - -#define TIM2_OR1_TI4_RMP_SHIFT (2) /* Bits 2-3: Timer input 4 remap */ -#define TIM2_OR1_TI4_RMP_MASK (0x3 << TIM2_OR1_TI4_RMP_SHIFT) -# define TIM2_OR1_TI4_RMP_GPIO (0x0 << TIM2_OR1_TI4_RMP_SHIFT) /* 00: TI4 connected to GPIO */ -# define TIM2_OR1_TI4_RMP_CMP1OUT (0x1 << TIM2_OR1_TI4_RMP_SHIFT) /* 01: TI4 connected to COMP1 output */ -# define TIM2_OR1_TI4_RMP_CMP2OUT (0x2 << TIM2_OR1_TI4_RMP_SHIFT) /* 10: TI4 connected to COMP2 output */ -# define TIM2_OR1_TI4_RMP_CMP1CMP2 (0x3 << TIM2_OR1_TI4_RMP_SHIFT) /* 11: TI4 connected to OR between COMP1-2 */ - -#define TIM16_OR1_TI1_RMP_SHIFT (0) /* Bits 0-1: TIM16 input 1 connection */ -#define TIM16_OR1_TI1_RMP_MASK (0x3 << TIM16_OR1_TI1_RMP_SHIFT) -# define TIM16_OR1_TI1_RMP_GPIO (0x0 << TIM16_OR1_TI1_RMP_SHIFT) /* 00: TI1 connected to GPIO */ -# define TIM16_OR1_TI1_RMP_LSI (0x1 << TIM16_OR1_TI1_RMP_SHIFT) /* 01: TI1 connected to LSI */ -# define TIM16_OR1_TI1_RMP_LSE (0x2 << TIM16_OR1_TI1_RMP_SHIFT) /* 10: TI1 connected to LSE */ -# define TIM16_OR1_TI1_RMP_RTCWKUP (0x3 << TIM16_OR1_TI1_RMP_SHIFT) /* 11: TI1 connected to RTC wake-up interrupt */ - -#define TIM17_OR1_TI1_RMP_SHIFT (0) /* Bits 0-1: TIM17 input 1 connection */ -#define TIM17_OR1_TI1_RMP_MASK (0x3 << TIM17_OR1_TI1_RMP_SHIFT) -# define TIM17_OR1_TI1_RMP_GPIO (0x0 << TIM17_OR1_TI1_RMP_SHIFT) /* 00: TI1 connected to GPIO */ -# define TIM17_OR1_TI1_RMP_MSI (0x1 << TIM17_OR1_TI1_RMP_SHIFT) /* 01: TI1 connected to MSI */ -# define TIM17_OR1_TI1_RMP_HSEd32 (0x2 << TIM17_OR1_TI1_RMP_SHIFT) /* 10: TI1 connected to HSE/32 */ -# define TIM17_OR1_TI1_RMP_MCO (0x3 << TIM17_OR1_TI1_RMP_SHIFT) /* 11: TI1 connected to MCO */ - -/* Alternate function registers */ - -#define TIM1_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ -#define TIM1_AF1_BKCMP1E (1 << 1) /* Bit 1: BRK COMP1 enable */ -#define TIM1_AF1_BKCMP2E (1 << 2) /* Bit 2: BRK COMP2 enable */ -#define TIM1_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ -#define TIM1_AF1_BKCMP1P (1 << 10) /* Bit 10: BRK COMP1 input polarity */ -#define TIM1_AF1_BKCMP2P (1 << 11) /* Bit 11: BRK COMP2 input polarity */ -#define TIM1_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection */ -#define TIM1_AF1_ETRSEL_MASK (0xf << TIM1_AF1_ETRSEL_SHIFT) -# define TIM1_AF1_ETRSEL_LEGACY (0x0 << TIM1_AF1_ETRSEL_SHIFT) /* 0000: ETR legacy mode */ -# define TIM1_AF1_ETRSEL_CMP1OUT (0x1 << TIM1_AF1_ETRSEL_SHIFT) /* 0001: COMP1 output */ -# define TIM1_AF1_ETRSEL_CMP2OUT (0x2 << TIM1_AF1_ETRSEL_SHIFT) /* 0010: COMP2 output */ - -#define TIM1_AF2_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */ -#define TIM1_AF2_BK2CMP1E (1 << 1) /* Bit 1: BRK2 COMP1 enable */ -#define TIM1_AF2_BK2CMP2E (1 << 2) /* Bit 2: BRK2 COMP2 enable */ -#define TIM1_AF2_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN input polarity */ -#define TIM1_AF2_BK2CMP1P (1 << 10) /* Bit 10: BRK2 COMP1 input polarity */ -#define TIM1_AF2_BK2CMP2P (1 << 11) /* Bit 11: BRK2 COMP2 input polarity */ - -#define TIM2_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection */ -#define TIM2_AF1_ETRSEL_MASK (0xf << TIM2_AF1_ETRSEL_SHIFT) -# define TIM2_AF1_ETRSEL_GPIO_LSE (0x0 << TIM2_AF1_ETRSEL_SHIFT) /* 0000: GPIO or LSE clock */ -# define TIM2_AF1_ETRSEL_CMP1OUT (0x1 << TIM2_AF1_ETRSEL_SHIFT) /* 0001: COMP1 output */ -# define TIM2_AF1_ETRSEL_CMP2OUT (0x2 << TIM2_AF1_ETRSEL_SHIFT) /* 0010: COMP2 output */ - -#define TIM16_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ -#define TIM16_AF1_BKCMP1E (1 << 1) /* Bit 1: BRK COMP1 enable */ -#define TIM16_AF1_BKCMP2E (1 << 2) /* Bit 2: BRK COMP2 enable */ -#define TIM16_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ -#define TIM16_AF1_BKCMP1P (1 << 10) /* Bit 10: BRK COMP1 input polarity */ -#define TIM16_AF1_BKCMP2P (1 << 11) /* Bit 11: BRK COMP2 input polarity */ - -#define TIM17_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ -#define TIM17_AF1_BKCMP1E (1 << 1) /* Bit 1: BRK COMP1 enable */ -#define TIM17_AF1_BKCMP2E (1 << 2) /* Bit 2: BRK COMP2 enable */ -#define TIM17_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ -#define TIM17_AF1_BKCMP1P (1 << 10) /* Bit 10: BRK COMP1 input polarity */ -#define TIM17_AF1_BKCMP2P (1 << 11) /* Bit 11: BRK COMP2 input polarity */ - -/* Timer input selection register */ - -#define TIM1_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */ -#define TIM1_TISEL_TI1SEL_MASK (0xf << TIM1_TISEL_TI1SEL_SHIFT) -# define TIM1_TISEL_TI1SEL_CH1 (0x0 << TIM1_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ - -#define TIM1_TISEL_TI2SEL_SHIFT (8) /* Bits 8-11: selects TI2[0] to TI2[15] input */ -#define TIM1_TISEL_TI2SEL_MASK (0xf << TIM1_TISEL_TI2SEL_SHIFT) -# define TIM1_TISEL_TI2SEL_CH2 (0x0 << TIM1_TISEL_TI2SEL_SHIFT) /* 0000: CH2 input */ - -#define TIM1_TISEL_TI3SEL_SHIFT (16) /* Bits 16-19: selects TI3[0] to TI3[15] input */ -#define TIM1_TISEL_TI3SEL_MASK (0xf << TIM1_TISEL_TI3SEL_SHIFT) -# define TIM1_TISEL_TI3SEL_CH3 (0x0 << TIM1_TISEL_TI3SEL_SHIFT) /* 0000: CH3 input */ - -#define TIM1_TISEL_TI4SEL_SHIFT (24) /* Bits 24-27: selects TI4[0] to TI4[15] input */ -#define TIM1_TISEL_TI4SEL_MASK (0xf << TIM1_TISEL_TI4SEL_SHIFT) -# define TIM1_TISEL_TI4SEL_CH4 (0x0 << TIM1_TISEL_TI4SEL_SHIFT) /* 0000: CH4 input */ - -#define TIM2_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */ -#define TIM2_TISEL_TI1SEL_MASK (0xf << TIM2_TISEL_TI1SEL_SHIFT) -# define TIM2_TISEL_TI1SEL_CH1 (0x0 << TIM2_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ - -#define TIM2_TISEL_TI2SEL_SHIFT (8) /* Bits 8-11: selects TI2[0] to TI2[15] input */ -#define TIM2_TISEL_TI2SEL_MASK (0xf << TIM2_TISEL_TI2SEL_SHIFT) -# define TIM2_TISEL_TI2SEL_CH2 (0x0 << TIM2_TISEL_TI2SEL_SHIFT) /* 0000: CH2 input */ - -#define TIM16_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */ -#define TIM16_TISEL_TI1SEL_MASK (0xf << TIM16_TISEL_TI1SEL_SHIFT) -# define TIM16_TISEL_TI1SEL_CH1 (0x0 << TIM16_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ - -#define TIM17_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */ -#define TIM17_TISEL_TI1SEL_MASK (0xf << TIM17_TISEL_TI1SEL_SHIFT) -# define TIM17_TISEL_TI1SEL_CH1 (0x0 << TIM17_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ - -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H */ diff --git a/arch/arm/src/stm32wb/stm32.h b/arch/arm/src/stm32wb/stm32.h index 539f3eb9ea420..5c52b14c8ba4b 100644 --- a/arch/arm/src/stm32wb/stm32.h +++ b/arch/arm/src/stm32wb/stm32.h @@ -37,6 +37,8 @@ /* Peripherals **************************************************************/ #include "chip.h" +#include "stm32wb_rcc.h" +#include "stm32wb_gpio.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c deleted file mode 100644 index c308a611db3c9..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ /dev/null @@ -1,300 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_freerun.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "stm32wb_freerun.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_handler - * - * Description: - * Timer interrupt callback. When the freerun timer counter overflows, - * this interrupt will occur. We will just increment an overflow count. - * - * Input Parameters: - * tch - The handle that represents the timer state - * arg - An opaque argument provided when the interrupt was registered - * sr - The value of the timer interrupt status register at the time - * that the interrupt occurred. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING -static int stm32_freerun_handler(int irq, void *context, void *arg) -{ - struct stm32_freerun_s *freerun = (struct stm32_freerun_s *)arg; - - DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); - freerun->overflow++; - - STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - return OK; -} -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(freerun != NULL && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - freerun->frequency = frequency; - - freerun->tch = stm32_tim_init(chan); - if (!freerun->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(freerun->tch, frequency); - - /* Initialize the remaining fields in the state structure and return - * success. - */ - - freerun->chan = chan; - freerun->width = STM32_TIM_GETWIDTH(freerun->tch); - -#ifdef CONFIG_CLOCK_TIMEKEEPING - freerun->counter_mask = 0xffffffff; -#endif - -#ifndef CONFIG_CLOCK_TIMEKEEPING - freerun->overflow = 0; - - /* Set up to receive the callback when the counter overflow occurs */ - - STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); -#endif - - /* Set timer period */ - - STM32_TIM_SETPERIOD(freerun->tch, - (uint32_t)((1ull << freerun->width) - 1)); - - /* Start the counter */ - - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); - -#ifndef CONFIG_CLOCK_TIMEKEEPING - STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - STM32_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time from the free-running - * timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts) -{ - uint64_t usec; - uint32_t counter; - uint32_t verify; - uint32_t overflow; - uint32_t sec; - int pending; - irqstate_t flags; - - DEBUGASSERT(freerun && freerun->tch && ts); - - /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32_tc_getpending() will reset the pending - * interrupt status. If we do not handle the overflow here then, it will - * be lost. - */ - - flags = enter_critical_section(); - - overflow = freerun->overflow; - counter = STM32_TIM_GETCOUNTER(freerun->tch); - pending = STM32_TIM_CHECKINT(freerun->tch, 0); - verify = STM32_TIM_GETCOUNTER(freerun->tch); - - /* If an interrupt was pending before we re-enabled interrupts, - * then the overflow needs to be incremented. - */ - - if (pending) - { - STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - - /* Increment the overflow count and use the value of the - * guaranteed to be AFTER the overflow occurred. - */ - - overflow++; - counter = verify; - - /* Update freerun overflow counter. */ - - freerun->overflow = overflow; - } - - leave_critical_section(flags); - - tmrinfo("counter=%" PRIu32 " (%" PRIu32 ") overflow=%" PRIu32 - ", pending=%i\n", - counter, verify, overflow, pending); - tmrinfo("frequency=%" PRIu32 "\n", freerun->frequency); - - /* Convert the whole thing to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = ((((uint64_t)overflow << freerun->width) + - (uint64_t)counter) * USEC_PER_SEC) / freerun->frequency; - - /* And return the value of the timer */ - - sec = (uint32_t)(usec / USEC_PER_SEC); - ts->tv_sec = sec; - ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - tmrinfo("usec=%llu ts=(%jd, %ld)\n", - usec, (intmax_t)ts->tv_sec, ts->tv_nsec); - - return OK; -} - -#else /* CONFIG_CLOCK_TIMEKEEPING */ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - uint64_t *counter) -{ - *counter = STM32_TIM_GETCOUNTER(freerun->tch); - return OK; -} - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) -{ - DEBUGASSERT(freerun && freerun->tch); - - /* Now we can disable the timer interrupt and disable the timer. */ - - STM32_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); - - /* Free the timer */ - - stm32_tim_deinit(freerun->tch); - freerun->tch = NULL; - - return OK; -} - -#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h deleted file mode 100644 index ae4dd49ba9c3a..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_freerun.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "stm32wb_tim.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* The freerun client must allocate an instance of this structure and called - * stm32_freerun_initialize() before using the freerun facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_freerun_s -{ - uint8_t chan; /* The timer/counter in use */ - uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - uint32_t frequency; - -#ifndef CONFIG_CLOCK_TIMEKEEPING - uint32_t overflow; /* Timer counter overflow */ -#endif - -#ifdef CONFIG_CLOCK_TIMEKEEPING - uint64_t counter_mask; -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts); - -#else /* CONFIG_CLOCK_TIMEKEEPING */ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - uint64_t *counter); - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.c b/arch/arm/src/stm32wb/stm32wb_ipcc.c index c9b889aec9a02..b03cb6534406c 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.c +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.c @@ -31,7 +31,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32wb_ipcc.h" -#include "hardware/stm32wb_rcc.h" +#include "hardware/stm32_rcc.h" #include "hardware/stm32wb_exti.h" #include "hardware/stm32wb_pwr.h" diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c deleted file mode 100644 index 80e63c4b4e9f8..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ /dev/null @@ -1,459 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_oneshot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "stm32wb_oneshot.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_oneshot_handler(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Common timer interrupt callback. When any oneshot timer interrupt - * expires, this function will be called. It will forward the call to - * the next level up. - * - * Input Parameters: - * oneshot - The state associated with the expired timer - * - * Returned Value: - * Always returns OK - * - ****************************************************************************/ - -static int stm32_oneshot_handler(int irq, void *context, void *arg) -{ - struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *)arg; - oneshot_handler_t oneshot_handler; - void *oneshot_arg; - - tmrinfo("Expired...\n"); - DEBUGASSERT(oneshot != NULL && oneshot->handler); - - /* The clock was stopped, but not disabled when the RC match occurred. - * Disable the TC now and disable any further interrupts. - */ - - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - - /* The timer is no longer running */ - - oneshot->running = false; - - /* Forward the event, clearing out any vestiges */ - - oneshot_handler = (oneshot_handler_t)oneshot->handler; - oneshot->handler = NULL; - oneshot_arg = (void *)oneshot->arg; - oneshot->arg = NULL; - - oneshot_handler(oneshot_arg); - return OK; -} - -/**************************************************************************** - * Name: stm32_allocate_handler - * - * Description: - * Allocate a timer callback handler for the oneshot instance. - * - * Input Parameters: - * oneshot - The state instance the new oneshot timer - * - * Returned Value: - * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. - * - ****************************************************************************/ - -static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) -{ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - int ret = -EBUSY; - int i; - - /* Search for an unused handler */ - - for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) - { - /* Is this handler available? */ - - if (g_oneshot[i] == NULL) - { - /* Yes... assign it to this oneshot */ - - g_oneshot[i] = oneshot; - oneshot->cbndx = i; - ret = OK; - break; - } - } - - return ret; - -#else - if (g_oneshot[0] == NULL) - { - g_oneshot[0] = oneshot; - return OK; - } - - return -EBUSY; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, - int chan, uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(oneshot && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - oneshot->frequency = frequency; - - oneshot->tch = stm32_tim_init(chan); - if (!oneshot->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(oneshot->tch, frequency); - - /* Initialize the remaining fields in the state structure. */ - - oneshot->chan = chan; - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - - /* Assign a callback handler to the oneshot */ - - return stm32_allocate_handler(oneshot); -} - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, - uint64_t *usec) -{ - DEBUGASSERT(oneshot != NULL && usec != NULL); - - *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * - (uint64_t)USEC_PER_SEC; - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts) -{ - uint64_t usec; - uint64_t period; - irqstate_t flags; - - tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", - handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); - DEBUGASSERT(oneshot && handler && ts); - DEBUGASSERT(oneshot->tch); - - /* Was the oneshot already running? */ - - flags = enter_critical_section(); - if (oneshot->running) - { - /* Yes.. then cancel it */ - - tmrinfo("Already running... cancelling\n"); - stm32_oneshot_cancel(oneshot, NULL); - } - - /* Save the new handler and its argument */ - - oneshot->handler = handler; - oneshot->arg = arg; - - /* Express the delay in microseconds */ - - usec = ts->tv_sec * USEC_PER_SEC + - (ts->tv_nsec / NSEC_PER_USEC); - - /* Get the timer counter frequency and determine the number of counts need - * to achieve the requested delay. - * - * frequency = ticks / second - * ticks = seconds * frequency - * = (usecs * frequency) / USEC_PER_SEC; - */ - - period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; - - tmrinfo("usec=%llu period=%08llx\n", usec, period); - DEBUGASSERT(period > 0 && period <= UINT32_MAX); - - /* Set up to receive the callback when the interrupt occurs */ - - STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); - - /* Set timer period */ - - oneshot->period = (uint32_t)period; - STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); - - /* Start the counter */ - - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); - - /* Enable interrupts. We should get the callback when the interrupt - * occurs. - */ - - oneshot->running = true; - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. ts may be zero in which case the time remaining - * is not returned. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts) -{ - irqstate_t flags; - uint64_t usec; - uint64_t sec; - uint64_t nsec; - uint32_t count; - uint32_t period; - - /* Was the timer running? */ - - flags = enter_critical_section(); - if (!oneshot->running) - { - /* No.. Just return zero timer remaining and successful cancellation. - * This function may execute at a high rate with no timer running - * (as when pre-emption is enabled and disabled). - */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - leave_critical_section(flags); - return OK; - } - - /* Yes.. Get the timer counter and period registers and stop the counter. - * If the counter expires while we are doing this, the counter clock will - * be stopped, but the clock will not be disabled. - * - * The expected behavior is that the counter register will freezes at - * a value equal to the RC register when the timer expires. The counter - * should have values between 0 and RC in all other cased. - * - * REVISIT: This does not appear to be the case. - */ - - tmrinfo("Cancelling...\n"); - - count = STM32_TIM_GETCOUNTER(oneshot->tch); - period = oneshot->period; - - /* Now we can disable the interrupt and stop the timer. */ - - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - leave_critical_section(flags); - - /* Did the caller provide us with a location to return the time - * remaining? - */ - - if (ts) - { - /* Yes.. then calculate and return the time remaining on the - * oneshot timer. - */ - - tmrinfo("period=%lu count=%lu\n", - (unsigned long)period, (unsigned long)count); - - /* REVISIT: I am not certain why the timer counter value sometimes - * exceeds RC. Might be a bug, or perhaps the counter does not stop - * in all cases. - */ - - if (count >= period) - { - /* No time remaining (?) */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - } - else - { - /* The total time remaining is the difference. Convert that - * to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / - oneshot->frequency; - - /* Return the time remaining in the correct form */ - - sec = usec / USEC_PER_SEC; - nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - ts->tv_sec = sec; - ts->tv_nsec = nsec; - } - - tmrinfo("remaining (%jd, %ld)\n", - (intmax_t)ts->tv_sec, ts->tv_nsec); - } - - return OK; -} - -#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h deleted file mode 100644 index 9b02e37ca1cd4..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32wb_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, - uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c deleted file mode 100644 index d98270362c4b7..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c +++ /dev/null @@ -1,309 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32wb_oneshot.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of the oneshot timer lower-half - * driver - */ - -struct stm32_oneshot_lowerhalf_s -{ - /* This is the part of the lower half driver that is visible to the upper- - * half client of the driver. This must be the first thing in this - * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. - */ - - struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ - - /* Private lower half data follows */ - - struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg); - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts); -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Lower half operations */ - -static const struct oneshot_operations_s g_oneshot_ops = -{ - .max_delay = stm32_max_delay, - .start = stm32_start, - .cancel = stm32_cancel, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Timer expiration handler - * - * Input Parameters: - * arg - Should be the same argument provided when stm32_oneshot_start() - * was called. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Perhaps the callback was nullified in a race condition with - * stm32_cancel? - */ - - oneshot_process_callback(&priv->lh); -} - -/**************************************************************************** - * Name: stm32_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the maximum delay. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - uint64_t usecs; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); - if (ret >= 0) - { - uint64_t sec = usecs / 1000000; - usecs -= 1000000 * sec; - - ts->tv_sec = sec; - ts->tv_nsec = usecs * 1000; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - - /* Save the callback information and start the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_start(&priv->oneshot, - stm32_oneshot_handler, priv, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * lower Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL); - - /* Cancel the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_cancel(&priv->oneshot, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: oneshot_initialize - * - * Description: - * Initialize the oneshot timer and return a oneshot lower half driver - * instance. - * - * Input Parameters: - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * On success, a non-NULL instance of the oneshot lower-half driver is - * returned. NULL is return on any failure. - * - ****************************************************************************/ - -struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) -{ - struct stm32_oneshot_lowerhalf_s *priv; - int ret; - - /* Allocate an instance of the lower half driver */ - - priv = (struct stm32_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); - - if (priv == NULL) - { - tmrerr("ERROR: Failed to initialized state structure\n"); - return NULL; - } - - /* Initialize the lower-half driver structure */ - - priv->lh.ops = &g_oneshot_ops; - - /* Initialize the contained STM32 oneshot timer */ - - ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); - kmm_free(priv); - return NULL; - } - - return &priv->lh; -} diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index d7dd502e49beb..389454e8058a4 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -789,7 +789,7 @@ static void stm32_stdclockconfig(void) #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32_rcc_enable_lsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index 438138e0de7ce..b14844a88b242 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -31,7 +31,7 @@ #include "arm_internal.h" #include "chip.h" -#include "hardware/stm32wb_rcc.h" +#include "hardware/stm32_rcc.h" /**************************************************************************** * Pre-processor Definitions @@ -190,24 +190,24 @@ void stm32_clockenable(void); void stm32_rcc_enable_lse(void); /**************************************************************************** - * Name: stm32_rcc_enable_lsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32_rcc_enable_lsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32_rcc_disable_lsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32_rcc_disable_lsi(void); +void stm32_rcc_disablelsi(void); /**************************************************************************** * Name: stm32_rcc_enable_hsi48 diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c deleted file mode 100644 index 7dcdc39a50b48..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_rcc_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32wb_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enable_lsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enable_lsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSI1ON); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disable_lsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disable_lsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSI1ON, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c deleted file mode 100644 index 561a0a45a4aae..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ /dev/null @@ -1,1289 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32wb_tim.h" -#include "stm32wb_gpio.h" -#include "stm32wb_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. - * Such special purposes include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32WB_TIMn is defined then the CONFIG_STM32WB_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32WB_TIMn is - * defined then CONFIG_STM32WB_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32WB_TIMn is defined then - * CONFIG_STM32WB_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32WB_TIM16_ADC) || \ - defined(CONFIG_STM32WB_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32WB_TIM17_ADC) || \ - defined(CONFIG_STM32WB_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ - defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ - defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) || defined(GPIO_TIM16_CH2OUT) || \ - defined(GPIO_TIM16_CH3OUT) || defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) || defined(GPIO_TIM17_CH2OUT) || \ - defined(GPIO_TIM17_CH3OUT) || defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif -static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setfreq = stm32_tim_setfreq, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .getwidth = stm32_tim_getwidth, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, - .dump_regs = stm32_tim_dumpregs, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the STM32WB - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2. - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the STM32WB - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2. - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_TIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_TIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); - - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_dumpregs - ****************************************************************************/ - -static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) -{ - struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; - - ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32_getreg16(dev, STM32_TIM_CR1_OFFSET), - stm32_getreg16(dev, STM32_TIM_CR2_OFFSET), - stm32_getreg16(dev, STM32_TIM_SMCR_OFFSET), - stm32_getreg16(dev, STM32_TIM_DIER_OFFSET) - ); - ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32_getreg16(dev, STM32_TIM_SR_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCMR1_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCMR2_OFFSET) - ); - ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32_getreg16(dev, STM32_TIM_CCER_OFFSET), - stm32_getreg16(dev, STM32_TIM_CNT_OFFSET), - stm32_getreg16(dev, STM32_TIM_PSC_OFFSET), - stm32_getreg16(dev, STM32_TIM_ARR_OFFSET) - ); - ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32_getreg16(dev, STM32_TIM_CCR1_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCR2_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCR3_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCR4_OFFSET) - ); - - if (priv->base == STM32_TIM1_BASE) - { - ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(dev, STM32_TIM_RCR_OFFSET), - stm32_getreg16(dev, STM32_TIM_BDTR_OFFSET), - stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); - } - else - { - ainfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); - } -} - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val; - - DEBUGASSERT(dev != NULL); - - /* The modes DOWN and UPDOWN are not supported on TIM16 and TIM17. */ - -#if defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) - { -#if defined(CONFIG_STM32_TIM16) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM16_BASE) - { - return -EINVAL; - } -#endif - -#if defined(CONFIG_STM32_TIM17) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM17_BASE) - { - return -EINVAL; - } -#endif - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_UP: - val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - break; - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) - case STM32_TIM_MODE_DOWN: - val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_DIR; - break; - - case STM32_TIM_MODE_UPDOWN: - val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_CMS_CNTR1; - - /* Our default: - * Interrupts are generated on compare, when counting down - */ - - break; -#endif - - case STM32_TIM_MODE_PULSE: - val = GTIM_CR1_CEN | GTIM_CR1_ARPE | GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); - -#ifdef CONFIG_STM32_TIM1 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE) - { - stm32_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setfreq - ****************************************************************************/ - -static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - uint32_t reload; - uint32_t timclk; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - * - * Calculate optimal values for the timer prescaler and for the timer - * reload register. If freq is the desired frequency, then - * - * reload = timclk / freq - * reload = (pclck / prescaler) / freq - * - * There are many solutions to do this, but the best solution will be the - * one that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= prescaler <= 65536 - * 1 <= reload <= 65535 - * - * So ( prescaler = pclck / 65535 / freq ) would be optimal. - */ - - prescaler = (freqin / freq + 65534) / 65535; - - /* We need to decrement value for '1', but only if that will not to - * cause underflow. - */ - - if (prescaler < 1) - { - awarn("WARNING: Prescaler underflowed.\n"); - prescaler = 1; - } - - /* Check for overflow as well. */ - - if (prescaler > 65536) - { - awarn("WARNING: Prescaler overflowed.\n"); - prescaler = 65536; - } - - timclk = freqin / prescaler; - - reload = timclk / freq; - if (reload < 1) - { - awarn("WARNING: Reload value underflowed.\n"); - reload = 1; - } - else if (reload > 65535) - { - awarn("WARNING: Reload value overflowed.\n"); - reload = 65535; - } - - /* Set the reload and prescaler values */ - - stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); - stm32_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); - - return (timclk / reload); -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_TIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_TIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_TIM_CNT_OFFSET); - - /* TIM2 is a 32-bit timer. */ - -#if defined(CONFIG_STM32_TIM2) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) - { - return counter; - } -#endif - - return counter & 0x0000ffff; -} - -/**************************************************************************** - * Name: stm32_tim_getwidth - ****************************************************************************/ - -static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - /* Only TIM2 is a 32-bit timer. */ - -#if defined(CONFIG_STM32_TIM2) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) - { - return 32; - } -#endif - - /* All others are 16-bit timers. */ - - return 16; -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 3) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_TIM_CCER_OFFSET); - ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = GTIM_CCMR_OCXM_PWM1(channel) | GTIM_CCMR_OCXPE(channel); - ccer_val |= GTIM_CCER_CCXE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CCXP(channel); - } - - if (channel > 1) - { - ccmr_offset = STM32_TIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_TIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_TIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_TIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_TIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_TIM_SR_OFFSET); - return (regval & source) ? 1 : 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim.h b/arch/arm/src/stm32wb/stm32wb_tim.h deleted file mode 100644 index a7ea2c7345189..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_tim.h +++ /dev/null @@ -1,254 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_TIM_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32wb_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Generalized register definitions */ - -#define GTIM_CR1_CEN TIM1_CR1_CEN -#define GTIM_CR1_OPM TIM1_CR1_OPM -#define GTIM_CR1_ARPE TIM1_CR1_ARPE -#define GTIM_DIER_UIE TIM1_DIER_UIE -#define GTIM_SR_UIF TIM1_SR_UIF -#define GTIM_EGR_UG TIM1_EGR_UG -#define TIM_1_2_CR1_DIR TIM1_CR1_DIR -#define TIM_1_2_CR1_CMS_CNTR1 TIM1_CR1_CMS_CNTR1 - -#define GTIM_CCER_CCX_SHIFT(ch) ((ch) << 2) /* 4-bits shift - * per channel */ -#define GTIM_CCMR_OCX_SHIFT(ch) (((ch) & 0x1) << 3) /* 8-bits shift - * per channel */ - -#define GTIM_CCER_CCXE(ch) (TIM1_CCER_CC1E << GTIM_CCER_CCX_SHIFT(ch)) -#define GTIM_CCER_CCXP(ch) (TIM1_CCER_CC1P << GTIM_CCER_CCX_SHIFT(ch)) -#define GTIM_CCMR_OCXPE(ch) (TIM1_CCMR1_OC1PE << GTIM_CCMR_OCX_SHIFT(ch)) -#define GTIM_CCMR_OCXM_MASK(ch) (TIM1_CCMR1_OC1M_MASK << \ - GTIM_CCMR_OCX_SHIFT(ch)) -#define GTIM_CCMR_OCXM_FRZN(ch) (TIM1_CCMR1_OC1M_FRZN << \ - GTIM_CCMR_OCX_SHIFT(ch)) -#define GTIM_CCMR_OCXM_PWM1(ch) (TIM1_CCMR1_OC1M_PWM1 << \ - GTIM_CCMR_OCX_SHIFT(ch)) - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active - * high when counter < compare - */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - -#if 0 - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC /* Open collector mode */ -#endif -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - uint32_t (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - uint32_t (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); - - /* Debug */ - - void (*dump_regs)(struct stm32_tim_dev_s *dev); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_TIM_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c deleted file mode 100644 index 38e8db5b4aabb..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ /dev/null @@ -1,488 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32wb_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *)arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = clock / 1000000; - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32wl5/CMakeLists.txt b/arch/arm/src/stm32wl5/CMakeLists.txt index b13a427ce34d6..2fc5af18c597d 100644 --- a/arch/arm/src/stm32wl5/CMakeLists.txt +++ b/arch/arm/src/stm32wl5/CMakeLists.txt @@ -32,10 +32,8 @@ set(SRCS stm32wl5_serial.c stm32wl5_start.c stm32wl5_lse.c - stm32wl5_lsi.c stm32wl5_idle.c stm32wl5_pwr.c - stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c stm32wl5_spi.c) diff --git a/arch/arm/src/stm32wl5/Make.defs b/arch/arm/src/stm32wl5/Make.defs index d61921e8c127b..d38f6c0ae48ab 100644 --- a/arch/arm/src/stm32wl5/Make.defs +++ b/arch/arm/src/stm32wl5/Make.defs @@ -33,8 +33,8 @@ include common/stm32/Make.defs CHIP_CSRCS += stm32wl5_allocateheap.c stm32wl5_exti_gpio.c stm32wl5_gpio.c CHIP_CSRCS += stm32wl5_irq.c stm32wl5_lowputc.c stm32wl5_rcc.c CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c -CHIP_CSRCS += stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c -CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c +CHIP_CSRCS += stm32wl5_lse.c stm32wl5_idle.c +CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_flash.c stm32wl5_timerisr.c CHIP_CSRCS += stm32wl5_spi.c CSRCS-$(CONFIG_STM32_IPCC) = stm32wl5_ipcc.c diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h rename to arch/arm/src/stm32wl5/hardware/stm32_rcc.h index 987fed3348f18..48a23d43d4e70 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h + * arch/arm/src/stm32wl5/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32wl5/stm32.h b/arch/arm/src/stm32wl5/stm32.h index 9cb9b9bbf3f1d..67835af8e0445 100644 --- a/arch/arm/src/stm32wl5/stm32.h +++ b/arch/arm/src/stm32wl5/stm32.h @@ -43,7 +43,6 @@ #include "stm32wl5_pwr.h" #include "stm32wl5_rcc.h" #include "stm32wl5_spi.h" -#include "stm32wl5_tim.h" #include "stm32wl5_uart.h" /**************************************************************************** diff --git a/arch/arm/src/stm32wl5/stm32wl5_lsi.c b/arch/arm/src/stm32wl5/stm32wl5_lsi.c deleted file mode 100644 index 12ce587823d89..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32wl5_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/stm32wl5_rcc.h index eea97c6d2402a..a3a7f30e79a18 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#include "hardware/stm32wl5_rcc.h" +#include "hardware/stm32_rcc.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.c b/arch/arm/src/stm32wl5/stm32wl5_tim.c deleted file mode 100644 index 3f3c958a1c53d..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.c +++ /dev/null @@ -1,1697 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" - -#include "stm32.h" -#include "stm32wl5_gpio.h" -#include "stm32wl5_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32WL5_TIMn is defined then the CONFIG_STM32WL5_TIMn_PWM may - * also be defined to indicate that the timer is intended to be used for - * pulsed output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32WL5_TIMn is - * defined then CONFIG_STM32WL5_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32WL5_TIMn is defined - * then CONFIG_STM32WL5_TIMn_DAC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32WL5_TIMn is defined then - * CONFIG_STM32WL5_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32WL5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32WL5_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32WL5_TIM7_PWM) || defined (CONFIG_STM32WL5_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32WL5_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32WL5_TIM15_DAC) || defined(CONFIG_STM32WL5_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32WL5_TIM16_ADC) || \ - defined(CONFIG_STM32WL5_TIM16_DAC) || defined(CONFIG_STM32WL5_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32WL5_TIM17_ADC) || \ - defined(CONFIG_STM32WL5_TIM17_DAC) || defined(CONFIG_STM32WL5_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ - defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ - defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ - defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the - * STM32WL5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the - * STM32WL5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, - 0, ATIM_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_TIM1_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_TIM2_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_TIM3_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_TIM7_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_TIM8_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_TIM15_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_TIM16_CLKIN; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); - - /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. - * reset it it result when not TIM2 or TIM5. - */ - -#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: -#endif - return counter; - - default: - return counter & 0x0000ffff; - } -#else - return counter & 0x0000ffff; -#endif -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -#if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -#if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -#if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -#if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -#if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & GTIM_SR_UIF) ? 1 : 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.h b/arch/arm/src/stm32wl5/stm32wl5_tim.h deleted file mode 100644 index 10f16b1695eb8..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.h +++ /dev/null @@ -1,214 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_TIM_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32wl5_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_TIM_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c deleted file mode 100644 index 233008d82f047..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c +++ /dev/null @@ -1,607 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32wl5_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = - (struct stm32_lowerhalf_s *)arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, 0); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = (clock == 1000000)? 1: (clock / 1000000); - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c index a43d7b85e278f..da5649eee2dae 100644 --- a/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c @@ -41,6 +41,7 @@ #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "hymini-stm32v.h" #include /* Should always be included last due to dependencies */ diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c index 679d23535de72..169cd28555019 100644 --- a/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c @@ -42,6 +42,7 @@ #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "hymini-stm32v.h" #include /* Should always be included last due to dependencies */ diff --git a/boards/arm/stm32f1/maple/src/stm32_lcd.c b/boards/arm/stm32f1/maple/src/stm32_lcd.c index 58f5831a33fe8..c744dbd936f79 100644 --- a/boards/arm/stm32f1/maple/src/stm32_lcd.c +++ b/boards/arm/stm32f1/maple/src/stm32_lcd.c @@ -43,6 +43,7 @@ #include "chip.h" #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "maple.h" /**************************************************************************** diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c index f0b29a830d7b0..e384b346e7df0 100644 --- a/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c @@ -64,6 +64,7 @@ #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "stm3210e-eval.h" /**************************************************************************** diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt index 20cf639591054..98249b1b9fcb3 100644 --- a/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt +++ b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt @@ -22,10 +22,6 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs index c704b2c356464..b65b48862a135 100644 --- a/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs +++ b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs @@ -24,10 +24,6 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_BOARDCTL_RESET),y) - CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c deleted file mode 100644 index 886ca544518ed..0000000000000 --- a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ -#ifdef CONFIG_STM32_DFU - /* TODO handle reboot to bootloader */ - -#endif - - up_systemreset(); - return 0; -} diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c index 4d80b05f9d86f..7231e2c83f6df 100644 --- a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c @@ -43,6 +43,7 @@ #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "viewtool_stm32f107.h" #ifdef CONFIG_LCD_SSD1289 diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt index 1f6f30ca92b66..3977def05e600 100644 --- a/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt @@ -60,14 +60,6 @@ if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs index 22ef4de2cdd6e..b5de1a7ff7ee6 100644 --- a/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs @@ -62,14 +62,6 @@ ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c deleted file mode 100644 index c17caaa874e35..0000000000000 --- a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c deleted file mode 100644 index 8eaaf58c73dc1..0000000000000 --- a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file provides contents of an optional ROMFS volume, mounted at boot */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/nucleo-f446re/Kconfig b/boards/arm/stm32f4/nucleo-f446re/Kconfig index 1e2e8b8e8b756..1007c8b531564 100644 --- a/boards/arm/stm32f4/nucleo-f446re/Kconfig +++ b/boards/arm/stm32f4/nucleo-f446re/Kconfig @@ -30,26 +30,4 @@ config NUCLEO_F446RE_AJOY_MINBUTTONS minimal set: SELECT (joystick down), FIRE (BUTTON B), and JUMP (BUTTON A). -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../rom.img" - endif # ARCH_BOARD_NUCLEO_F446RE diff --git a/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt index 25458b16ff5ca..610cad1a6c0d2 100644 --- a/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt @@ -70,10 +70,6 @@ if(CONFIG_BOARD_STM32_IHM08M1) list(APPEND SRCS stm32_foc_ihm08m1.c) endif() -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f446re.ld") diff --git a/boards/arm/stm32f4/nucleo-f446re/src/Make.defs b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs index f861a66574e08..f4f9c4ec5ce29 100644 --- a/boards/arm/stm32f4/nucleo-f446re/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs @@ -72,10 +72,6 @@ ifeq ($(CONFIG_BOARD_STM32_IHM08M1),y) CSRCS += stm32_foc_ihm08m1.c endif -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c index 94dd44f58397a..13cf8656c7ca4 100644 --- a/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c @@ -64,7 +64,9 @@ # include #endif -#include "stm32_romfs.h" +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif #include "nucleo-f446re.h" /**************************************************************************** diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h deleted file mode 100644 index fa4e75ddadddf..0000000000000 --- a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_begin) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c deleted file mode 100644 index f1fe6d0806254..0000000000000 --- a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file provides contents of an optional ROMFS volume, mounted at boot */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [&romfs_data_begin .. &romfs_data_begin) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - uintptr_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = (uintptr_t)romfs_data_end - (uintptr_t)romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/omnibusf4/Kconfig b/boards/arm/stm32f4/omnibusf4/Kconfig index ba690b483338e..bb0e7ff53b936 100644 --- a/boards/arm/stm32f4/omnibusf4/Kconfig +++ b/boards/arm/stm32f4/omnibusf4/Kconfig @@ -5,26 +5,4 @@ if ARCH_BOARD_OMNIBUSF4 -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../rom.img" - endif diff --git a/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt index 531c7feb5d6f6..e7c271fa8e38b 100644 --- a/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt +++ b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt @@ -62,10 +62,6 @@ if(CONFIG_TIMER) list(APPEND SRCS stm32_timer.c) endif() -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - if(CONFIG_BOARDCTL_UNIQUEID) list(APPEND SRCS stm32_uid.c) endif() diff --git a/boards/arm/stm32f4/omnibusf4/src/Make.defs b/boards/arm/stm32f4/omnibusf4/src/Make.defs index b0c74f55cdee9..8cea316c75d79 100644 --- a/boards/arm/stm32f4/omnibusf4/src/Make.defs +++ b/boards/arm/stm32f4/omnibusf4/src/Make.defs @@ -63,10 +63,6 @@ ifeq ($(CONFIG_TIMER),y) CSRCS += stm32_timer.c endif -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) CSRCS += stm32_uid.c endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c index 59aa712f47fda..a8d3e5d7a4a8e 100644 --- a/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c @@ -38,7 +38,9 @@ #endif #include "stm32.h" -#include "stm32_romfs.h" +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif #ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h deleted file mode 100644 index b1376c031e76b..0000000000000 --- a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c deleted file mode 100644 index 8c5d8069a9522..0000000000000 --- a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - ".section .rodata, \"a\"\n" - ".balign 16\n" - ".globl romfs_data_begin\n" -"romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ - \ - ".balign " STR(ROMFS_SECTOR_SIZE) "\n" - ".globl romfs_data_end\n" -"romfs_data_end:\n"); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig index 303875d809fa1..b29a0ff745914 100644 --- a/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig @@ -11,6 +11,7 @@ # CONFIG_SYSTEM_TELNETD is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt index 64b46b4813d14..968d1e9dd9244 100644 --- a/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt @@ -30,10 +30,6 @@ if(CONFIG_USERLED) list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs index 04f89e99e4f6d..cc672de33d24d 100644 --- a/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs @@ -41,10 +41,6 @@ ifeq ($(CONFIG_USERLED),y) CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c deleted file mode 100644 index 5e24309298006..0000000000000 --- a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/stm32f4discovery/Kconfig b/boards/arm/stm32f4/stm32f4discovery/Kconfig index 084ab04bc12b9..8dfe3c0fc7940 100644 --- a/boards/arm/stm32f4/stm32f4discovery/Kconfig +++ b/boards/arm/stm32f4/stm32f4discovery/Kconfig @@ -12,28 +12,6 @@ config STM32F4DISBB Select if you are using the STM32F4DIS-BB base board with the STM32F4Discovery. -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../../../rom.img" - config STM32F4DISCO_USBHOST_STACKSIZE int "USB host waiter stack size" default 1024 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig index 493408723d332..3edc516822576 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig @@ -13,6 +13,7 @@ CONFIG_ADBD_SHELL_SERVICE=y CONFIG_ADBD_USB_SERVER=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig index 51f162f19cf6e..6125b59ae1516 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig @@ -12,6 +12,7 @@ CONFIG_ALLOW_BSD_COMPONENTS=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig index 905b47c6c4eca..91350175be5b3 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig @@ -14,6 +14,7 @@ # CONFIG_STM32_CCMEXCLUDE is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig index e18237614b4f4..e7e4cc4c09599 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig @@ -12,6 +12,7 @@ # CONFIG_NSH_CMDOPT_HEXDUMP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig index dafce58d6125d..f57a05ca6c5bc 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig @@ -11,6 +11,7 @@ CONFIG_ALLOW_BSD_COMPONENTS=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig index 673265e3c7724..73a18bd96ac3f 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig @@ -13,6 +13,7 @@ # CONFIG_SPI_CALLBACK is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt index f65fa366811b4..36cebfbb8cf77 100644 --- a/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt @@ -92,10 +92,6 @@ if(CONFIG_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_CUSTOM_PMINIT) list(APPEND SRCS stm32_pm.c) endif() @@ -138,10 +134,6 @@ if(CONFIG_STM32_HCIUART) endif() endif() -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - if(CONFIG_BOARDCTL_UNIQUEID) list(APPEND SRCS stm32_uid.c) endif() diff --git a/boards/arm/stm32f4/stm32f4discovery/src/Make.defs b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs index bb7e1b041232a..78fe9c2a0afc2 100644 --- a/boards/arm/stm32f4/stm32f4discovery/src/Make.defs +++ b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs @@ -98,10 +98,6 @@ ifeq ($(CONFIG_CAPTURE),y) CSRCS += stm32_capture.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) CSRCS += stm32_pm.c endif @@ -148,10 +144,6 @@ CSRCS += stm32_hciuart.c endif endif -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) CSRCS += stm32_uid.c endif diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c index a9ea083a7065c..16d4cbc15f25d 100644 --- a/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c @@ -39,7 +39,9 @@ #endif #include "stm32.h" -#include "stm32_romfs.h" +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif #ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c deleted file mode 100644 index 8381b158e684b..0000000000000 --- a/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h deleted file mode 100644 index 7cfb268ae3d6d..0000000000000 --- a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c deleted file mode 100644 index 2814a9eb8e1bd..0000000000000 --- a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c - * This file provides contents of an optional ROMFS volume, mounted at boot. - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - ".section .rodata, \"a\"\n" - ".balign 16\n" - ".globl romfs_data_begin\n" -"romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ - \ - ".balign " STR(ROMFS_SECTOR_SIZE) "\n" - ".globl romfs_data_end\n" -"romfs_data_end:\n"); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c index ecfabfc0424d3..8fec793b89ee1 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c @@ -29,7 +29,7 @@ #include -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "b-l475e-iot01a.h" /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index c1842f4e555f5..97b530c714264 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -44,7 +44,7 @@ #include "ram_vectors.h" #include "stm32l4_pwm.h" -#include "stm32l4_tim.h" +#include "stm32_tim.h" #ifdef CONFIG_NUCLEOL432KC_SPWM diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c index 8d7ac77627f2f..50a21574bffed 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c @@ -29,7 +29,7 @@ #include -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "nucleo-l432kc.h" #ifdef CONFIG_TIMER diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c index 7ae7885ca8bfe..a29fd9da67f92 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c @@ -29,7 +29,7 @@ #include -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "nucleo-l476rg.h" #ifdef CONFIG_TIMER diff --git a/boards/arm/stm32wb/common/Makefile b/boards/arm/stm32wb/common/Makefile index 37068a4128551..8480f786704c3 100644 --- a/boards/arm/stm32wb/common/Makefile +++ b/boards/arm/stm32wb/common/Makefile @@ -23,6 +23,7 @@ include $(TOPDIR)/Make.defs STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 include board/Make.defs include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs @@ -34,3 +35,4 @@ include $(TOPDIR)/boards/Board.mk ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src BOARDDIR = $(ARCHSRCDIR)$(DELIM)board CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c index 2f549b32aac0a..aa5f77a85a7a5 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c @@ -40,7 +40,7 @@ #include -#include "stm32wb_tim.h" +#include "stm32_tim.h" #ifdef CONFIG_RTC_DRIVER # include diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c index ff849aff0dbc2..6420d71a69874 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c @@ -40,7 +40,7 @@ #include -#include "stm32wb_tim.h" +#include "stm32_tim.h" #ifdef CONFIG_RTC_DRIVER # include