From 3e5314c08e99a412384656ba7698077940ae4c7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mahmut=20Sami=20=C3=96ZMEN?= Date: Wed, 22 Jul 2026 13:17:41 +0300 Subject: [PATCH] arm/rm57: Add support for TI Hercules RM57 and LaunchXL2 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial NuttX support for the TI Hercules RM57Lx (Cortex-R5F) microcontroller family and the LAUNCHXL2-RM57L843 development board. * Add arch/arm/src/rm57 chip layer: boot/startup code, clock configuration, GIO, VIM interrupt controller, ESM, RTI, SCI serial driver, MPU initialization, and timer ISR support. * Add board support for rm57l843-launchxl2, including board bring-up, LED handling, linker scripts, and an nsh defconfig. * Add Documentation pages describing the RM57 architecture and the LaunchXL2 board. Assisted-by: Claude:claude-fable-5 Signed-off-by: Mahmut Sami ÖZMEN --- .../rm57/boards/rm57l843-launchxl2/index.rst | 115 +++ Documentation/platforms/arm/rm57/index.rst | 46 ++ arch/arm/Kconfig | 13 + arch/arm/include/rm57/chip.h | 66 ++ arch/arm/include/rm57/irq.h | 91 +++ arch/arm/include/rm57/rm57l843_irq.h | 150 ++++ arch/arm/src/rm57/CMakeLists.txt | 38 + arch/arm/src/rm57/Kconfig | 33 + arch/arm/src/rm57/Make.defs | 40 + arch/arm/src/rm57/chip.h | 44 ++ arch/arm/src/rm57/hardware/rm57_esm.h | 140 ++++ arch/arm/src/rm57/hardware/rm57_flash.h | 80 ++ arch/arm/src/rm57/hardware/rm57_gio.h | 122 ++++ arch/arm/src/rm57/hardware/rm57_pcr.h | 134 ++++ arch/arm/src/rm57/hardware/rm57_rti.h | 139 ++++ arch/arm/src/rm57/hardware/rm57_sci.h | 230 ++++++ arch/arm/src/rm57/hardware/rm57_sys.h | 355 +++++++++ arch/arm/src/rm57/hardware/rm57_vim.h | 213 ++++++ .../src/rm57/hardware/rm57l843_memorymap.h | 87 +++ arch/arm/src/rm57/rm57_boot.c | 192 +++++ arch/arm/src/rm57/rm57_boot.h | 61 ++ arch/arm/src/rm57/rm57_clockconfig.c | 229 ++++++ arch/arm/src/rm57/rm57_clockconfig.h | 49 ++ arch/arm/src/rm57/rm57_coreinit.S | 98 +++ arch/arm/src/rm57/rm57_esm.c | 109 +++ arch/arm/src/rm57/rm57_esm.h | 48 ++ arch/arm/src/rm57/rm57_gio.c | 234 ++++++ arch/arm/src/rm57/rm57_gio.h | 199 +++++ arch/arm/src/rm57/rm57_irq.c | 296 ++++++++ arch/arm/src/rm57/rm57_irq.h | 65 ++ arch/arm/src/rm57/rm57_lowputc.c | 278 +++++++ arch/arm/src/rm57/rm57_lowputc.h | 99 +++ arch/arm/src/rm57/rm57_mpuinit.c | 77 ++ arch/arm/src/rm57/rm57_mpuinit.h | 98 +++ arch/arm/src/rm57/rm57_serial.c | 688 ++++++++++++++++++ arch/arm/src/rm57/rm57_timerisr.c | 157 ++++ boards/Kconfig | 12 + .../rm57/rm57l843-launchxl2/CMakeLists.txt | 25 + boards/arm/rm57/rm57l843-launchxl2/Kconfig | 8 + .../rm57l843-launchxl2/configs/nsh/defconfig | 36 + .../rm57/rm57l843-launchxl2/include/board.h | 128 ++++ .../rm57/rm57l843-launchxl2/scripts/Make.defs | 43 ++ .../rm57l843-launchxl2/scripts/flash-sram.ld | 121 +++ .../rm57l843-launchxl2/src/CMakeLists.txt | 31 + .../arm/rm57/rm57l843-launchxl2/src/Makefile | 33 + .../rm57l843-launchxl2/src/rm57_autoleds.c | 89 +++ .../rm57l843-launchxl2/src/rm57_bringup.c | 48 ++ .../rm57l843-launchxl2/src/rm57_initialize.c | 95 +++ .../rm57l843-launchxl2/src/rm57_userleds.c | 81 +++ .../src/rm57l843-launchxl2.h | 73 ++ 50 files changed, 5936 insertions(+) create mode 100644 Documentation/platforms/arm/rm57/boards/rm57l843-launchxl2/index.rst create mode 100644 Documentation/platforms/arm/rm57/index.rst create mode 100644 arch/arm/include/rm57/chip.h create mode 100644 arch/arm/include/rm57/irq.h create mode 100644 arch/arm/include/rm57/rm57l843_irq.h create mode 100644 arch/arm/src/rm57/CMakeLists.txt create mode 100644 arch/arm/src/rm57/Kconfig create mode 100644 arch/arm/src/rm57/Make.defs create mode 100644 arch/arm/src/rm57/chip.h create mode 100644 arch/arm/src/rm57/hardware/rm57_esm.h create mode 100644 arch/arm/src/rm57/hardware/rm57_flash.h create mode 100644 arch/arm/src/rm57/hardware/rm57_gio.h create mode 100644 arch/arm/src/rm57/hardware/rm57_pcr.h create mode 100644 arch/arm/src/rm57/hardware/rm57_rti.h create mode 100644 arch/arm/src/rm57/hardware/rm57_sci.h create mode 100644 arch/arm/src/rm57/hardware/rm57_sys.h create mode 100644 arch/arm/src/rm57/hardware/rm57_vim.h create mode 100644 arch/arm/src/rm57/hardware/rm57l843_memorymap.h create mode 100644 arch/arm/src/rm57/rm57_boot.c create mode 100644 arch/arm/src/rm57/rm57_boot.h create mode 100644 arch/arm/src/rm57/rm57_clockconfig.c create mode 100644 arch/arm/src/rm57/rm57_clockconfig.h create mode 100644 arch/arm/src/rm57/rm57_coreinit.S create mode 100644 arch/arm/src/rm57/rm57_esm.c create mode 100644 arch/arm/src/rm57/rm57_esm.h create mode 100644 arch/arm/src/rm57/rm57_gio.c create mode 100644 arch/arm/src/rm57/rm57_gio.h create mode 100644 arch/arm/src/rm57/rm57_irq.c create mode 100644 arch/arm/src/rm57/rm57_irq.h create mode 100644 arch/arm/src/rm57/rm57_lowputc.c create mode 100644 arch/arm/src/rm57/rm57_lowputc.h create mode 100644 arch/arm/src/rm57/rm57_mpuinit.c create mode 100644 arch/arm/src/rm57/rm57_mpuinit.h create mode 100644 arch/arm/src/rm57/rm57_serial.c create mode 100644 arch/arm/src/rm57/rm57_timerisr.c create mode 100644 boards/arm/rm57/rm57l843-launchxl2/CMakeLists.txt create mode 100644 boards/arm/rm57/rm57l843-launchxl2/Kconfig create mode 100644 boards/arm/rm57/rm57l843-launchxl2/configs/nsh/defconfig create mode 100644 boards/arm/rm57/rm57l843-launchxl2/include/board.h create mode 100644 boards/arm/rm57/rm57l843-launchxl2/scripts/Make.defs create mode 100644 boards/arm/rm57/rm57l843-launchxl2/scripts/flash-sram.ld create mode 100644 boards/arm/rm57/rm57l843-launchxl2/src/CMakeLists.txt create mode 100644 boards/arm/rm57/rm57l843-launchxl2/src/Makefile create mode 100644 boards/arm/rm57/rm57l843-launchxl2/src/rm57_autoleds.c create mode 100644 boards/arm/rm57/rm57l843-launchxl2/src/rm57_bringup.c create mode 100644 boards/arm/rm57/rm57l843-launchxl2/src/rm57_initialize.c create mode 100644 boards/arm/rm57/rm57l843-launchxl2/src/rm57_userleds.c create mode 100644 boards/arm/rm57/rm57l843-launchxl2/src/rm57l843-launchxl2.h diff --git a/Documentation/platforms/arm/rm57/boards/rm57l843-launchxl2/index.rst b/Documentation/platforms/arm/rm57/boards/rm57l843-launchxl2/index.rst new file mode 100644 index 0000000000000..671b50e84fb9b --- /dev/null +++ b/Documentation/platforms/arm/rm57/boards/rm57l843-launchxl2/index.rst @@ -0,0 +1,115 @@ +===================== +LAUNCHXL2-RM57L +===================== + +.. tags:: chip:rm57, arch:armv7-r, vendor:ti + +The `LAUNCHXL2-RM57L `__ is a +LaunchPad-format evaluation board from Texas Instruments built around the +Hercules RM57L843 safety microcontroller (dual Cortex-R5F cores in +lockstep). It's aimed at evaluating TI's Hercules safety MCU family rather +than any particular application. + +.. warning:: + + This board port is new and experimental. Only the serial console (SCI1) + and the two user LEDs are currently supported; pin-mux configuration, + button support, and most on-chip peripherals are not yet implemented. + Some of the values documented below (PLL/clock configuration, LED + polarity, JTAG IDCODE) were taken from TI's HALCoGen-generated reference + project or from the RM57L843 datasheet rather than confirmed against + this specific board's schematic — see the comments in + ``boards/arm/rm57/rm57l843-launchxl2/include/board.h`` for details. + +Features +======== + +* TI Hercules RM57L843 microcontroller +* Dual-core lockstep ARM Cortex-R5F, running at 150 MHz HCLK (300 MHz + PLL/GCLK) in the current clock configuration +* 4 MB of on-chip program flash, 512 KB of on-chip SRAM +* Onboard XDS110 debug probe (JTAG) +* 2 user LEDs +* Single SCI (serial) interface currently supported + +.. note:: + + Peripherals that are part of the RM57L843 chip itself (N2HET, MibSPI, + CAN, ADC, the ESM diagnostic module, PBIST/STC self-test, etc.) but are + not yet wired up by this board port are tracked on the + :doc:`RM57 chip documentation page `. + +Buttons and LEDs +================ + +LEDs +---- + +The LAUNCHXL2-RM57L has two user LEDs, labeled **B6** and **B7** on the +board silkscreen, driven by GIOB[6] and GIOB[7] respectively. + +Buttons +------- + +Button support is not yet implemented by this board port. + +Pin Mapping +=========== + +Only the pins used by the currently supported peripherals are listed. + +.. list-table:: + :widths: auto + :header-rows: 1 + + * - Pin + - Signal + - Notes + * - (n/a) + - LIN1RX / LIN1TX + - SCI1, used as the serial console + * - J2 + - GIOB[6] + - User LED B6 + * - F1 + - GIOB[7] + - User LED B7 + +.. note:: + + The RM57L843 SCI1/LIN1 pins are used at their reset-default (primary) + function, so no pin-mux configuration is required for the console. + Header/connector pin numbers for LIN1RX/LIN1TX have not been confirmed + against the LAUNCHXL2-RM57L schematic. + +Serial Console +============== + +SCI1 is used as the serial console. The default configuration is: + +* 9600 baud, 8 data bits, no parity, 2 stop bits + +The baud rate and stop bits are configurable via ``CONFIG_SCI1_BAUD`` and +``CONFIG_SCI1_2STOP``. + +Power Supply +============ + +The LAUNCHXL2-RM57L can be powered over USB through the onboard XDS110 +debug probe. Consult the +`LAUNCHXL2-RM57L user's guide `_ +for the full range of supported input voltages. + +Debugging +========= + +The board's onboard XDS110 probe exposes a JTAG interface (Hercules' +ICEpick-C JTAG router is JTAG-only; XDS110's default SWD mode is not +usable here). OpenOCD can be used with a Cortex-R5 (``cortex_r4`` driver) +target configuration that routes through the ICEpick-C, followed by GDB +to load and debug the image. + +nsh +--- + +Basic NuttShell configuration (console enabled on SCI1, at 9600 baud). diff --git a/Documentation/platforms/arm/rm57/index.rst b/Documentation/platforms/arm/rm57/index.rst new file mode 100644 index 0000000000000..2b7a9caf1f044 --- /dev/null +++ b/Documentation/platforms/arm/rm57/index.rst @@ -0,0 +1,46 @@ +================ +TI/Hercules RM57 +================ + +.. tags:: chip:rm57, arch:armv7-r + +The RM57 is part of TI's Hercules family of ARM Cortex-R5F safety +microcontrollers, aimed at applications that need lockstep execution and +built-in self-test (industrial, medical, and automotive safety systems). +NuttX currently supports the **RM57L843** part. + +.. warning:: + + Support for this chip family is new and experimental. Only the SCI + (serial) and GIO (LED) peripherals have been brought up so far; the + PLL/clock configuration values, JTAG IDCODE, and LED polarity have not + all been independently confirmed against hardware/schematics. See the + :doc:`board documentation ` for + details. + +Peripheral Support +================== + +The following list indicates RM57 peripherals currently supported in NuttX: + +============== ===== +Peripheral Notes +============== ===== +SCI Serial Communication Interface, used for the console +GIO General purpose I/O, used for LEDs +============== ===== + +.. todo:: + + Many peripherals available on the RM57L843 (N2HET, MibSPI, CAN, ADC, + the ESM diagnostic module, PBIST/STC self-test, etc.) are not yet + implemented. Contributions are welcome. + +Supported Boards +================= + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b107f0ab91d2f..e7a1ea7e3c685 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -783,6 +783,15 @@ config ARCH_CHIP_TMS570 ---help--- TI TMS570 family +config ARCH_CHIP_RM57 + bool "TI Hercules RM57" + select ARCH_HAVE_LOWVECTORS + select ARCH_HAVE_FETCHADD + select ARMV7R_MEMINIT + select ARMV7R_HAVE_DECODEFIQ + ---help--- + TI Hercules RM57 family (ARM Cortex-R5F) + config ARCH_CHIP_TIVA bool "TI Tiva" select ARCH_HAVE_MPU @@ -1360,6 +1369,7 @@ config ARCH_CHIP default "stm32wl5" if ARCH_CHIP_STM32WL5 default "str71x" if ARCH_CHIP_STR71X default "tms570" if ARCH_CHIP_TMS570 + default "rm57" if ARCH_CHIP_RM57 default "xmc4" if ARCH_CHIP_XMC4 default "mx8mp" if ARCH_CHIP_MX8MP default "cxd56xx" if ARCH_CHIP_CXD56XX @@ -1917,6 +1927,9 @@ endif if ARCH_CHIP_TMS570 source "arch/arm/src/tms570/Kconfig" endif +if ARCH_CHIP_RM57 +source "arch/arm/src/rm57/Kconfig" +endif if ARCH_CHIP_XMC4 source "arch/arm/src/xmc4/Kconfig" endif diff --git a/arch/arm/include/rm57/chip.h b/arch/arm/include/rm57/chip.h new file mode 100644 index 0000000000000..05ca85c9b147a --- /dev/null +++ b/arch/arm/include/rm57/chip.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/arm/include/rm57/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_RM57_CHIP_H +#define __ARCH_ARM_INCLUDE_RM57_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Values below are taken from TI's HALCoGen project for RM57L843 + * (HL_sys_link.ld for flash/RAM size, RM57L_Contents.dil VIM channel + * table for peripheral counts - see rm57l843_irq.h). + */ + +#if defined(CONFIG_ARCH_CHIP_RM57L843) +# undef RM57_CORTEX_R4 /* Not Cortex-R4 family */ +# undef RM57_CORTEX_R4F /* Not Cortex-R4F family */ +# undef RM57_CORTEX_R5 /* Not Cortex-R5 family */ +# define RM57_CORTEX_R5F 1 /* Cortex-R5F family */ + +/* 4MB Program FLASH (HL_sys_link.ld) */ +# define RM57_PFLASH (4096*1024) +# define RM57_SRAM (512*1024) /* 512KB SRAM (HL_sys_link.ld) */ + +/* DCAN1-4 (VIM req 16/29, 35/42, 45/55, 113/117) */ +# define RM57_NCAN 4 + +/* SCI1(LIN1)/SCI2/SCI3/SCI4 (HL_reg_sci.h) */ +# define RM57_NSCI 4 + +/* MibSPI1-5 (VIM req 12/26, 30, 37/38, 49/54, 53/56) */ +# define RM57_NMIBSPI 5 + +/* GIO Port A, Port B (HL_reg_gio.h) */ +# define RM57_NGIOPORT 2 +#else +# error Unrecognized RM57 chip +#endif + +#endif /* __ARCH_ARM_INCLUDE_RM57_CHIP_H */ diff --git a/arch/arm/include/rm57/irq.h b/arch/arm/include/rm57/irq.h new file mode 100644 index 0000000000000..d781c1e966dfe --- /dev/null +++ b/arch/arm/include/rm57/irq.h @@ -0,0 +1,91 @@ +/**************************************************************************** + * arch/arm/include/rm57/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_RM57_IRQ_H +#define __ARCH_ARM_INCLUDE_RM57_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* The VIM interrupt vector table has one phantom vector plus a set of + * real interrupt channels, per the classic Hercules VIM layout (see + * arch/arm/include/tms570/irq.h for the sibling family's equivalent). + */ + +#define RM57_VECT_PHANTOM 0 /* The first is the "phantom" interrupt */ + +/* Default channel assignments are MCU-dependent */ + +#if defined(CONFIG_ARCH_CHIP_RM57L843) +# include +#else +# error "Unrecognized Hercules RM57 chip" +#endif + +/* Total number of IRQ numbers. + * Includes all channels plus GIO second-level interrupts (if enabled). + * Excludes the phantom vector. Zero corresponds to channel 0, vector 1. + */ + +#define NR_IRQS (RM57_IRQ_NCHANNELS + RM57_NGIO_IRQS) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_RM57_IRQ_H */ diff --git a/arch/arm/include/rm57/rm57l843_irq.h b/arch/arm/include/rm57/rm57l843_irq.h new file mode 100644 index 0000000000000..aca0bc29b91b8 --- /dev/null +++ b/arch/arm/include/rm57/rm57l843_irq.h @@ -0,0 +1,150 @@ +/**************************************************************************** + * arch/arm/include/rm57/rm57l843_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +/* VIM channel -> peripheral request assignment is a fixed hardware + * property, extracted directly from TI's HALCoGen project file + * (RM57L_Contents.dil, VIM_CHANNEL__NAME entries) rather than assumed + * from TMS570 parity. The project's VIM_CHANNELx_MAPPING values confirm + * HALCoGen configured the default identity mapping (channel N carries + * request N) - if a future board re-maps channels via vimChannelMap(), + * this table describes the *request* identity, and the active *channel* + * routing must be re-derived from that call. + * + * Channel 127 has no dedicated request (always phantomInterrupt) and + * must not be used, mirroring the sibling TMS570_IRQ_NCHANNELS pattern. + */ + +#ifndef __ARCH_ARM_INCLUDE_RM57_RM57L843_IRQ_H +#define __ARCH_ARM_INCLUDE_RM57_RM57L843_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#define RM57_IRQ_NCHANNELS 127 /* The "phantom" vector is followed by 127 + * real channels; channel 127 is reserved + * (always phantomInterrupt) */ + +/* Default channel (=request) assignments, from RM57L_Contents.dil */ + +#define RM57_REQ_ESMHIGH 0 /* ESM High level interrupt (FIQ) */ +#define RM57_REQ_RTICOMPARE0 2 /* RTI compare interrupt 0 */ +#define RM57_REQ_RTICOMPARE1 3 /* RTI compare interrupt 1 */ +#define RM57_REQ_RTICOMPARE2 4 /* RTI compare interrupt 2 */ +#define RM57_REQ_RTICOMPARE3 5 /* RTI compare interrupt 3 */ +#define RM57_REQ_RTIOVERFLOW0 6 /* RTI overflow interrupt 0 */ +#define RM57_REQ_RTIOVERFLOW1 7 /* RTI overflow interrupt 1 */ +#define RM57_REQ_RTITIMEBASE 8 /* RTI timebase interrupt */ +#define RM57_REQ_GIOHIGH 9 /* GIO high level interrupt */ +#define RM57_REQ_HET1HIGH 10 /* HET1 high level interrupt */ +#define RM57_REQ_MIBSPI1HIGH 12 /* MibSPI1 high level interrupt */ +#define RM57_REQ_LIN1HIGH 13 /* LIN1/SCI1 high level interrupt */ +#define RM57_REQ_ADC1GROUP0 14 /* ADC1 group 0 interrupt */ +#define RM57_REQ_ADC1GROUP1 15 /* ADC1 group 1 interrupt */ +#define RM57_REQ_CAN1HIGH 16 /* DCAN1 high level interrupt */ +#define RM57_REQ_SPI2HIGH 17 /* SPI2 high level interrupt */ +#define RM57_REQ_CRC 19 /* CRC interrupt */ +#define RM57_REQ_ESMLOW 20 /* ESM Low level interrupt */ +#define RM57_REQ_GIOLOW 23 /* GIO low level interrupt */ +#define RM57_REQ_HET1LOW 24 /* HET1 low level interrupt */ +#define RM57_REQ_MIBSPI1LOW 26 /* MibSPI1 low level interrupt */ +#define RM57_REQ_LIN1LOW 27 /* LIN1/SCI1 low level interrupt */ +#define RM57_REQ_ADC1GROUP2 28 /* ADC1 group 2 interrupt */ +#define RM57_REQ_CAN1LOW 29 /* DCAN1 low level interrupt */ +#define RM57_REQ_MIBSPI2LOW 30 /* MibSPI2 low level interrupt */ +#define RM57_REQ_DMAFTCA 33 /* DMA FTCA interrupt */ +#define RM57_REQ_DMALFSA 34 /* DMA LFSA interrupt */ +#define RM57_REQ_CAN2HIGH 35 /* DCAN2 high level interrupt */ +#define RM57_REQ_MIBSPI3HIGH 37 /* MibSPI3 high level interrupt */ +#define RM57_REQ_MIBSPI3LOW 38 /* MibSPI3 low level interrupt */ +#define RM57_REQ_DMAHBCA 39 /* DMA HBCA interrupt */ +#define RM57_REQ_DMABTCA 40 /* DMA BTCA interrupt */ +#define RM57_REQ_CAN2LOW 42 /* DCAN2 low level interrupt */ +#define RM57_REQ_CAN3HIGH 45 /* DCAN3 high level interrupt */ +#define RM57_REQ_MIBSPI4HIGH 49 /* MibSPI4 high level interrupt */ +#define RM57_REQ_ADC2GROUP0 50 /* ADC2 group 0 interrupt */ +#define RM57_REQ_ADC2GROUP1 51 /* ADC2 group 1 interrupt */ +#define RM57_REQ_MIBSPI5HIGH 53 /* MibSPI5 high level interrupt */ +#define RM57_REQ_MIBSPI4LOW 54 /* MibSPI4 low level interrupt */ +#define RM57_REQ_CAN3LOW 55 /* DCAN3 low level interrupt */ +#define RM57_REQ_MIBSPI5LOW 56 /* MibSPI5 low level interrupt */ +#define RM57_REQ_ADC2GROUP2 57 /* ADC2 group 2 interrupt */ +#define RM57_REQ_HET2HIGH 63 /* HET2 high level interrupt */ +#define RM57_REQ_SCI3HIGH 64 /* SCI3 high level interrupt */ +#define RM57_REQ_I2C 66 /* I2C interrupt */ +#define RM57_REQ_HET2LOW 73 /* HET2 low level interrupt */ +#define RM57_REQ_SCILOW 74 /* SCI2 (LIN-less) low level + * interrupt */ +#define RM57_REQ_EMACTX 77 /* EMAC Tx interrupt */ +#define RM57_REQ_EMACRX 79 /* EMAC Rx interrupt */ +#define RM57_REQ_DCC1DONE 82 /* DCC1 done interrupt */ +#define RM57_REQ_DCC2DONE 83 /* DCC2 done interrupt */ +#define RM57_REQ_ETPWM1 90 /* ETPWM1 interrupt */ +#define RM57_REQ_ETPWM1TZ 91 /* ETPWM1 trip-zone interrupt */ +#define RM57_REQ_ETPWM2 92 /* ETPWM2 interrupt */ +#define RM57_REQ_ETPWM2TZ 93 /* ETPWM2 trip-zone interrupt */ +#define RM57_REQ_ETPWM3 94 /* ETPWM3 interrupt */ +#define RM57_REQ_ETPWM3TZ 95 /* ETPWM3 trip-zone interrupt */ +#define RM57_REQ_ETPWM4 96 /* ETPWM4 interrupt */ +#define RM57_REQ_ETPWM4TZ 97 /* ETPWM4 trip-zone interrupt */ +#define RM57_REQ_ETPWM5 98 /* ETPWM5 interrupt */ +#define RM57_REQ_ETPWM5TZ 99 /* ETPWM5 trip-zone interrupt */ +#define RM57_REQ_ETPWM6 100 /* ETPWM6 interrupt */ +#define RM57_REQ_ETPWM6TZ 101 /* ETPWM6 trip-zone interrupt */ +#define RM57_REQ_ETPWM7 102 /* ETPWM7 interrupt */ +#define RM57_REQ_ETPWM7TZ 103 /* ETPWM7 trip-zone interrupt */ +#define RM57_REQ_ECAP1 104 /* ECAP1 interrupt */ +#define RM57_REQ_ECAP2 105 /* ECAP2 interrupt */ +#define RM57_REQ_ECAP3 106 /* ECAP3 interrupt */ +#define RM57_REQ_ECAP4 107 /* ECAP4 interrupt */ +#define RM57_REQ_ECAP5 108 /* ECAP5 interrupt */ +#define RM57_REQ_ECAP6 109 /* ECAP6 interrupt */ +#define RM57_REQ_EQEP1 110 /* EQEP1 interrupt */ +#define RM57_REQ_EQEP2 111 /* EQEP2 interrupt */ +#define RM57_REQ_CAN4HIGH 113 /* DCAN4 high level interrupt */ +#define RM57_REQ_I2C2 114 /* I2C2 interrupt */ +#define RM57_REQ_LIN2HIGH 115 /* LIN2 high level interrupt */ +#define RM57_REQ_SCI4HIGH 116 /* SCI4 high level interrupt */ +#define RM57_REQ_CAN4LOW 117 /* DCAN4 low level interrupt */ +#define RM57_REQ_LIN2LOW 118 /* LIN2 low level interrupt */ +#define RM57_REQ_SCI4LOW 119 /* SCI4 low level interrupt */ +#define RM57_REQ_CRC2 121 /* CRC2 interrupt */ +#define RM57_REQ_EPCFULL 124 /* EPC FIFO full interrupt */ + +/* Second-level GIO pin interrupt demux is not yet implemented for RM57 - + * no extra IRQ numbers are allocated for it here, matching TMS570's + * "#else ... 0" case. + */ + +#define RM57_NGIO_IRQS 0 + +#endif /* __ARCH_ARM_INCLUDE_RM57_RM57L843_IRQ_H */ diff --git a/arch/arm/src/rm57/CMakeLists.txt b/arch/arm/src/rm57/CMakeLists.txt new file mode 100644 index 0000000000000..287c02dc8fa99 --- /dev/null +++ b/arch/arm/src/rm57/CMakeLists.txt @@ -0,0 +1,38 @@ +# ############################################################################## +# arch/arm/src/rm57/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS + rm57_boot.c + rm57_clockconfig.c + rm57_mpuinit.c + rm57_gio.c + rm57_irq.c + rm57_lowputc.c + rm57_serial.c + rm57_esm.c + rm57_coreinit.S) + +if(NOT CONFIG_SCHED_TICKLESS) + list(APPEND SRCS rm57_timerisr.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/rm57/Kconfig b/arch/arm/src/rm57/Kconfig new file mode 100644 index 0000000000000..ac031bdf9e532 --- /dev/null +++ b/arch/arm/src/rm57/Kconfig @@ -0,0 +1,33 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_RM57 + +comment "RM57 Configuration Options" + +# Chip Selection + +choice + prompt "TI Hercules RM57 Chip Selection" + default ARCH_CHIP_RM57L843 + +config ARCH_CHIP_RM57L843 + bool "TI RM57L843" + select ARCH_CORTEXR5 + select ARCH_HAVE_FPU + +endchoice # TI Hercules RM57 Chip Selection + +menu "RM57 Peripheral Support" + +config RM57_SCI1 + bool "Serial Communication Interface 1 (SCI1)" + default n + select SCI1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +endmenu # RM57 Peripheral Support + +endif # ARCH_CHIP_RM57 diff --git a/arch/arm/src/rm57/Make.defs b/arch/arm/src/rm57/Make.defs new file mode 100644 index 0000000000000..cc9c8d59d78e4 --- /dev/null +++ b/arch/arm/src/rm57/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# arch/arm/src/rm57/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-r/Make.defs + +# RM57-specific C source files + +CHIP_CSRCS = rm57_boot.c rm57_clockconfig.c rm57_mpuinit.c rm57_gio.c +CHIP_CSRCS += rm57_irq.c rm57_lowputc.c rm57_serial.c rm57_esm.c + +CHIP_ASRCS = rm57_coreinit.S + +# Configuration dependent C and assembly language files + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += rm57_timerisr.c +endif + +# RM57 has no GIC - it uses the classic Hercules VIM interrupt controller + +CMN_CSRCS := $(filter-out arm_gicv2.c arm_gicv2_dump.c, $(CMN_CSRCS)) diff --git a/arch/arm/src/rm57/chip.h b/arch/arm/src/rm57/chip.h new file mode 100644 index 0000000000000..12c670cce9e55 --- /dev/null +++ b/arch/arm/src/rm57/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/rm57/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RM57_CHIP_H +#define __ARCH_ARM_SRC_RM57_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "hardware/rm57l843_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Cache line sizes (in bytes) */ + +#define ARMV7A_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */ +#define ARMV7A_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */ + +#endif /* __ARCH_ARM_SRC_RM57_CHIP_H */ diff --git a/arch/arm/src/rm57/hardware/rm57_esm.h b/arch/arm/src/rm57/hardware/rm57_esm.h new file mode 100644 index 0000000000000..88eada618e72e --- /dev/null +++ b/arch/arm/src/rm57/hardware/rm57_esm.h @@ -0,0 +1,140 @@ +/**************************************************************************** + * arch/arm/src/rm57/hardware/rm57_esm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Register layout taken from TI's HALCoGen HL_reg_esm.h for + * RM57L843 - matches TMS570's ESM address (0xfffff500). See + * rm57_esm.c for the early-boot ESM quiesce sequence. + */ + +#ifndef __ARCH_ARM_SRC_RM57_HARDWARE_RM57_ESM_H +#define __ARCH_ARM_SRC_RM57_HARDWARE_RM57_ESM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/rm57l843_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RM57_ESM_EEPAPR1_OFFSET 0x0000 /* Error Enable Primary Register 1 */ + +/* Error Disable Primary Register 1 */ +#define RM57_ESM_DEPAPR1_OFFSET 0x0004 + +/* Interrupt Enable Set/Status Register 1 */ +#define RM57_ESM_IESR1_OFFSET 0x0008 + +/* Interrupt Enable Clear Register 1 */ +#define RM57_ESM_IECR1_OFFSET 0x000c +#define RM57_ESM_ILSR1_OFFSET 0x0010 /* Interrupt Level Set Register 1 */ + +/* Interrupt Level Clear Register 1 */ +#define RM57_ESM_ILCR1_OFFSET 0x0014 + +/* Status Register 1, n=0..2 */ +#define RM57_ESM_SR1_OFFSET(n) (0x0018 + ((n) << 2)) +#define RM57_ESM_EPSR_OFFSET 0x0024 /* Error Pin Status Register */ +#define RM57_ESM_IOFFHR_OFFSET 0x0028 /* Interrupt Offset High Register */ +#define RM57_ESM_IOFFLR_OFFSET 0x002c /* Interrupt Offset Low Register */ +#define RM57_ESM_LTCR_OFFSET 0x0030 /* Low Time Counter Register */ + +/* Low Time Counter Preload Register */ +#define RM57_ESM_LTCPR_OFFSET 0x0034 +#define RM57_ESM_EKR_OFFSET 0x0038 /* Error Key Register */ +#define RM57_ESM_SSR2_OFFSET 0x003c /* Status Shadow Register 2 */ + +/* Interrupt Enable Primary Status Register 4 */ +#define RM57_ESM_IEPSR4_OFFSET 0x0040 + +/* Interrupt Enable Primary Clear Register 4 */ +#define RM57_ESM_IEPCR4_OFFSET 0x0044 + +/* Interrupt Enable Set/Status Register 4 */ +#define RM57_ESM_IESR4_OFFSET 0x0048 + +/* Interrupt Enable Clear Register 4 */ +#define RM57_ESM_IECR4_OFFSET 0x004c +#define RM57_ESM_ILSR4_OFFSET 0x0050 /* Interrupt Level Set Register 4 */ + +/* Interrupt Level Clear Register 4 */ +#define RM57_ESM_ILCR4_OFFSET 0x0054 + +/* Status Register 4, n=0..2 */ +#define RM57_ESM_SR4_OFFSET(n) (0x0058 + ((n) << 2)) + +/* Interrupt Enable Primary Status Register 7 */ +#define RM57_ESM_IEPSR7_OFFSET 0x0080 + +/* Interrupt Enable Primary Clear Register 7 */ +#define RM57_ESM_IEPCR7_OFFSET 0x0084 + +/* Interrupt Enable Set/Status Register 7 */ +#define RM57_ESM_IESR7_OFFSET 0x0088 + +/* Interrupt Enable Clear Register 7 */ +#define RM57_ESM_IECR7_OFFSET 0x008c +#define RM57_ESM_ILSR7_OFFSET 0x0090 /* Interrupt Level Set Register 7 */ + +/* Interrupt Level Clear Register 7 */ +#define RM57_ESM_ILCR7_OFFSET 0x0094 + +/* Status Register 7, n=0..2 */ +#define RM57_ESM_SR7_OFFSET(n) (0x0098 + ((n) << 2)) + +/* Register Addresses *******************************************************/ + +#define RM57_ESM_EEPAPR1 (RM57_ESM_BASE + RM57_ESM_EEPAPR1_OFFSET) +#define RM57_ESM_DEPAPR1 (RM57_ESM_BASE + RM57_ESM_DEPAPR1_OFFSET) +#define RM57_ESM_IESR1 (RM57_ESM_BASE + RM57_ESM_IESR1_OFFSET) +#define RM57_ESM_IECR1 (RM57_ESM_BASE + RM57_ESM_IECR1_OFFSET) +#define RM57_ESM_ILSR1 (RM57_ESM_BASE + RM57_ESM_ILSR1_OFFSET) +#define RM57_ESM_ILCR1 (RM57_ESM_BASE + RM57_ESM_ILCR1_OFFSET) +#define RM57_ESM_EPSR (RM57_ESM_BASE + RM57_ESM_EPSR_OFFSET) +#define RM57_ESM_IOFFHR (RM57_ESM_BASE + RM57_ESM_IOFFHR_OFFSET) +#define RM57_ESM_IOFFLR (RM57_ESM_BASE + RM57_ESM_IOFFLR_OFFSET) +#define RM57_ESM_LTCR (RM57_ESM_BASE + RM57_ESM_LTCR_OFFSET) +#define RM57_ESM_LTCPR (RM57_ESM_BASE + RM57_ESM_LTCPR_OFFSET) +#define RM57_ESM_EKR (RM57_ESM_BASE + RM57_ESM_EKR_OFFSET) +#define RM57_ESM_SR1(n) (RM57_ESM_BASE + RM57_ESM_SR1_OFFSET(n)) +#define RM57_ESM_SSR2 (RM57_ESM_BASE + RM57_ESM_SSR2_OFFSET) +#define RM57_ESM_IEPSR4 (RM57_ESM_BASE + RM57_ESM_IEPSR4_OFFSET) +#define RM57_ESM_IEPCR4 (RM57_ESM_BASE + RM57_ESM_IEPCR4_OFFSET) +#define RM57_ESM_IESR4 (RM57_ESM_BASE + RM57_ESM_IESR4_OFFSET) +#define RM57_ESM_IECR4 (RM57_ESM_BASE + RM57_ESM_IECR4_OFFSET) +#define RM57_ESM_ILSR4 (RM57_ESM_BASE + RM57_ESM_ILSR4_OFFSET) +#define RM57_ESM_ILCR4 (RM57_ESM_BASE + RM57_ESM_ILCR4_OFFSET) +#define RM57_ESM_SR4(n) (RM57_ESM_BASE + RM57_ESM_SR4_OFFSET(n)) +#define RM57_ESM_IEPSR7 (RM57_ESM_BASE + RM57_ESM_IEPSR7_OFFSET) +#define RM57_ESM_IEPCR7 (RM57_ESM_BASE + RM57_ESM_IEPCR7_OFFSET) +#define RM57_ESM_IESR7 (RM57_ESM_BASE + RM57_ESM_IESR7_OFFSET) +#define RM57_ESM_IECR7 (RM57_ESM_BASE + RM57_ESM_IECR7_OFFSET) +#define RM57_ESM_ILSR7 (RM57_ESM_BASE + RM57_ESM_ILSR7_OFFSET) +#define RM57_ESM_ILCR7 (RM57_ESM_BASE + RM57_ESM_ILCR7_OFFSET) +#define RM57_ESM_SR7(n) (RM57_ESM_BASE + RM57_ESM_SR7_OFFSET(n)) + +#endif /* __ARCH_ARM_SRC_RM57_HARDWARE_RM57_ESM_H */ diff --git a/arch/arm/src/rm57/hardware/rm57_flash.h b/arch/arm/src/rm57/hardware/rm57_flash.h new file mode 100644 index 0000000000000..bd926a7b94f6e --- /dev/null +++ b/arch/arm/src/rm57/hardware/rm57_flash.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/rm57/hardware/rm57_flash.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Register layout taken from TI's HALCoGen HL_reg_flash.h for + * RM57L843 - matches TMS570's Flash Wrapper address (0xfff87000). Used + * for flash read-access wait-state configuration during clock/PLL + * setup (a higher CPU clock requires more flash wait states). + */ + +#ifndef __ARCH_ARM_SRC_RM57_HARDWARE_RM57_FLASH_H +#define __ARCH_ARM_SRC_RM57_HARDWARE_RM57_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/rm57l843_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* Flash Read Control Register */ +#define RM57_FLASH_FRDCNTL_OFFSET 0x0000 + +/* EEPROM/Flash EDAC Control Register 1 */ +#define RM57_FLASH_FEDACCTRL1_OFFSET 0x0008 + +/* Flash Bank Primary Address Tag Register */ +#define RM57_FLASH_FPRIM_ADD_TAG_OFFSET 0x0028 + +/* Flash Bank Access Control Register */ +#define RM57_FLASH_FBAC_OFFSET 0x003c + +/* Flash Bank Power Mode Register */ +#define RM57_FLASH_FBPWRMODE_OFFSET 0x0040 + +/* Flash Bank Power Mode Status Register */ +#define RM57_FLASH_FBPRDY_OFFSET 0x0044 + +/* Register Addresses *******************************************************/ + +#define RM57_FLASH_FRDCNTL (RM57_FWRAP_BASE + RM57_FLASH_FRDCNTL_OFFSET) +#define RM57_FLASH_FEDACCTRL1 (RM57_FWRAP_BASE + RM57_FLASH_FEDACCTRL1_OFFSET) +#define RM57_FLASH_FBAC (RM57_FWRAP_BASE + RM57_FLASH_FBAC_OFFSET) +#define RM57_FLASH_FBPWRMODE (RM57_FWRAP_BASE + RM57_FLASH_FBPWRMODE_OFFSET) +#define RM57_FLASH_FBPRDY (RM57_FWRAP_BASE + RM57_FLASH_FBPRDY_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* Flash Read Control Register */ + +/* Bits 8-11: Random read wait-states */ +#define FLASH_FRDCNTL_RWAIT_SHIFT (8) +#define FLASH_FRDCNTL_RWAIT_MASK (0xf << FLASH_FRDCNTL_RWAIT_SHIFT) +# define FLASH_FRDCNTL_RWAIT(n) ((uint32_t)(n) << FLASH_FRDCNTL_RWAIT_SHIFT) + +#endif /* __ARCH_ARM_SRC_RM57_HARDWARE_RM57_FLASH_H */ diff --git a/arch/arm/src/rm57/hardware/rm57_gio.h b/arch/arm/src/rm57/hardware/rm57_gio.h new file mode 100644 index 0000000000000..c0e8ac177aaed --- /dev/null +++ b/arch/arm/src/rm57/hardware/rm57_gio.h @@ -0,0 +1,122 @@ +/**************************************************************************** + * arch/arm/src/rm57/hardware/rm57_gio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Register layout for RM57L843 GIO, per TI's HALCoGen HL_reg_gio.h - + * matches TMS570's GIO layout/address (0xfff7bc00). + */ + +#ifndef __ARCH_ARM_SRC_RM57_HARDWARE_RM57_GIO_H +#define __ARCH_ARM_SRC_RM57_HARDWARE_RM57_GIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/rm57l843_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RM57_NPORTS 2 /* GIO Port A, Port B */ + +/* GIO Module Register Offsets **********************************************/ + +#define RM57_GIO_GCR0_OFFSET 0x0000 /* Global Control Register */ +#define RM57_GIO_INTDET_OFFSET 0x0008 /* Interrupt Detect Register */ +#define RM57_GIO_POL_OFFSET 0x000c /* Interrupt Polarity Register */ +#define RM57_GIO_ENASET_OFFSET 0x0010 /* Interrupt Enable Set Register */ +#define RM57_GIO_ENACLR_OFFSET 0x0014 /* Interrupt Enable Clear Register */ +#define RM57_GIO_LVLSET_OFFSET 0x0018 /* Interrupt Priority Set Register */ + +/* Interrupt Priority Clear Register */ +#define RM57_GIO_LVLCLR_OFFSET 0x001c +#define RM57_GIO_FLG_OFFSET 0x0020 /* Interrupt Flag Register */ +#define RM57_GIO_OFF1_OFFSET 0x0024 /* Interrupt Offset A Register */ +#define RM57_GIO_OFF2_OFFSET 0x0028 /* Interrupt Offset B Register */ +#define RM57_GIO_EMU1_OFFSET 0x002c /* Emulation 1 Register */ +#define RM57_GIO_EMU2_OFFSET 0x0030 /* Emulation 2 Register */ + +/* GIO Port Register Offsets (relative to each gioPORTx base) ***************/ + +#define RM57_GIO_DIR_OFFSET 0x0000 /* Data Direction Register */ +#define RM57_GIO_DIN_OFFSET 0x0004 /* Data Input Register */ +#define RM57_GIO_DOUT_OFFSET 0x0008 /* Data Output Register */ +#define RM57_GIO_DSET_OFFSET 0x000c /* Data Output Set Register */ +#define RM57_GIO_DCLR_OFFSET 0x0010 /* Data Output Clear Register */ +#define RM57_GIO_PDR_OFFSET 0x0014 /* Open Drain Register */ +#define RM57_GIO_PULDIS_OFFSET 0x0018 /* Pullup Disable Register */ +#define RM57_GIO_PSL_OFFSET 0x001c /* Pull Up/Down Selection Register */ + +/* Register Addresses *******************************************************/ + +#define RM57_GIO_GCR0 (RM57_GIO_BASE + RM57_GIO_GCR0_OFFSET) +#define RM57_GIO_INTDET (RM57_GIO_BASE + RM57_GIO_INTDET_OFFSET) +#define RM57_GIO_POL (RM57_GIO_BASE + RM57_GIO_POL_OFFSET) +#define RM57_GIO_ENASET (RM57_GIO_BASE + RM57_GIO_ENASET_OFFSET) +#define RM57_GIO_ENACLR (RM57_GIO_BASE + RM57_GIO_ENACLR_OFFSET) +#define RM57_GIO_LVLSET (RM57_GIO_BASE + RM57_GIO_LVLSET_OFFSET) +#define RM57_GIO_LVLCLR (RM57_GIO_BASE + RM57_GIO_LVLCLR_OFFSET) +#define RM57_GIO_FLG (RM57_GIO_BASE + RM57_GIO_FLG_OFFSET) +#define RM57_GIO_OFF1 (RM57_GIO_BASE + RM57_GIO_OFF1_OFFSET) +#define RM57_GIO_OFF2 (RM57_GIO_BASE + RM57_GIO_OFF2_OFFSET) +#define RM57_GIO_EMU1 (RM57_GIO_BASE + RM57_GIO_EMU1_OFFSET) +#define RM57_GIO_EMU2 (RM57_GIO_BASE + RM57_GIO_EMU2_OFFSET) + +/* Port n base address: Port A and Port B are 0x20 bytes apart + * (gioPORT_t is 8 32-bit registers), matching + * RM57_GIO_PORTA_BASE/RM57_GIO_PORTB_BASE in rm57l843_memorymap.h + */ + +#define RM57_GIO_PORTBASE(n) (RM57_GIO_PORTA_BASE + ((n) << 5)) +#define RM57_GIO_DIR(n) (RM57_GIO_PORTBASE(n) + RM57_GIO_DIR_OFFSET) +#define RM57_GIO_DIN(n) (RM57_GIO_PORTBASE(n) + RM57_GIO_DIN_OFFSET) +#define RM57_GIO_DOUT(n) (RM57_GIO_PORTBASE(n) + RM57_GIO_DOUT_OFFSET) +#define RM57_GIO_DSET(n) (RM57_GIO_PORTBASE(n) + RM57_GIO_DSET_OFFSET) +#define RM57_GIO_DCLR(n) (RM57_GIO_PORTBASE(n) + RM57_GIO_DCLR_OFFSET) +#define RM57_GIO_PDR(n) (RM57_GIO_PORTBASE(n) + RM57_GIO_PDR_OFFSET) +#define RM57_GIO_PULDIS(n) (RM57_GIO_PORTBASE(n) + RM57_GIO_PULDIS_OFFSET) +#define RM57_GIO_PSL(n) (RM57_GIO_PORTBASE(n) + RM57_GIO_PSL_OFFSET) + +/* GIO Interrupt Enable Clear / Priority Clear Register: one byte per + * port, one bit per pin within the byte + */ + +#define GIO_ENACLR_PORT_SHIFT(p) ((p) << 3) +#define GIO_ENACLR_PORT_PIN(p,n) (1 << (GIO_ENACLR_PORT_SHIFT(p) + (n))) +#define GIO_LVLCLR_PORT_SHIFT(p) ((p) << 3) +#define GIO_LVLCLR_PORT_PIN(p,n) (1 << (GIO_LVLCLR_PORT_SHIFT(p) + (n))) + +/* Register Bit-Field Definitions *******************************************/ + +/* Global Control Register */ + +/* Bit 0: Take GIO module out of reset */ +#define GIO_GCR0_RESET (1 << 0) + +/* Per-pin bitmasks for GIOA0-GIOA7/GIOB0-GIOB7 are computed at the + * pinset-encoding level (see rm57_gio_pinmask() / GIO_PINn in + * rm57_gio.h), not duplicated here. + */ + +#endif /* __ARCH_ARM_SRC_RM57_HARDWARE_RM57_GIO_H */ diff --git a/arch/arm/src/rm57/hardware/rm57_pcr.h b/arch/arm/src/rm57/hardware/rm57_pcr.h new file mode 100644 index 0000000000000..a90b67395dade --- /dev/null +++ b/arch/arm/src/rm57/hardware/rm57_pcr.h @@ -0,0 +1,134 @@ +/**************************************************************************** + * arch/arm/src/rm57/hardware/rm57_pcr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Register layout taken from TI's HALCoGen HL_reg_pcr.h for + * RM57L843. Note RM57's PCR frame 1 (0xffff1000) is at a different + * address than TMS570LS04x's PCR (0xffffe000) - do not assume parity. + * RM57L843 also has three PCR frames (pcrREG1/2/3) vs. TMS570's one. + */ + +#ifndef __ARCH_ARM_SRC_RM57_HARDWARE_RM57_PCR_H +#define __ARCH_ARM_SRC_RM57_HARDWARE_RM57_PCR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/rm57l843_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* Peripheral Memory Protection Set Register 0 */ +#define RM57_PCR_PMPROTSET0_OFFSET 0x0000 + +/* Peripheral Memory Protection Set Register 1 */ +#define RM57_PCR_PMPROTSET1_OFFSET 0x0004 + +/* Peripheral Memory Protection Clear Register 0 */ +#define RM57_PCR_PMPROTCLR0_OFFSET 0x0010 + +/* Peripheral Memory Protection Clear Register 1 */ +#define RM57_PCR_PMPROTCLR1_OFFSET 0x0014 + +/* Peripheral Protection Set Register 0 */ +#define RM57_PCR_PPROTSET0_OFFSET 0x0020 + +/* Peripheral Protection Set Register 1 */ +#define RM57_PCR_PPROTSET1_OFFSET 0x0024 + +/* Peripheral Protection Set Register 2 */ +#define RM57_PCR_PPROTSET2_OFFSET 0x0028 + +/* Peripheral Protection Set Register 3 */ +#define RM57_PCR_PPROTSET3_OFFSET 0x002c + +/* Peripheral Protection Clear Register 0 */ +#define RM57_PCR_PPROTCLR0_OFFSET 0x0040 + +/* Peripheral Protection Clear Register 1 */ +#define RM57_PCR_PPROTCLR1_OFFSET 0x0044 + +/* Peripheral Protection Clear Register 2 */ +#define RM57_PCR_PPROTCLR2_OFFSET 0x0048 + +/* Peripheral Protection Clear Register 3 */ +#define RM57_PCR_PPROTCLR3_OFFSET 0x004c + +/* Peripheral Clock Set Power-Down Register 0 */ +#define RM57_PCR_PCSPWRDWNSET0_OFFSET 0x0060 + +/* Peripheral Clock Set Power-Down Register 1 */ +#define RM57_PCR_PCSPWRDWNSET1_OFFSET 0x0064 + +/* Peripheral Clock Clear Power-Down Register 0 */ +#define RM57_PCR_PCSPWRDWNCLR0_OFFSET 0x0070 + +/* Peripheral Clock Clear Power-Down Register 1 */ +#define RM57_PCR_PCSPWRDWNCLR1_OFFSET 0x0074 + +/* Peripheral Set Power-Down Register 0 */ +#define RM57_PCR_PSPWRDWNSET0_OFFSET 0x0080 + +/* Peripheral Set Power-Down Register 1 */ +#define RM57_PCR_PSPWRDWNSET1_OFFSET 0x0084 + +/* Peripheral Set Power-Down Register 2 */ +#define RM57_PCR_PSPWRDWNSET2_OFFSET 0x0088 + +/* Peripheral Set Power-Down Register 3 */ +#define RM57_PCR_PSPWRDWNSET3_OFFSET 0x008c + +/* Peripheral Clear Power-Down Register 0 */ +#define RM57_PCR_PSPWRDWNCLR0_OFFSET 0x00a0 + +/* Peripheral Clear Power-Down Register 1 */ +#define RM57_PCR_PSPWRDWNCLR1_OFFSET 0x00a4 + +/* Peripheral Clear Power-Down Register 2 */ +#define RM57_PCR_PSPWRDWNCLR2_OFFSET 0x00a8 + +/* Peripheral Clear Power-Down Register 3 */ +#define RM57_PCR_PSPWRDWNCLR3_OFFSET 0x00ac + +/* Peripheral Domain Set Power-Down Register */ +#define RM57_PCR_PDPWRDWNSET_OFFSET 0x00c0 + +/* Peripheral Domain Clear Power-Down Register */ +#define RM57_PCR_PDPWRDWNCLR_OFFSET 0x00c4 + +/* Register Addresses (PCR frame 1) *****************************************/ + +#define RM57_PCR1_PSPWRDWNSET0 (RM57_PCR1_BASE + RM57_PCR_PSPWRDWNSET0_OFFSET) +#define RM57_PCR1_PSPWRDWNSET1 (RM57_PCR1_BASE + RM57_PCR_PSPWRDWNSET1_OFFSET) +#define RM57_PCR1_PSPWRDWNSET2 (RM57_PCR1_BASE + RM57_PCR_PSPWRDWNSET2_OFFSET) +#define RM57_PCR1_PSPWRDWNSET3 (RM57_PCR1_BASE + RM57_PCR_PSPWRDWNSET3_OFFSET) +#define RM57_PCR1_PSPWRDWNCLR0 (RM57_PCR1_BASE + RM57_PCR_PSPWRDWNCLR0_OFFSET) +#define RM57_PCR1_PSPWRDWNCLR1 (RM57_PCR1_BASE + RM57_PCR_PSPWRDWNCLR1_OFFSET) +#define RM57_PCR1_PSPWRDWNCLR2 (RM57_PCR1_BASE + RM57_PCR_PSPWRDWNCLR2_OFFSET) +#define RM57_PCR1_PSPWRDWNCLR3 (RM57_PCR1_BASE + RM57_PCR_PSPWRDWNCLR3_OFFSET) + +#endif /* __ARCH_ARM_SRC_RM57_HARDWARE_RM57_PCR_H */ diff --git a/arch/arm/src/rm57/hardware/rm57_rti.h b/arch/arm/src/rm57/hardware/rm57_rti.h new file mode 100644 index 0000000000000..1049acf4e6c7d --- /dev/null +++ b/arch/arm/src/rm57/hardware/rm57_rti.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/arm/src/rm57/hardware/rm57_rti.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Register layout taken from TI's HALCoGen HL_reg_rti.h for + * RM57L843 - matches TMS570's RTI+DWWD address (0xfffffc00). Used for + * the NuttX system tick. + */ + +#ifndef __ARCH_ARM_SRC_RM57_HARDWARE_RM57_RTI_H +#define __ARCH_ARM_SRC_RM57_HARDWARE_RM57_RTI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/rm57l843_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RM57_RTI_GCTRL_OFFSET 0x0000 /* Global Control Register */ +#define RM57_RTI_TBCTRL_OFFSET 0x0004 /* Timebase Control Register */ +#define RM57_RTI_CAPCTRL_OFFSET 0x0008 /* Capture Control Register */ +#define RM57_RTI_COMPCTRL_OFFSET 0x000c /* Compare Control Register */ + +/* Counter x block (x = 0, 1), block size 0x20 */ + +/* Free Running Counter x */ +#define RM57_RTI_FRCx_OFFSET(x) (0x0010 + ((x) << 5)) +#define RM57_RTI_UCx_OFFSET(x) (0x0014 + ((x) << 5)) /* Up Counter x */ + +/* Compare Up Counter x */ +#define RM57_RTI_CPUCx_OFFSET(x) (0x0018 + ((x) << 5)) + +/* Capture Free Running Counter x */ +#define RM57_RTI_CAFRCx_OFFSET(x) (0x0020 + ((x) << 5)) + +/* Capture Up Counter x */ +#define RM57_RTI_CAUCx_OFFSET(x) (0x0024 + ((x) << 5)) + +/* Compare x block (x = 0..3), block size 0x08 */ + +#define RM57_RTI_COMPx_OFFSET(x) (0x0050 + ((x) << 3)) /* Compare x */ + +/* Update Compare x */ +#define RM57_RTI_UDCPx_OFFSET(x) (0x0054 + ((x) << 3)) + +/* External Clock Timebase Low Compare Register */ +#define RM57_RTI_TBLCOMP_OFFSET 0x0070 + +/* External Clock Timebase High Compare Register */ +#define RM57_RTI_TBHCOMP_OFFSET 0x0074 +#define RM57_RTI_SETINTENA_OFFSET 0x0080 /* Set/Status Interrupt Register */ + +/* Clear/Status Interrupt Register */ +#define RM57_RTI_CLEARINTENA_OFFSET 0x0084 +#define RM57_RTI_INTFLAG_OFFSET 0x0088 /* Interrupt Flag Register */ + +/* Digital Watchdog Control Register */ +#define RM57_RTI_DWDCTRL_OFFSET 0x0090 + +/* Digital Watchdog Preload Register */ +#define RM57_RTI_DWDPRLD_OFFSET 0x0094 +#define RM57_RTI_WDSTATUS_OFFSET 0x0098 /* Watchdog Status Register */ +#define RM57_RTI_WDKEY_OFFSET 0x009c /* Watchdog Key Register */ +#define RM57_RTI_DWDCNTR_OFFSET 0x00a0 /* Digital Watchdog Down Counter */ + +/* Windowed Watchdog Reaction Control */ +#define RM57_RTI_WWDRXNCTRL_OFFSET 0x00a4 + +/* Windowed Watchdog Window Size Control */ +#define RM57_RTI_WWDSIZECTRL_OFFSET 0x00a8 + +/* Compare Interrupt Clear Enable Register */ +#define RM57_RTI_INTCLRENABLE_OFFSET 0x00ac +#define RM57_RTI_COMP0CLR_OFFSET 0x00b0 /* Compare 0 Clear Register */ +#define RM57_RTI_COMP1CLR_OFFSET 0x00b4 /* Compare 1 Clear Register */ +#define RM57_RTI_COMP2CLR_OFFSET 0x00b8 /* Compare 2 Clear Register */ +#define RM57_RTI_COMP3CLR_OFFSET 0x00bc /* Compare 3 Clear Register */ + +/* Register Addresses (RTI1, counter/compare block 0) ***********************/ + +#define RM57_RTI_GCTRL (RM57_RTI1_BASE + RM57_RTI_GCTRL_OFFSET) +#define RM57_RTI_TBCTRL (RM57_RTI1_BASE + RM57_RTI_TBCTRL_OFFSET) +#define RM57_RTI_CAPCTRL (RM57_RTI1_BASE + RM57_RTI_CAPCTRL_OFFSET) +#define RM57_RTI_COMPCTRL (RM57_RTI1_BASE + RM57_RTI_COMPCTRL_OFFSET) +#define RM57_RTI_FRC0 (RM57_RTI1_BASE + RM57_RTI_FRCx_OFFSET(0)) +#define RM57_RTI_UC0 (RM57_RTI1_BASE + RM57_RTI_UCx_OFFSET(0)) +#define RM57_RTI_CPUC0 (RM57_RTI1_BASE + RM57_RTI_CPUCx_OFFSET(0)) +#define RM57_RTI_COMP0 (RM57_RTI1_BASE + RM57_RTI_COMPx_OFFSET(0)) +#define RM57_RTI_UDCP0 (RM57_RTI1_BASE + RM57_RTI_UDCPx_OFFSET(0)) +#define RM57_RTI_SETINTENA (RM57_RTI1_BASE + RM57_RTI_SETINTENA_OFFSET) +#define RM57_RTI_CLEARINTENA (RM57_RTI1_BASE + RM57_RTI_CLEARINTENA_OFFSET) +#define RM57_RTI_INTFLAG (RM57_RTI1_BASE + RM57_RTI_INTFLAG_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* Global Control Register */ + +/* Bit 0: Enable counter block 0 */ +#define RTI_GCTRL_CNT0EN (1 << 0) + +/* Bit 1: Enable counter block 1 */ +#define RTI_GCTRL_CNT1EN (1 << 1) + +/* Compare/interrupt bits (SETINTENA/CLEARINTENA/INTFLAG) */ + +#define RTI_INT_COMPARE0 (1 << 0) +#define RTI_INT_COMPARE1 (1 << 1) +#define RTI_INT_COMPARE2 (1 << 2) +#define RTI_INT_COMPARE3 (1 << 3) +#define RTI_INT_OVERFLOW0 (1 << 16) +#define RTI_INT_OVERFLOW1 (1 << 17) +#define RTI_INT_TIMEBASE (1 << 18) + +#endif /* __ARCH_ARM_SRC_RM57_HARDWARE_RM57_RTI_H */ diff --git a/arch/arm/src/rm57/hardware/rm57_sci.h b/arch/arm/src/rm57/hardware/rm57_sci.h new file mode 100644 index 0000000000000..e4f3818526d59 --- /dev/null +++ b/arch/arm/src/rm57/hardware/rm57_sci.h @@ -0,0 +1,230 @@ +/**************************************************************************** + * arch/arm/src/rm57/hardware/rm57_sci.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Register layout taken from TI's HALCoGen HL_reg_sci.h for + * RM57L843. RM57L843 has four SCI instances (SCI1/LIN1, SCI2, SCI3, + * SCI4) vs. TMS570LS's one or two - see rm57l843_memorymap.h for the + * per-instance base addresses. + */ + +#ifndef __ARCH_ARM_SRC_RM57_HARDWARE_RM57_SCI_H +#define __ARCH_ARM_SRC_RM57_HARDWARE_RM57_SCI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/rm57l843_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RM57_SCI_GCR0_OFFSET 0x0000 /* Global Control Register 0 */ +#define RM57_SCI_GCR1_OFFSET 0x0004 /* Global Control Register 1 */ + +/* Global Control Register 2 (LIN mode only) */ +#define RM57_SCI_GCR2_OFFSET 0x0008 + +/* Set Interrupt Enable Register */ +#define RM57_SCI_SETINT_OFFSET 0x000c + +/* Clear Interrupt Enable Register */ +#define RM57_SCI_CLEARINT_OFFSET 0x0010 +#define RM57_SCI_SETINTLVL_OFFSET 0x0014 /* Set Interrupt Level Register */ + +/* Clear Interrupt Level Register */ +#define RM57_SCI_CLEARINTLVL_OFFSET 0x0018 +#define RM57_SCI_FLR_OFFSET 0x001c /* Interrupt Flag Register */ +#define RM57_SCI_INTVECT0_OFFSET 0x0020 /* Interrupt Vector Offset 0 */ +#define RM57_SCI_INTVECT1_OFFSET 0x0024 /* Interrupt Vector Offset 1 */ +#define RM57_SCI_FORMAT_OFFSET 0x0028 /* Format Control Register */ +#define RM57_SCI_BRS_OFFSET 0x002c /* Baud Rate Selection Register */ +#define RM57_SCI_ED_OFFSET 0x0030 /* Emulation Register */ +#define RM57_SCI_RD_OFFSET 0x0034 /* Receive Data Buffer */ +#define RM57_SCI_TD_OFFSET 0x0038 /* Transmit Data Buffer */ +#define RM57_SCI_PIO0_OFFSET 0x003c /* Pin Function Register */ +#define RM57_SCI_PIO1_OFFSET 0x0040 /* Pin Direction Register */ +#define RM57_SCI_PIO2_OFFSET 0x0044 /* Pin Data In Register */ +#define RM57_SCI_PIO3_OFFSET 0x0048 /* Pin Data Out Register */ +#define RM57_SCI_PIO4_OFFSET 0x004c /* Pin Data Set Register */ +#define RM57_SCI_PIO5_OFFSET 0x0050 /* Pin Data Clr Register */ + +/* Pin Open Drain Output Enable Register */ +#define RM57_SCI_PIO6_OFFSET 0x0054 + +/* Pin Pullup/Pulldown Disable Register */ +#define RM57_SCI_PIO7_OFFSET 0x0058 + +/* Pin Pullup/Pulldown Selection Register */ +#define RM57_SCI_PIO8_OFFSET 0x005c +#define RM57_SCI_IODFTCTRL_OFFSET 0x0090 /* I/O Error Enable Register */ + +/* Register Bit-Field Definitions *******************************************/ + +/* Global Control Register 0 */ + +/* Bit 0: Take SCI out of reset */ +#define SCI_GCR0_RESET (1 << 0) + +/* Global Control Register 1 */ + +/* Bit 0: 0=idle-line, 1=addr-bit mode */ +#define SCI_GCR1_COMM_MODE (1 << 0) + +/* Bit 1: Asynchronous timing mode */ +#define SCI_GCR1_TIMING_MODE (1 << 1) +#define SCI_GCR1_PARITY_ENA (1 << 2) /* Bit 2: Parity enable */ +#define SCI_GCR1_PARITY (1 << 3) /* Bit 3: 0=odd, 1=even */ + +/* Bit 4: 0=1 stop bit, 1=2 stop bits */ +#define SCI_GCR1_STOP (1 << 4) + +/* Bit 5: Clock signal source (LIN mode) */ +#define SCI_GCR1_CLOCK (1 << 5) +#define SCI_GCR1_LIN_MODE (1 << 6) /* Bit 6: 0=SCI, 1=LIN */ + +/* Bit 7: Software reset, active low */ +#define SCI_GCR1_SWRST (1 << 7) + +/* Bit 8: Character type, 0=1 stop, 1=2 stop */ +#define SCI_GCR1_CTYPE (1 << 8) + +/* Bit 9: LIN hardware generation control */ +#define SCI_GCR1_HGEN_CTRL (1 << 9) +#define SCI_GCR1_RXENA (1 << 24) /* Bit 24: Receiver enable */ + +/* Bit 25: Transmitter enable */ +#define SCI_GCR1_TXENA (1 << 25) +#define SCI_GCR1_LOOPBACK (1 << 16) /* Bit 16: Loop back enable */ + +/* Interrupt Flag / Set / Clear Register bits (common to SETINT/CLEARINT/ + * FLR) - values confirmed from TI's HALCoGen HL_sci.h sciInterrupt_t + * enum, not guessed + */ + +#define SCI_INT_BREAK (0x00000001) /* Break detect */ +#define SCI_INT_WAKE (0x00000002) /* Wakeup */ +#define SCI_INT_TX (0x00000100) /* Transmit buffer ready */ +#define SCI_INT_RX (0x00000200) /* Receive buffer ready */ +#define SCI_INT_PE (0x01000000) /* Parity error */ +#define SCI_INT_OE (0x02000000) /* Overrun error */ +#define SCI_INT_FE (0x04000000) /* Framing error */ +#define SCI_INT_ALLINTS (0xff0023d3) + +/* Baud Rate Selection Register: P (integer divider, bits 0-23), M (4-bit + * fractional divider, bits 24-27), U (super-fractional divider, bits + * 28-30) + */ + +#define SCI_BRS_P_SHIFT (0) +#define SCI_BRS_P_MASK (0x00ffffff << SCI_BRS_P_SHIFT) +# define SCI_BRS_P(n) ((uint32_t)(n) << SCI_BRS_P_SHIFT) +#define SCI_BRS_M_SHIFT (24) +#define SCI_BRS_M_MASK (15 << SCI_BRS_M_SHIFT) +# define SCI_BRS_M(n) ((uint32_t)(n) << SCI_BRS_M_SHIFT) +#define SCI_BRS_U_SHIFT (28) +#define SCI_BRS_U_MASK (7 << SCI_BRS_U_SHIFT) +# define SCI_BRS_U(n) ((uint32_t)(n) << SCI_BRS_U_SHIFT) + +/* Format Control Register: frame length control, bits 0-2 (nbits - 1) */ + +#define SCI_FORMAT_CHAR_SHIFT (0) +#define SCI_FORMAT_CHAR_MASK (7 << SCI_FORMAT_CHAR_SHIFT) +# define SCI_FORMAT_CHAR(n) ((uint32_t)(n) << SCI_FORMAT_CHAR_SHIFT) + +/* Pin Function Register (PIO0): confirmed from HL_sci.h + * SCI3_PIO0_CONFIGVALUE = (1<<2)|(1<<1) + */ + +#define SCI_PIO_RX (1 << 1) /* Bit 1: RX pin */ +#define SCI_PIO_TX (1 << 2) /* Bit 2: TX pin */ + +/* SCI Flags Register (FLR) - same bit positions as SETINT/CLEARINT above, + * plus status-only bits below. NOT independently derivable from + * HL_reg_sci.h (which only gives register offsets, not TRM-documented + * bit tables); reused from tms570_sci.h since both TMS570 and RM57 share + * the same underlying Hercules SCI IP block (confirmed by the GCR1 bit + * positions matching exactly against the HALCoGen SCI3_GCR1_CONFIGVALUE + * decode above). + */ + +/* Bit 0: Break detect flag */ +#define SCI_FLR_BRKDT (1 << 0) +#define SCI_FLR_WAKEUP (1 << 1) /* Bit 1: Wake-up flag */ + +/* Bit 2: SCI receiver in idle state */ +#define SCI_FLR_IDLE (1 << 2) +#define SCI_FLR_BUSY (1 << 3) /* Bit 3: Bus busy flag */ +#define SCI_FLR_TIMEOUT (1 << 4) /* Bit 4: Timeout flag */ + +/* Bit 8: Transmit buffer ready flag */ +#define SCI_FLR_TXRDY (1 << 8) + +/* Bit 9: Receive buffer ready flag */ +#define SCI_FLR_RXRDY (1 << 9) + +/* Bit 11: Transmitter empty flag */ +#define SCI_FLR_TXEMPTY (1 << 11) + +/* Bit 24: Parity error flag */ +#define SCI_FLR_PE (1 << 24) + +/* Bit 25: Overrun error flag */ +#define SCI_FLR_OE (1 << 25) + +/* Bit 26: Framing error flag */ +#define SCI_FLR_FE (1 << 26) + +/* SCI Interrupt Vector Offset Registers (INTVECT0/1): priority-encoded + * pending-interrupt code, cleared on read (same source table as + * tms570_sci.h - see note above) + */ + +#define SCI_INTVECT_MASK (0x1f) +# define SCI_INTVECT_NONE (0) +# define SCI_INTVECT_WAKEUP (1) +# define SCI_INTVECT_ISFE (2) +# define SCI_INTVECT_PE (3) +# define SCI_INTVECT_ID (4) +# define SCI_INTVECT_PBE (5) +# define SCI_INTVECT_FE (6) +# define SCI_INTVECT_BRKDT (7) +# define SCI_INTVECT_CE (8) +# define SCI_INTVECT_OE (9) +# define SCI_INTVECT_BE (10) +# define SCI_INTVECT_RX (11) +# define SCI_INTVECT_TX (12) +# define SCI_INTVECT_NRE (13) +# define SCI_INTVECT_TOAWUS (14) +# define SCI_INTVECT_TOA3WUS (15) +# define SCI_INTVECT_TIMEOUT (16) + +/* Receive/Transmit Data Buffer */ + +#define SCI_RD_MASK (0xff) +#define SCI_TD_MASK (0xff) + +#endif /* __ARCH_ARM_SRC_RM57_HARDWARE_RM57_SCI_H */ diff --git a/arch/arm/src/rm57/hardware/rm57_sys.h b/arch/arm/src/rm57/hardware/rm57_sys.h new file mode 100644 index 0000000000000..86f87a589832a --- /dev/null +++ b/arch/arm/src/rm57/hardware/rm57_sys.h @@ -0,0 +1,355 @@ +/**************************************************************************** + * arch/arm/src/rm57/hardware/rm57_sys.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Register layout taken from TI's HALCoGen HL_reg_system.h for + * RM57L843. System Frame 1 (systemREG1, 0xffffff00) and Frame 2 + * (systemREG2, 0xffffe100) match TMS570's addresses - this is common + * Hercules "SYS" module infrastructure. Field-level PLL/clock values + * (BOARD_PLL_* etc) are supplied per-board (arch/board/board.h), not + * here. + */ + +#ifndef __ARCH_ARM_SRC_RM57_HARDWARE_RM57_SYS_H +#define __ARCH_ARM_SRC_RM57_HARDWARE_RM57_SYS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/rm57l843_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* System Frame 1 Register Offsets ******************************************/ + +#define RM57_SYS_SYSPC1_OFFSET 0x0000 /* SYS Pin Control Register 1 */ +#define RM57_SYS_SYSPC2_OFFSET 0x0004 /* SYS Pin Control Register 2 */ +#define RM57_SYS_SYSPC3_OFFSET 0x0008 /* SYS Pin Control Register 3 */ +#define RM57_SYS_SYSPC4_OFFSET 0x000c /* SYS Pin Control Register 4 */ +#define RM57_SYS_SYSPC5_OFFSET 0x0010 /* SYS Pin Control Register 5 */ +#define RM57_SYS_SYSPC6_OFFSET 0x0014 /* SYS Pin Control Register 6 */ +#define RM57_SYS_SYSPC7_OFFSET 0x0018 /* SYS Pin Control Register 7 */ +#define RM57_SYS_SYSPC8_OFFSET 0x001c /* SYS Pin Control Register 8 */ +#define RM57_SYS_SYSPC9_OFFSET 0x0020 /* SYS Pin Control Register 9 */ +#define RM57_SYS_CSDIS_OFFSET 0x0030 /* Clock Source Disable Register */ + +/* Clock Source Disable Set Register */ +#define RM57_SYS_CSDISSET_OFFSET 0x0034 + +/* Clock Source Disable Clear Register */ +#define RM57_SYS_CSDISCLR_OFFSET 0x0038 +#define RM57_SYS_CDDIS_OFFSET 0x003c /* Clock Domain Disable Register */ + +/* Clock Domain Disable Set Register */ +#define RM57_SYS_CDDISSET_OFFSET 0x0040 + +/* Clock Domain Disable Clear Register */ +#define RM57_SYS_CDDISCLR_OFFSET 0x0044 + +/* GCLK, HCLK, VCLK, VCLK2 Source Register */ +#define RM57_SYS_GHVSRC_OFFSET 0x0048 + +/* Peripheral Asynchronous Clock Source Register */ +#define RM57_SYS_VCLKASRC_OFFSET 0x004c +#define RM57_SYS_RCLKSRC_OFFSET 0x0050 /* RTI Clock Source Register */ + +/* Clock Source Valid Status Register */ +#define RM57_SYS_CSVSTAT_OFFSET 0x0054 + +/* Memory Self-Test Global Control Register */ +#define RM57_SYS_MSTGCR_OFFSET 0x0058 + +/* Memory Hardware Initialization Global Control Register */ +#define RM57_SYS_MINITGCR_OFFSET 0x005c + +/* Memory Self-Test/Initialization Enable Register */ +#define RM57_SYS_MSINENA_OFFSET 0x0060 + +/* Memory Self-Test Fail Status Register */ +#define RM57_SYS_MSTFAIL_OFFSET 0x0064 +#define RM57_SYS_MSTCGSTAT_OFFSET 0x0068 /* MSTC Global Status Register */ + +/* Memory Hardware Initialization Status Register */ +#define RM57_SYS_MINISTAT_OFFSET 0x006c +#define RM57_SYS_PLLCTL1_OFFSET 0x0070 /* PLL Control Register 1 */ +#define RM57_SYS_PLLCTL2_OFFSET 0x0074 /* PLL Control Register 2 */ +#define RM57_SYS_SYSPC10_OFFSET 0x0078 /* SYS Pin Control Register 10 */ + +/* Die Identification Register, Lower Word */ +#define RM57_SYS_DIEIDL_OFFSET 0x007c + +/* Die Identification Register, Upper Word */ +#define RM57_SYS_DIEIDH_OFFSET 0x0080 + +/* LPO/Clock Monitor Control Register */ +#define RM57_SYS_LPOMONCTL_OFFSET 0x0088 +#define RM57_SYS_CLKTEST_OFFSET 0x008c /* Clock Test Register */ +#define RM57_SYS_DFTCTRLREG1_OFFSET 0x0090 /* DFT Control Register 1 */ +#define RM57_SYS_DFTCTRLREG2_OFFSET 0x0094 /* DFT Control Register 2 */ +#define RM57_SYS_GPREG1_OFFSET 0x00a0 /* General Purpose Register */ + +/* System Software Interrupt Request 1 Register */ +#define RM57_SYS_SSIR1_OFFSET 0x00b0 + +/* System Software Interrupt Request 2 Register */ +#define RM57_SYS_SSIR2_OFFSET 0x00b4 + +/* System Software Interrupt Request 3 Register */ +#define RM57_SYS_SSIR3_OFFSET 0x00b8 + +/* System Software Interrupt Request 4 Register */ +#define RM57_SYS_SSIR4_OFFSET 0x00bc +#define RM57_SYS_RAMGCR_OFFSET 0x00c0 /* RAM Control Register */ + +/* Bus Matrix Module Control Register 1 */ +#define RM57_SYS_BMMCR1_OFFSET 0x00c4 +#define RM57_SYS_CPURSTCR_OFFSET 0x00cc /* CPU Reset Control Register */ +#define RM57_SYS_CLKCNTL_OFFSET 0x00d0 /* Clock Control Register */ +#define RM57_SYS_ECPCNTL_OFFSET 0x00d4 /* ECP Control Register */ +#define RM57_SYS_DEVCR1_OFFSET 0x00dc /* DEV Parity Control Register 1 */ + +/* System Exception Control Register */ +#define RM57_SYS_SYSECR_OFFSET 0x00e0 + +/* System Exception Status Register */ +#define RM57_SYS_SYSESR_OFFSET 0x00e4 + +/* System Test Abort Status Register */ +#define RM57_SYS_SYSTASR_OFFSET 0x00e8 +#define RM57_SYS_GBLSTAT_OFFSET 0x00ec /* Global Status Register */ + +/* Device Identification Register */ +#define RM57_SYS_DEVID_OFFSET 0x00f0 + +/* Software Interrupt Vector Register */ +#define RM57_SYS_SSIVEC_OFFSET 0x00f4 + +/* System Software Interrupt Flag Register */ +#define RM57_SYS_SSIF_OFFSET 0x00f8 + +/* System Frame 2 Register Offsets ******************************************/ + +#define RM57_SYS2_PLLCTL3_OFFSET 0x0000 /* PLL Control Register 3 */ +#define RM57_SYS2_STCCLKDIV_OFFSET 0x0008 /* STC Clock Divider Register */ +#define RM57_SYS2_ECPCNTL_OFFSET 0x0024 /* ECP Control Register */ +#define RM57_SYS2_ECPCNTL1_OFFSET 0x0028 /* ECP Control Register 1 */ + +/* Peripheral Asynchronous Clock 2 Control Register */ +#define RM57_SYS2_CLK2CNTRL_OFFSET 0x003c + +/* Peripheral Asynchronous Clock Control Register */ +#define RM57_SYS2_VCLKACON1_OFFSET 0x0040 +#define RM57_SYS2_HCLKCNTL_OFFSET 0x0054 /* HCLK Control Register */ +#define RM57_SYS2_CLKSLIP_OFFSET 0x0070 /* Clock Slip Register */ +#define RM57_SYS2_EFC_CTLEN_OFFSET 0x00ec /* EFC Control Enable Register */ + +/* Register Addresses (System Frame 1) **************************************/ + +#define RM57_SYS_CSDIS (RM57_SYS1_BASE + RM57_SYS_CSDIS_OFFSET) +#define RM57_SYS_CSDISSET (RM57_SYS1_BASE + RM57_SYS_CSDISSET_OFFSET) +#define RM57_SYS_CSDISCLR (RM57_SYS1_BASE + RM57_SYS_CSDISCLR_OFFSET) +#define RM57_SYS_CDDIS (RM57_SYS1_BASE + RM57_SYS_CDDIS_OFFSET) +#define RM57_SYS_CDDISSET (RM57_SYS1_BASE + RM57_SYS_CDDISSET_OFFSET) +#define RM57_SYS_CDDISCLR (RM57_SYS1_BASE + RM57_SYS_CDDISCLR_OFFSET) +#define RM57_SYS_GHVSRC (RM57_SYS1_BASE + RM57_SYS_GHVSRC_OFFSET) +#define RM57_SYS_VCLKASRC (RM57_SYS1_BASE + RM57_SYS_VCLKASRC_OFFSET) +#define RM57_SYS_RCLKSRC (RM57_SYS1_BASE + RM57_SYS_RCLKSRC_OFFSET) +#define RM57_SYS_CSVSTAT (RM57_SYS1_BASE + RM57_SYS_CSVSTAT_OFFSET) +#define RM57_SYS_MSTGCR (RM57_SYS1_BASE + RM57_SYS_MSTGCR_OFFSET) +#define RM57_SYS_MINITGCR (RM57_SYS1_BASE + RM57_SYS_MINITGCR_OFFSET) +#define RM57_SYS_MSINENA (RM57_SYS1_BASE + RM57_SYS_MSINENA_OFFSET) +#define RM57_SYS_MSTCGSTAT (RM57_SYS1_BASE + RM57_SYS_MSTCGSTAT_OFFSET) +#define RM57_SYS_MINISTAT (RM57_SYS1_BASE + RM57_SYS_MINISTAT_OFFSET) +#define RM57_SYS_PLLCTL1 (RM57_SYS1_BASE + RM57_SYS_PLLCTL1_OFFSET) +#define RM57_SYS_PLLCTL2 (RM57_SYS1_BASE + RM57_SYS_PLLCTL2_OFFSET) +#define RM57_SYS_GPREG1 (RM57_SYS1_BASE + RM57_SYS_GPREG1_OFFSET) +#define RM57_SYS_RAMGCR (RM57_SYS1_BASE + RM57_SYS_RAMGCR_OFFSET) +#define RM57_SYS_CPURSTCR (RM57_SYS1_BASE + RM57_SYS_CPURSTCR_OFFSET) +#define RM57_SYS_CLKCNTL (RM57_SYS1_BASE + RM57_SYS_CLKCNTL_OFFSET) +#define RM57_SYS_SYSECR (RM57_SYS1_BASE + RM57_SYS_SYSECR_OFFSET) +#define RM57_SYS_SYSESR (RM57_SYS1_BASE + RM57_SYS_SYSESR_OFFSET) +#define RM57_SYS_GBLSTAT (RM57_SYS1_BASE + RM57_SYS_GBLSTAT_OFFSET) +#define RM57_SYS_DEVID (RM57_SYS1_BASE + RM57_SYS_DEVID_OFFSET) + +/* Register Addresses (System Frame 2) **************************************/ + +#define RM57_SYS2_PLLCTL3 (RM57_SYS2_BASE + RM57_SYS2_PLLCTL3_OFFSET) +#define RM57_SYS2_STCCLKDIV (RM57_SYS2_BASE + RM57_SYS2_STCCLKDIV_OFFSET) +#define RM57_SYS2_HCLKCNTL (RM57_SYS2_BASE + RM57_SYS2_HCLKCNTL_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* Clock Source Disable / Domain Disable Registers */ + +#define SYS_CSDIS_CLKSR0OFF (1 << 0) /* Bit 0: Oscillator */ +#define SYS_CSDIS_CLKSR1OFF (1 << 1) /* Bit 1: PLL1 */ +#define SYS_CSDIS_CLKSR3OFF (1 << 3) /* Bit 3: External clock in */ +#define SYS_CSDIS_CLKSR4OFF (1 << 4) /* Bit 4: Low-freq LPO */ +#define SYS_CSDIS_CLKSR5OFF (1 << 5) /* Bit 5: High-freq LPO */ +#define SYS_CSDIS_CLKSR6OFF (1 << 6) /* Bit 6: PLL2 */ + +/* Bit 7: External clock in 2 */ +#define SYS_CSDIS_CLKSR7OFF (1 << 7) + +#define SYS_CDDIS_GCLKOFF (1 << 0) /* Bit 0: GCLK domain off */ + +/* Bit 1: HCLK/VCLK_sys domains off */ +#define SYS_CDDIS_HCLKOFF (1 << 1) + +/* Bit 2: VCLK_periph domain off */ +#define SYS_CDDIS_VCLKPOFF (1 << 2) +#define SYS_CDDIS_VCLK2OFF (1 << 3) /* Bit 3: VCLK2 domain off */ +#define SYS_CDDIS_VCLKA1OFF (1 << 4) /* Bit 4: VCLKA1 domain off */ +#define SYS_CDDIS_RTICLK1OFF (1 << 6) /* Bit 6: RTICLK1 domain off */ + +/* GCLK, HCLK, VCLK, VCLK2 Source Register clock source aliases */ + +#define SYS_CLKSRC_OSC 0 +#define SYS_CLKSRC_PLL1 1 +#define SYS_CLKSRC_EXTERNAL1 3 +#define SYS_CLKSRC_LPOLOW 4 +#define SYS_CLKSRC_LPOHIGH 5 +#define SYS_CLKSRC_PLL2 6 +#define SYS_CLKSRC_EXTERNAL2 7 +#define SYS_CLKSRC_VCLK 9 + +/* Bits 0-3: GCLK/HCLK/VCLK/VCLK2 current source */ +#define SYS_GHVSRC_GHVSRC_SHIFT (0) +#define SYS_GHVSRC_GHVSRC_MASK (15 << SYS_GHVSRC_GHVSRC_SHIFT) +# define SYS_GHVSRC_GHVSRC_SRC(n) ((uint32_t)(n) << SYS_GHVSRC_GHVSRC_SHIFT) + +/* Bits 16-19: HCLK/VCLK/VCLK2 source on wakeup */ +#define SYS_GHVSRC_HVLPM_SHIFT (16) +#define SYS_GHVSRC_HVLPM_MASK (15 << SYS_GHVSRC_HVLPM_SHIFT) +# define SYS_GHVSRC_HVLPM(n) ((uint32_t)(n) << SYS_GHVSRC_HVLPM_SHIFT) + +/* Bits 24-27: GCLK/HCLK/VCLK/VCLK2 source on wakeup */ +#define SYS_GHVSRC_GHVWAKE_SHIFT (24) +#define SYS_GHVSRC_GHVWAKE_MASK (15 << SYS_GHVSRC_GHVWAKE_SHIFT) +# define SYS_GHVSRC_GHVWAKE(n) ((uint32_t)(n) << SYS_GHVSRC_GHVWAKE_SHIFT) + +/* RTI Clock Source Register */ + +/* Bits 0-3: RTI clock1 source */ +#define SYS_RCLKSRC_RTI1SRC_SHIFT (0) +#define SYS_RCLKSRC_RTI1SRC_MASK (15 << SYS_RCLKSRC_RTI1SRC_SHIFT) +# define SYS_RCLKSRC_RTI1SRC(n) ((uint32_t)(n) << SYS_RCLKSRC_RTI1SRC_SHIFT) + +/* Bits 8-9: RTI clock1 divider */ +#define SYS_RCLKSRC_RTI1DIV_SHIFT (8) +#define SYS_RCLKSRC_RTI1DIV_MASK (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) +# define SYS_RCLKSRC_RTI1DIV_DIV1 (0 << SYS_RCLKSRC_RTI1DIV_SHIFT) +# define SYS_RCLKSRC_RTI1DIV_DIV2 (1 << SYS_RCLKSRC_RTI1DIV_SHIFT) +# define SYS_RCLKSRC_RTI1DIV_DIV4 (2 << SYS_RCLKSRC_RTI1DIV_SHIFT) +# define SYS_RCLKSRC_RTI1DIV_DIV8 (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) + +/* Memory Self-Test / Hardware Init Global Control Registers (ECC RAM init) */ + +/* Bits 0-3: Memory self-test global enable key */ +#define SYS_MSTGCR_MSTGENA_SHIFT (0) +#define SYS_MSTGCR_MSTGENA_MASK (15 << SYS_MSTGCR_MSTGENA_SHIFT) +# define SYS_MSTGCR_MSTGENA_ENABLE (10 << SYS_MSTGCR_MSTGENA_SHIFT) +# define SYS_MSTGCR_MSTGENA_DISABLE (5 << SYS_MSTGCR_MSTGENA_SHIFT) + +/* Bits 0-7: Memory hardware init key */ +#define SYS_MINITGCR_MASK (0xff) +# define SYS_MINITGCR_ENABLE (0x0a) +# define SYS_MINITGCR_DISABLE (0x05) + +/* Bit 0: Memory self-test done */ +#define SYS_MSTCGSTAT_MSTDONE (1 << 0) + +/* Bit 8: Hardware init of all memory done */ +#define SYS_MSTCGSTAT_MINIDONE (1 << 8) + +/* PLL Control Register 1 */ + +/* Bits 0-15: PLL multiplication factor */ +#define SYS_PLLCTL1_PLLMUL_SHIFT (0) +#define SYS_PLLCTL1_PLLMUL_MASK (0xffff << SYS_PLLCTL1_PLLMUL_SHIFT) +# define SYS_PLLCTL1_PLLMUL(n) ((uint32_t)(n) << SYS_PLLCTL1_PLLMUL_SHIFT) + +/* Bits 16-21: Reference clock divider */ +#define SYS_PLLCTL1_REFCLKDIV_SHIFT (16) +#define SYS_PLLCTL1_REFCLKDIV_MASK (0x3f << SYS_PLLCTL1_REFCLKDIV_SHIFT) +# define SYS_PLLCTL1_REFCLKDIV(n) ((uint32_t)(n) << \ + SYS_PLLCTL1_REFCLKDIV_SHIFT) + +/* Bit 23: Reset on oscillator fail */ +#define SYS_PLLCTL1_ROF (1 << 23) + +/* Bits 24-28: PLL output clock divider */ +#define SYS_PLLCTL1_PLLDIV_SHIFT (24) +#define SYS_PLLCTL1_PLLDIV_MASK (0x1f << SYS_PLLCTL1_PLLDIV_SHIFT) +# define SYS_PLLCTL1_PLLDIV(n) ((uint32_t)(n) << SYS_PLLCTL1_PLLDIV_SHIFT) + +/* Bit 31: Reset on PLL slip */ +#define SYS_PLLCTL1_ROS (1 << 31) + +/* PLL Control Register 2 */ + +/* Bits 0-8: Spreading amount */ +#define SYS_PLLCTL2_SPRAMOUNT_SHIFT (0) +#define SYS_PLLCTL2_SPRAMOUNT_MASK (0xff << SYS_PLLCTL2_SPRAMOUNT_SHIFT) +# define SYS_PLLCTL2_SPRAMOUNT(n) ((uint32_t)(n) << \ + SYS_PLLCTL2_SPRAMOUNT_SHIFT) + +/* Bits 9-11: Internal PLL output divider */ +#define SYS_PLLCTL2_ODPLL_SHIFT (9) +#define SYS_PLLCTL2_ODPLL_MASK (7 << SYS_PLLCTL2_ODPLL_SHIFT) +# define SYS_PLLCTL2_ODPLL(n) ((uint32_t)(n) << SYS_PLLCTL2_ODPLL_SHIFT) + +/* Bits 12-20: Multiplier correction (freq modulation) */ +#define SYS_PLLCTL2_MULMOD_SHIFT (12) +#define SYS_PLLCTL2_MULMOD_MASK (0x1ff << SYS_PLLCTL2_MULMOD_SHIFT) +# define SYS_PLLCTL2_MULMOD(n) ((uint32_t)(n) << SYS_PLLCTL2_MULMOD_SHIFT) + +/* Bit 31: Frequency modulation enable */ +#define SYS_PLLCTL2_FMENA (1 << 31) + +/* PLL Control Register 3 (System Frame 2) */ + +/* Bits 0-4: PLL2 output clock divider */ +#define SYS2_PLLCTL3_PLLDIV_SHIFT (0) +#define SYS2_PLLCTL3_PLLDIV_MASK (0x1f << SYS2_PLLCTL3_PLLDIV_SHIFT) +# define SYS2_PLLCTL3_PLLDIV(n) ((uint32_t)(n) << SYS2_PLLCTL3_PLLDIV_SHIFT) + +/* Bits 9-11: PLL2 internal output divider */ +#define SYS2_PLLCTL3_ODPLL2_SHIFT (9) +#define SYS2_PLLCTL3_ODPLL2_MASK (7 << SYS2_PLLCTL3_ODPLL2_SHIFT) +# define SYS2_PLLCTL3_ODPLL2(n) ((uint32_t)(n) << SYS2_PLLCTL3_ODPLL2_SHIFT) + +/* Bits 16-31: PLL2 multiplication factor */ +#define SYS2_PLLCTL3_PLLMUL2_SHIFT (16) +#define SYS2_PLLCTL3_PLLMUL2_MASK (0xffff << SYS2_PLLCTL3_PLLMUL2_SHIFT) +# define SYS2_PLLCTL3_PLLMUL2(n) ((uint32_t)(n) << \ + SYS2_PLLCTL3_PLLMUL2_SHIFT) + +/* System Exception Control Register (software reset) */ + +/* Bit 15: Software reset request */ +#define SYS_SYSECR_RESET (1 << 15) + +#endif /* __ARCH_ARM_SRC_RM57_HARDWARE_RM57_SYS_H */ diff --git a/arch/arm/src/rm57/hardware/rm57_vim.h b/arch/arm/src/rm57/hardware/rm57_vim.h new file mode 100644 index 0000000000000..63144d9f1428b --- /dev/null +++ b/arch/arm/src/rm57/hardware/rm57_vim.h @@ -0,0 +1,213 @@ +/**************************************************************************** + * arch/arm/src/rm57/hardware/rm57_vim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Register layout taken from TI's HALCoGen HL_reg_vim.h for + * RM57L843. Note RM57's VIM register frame (0xfffffd00) is at a + * different address than TMS570LS04x's VIM (0xfffffe00) - do not assume + * parity with the sibling tms570_vim.h. + */ + +#ifndef __ARCH_ARM_SRC_RM57_HARDWARE_RM57_VIM_H +#define __ARCH_ARM_SRC_RM57_HARDWARE_RM57_VIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/rm57l843_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* VIM has 128 total channel slots: one phantom + 127 real channels + * (channel 127 has no dedicated vector, per the HALCoGen s_vim_init table) + */ + +#define VIM_CHANNELS 128 + +/* Helpers for indexing into the 4 groups of 32-bit-per-channel + * registers (FIRQPRn/INTREQn/REQMASKSETn/REQMASKCLRn/WAKEMASKSETn/ + * WAKEMASKCLRn) + */ + +#define VIM_REGNDX(ch) ((ch) >> 5) +#define VIM_REGBIT(ch) ((ch) & 31) + +/* Register Offsets *********************************************************/ + +#define RM57_VIM_ECCSTAT_OFFSET 0x00ec /* ECC Status Register */ +#define RM57_VIM_ECCCTL_OFFSET 0x00f0 /* ECC Control Register */ + +/* Uncorrectable Error Address Register */ +#define RM57_VIM_UERRADDR_OFFSET 0x00f4 + +/* Fall-Back Address Register */ +#define RM57_VIM_FBVECADDR_OFFSET 0x00f8 + +/* Single Bit Error Address Register */ +#define RM57_VIM_SBERRADDR_OFFSET 0x00fc + +/* IRQ Index Offset Vector Register */ +#define RM57_VIM_IRQINDEX_OFFSET 0x0100 + +/* FIQ Index Offset Vector Register */ +#define RM57_VIM_FIQINDEX_OFFSET 0x0104 + +/* FIQ/IRQ Program Register 0 */ +#define RM57_VIM_FIRQPR0_OFFSET 0x0110 + +/* FIQ/IRQ Program Register 1 */ +#define RM57_VIM_FIRQPR1_OFFSET 0x0114 + +/* FIQ/IRQ Program Register 2 */ +#define RM57_VIM_FIRQPR2_OFFSET 0x0118 + +/* FIQ/IRQ Program Register 3 */ +#define RM57_VIM_FIRQPR3_OFFSET 0x011c + +/* Pending Interrupt Read Location Register 0 */ +#define RM57_VIM_INTREQ0_OFFSET 0x0120 + +/* Pending Interrupt Read Location Register 1 */ +#define RM57_VIM_INTREQ1_OFFSET 0x0124 + +/* Pending Interrupt Read Location Register 2 */ +#define RM57_VIM_INTREQ2_OFFSET 0x0128 + +/* Pending Interrupt Read Location Register 3 */ +#define RM57_VIM_INTREQ3_OFFSET 0x012c + +/* Interrupt Enable Set Register 0 */ +#define RM57_VIM_REQMASKSET0_OFFSET 0x0130 + +/* Interrupt Enable Set Register 1 */ +#define RM57_VIM_REQMASKSET1_OFFSET 0x0134 + +/* Interrupt Enable Set Register 2 */ +#define RM57_VIM_REQMASKSET2_OFFSET 0x0138 + +/* Interrupt Enable Set Register 3 */ +#define RM57_VIM_REQMASKSET3_OFFSET 0x013c + +/* Interrupt Enable Clear Register 0 */ +#define RM57_VIM_REQMASKCLR0_OFFSET 0x0140 + +/* Interrupt Enable Clear Register 1 */ +#define RM57_VIM_REQMASKCLR1_OFFSET 0x0144 + +/* Interrupt Enable Clear Register 2 */ +#define RM57_VIM_REQMASKCLR2_OFFSET 0x0148 + +/* Interrupt Enable Clear Register 3 */ +#define RM57_VIM_REQMASKCLR3_OFFSET 0x014c + +/* Wake-up Enable Set Register 0 */ +#define RM57_VIM_WAKEMASKSET0_OFFSET 0x0150 + +/* Wake-up Enable Set Register 1 */ +#define RM57_VIM_WAKEMASKSET1_OFFSET 0x0154 + +/* Wake-up Enable Set Register 2 */ +#define RM57_VIM_WAKEMASKSET2_OFFSET 0x0158 + +/* Wake-up Enable Set Register 3 */ +#define RM57_VIM_WAKEMASKSET3_OFFSET 0x015c + +/* Wake-up Enable Clear Register 0 */ +#define RM57_VIM_WAKEMASKCLR0_OFFSET 0x0160 + +/* Wake-up Enable Clear Register 1 */ +#define RM57_VIM_WAKEMASKCLR1_OFFSET 0x0164 + +/* Wake-up Enable Clear Register 2 */ +#define RM57_VIM_WAKEMASKCLR2_OFFSET 0x0168 + +/* Wake-up Enable Clear Register 3 */ +#define RM57_VIM_WAKEMASKCLR3_OFFSET 0x016c + +/* IRQ Interrupt Vector Register */ +#define RM57_VIM_IRQVECREG_OFFSET 0x0170 + +/* FIQ Interrupt Vector Register */ +#define RM57_VIM_FIQVECREG_OFFSET 0x0174 +#define RM57_VIM_CAPEVT_OFFSET 0x0178 /* Capture Event Register */ + +/* Channel Control Register n/4, n=0..31 */ +#define RM57_VIM_CHANCTRL_OFFSET(n) (0x0180 + (((n) >> 2) << 2)) + +/* Register Addresses *******************************************************/ + +#define RM57_VIM_ECCSTAT (RM57_VIM_BASE + RM57_VIM_ECCSTAT_OFFSET) +#define RM57_VIM_ECCCTL (RM57_VIM_BASE + RM57_VIM_ECCCTL_OFFSET) +#define RM57_VIM_UERRADDR (RM57_VIM_BASE + RM57_VIM_UERRADDR_OFFSET) +#define RM57_VIM_FBVECADDR (RM57_VIM_BASE + RM57_VIM_FBVECADDR_OFFSET) +#define RM57_VIM_SBERRADDR (RM57_VIM_BASE + RM57_VIM_SBERRADDR_OFFSET) +#define RM57_VIM_IRQINDEX (RM57_VIM_BASE + RM57_VIM_IRQINDEX_OFFSET) +#define RM57_VIM_FIQINDEX (RM57_VIM_BASE + RM57_VIM_FIQINDEX_OFFSET) +#define RM57_VIM_FIRQPR0 (RM57_VIM_BASE + RM57_VIM_FIRQPR0_OFFSET) +#define RM57_VIM_FIRQPR1 (RM57_VIM_BASE + RM57_VIM_FIRQPR1_OFFSET) +#define RM57_VIM_FIRQPR2 (RM57_VIM_BASE + RM57_VIM_FIRQPR2_OFFSET) +#define RM57_VIM_FIRQPR3 (RM57_VIM_BASE + RM57_VIM_FIRQPR3_OFFSET) +#define RM57_VIM_INTREQ0 (RM57_VIM_BASE + RM57_VIM_INTREQ0_OFFSET) +#define RM57_VIM_INTREQ1 (RM57_VIM_BASE + RM57_VIM_INTREQ1_OFFSET) +#define RM57_VIM_INTREQ2 (RM57_VIM_BASE + RM57_VIM_INTREQ2_OFFSET) +#define RM57_VIM_INTREQ3 (RM57_VIM_BASE + RM57_VIM_INTREQ3_OFFSET) +#define RM57_VIM_REQMASKSET0 (RM57_VIM_BASE + RM57_VIM_REQMASKSET0_OFFSET) +#define RM57_VIM_REQMASKSET1 (RM57_VIM_BASE + RM57_VIM_REQMASKSET1_OFFSET) +#define RM57_VIM_REQMASKSET2 (RM57_VIM_BASE + RM57_VIM_REQMASKSET2_OFFSET) +#define RM57_VIM_REQMASKSET3 (RM57_VIM_BASE + RM57_VIM_REQMASKSET3_OFFSET) +#define RM57_VIM_REQMASKCLR0 (RM57_VIM_BASE + RM57_VIM_REQMASKCLR0_OFFSET) +#define RM57_VIM_REQMASKCLR1 (RM57_VIM_BASE + RM57_VIM_REQMASKCLR1_OFFSET) +#define RM57_VIM_REQMASKCLR2 (RM57_VIM_BASE + RM57_VIM_REQMASKCLR2_OFFSET) +#define RM57_VIM_REQMASKCLR3 (RM57_VIM_BASE + RM57_VIM_REQMASKCLR3_OFFSET) +#define RM57_VIM_IRQVECREG (RM57_VIM_BASE + RM57_VIM_IRQVECREG_OFFSET) +#define RM57_VIM_FIQVECREG (RM57_VIM_BASE + RM57_VIM_FIQVECREG_OFFSET) +#define RM57_VIM_CAPEVT (RM57_VIM_BASE + RM57_VIM_CAPEVT_OFFSET) +#define RM57_VIM_CHANCTRL(n) (RM57_VIM_BASE + RM57_VIM_CHANCTRL_OFFSET(n)) + +/* Generic register-group accessors, indexed by VIM_REGNDX(channel) */ + +#define RM57_VIM_FIRQPR(n) (RM57_VIM_BASE + 0x0110 + ((n) << 2)) +#define RM57_VIM_REQMASKSET(n) (RM57_VIM_BASE + 0x0130 + ((n) << 2)) +#define RM57_VIM_REQMASKCLR(n) (RM57_VIM_BASE + 0x0140 + ((n) << 2)) + +/* Register Bit-Field Definitions *******************************************/ + +/* ECC Control Register: default HALCoGen init value, Errata VIM#28 + * workaround (disable single-bit correction) + */ + +#define VIM_ECCCTL_INIT (((uint32_t)0xa << 0) | ((uint32_t)0x5 << 16)) + +/* FIQ/IRQ Program Registers: 0 = IRQ, 1 = FIQ (per channel bit) */ + +#define VIM_FIRQPR_IRQ 0 +#define VIM_FIRQPR_FIQ 1 + +/* IRQ/FIQ Index Offset Vector Registers */ + +#define VIM_IRQINDEX_MASK (0x000000ff) +#define VIM_FIQINDEX_MASK (0x000000ff) + +#endif /* __ARCH_ARM_SRC_RM57_HARDWARE_RM57_VIM_H */ diff --git a/arch/arm/src/rm57/hardware/rm57l843_memorymap.h b/arch/arm/src/rm57/hardware/rm57l843_memorymap.h new file mode 100644 index 0000000000000..f1f459786107a --- /dev/null +++ b/arch/arm/src/rm57/hardware/rm57l843_memorymap.h @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/arm/src/rm57/hardware/rm57l843_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Base addresses below are taken directly from TI's HALCoGen-generated + * register headers (HL_reg_*.h) for RM57L843, not assumed from TMS570 + * parity - several peripheral base addresses differ between the two + * Hercules generations (VIM, PCR, and pinmux in particular). + */ + +#ifndef __ARCH_ARM_SRC_RM57_HARDWARE_RM57L843_MEMORYMAP_H +#define __ARCH_ARM_SRC_RM57_HARDWARE_RM57L843_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Memory Map Overview (from HL_sys_link.ld) */ + +/* 0x00000000-0x003fffff: Program FLASH (4MB) */ +#define RM57_FLASH_BASE 0x00000000 + +/* 0x08000000-0x0807ffff: RAM (512KB) */ +#define RM57_RAM_BASE 0x08000000 + +/* Peripheral Control Registers (from HL_reg_*.h) */ + +#define RM57_GIO_BASE 0xfff7bc00 /* GIO (gioREG) */ +#define RM57_GIO_PORTA_BASE 0xfff7bc34 /* GIO Port A (gioPORTA) */ +#define RM57_GIO_PORTB_BASE 0xfff7bc54 /* GIO Port B (gioPORTB) */ +#define RM57_SCI1_BASE 0xfff7e400 /* SCI1/LIN1 (sciREG1) */ +#define RM57_SCI1_PORT_BASE 0xfff7e440 /* SCI1 GIO port (sciPORT1) */ +#define RM57_SCI3_BASE 0xfff7e500 /* SCI3 (sciREG3) */ +#define RM57_SCI3_PORT_BASE 0xfff7e540 /* SCI3 GIO port (sciPORT3) */ +#define RM57_SCI2_BASE 0xfff7e600 /* SCI2 (sciREG2) */ +#define RM57_SCI2_PORT_BASE 0xfff7e640 /* SCI2 GIO port (sciPORT2) */ +#define RM57_SCI4_BASE 0xfff7e700 /* SCI4 (sciREG4) */ +#define RM57_SCI4_PORT_BASE 0xfff7e740 /* SCI4 GIO port (sciPORT4) */ + +/* System Modules Control Registers and Memories */ + +#define RM57_VIMRAM_BASE 0xfff82000 /* VIM RAM (vimRAM) */ +#define RM57_FWRAP_BASE 0xfff87000 /* Flash Wrapper (flashWREG) */ +#define RM57_PCR1_BASE 0xffff1000 /* PCR frame 1 (pcrREG1) */ + +/* Pin Multiplexing (pinMuxReg) */ +#define RM57_PINMUX_BASE 0xffff1c00 +#define RM57_PCR3_BASE 0xfff78000 /* PCR frame 3 (pcrREG3) */ + +/* PCR frame 2, mirrored bus (pcrREG2) */ +#define RM57_PCR2_BASE 0xfcff1000 + +/* System Module - Frame 2 (systemREG2) */ +#define RM57_SYS2_BASE 0xffffe100 +#define RM57_ESM_BASE 0xfffff500 /* ESM (esmREG) */ +#define RM57_RTI1_BASE 0xfffffc00 /* RTI + DWWD (rtiREG1) */ +#define RM57_VIM_BASE 0xfffffd00 /* VIM (vimREG) */ + +/* System Module - Frame 1 (systemREG1) */ +#define RM57_SYS1_BASE 0xffffff00 +#define RM57_ECLK_PORT_BASE 0xffffff04 /* ECLK GIO port (systemPORT) */ + +#endif /* __ARCH_ARM_SRC_RM57_HARDWARE_RM57L843_MEMORYMAP_H */ diff --git a/arch/arm/src/rm57/rm57_boot.c b/arch/arm/src/rm57/rm57_boot.c new file mode 100644 index 0000000000000..b6246605c1adf --- /dev/null +++ b/arch/arm/src/rm57/rm57_boot.c @@ -0,0 +1,192 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "arm.h" +#include "arm_internal.h" +#include "sctlr.h" + +#include "hardware/rm57_sys.h" +#include "rm57_boot.h" +#include "rm57_clockconfig.h" +#include "rm57_esm.h" +#include "rm57_gio.h" +#include "rm57_lowputc.h" +#include "rm57_mpuinit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_ARMV7R_MEMINIT +#error CONFIG_ARMV7R_MEMINIT is required by this architecture. +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_event_export + * + * Description: + * Enable CPU Event Export by setting the X bit in the PMCR. This + * allows the CPU to signal any single-bit or double-bit errors + * detected by its ECC logic for accesses to program flash or data RAM. + * via TMS570's event bus to the ESM (Error Signaling Module). + * + ****************************************************************************/ + +static inline void rm57_event_export(void) +{ + cp15_pmu_pmcr(PMCR_X); +} + +/**************************************************************************** + * Name: rm57_memory_initialize + * + * Description: + * Hardware-initialize (ECC-clear) the on-chip SRAM before .bss/.data + * are written to it. Ported from TI's HALCoGen _memInit_ assembly + * routine (HL_sys_core.s) to C using NuttX register macros. + * + ****************************************************************************/ + +static void rm57_memory_initialize(void) +{ + /* Enable Memory Hardware Initialization */ + + putreg32(SYS_MINITGCR_ENABLE, RM57_SYS_MINITGCR); + + /* Enable Memory Hardware Initialization for main SRAM (bit 0) */ + + putreg32(1, RM57_SYS_MSINENA); + + /* Wait until Memory Hardware Initialization completes */ + + while ((getreg32(RM57_SYS_MSTCGSTAT) & SYS_MSTCGSTAT_MINIDONE) == 0) + { + } + + /* Disable Memory Hardware Initialization */ + + putreg32(SYS_MINITGCR_DISABLE, RM57_SYS_MINITGCR); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_boot + * + * Description: + * Complete boot operations started in arm_head.S + * + * Boot Sequence + * + * 1. The __start entry point in armv7-r/arm_head.S is invoked upon + * power-on reset and prepares the CPU for code execution. + * 2. Because CONFIG_ARMV7R_MEMINIT is set, this function is called + * *before* .bss/.data have been initialized - it must not touch + * any global/static data until arm_data_initialize() has run. + * 3. This function configures clocking, hardware-initializes SRAM + * (clearing ECC), then calls arm_data_initialize(). + * 4. Only after that can the MPU and board-specific bring-up run. + * 5. This function then branches to nx_start() to start the OS. + * + * NOTE: unlike the sibling tms570_boot.c, this function does not perform + * PBIST/self-test - that is not yet implemented for RM57. + * + ****************************************************************************/ + +void arm_boot(void) +{ + /* Zero r0-r12/SPSR in every CPU mode first, before anything else, to + * avoid a lockstep CPU Compare Module (CCM) mismatch between + * RM57L843's two redundant cores (see rm57_coreinit.S). + */ + + rm57_core_init_registers(); + + /* Enable CPU Event Export */ + + rm57_event_export(); + + /* Initialize clocking (PLL, peripheral clocks, flash wait-states) */ + + rm57_clockconfig(); + + /* Put the Error Signaling Module into a known, quiet state (all + * error-pin channels/interrupts disabled, all latched flags + * cleared, nERROR pin released). + */ + + rm57_esm_initialize(); + + /* Hardware-initialize (ECC-clear) SRAM before .bss/.data are touched */ + + rm57_memory_initialize(); + + /* Initialize the FPU (RM57L843 is Cortex-R5F) */ + + arm_fpuconfig(); + + /* Initialize .bss and .data now that SRAM has been initialized */ + + arm_data_initialize(); + + /* Configure the MPU regions (flash, SRAM, peripherals) */ + + rm57_mpu_init(); + + /* Initialize GIO for use by board initialization logic */ + + rm57_gio_initialize(); + + /* Perform board-specific initialization */ + + rm57_board_initialize(); + + /* Bring up the console SCI (RX/TX pin function, baud/format/GCR1). + * This must run before nx_start() - without it the SCI module is left + * in its power-on-reset state (module held in reset, RX/TX pin + * function bits unset) and produces no output even though register + * writes to it "succeed" from software's point of view. + */ + + rm57_lowsetup(); + + /* Then start NuttX */ + + nx_start(); +} diff --git a/arch/arm/src/rm57/rm57_boot.h b/arch/arm/src/rm57/rm57_boot.h new file mode 100644 index 0000000000000..54b88500be548 --- /dev/null +++ b/arch/arm/src/rm57/rm57_boot.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_boot.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RM57_RM57_BOOT_H +#define __ARCH_ARM_SRC_RM57_RM57_BOOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_core_init_registers + * + * Description: + * Zero r0-r12 and clear SPSR in every CPU privilege mode (implemented + * in rm57_coreinit.S). Must be called as the very first thing in + * arm_boot(), before any other code, to avoid a lockstep CPU Compare + * Module (CCM) mismatch between RM57L843's two redundant cores. + * + ****************************************************************************/ + +void rm57_core_init_registers(void); + +/**************************************************************************** + * Name: rm57_board_initialize + * + * Description: + * All RM57 boards must provide the following entry point. This + * function is called from arm_boot() after clocking, memory, and MPU + * have been configured but before any devices have been initialized. + * + ****************************************************************************/ + +void rm57_board_initialize(void); + +#endif /* __ARCH_ARM_SRC_RM57_RM57_BOOT_H */ diff --git a/arch/arm/src/rm57/rm57_clockconfig.c b/arch/arm/src/rm57/rm57_clockconfig.c new file mode 100644 index 0000000000000..7233d36b691c5 --- /dev/null +++ b/arch/arm/src/rm57/rm57_clockconfig.c @@ -0,0 +1,229 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_clockconfig.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Register write sequence ported from TI's HALCoGen-generated + * HL_system.c (setupPLL/periphInit/setupFlash/mapClocks), translated to + * NuttX register-header macros. Board-specific PLL parameters + * (BOARD_PLL_*) come from arch/board/board.h, following the same + * chip/board split tms570_clockconfig.c uses. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" + +#include "hardware/rm57_sys.h" +#include "hardware/rm57_pcr.h" +#include "hardware/rm57_flash.h" +#include "rm57_clockconfig.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_setup_pll + * + * Description: + * Disable PLL1/PLL2, configure their control registers from the board- + * supplied BOARD_PLL_* parameters, then re-enable them. The PLL output + * divider is deliberately left at its maximum (slowest) setting here; + * rm57_map_clocks() switches it to the final board.h value only after + * the PLL has locked. + * + ****************************************************************************/ + +static void rm57_setup_pll(void) +{ + /* Disable PLL1 and PLL2 */ + + putreg32(SYS_CSDIS_CLKSR1OFF | SYS_CSDIS_CLKSR6OFF, RM57_SYS_CSDISSET); + while ((getreg32(RM57_SYS_CSDIS) & + (SYS_CSDIS_CLKSR1OFF | SYS_CSDIS_CLKSR6OFF)) != + (SYS_CSDIS_CLKSR1OFF | SYS_CSDIS_CLKSR6OFF)) + { + } + + /* Clear Global Status Register (oscillator fail / PLL slip flags) */ + + putreg32(0x301, RM57_SYS_GBLSTAT); + + /* PLL1: output divider forced to max until locked, reset-on-osc-fail, + * reference clock divider and multiplier from board.h + */ + + putreg32(SYS_PLLCTL1_PLLDIV_MASK | + SYS_PLLCTL1_REFCLKDIV(BOARD_PLL_NR - 1) | + SYS_PLLCTL1_PLLMUL(BOARD_PLL_PLLMUL), + RM57_SYS_PLLCTL1); + + putreg32(((uint32_t)255 << 22) | ((uint32_t)7 << 12) | + SYS_PLLCTL2_ODPLL(BOARD_PLL_OD - 1) | 61, + RM57_SYS_PLLCTL2); + + /* PLL2: same output-divider-forced-to-max pattern */ + + putreg32(SYS_PLLCTL1_PLLDIV_MASK | + SYS_PLLCTL1_REFCLKDIV(BOARD_PLL_NR - 1) | + SYS_PLLCTL1_PLLMUL(BOARD_PLL_PLLMUL), + RM57_SYS2_PLLCTL3); + + /* Enable PLL1 and PLL2 to start up / lock (also re-enable oscillator + * and the two LPO clock sources, matching the HALCoGen default) + */ + + putreg32(SYS_CSDIS_CLKSR3OFF | SYS_CSDIS_CLKSR7OFF, RM57_SYS_CSDIS); +} + +/**************************************************************************** + * Name: rm57_periph_init + * + * Description: + * Release all peripherals from local reset and enable their clocks. + * + ****************************************************************************/ + +static void rm57_periph_init(void) +{ + uint32_t regval; + + /* Disable peripherals before peripheral power-up */ + + regval = getreg32(RM57_SYS_CLKCNTL); + regval &= ~(1 << 8); + putreg32(regval, RM57_SYS_CLKCNTL); + + /* Power up all peripherals on PCR frame 1 */ + + putreg32(0xffffffff, RM57_PCR1_PSPWRDWNCLR0); + putreg32(0xffffffff, RM57_PCR1_PSPWRDWNCLR1); + putreg32(0xffffffff, RM57_PCR1_PSPWRDWNCLR2); + putreg32(0xffffffff, RM57_PCR1_PSPWRDWNCLR3); + + /* Enable peripherals */ + + regval = getreg32(RM57_SYS_CLKCNTL); + regval |= (1 << 8); + putreg32(regval, RM57_SYS_CLKCNTL); +} + +/**************************************************************************** + * Name: rm57_setup_flash + * + * Description: + * Configure flash read wait-states for the target CPU clock frequency. + * + ****************************************************************************/ + +static void rm57_setup_flash(void) +{ + putreg32(FLASH_FRDCNTL_RWAIT(BOARD_FLASH_RWAIT) | 3, RM57_FLASH_FRDCNTL); +} + +/**************************************************************************** + * Name: rm57_map_clocks + * + * Description: + * Wait for the PLLs to lock, then map GCLK/HCLK/VCLK/RTICLK to their + * final clock sources and switch the PLL output dividers to their + * final (board.h) values. + * + ****************************************************************************/ + +static void rm57_map_clocks(void) +{ + uint32_t csvstat; + uint32_t csdis; + uint32_t regval; + + /* Setup HCLK divider */ + + putreg32(1, RM57_SYS2_HCLKCNTL); + + /* Wait until the enabled clock sources are valid. + * + * Bit 2 of both CSDIS and CSVSTAT is reserved (there is no clock + * source 2) and reads back as 0 on this silicon. Comparing the full + * 0xff byte therefore always requires bit 2 of CSVSTAT to become 1, + * which it never does - confirmed on real hardware via JTAG + * (CSDIS=0x88, CSVSTAT=0xfb read while stuck here: oscillator, PLL1 + * and PLL2 were all already valid, only the reserved-bit compare was + * failing). Mask it out of the comparison. + */ + + do + { + csvstat = getreg32(RM57_SYS_CSVSTAT); + csdis = getreg32(RM57_SYS_CSDIS); + } + while ((csvstat & ((csdis ^ 0xff) & 0xfb)) != ((csdis ^ 0xff) & 0xfb)); + + /* Map GCLK/HCLK/VCLK/VCLK2 to PLL1 */ + + putreg32(SYS_GHVSRC_GHVWAKE(SYS_CLKSRC_PLL1) | + SYS_GHVSRC_HVLPM(SYS_CLKSRC_PLL1) | + SYS_GHVSRC_GHVSRC_SRC(SYS_CLKSRC_PLL1), + RM57_SYS_GHVSRC); + + /* Map RTICLK1 to VCLK */ + + putreg32(SYS_RCLKSRC_RTI1DIV_DIV2 | SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_VCLK), + RM57_SYS_RCLKSRC); + + /* Now that the PLLs are locked, switch the output dividers from their + * max (slow) startup value to the final board.h value + */ + + regval = getreg32(RM57_SYS_PLLCTL1); + regval &= ~SYS_PLLCTL1_PLLDIV_MASK; + regval |= SYS_PLLCTL1_PLLDIV(BOARD_PLL_R - 1); + putreg32(regval, RM57_SYS_PLLCTL1); + + regval = getreg32(RM57_SYS2_PLLCTL3); + regval &= ~SYS_PLLCTL1_PLLDIV_MASK; + regval |= SYS_PLLCTL1_PLLDIV(BOARD_PLL_R - 1); + putreg32(regval, RM57_SYS2_PLLCTL3); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_clockconfig + ****************************************************************************/ + +void rm57_clockconfig(void) +{ + rm57_setup_pll(); + rm57_periph_init(); + rm57_setup_flash(); + rm57_map_clocks(); +} diff --git a/arch/arm/src/rm57/rm57_clockconfig.h b/arch/arm/src/rm57/rm57_clockconfig.h new file mode 100644 index 0000000000000..fe902dd7e6733 --- /dev/null +++ b/arch/arm/src/rm57/rm57_clockconfig.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_clockconfig.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RM57_RM57_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_RM57_RM57_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_clockconfig + * + * Description: + * Called to initialize the RM57L843. This does whatever setup is + * needed to put the SoC in a usable state. This includes the + * initialization of clocking using the settings in board.h, and + * flash read wait-state configuration. + * + ****************************************************************************/ + +void rm57_clockconfig(void); + +#endif /* __ARCH_ARM_SRC_RM57_RM57_CLOCKCONFIG_H */ diff --git a/arch/arm/src/rm57/rm57_coreinit.S b/arch/arm/src/rm57/rm57_coreinit.S new file mode 100644 index 0000000000000..12b07b6bcaced --- /dev/null +++ b/arch/arm/src/rm57/rm57_coreinit.S @@ -0,0 +1,98 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_coreinit.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Ported from TI's HALCoGen _coreInitRegisters_ (HL_sys_core.s), + * which that file documents as required "to avoid CCM Error". RM57L843 + * is a lockstep dual-CPU part: if the two redundant cores' register + * files hold different power-on-reset garbage, the CPU Compare Module + * (CCM) can flag an immediate mismatch and force a hardware reset that + * bypasses all software exception handling - confirmed on real + * hardware as the cause of an early boot reset loop that occurred even + * after the exception vector table itself was fixed (see + * boards/.../scripts/flash-sram.ld and its EXTERN(_vector_start) fix). + * + * Must run as early as possible in boot - called as the first thing + * arm_boot() does, before any C code that could cause the two lockstep + * cores' internal state to diverge. + */ + + .syntax unified + .text + + .global rm57_core_init_registers + .type rm57_core_init_registers, %function + +rm57_core_init_registers: + + mov r0, lr /* Preserve the return address across mode switches */ + + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mrs r1, cpsr + msr spsr_cxsf, r1 + + cps #0x11 /* FIQ mode */ + mov lr, r0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mrs r1, cpsr + msr spsr_cxsf, r1 + + cps #0x12 /* IRQ mode */ + mov lr, r0 + mrs r1, cpsr + msr spsr_cxsf, r1 + + cps #0x17 /* Abort mode */ + mov lr, r0 + mrs r1, cpsr + msr spsr_cxsf, r1 + + cps #0x1b /* Undefined mode */ + mov lr, r0 + mrs r1, cpsr + msr spsr_cxsf, r1 + + cps #0x13 /* Supervisor mode */ + mov lr, r0 + mrs r1, cpsr + msr spsr_cxsf, r1 + + cps #0x1f /* Back to System mode (the caller's mode) */ + mov lr, r0 + bx lr + + .size rm57_core_init_registers, . - rm57_core_init_registers + .end diff --git a/arch/arm/src/rm57/rm57_esm.c b/arch/arm/src/rm57/rm57_esm.c new file mode 100644 index 0000000000000..c78c01a1d61e8 --- /dev/null +++ b/arch/arm/src/rm57/rm57_esm.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_esm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Ported from TI's HALCoGen esmInit() (HL_esm.c). Runs as early + * as possible in boot (right after clock configuration) to put the + * Error Signaling Module into a known, quiet state: all error-pin + * channels disabled, all interrupts disabled, all latched status + * flags cleared, the nERROR pin released, and all interrupt levels + * set to 0 (no channel forces a group2 high-priority response). The + * reference project enables nothing beyond this default-quiet state. + * + * Without this, ESM is left at its power-on-reset configuration for + * the whole early boot sequence, which on this device family is not + * necessarily benign. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "hardware/rm57_esm.h" +#include "rm57_esm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_esm_initialize + ****************************************************************************/ + +void rm57_esm_initialize(void) +{ + /* Disable all error-pin channels and interrupts */ + + putreg32(0xffffffff, RM57_ESM_DEPAPR1); + putreg32(0xffffffff, RM57_ESM_IEPCR4); + putreg32(0xffffffff, RM57_ESM_IEPCR7); + + putreg32(0xffffffff, RM57_ESM_IECR1); + putreg32(0xffffffff, RM57_ESM_IECR4); + putreg32(0xffffffff, RM57_ESM_IECR7); + + /* Clear all latched error status flags */ + + putreg32(0xffffffff, RM57_ESM_SR1(0)); + putreg32(0xffffffff, RM57_ESM_SR1(1)); + putreg32(0xffffffff, RM57_ESM_SSR2); + putreg32(0xffffffff, RM57_ESM_SR1(2)); + + putreg32(0xffffffff, RM57_ESM_SR4(0)); + putreg32(0xffffffff, RM57_ESM_SR7(0)); + + /* Low-pulse counter preload (matches HALCoGen default) */ + + putreg32(16384 - 1, RM57_ESM_LTCPR); + + /* Release the nERROR pin */ + + if (getreg32(RM57_ESM_EPSR) == 0) + { + putreg32(0x00000005, RM57_ESM_EKR); + } + else + { + putreg32(0x00000000, RM57_ESM_EKR); + } + + /* Clear then zero all interrupt levels (no channel forces the + * group2 high-priority response) + */ + + putreg32(0xffffffff, RM57_ESM_ILCR1); + putreg32(0xffffffff, RM57_ESM_ILCR4); + putreg32(0xffffffff, RM57_ESM_ILCR7); + + putreg32(0, RM57_ESM_ILSR1); + putreg32(0, RM57_ESM_ILSR4); + putreg32(0, RM57_ESM_ILSR7); + + /* Leave all error-pin channels and interrupts disabled (EEPAPR1 / + * IEPSR4 / IEPSR7 left at 0) - matches the reference project, which + * does not arm any ESM-driven response beyond this quiet default. + */ +} diff --git a/arch/arm/src/rm57/rm57_esm.h b/arch/arm/src/rm57/rm57_esm.h new file mode 100644 index 0000000000000..8dc8201949ce4 --- /dev/null +++ b/arch/arm/src/rm57/rm57_esm.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_esm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RM57_RM57_ESM_H +#define __ARCH_ARM_SRC_RM57_RM57_ESM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_esm_initialize + * + * Description: + * Put the Error Signaling Module into a known, quiet state early in + * boot: all error-pin channels and interrupts disabled, all latched + * status flags cleared, the nERROR pin released. + * + ****************************************************************************/ + +void rm57_esm_initialize(void); + +#endif /* __ARCH_ARM_SRC_RM57_RM57_ESM_H */ diff --git a/arch/arm/src/rm57/rm57_gio.c b/arch/arm/src/rm57/rm57_gio.c new file mode 100644 index 0000000000000..8da7322ea2928 --- /dev/null +++ b/arch/arm/src/rm57/rm57_gio.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_gio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Adapted from tms570_gio.c, using RM57's 2-port GIO register layout. */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/rm57_gio.h" +#include "rm57_gio.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_gio_initialize + * + * Description: + * Take the GIO block out of reset and assure that it is ready for use. + * + ****************************************************************************/ + +int rm57_gio_initialize(void) +{ + /* Take the GIO block out of reset */ + + putreg32(GIO_GCR0_RESET, RM57_GIO_GCR0); + + /* Disable all pin interrupts. Make sure they are all level 0. */ + + putreg32(0xffffffff, RM57_GIO_ENACLR); + putreg32(0xffffffff, RM57_GIO_LVLCLR); + return OK; +} + +/**************************************************************************** + * Name: rm57_configgio + * + * Description: + * Configure a GIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int rm57_configgio(gio_pinset_t cfgset) +{ + uint32_t port = rm57_gio_port(cfgset); + uintptr_t base = rm57_gio_base(cfgset); + uint32_t pin = rm57_gio_pin(cfgset); + uint32_t pinmask = rm57_gio_pinmask(cfgset); + uint32_t regval; + irqstate_t flags; + + /* Disable interrupts to prohibit re-entrance. */ + + flags = enter_critical_section(); + + /* Force the pin to be an input for now */ + + regval = getreg32(base + RM57_GIO_DIR_OFFSET); + regval &= ~pinmask; + putreg32(regval, base + RM57_GIO_DIR_OFFSET); + + /* Disable interrupts on the pin. Make sure this is a level 0 pin. */ + + putreg32(GIO_ENACLR_PORT_PIN(port, pin), RM57_GIO_ENACLR); + putreg32(GIO_LVLCLR_PORT_PIN(port, pin), RM57_GIO_LVLCLR); + + /* Enable/disable the pull-up/down as requested */ + + switch (cfgset & GIO_CFG_MASK) + { + case GIO_CFG_DEFAULT: /* Default, no attribute */ + default: + { + /* Disable pull functionality */ + + regval = getreg32(base + RM57_GIO_PULDIS_OFFSET); + regval &= ~pinmask; + putreg32(regval, base + RM57_GIO_PULDIS_OFFSET); + } + break; + + case GIO_CFG_PULLUP: /* Internal pull-up */ + { + /* Select pull-up */ + + regval = getreg32(base + RM57_GIO_PSL_OFFSET); + regval |= pinmask; + putreg32(regval, base + RM57_GIO_PSL_OFFSET); + + /* Enable pull functionality */ + + regval = getreg32(base + RM57_GIO_PULDIS_OFFSET); + regval |= pinmask; + putreg32(regval, base + RM57_GIO_PULDIS_OFFSET); + } + break; + + case GIO_CFG_PULLDOWN: /* Internal pull-down */ + { + /* Select pull-down */ + + regval = getreg32(base + RM57_GIO_PSL_OFFSET); + regval |= pinmask; + putreg32(regval, base + RM57_GIO_PSL_OFFSET); + + /* Enable pull functionality */ + + regval = getreg32(base + RM57_GIO_PULDIS_OFFSET); + regval |= pinmask; + putreg32(regval, base + RM57_GIO_PULDIS_OFFSET); + } + break; + } + + /* Then do unique operations for an output pin */ + + if ((cfgset & GIO_MODE_MASK) == GIO_OUTPUT) + { + /* Enable the open drain driver if requested */ + + regval = getreg32(base + RM57_GIO_PDR_OFFSET); + if ((cfgset & GIO_OPENDRAIN) != 0) + { + regval |= pinmask; + } + else + { + regval &= ~pinmask; + } + + putreg32(regval, base + RM57_GIO_PDR_OFFSET); + + /* Set default output value */ + + if ((cfgset & GIO_OUTPUT_SET) != 0) + { + putreg32(pinmask, base + RM57_GIO_DSET_OFFSET); + } + else + { + putreg32(pinmask, base + RM57_GIO_DCLR_OFFSET); + } + + /* Finally, configure the pin as an output */ + + regval = getreg32(base + RM57_GIO_DIR_OFFSET); + regval |= pinmask; + putreg32(regval, base + RM57_GIO_DIR_OFFSET); + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: rm57_giowrite + * + * Description: + * Write one or zero to the selected GIO pin + * + ****************************************************************************/ + +void rm57_giowrite(gio_pinset_t pinset, bool value) +{ + uintptr_t base = rm57_gio_base(pinset); + uint32_t pinmask = rm57_gio_pinmask(pinset); + + if (value) + { + putreg32(pinmask, base + RM57_GIO_DSET_OFFSET); + } + else + { + putreg32(pinmask, base + RM57_GIO_DCLR_OFFSET); + } +} + +/**************************************************************************** + * Name: rm57_gioread + * + * Description: + * Read one or zero from the selected GIO pin + * + ****************************************************************************/ + +bool rm57_gioread(gio_pinset_t pinset) +{ + uintptr_t base = rm57_gio_base(pinset); + uint32_t pinmask = rm57_gio_pinmask(pinset); + uint32_t regval; + + if ((pinset & GIO_MODE_MASK) == GIO_OUTPUT) + { + regval = getreg32(base + RM57_GIO_DOUT_OFFSET); + } + else + { + regval = getreg32(base + RM57_GIO_DIN_OFFSET); + } + + return (regval & pinmask) != 0; +} diff --git a/arch/arm/src/rm57/rm57_gio.h b/arch/arm/src/rm57/rm57_gio.h new file mode 100644 index 0000000000000..d079efb6422e0 --- /dev/null +++ b/arch/arm/src/rm57/rm57_gio.h @@ -0,0 +1,199 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_gio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Adapted from tms570_gio.h. RM57L843 only has 2 GIO ports (A, B) vs. + * TMS570's up to 8; the pin-encoding bit layout is otherwise identical + * Hercules GIO IP. + */ + +#ifndef __ARCH_ARM_SRC_RM57_RM57_GIO_H +#define __ARCH_ARM_SRC_RM57_RM57_GIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "hardware/rm57_gio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Bit-encoded input to rm57_configgio() ************************************/ + +/* 16-bit Encoding: + * + * .... .... M.CC IIOV PPP. .BBB + */ + +/* Input/Output mode: .... .... M... .... .... .... */ + +#define GIO_MODE_SHIFT (15) /* Bit 15: GIO mode */ +#define GIO_MODE_MASK (1 << GIO_MODE_SHIFT) +# define GIO_INPUT (0 << GIO_MODE_SHIFT) /* GIO Input */ +# define GIO_OUTPUT (1 << GIO_MODE_SHIFT) /* GIO Output */ + +/* Pin configuration bits (pull-up/down): .... .... ..CC .... .... .... */ + +#define GIO_CFG_SHIFT (12) /* Bits 12-14: GIO configuration bits */ +#define GIO_CFG_MASK (3 << GIO_CFG_SHIFT) +# define GIO_CFG_DEFAULT (0 << GIO_CFG_SHIFT) /* Default, no attribute */ +# define GIO_CFG_PULLUP (1 << GIO_CFG_SHIFT) /* Internal pull-up */ +# define GIO_CFG_PULLDOWN (2 << GIO_CFG_SHIFT) /* Internal pull-down */ + +/* Interrupt modes: .... .... .... II.. .... .... */ + +#define GIO_INT_SHIFT (10) /* Bits 10-11: GIO interrupt bits */ +#define GIO_INT_MASK (3 << GIO_INT_SHIFT) +# define GIO_INT_NONE (0 << GIO_INT_SHIFT) +# define GIO_INT_RISING (1 << GIO_INT_SHIFT) +# define GIO_INT_FALLING (2 << GIO_INT_SHIFT) +# define GIO_INT_BOTHEDGES (3 << GIO_INT_SHIFT) + +/* Open drain select (output only): .... .... .... ..O. .... .... */ + +#define GIO_OPENDRAIN (1 << 9) /* Bit 9: Open drain mode */ + +/* Initial output value (output only): .... .... .... ...V .... .... */ + +#define GIO_OUTPUT_SET (1 << 8) /* Bit 8: Initial value of output */ +#define GIO_OUTPUT_CLEAR (0) + +/* GIO port: .... .... .... .... PPP. .... */ + +#define GIO_PORT_SHIFT (5) /* Bit 5-7: Port number */ +#define GIO_PORT_MASK (7 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOA (0 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOB (1 << GIO_PORT_SHIFT) + +/* GIO pin: .... .... .... .... .... .BBB */ + +#define GIO_PIN_SHIFT (0) /* Bits 0-2: GIO number: 0-7 */ +#define GIO_PIN_MASK (7 << GIO_PIN_SHIFT) +# define GIO_PIN0 (0 << GIO_PIN_SHIFT) +# define GIO_PIN1 (1 << GIO_PIN_SHIFT) +# define GIO_PIN2 (2 << GIO_PIN_SHIFT) +# define GIO_PIN3 (3 << GIO_PIN_SHIFT) +# define GIO_PIN4 (4 << GIO_PIN_SHIFT) +# define GIO_PIN5 (5 << GIO_PIN_SHIFT) +# define GIO_PIN6 (6 << GIO_PIN_SHIFT) +# define GIO_PIN7 (7 << GIO_PIN_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +typedef uint16_t gio_pinset_t; + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +static inline uintptr_t rm57_gio_base(gio_pinset_t cfgset) +{ + int port = (cfgset & GIO_PORT_MASK) >> GIO_PORT_SHIFT; + return RM57_GIO_PORTBASE(port); +} + +static inline int rm57_gio_port(gio_pinset_t cfgset) +{ + return (cfgset & GIO_PORT_MASK) >> GIO_PORT_SHIFT; +} + +static inline int rm57_gio_pin(gio_pinset_t cfgset) +{ + return (cfgset & GIO_PIN_MASK) >> GIO_PIN_SHIFT; +} + +static inline int rm57_gio_pinmask(gio_pinset_t cfgset) +{ + return 1 << ((cfgset & GIO_PIN_MASK) >> GIO_PIN_SHIFT); +} + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_gio_initialize + * + * Description: + * Take the GIO block out of reset and assure that it is ready for use. + * + ****************************************************************************/ + +int rm57_gio_initialize(void); + +/**************************************************************************** + * Name: rm57_configgio + * + * Description: + * Configure a GIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int rm57_configgio(gio_pinset_t cfgset); + +/**************************************************************************** + * Name: rm57_giowrite + * + * Description: + * Write one or zero to the selected GIO pin + * + ****************************************************************************/ + +void rm57_giowrite(gio_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: rm57_gioread + * + * Description: + * Read one or zero from the selected GIO pin + * + ****************************************************************************/ + +bool rm57_gioread(gio_pinset_t pinset); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_RM57_RM57_GIO_H */ diff --git a/arch/arm/src/rm57/rm57_irq.c b/arch/arm/src/rm57/rm57_irq.c new file mode 100644 index 0000000000000..dbfff651d1142 --- /dev/null +++ b/arch/arm/src/rm57/rm57_irq.c @@ -0,0 +1,296 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_irq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Adapted from tms570_irq.c, but using the RM57L843 VIM register layout + * (see hardware/rm57_vim.h), which differs from TMS570's VIM/VIM-Parity + * split (RM57's VIM has 4 groups of 32 channels plus on-chip ECC + * registers, not present on TMS570LS04x). + * + * ESM (Error Signaling Module) interrupt attach/enable is deferred along + * with the rest of ESM support. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/rm57l843_memorymap.h" +#include "hardware/rm57_vim.h" +#include "rm57_irq.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_error_handler + ****************************************************************************/ + +static void rm57_error_handler(void) +{ + PANIC(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + * + * Description: + * Only the indexed interrupt mode is supported here: after the CPU + * takes an IRQ/FIQ exception, it branches to the vector at 0x18/0x1c. + * The main handler reads the IRQINDEX/FIQINDEX register to determine + * which channel fired. See tms570_irq.c for a more detailed + * description of the VIM's three interrupt handling modes; only mode + * 1 (indexed) is used here, matching the sibling TMS570 port. + * + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uintptr_t *vimram; + int i; + + /* Initialize VIM RAM vectors with a default error handler. These + * vectors are not used by the indexed-mode interrupt handling below, + * but are populated as a safety net for the fall-back vector logic. + */ + + vimram = (uintptr_t *)RM57_VIMRAM_BASE; + for (i = 0; i < (RM57_IRQ_NCHANNELS + 1); i++) + { + *vimram++ = (uintptr_t)rm57_error_handler; + } + + putreg32((uint32_t)rm57_error_handler, RM57_VIM_FBVECADDR); + + /* Assign all channels to IRQ (not FIQ) */ + + putreg32(0, RM57_VIM_FIRQPR0); + putreg32(0, RM57_VIM_FIRQPR1); + putreg32(0, RM57_VIM_FIRQPR2); + putreg32(0, RM57_VIM_FIRQPR3); + + /* Disable all interrupts (channels 0/1 - ESM high / phantom - are left + * alone, matching TMS570's convention of never disabling channel 0/1 + * through the mask registers) + */ + + putreg32(0xfffffffc, RM57_VIM_REQMASKCLR0); + putreg32(0xffffffff, RM57_VIM_REQMASKCLR1); + putreg32(0xffffffff, RM57_VIM_REQMASKCLR2); + putreg32(0xffffffff, RM57_VIM_REQMASKCLR3); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And finally, enable interrupts globally */ + + arm_color_intstack(); + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: arm_decodeirq + * + * Description: + * This function is called from the IRQ vector handler in arm_vectors.S. + * At this point, the interrupt has been taken and the registers have + * been saved on the stack. This function simply needs to determine + * the irq number of the interrupt and then to call arm_doirq to + * dispatch the interrupt. + * + ****************************************************************************/ + +uint32_t *arm_decodeirq(uint32_t *regs) +{ + int vector; + + /* Get the interrupting vector number from the IRQINDEX register. Zero, + * the "phantom" vector, is returned when no channel is pending. + */ + + vector = getreg32(RM57_VIM_IRQINDEX) & VIM_IRQINDEX_MASK; + if (vector > 0) + { + /* Dispatch the interrupt. NOTE that the IRQ number is the vector + * number offset by one to skip over the "phantom" vector. + */ + + regs = arm_doirq(vector - 1, regs); + } + + return regs; +} + +/**************************************************************************** + * Name: arm_decodefiq + * + * Description: + * This function is called from the FIQ vector handler in arm_vectors.S. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7R_HAVE_DECODEFIQ +uint32_t *arm_decodefiq(uint32_t *regs) +{ + int vector; + + vector = getreg32(RM57_VIM_FIQINDEX) & VIM_FIQINDEX_MASK; + if (vector > 0) + { + regs = arm_doirq(vector - 1, regs); + } + + return regs; +} +#endif + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ or FIQ specified by 'channel' + * + ****************************************************************************/ + +void up_disable_irq(int channel) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bitmask; + unsigned int regndx; + + DEBUGASSERT(channel >= 0 && channel < RM57_IRQ_NCHANNELS); + + regndx = VIM_REGNDX(channel); + channel = VIM_REGBIT(channel); + bitmask = (1 << channel); + + /* Disable the IRQ/FIQ by setting the corresponding REQMASKCLR bit. */ + + regaddr = RM57_VIM_REQMASKCLR(regndx); + regval = getreg32(regaddr); + regval |= bitmask; + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'channel' + * + ****************************************************************************/ + +void up_enable_irq(int channel) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bitmask; + unsigned int regndx; + + DEBUGASSERT(channel >= 0 && channel < RM57_IRQ_NCHANNELS); + + regndx = VIM_REGNDX(channel); + channel = VIM_REGBIT(channel); + bitmask = (1 << channel); + +#ifdef CONFIG_ARMV7R_HAVE_DECODEFIQ + /* Select IRQ (vs FIQ) by clearing the corresponding FIRQPR bit */ + + regaddr = RM57_VIM_FIRQPR(regndx); + regval = getreg32(regaddr); + regval &= ~bitmask; + putreg32(regval, regaddr); +#endif + + /* Enable the IRQ by setting the corresponding REQMASKSET bit. */ + + regaddr = RM57_VIM_REQMASKSET(regndx); + regval = getreg32(regaddr); + regval |= bitmask; + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: up_enable_fiq + * + * Description: + * Enable the FIQ specified by 'channel' + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7R_HAVE_DECODEFIQ +void up_enable_fiq(int channel) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bitmask; + unsigned int regndx; + + DEBUGASSERT(channel >= 0 && channel < RM57_IRQ_NCHANNELS); + + regndx = VIM_REGNDX(channel); + channel = VIM_REGBIT(channel); + bitmask = (1 << channel); + + /* Select FIQ (vs IRQ) by setting the corresponding FIRQPR bit */ + + regaddr = RM57_VIM_FIRQPR(regndx); + regval = getreg32(regaddr); + regval |= bitmask; + putreg32(regval, regaddr); + + /* Enable the FIQ by setting the corresponding REQMASKSET bit. */ + + regaddr = RM57_VIM_REQMASKSET(regndx); + regval = getreg32(regaddr); + regval |= bitmask; + putreg32(regval, regaddr); +} +#endif + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ +} diff --git a/arch/arm/src/rm57/rm57_irq.h b/arch/arm/src/rm57/rm57_irq.h new file mode 100644 index 0000000000000..f79f4732382fc --- /dev/null +++ b/arch/arm/src/rm57/rm57_irq.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RM57_RM57_IRQ_H +#define __ARCH_ARM_SRC_RM57_RM57_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: up_enable_fiq + * + * Description: + * Enable the FIQ specified by 'channel' + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7R_HAVE_DECODEFIQ +void up_enable_fiq(int channel); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_RM57_RM57_IRQ_H */ diff --git a/arch/arm/src/rm57/rm57_lowputc.c b/arch/arm/src/rm57/rm57_lowputc.c new file mode 100644 index 0000000000000..f63e62bf869c0 --- /dev/null +++ b/arch/arm/src/rm57/rm57_lowputc.c @@ -0,0 +1,278 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_lowputc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Adapted from tms570_lowputc.c, using RM57's SCI register layout + * (hardware/rm57_sci.h). Only SCI1 is currently supported. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/rm57_sci.h" +#include "rm57_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select SCI parameters for the selected console */ + +#if defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_RM57_SCI1) +# define RM57_CONSOLE_BASE RM57_SCI1_BASE +# define RM57_CONSOLE_BAUD CONFIG_SCI1_BAUD +# define RM57_CONSOLE_BITS 8 +# define RM57_CONSOLE_PARITY 0 +# define RM57_CONSOLE_2STOP CONFIG_SCI1_2STOP +# define HAVE_SERIAL_CONSOLE 1 +#else +# error "No CONFIG_SCIn_SERIAL_CONSOLE Setting" +# undef HAVE_SERIAL_CONSOLE +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_rm57_lowputc_lock = SP_UNLOCKED; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef HAVE_SERIAL_CONSOLE +static const struct sci_config_s g_console_config = +{ + .baud = RM57_CONSOLE_BAUD, + .parity = RM57_CONSOLE_PARITY, + .bits = RM57_CONSOLE_BITS, + .stopbits2 = RM57_CONSOLE_2STOP, +}; +#endif /* HAVE_SERIAL_CONSOLE */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_sci_initialize + * + * Description: + * Perform one-time initialization of an SCI module: bring it out of + * reset and configure its RX/TX pins. + * + ****************************************************************************/ + +static void rm57_sci_initialize(uint32_t base) +{ + /* Bring the SCI out of reset */ + + putreg32(0x0, base + RM57_SCI_GCR0_OFFSET); + putreg32(SCI_GCR0_RESET, base + RM57_SCI_GCR0_OFFSET); + + /* Pin Function Register: RX is receive pin, TX is transmit pin */ + + putreg32(SCI_PIO_RX | SCI_PIO_TX, base + RM57_SCI_PIO0_OFFSET); + + /* Pin Direction Register: general purpose inputs (irrelevant, TX/RX + * function bits above take priority) + */ + + putreg32(0, base + RM57_SCI_PIO1_OFFSET); + + /* Pin Open Drain Output Enable Register: disabled */ + + putreg32(0, base + RM57_SCI_PIO6_OFFSET); + + /* Pin Pullup/Pulldown Disable Register: pull control enabled */ + + putreg32(0, base + RM57_SCI_PIO7_OFFSET); + + /* Pin Pullup/Pulldown Selection Register: pulled up */ + + putreg32(SCI_PIO_RX | SCI_PIO_TX, base + RM57_SCI_PIO8_OFFSET); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + irqstate_t flags; + + /* Wait for the transmitter to be available */ + + flags = spin_lock_irqsave(&g_rm57_lowputc_lock); + + while ((getreg32(RM57_CONSOLE_BASE + RM57_SCI_FLR_OFFSET) & + SCI_FLR_TXRDY) == 0) + { + } + + /* Send the character */ + + putreg32((uint32_t)ch, RM57_CONSOLE_BASE + RM57_SCI_TD_OFFSET); + + spin_unlock_irqrestore(&g_rm57_lowputc_lock, flags); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + arm_lowputc(ch); +#endif +} + +/**************************************************************************** + * Name: rm57_lowsetup + * + * Description: + * This performs basic initialization of the SCI used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void rm57_lowsetup(void) +{ +#ifdef CONFIG_RM57_SCI1 + rm57_sci_initialize(RM57_SCI1_BASE); +#endif + +#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_SCI_CONFIG) + /* Configure the console (only) */ + + rm57_sci_configure(RM57_CONSOLE_BASE, &g_console_config); +#endif +} + +/**************************************************************************** + * Name: rm57_sci_configure + * + * Description: + * Configure an SCI for non-interrupt driven operation + * + ****************************************************************************/ + +int rm57_sci_configure(uint32_t base, const struct sci_config_s *config) +{ + float divb7; + uint32_t intpart; + uint32_t p; + uint32_t regval; + uint32_t gcr1; + uint32_t nbits; + + /* Pre-calculate the baud-rate divisor (integer part only - see note + * below). The input clock to the baud rate generator is VCLK (asynchronous + * timing). + */ + + divb7 = (float)BOARD_VCLK_FREQUENCY / (config->baud * 16); + intpart = (uint32_t)divb7; + + /* Disable all interrupts */ + + putreg32(SCI_INT_ALLINTS, base + RM57_SCI_CLEARINT_OFFSET); + putreg32(SCI_INT_ALLINTS, base + RM57_SCI_CLEARINTLVL_OFFSET); + + /* Global Control 1: async timing, internal clock, parity/stop-bits per + * config, receiver+transmitter enabled + */ + + gcr1 = SCI_GCR1_TIMING_MODE | SCI_GCR1_CLOCK | + SCI_GCR1_RXENA | SCI_GCR1_TXENA; + + DEBUGASSERT(config->parity <= 2); + if (config->parity == 1) + { + gcr1 |= SCI_GCR1_PARITY_ENA; + } + else if (config->parity == 2) + { + gcr1 |= (SCI_GCR1_PARITY_ENA | SCI_GCR1_PARITY); + } + + if (config->stopbits2) + { + gcr1 |= SCI_GCR1_STOP; + } + + putreg32(gcr1, base + RM57_SCI_GCR1_OFFSET); + + /* Baud rate divisor. Only the integer P divisor is used (M=0), matching + * TI's HALCoGen-generated sciInit() (HL_sci.c) for this SCI IP, e.g. + * BRS=487 for a 9600 target at BOARD_VCLK_FREQUENCY yields the + * documented 9606 actual baud. A fractional M term should not be added + * without validating it against real hardware first. + */ + + p = intpart - 1; + + regval = SCI_BRS_P(p); + putreg32(regval, base + RM57_SCI_BRS_OFFSET); + + /* Transmission length */ + + nbits = config->bits; + DEBUGASSERT(nbits >= 1 && nbits <= 8); + + regval = SCI_FORMAT_CHAR(nbits - 1); + putreg32(regval, base + RM57_SCI_FORMAT_OFFSET); + + /* Put the SCI in its operational state */ + + gcr1 |= SCI_GCR1_SWRST; + putreg32(gcr1, base + RM57_SCI_GCR1_OFFSET); + return OK; +} diff --git a/arch/arm/src/rm57/rm57_lowputc.h b/arch/arm/src/rm57/rm57_lowputc.h new file mode 100644 index 0000000000000..573c8b67cc594 --- /dev/null +++ b/arch/arm/src/rm57/rm57_lowputc.h @@ -0,0 +1,99 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_lowputc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RM57_RM57_LOWPUTC_H +#define __ARCH_ARM_SRC_RM57_RM57_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This structure describes the configuration of an SCI UART */ + +struct sci_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits + * instead of 1 */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: rm57_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console SCI. This is done + * early so that the serial console is available for debugging very + * early in the boot sequence. + * + ****************************************************************************/ + +void rm57_lowsetup(void); + +/**************************************************************************** + * Name: rm57_sci_configure + * + * Description: + * Configure an SCI for non-interrupt driven operation + * + ****************************************************************************/ + +int rm57_sci_configure(uint32_t base, const struct sci_config_s *config); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_RM57_RM57_LOWPUTC_H */ diff --git a/arch/arm/src/rm57/rm57_mpuinit.c b/arch/arm/src/rm57/rm57_mpuinit.c new file mode 100644 index 0000000000000..ec4dcffb04661 --- /dev/null +++ b/arch/arm/src/rm57/rm57_mpuinit.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_mpuinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "rm57_mpuinit.h" +#include "mpu.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_mpu_reset + * + * Description: + * Reset all MPU regions by disabling each region. + * + ****************************************************************************/ + +static void rm57_mpu_reset(void) +{ + int i; + + for (i = 0; i < CONFIG_ARM_MPU_NREGIONS; i++) + { + mpu_set_rgnr(i); + mpu_set_drbar(0); + mpu_set_drsr(0); + mpu_set_dracr(0); + } +} + +/**************************************************************************** + * Name: rm57_mpu_init + * + * Description: + * Initialize the MPU by disabling it, resetting all regions, configuring + * the flash/SRAM/peripheral regions, and then re-enabling the MPU. + * + ****************************************************************************/ + +void rm57_mpu_init(void) +{ + mpu_control(false); + + rm57_mpu_reset(); + + rm57_flash_region(RM57_FLASH_BASE, RM57_PFLASH); + rm57_sram_region(RM57_RAM_BASE, RM57_SRAM); + rm57_periph_region(RM57_PERIPH_START_ADDR, RM57_PERIPH_SIZE); + + mpu_control(true); +} diff --git a/arch/arm/src/rm57/rm57_mpuinit.h b/arch/arm/src/rm57/rm57_mpuinit.h new file mode 100644 index 0000000000000..461945938191c --- /dev/null +++ b/arch/arm/src/rm57/rm57_mpuinit.h @@ -0,0 +1,98 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_mpuinit.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RM57_RM57_MPUINIT_H +#define __ARCH_ARM_SRC_RM57_RM57_MPUINIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "mpu.h" +#include "hardware/rm57l843_memorymap.h" +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RM57_NUM_OF_MPU_REGION (3) + +/* Peripheral register region: covers the 0xf0000000-0xffffffff span, + * which contains all peripheral bases used by this port (GIO, SCI, VIM, + * ESM, PCR, RTI, SYS, flash wrapper, pinmux - see + * hardware/rm57l843_memorymap.h). Not cacheable, not executable. + */ + +#define RM57_PERIPH_START_ADDR (0xf0000000) +#define RM57_PERIPH_SIZE (0x10000000ul) + +/* FLASH REGION + * Cacheable, bufferable, executable + */ + +#define rm57_flash_region(base, size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_C | \ + MPU_RACR_B | \ + MPU_RACR_AP_RWRW) + +/* SRAM REGION + * Cacheable, bufferable, executable + */ + +#define rm57_sram_region(base, size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_C | \ + MPU_RACR_B | \ + MPU_RACR_AP_RWRW) + +/* PERIPHERAL REGION + * Not cacheable, not bufferable, shareable (device memory), execute + * never + */ + +#define rm57_periph_region(base, size) \ + mpu_configure_region(base, size, MPU_RACR_S | \ + MPU_RACR_AP_RWRW | \ + MPU_RACR_XN) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_mpu_init + * + * Description: + * Initialize the MPU by disabling it, resetting all regions, configuring + * the flash/SRAM/peripheral regions, and then re-enabling the MPU. + * + ****************************************************************************/ + +void rm57_mpu_init(void); + +#endif /* __ARCH_ARM_SRC_RM57_RM57_MPUINIT_H */ diff --git a/arch/arm/src/rm57/rm57_serial.c b/arch/arm/src/rm57/rm57_serial.c new file mode 100644 index 0000000000000..2247541eb6616 --- /dev/null +++ b/arch/arm/src/rm57/rm57_serial.c @@ -0,0 +1,688 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_serial.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Adapted from tms570_serial.c, using RM57's SCI register layout. Only + * SCI1/LIN1 is currently supported. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/rm57_sci.h" +#include "rm57_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef USE_SERIALDRIVER + +/* Which SCI will be tty0/console? */ + +#if defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_RM57_SCI1) +# define CONSOLE_DEV g_sci1port /* SCI1 is console */ +# define TTYS0_DEV g_sci1port /* SCI1 is ttyS0 */ +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_RM57_SCI1) +# define TTYS0_DEV g_sci1port /* SCI1 is ttyS0 */ +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rm57_dev_s +{ + const uint32_t scibase; /* Base address of SCI registers */ + struct sci_config_s config; /* SCI configuration */ + uint8_t irq; /* IRQ associated with this SCI */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int rm57_setup(struct uart_dev_s *dev); +static void rm57_shutdown(struct uart_dev_s *dev); +static int rm57_attach(struct uart_dev_s *dev); +static void rm57_detach(struct uart_dev_s *dev); +static int rm57_interrupt(int irq, void *context, void *arg); +static int rm57_ioctl(struct file *filep, int cmd, unsigned long arg); +static int rm57_receive(struct uart_dev_s *dev, unsigned int *status); +static void rm57_rxint(struct uart_dev_s *dev, bool enable); +static bool rm57_rxavailable(struct uart_dev_s *dev); +static void rm57_send(struct uart_dev_s *dev, int ch); +static void rm57_txint(struct uart_dev_s *dev, bool enable); +static bool rm57_txready(struct uart_dev_s *dev); +static bool rm57_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_sci_ops = +{ + .setup = rm57_setup, + .shutdown = rm57_shutdown, + .attach = rm57_attach, + .detach = rm57_detach, + .ioctl = rm57_ioctl, + .receive = rm57_receive, + .rxint = rm57_rxint, + .rxavailable = rm57_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = rm57_send, + .txint = rm57_txint, + .txready = rm57_txready, + .txempty = rm57_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_RM57_SCI1 +static char g_sci1rxbuffer[CONFIG_SCI1_RXBUFSIZE]; +static char g_sci1txbuffer[CONFIG_SCI1_TXBUFSIZE]; +#endif + +/* This describes the state of the SCI1 port. */ + +#ifdef CONFIG_RM57_SCI1 +static struct rm57_dev_s g_sci1priv = +{ + .scibase = RM57_SCI1_BASE, + .config = + { + .baud = CONFIG_SCI1_BAUD, + .parity = 0, + .bits = 8, + .stopbits2 = CONFIG_SCI1_2STOP, + }, + .irq = RM57_REQ_LIN1HIGH, +}; + +static uart_dev_t g_sci1port = +{ + .recv = + { + .size = CONFIG_SCI1_RXBUFSIZE, + .buffer = g_sci1rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI1_TXBUFSIZE, + .buffer = g_sci1txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci1priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_serialin + ****************************************************************************/ + +static inline uint32_t rm57_serialin(struct rm57_dev_s *priv, int offset) +{ + return getreg32(priv->scibase + offset); +} + +/**************************************************************************** + * Name: rm57_serialout + ****************************************************************************/ + +static inline void rm57_serialout(struct rm57_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->scibase + offset); +} + +/**************************************************************************** + * Name: rm57_restoresciint + ****************************************************************************/ + +static inline void rm57_restoresciint(struct rm57_dev_s *priv, + uint32_t ints) +{ + rm57_serialout(priv, RM57_SCI_SETINT_OFFSET, ints); +} + +/**************************************************************************** + * Name: rm57_disableallints + ****************************************************************************/ + +static void rm57_disableallints(struct rm57_dev_s *priv, uint32_t *ints) +{ + irqstate_t flags; + + /* The following must be atomic */ + + flags = enter_critical_section(); + if (ints) + { + *ints = rm57_serialin(priv, RM57_SCI_SETINT_OFFSET); + } + + rm57_serialout(priv, RM57_SCI_CLEARINT_OFFSET, SCI_INT_ALLINTS); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: rm57_setup + * + * Description: + * Configure the SCI baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int rm57_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_SCI_CONFIG + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + + return rm57_sci_configure(priv->scibase, &priv->config); +#else + return OK; +#endif +} + +/**************************************************************************** + * Name: rm57_shutdown + * + * Description: + * Disable the SCI. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void rm57_shutdown(struct uart_dev_s *dev) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + + rm57_serialout(priv, RM57_SCI_GCR1_OFFSET, 0); + rm57_disableallints(priv, NULL); +} + +/**************************************************************************** + * Name: rm57_attach + * + * Description: + * Configure the SCI to operate in interrupt driven mode. This method + * is called when the serial port is opened, normally just after the + * setup() method is called. + * + ****************************************************************************/ + +static int rm57_attach(struct uart_dev_s *dev) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + int ret; + + ret = irq_attach(priv->irq, rm57_interrupt, dev); + if (ret == OK) + { + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: rm57_detach + * + * Description: + * Detach SCI interrupts. This method is called when the serial port + * is closed normally, just before the shutdown method is called. + * + ****************************************************************************/ + +static void rm57_detach(struct uart_dev_s *dev) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: rm57_interrupt + * + * Description: + * This is the common SCI interrupt handler. + * + ****************************************************************************/ + +static int rm57_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct rm57_dev_s *priv; + uint32_t intvec; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct rm57_dev_s *)dev->priv; + + for (; ; ) + { + /* Reading INTVECT0 clears the corresponding INTFLAG bit for most + * interrupt sources. + */ + + intvec = rm57_serialin(priv, RM57_SCI_INTVECT0_OFFSET) & + SCI_INTVECT_MASK; + + switch (intvec) + { + case SCI_INTVECT_NONE: /* No interrupt */ + return OK; + + case SCI_INTVECT_WAKEUP: /* Wake-up interrupt (ignored) */ + break; + + /* SCI errors: ignored for now, since break-detect interrupt + * is never enabled + */ + + case SCI_INTVECT_PE: + case SCI_INTVECT_FE: + case SCI_INTVECT_OE: + case SCI_INTVECT_BRKDT: + case SCI_INTVECT_BE: + break; + + case SCI_INTVECT_RX: /* Receive interrupt */ + uart_recvchars(dev); + break; + + case SCI_INTVECT_TX: /* Transmit interrupt */ + uart_xmitchars(dev); + break; + + /* LIN mode only. These should never occur in SCI mode */ + + case SCI_INTVECT_ISFE: + case SCI_INTVECT_ID: + case SCI_INTVECT_PBE: + case SCI_INTVECT_CE: + case SCI_INTVECT_NRE: + case SCI_INTVECT_TOAWUS: + case SCI_INTVECT_TOA3WUS: + case SCI_INTVECT_TIMEOUT: + default: + DEBUGPANIC(); + } + } + + return OK; +} + +/**************************************************************************** + * Name: rm57_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int rm57_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct rm57_dev_s *user = (struct rm57_dev_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev->priv, sizeof(struct rm57_dev_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + termiosp->c_cflag = ((priv->config.parity != 0) ? PARENB : 0) | + ((priv->config.parity == 1) ? PARODD : 0); + termiosp->c_cflag |= (priv->config.stopbits2) ? CSTOPB : 0; + cfsetispeed(termiosp, priv->config.baud); + + switch (priv->config.bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + uint32_t baud; + uint32_t ints; + uint8_t parity; + uint8_t nbits; + bool stop2; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + ret = OK; + baud = cfgetispeed(termiosp); + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; + + default: + ret = -EINVAL; + break; + } + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + if (ret == OK) + { + priv->config.baud = baud; + priv->config.parity = parity; + priv->config.bits = nbits; + priv->config.stopbits2 = stop2; + + rm57_disableallints(priv, &ints); + ret = rm57_sci_configure(priv->scibase, &priv->config); + rm57_restoresciint(priv, ints); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: rm57_receive + * + * Description: + * Called (usually) from the interrupt level to receive one character + * from the SCI. Error bits associated with the receipt are provided + * in the return 'status'. + * + ****************************************************************************/ + +static int rm57_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + + *status = rm57_serialin(priv, RM57_SCI_FLR_OFFSET); + return (int)(rm57_serialin(priv, RM57_SCI_RD_OFFSET) & 0xff); +} + +/**************************************************************************** + * Name: rm57_rxint + * + * Description: + * Call to enable or disable RXRDY interrupts + * + ****************************************************************************/ + +static void rm57_rxint(struct uart_dev_s *dev, bool enable) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + rm57_serialout(priv, RM57_SCI_SETINT_OFFSET, SCI_INT_RX); +#endif + } + else + { + rm57_serialout(priv, RM57_SCI_CLEARINT_OFFSET, SCI_INT_RX); + } +} + +/**************************************************************************** + * Name: rm57_rxavailable + * + * Description: + * Return true if the receive holding register is not empty + * + ****************************************************************************/ + +static bool rm57_rxavailable(struct uart_dev_s *dev) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + return ((rm57_serialin(priv, RM57_SCI_FLR_OFFSET) & SCI_FLR_RXRDY) != 0); +} + +/**************************************************************************** + * Name: rm57_send + * + * Description: + * This method will send one byte on the SCI + * + ****************************************************************************/ + +static void rm57_send(struct uart_dev_s *dev, int ch) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + rm57_serialout(priv, RM57_SCI_TD_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: rm57_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void rm57_txint(struct uart_dev_s *dev, bool enable) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + rm57_serialout(priv, RM57_SCI_SETINT_OFFSET, SCI_INT_TX); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + rm57_serialout(priv, RM57_SCI_CLEARINT_OFFSET, SCI_INT_TX); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: rm57_txready + * + * Description: + * Return true if the transmit holding register is empty (TXRDY) + * + ****************************************************************************/ + +static bool rm57_txready(struct uart_dev_s *dev) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + return ((rm57_serialin(priv, RM57_SCI_FLR_OFFSET) & SCI_FLR_TXRDY) != 0); +} + +/**************************************************************************** + * Name: rm57_txempty + * + * Description: + * Return true if the transmit holding and shift registers are empty + * + ****************************************************************************/ + +static bool rm57_txempty(struct uart_dev_s *dev) +{ + struct rm57_dev_s *priv = (struct rm57_dev_s *)dev->priv; + return ((rm57_serialin(priv, RM57_SCI_FLR_OFFSET) & + SCI_FLR_TXEMPTY) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ + /* Disable all SCIs */ + + rm57_disableallints(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + rm57_disableallints(TTYS1_DEV.priv, NULL); +#endif + +#ifdef CONSOLE_DEV + /* Configure whichever one is the console. NOTE: this was already done + * in rm57_lowsetup(). + */ + + CONSOLE_DEV.isconsole = true; + rm57_setup(&CONSOLE_DEV); + + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/rm57/rm57_timerisr.c b/arch/arm/src/rm57/rm57_timerisr.c new file mode 100644 index 0000000000000..9bb1e73955286 --- /dev/null +++ b/arch/arm/src/rm57/rm57_timerisr.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * arch/arm/src/rm57/rm57_timerisr.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Adapted from tms570_timerisr.c, using RM57's RTI1 register layout + * (hardware/rm57_rti.h) which matches TMS570's RTI/DWWD module - + * same peripheral IP, same base offset pattern. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" +#include "hardware/rm57_rti.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The input clock to the RTI is RTICLK, sourced from VCLK. The correct + * RTICLK frequency must be provided by board.h as BOARD_RTICLK_FREQUENCY. + */ + +#ifndef BOARD_RTICLK_FREQUENCY +# error BOARD_RTICLK_FREQUENCY not defined +#endif + +/* Timing Calculations: + * + * FRC0CLK = RTICLK / (CPUC0 + 1) Hz + * Tcount = 1,000,000 / FRC0CLK Microseconds + * CMP0 = CONFIG_USEC_PER_TICK * FRC0CLK / 1,000,000 + * + * (identical derivation to the sibling tms570_timerisr.c) + */ + +#if BOARD_RTICLK_FREQUENCY > 10000000 +# define RTI_FRC0CLK (1000000) +#elif BOARD_RTICLK_FREQUENCY > 5000000 +# define RTI_FRC0CLK (500000) +#elif BOARD_RTICLK_FREQUENCY > 1000000 +# define RTI_FRC0CLK (100000) +#else +# error No logic for this value of RTICLK +#endif + +#define RTI_CPUC0 (((BOARD_RTICLK_FREQUENCY) / RTI_FRC0CLK) - 1) + +#define RTI_CMP0 ((CONFIG_USEC_PER_TICK * (RTI_FRC0CLK / 100000) + 50) / 10) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int rm57_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Clear the RTI Compare 0 interrupt */ + + putreg32(RTI_INT_COMPARE0, RM57_RTI_INTFLAG); + + /* Process timer interrupt */ + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize the timer + * interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + /* Disable all RTI interrupts */ + + up_disable_irq(RM57_REQ_RTICOMPARE0); + putreg32(0x0, RM57_RTI_GCTRL); + putreg32(0xffffffff, RM57_RTI_CLEARINTENA); + + /* Configure RTICOMP0 and RTIUDCP0 with the calculated compare value */ + + putreg32(RTI_CMP0, RM57_RTI_COMP0); + putreg32(RTI_CMP0, RM57_RTI_UDCP0); + + /* Configure the FRC0CLK clock via RTICPUC0 */ + + putreg32(RTI_CPUC0, RM57_RTI_CPUC0); + + /* Initialize the free-running counter and the RTI up-counter */ + + putreg32(0, RM57_RTI_FRC0); + putreg32(0, RM57_RTI_UC0); + + /* Clear any pending interrupts */ + + putreg32(0xffffffff, RM57_RTI_INTFLAG); + + /* Enable the RTI Compare 0 interrupt (still disabled at the VIM) */ + + putreg32(RTI_INT_COMPARE0, RM57_RTI_SETINTENA); + + /* Enable counter 0 */ + + putreg32(RTI_GCTRL_CNT0EN, RM57_RTI_GCTRL); + + /* Attach the interrupt handler to the RTI Compare 0 interrupt */ + + DEBUGVERIFY(irq_attach(RM57_REQ_RTICOMPARE0, (xcpt_t)rm57_timerisr, NULL)); + + /* Enable RTI compare 0 interrupts at the VIM */ + + up_enable_irq(RM57_REQ_RTICOMPARE0); +} diff --git a/boards/Kconfig b/boards/Kconfig index 44e9a245bd3e0..2359e00a2a736 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1050,6 +1050,14 @@ config ARCH_BOARD_LAUNCHXL_TMS57004 TI Hercules TMS570LS04x/03x LaunchPad Evaluation Kit (LAUNCHXL- TMS57004) featuring the Hercules TMS570LS0432PZ chip. +config ARCH_BOARD_RM57L843_LAUNCHXL2 + bool "TI Hercules RM57L LaunchXL2" + depends on ARCH_CHIP_RM57L843 + select ARCH_HAVE_LEDS + ---help--- + TI Hercules RM57L LaunchPad Development Kit (LAUNCHXL2-RM57L) + featuring the Hercules RM57L843 chip. + config ARCH_BOARD_LM3S6432S2E bool "Stellaris RDK-S2E Reference Design Kit" depends on ARCH_CHIP_LM3S6432 @@ -3803,6 +3811,7 @@ config ARCH_BOARD default "launchxl-cc1310" if ARCH_BOARD_LAUNCHXL_CC1310 default "launchxl-cc1312r1" if ARCH_BOARD_LAUNCHXL_CC1312R1 default "launchxl-tms57004" if ARCH_BOARD_LAUNCHXL_TMS57004 + default "rm57l843-launchxl2" if ARCH_BOARD_RM57L843_LAUNCHXL2 default "lc823450-xgevk" if ARCH_BOARD_LC823450_XGEVK default "lincoln60" if ARCH_BOARD_LINCOLN60 default "lm3s6432-s2e" if ARCH_BOARD_LM3S6432S2E @@ -4920,6 +4929,9 @@ endif if ARCH_BOARD_TMS570LS31X_USB_KIT source "boards/arm/tms570/tms570ls31x-usb-kit/Kconfig" endif +if ARCH_BOARD_RM57L843_LAUNCHXL2 +source "boards/arm/rm57/rm57l843-launchxl2/Kconfig" +endif if ARCH_BOARD_XMC4500RELAX source "boards/arm/xmc4/xmc4500-relax/Kconfig" endif diff --git a/boards/arm/rm57/rm57l843-launchxl2/CMakeLists.txt b/boards/arm/rm57/rm57l843-launchxl2/CMakeLists.txt new file mode 100644 index 0000000000000..53319944c8624 --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/arm/rm57/rm57l843-launchxl2/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_BOARD_RM57L843_LAUNCHXL2) + add_subdirectory(src) +endif() diff --git a/boards/arm/rm57/rm57l843-launchxl2/Kconfig b/boards/arm/rm57/rm57l843-launchxl2/Kconfig new file mode 100644 index 0000000000000..ba1873ebba43c --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_RM57L843_LAUNCHXL2 + +endif # ARCH_BOARD_RM57L843_LAUNCHXL2 diff --git a/boards/arm/rm57/rm57l843-launchxl2/configs/nsh/defconfig b/boards/arm/rm57/rm57l843-launchxl2/configs/nsh/defconfig new file mode 100644 index 0000000000000..51256fb9bc030 --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/configs/nsh/defconfig @@ -0,0 +1,36 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="rm57l843-launchxl2" +CONFIG_ARCH_BOARD_RM57L843_LAUNCHXL2=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_CHIP="rm57" +CONFIG_ARCH_CHIP_RM57=y +CONFIG_ARCH_CHIP_RM57L843=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_LOWVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_ARM_TOOLCHAIN_GNU_EABI=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=524288 +CONFIG_RAM_START=0x08000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_RM57_SCI1=y +CONFIG_SCI1_2STOP=1 +CONFIG_SCI1_SERIAL_CONSOLE=y +CONFIG_SCI1_BAUD=9600 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/rm57/rm57l843-launchxl2/include/board.h b/boards/arm/rm57/rm57l843-launchxl2/include/board.h new file mode 100644 index 0000000000000..e29a24b6cdd90 --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/include/board.h @@ -0,0 +1,128 @@ +/**************************************************************************** + * boards/arm/rm57/rm57l843-launchxl2/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RM57_RM57L843_LAUNCHXL2_INCLUDE_BOARD_H +#define __BOARDS_ARM_RM57_RM57L843_LAUNCHXL2_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Values below are taken directly from TI's HALCoGen HL_system.c + * (setupPLL()/mapClocks()) and HL_system.h (OSC_FREQ/PLL1_FREQ/etc + * comments), i.e. the PLL configuration this HALCoGen project was + * actually generated with - not recomputed from scratch. Verify against + * the LAUNCHXL2-RM57L schematic if the crystal is ever changed. + */ + +/* 16 MHz crystal (HL_system.h OSC_FREQ) */ +#define BOARD_FCLKIN_FREQUENCY 16000000 + +/* PLLCTL1/PLLCTL2 encode: + * NR (REFCLKDIV+1) = 8 + * PLLMUL (raw field) = 0x9500 + * OD (ODPLL+1) = 1 + * R (PLLDIV+1, final) = 1 + * + * HALCoGen computes the resulting PLL1/GCLK frequency as 300 MHz + * (HL_system.h PLL1_FREQ/GCLK_FREQ) - taken as-is rather than + * re-derived from the PLLMUL fixed-point encoding. + */ + +#define BOARD_PLL_NR 8 +#define BOARD_PLL_PLLMUL 0x9500 +#define BOARD_PLL_OD 1 +#define BOARD_PLL_R 1 +#define BOARD_PLL_FREQUENCY 300000000 /* PLL1_FREQ / GCLK_FREQ */ + +/* HCLKCNTL = 1 -> HCLK = GCLK / (1 + 1) = 150 MHz (HL_system.h HCLK_FREQ) */ + +#define BOARD_HCLK_FREQUENCY 150000000 + +/* VCLK1 is the input clock to the SCI baud rate generator + * (HL_system.h VCLK1_FREQ) + */ + +#define BOARD_VCLK_FREQUENCY 75000000 + +/* Flash read wait-states (HL_system.c setupFlash(): FRDCNTL RWAIT field) */ + +#define BOARD_FLASH_RWAIT 3 + +/* RTI1 clock, used for the NuttX system tick (HL_system.h RTI_FREQ) */ + +#define BOARD_RTICLK_FREQUENCY 75000000 + +/* PIN Multiplexor Initializer **********************************************/ + +/* Pin-mux initialization is not yet implemented for this board; + * BOARD_PINMUX_INITIALIZER is not currently defined. + */ + +/* LED definitions **********************************************************/ + +/* The LAUNCHXL2-RM57L has two user LEDs, labeled B6 and B7 on the board + * silkscreen (driven by GIOB[6] and GIOB[7] respectively; see + * src/rm57l843-launchxl2.h for the GIO pin definitions). + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_B6 0 +#define BOARD_LED_B7 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_B6_BIT (1 << BOARD_LED_B6) +#define BOARD_LED_B7_BIT (1 << BOARD_LED_B7) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * src/rm57_autoleds.c. Both LEDs are driven together to encode + * OS-related events as follows: + */ + +#define LED_STARTED 0 /* NuttX has been started */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated */ +#define LED_IRQSENABLED 0 /* Interrupts enabled */ +#define LED_STACKCREATED 1 /* Idle stack created */ +#define LED_INIRQ 2 /* In an interrupt */ +#define LED_SIGNAL 2 /* In a signal handler */ +#define LED_ASSERTION 2 /* An assertion failed */ +#define LED_PANIC 3 /* The system has crashed */ +#undef LED_IDLE /* MCU is in sleep mode: Not used */ + +#endif /* __BOARDS_ARM_RM57_RM57L843_LAUNCHXL2_INCLUDE_BOARD_H */ diff --git a/boards/arm/rm57/rm57l843-launchxl2/scripts/Make.defs b/boards/arm/rm57/rm57l843-launchxl2/scripts/Make.defs new file mode 100644 index 0000000000000..a94d995ca0496 --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/scripts/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/rm57/rm57l843-launchxl2/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-r/Toolchain.defs + +LDSCRIPT = flash-sram.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/rm57/rm57l843-launchxl2/scripts/flash-sram.ld b/boards/arm/rm57/rm57l843-launchxl2/scripts/flash-sram.ld new file mode 100644 index 0000000000000..ade93309b5dac --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/scripts/flash-sram.ld @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/rm57/rm57l843-launchxl2/scripts/flash-sram.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The flash/SRAM sizes below match the RM57L843's memory layout as + * given in TI's HALCoGen-generated HL_sys_link.ld (4MB program flash, + * 512KB SRAM); see also RM57_PFLASH/RM57_SRAM in + * arch/arm/include/rm57/chip.h. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 4096K + sram (rwx) : ORIGIN = 0x08000000, LENGTH = 512K +} + +/* Keep the exception vector table alive through --gc-sections. + * + * arm_vectortab.S defines the .vectors section using the symbols + * _vector_start/_vector_end, not "_vectors" - referencing that + * (nonexistent) name here is a no-op EXTERN that doesn't protect + * anything, and CONFIG_DEBUG_OPT_UNUSED_SECTIONS (--gc-sections) then + * discards the whole vector table since nothing else references it. + * Confirmed on real hardware: nm showed "_vectors" as undefined and + * _vector_start/_vector_end simply missing from the final image - + * address 0x0 held plain __start startup code with no vector table + * ahead of it, so any real exception (data abort, etc.) branched into + * whatever code happened to occupy that vector slot instead of a + * handler. + */ + +EXTERN(_vector_start) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/rm57/rm57l843-launchxl2/src/CMakeLists.txt b/boards/arm/rm57/rm57l843-launchxl2/src/CMakeLists.txt new file mode 100644 index 0000000000000..a7d0bc9368b23 --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/src/CMakeLists.txt @@ -0,0 +1,31 @@ +# ############################################################################## +# boards/arm/rm57/rm57l843-launchxl2/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS rm57_initialize.c rm57_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS rm57_autoleds.c) +else() + list(APPEND SRCS rm57_userleds.c) +endif() + +target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/rm57/rm57l843-launchxl2/src/Makefile b/boards/arm/rm57/rm57l843-launchxl2/src/Makefile new file mode 100644 index 0000000000000..260faa3a22efd --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/src/Makefile @@ -0,0 +1,33 @@ +############################################################################ +# boards/arm/rm57/rm57l843-launchxl2/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = rm57_initialize.c rm57_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += rm57_autoleds.c +else + CSRCS += rm57_userleds.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/rm57/rm57l843-launchxl2/src/rm57_autoleds.c b/boards/arm/rm57/rm57l843-launchxl2/src/rm57_autoleds.c new file mode 100644 index 0000000000000..642e4381eb9bb --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/src/rm57_autoleds.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/rm57/rm57l843-launchxl2/src/rm57_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* LEDs + * + * The LAUNCHXL2-RM57L has two user LEDs, labeled B6 and B7 on the board + * silkscreen, driven by GIOB[6] and GIOB[7] (see rm57l843-launchxl2.h). + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "rm57_gio.h" +#include "rm57l843-launchxl2.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GIOs for output */ + + rm57_configgio(GIO_LED_B6); + rm57_configgio(GIO_LED_B7); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == LED_STACKCREATED || led == LED_PANIC) + { + rm57_giowrite(GIO_LED_B6, true); /* High illuminates */ + rm57_giowrite(GIO_LED_B7, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_STACKCREATED || led == LED_PANIC) + { + rm57_giowrite(GIO_LED_B6, false); /* Low extinguishes */ + rm57_giowrite(GIO_LED_B7, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/rm57/rm57l843-launchxl2/src/rm57_bringup.c b/boards/arm/rm57/rm57l843-launchxl2/src/rm57_bringup.c new file mode 100644 index 0000000000000..374634236bccd --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/src/rm57_bringup.c @@ -0,0 +1,48 @@ +/**************************************************************************** + * boards/arm/rm57/rm57l843-launchxl2/src/rm57_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "rm57l843-launchxl2.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_bringup + * + * Description: + * Bring up board features. + * + ****************************************************************************/ + +int rm57_bringup(void) +{ + return OK; +} diff --git a/boards/arm/rm57/rm57l843-launchxl2/src/rm57_initialize.c b/boards/arm/rm57/rm57l843-launchxl2/src/rm57_initialize.c new file mode 100644 index 0000000000000..ea61275186f05 --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/src/rm57_initialize.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/rm57/rm57l843-launchxl2/src/rm57_initialize.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "rm57l843-launchxl2.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_board_initialize + * + * Description: + * All RM57 architectures must provide the following entry point. This + * function is called near the beginning of _start. This function is + * called after clocking has been configured but before caches have been + * enabled and before any devices have been initialized. .data/.bss + * memory may or may not have been initialized (see the "special + * precautions" below). + * + * This function must perform low level initialization including + * + * - Initialization of board-specific memory resources + * - Configuration of board specific resources (GPIOs, LEDs, etc). + * - Setup of the console UART. This UART done early so that the serial + * console is available for debugging very early in the boot sequence. + * + * Special precautions must be taken if .data/.bss lie in SRAM. In that + * case, the boot logic cannot initialize .data or .bss. The function + * must then: + * + * - Take precautions to assume that logic does not access any global + * data that might lie in SRAM before it is initialized. + * - Call the function arm_data_initialize() as soon as SRAM has been + * properly configured for use. + * + ****************************************************************************/ + +void rm57_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform application level board initialization */ + + rm57_bringup(); +} +#endif diff --git a/boards/arm/rm57/rm57l843-launchxl2/src/rm57_userleds.c b/boards/arm/rm57/rm57l843-launchxl2/src/rm57_userleds.c new file mode 100644 index 0000000000000..4c144933910e8 --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/src/rm57_userleds.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/rm57/rm57l843-launchxl2/src/rm57_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "rm57_gio.h" +#include "rm57l843-launchxl2.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GIOs for output */ + + rm57_configgio(GIO_LED_B6); + rm57_configgio(GIO_LED_B7); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED_B6) + { + rm57_giowrite(GIO_LED_B6, ledon); /* High illuminates */ + } + else if (led == BOARD_LED_B7) + { + rm57_giowrite(GIO_LED_B7, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + /* High illuminates */ + + rm57_giowrite(GIO_LED_B6, (ledset & BOARD_LED_B6_BIT) != 0); + rm57_giowrite(GIO_LED_B7, (ledset & BOARD_LED_B7_BIT) != 0); +} diff --git a/boards/arm/rm57/rm57l843-launchxl2/src/rm57l843-launchxl2.h b/boards/arm/rm57/rm57l843-launchxl2/src/rm57l843-launchxl2.h new file mode 100644 index 0000000000000..47085dcaf4c5a --- /dev/null +++ b/boards/arm/rm57/rm57l843-launchxl2/src/rm57l843-launchxl2.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/arm/rm57/rm57l843-launchxl2/src/rm57l843-launchxl2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RM57_RM57L843_LAUNCHXL2_SRC_RM57L843_LAUNCHXL2_H +#define __BOARDS_ARM_RM57_RM57L843_LAUNCHXL2_SRC_RM57L843_LAUNCHXL2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "rm57_gio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDs + * + * The LAUNCHXL2-RM57L has two user LEDs, labeled B6 and B7 on the board + * silkscreen after the GIO pins that drive them: GIOB[6] (ball J2) and + * GIOB[7] (ball F1) on the RM57L843 337ZWT package. Both are the reset + * default (primary) function on their respective balls per the RM57L843 + * datasheet pin table, so no PINMUX configuration is required to use them + * as plain GIO. + * + * LED illumination polarity is assumed active-high (GIO_OUTPUT_SET = on); + * this has not been confirmed against the board schematic. If the LEDs + * appear inverted on real hardware, swap GIO_OUTPUT_SET/GIO_OUTPUT_CLEAR + * here and invert the true/false sense in rm57_autoleds.c / + * rm57_userleds.c. + */ + +#define GIO_LED_B6 (GIO_OUTPUT | GIO_CFG_DEFAULT | GIO_OUTPUT_SET | \ + GIO_PORT_GIOB | GIO_PIN6) +#define GIO_LED_B7 (GIO_OUTPUT | GIO_CFG_DEFAULT | GIO_OUTPUT_SET | \ + GIO_PORT_GIOB | GIO_PIN7) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rm57_bringup + * + * Description: + * Bring up board features. + * + ****************************************************************************/ + +int rm57_bringup(void); + +#endif /* __BOARDS_ARM_RM57_RM57L843_LAUNCHXL2_SRC_RM57L843_LAUNCHXL2_H */