tscore: SIMD ts::memcpy_tolower; use in URL.cc cache-key fast path

[phongn]

Summary

Add a SIMD-accelerated bulk ASCII tolower helper ts::memcpy_tolower in tscore, and use it in place of the byte-at-a-time loop on the URL canonicalization fast path that produces the cache-key digest. Header-only helper with a compile-time ISA cascade: 64-byte AVX-512BW, 32-byte AVX2, 16-byte SSE2 on x86_64, plus 16-byte NEON on ARMv8. Selection is purely compile-time; runtime ifunc dispatch is left for a follow-up. Operators get the wider path automatically by raising -march (x86-64-v3 = AVX2, x86-64-v4 = AVX-512BW); a stock x86_64 build keeps SSE2.

Behavior matches ParseRules::ink_tolower exactly: bytes in A..Z map to a..z, all others (including 0x80..0xFF) pass through unchanged.

Implementation notes

• Cascade: wider bodies drain into narrower ones, so the worst-case scalar tail is always <16 bytes regardless of build flags.
• AVX-512BW kernel uses _mm512_mask_add_epi8 to fuse the conditional +0x20 into a single op, and a masked load/store for the 1–63-byte tail in one SIMD pass. Inspired by Tony Finch's copytolower64.c.
• The whole AVX-512BW block is gated at n ≥ 64, because the masked load/store carries ~7 ns of fixed setup that loses to the narrower paths for short inputs; below 64 bytes the AVX-512BW build falls through to its AVX2 + SSE2 cascade.

src/proxy/hdrs/URL.cc drops its static-inline memcpy_tolower and calls ts::memcpy_tolower instead.

Performance — measured on Xeon Gold 6338 (Ice Lake, 2.0 GHz)

Mean ns per call from tools/benchmark/benchmark_memcpy_tolower:

Size	scalar	SSE2	AVX2 (-mavx2)	AVX-512BW (-mavx512bw)
16 B	10.4	2.15	1.75	1.98
32 B	15.4	2.90	2.24	2.31
64 B	28.0	4.43	2.85	2.61
256 B	113	13.87	7.57	6.20
1024 B	425	50.47	24.23	17.49

Speedup vs scalar at 1024 B: SSE2 8.4×, AVX2 17.5×, AVX-512BW 24.3×.

URL hot path inputs: HTTP schemes ("http"/"https") are 4–5 bytes and stay on the scalar tail with no change. Typical host names (16+ bytes) get the full 4–14× speedup depending on build flags.

Test plan

• Microbench tools/benchmark/benchmark_memcpy_tolower runs 269 correctness assertions covering:
  • Sizes 0, 1, 5, 15, 16, 17, 23, 31, 32, 33, 64, 257 (bracketing each SIMD body) against the scalar reference.
  • An exhaustive sweep of all 256 byte values verifying that only A..Z are remapped — guards against any future widening of the case-fold range.
• All paths run correctness clean on:
  • Broadwell (AVX2-capable) with -mavx2
  • Ice Lake (AVX-512BW) with -mavx2, -mavx512bw, and the default
• cmake --build build -t format clean.
• src/proxy/hdrs/libhdrs.a builds clean with the updated URL.cc.
• Jenkins CI green.

Notes for reviewers

• No new compile flags or dependencies. Just baseline SSE2 (x86_64 ABI) and baseline NEON (ARMv8 ABI); wider paths kick in automatically with -march=x86-64-v3 or -march=x86-64-v4.
• The header includes <immintrin.h> / <arm_neon.h> only inside the #if that needs them, so other architectures don't pull them in.
• AVX-512BW kernel design (mask_add + masked tail) was adapted from Tony Finch's vectolower, license-compatible (0BSD / MIT-0).
• Other call sites with the same byte-at-a-time tolower pattern (HPACK.cc, QPACK.cc, UrlRewrite.cc) could also benefit; left untouched here to keep this PR focused.

🤖 Generated with Claude Code

[bryancall]

@phongn Should we do this for in place too?

[Copilot]

Pull request overview

This PR adds a header-only SIMD ASCII lowercase-copy helper in tscore and switches the URL cache-key fast path to use it instead of the local scalar loop.

Changes:

• Adds ts::memcpy_tolower with scalar, SSE2, AVX2, AVX-512BW, and NEON paths.
• Replaces URL fast-path scheme/host lowercasing with the shared helper.
• Adds an optional Catch2 benchmark/correctness harness for the helper.

Reviewed changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated 4 comments.

File	Description
include/tscore/ink_memcpy_tolower.h	Defines the new SIMD/scalar lowercase-copy helper.
src/proxy/hdrs/URL.cc	Uses ts::memcpy_tolower in cache-key fast-path canonicalization.
tools/benchmark/benchmark_memcpy_tolower.cc	Adds benchmark and correctness checks for the helper.
tools/benchmark/CMakeLists.txt	Builds the new benchmark target when benchmarks are enabled.

[phongn]

Good catch — comment was stale from an earlier iteration that used a cascade for the tail. Updated in faeb167 to describe what the code actually does: AVX-512BW gates at n >= 64, runs a 64-byte main loop, finishes any 1..63-byte tail with a single masked load/store, then early-returns. The AVX2 + SSE2 cascade only runs for n < 64, where the masked-tail setup cost (~7 ns) would otherwise lose to the narrower paths.

[phongn]

Yes — migrated the in-place tolower loop in QPACK::_encode_header to ts::memcpy_tolower in faeb167. The helper's contract now explicitly supports dst == src: every SIMD body loads a full block into a register before storing back at the same offset, and the AVX-512BW masked tail does masked-load/masked-store at the same offset. Partial overlap (where dst != src but the ranges intersect) is still unsupported. Unit test coverage for the in-place form added too.

UrlRewrite.cc and HPACK.cc have similar byte-at-a-time loops with separate buffers — those are easy follow-up migrations if you'd like them rolled in, or I can leave them as a separate PR.

[masaori335]

I expect applying this to UrlRewrite and HPACK has more performance impact than cache-key in real traffic 👍 I can spawn benchmark in our tool and share result when tests are passed.