PCI issue tracker

[cl91]

• Fix ISA bridge config so SuperIO can decode the floppy controller IO range. Basically LPC bridge (ICH7, PCI device 00:1f.0) → sets bit 0 (FDCEN) in config register 0x82. This is needed to get the floppy controller working on Gigabyte EG41M-S2H (Intel ICH7) #37
• PCI hotplug. We need to implement arbitration of bus number, BAR, and IO/memory forward windows. #45
• Enable legacy interrupt if no MSI/MSIX is available. We don't allow sharing of interrupt lines, but at least one of the devices will be able to work. This is probably not worth it. Since we target Core 2 Duo and later, the biggest problem is EHCI (USB2.0) controllers and PCI (non-PCIE) NIC. We will have to give up on supporting USB and non-PCIE Ethernet on these platforms. Starting from Ivy Bridge USB is xHCI (BIOS has a configuration to route all USB2.0 ports to xHCI), and NIC is PCIE, so there is no problem there.
• Do not blast the entire PCI config space. Real devices don't like this. Instead, only program the necessary bits. This might be related to Fix ISA bridge config so SuperIO can decode the floppy controller IO range. Basically LPC bridge (ICH7, PCI device 00:1f.0) → sets bit 0 (FDCEN) in config register 0x82. This is needed to get the floppy controller working on Gigabyte EG41M-S2H (Intel ICH7) #37