diff --git a/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/libcox/dma.c b/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/libcox/dma.c new file mode 100644 index 00000000..d8196480 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/libcox/dma.c @@ -0,0 +1,962 @@ +//***************************************************************************** +// +//! \file xdma.c +//! \brief Driver for the DMA Controller. +//! \version V2.1.1.1 +//! \date 11/14/2011 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#include "xhw_types.h" +#include "xhw_ints.h" +#include "xhw_memmap.h" +#include "xhw_nvic.h" +#include "xhw_sysctl.h" +#include "xhw_dma.h" +#include "xdebug.h" +#include "xcore.h" +#include "xsysctl.h" +#include "xdma.h" + +typedef struct +{ + // + // Channel ID. + // + unsigned long ulChannelID; + + // + // + // + xtEventCallback pfnDMAChannelHandlerCallback; + + // + // Channel Assignment status + // + xtBoolean bChannelAssigned; + +} +tDMAChannelAsssign; + +// +// DMA Channels Address. +// +static unsigned long g_psDMAChannelAddress[] = +{ + PDMA0_BASE, + PDMA1_BASE, + PDMA2_BASE, + PDMA3_BASE, + PDMA4_BASE, + PDMA5_BASE, + PDMA6_BASE, + PDMA7_BASE, + PDMA8_BASE +}; + +// +// PDMA Service Selection Control Register. +// +static unsigned long g_psDMAIPSelectReg[] = +{ + PDMA_PDSSR0, + PDMA_PDSSR1, + PDMA_PDSSR2 +}; + +#define PDMA_PDSRx(a) (((a) >> 28) & 0x3) +#define PDMA_PDSR_M(a) ((((a) & 0xF) << ((a) & 0x1f0000 >> 16))) + +//***************************************************************************** +// +// An array is DMA Callback function point +// +//***************************************************************************** +// static xtEventCallback g_pfnDMAGHandlerCallbacks[9]={0}; + +// +// DMA Channels Assignment table. +// +static tDMAChannelAsssign g_psDMAChannelAssignTable[] = +{ + { xDMA_CHANNEL_0, 0, xfalse }, + { xDMA_CHANNEL_1, 0, xfalse }, + { xDMA_CHANNEL_2, 0, xfalse }, + { xDMA_CHANNEL_3, 0, xfalse }, + { xDMA_CHANNEL_4, 0, xfalse }, + { xDMA_CHANNEL_5, 0, xfalse }, + { xDMA_CHANNEL_6, 0, xfalse }, + { xDMA_CHANNEL_7, 0, xfalse }, + { xDMA_CHANNEL_8, 0, xfalse }, + + // + // End. + // + { xDMA_CHANNEL_NOT_EXIST, xfalse }, + +}; + +//***************************************************************************** +// +//! \internal +//! Checks a DMA channel ID. +//! +//! \param ulChannelID is the DMA channel ID. +//! +//! This function determines if a DMA channel ID is valid. +//! +//! \return Returns \b xtrue if the ID is valid and \b xfalse +//! otherwise. +// +//***************************************************************************** +#ifdef xDEBUG +static xtBoolean +xDMAChannelIDValid(unsigned long ulChannelID) +{ + return( (ulChannelID >= 0) && (ulChannelID < 9)); +} +#endif + + +//***************************************************************************** +// +//! DMA Interrupt Handler. +//! +//! The interrupt handler for uDMA interrupts from the memory channel. +//! +//! \return None. +// +//***************************************************************************** +void +PDMAIntHandler(void) +{ + unsigned long ulChannelID; + unsigned long ulStatus; + ulStatus = xHWREG(PDMA_GCRISR); + for(ulChannelID = 0; + g_psDMAChannelAssignTable[ulChannelID].ulChannelID != + xDMA_CHANNEL_NOT_EXIST; + ulChannelID++) + { + if(g_psDMAChannelAssignTable[ulChannelID].bChannelAssigned == xtrue) + { + if (ulStatus & (1< nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +#include "CoX.h" +#include "xhw_sysctl.h" +#include "xhw_i2c.h" + +//***************************************************************************** +// +// An array is I2C callback function point +// +//***************************************************************************** +static xtEventCallback g_pfnI2CHandlerCallbacks[1]={0}; + +//***************************************************************************** +// +//! \brief I2C0 interrupt handler. Clear the I2C0 interrupt flag and execute the +//! callback function. +//! +//! \param none. +//! +//! This function is the I2C0 interrupt handler,it will Clear the I2C0 +//! interrupt flag and execute the callback function if there be one. +//! +//! \note There are two source of this interrupt.One is I2C0 function +//! and one is I2C0 time out. +//! +//! \return None. +// +//***************************************************************************** +void +I2C0_IRQHandler(void) +{ + unsigned long ulBase = I2C0_BASE; + unsigned long ulStatus = xHWREG(ulBase + I2C_STATUS); + unsigned long ulTimeout; + // + // 0 + // + //I2CFlagStatusClear(ulBase, I2C_EVENT_BUSERR | I2C_EVENT_RXNACK | + // I2C_EVENT_ARBLOS); + + if((ulStatus == I2C_I2STAT_S_RX_SLAW_ACK) || + (ulStatus == I2C_I2STAT_S_RX_GENCALL_ACK) || + (ulStatus == I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK) || + (ulStatus == I2C_I2STAT_S_TX_DAT_NACK) || + (ulStatus == I2C_I2STAT_S_TX_SLAR_ACK)) + { + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + } + + if((ulStatus == I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK) || + (ulStatus == I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK)) + { + g_pfnI2CHandlerCallbacks[0](0, 0, xI2C_SLAVE_EVENT_RREQ, 0); + } + if((ulStatus == I2C_I2STAT_S_TX_SLAR_ACK) || + (ulStatus == I2C_I2STAT_S_TX_DAT_ACK)) + { + g_pfnI2CHandlerCallbacks[0](0, 0, xI2C_SLAVE_EVENT_TREQ, 0); + } + if((ulStatus == I2C_I2STAT_M_TX_SLAW_ACK) || + (ulStatus == I2C_I2STAT_M_TX_DAT_ACK)) + { + g_pfnI2CHandlerCallbacks[0](0, 0, xI2C_MASTER_EVENT_TX, 0); + } + if((ulStatus == I2C_I2STAT_M_RX_SLAR_ACK) || + (ulStatus == I2C_I2STAT_M_RX_DAT_ACK)) + { + g_pfnI2CHandlerCallbacks[0](0, 0, xI2C_MASTER_EVENT_RX, 0); + } + if((ulStatus == I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX)) + { + // + //Temporally lock the interrupt for timeout condition + // + xI2CSlaveIntDisable(ulBase, 0); + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + // + // enable time out + // + ulTimeout = 0x10000; + while(1) + { + if (xHWREG(ulBase + I2C_CON) & I2C_CON_SI) + { + // + // re-Enable interrupt + // + xI2CSlaveIntEnable(ulBase, 0); + break; + } + else + { + ulTimeout--; + if (ulTimeout == 0) + { + // + //timeout occur, it's really a stop condition + // + g_pfnI2CHandlerCallbacks[0](0, 0, xI2C_SLAVE_EVENT_STOP, 0); + break; + } + } + } + } +} + +//***************************************************************************** +// +//! \internal +//! \brief Get the I2C number. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to get the I2C number . +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return value of I2C number,it can only be 0. +// +//***************************************************************************** +static unsigned long I2CNumGet(unsigned long ulBase) +{ + unsigned char num = 0; + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + return 0; +} + +//***************************************************************************** +// +//! \internal +//! \brief Generate a start condition on I2C bus. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to generate a start condition on +//! specified I2C BUS. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note This is only for master +//! +//! \return value of I2C status register after generate a start condition. +// +//***************************************************************************** +static unsigned long I2CStartSend (unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + xHWREG(ulBase + I2C_CON) |= I2C_CON_STA; + + // + // Wait for complete + // + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + + return (xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M); +} + +//***************************************************************************** +// +//! \internal +//! \brief Generate a stop condition on I2C bus. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to generate a stop condition on +//! specified I2C BUS. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note This is only for master +//! +//! \return None. +// +//***************************************************************************** +static void I2CStopSend (unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + if (xHWREG(ulBase + I2C_CON) & I2C_CON_STA) + { + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_STA; + } + xHWREG(ulBase + I2C_CON) |= I2C_CON_STO; + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_AA; +} + +//***************************************************************************** +// +//! \internal +//! \brief Send a byte to I2C bus. +//! +//! \param ulBase specifies the I2C module base address. +//! \param ucData specifies the data which will send to I2C BUS. +//! +//! This function is to send a byte on specified I2C BUS. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note This is only for master +//! +//! \return value of I2C status register after send a byte. +// +//***************************************************************************** +static unsigned long I2CByteSend (unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + // + // Make sure start bit is not active,but do not clear SI + // + if (xHWREG(ulBase + I2C_CON) & I2C_CON_STA) + { + xHWREG(ulBase + I2C_CON) &= ~(I2C_CON_STA | I2C_CON_SI); + } + + // + // Send i2c address and RW bit + // + xHWREG(ulBase + I2C_DAT) = ucData; + + // + // Make sure AA and EI bit is not active,and clear SI + // + xHWREG(ulBase + I2C_CON) &= ~(I2C_CON_AA | I2C_CON_EI); + + // + // Wait the SI be set again by hardware + // + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + + // + // Return the i2c status + // + return (xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M); +} + +//***************************************************************************** +// +//! \internal +//! \brief Get a byte to I2C bus. +//! +//! \param ulBase specifies the I2C module base address. +//! \param ucpData specifies the data point which will save the data get from +//! I2C BUS. +//! +//! This function is to get a byte on specified I2C BUS. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note This is only for master +//! +//! \return value of I2C status register after send a byte. +// +//***************************************************************************** +static unsigned long I2CByteGet (unsigned long ulBase, unsigned char *ucpData, + unsigned char ucAck) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + // + // Make sure start bit is not active + // + if (ucAck == 1) + { + xHWREG(ulBase + I2C_CON) |= I2C_CON_AA; + } + else + { + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_AA; + } + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + *ucpData = (unsigned char)xHWREG(ulBase + I2C_DAT); + return (xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M); +} + +//***************************************************************************** +// +//! \brief Set the clock rate of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! \param ulI2CClk specifies the I2C clock rate. +//! +//! This function is to init and set the clock rate +//! specified SPI port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! The \e ulI2CClk is the I2C clock rate: +//! +//! \note This is only for master +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterInit(unsigned long ulBase, unsigned long ulI2CClk) +{ + unsigned long ulHclk; + unsigned long ulDiv; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xSysCtlPeripheralReset(xSYSCTL_PERIPH_I2C0); + + ulHclk = xSysCtlClockGet(); + + ulDiv = (unsigned long) (((ulHclk * 10)/(ulI2CClk * 4) + 5) / 10 - 1); + xHWREG(ulBase + I2C_CLKDIV) = ulDiv; + + xHWREG(ulBase + I2C_CON) = 0; + xHWREG(ulBase + I2C_CON) = I2C_CON_ENS1; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! This function returns an indication of whether or not the I2C bus +//! is busy. This function can be used in a multi-master environment to +//! determine if another master is currently using the bus. +//! +//! \param [in] ulBase is the I2C module base address. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \return The I2C bus status: +//! - xtrue if I2C bus is busy. +//! - xfalse if I2C bus is free. +// +//***************************************************************************** +xtBoolean xI2CMasterBusBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + return ((xHWREG(ulBase + I2C_STATUS)&0xF8) == 0xF8)? xfalse : xtrue; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C Master is busy. +//! This function returns an indication of whether or not the I2C Master +//! is busy transmitting or receiving data. +//! +//! \param [in] ulBase is the I2C module base address. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \return The I2C bus status: +//! - xtrue if I2C bus is busy. +//! - xfalse if I2C bus is free. +// +//***************************************************************************** +xtBoolean xI2CMasterBusy(unsigned long ulBase) +{ + return xfalse; +} + +//***************************************************************************** +// +//! \brief Gets the error status of the I2C Master module. +//! This function is used to obtain the error status of the Master module +//! send and receive operations. +//! +//! \param [in] ulBase is the I2C module base address. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \return Returns the error status, can be one of the following value: +//! - \ref I2C_MASTER_ERR_NONE +//! - \ref I2C_MASTER_ERR_ADDR_ACK +//! - \ref I2C_MASTER_ERR_DATA_ACK +//! - \ref I2C_MASTER_ERR_ARB_LOST +// +//***************************************************************************** +unsigned long xI2CMasterError(unsigned long ulBase) +{ + unsigned long ulStatus; + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + ulStatus = (xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M); + + if((ulStatus == I2C_I2STAT_M_TX_DAT_NACK) || + (ulStatus == I2C_I2STAT_M_RX_DAT_NACK)) + { + return xI2C_MASTER_ERR_ADDR_ACK; + } + if((ulStatus == I2C_I2STAT_M_TX_SLAW_NACK) || + (ulStatus == I2C_I2STAT_M_RX_SLAR_NACK)) + { + return xI2C_MASTER_ERR_DATA_ACK; + } + if((ulStatus == I2C_I2STAT_M_TX_ARB_LOST)) + { + return xI2C_MASTER_ERR_ARB_LOST; + } + return xI2C_MASTER_ERR_NONE; +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C Master. +//! +//! \param ulBase is the base address of the I2C module. +//! \param ucData data to be transmitted from the I2C Master +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \return None. +// +//***************************************************************************** +void xI2CMasterDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Send data to I2C BUS + // + xHWREG(ulBase + I2C_DAT) = ucData; + + // + // Make sure AA bit is active,and clear EI + // + xHWREG(ulBase + I2C_CON) |= I2C_CON_AA; + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Master. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! unsigned long. +// +//***************************************************************************** +unsigned long xI2CMasterDataGet(unsigned long ulBase) +{ + unsigned long ulData = xHWREG(ulBase + I2C_DAT); + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + return ulData; +} + +//***************************************************************************** +// +//! \brief Transmite the STOP condition, master goes to idle state. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function free the I2C bus. When the master no longer need send or +//! receive any more data, or need to terminate this transmition after getting +//! some errors, call this function. +//! +//! \return None. +// +//***************************************************************************** +void xI2CMasterStop(unsigned long ulBase) +{ + +} + +//***************************************************************************** +// +//! \brief Send a master transmit request when the bus is idle.(Write Step1) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucSlaveAddr is the 7-bit slave address. +//! \param ucData is the byte to transmit. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! This function init a new write transmition. When the master have not obtained +//! control of the bus, This function send request to transmit the START +//! condition, the slave address and the data, Then it returns immediately, no +//! waiting any bus transmition to complete. +//! +//! Users can call I2CMasterBusy() to check if all the bus transmition +//! complete, the call I2CMasterErr() to check if any error occurs. +//! +//! After the master obtained control of the bus, and haven't release it, users +//! can call I2CMasterWriteRequestS2() to continue transmit data to slave. +//! Users can also call I2CMasterStop() to terminate this transmition and +//! release the I2C bus. +//! +//! For this function returns immediately, it is always using in the interrupt +//! hander. +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterWriteRequestS1(unsigned long ulBase, unsigned char ucSlaveAddr, + unsigned char ucData, xtBoolean bEndTransmition) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + xASSERT(!(ucSlaveAddr & 0x80)); + + // + // Send start + // + ulStatus = I2CStartSend(ulBase); + + if(!(ulStatus == I2C_I2STAT_M_TX_START)) + { + I2CStopSend(ulBase); + return; + } + + // + // Send address + // + ulStatus = I2CByteSend(ulBase, (ucSlaveAddr << 1)); + if(!(ulStatus == I2C_I2STAT_M_TX_SLAW_ACK)) + { + I2CStopSend(ulBase); + return; + } + + // + // Send data to I2C BUS + // + xHWREG(ulBase + I2C_DAT) = ucData; + + // + // Make sure AA and EI bit is not active,and clear EI + // + //xHWREG(ulBase + I2C_CON) &= ~(I2C_CON_AA | I2C_CON_EI); + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + + if(bEndTransmition) + { + I2CStopSend(ulBase); + } +} + +//***************************************************************************** +// +//! \brief Send a master data transmit request when the master have obtained +//! control of the bus.(Write Step2) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucData is the byte to transmit. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! After the master obtained control of the bus(have called +//! I2CMasterWriteRequestS1() without any error), and haven't release it, users +//! can call this function to continue transmit data to slave. +//! +//! This function just send request to transmit the data, and it returns +//! immediately, no waiting any bus transmition to complete. +//! +//! Users can call I2CMasterBusy() to check if all the bus transmition +//! complete, the call I2CMasterErr() to check if any error occurs. Users call +//! also can I2CMasterStop() to terminate this transmition and release the +//! I2C bus. +//! +//! For this function returns immediately, it is always using in the interrupt +//! hander. +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterWriteRequestS2(unsigned long ulBase, unsigned char ucData, + xtBoolean bEndTransmition) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + // + // Send data to I2C BUS + // + xHWREG(ulBase + I2C_DAT) = ucData; + + // + // Make sure AA and EI bit is not active,and clear EI + // + xHWREG(ulBase + I2C_CON) &= ~(I2C_CON_AA | I2C_CON_EI); + + // + // Send the stop if End Transmition. + // + if(bEndTransmition) + { + I2CStopSend(ulBase); + } +} + +//***************************************************************************** +// +//! \brief Write a data to the slave when the bus is idle, and waiting for all +//! bus transmiton complete.(Write Step1) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucSlaveAddr is the 7-bit slave address. +//! \param ucData is the byte to transmit. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! This function init a new write transmition. When the master have not obtained +//! control of the bus, This function transmit the START condition, the slave +//! address and the data, then waiting for all bus transmition complete. +//! +//! Users can then check the return value to see if any error occurs: +//! - \ref I2C_MASTER_ERR_NONE - \b 0, no error +//! - \ref I2C_MASTER_ERR_ADDR_ACK - The transmitted address was not acknowledged +//! - \ref I2C_MASTER_ERR_DATA_ACK - The transmitted data was not acknowledged +//! - \ref I2C_MASTER_ERR_ARB_LOST - The I2C controller lost arbitration. +//! +//! After the master obtained control of the bus, and haven't release it, users +//! can call I2CMasterWriteS2() to continue transmit data to slave. +//! Users call also can I2CMasterStop() to terminate this transmition and +//! release the I2C bus. +//! +//! This function is always used in thread mode. +//! +//! \return Returns the master error status. +// +//***************************************************************************** +unsigned long +xI2CMasterWriteS1(unsigned long ulBase, unsigned char ucSlaveAddr, + unsigned char ucData, xtBoolean bEndTransmition) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + xASSERT(!(ucSlaveAddr & 0x80)); + + // + // Send write request + // + xI2CMasterWriteRequestS1(ulBase, ucSlaveAddr, ucData, xfalse); + + // + // Wait the SI be set again by hardware + // + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + ulStatus = xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M; + if(!(ulStatus == I2C_I2STAT_M_TX_DAT_ACK)) + { + ulStatus = xI2CMasterError(ulBase); + I2CStopSend(ulBase); + return ulStatus; + } + + if(bEndTransmition) + { + I2CStopSend(ulBase); + } + + // + // return the error status + // + return xI2C_MASTER_ERR_NONE; +} + +//***************************************************************************** +// +//! \brief Write a data to the slave, when the master have obtained control of +//! the bus, and waiting for all bus transmiton complete.(Write Step2) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucData is the byte to transmit. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! After the master obtained control of the bus(have called +//! I2CMasterWriteS1() without any error), and haven't release it, users +//! can call this function to continue transmit data to slave. +//! +//! This function transmit the data to the slave, and waiting for all bus +//! transmition complete. +//! +//! Users can then check the return value to see if any error occurs: +//! - \ref I2C_MASTER_ERR_NONE - \b 0, no error +//! - \ref I2C_MASTER_ERR_ADDR_ACK - The transmitted address was not acknowledged +//! - \ref I2C_MASTER_ERR_DATA_ACK - The transmitted data was not acknowledged +//! - \ref I2C_MASTER_ERR_ARB_LOST - The I2C controller lost arbitration. +//! +//! Then users can call this function to continue transmit data to slave. +//! Users call also call I2CMasterStop() to terminate this transmition and +//! release the I2C bus. +//! +//! This function is always used in thread mode. +//! +//! \return Returns the master error status. +// +//***************************************************************************** +unsigned long +xI2CMasterWriteS2(unsigned long ulBase, unsigned char ucData, + xtBoolean bEndTransmition) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + // + // Send write request + // + xI2CMasterWriteRequestS2(ulBase, ucData, xfalse); + + // + // Wait the SI be set again by hardware + // + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + ulStatus = xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M; + if(!(ulStatus == I2C_I2STAT_M_TX_DAT_ACK)) + { + ulStatus = xI2CMasterError(ulBase); + I2CStopSend(ulBase); + return ulStatus; + } + + if(bEndTransmition) + { + I2CStopSend(ulBase); + } + + // + // return the error status + // + return xI2C_MASTER_ERR_NONE; +} + +//***************************************************************************** +// +//! \brief Write a data buffer to the slave when the bus is idle, and waiting +//! for all bus transmiton complete.(Write Buffer Step1) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucSlaveAddr is the 7-bit slave address. +//! \param pucDataBuf is the data buffer to transmit. +//! \param ulLen is the data buffer byte size. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! This function init a new data buffer write transmition. When the master have +//! not obtained control of the bus, This function transmit the START condition, +//! the slave address and the data, then waiting for the data transmition +//! complete, and continue next data transmition, until all complete. If there +//! is any error occurs, the remain data will be canceled. +//! +//! Users can then check the return value to see how many datas have been +//! successfully transmited. if the number != ulLen, user can call +//! I2CMasterErr() to see what error occurs. +//! +//! After the master obtained control of the bus, and haven't release it, users +//! can call I2CMasterWriteS2() / I2CMasterWriteBufS2() to continue transmit data +//! to slave. Users call also call I2CMasterStop() to terminate this transmition +//! and release the I2C bus. +//! +//! This function is always used in thread mode. +//! +//! \return Returns the data number that have been successully tranmited. +// +//***************************************************************************** +unsigned long +xI2CMasterWriteBufS1(unsigned long ulBase, unsigned char ucSlaveAddr, + unsigned char *pucDataBuf, unsigned long ulLen, + xtBoolean bEndTransmition) +{ + + unsigned long ulStatus; + unsigned long ulWritten; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + xASSERT(pucDataBuf); + + if(ulLen == 1) + { + ulStatus = xI2CMasterWriteS1(ulBase, ucSlaveAddr, + pucDataBuf[0], bEndTransmition); + + return (ulStatus == xI2C_MASTER_ERR_NONE) ? 1 : 0; + } + + // + // Send start + // + ulStatus = I2CStartSend(ulBase); + if(!(ulStatus == I2C_I2STAT_M_TX_START)) + { + I2CStopSend(ulBase); + return 0; + } + // + // Send address + // + ulStatus = I2CByteSend(ulBase, (ucSlaveAddr << 1)); + if(!(ulStatus == I2C_I2STAT_M_TX_SLAW_ACK)) + { + I2CStopSend(ulBase); + return 0; + } + + // + // Send data + // + ulStatus = I2CByteSend(ulBase, *pucDataBuf); + + // + // Check if any error occurs + // + if(!(ulStatus == I2C_I2STAT_M_TX_DAT_ACK)) + { + I2CStopSend(ulBase); + return 0; + } + else + { + ulWritten = 1; + } + + ulWritten += xI2CMasterWriteBufS2(ulBase, + &pucDataBuf[1], + ulLen - 1, + bEndTransmition); + + return ulWritten; +} + +//***************************************************************************** +// +//! \brief Write a data buffer to the slave, when the master have obtained +//! control of the bus, and waiting for all bus transmiton complete.(Write +//! Buffer Step2) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param pucDataBuf is the data buffer to transmit. +//! \param ulLen is the data buffer byte size. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! After the master obtained control of the bus(have called +//! I2CMasterWriteS1() or I2CMasterWriteBufS1() without any error), and haven't +//! release it, users can call this function to continue transmit data to slave. +//! +//! This function transmit the data one by one to the slave, waiting for every +//! data transmition complete, and continue next data transmition, until all +//! complete. If there is any error occurs, the remain data will be canceled. +//! +//! Users can then check the return value to see how many datas have been +//! successfully transmited. if the number != ulLen, user can call +//! I2CMasterErr() to see what error occurs. +//! +//! Then users can call I2CMasterWriteS2() or this function to continue +//! transmit data to slave. Users call also call I2CMasterStop() to terminate +//! this transmition and release the I2C bus. +//! +//! This function is always used in thread mode. +//! +//! \return Returns the data number that have been successully tranmited. +// +//***************************************************************************** +unsigned long +xI2CMasterWriteBufS2(unsigned long ulBase, unsigned char *pucDataBuf, + unsigned long ulLen, xtBoolean bEndTransmition) +{ + unsigned long i; + unsigned long ulStatus; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + xASSERT(pucDataBuf); + + for(i = 0; i < ulLen - 1; i++) + { + // + // Send data + // + ulStatus = I2CByteSend(ulBase, *pucDataBuf++); + + // + // Check if any error occurs + // + if(!(ulStatus == I2C_I2STAT_M_TX_DAT_ACK)) + { + I2CStopSend(ulBase); + return i; + + } + } + // + // Waiting the I2C controller to idle + // + ulStatus = I2CByteSend(ulBase, *pucDataBuf); + if(!(ulStatus == I2C_I2STAT_M_TX_DAT_ACK)) + { + I2CStopSend(ulBase); + return i; + } + + if(bEndTransmition) + { + I2CStopSend(ulBase); + } + + return ulLen; +} + +//***************************************************************************** +// +//! \brief Send a master receive request when the bus is idle.(Read Step1) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucSlaveAddr is the 7-bit slave address. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! This function init a new receive transmition. When the master have not obtained +//! control of the bus, This function send request to transmit the START +//! condition, the slave address and the data request, Then it returns +//! immediately, no waiting any bus transmition to complete. +//! +//! If bEndTransmition is xtrue, the receive operation will followed by an +//! negative ACK and STOP condition. +//! +//! Users can call I2CMasterBusy() to check if all the bus transmition +//! complete, then call I2CMasterErr() to check if any error occurs. Then user +//! can get the data by calling I2CMasterDataGet() if there is no error occurs. +//! +//! After the master obtained control of the bus, and haven't release it, users +//! can call I2CMasterReadRequestS2() to continue receive data from slave. +//! Users call also can I2CMasterStop() to terminate this transmition and +//! release the I2C bus. +//! +//! For this function returns immediately, it is always using in the interrupt +//! hander. +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterReadRequestS1(unsigned long ulBase, unsigned char ucSlaveAddr, + xtBoolean bEndTransmition) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + xHWREG(ulBase + I2C_CON) |= I2C_CON_AA; + // + // Send start and address + // + ulStatus = I2CStartSend(ulBase); + if(!((ulStatus == I2C_I2STAT_M_TX_START) || + (ulStatus == I2C_I2STAT_M_TX_RESTART))) + { + I2CStopSend(ulBase); + return ; + } + // + // Send address + // + ulStatus = I2CByteSend(ulBase, (ucSlaveAddr << 1) | 1) ; + if(!(ulStatus == I2C_I2STAT_M_RX_SLAR_ACK)) + { + I2CStopSend(ulBase); + return ; + } + if(bEndTransmition) + { + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_AA; + I2CStopSend(ulBase); + } +} + +//***************************************************************************** +// +//! \brief Send a master data receive request when the master have obtained +//! control of the bus.(Write Step2) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! After the master obtained control of the bus(have called +//! I2CMasterReadRequestS1() without any error), and haven't release it, users +//! can call this function to continue receive data from slave. +//! +//! If bEndTransmition is xtrue, the receive operation will followed by an +//! negative ACK and STOP condition. +//! +//! Users can call I2CMasterBusy() to check if all the bus transmition +//! complete, then call I2CMasterErr() to check if any error occurs. Then user +//! can get the data by calling I2CMasterDataGet() if there is no error occurs. +//! +//! Then users can call this function to continue receive data from slave. +//! Users call also can I2CMasterStop() to terminate this transmition and +//! release the I2C bus. +//! +//! For this function returns immediately, it is always using in the interrupt +//! hander. +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterReadRequestS2(unsigned long ulBase, xtBoolean bEndTransmition) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + // + // Send the stop if End Transmition. + // + if(bEndTransmition) + { + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_AA; + I2CStopSend(ulBase); + } +} + +//***************************************************************************** +// +//! \brief Send a master data receive request with an NACK when the master have +//! obtained control of the bus(Write Step2). +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function is used to request the last data to receive, and signal the +//! end of the transfer to the slave transmitter. Then the master can repeat +//! START condition, switch to transmit or other slaves without lost control +//! of the bus. +//! +//! Users can call I2CMasterBusy() to check if all the bus transmition +//! complete, then call I2CMasterErr() to check if any error occurs. Then user +//! can get the data by calling I2CMasterDataGet() if there is no error occurs. +//! +//! Users call also can I2CMasterStop() to terminate this transmition and +//! release the I2C bus. +//! +//! For this function returns immediately, it is always using in the interrupt +//! hander. +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterReadLastRequestS2(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + // + // RECEIVE operation with negative ACK(no stop) + // + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_AA; +} + +//***************************************************************************** +// +//! \brief Read a data from a slave when the bus is idle, and waiting for all +//! bus transmiton complete.(Read Step1) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucSlaveAddr is the 7-bit slave address. +//! \param pucData is the buffer where to save the data. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! This function init a new receive transmition. When the master have not obtained +//! control of the bus, This function send request to transmit the START +//! condition, the slave address and the data request, then waiting for all bus +//! transmition complete. +//! +//! If bEndTransmition is xtrue, the receive operation will followed by an +//! negative ACK and STOP condition. +//! +//! Users can then check the return value to see if any error occurs: +//! - \ref I2C_MASTER_ERR_NONE - \b 0, no error +//! - \ref I2C_MASTER_ERR_ADDR_ACK - The transmitted address was not acknowledged +//! - \ref I2C_MASTER_ERR_DATA_ACK - The transmitted data was not acknowledged +//! - \ref I2C_MASTER_ERR_ARB_LOST - The I2C controller lost arbitration. +//! +//! After the master obtained control of the bus, and haven't release it, users +//! can call I2CMasterReadS2() to continue receive data from slave. +//! Users call also can I2CMasterStop() to terminate this transmition and +//! release the I2C bus. +//! +//! This function is usually used in thread mode. +//! +//! \return Returns the master error status. +// +//***************************************************************************** +unsigned long +xI2CMasterReadS1(unsigned long ulBase, + unsigned char ucSlaveAddr, + unsigned char *pucData, + xtBoolean bEndTransmition) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + xASSERT(pucData); + + xI2CMasterReadRequestS1(ulBase, ucSlaveAddr, xfalse); + + xHWREG(ulBase + I2C_CON) |= I2C_CON_AA; + xSysCtlDelay(100); + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + + *pucData = xHWREG(ulBase + I2C_DAT); + + ulStatus = (xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M); + + if (ulStatus != I2C_I2STAT_M_RX_DAT_ACK) + { + ulStatus = xI2CMasterError(ulBase); + I2CStopSend(ulBase); + return ulStatus; + } + if(bEndTransmition) + { + I2CStopSend(ulBase); + } + + // + // return the error status + // + return xI2C_MASTER_ERR_NONE; +} + +//***************************************************************************** +// +//! \brief Read a data from a slave when the master have obtained control of +//! the bus, and waiting for all bus transmiton complete.(Read Step2) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param pucData is the buffer where to save the data. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! After the master obtained control of the bus(have called +//! I2CMasterReadS1() without any error), and haven't release it, users can +//! call this function to continue receive data from the slave. +//! +//! If bEndTransmition is xtrue, the receive operation will followed by an +//! negative ACK and STOP condition. +//! +//! It will be waiting for all bus transmition complete before return. +//! Users can then check the return value to see if any error occurs: +//! - \ref I2C_MASTER_ERR_NONE - \b 0, no error +//! - \ref I2C_MASTER_ERR_ADDR_ACK - The transmitted address was not acknowledged +//! - \ref I2C_MASTER_ERR_DATA_ACK - The transmitted data was not acknowledged +//! - \ref I2C_MASTER_ERR_ARB_LOST - The I2C controller lost arbitration. +//! +//! Then useres can call this function to continue receive data from slave. +//! Users call also can I2CMasterStop() to terminate this transmition and +//! release the I2C bus. +//! +//! This function is usually used in thread mode. +//! +//! \return Returns the master error status. +// +//***************************************************************************** +unsigned long +xI2CMasterReadS2(unsigned long ulBase, + unsigned char *pucData, + xtBoolean bEndTransmition) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xI2CMasterReadRequestS2(ulBase, xfalse); + + if(bEndTransmition) + { + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_AA; + } + + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + + // + // Waiting the I2C controller to be transmited + // + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + *pucData = (unsigned char)xHWREG(ulBase + I2C_DAT); + + // + // Get the Status code + // + ulStatus = (xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M); + + // + // Waiting the I2C controller to be transmited + // + if (ulStatus != I2C_I2STAT_M_RX_DAT_ACK) + { + ulStatus = xI2CMasterError(ulBase); + I2CStopSend(ulBase); + return ulStatus; + } + + if(bEndTransmition) + { + I2CStopSend(ulBase); + } + + // + // return the error status + // + return xI2C_MASTER_ERR_NONE; +} + +//***************************************************************************** +// +//! \brief Read some data from a slave when the bus is idle, and waiting for all +//! bus transmiton complete.(Read Buffer Step1) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucSlaveAddr is the 7-bit slave address. +//! \param pucDataBuf is the buffer where to save the data. +//! \param ulLen is the data number to receive. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! This function init a new data buffer receive transmition. When the master +//! have not obtained control of the bus, This function send request to transmit +//! the START condition, the slave address and the data request, then waiting for +//! the data transmition complete, and continue next data transmition, until all +//! complete. If there is any error occurs, the remain data will be canceled. +//! +//! If bEndTransmition is xtrue, the receive operation will followed by an +//! negative ACK and STOP condition. +//! +//! Users can then check the return value to see how many datas have been +//! successfully received. if the number != ulLen, user can call +//! I2CMasterErr() to see what error occurs. +//! +//! After the master obtained control of the bus, and haven't release it, users +//! can call I2CMasterReadS2() or I2CMasterReadBufS2() to continue receive data . +//! from slave .Users call also can I2CMasterStop() to terminate this transmition +//! and release the I2C bus. +//! +//! This function is usually used in thread mode. +//! +//! \return Returns the data number that have been successully received. +// +//***************************************************************************** +unsigned long +xI2CMasterReadBufS1(unsigned long ulBase, unsigned char ucSlaveAddr, + unsigned char* pucDataBuf, unsigned long ulLen, + xtBoolean bEndTransmition) +{ + unsigned long ulStatus,ulStatusStart; + unsigned long ulRead; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + xASSERT(pucDataBuf); + + if(ulLen == 0) + return 0; + + else if(ulLen == 1) + { + ulStatus = xI2CMasterReadS1(ulBase, ucSlaveAddr, + pucDataBuf, bEndTransmition); + + if (ulStatus == xI2C_MASTER_ERR_NONE) + { + pucDataBuf[0] = xHWREG(ulBase + I2C_DAT); + + return 1; + } + else + { + return 0; + } + } + + xHWREG(ulBase + I2C_CON) |= I2C_CON_AA; + + // + // Send start and address + // + ulStatusStart = I2CStartSend(ulBase); + if(!((ulStatusStart == I2C_I2STAT_M_TX_START) || + (ulStatusStart == I2C_I2STAT_M_TX_RESTART))) + { + I2CStopSend(ulBase); + return 0; + } + // + // Send address + // + //ulStatus = I2CByteSend(ulBase, (ucSlaveAddr << 1) | 1) ; + // + // Make sure start bit is not active,but do not clear SI + // + if (xHWREG(ulBase + I2C_CON) & I2C_CON_STA) + { + xHWREG(ulBase + I2C_CON) &= ~(I2C_CON_STA | I2C_CON_SI); + } + + // + // Send data to I2C BUS + // + xHWREG(ulBase + I2C_DAT) = (ucSlaveAddr << 1) | 1; + + // + // Make sure AA and EI bit is not active,and clear SI + // + xHWREG(ulBase + I2C_CON) &= ~(I2C_CON_EI); + + // + // Wait the SI be set again by hardware + // + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + + // + // Return the i2c status + // + ulStatus = (xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M); + if(!(ulStatus == I2C_I2STAT_M_RX_SLAR_ACK)) + { + I2CStopSend(ulBase); + return 0; + } + + // + // Waiting the I2C controller to be transmited + // + //xI2CMasterReadRequestS1(ulBase, ucSlaveAddr, xfalse); + if(ulStatusStart == I2C_I2STAT_M_TX_RESTART) + { + xHWREG(ulBase + I2C_CON) |= I2C_CON_AA; + } + xSysCtlDelay(100); + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + + pucDataBuf[0] = xHWREG(ulBase + I2C_DAT); + + //ulStatus = I2CByteGet(ulBase, &pucDataBuf[0], 1); + + ulRead = 1; + ulRead += xI2CMasterReadBufS2(ulBase, + &pucDataBuf[1], + ulLen - 1, + bEndTransmition); + + return ulRead; +} + +//***************************************************************************** +// +//! \brief Read some data from a slave when the master have obtained control of +//! the bus, and waiting for all bus transmiton complete.(Write Buffer Step2) +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucSlaveAddr is the 7-bit slave address. +//! \param pucDataBuf is the buffer where to save the data. +//! \param ulLen is the data number to receive. +//! \param bEndTransmition is flag to control if transmit the STOP condition and +//! terminate this transmition. +//! +//! After the master obtained control of the bus(have called +//! I2CMasterReadS1() or I2CMasterReadBufS1() without any error), and haven't +//! release it, users can call this function to continue receive data from slave. +//! +//! This function receive data one by one from the slave, waiting for every +//! data transmition complete, and continue next data transmition, until all +//! complete. If there is any error occurs, the remain data will be canceled. +//! +//! If bEndTransmition is xtrue, the receive operation will followed by an +//! negative ACK and STOP condition. +//! +//! Users can then check the return value to see how many datas have been +//! successfully received. if the number != ulLen, user can call +//! I2CMasterErr() to see what error occurs. +//! +//! After the master obtained control of the bus, and haven't release it, users +//! can call I2CMasterReadS2() or I2CMasterReadBufS2() to continue receive data +//! from slave. Users call also can I2CMasterStop() to terminate this transmition +//! and release the I2C bus. +//! +//! This function is usually used in thread mode. +//! +//! \return Returns the data number that have been successully received. +// +//***************************************************************************** +unsigned long +xI2CMasterReadBufS2(unsigned long ulBase, unsigned char *pucDataBuf, + unsigned long ulLen, xtBoolean bEndTransmition) +{ + unsigned long i; + unsigned long ulStatus; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + xASSERT(pucDataBuf); + + if(ulLen == 0) + return 0; + + for(i = 0; i < ulLen - 1; i++) + { + // + // Issue an ACK signal for next data frame + // + ulStatus = I2CByteGet(ulBase, pucDataBuf++, 1); + if (ulStatus != I2C_I2STAT_M_RX_DAT_ACK) + { + I2CStopSend(ulBase); + return i; + } + } + + if(bEndTransmition) + { + xHWREG(ulBase + I2C_CON) &= ~(I2C_CON_AA|I2C_CON_SI); + } + + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; + + while (!(xHWREG(ulBase + I2C_CON) & I2C_CON_SI)); + + *pucDataBuf = xHWREG(ulBase + I2C_DAT); + + if(bEndTransmition) + { + I2CStopSend(ulBase); + } + + return ulLen; +} + +//***************************************************************************** +// +//! \brief Set the clock rate of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! \param ucSlaveAddr specifies the slave address. +//! \param ulGeneralCall specifies enable General Call function or not. +//! +//! This function is to Set 4 7-bit slave addresses and enable General Call +//! function of specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! The \e ucSlaveAddr is the I2C slave address,There are 4 slave addrss. +//! The ucSlaveAddr can be a 7-bit value. +//! +//! The \e ulGeneralCall is to enable the General Call function or not. +//! The ulGeneralCall can be one of the following values: +//! \b I2C_GENERAL_CALL_EN,\b I2C_GENERAL_CALL_DIS. +//! +//! \note this is only for slave +//! +//! \return None. +// +//***************************************************************************** +void +xI2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr, + unsigned long ulGeneralCall) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xSysCtlPeripheralReset(xSYSCTL_PERIPH_I2C0); + + xHWREG(ulBase + I2C_CON) = I2C_CON_ENS1; + + xHWREG(ulBase + I2C_CON) = 0; + + xHWREG(ulBase + I2C_ADDR0) = (ucSlaveAddr << 1) | ulGeneralCall; + + xHWREG(ulBase + I2C_CON) = I2C_CON_ENS1; + xHWREG(ulBase + I2C_CON) |= I2C_CON_AA; +} + +//***************************************************************************** +// +//! \brief Slave Send a byte to I2C bus. +//! This function is to send a byte on specified I2C BUS. +//! +//! \param [in] ulBase is the I2C module base address. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \param [in] ucData specifies the data which will send to I2C BUS. +//! +//! \return None. +//! +//! \note This is only for slave +// +//***************************************************************************** +void xI2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) +{ + xI2CMasterDataPut(ulBase, ucData); +} + +//***************************************************************************** +//! \brief Slave receive a byte to I2C bus. +//! This function is to receive a byte on specified I2C BUS. +//! +//! \param [in] ulBase is the I2C module base address. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \return None. +//! +//! \note This is only for slave +// +//***************************************************************************** +unsigned long xI2CSlaveDataGet(unsigned long ulBase) +{ + return xI2CMasterDataGet(ulBase); +} + +//***************************************************************************** +// +//! \brief Set the slave address of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! \param ucSlaveNum specifies the salve address number. +//! \param ucSlaveAddr specifies the slave address. +//! \param ulGeneralCall specifies enable General Call function or not. +//! +//! This function is to Set 4 7-bit slave addresses and enable General Call +//! function of specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! The \e ucSlaveNum is the I2C slave address number,There are 4 slave addrss,so +//! The ucSlaveNum can be: \b 0, \b 1, \b 2, \b 3. +//! +//! The \e ucSlaveAddr is the I2C slave address,There are 4 slave addrss. +//! The ucSlaveAddr can be a 7-bit value. +//! +//! The \e ulGeneralCall is to enable the General Call function or not. +//! The ulGeneralCall can be one of the following values: +//! \b I2C_GENERAL_CALL_EN,\b I2C_GENERAL_CALL_DIS. +//! +//! \note this is only for slave +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveOwnAddressSet(unsigned long ulBase, unsigned char ucSlaveNum, + unsigned char ucSlaveAddr, unsigned long ulGeneralCall) +{ + unsigned long ulTemp[4] = {0x04, 0x18, 0x1C, 0x20}; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + // + // Check the arguments. + // + xASSERT((ucSlaveNum == 0) || (ucSlaveNum == 1) || + (ucSlaveNum == 2) || (ucSlaveNum == 3)); + + // + // Check the arguments. + // + xASSERT((ulGeneralCall == I2C_GENERAL_CALL_EN) || + (ulGeneralCall == I2C_GENERAL_CALL_DIS)); + + + xHWREG(ulBase + ulTemp[ucSlaveNum]) |= ((ucSlaveAddr << 1) | + ulGeneralCall); +} + +//***************************************************************************** +// +//! \brief Set 4 7-bit slave address mask of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! \param ucSlaveNum specifies the salve address number. +//! \param ucSlaveAddrMask specifies the slave address mask. +//! +//! This function is to Set 4 7-bit slave address mask +//! of specified I2C port.The corresponding address bit is "Don't Care" +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! The \e ucSlaveNum is the I2C slave address number,There are 4 slave addrss,so +//! The ucSlaveNum can be: \b 0, \b 1, \b 2, \b 3. +//! +//! The \e ucSlaveAddrMask is the I2C slave address mask,There are 4 slave addrss. +//! The ucSlaveAddrMask can be a 7-bit value. +//! +//! \note this is only for slave +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveOwnAddressMaskSet(unsigned long ulBase, + unsigned char ucSlaveNum, + unsigned char ucSlaveAddrMask) +{ + unsigned long ulTemp[4] = {0x24, 0x28, 0x2C, 0x30}; + + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + // + // Check the arguments. + // + xASSERT((ucSlaveNum == 0) || (ucSlaveNum == 1) || + (ucSlaveNum == 2) || (ucSlaveNum == 3)); + + xHWREG(ulBase + ulTemp[ucSlaveNum]) |= (ucSlaveAddrMask << 1); +} + +//***************************************************************************** +// +//! \brief Get I2C status of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to get I2C status of the specified I2C port. +//! There are 26 status codes. Please refer to Xi2c.h AU9110_I2C_STATUS_Type +//! in detail. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return I2C status. +// +//***************************************************************************** +unsigned long +I2CStatusGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + return (xHWREG(ulBase + I2C_STATUS) & I2C_STATUS_M); +} + +//***************************************************************************** +// +//! \brief Enable I2C interrupt of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to enable I2C interrupt of the specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterIntEnable(unsigned long ulBase, unsigned long ulIntType) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) |= I2C_CON_EI; + xIntEnable(xINT_I2C0); +} + +//***************************************************************************** +// +//! \brief Enables the I2C Slave interrupt. +//! +//! \param [in] ulBase is the I2C module base address. +//! - \ref xI2C0_BASE +//! +//! \param [in] ulIntType is the interrupt type of the I2C module. +//! This value can be one of the following value: +//! - \ref xI2C_SLAVE_INT_STOP +//! - \ref xI2C_SLAVE_INT_DATA +//! +//! \return None. +// +//***************************************************************************** +void +xI2CSlaveIntEnable(unsigned long ulBase, unsigned long ulIntType) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) |= I2C_CON_EI; +} + +//***************************************************************************** +// +//! \brief Init interrupts callback for the specified Port. +//! +//! \param ulPort is the base address of the I2C port. +//! \param xtI2CCallback is callback for the specified Port. +//! +//! Init interrupts callback for the specified Port. +//! +//! \return None. +// +//***************************************************************************** +void +xI2CIntCallbackInit(unsigned long ulBase, xtEventCallback xtI2CCallback) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + g_pfnI2CHandlerCallbacks[I2CNumGet(ulBase)] = xtI2CCallback; +} + +//***************************************************************************** +// +//! \brief Disable I2C interrupt of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to disable I2C interrupt of the specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterIntDisable(unsigned long ulBase, unsigned long ulIntType) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_EI; +} + +//***************************************************************************** +// +//! \brief Disables the I2C Slave interrupt. +//! +//! \param [in] ulBase is the I2C module base address. +//! - \ref xI2C0_BASE +//! +//! \param [in] ulIntType is the interrupt type of the I2C module. +//! This value can be one of the following value: +//! - \ref xI2C_SLAVE_INT_STOP +//! - \ref xI2C_SLAVE_INT_DATA +//! +//! \return None. +// +//***************************************************************************** +void +xI2CSlaveIntDisable(unsigned long ulBase, unsigned long ulIntType) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_EI; +} + +//***************************************************************************** +// +//! \brief Get the I2C interrupt flag of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to get the I2C interrupt flag of the specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return a xtBoolean value xtrue or xfalse. +// +//***************************************************************************** +unsigned long +xI2CMasterIntFlagGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + return ((xHWREG(ulBase + I2C_CON) & I2C_CON_SI) ? xtrue : xfalse); +} + +//***************************************************************************** +// +//! Gets the current I2C Slave status. +//! +//! \param ulBase is the base address of the I2C module. +//! - \ref xI2C0_BASE +//! +//! This function reads the bytes of data from the I2C Slave status Register. +//! +//! \return Returns the bytes(unsigned long) of I2C Slave status Register. +// +//***************************************************************************** +unsigned char xI2CSlaveIntFlagGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + return ((xHWREG(ulBase + I2C_CON) & I2C_CON_SI) ? xtrue : xfalse); +} +//***************************************************************************** +// +//! \brief Enable I2C master module of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to enable I2C module of the specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) |= I2C_CON_ENS1; +} + +//***************************************************************************** +// +//! \brief Enables the I2C Slave block. +//! This will enable operation of the I2C Slave block. +//! +//! \param [in] ulBase is the I2C module base address. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \return None. +// +//***************************************************************************** +void xI2CSlaveEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) |= I2C_CON_ENS1; +} + +//***************************************************************************** +// +//! \brief Disable I2C master module of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to disable I2C module of the specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xI2CMasterDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_ENS1; +} + +//***************************************************************************** +// +//! \brief Disables the I2C slave block. +//! This will disable operation of the I2C slave block. +//! +//! \param [in] ulBase is the I2C module base address. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \return None. +// +//***************************************************************************** +void xI2CSlaveDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) &= ~I2C_CON_ENS1; +} +//***************************************************************************** +// +//! \brief Get the I2C time out flag of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to get the I2C time out flag of the specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return a xtBoolean value xtrue or xfalse. +// +//***************************************************************************** +xtBoolean +I2CTimeoutFlagGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + return ((xHWREG(ulBase + I2C_TOC) & I2C_TOC_TIF) ? xtrue : xfalse); +} + +//***************************************************************************** +// +//! \brief Clear the I2C interrupt flag of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to clear the I2C interrupt flag of the specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +I2CIntFlagClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_CON) |= I2C_CON_SI; +} + +//***************************************************************************** +// +//! \brief Clear the I2C time out flag of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! +//! This function is to clear the I2C time out flag of the specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +I2CTimeoutFlagClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + xHWREG(ulBase + I2C_TOC) |= I2C_TOC_TIF; +} + +//***************************************************************************** +// +//! \brief Enable/Disable I2C 14-bit timeout counter of the specified I2C port. +//! +//! \param ulBase specifies the I2C module base address. +//! \param ulEnable specifies Enable/Disable 14-bit timeout counter. +//! \param ulDiv4 specifies 4 time the 14-bit timeout counter or not. +//! +//! This function is to Enable/Disable I2C 14-bit timeout counter and +//! set div4 bit of timeout counter of the specified I2C port. +//! +//! The \e ulBase can be one of the following values: +//! \b I2C0_BASE. +//! +//! The \e ulEnable can be one of the following values: +//! \b I2C_TIMEOUT_EN, \b I2C_TIMEOUT_DIS. +//! +//! The \e ulDiv4 can be one of the following values: +//! \b I2C_TIMEOUT_DIV4, \b I2C_TIMEOUT_DIV_NO. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +I2CTimeoutCounterSet(unsigned long ulBase, unsigned long ulEnable, + unsigned long ulDiv4) +{ + // + // Check the arguments. + // + xASSERT((ulBase == I2C0_BASE)); + + // + // Check the arguments. + // + xASSERT((ulEnable == I2C_TIMEOUT_EN) || (ulEnable == I2C_TIMEOUT_DIS)); + + // + // Check the arguments. + // + xASSERT((ulDiv4 == I2C_TIMEOUT_DIV4) || (ulDiv4 == I2C_TIMEOUT_DIV_NO)); + + xHWREG(ulBase + I2C_TOC) &= ~0x00000006; + xHWREG(ulBase + I2C_TOC) |= ulEnable | ulDiv4; +} diff --git a/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/libcox/pwm.c b/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/libcox/pwm.c new file mode 100644 index 00000000..886a957e --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/libcox/pwm.c @@ -0,0 +1,1049 @@ +//***************************************************************************** +// +//! \file xpwm.c +//! \brief Driver for the AU9110 PWM +//! \version V2.1.1.1 +//! \date 11/14/2011 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#include "CoX.h" +#include "pwm.h" + +//***************************************************************************** +// +// An array is PWM Callback function point +// +//***************************************************************************** +static xtEventCallback g_pfnPWMHandlerCallbacks[2]={0}; + + +//***************************************************************************** +// +//! \brief The PWMA default IRQ, declared in start up code. +//! +//! \param None. +//! +//! This function is to give a default PWMA IRQ service. +//! +//! \note The Callback function have two effective parameters,One is indicate +//! is a PWM or Capture interrupt.And the other one show which channel have a +//! interrupt,bit0 in ulPWMStastus shows PWM_CHANNEL0,bit1 in ulPWMStastus +//! shows PWM_CHANNEL1,bit2 in ulPWMStastus shows PWM_CHANNEL2 and bit3 in +//! ulPWMStastus shows PWM_CHANNEL3. +//! Only the last four bits(0~3 bits) is effective. +//! +//! \return None. +// +//***************************************************************************** +void +PWMAIntHandler(void) +{ + unsigned long ulPWMStastus; + unsigned long ulCAPStastus0; + unsigned long ulBase = PWMA_BASE; + + // + //! Clear the PWMA INT Flag + // + ulPWMStastus = xHWREG(ulBase + PWM_PIIR) & 0xF; + xHWREG(ulBase + PWM_PIIR) = ulPWMStastus; + + ulCAPStastus0 = xHWREG(ulBase + PWM_CCR0) & 0x100010; + + if (g_pfnPWMHandlerCallbacks[0] != 0) + { + if(ulPWMStastus != 0) + { + g_pfnPWMHandlerCallbacks[0](0, PWM_EVENT_PWM, ulPWMStastus, 0); + } + if(ulCAPStastus0 != 0) + { + ulPWMStastus = 0; + if (ulCAPStastus0 & 0x10) + { + ulPWMStastus |= (1 << PWM_CHANNEL0); + } + if (ulCAPStastus0 & 0x100000) + { + ulPWMStastus |= (1 << PWM_CHANNEL1); + } + g_pfnPWMHandlerCallbacks[0](0, PWM_EVENT_CAP, ulPWMStastus, 0); + } + } + xHWREG(ulBase + PWM_CCR0) |= ulCAPStastus0; +} + +//***************************************************************************** +// +//! \internal +//! \brief Get the PWM module's clock. +//! +//! \param ulBase is the base address of the PWM port. +//! +//! This function is to get the PWM module's clock. +//! +//! +//! \return the PWM module's input clock. +// +//***************************************************************************** +static unsigned long +PWMClockGet(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulTemp; + unsigned long ulPWMFreq; + + ulTemp = ulChannel; + + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulTemp >= 0) || (ulTemp <= 1))); + switch(ulChannel) + { + case PWM_CHANNEL0: + case PWM_CHANNEL1: + ulTemp = ((xHWREG(SYSCLK_CLKSEL1) & SYSCLK_CLKSEL1_PWM01_M) >> + SYSCLK_CLKSEL1_PWM01_S); + break; + default: + break; + } + if (ulTemp == 0) + { + ulPWMFreq = 12000000; + } + else if (ulTemp == 1) + { + ulPWMFreq = 32768; + } + else if (ulTemp == 2) + { + ulPWMFreq = SysCtlHClockGet(); + } + else + { + ulPWMFreq = 22118400; + } + return ulPWMFreq; +} + +//***************************************************************************** +// +//! \brief Initialize and configure the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! \param ulConfig is the configuration of PWM channel. +//! +//! This function is to initialize and configure channel of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! The \e ulConfig parameter is the logical OR of four values: The PWM mode, +//! Inverter or not,and use dead zero or not and dead zone length. +//! \b PWM_ONE_SHOT_MODE,\b PWM_TOGGLE_MODE is the mode selecet. +//! \b PWM_OUTPUT_INVERTER_EN, +//! \b PWM_OUTPUT_INVERTER_DIS is to enable Inverter or not.\b PWM_DEAD_ZONE_EN +//! \b PWM_DEAD_ZONE_DIS is to enable dead zone Generator or not. +//! The dead zone length will be set at the 16~23 bits of the ulConfig. +//! +//! \note When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 +//! becomes a complementary pair for PWM group A and the pair of PWM4 and +//! PWM5 becomes a complementary pair for PWM group B. +//! +//! \return None. +// +//***************************************************************************** +void +xPWMInitConfigure(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig) +{ + unsigned long ulChannelTemp; + + ulChannelTemp = ulChannel; + + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannelTemp >= 0) || (ulChannelTemp <= 1))); + xASSERT((ulConfig & 0xFFFFFF00) == 0); + xASSERT(((ulConfig & PWM_PCR_CH0INV) == PWM_OUTPUT_INVERTER_EN) || + ((ulConfig & PWM_PCR_CH0INV) == PWM_OUTPUT_INVERTER_DIS)); + + xASSERT(((ulConfig & PWM_PCR_CH0MOD) == PWM_ONE_SHOT_MODE) || + ((ulConfig & PWM_PCR_CH0MOD) == PWM_TOGGLE_MODE)); + + xASSERT(((ulConfig & PWM_DEAD_ZONE_EN) == PWM_DEAD_ZONE_EN) || + ((ulConfig & PWM_DEAD_ZONE_EN) == PWM_DEAD_ZONE_DIS)); + + xSysCtlPeripheralReset(xSYSCTL_PERIPH_PWMA); + + xHWREG(ulBase + PWM_PCR) |= ((ulConfig & 0xF) << (ulChannelTemp * 8)); + if (ulConfig & PWM_DEAD_ZONE_EN) + { + xHWREG(ulBase + PWM_PCR) |= (PWM_DEAD_ZONE_EN << (ulChannelTemp >> 1)); + xHWREG(ulBase + PWM_PPR) &= ~(PWM_PPR_DZI01_M << + (ulChannelTemp >> 1) * 8); + xHWREG(ulBase + PWM_PPR) |= ((ulConfig & PWM_PPR_DZI01_M) << + (ulChannelTemp >> 1) * 8); + } +} + + +//***************************************************************************** +// +//! \brief Set the PWM frequency of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! \param ulFrequency is the PWM frequency of PWM channel. +//! +//! This function is to set the PWM frequency of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! The \e ulFrequency parameter can be values: Any values ,ulFrequency > 0 && +//! ulFrequency < PWM module input clock. +//! +//! \note +//! +//! \return the Actual Frequency of PWM, if return 0 . +// +//***************************************************************************** +unsigned long +xPWMFrequencySet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulFrequency) +{ + unsigned long ulFrepDiv; + unsigned long ulActualFrep; + unsigned short usCNRData; + unsigned char ucDivider; + unsigned short usPreScale; + unsigned char i; + + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 1))); + xASSERT(((ulFrequency > 0) || + (ulFrequency <= PWMClockGet(ulBase, ulChannel)))); + + ulFrepDiv = PWMClockGet(ulBase, ulChannel) / ulFrequency; + + xASSERT(ulFrepDiv <= 0x10000000); + + ucDivider = 1; + usPreScale = 1; + + if (ulFrepDiv < 0x100000) + { + i = 0; + while((ulFrepDiv/(ucDivider << i++)) > 65536); + ucDivider = ucDivider << (i - 1); + } + else + { + usPreScale = ulFrepDiv / 65536; + if (ulFrepDiv / usPreScale > 65536) + { + usPreScale++; + } + if (usPreScale > 256) + { + usPreScale = 256; + ulFrepDiv = ulFrepDiv / usPreScale; + ucDivider = ulFrepDiv / 65536; + + if(ulFrepDiv / ucDivider > 65536) + ucDivider++; + i = 0; + while(1) + { + if((1 << i++) > ucDivider) + { + break; + } + } + ucDivider = 1 << (i - 1); + + if (ucDivider > 16) + { + return 0; + } + + ulFrepDiv = ulFrepDiv * usPreScale; + } + } + usCNRData = (unsigned short)(ulFrepDiv / usPreScale / ucDivider); + ulActualFrep = (PWMClockGet(ulBase, ulChannel) / usPreScale / ucDivider / + usCNRData); + + xHWREG(ulBase + PWM_PPR) &= ~(PWM_PPR_CP01_M << (ulChannel / 2)); + xHWREG(ulBase + PWM_PPR) |= ((usPreScale - 1) << (ulChannel / 2)); + + switch(ucDivider) + { + case 1: + ucDivider = PWM_CLOCK_DIV_1; + break; + + case 2: + ucDivider = PWM_CLOCK_DIV_2; + break; + + case 4: + ucDivider = PWM_CLOCK_DIV_4; + break; + + case 8: + ucDivider = PWM_CLOCK_DIV_8; + break; + + case 16: + ucDivider = PWM_CLOCK_DIV_16; + break; + + } + xHWREG(ulBase + PWM_CSR) &= ~(PWM_CSR_CSR0_M << (ulChannel << 2)); + xHWREG(ulBase + PWM_CSR) |= (ucDivider << (ulChannel << 2)); + + xHWREG(ulBase + PWM_CNR0 +(ulChannel * 12)) = usCNRData - 1; + + return ulActualFrep; +} + +//***************************************************************************** +// +//! \brief Set the PWM frequency of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! \param ulConfig is the configuration of PWM channel' frequency. +//! +//! This function is to set the PWM frequency of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! The \e ulConfig parameter is the logical OR of three values: The PreScale +//! value, The Divider value and the PWM Counter Register value. +//! +//! \note +//! +//! \return the Actual Frequency of PWM. +// +//***************************************************************************** +unsigned long +xPWMFrequencyConfig(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE)); + xASSERT(((ulChannel >= 0) || (ulChannel <= 1))); + + xHWREG(ulBase + PWM_PPR) &= ~(PWM_PPR_CP01_M << (ulChannel / 2 * 8)); + xHWREG(ulBase + PWM_PPR) |= (((ulConfig & 0xFF0000) >> 16) + << (ulChannel / 2 * 8)); + + xHWREG(ulBase + PWM_CSR) &= ~(PWM_CSR_CSR0_M << (ulChannel << 2)); + xHWREG(ulBase + PWM_CSR) |= (((ulConfig & 0x7000000) >> 24) + << (ulChannel << 2)); + + xHWREG(ulBase + PWM_CNR0 +(ulChannel * 12)) = (ulConfig & 0xFFFF); + + switch(((ulConfig & 0x7000000) >> 24)) + { + case PWM_CLOCK_DIV_1: + ulChannel = 1; + break; + + case PWM_CLOCK_DIV_2: + ulChannel = 2; + break; + + case PWM_CLOCK_DIV_4: + ulChannel = 4; + break; + + case PWM_CLOCK_DIV_8: + ulChannel = 8; + break; + + case PWM_CLOCK_DIV_16: + ulChannel = 16; + break; + } + + return (PWMClockGet(ulBase, ulChannel) / (((ulConfig & 0xFF0000) >> 16) + 1) + / ulChannel / ((ulConfig & 0xFFFF) + 1)); +} + +//***************************************************************************** +// +//! \brief Set the PWM duty of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! \param ulDuty is the duty of PWM channel. +//! +//! This function is to set the PWM duty of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! The \e ulDuty parameter can be values: duty > 0 && duty <= 100. +//! +//! \note Duty should not be 0; +//! +//! \return None. +// +//***************************************************************************** +void +xPWMDutySet(unsigned long ulBase, unsigned long ulChannel, + unsigned char ulDuty) +{ + unsigned long ulCMRData; + + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 1))); + xASSERT(((ulDuty > 0) || (ulDuty <= 100))); + + ulCMRData = (xHWREG(ulBase + PWM_CNR0 +(ulChannel * 12)) + 1) * + ulDuty / 100 - 1; + if ((xHWREG(ulBase + PWM_CNR0 +(ulChannel * 12)) + 1) *ulDuty / 100 == 0) + { + ulCMRData = 0; + } + xHWREG(ulBase + PWM_CMR0 +(ulChannel * 12)) = ulCMRData; +} + +//***************************************************************************** +// +//! \brief Get the PWM duty of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to get the PWM duty of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return the Actual duty of PWM. +// +//***************************************************************************** +unsigned long +xPWMDutyGet(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulCMRData; + unsigned long ulCNRData; + + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 1))); + + ulCNRData = (xHWREG(ulBase + PWM_CNR0 +(ulChannel * 12))); + ulCMRData = (xHWREG(ulBase + PWM_CMR0 +(ulChannel * 12))); + ulChannel = (ulCMRData + 1) * 100 / (ulCNRData + 1); + return ulChannel; +} + +//***************************************************************************** +// +//! \brief get the PWM frequency of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to get the PWM frequency of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return the Actual Frequency of PWM. +// +//***************************************************************************** +unsigned long +xPWMFrequencyGet(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulCNRData; + unsigned char ucDivider; + unsigned short usPreScale; + + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 1))); + + usPreScale = ((xHWREG(ulBase + PWM_PPR) >> (ulChannel << 2)) & + PWM_CSR_CSR0_M); + + ucDivider = (xHWREG(ulBase + PWM_CSR) >> (ulChannel << 2)) & + PWM_CSR_CSR0_M; + + switch(ucDivider) + { + case PWM_CLOCK_DIV_1: + ucDivider = 1; + break; + + case PWM_CLOCK_DIV_2: + ucDivider = 2; + break; + + case PWM_CLOCK_DIV_4: + ucDivider = 4; + break; + + case PWM_CLOCK_DIV_8: + ucDivider = 8; + break; + + case PWM_CLOCK_DIV_16: + ucDivider = 16; + break; + default: + break; + } + ulCNRData = xHWREG(ulBase + PWM_CNR0 +(ulChannel * 12)); + return (PWMClockGet(ulBase, ulChannel) / (usPreScale + 1) / ucDivider / + ulCNRData); +} + +//***************************************************************************** +// +//! \brief Enable the PWM output of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to enable the PWM output of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xPWMOutputEnable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 1))); + + xHWREG(ulBase + PWM_POE) |= (PWM_POE_PWM0 << (ulChannel)); +} + +//***************************************************************************** +// +//! \brief Disable the PWM output of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to disable the PWM output of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xPWMOutputDisable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 1))); + + xHWREG(ulBase + PWM_POE) &= ~(PWM_POE_PWM0 << (ulChannel)); +} + +//***************************************************************************** +// +//! \brief Start the PWM of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to start the PWM of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xPWMStart(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 1))); + + xHWREG(ulBase + PWM_PCR) |= (PWM_PCR_CH0EN << (ulChannel << 3)); +} + +//***************************************************************************** +// +//! \brief Stop the PWM of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to stop the PWM of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xPWMStop(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 1))); + + xHWREG(ulBase + PWM_PCR) &= ~(PWM_PCR_CH0EN << (ulChannel << 3)); +} + +//***************************************************************************** +// +//! \brief Enable the PWM interrupt of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! \param ulIntType is the PWM channel interrupt type. +//! +//! This function is to enable the PWM interrupt of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! //! The \e ulIntType parameter can be values: +//! \b PWM_INT_CAP_BOTH, \b PWM_INT_CAP_FALL, \b PWM_INT_CAP_RISE and +//! \b PWM_INT_PWM. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xPWMIntEnable(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + xASSERT((ulIntType == PWM_INT_CAP_BOTH) || (ulIntType == PWM_INT_CAP_FALL) || + (ulIntType == PWM_INT_CAP_RISE) || (ulIntType == PWM_INT_PWM)); + + if (ulIntType == PWM_INT_PWM) + { + xHWREG(ulBase + PWM_PIER) |= (PWM_PIER_PWMIE0 << ulChannel); + } + else + { + xHWREG(ulBase + PWM_CCR0 + (ulChannel >> 1)*4) |= + (ulIntType << ((ulChannel % 2) ? 16 : 0)); + } +} + +//***************************************************************************** +// +//! \brief Disable the PWM interrupt of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! \param ulIntType is the PWM channel interrupt type. +//! +//! This function is to disable the PWM interrupt of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! //! The \e ulIntType parameter can be values: +//! \b PWM_INT_CAP_BOTH, \b PWM_INT_CAP_FALL, \b PWM_INT_CAP_RISE and +//! \b PWM_INT_PWM. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +xPWMIntDisable(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + + xASSERT((ulIntType == PWM_INT_CAP_BOTH) || (ulIntType == PWM_INT_CAP_FALL) || + (ulIntType == PWM_INT_CAP_RISE) || (ulIntType == PWM_INT_PWM)); + + if (ulIntType == PWM_INT_PWM) + { + xHWREG(ulBase + PWM_PIER) &= ~(PWM_PIER_PWMIE0 << ulChannel); + } + else + { + xHWREG(ulBase + PWM_CCR0 + (ulChannel >> 1)*4) &= + ~(ulIntType << ((ulChannel % 2) ? 16 : 0)); + } +} + +//***************************************************************************** +// +//! \brief Get the PWM interrupt flag of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! \param ulIntType is the PWM channel interrupt type. +//! +//! This function is to get the PWM interrupt flag of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! //! The \e ulIntType parameter can be values: +//! \b PWM_INT_CAP_BOTH, \b PWM_INT_CAP_FALL, \b PWM_INT_CAP_RISE and +//! \b PWM_INT_PWM. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +xtBoolean +xPWMIntFlagGet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + xASSERT((ulBase == PWMA_BASE) || (ulBase == PWMB_BASE)); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + + xASSERT((ulIntType == PWM_INT_CAP_BOTH) || (ulIntType == PWM_INT_CAP_FALL) || + (ulIntType == PWM_INT_CAP_RISE) || (ulIntType == PWM_INT_PWM)); + + if (ulIntType == PWM_INT_PWM) + { + return ((xHWREG(ulBase + PWM_PIER) & (PWM_PIER_PWMIE0 << ulChannel)) + ? xtrue : xfalse); + } + else + { + return ((xHWREG(ulBase + PWM_CCR0 + (ulChannel << 1)) & + (PWM_CCR0_CAPIF0 << ((ulChannel % 2) ? 16 : 0))) ? xtrue : xfalse); + } +} + +//***************************************************************************** +// +//! \brief Clear the PWM interrupt flag of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! \param ulIntType is the PWM channel interrupt type. +//! +//! This function is to Clear the PWM interrupt flag of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! The \e ulIntType parameter can be values: +//! \b PWM_INT_CAP_BOTH, \b PWM_INT_CAP_FALL, \b PWM_INT_CAP_RISE and +//! \b PWM_INT_PWM. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +PWMIntFlagClear(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + + xASSERT((ulIntType == PWM_INT_CAP_BOTH) || (ulIntType == PWM_INT_CAP_FALL) || + (ulIntType == PWM_INT_CAP_RISE) || (ulIntType == PWM_INT_PWM)); + + if (ulIntType == PWM_INT_PWM) + { + xHWREG(ulBase + PWM_PIIR) |= (PWM_PIER_PWMIE0 << ulChannel); + } + else + { + xHWREG(ulBase + PWM_CCR0 + (ulChannel << 1)) |= + (PWM_CCR0_CAPIF0 << ((ulChannel % 2) ? 16 : 0)) ; + } +} + +//***************************************************************************** +// +//! \brief Init interrupts callback for the PWM timer. +//! +//! \param xtPortCallback is callback for the PWM timer. +//! +//! This function is to init interrupts callback for the PWM timer. +//! +//! \return None. +// +//***************************************************************************** +void +xPWMIntCallbackInit(unsigned long ulBase, xtEventCallback xtPWMCallback) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + + if (xtPWMCallback != 0) + { + if (ulBase == PWMA_BASE) + { + g_pfnPWMHandlerCallbacks[0] = xtPWMCallback; + } + else + { + g_pfnPWMHandlerCallbacks[1] = xtPWMCallback; + } + } +} + +//***************************************************************************** +// +//! \brief Enable the Capture of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to Enable the Capture of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +PWMCAPEnable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + + xHWREG(ulBase + PWM_CCR0 + (ulChannel >> 1)*4) |= + (PWM_CCR0_CAPCH0EN << ((ulChannel % 2) ? 16 : 0)); + xHWREG(ulBase + PWM_PCR) |= (PWM_PCR_CH0EN << (ulChannel << 3)); +} + +//***************************************************************************** +// +//! \brief Disable the Capture of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to disable the Capture of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +PWMCAPDisable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + + xHWREG(ulBase + PWM_CCR0 + (ulChannel >> 1)*4) &= + ~(PWM_CCR0_CAPCH0EN << ((ulChannel % 2) ? 16 : 0)); + xHWREG(ulBase + PWM_PCR) &= ~(PWM_PCR_CH0EN << (ulChannel << 3)); +} + +//***************************************************************************** +// +//! \brief Enable the Capture input of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to enable the Capture input of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +PWMCAPInputEnable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + + xHWREG(ulBase + PWM_CAPENR) |= (PWM_CAPENR_CAPIE_0 << (ulChannel)); +} + +//***************************************************************************** +// +//! \brief Disable the Capture input of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to disable the Capture input of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return None. +// +//***************************************************************************** +void +PWMCAPInputDisable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + + xHWREG(ulBase + PWM_CAPENR) &= ~(PWM_CAPENR_CAPIE_0 << (ulChannel)); +} + +//***************************************************************************** +// +//! \brief Get the Rising Latched PWM counter of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to Get the Rising Latched PWM counter of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return PWM counter when Channel \b ulChannel has rising transition. +// +//***************************************************************************** +unsigned long +PWMCAPRisingCounterGet(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + + return xHWREG(ulBase + PWM_CRLR0 + ulChannel * 8); +} + +//***************************************************************************** +// +//! \brief Get the Falling Latched PWM counter of the PWM module. +//! +//! \param ulBase is the base address of the PWM port. +//! \param ulChannel is the PWM channel. +//! +//! This function is to Get the Falling Latched PWM counter of the PWM module. +//! +//! The \e ulChannel parameter can be values: xPWM_CHANNEL0 or xPWM_CHANNEL1. +//! +//! \note None +//! +//! \return PWM counter when Channel \b ulChannel has Falling transition. +// +//***************************************************************************** +unsigned long +PWMCAPFallingCounterGet(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + xASSERT(ulBase == PWMA_BASE); + xASSERT(((ulChannel >= 0) || (ulChannel <= 3))); + + return xHWREG(ulBase + PWM_CFLR0 + ulChannel * 8); +} diff --git a/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/startup/src/startup_coide.c b/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/startup/src/startup_coide.c index a1f308fb..0fca744b 100644 --- a/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/startup/src/startup_coide.c +++ b/CoX/CoX_Peripheral/CoX_Peripehral_AU9110/startup/src/startup_coide.c @@ -1,481 +1,302 @@ -/** - ****************************************************************************** - * @file startup_Cortex_M4.c - * @author Coocox - * @version V1.0 - * @date 06/06/2014 - * @brief Cortex M4 Devices Startup code. - * This module performs: - * - Set the initial SP - * - Set the vector table entries with the exceptions ISR address - * - Initialize data and bss - * - Call the application's entry point. - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - */ - -//#ifdef __cplusplus -// extern "C" { -//#endif +//***************************************************************************** +// +//! \file startup_coide.c +//! \brief NUC122 Devices Startup code for CooCox CoIDE. +//! This module performs: +//! - Set the initial SP +//! - Set the vector table entries with the exceptions ISR address +//! - Initialize data and bss +//! - Setup the microcontroller system. +//! - Call the application's entry point. +//! . +//! \version V2.1.1.0 +//! \date 7/22/2012 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** -/*----------Stack Configuration-----------------------------------------------*/ -#define STACK_SIZE 0x00000800 /*!< Stack size (in Words) */ +//***************************************************************************** +// +// Stack Configuration +// +//***************************************************************************** +// +// Stack size (in Words) +// +#define STACK_SIZE 0x00000100 __attribute__ ((section(".co_stack"))) unsigned long pulStack[STACK_SIZE]; - - -/*----------Macro definition--------------------------------------------------*/ + #define WEAK __attribute__ ((weak)) +//***************************************************************************** +// +// Declaration of the default fault handlers +// +//***************************************************************************** +void WEAK ResetHandler(void); +void WEAK NMIIntHandler(void); +void WEAK HardFaultIntHandler(void); +void WEAK MemManageIntHandler(void); +void WEAK BusFaultIntHandler(void); +void WEAK UsageFaultIntHandler(void); +void WEAK SVCIntHandler(void); +void WEAK DebugMonIntHandler(void); +void WEAK PendSVIntHandler(void); +void WEAK SysTickIntHandler(void); +void WEAK BODIntHandler(void); +void WEAK WDTIntHandler(void); +void WEAK EINT0IntHandler(void); +void WEAK EINT1IntHandler(void); +void WEAK GPABIntHandler(void); +void WEAK GPCDIntHandler(void); +void WEAK PWMAIntHandler(void); +void WEAK TIMER0IntHandler(void); +void WEAK TIMER1IntHandler(void); +void WEAK TIMER2IntHandler(void); +void WEAK TIMER3IntHandler(void); +void WEAK UART0IntHandler(void); +void WEAK UART1IntHandler(void); +void WEAK SPI0IntHandler(void); +void WEAK SPI1IntHandler(void); +void WEAK I2C0IntHandler(void); +void WEAK USBDIntHandler(void); +void WEAK PS2IntHandler(void); +void WEAK PWRWUIntHandler(void); +void WEAK RTCIntHandler(void); -/*----------Declaration of the default fault handlers-------------------------*/ -/* System exception vector handler */ -__attribute__ ((used)) -void WEAK Reset_Handler(void); -void WEAK NMI_Handler(void); -void WEAK HardFault_Handler(void); -void WEAK MemManage_Handler(void); -void WEAK BusFault_Handler(void); -void WEAK UsageFault_Handler(void); -void WEAK SVC_Handler(void); -void WEAK DebugMon_Handler(void); -void WEAK PendSV_Handler(void); -void WEAK SysTick_Handler(void); +//***************************************************************************** +// +// Symbols defined in linker script +// +//***************************************************************************** +// +// Start address for the initialization values of the .data section. +// +extern unsigned long _sidata; -void WEAK BOD_IRQHandler(void); -void WEAK IRC_IRQHandler(void); -void WEAK PWRWU_IRQHandler(void); -void WEAK SRAMF_IRQHandler(void); -void WEAK CLKF_IRQHandler(void); -void WEAK RTC_IRQHandler(void); -void WEAK TAMPER_IRQHandler(void); -void WEAK EINT0_IRQHandler(void); -void WEAK EINT1_IRQHandler(void); -void WEAK EINT2_IRQHandler(void); -void WEAK EINT3_IRQHandler(void); -void WEAK EINT4_IRQHandler(void); -void WEAK EINT5_IRQHandler(void); -void WEAK EINT6_IRQHandler(void); -void WEAK EINT7_IRQHandler(void); -void WEAK GPA_IRQHandler(void); -void WEAK GPB_IRQHandler(void); -void WEAK GPC_IRQHandler(void); -void WEAK GPD_IRQHandler(void); -void WEAK GPE_IRQHandler(void); -void WEAK GPF_IRQHandler(void); -void WEAK GPG_IRQHandler(void); -void WEAK GPH_IRQHandler(void); -void WEAK GPI_IRQHandler(void); -void WEAK TMR0_IRQHandler(void); -void WEAK TMR1_IRQHandler(void); -void WEAK TMR2_IRQHandler(void); -void WEAK TMR3_IRQHandler(void); -void WEAK PDMA_IRQHandler(void); -void WEAK ADC_IRQHandler(void); -void WEAK WDT_IRQHandler(void); -void WEAK WWDT_IRQHandler(void); -void WEAK EADC0_IRQHandler(void); -void WEAK EADC1_IRQHandler(void); -void WEAK EADC2_IRQHandler(void); -void WEAK EADC3_IRQHandler(void); -void WEAK ACMP_IRQHandler(void); -void WEAK OPA0_IRQHandler(void); -void WEAK OPA1_IRQHandler(void); -void WEAK ICAP0_IRQHandler(void); -void WEAK ICAP1_IRQHandler(void); -void WEAK PWM0CH0_IRQHandler(void); -void WEAK PWM0CH1_IRQHandler(void); -void WEAK PWM0CH2_IRQHandler(void); -void WEAK PWM0CH3_IRQHandler(void); -void WEAK PWM0CH4_IRQHandler(void); -void WEAK PWM0CH5_IRQHandler(void); -void WEAK PWM0_BRK_IRQHandler(void); -void WEAK QEI0_IRQHandler(void); -void WEAK PWM1CH0_IRQHandler(void); -void WEAK PWM1CH1_IRQHandler(void); -void WEAK PWM1CH2_IRQHandler(void); -void WEAK PWM1CH3_IRQHandler(void); -void WEAK PWM1CHCH4_IRQHandler(void); -void WEAK PWM1CH5_IRQHandler(void); -void WEAK PWM1_BRK_IRQHandler(void); -void WEAK QEI1_IRQHandler(void); -void WEAK EPWM0_IRQHandler(void); -void WEAK EPWM0BRK_IRQHandler(void); -void WEAK EPWM1_IRQHandler(void); -void WEAK EPWM1BRK_IRQHandler(void); -void WEAK USBD_IRQHandler(void); -void WEAK USBH_IRQHandler(void); -void WEAK USB_OTG_IRQHandler(void); -void WEAK EMAC_TX_IRQHandler(void); -void WEAK EMAC_RX_IRQHandler(void); -void WEAK SPI0_IRQHandler(void); -void WEAK SPI1_IRQHandler(void); -void WEAK SPI2_IRQHandler(void); -void WEAK SPI3_IRQHandler(void); -void WEAK UART0_IRQHandler(void); -void WEAK UART1_IRQHandler(void); -void WEAK UART2_IRQHandler(void); -void WEAK UART3_IRQHandler(void); -void WEAK UART4_IRQHandler(void); -void WEAK UART5_IRQHandler(void); -void WEAK I2C0_IRQHandler(void); -void WEAK I2C1_IRQHandler(void); -void WEAK I2C2_IRQHandler(void); -void WEAK I2C3_IRQHandler(void); -void WEAK I2C4_IRQHandler(void); -void WEAK SC0_IRQHandler(void); -void WEAK SC1_IRQHandler(void); -void WEAK SC2_IRQHandler(void); -void WEAK SC3_IRQHandler(void); -void WEAK SC4_IRQHandler(void); -void WEAK SC5_IRQHandler(void); -void WEAK CAN0_IRQHandler(void); -void WEAK CAN1_IRQHandler(void); -void WEAK I2S0_IRQHandler(void); -void WEAK I2S1_IRQHandler(void); -void WEAK SD_IRQHandler(void); -void WEAK PS2D_IRQHandler(void); -void WEAK CAP_IRQHandler(void); -void WEAK CRYPTO_IRQHandler(void); -void WEAK CRC_IRQHandler(void); +// +// Start address for the .data section +// +extern unsigned long _sdata; -/*----------Symbols defined in linker script----------------------------------*/ -extern unsigned long _sidata; /*!< Start address for the initialization - values of the .data section. */ -extern unsigned long _sdata; /*!< Start address for the .data section */ -extern unsigned long _edata; /*!< End address for the .data section */ -extern unsigned long _sbss; /*!< Start address for the .bss section */ -extern unsigned long _ebss; /*!< End address for the .bss section */ -extern void _eram; /*!< End address for ram */ +// +// End address for the .data section +// +extern unsigned long _edata; +// +// Start address for the .bss section +// +extern unsigned long _sbss; -/*----------Function prototypes-----------------------------------------------*/ -extern int main(void); /*!< The entry point for the application. */ -void Default_Reset_Handler(void); /*!< Default reset handler */ -static void Default_Handler(void); /*!< Default exception handler */ +// +// End address for the .bss section +// +extern unsigned long _ebss; +// +// End address for ram +// +extern void _eram; -/** - *@brief The minimal vector table for a Cortex M4. Note that the proper constructs - * must be placed on this to ensure that it ends up at physical address - * 0x00000000. - */ -__attribute__ ((used,section(".isr_vector"))) +//***************************************************************************** +// +// Function prototypes +// +//***************************************************************************** +extern int main(void); +void ResetHandler(void); +static void DefaultIntHandler(void); + +// +// The minimal vector table for a Cortex M0. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x00000000. +// +__attribute__ ((section(".isr_vector"))) void (* const g_pfnVectors[])(void) = -{ - /*----------Core Exceptions------------------------------------------------ */ - (void *)&pulStack[STACK_SIZE-1], /*!< The initial stack pointer */ - Reset_Handler, /*!< Reset Handler */ - NMI_Handler, /*!< NMI Handler */ - HardFault_Handler, /*!< Hard Fault Handler */ - MemManage_Handler, /*!< MPU Fault Handler */ - BusFault_Handler, /*!< Bus Fault Handler */ - UsageFault_Handler, /*!< Usage Fault Handler */ - 0,0,0,0, /*!< Reserved */ - SVC_Handler, /*!< SVCall Handler */ - DebugMon_Handler, /*!< Debug Monitor Handler */ - 0, /*!< Reserved */ - PendSV_Handler, /*!< PendSV Handler */ - SysTick_Handler, /*!< SysTick Handler */ - BOD_IRQHandler, - IRC_IRQHandler, - PWRWU_IRQHandler, - SRAMF_IRQHandler, - CLKF_IRQHandler, - 0, - RTC_IRQHandler, - TAMPER_IRQHandler, - EINT0_IRQHandler, - EINT1_IRQHandler, - EINT2_IRQHandler, - EINT3_IRQHandler, - EINT4_IRQHandler, - EINT5_IRQHandler, - EINT6_IRQHandler, - EINT7_IRQHandler, - GPA_IRQHandler, - GPB_IRQHandler, - GPC_IRQHandler, - GPD_IRQHandler, - GPE_IRQHandler, - GPF_IRQHandler, - GPG_IRQHandler, - GPH_IRQHandler, - GPI_IRQHandler, - 0,0,0,0,0,0,0, - TMR0_IRQHandler, - TMR1_IRQHandler, - TMR2_IRQHandler, - TMR3_IRQHandler, - 0,0,0,0, - PDMA_IRQHandler, - 0, - ADC_IRQHandler, - 0,0,0, - WDT_IRQHandler, - WWDT_IRQHandler, - EADC0_IRQHandler, - EADC1_IRQHandler, - EADC2_IRQHandler, - EADC3_IRQHandler, - 0,0,0,0, - ACMP_IRQHandler, - 0,0,0, - OPA0_IRQHandler, - OPA1_IRQHandler, - ICAP0_IRQHandler, - ICAP1_IRQHandler, - PWM0CH0_IRQHandler, - PWM0CH1_IRQHandler, - PWM0CH2_IRQHandler, - PWM0CH3_IRQHandler, - PWM0CH4_IRQHandler, - PWM0CH5_IRQHandler, - PWM0_BRK_IRQHandler, - QEI0_IRQHandler, - PWM1CH0_IRQHandler, - PWM1CH1_IRQHandler, - PWM1CH2_IRQHandler, - PWM1CH3_IRQHandler, - PWM1CHCH4_IRQHandler, - PWM1CH5_IRQHandler, - PWM1_BRK_IRQHandler, - QEI1_IRQHandler, - EPWM0_IRQHandler, - EPWM0BRK_IRQHandler, - EPWM1_IRQHandler, - EPWM1BRK_IRQHandler, - 0,0,0,0, - USBD_IRQHandler, - USBH_IRQHandler, - USB_OTG_IRQHandler, - 0, - EMAC_TX_IRQHandler, - EMAC_RX_IRQHandler, - 0,0, - SPI0_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - SPI3_IRQHandler, - 0,0,0,0, - UART0_IRQHandler, - UART1_IRQHandler, - UART2_IRQHandler, - UART3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - 0,0, - I2C0_IRQHandler, - I2C1_IRQHandler, - I2C2_IRQHandler, - I2C3_IRQHandler, - I2C4_IRQHandler, - 0,0,0, - SC0_IRQHandler, - SC1_IRQHandler, - SC2_IRQHandler, - SC3_IRQHandler, - SC4_IRQHandler, - SC5_IRQHandler, - 0,0, - CAN0_IRQHandler, - CAN1_IRQHandler, - 0,0, - I2S0_IRQHandler, - I2S1_IRQHandler, - 0,0, - SD_IRQHandler, - 0, - PS2D_IRQHandler, - CAP_IRQHandler, - CRYPTO_IRQHandler, - CRC_IRQHandler, - /*----------External Exceptions---------------------------------------------*/ +{ + (void *)&pulStack[STACK_SIZE], // The initial stack pointer + ResetHandler, // The reset handler + NMIIntHandler, // The NMI handler + HardFaultIntHandler, // The hard fault handler + MemManageIntHandler, // The MPU fault handler + BusFaultIntHandler, // The bus fault handler + UsageFaultIntHandler, // The usage fault handler + 0,0,0,0, // Reserved + SVCIntHandler, // SVCall handler + DebugMonIntHandler, // Debug monitor handler + 0, // Reserved + PendSVIntHandler, // The PendSV handler + SysTickIntHandler, // The SysTick handler + BODIntHandler, // Brownout low voltage detected + WDTIntHandler, // Watch Dog Timer + EINT0IntHandler, // External signal interrupt from + // PB.14 pin + EINT1IntHandler, // External signal interrupt from + // PB.15 pin + GPABIntHandler, // External signal interrupt from + // PA[15:0] / PB[13:0] + GPCDIntHandler, // External interrupt from + // PC[15:0]/PD[15:0] + PWMAIntHandler, // PWM0 or PWM2,PWM1 or PWM3 + DefaultIntHandler, // Reserved + TIMER0IntHandler, // Timer 0 + TIMER1IntHandler, // Timer 1 + TIMER2IntHandler, // Timer 2 + TIMER3IntHandler, // Timer 3 + UART0IntHandler, // UART0 + UART1IntHandler, // UART1 + SPI0IntHandler, // SPI0 + SPI1IntHandler, // SPI1 + DefaultIntHandler, // Reserved + DefaultIntHandler, // Reserved + DefaultIntHandler, // Reserved + I2C0IntHandler, // I2C + DefaultIntHandler, // Reserved + DefaultIntHandler, // Reserved + DefaultIntHandler, // Reserved + USBDIntHandler, // USB Device + PS2IntHandler, // PS2 + DefaultIntHandler, // Reserved + DefaultIntHandler, // Reserved + DefaultIntHandler, // Reserved + PWRWUIntHandler, // Clock controller + DefaultIntHandler, // Reserved + DefaultIntHandler, // Reserved + RTCIntHandler, // RTC }; - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None - */ -void Default_Reset_Handler(void) +//***************************************************************************** +// +//! \brief This is the code that gets called when the processor first +//! starts execution following a reset event. +//! +//! \param None. +//! +//! Only the absolutely necessary set is performed, after which the +//! application supplied main() routine is called. +//! +//! \return None. +// +//***************************************************************************** +void Default_ResetHandler(void) { - /* Initialize data and bss */ + // + // Initialize data and bss + // unsigned long *pulSrc, *pulDest; - /* Copy the data segment initializers from flash to SRAM */ + // + // Copy the data segment initializers from flash to SRAM + // pulSrc = &_sidata; for(pulDest = &_sdata; pulDest < &_edata; ) { - *(pulDest++) = *(pulSrc++); + *(pulDest++) = *(pulSrc++); } - - /* Zero fill the bss segment. This is done with inline assembly since this - will clear the value of pulDest if it is not kept in a register. */ - __asm(" ldr r0, =_sbss\n" - " ldr r1, =_ebss\n" - " mov r2, #0\n" - " .thumb_func\n" - "zero_loop:\n" - " cmp r0, r1\n" - " it lt\n" - " strlt r2, [r0], #4\n" - " blt zero_loop"); -#ifdef __FPU_USED - /* Enable FPU.*/ - __asm(" LDR.W R0, =0xE000ED88\n" - " LDR R1, [R0]\n" - " ORR R1, R1, #(0xF << 20)\n" - " STR R1, [R0]"); -#endif + // + // Zero fill the bss segment. + // + for(pulDest = &_sbss; pulDest < &_ebss; ) + { + *(pulDest++) = 0; + } -#ifdef SUPPORT_CPLUSPLUS - extern void __libc_init_array(void); - __libc_init_array(); -#endif - - /* Call the application's entry point.*/ + // + // Call the application's entry point. + // main(); } +//***************************************************************************** +// +// Provide weak aliases for each Exception handler to the DefaultIntHandler. +// As they are weak aliases, any function with the same name will override +// this definition. +// +//***************************************************************************** +#pragma weak ResetHandler = Default_ResetHandler +#pragma weak NMIIntHandler = DefaultIntHandler +#pragma weak HardFaultIntHandler = DefaultIntHandler +#pragma weak MemManageIntHandler = DefaultIntHandler +#pragma weak BusFaultIntHandler = DefaultIntHandler +#pragma weak UsageFaultIntHandler = DefaultIntHandler +#pragma weak SVCIntHandler = DefaultIntHandler +#pragma weak DebugMonIntHandler = DefaultIntHandler +#pragma weak PendSVIntHandler = DefaultIntHandler +#pragma weak SysTickIntHandler = DefaultIntHandler +#pragma weak BODIntHandler = DefaultIntHandler +#pragma weak WDTIntHandler = DefaultIntHandler +#pragma weak EINT0IntHandler = DefaultIntHandler +#pragma weak EINT1IntHandler = DefaultIntHandler +#pragma weak GPABIntHandler = DefaultIntHandler +#pragma weak GPCDIntHandler = DefaultIntHandler +#pragma weak PWMAIntHandler = DefaultIntHandler +#pragma weak TIMER0IntHandler = DefaultIntHandler +#pragma weak TIMER1IntHandler = DefaultIntHandler +#pragma weak TIMER2IntHandler = DefaultIntHandler +#pragma weak TIMER3IntHandler = DefaultIntHandler +#pragma weak UART0IntHandler = DefaultIntHandler +#pragma weak UART1IntHandler = DefaultIntHandler +#pragma weak SPI0IntHandler = DefaultIntHandler +#pragma weak SPI1IntHandler = DefaultIntHandler +#pragma weak I2C0IntHandler = DefaultIntHandler +#pragma weak USBDIntHandler = DefaultIntHandler +#pragma weak PS2IntHandler = DefaultIntHandler +#pragma weak PWRWUIntHandler = DefaultIntHandler +#pragma weak RTCIntHandler = DefaultIntHandler -/** - *@brief Provide weak aliases for each Exception handler to the Default_Handler. - * As they are weak aliases, any function with the same name will override - * this definition. - */ -#pragma weak Reset_Handler = Default_Reset_Handler -#pragma weak NMI_Handler = Default_Handler -#pragma weak HardFault_Handler = Default_Handler -#pragma weak MemManage_Handler = Default_Handler -#pragma weak BusFault_Handler = Default_Handler -#pragma weak UsageFault_Handler = Default_Handler -#pragma weak SVC_Handler = Default_Handler -#pragma weak DebugMon_Handler = Default_Handler -#pragma weak PendSV_Handler = Default_Handler -#pragma weak SysTick_Handler = Default_Handler - -#pragma weak BOD_IRQHandler= Default_Handler -#pragma weak IRC_IRQHandler= Default_Handler -#pragma weak PWRWU_IRQHandler= Default_Handler -#pragma weak SRAMF_IRQHandler= Default_Handler -#pragma weak CLKF_IRQHandler= Default_Handler -#pragma weak RTC_IRQHandler= Default_Handler -#pragma weak TAMPER_IRQHandler= Default_Handler -#pragma weak EINT0_IRQHandler= Default_Handler -#pragma weak EINT1_IRQHandler= Default_Handler -#pragma weak EINT2_IRQHandler= Default_Handler -#pragma weak EINT3_IRQHandler= Default_Handler -#pragma weak EINT4_IRQHandler= Default_Handler -#pragma weak EINT5_IRQHandler= Default_Handler -#pragma weak EINT6_IRQHandler= Default_Handler -#pragma weak EINT7_IRQHandler= Default_Handler -#pragma weak GPA_IRQHandler= Default_Handler -#pragma weak GPB_IRQHandler= Default_Handler -#pragma weak GPC_IRQHandler= Default_Handler -#pragma weak GPD_IRQHandler= Default_Handler -#pragma weak GPE_IRQHandler= Default_Handler -#pragma weak GPF_IRQHandler= Default_Handler -#pragma weak GPG_IRQHandler= Default_Handler -#pragma weak GPH_IRQHandler= Default_Handler -#pragma weak GPI_IRQHandler= Default_Handler -#pragma weak TMR0_IRQHandler= Default_Handler -#pragma weak TMR1_IRQHandler= Default_Handler -#pragma weak TMR2_IRQHandler= Default_Handler -#pragma weak TMR3_IRQHandler= Default_Handler -#pragma weak PDMA_IRQHandler= Default_Handler -#pragma weak ADC_IRQHandler= Default_Handler -#pragma weak WDT_IRQHandler= Default_Handler -#pragma weak WWDT_IRQHandler= Default_Handler -#pragma weak EADC0_IRQHandler= Default_Handler -#pragma weak EADC1_IRQHandler= Default_Handler -#pragma weak EADC2_IRQHandler= Default_Handler -#pragma weak EADC3_IRQHandler= Default_Handler -#pragma weak ACMP_IRQHandler= Default_Handler -#pragma weak OPA0_IRQHandler= Default_Handler -#pragma weak OPA1_IRQHandler= Default_Handler -#pragma weak ICAP0_IRQHandler= Default_Handler -#pragma weak ICAP1_IRQHandler= Default_Handler -#pragma weak PWM0CH0_IRQHandler= Default_Handler -#pragma weak PWM0CH1_IRQHandler= Default_Handler -#pragma weak PWM0CH2_IRQHandler= Default_Handler -#pragma weak PWM0CH3_IRQHandler= Default_Handler -#pragma weak PWM0CH4_IRQHandler= Default_Handler -#pragma weak PWM0CH5_IRQHandler= Default_Handler -#pragma weak PWM0_BRK_IRQHandler= Default_Handler -#pragma weak QEI0_IRQHandler= Default_Handler -#pragma weak PWM1CH0_IRQHandler= Default_Handler -#pragma weak PWM1CH1_IRQHandler= Default_Handler -#pragma weak PWM1CH2_IRQHandler= Default_Handler -#pragma weak PWM1CH3_IRQHandler= Default_Handler -#pragma weak PWM1CHCH4_IRQHandler= Default_Handler -#pragma weak PWM1CH5_IRQHandler= Default_Handler -#pragma weak PWM1_BRK_IRQHandler= Default_Handler -#pragma weak QEI1_IRQHandler= Default_Handler -#pragma weak EPWM0_IRQHandler= Default_Handler -#pragma weak EPWM0BRK_IRQHandler= Default_Handler -#pragma weak EPWM1_IRQHandler= Default_Handler -#pragma weak EPWM1BRK_IRQHandler= Default_Handler -#pragma weak USBD_IRQHandler= Default_Handler -#pragma weak USBH_IRQHandler= Default_Handler -#pragma weak USB_OTG_IRQHandler= Default_Handler -#pragma weak EMAC_TX_IRQHandler= Default_Handler -#pragma weak EMAC_RX_IRQHandler= Default_Handler -#pragma weak SPI0_IRQHandler= Default_Handler -#pragma weak SPI1_IRQHandler= Default_Handler -#pragma weak SPI2_IRQHandler= Default_Handler -#pragma weak SPI3_IRQHandler= Default_Handler -#pragma weak UART0_IRQHandler= Default_Handler -#pragma weak UART1_IRQHandler= Default_Handler -#pragma weak UART2_IRQHandler= Default_Handler -#pragma weak UART3_IRQHandler= Default_Handler -#pragma weak UART4_IRQHandler= Default_Handler -#pragma weak UART5_IRQHandler= Default_Handler -#pragma weak I2C0_IRQHandler= Default_Handler -#pragma weak I2C1_IRQHandler= Default_Handler -#pragma weak I2C2_IRQHandler= Default_Handler -#pragma weak I2C3_IRQHandler= Default_Handler -#pragma weak I2C4_IRQHandler= Default_Handler -#pragma weak SC0_IRQHandler= Default_Handler -#pragma weak SC1_IRQHandler= Default_Handler -#pragma weak SC2_IRQHandler= Default_Handler -#pragma weak SC3_IRQHandler= Default_Handler -#pragma weak SC4_IRQHandler= Default_Handler -#pragma weak SC5_IRQHandler= Default_Handler -#pragma weak CAN0_IRQHandler= Default_Handler -#pragma weak CAN1_IRQHandler= Default_Handler -#pragma weak I2S0_IRQHandler= Default_Handler -#pragma weak I2S1_IRQHandler= Default_Handler -#pragma weak SD_IRQHandler= Default_Handler -#pragma weak PS2D_IRQHandler= Default_Handler -#pragma weak CAP_IRQHandler= Default_Handler -#pragma weak CRYPTO_IRQHandler= Default_Handler -#pragma weak CRC_IRQHandler= Default_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, - * preserving the system state for examination by a debugger. - * @param None - * @retval None - */ -static void Default_Handler(void) +//***************************************************************************** +// +//! \brief This is the code that gets called when the processor receives an +//! unexpected interrupt. +//! +//! \param None. +//! +//! This simply enters an infinite loop, preserving the system state for +//! examination by a debugger. +//! +//! \return None. +//***************************************************************************** +static void DefaultIntHandler(void) { - /* Go into an infinite loop. */ - while (1) + // + // Go into an infinite loop. + // + while (1) { } -} - -//#ifdef __cplusplus -//} -//#endif - -/*********************** (C) COPYRIGHT 2014 Coocox ************END OF FILE*****/ +} \ No newline at end of file diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/gpio.c b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/gpio.c new file mode 100644 index 00000000..84160538 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/gpio.c @@ -0,0 +1,937 @@ +//***************************************************************************** +// +//! \file gpio.c +//! \brief Driver for the GPIO controller +//! \version V3.0.0.0 +//! \date 8/15/2014 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2014, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#include "CoX.h" +#include "hw_gpio.h" +#include "hw_sysctl.h" + +//***************************************************************************** +// +// An array is Watchdog callback function point +// +//***************************************************************************** +static xtEventCallback g_psGPIOPinIntAssignTable[64] = +{ + 0, +}; + +//***************************************************************************** +// +//! \brief GPIO interrupt handler. +//! This function is the GPIO interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +//! \note EINT3 channel is shared with GPIO interrupts. +// +//***************************************************************************** +void EINT3IntHandler(void) +{ + unsigned long i = 0; + + //Find and call any interrupt function. + for(i = 0; i < 64; i++) + { + if(g_psGPIOPinIntAssignTable[i]) + { + g_psGPIOPinIntAssignTable[i](0,0,0,0); + } + } +} + +//***************************************************************************** +// +//! \internal +//! \brief This function convert gpio ID to the number of the gpio. +//! For example: +//! +//! GPIO_PIN_1 --> 1 +//! GPIO_PIN_5 --> 5 +//! +//! \param [in] ulPin is the gpio id, which can be one of the following vaule: +//! - \ref GPIO_PIN_0 +//! - \ref GPIO_PIN_1 +//! - ... +//! - \ref GPIO_PIN_31 +//! +//! \return The number of GPIO. +//! \note If call this function with wrong parameter, it will exit with -1. +//! +// +//***************************************************************************** +static unsigned long PinIDToPos(unsigned long ulPin) +{ + unsigned long i = 0; + unsigned long ulFlag = 0; + + for(i = 0; i < 32; i++) + { + ulFlag = 0x01 << i; + if(ulPin & ulFlag) + { + return (i); + } + } + + return (-1); +} + +//***************************************************************************** +// +//! \brief Get the GPIO port from a Pin. +//! +//! \param [in] eShortPin is the base address of the GPIO port +//! +//! \return GPIO port code, which is one of the following value: +//! - \ref xSYSCTL_PERIPH_GPIOC +//! - \ref xSYSCTL_PERIPH_I2C1 +//! - ... +//! - \ref xSYSCTL_PERIPH_TIMER2 +//! - \ref xSYSCTL_PERIPH_TIMER3 +//! +//! which can be used in those functions: +//! - \ref xSysCtlPeripheralEnable +//! - \ref xSysCtlPeripheralDisable +//! - \ref xSysCtlPeripheralReset +// +//***************************************************************************** +unsigned long GPIOPinToPeripheralId(unsigned long ulPort, unsigned long ulPin) +{ + + switch (ulPort) + { + case GPIOA_BASE: + { + return (xSYSCTL_PERIPH_GPIOA); + break; + } + case GPIOB_BASE: + { + return (xSYSCTL_PERIPH_GPIOB); + break; + } + case GPIOC_BASE: + { + return (xSYSCTL_PERIPH_GPIOC); + break; + } + case GPIOD_BASE: + { + return (xSYSCTL_PERIPH_GPIOD); + break; + } + case GPIOE_BASE: + { + return (xSYSCTL_PERIPH_GPIOE); + break; + } + } + + return (0); // Error +} + +//***************************************************************************** +// +//! \brief Get the GPIO port from a short Pin. +//! +//! \param [in] eShortPin is the base address of the GPIO port +//! +//! \return GPIO port address which is used by GPIO API. +// +//***************************************************************************** +unsigned long GPIOPinToPort(unsigned long ulPort, unsigned long ulPin) +{ + + return (ulPort); +} + +//***************************************************************************** +// +//! \brief Get the GPIO pin number from a short Pin. +//! +//! \param [in] eShortPin is the base address of the GPIO port +//! +//! \return GPIO pin number which is used by GPIO API. +// +//***************************************************************************** +unsigned long GPIOPinToPin(unsigned long ulPort, unsigned long ulPin) +{ + + return (ulPin); +} + + +//***************************************************************************** +// +//! \brief Configure GPIO function. +//! This function map gpio to special function. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! \param [in] ulPins is the bit-packed representation of the pin(s). +//! \param [in] ulCfg is the GPIO configure parameter, which can be one of +//! the following value; +//! - \ref GPIO_PA0_PA0 +//! - \ref GPIO_PA0_RD1 +//! - \ref GPIO_PA0_UART3TX +//! - \ref GPIO_PA0_I2C1SDA +//! ... and so on, more information, please reference GPIO +//! alterfunction. +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinFunCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulCfg) +{ + unsigned long ulRegAddr = 0; + unsigned long ulTmpReg = 0; + + switch(ulPort) + { + case GPIOA_BASE: // Port 0 + { + ulRegAddr = PINSEL0; + break; + } + case GPIOB_BASE: // Port 1 + { + ulRegAddr = PINSEL2; + break; + } + case GPIOC_BASE: // Port 2 + { + ulRegAddr = PINSEL4; + break; + } + case GPIOD_BASE: // Port 3 + { + ulRegAddr = PINSEL6; + break; + } + case GPIOE_BASE: // Port 4 + { + ulRegAddr = PINSEL8; + break; + } + default: + { + //while(1); // Error + } + } + + ulPin = PinIDToPos(ulPin); + // Select Pin ID + if(ulPin >= 16) + { + ulPin -= 16; + ulRegAddr += 4; + } + + // Read --> Modify --> WriteBack + ulTmpReg = xHWREG(PIN_CON_BASE + ulRegAddr); + ulTmpReg &= ~(0x03 << (2*ulPin)); + ulTmpReg |= ulCfg; + xHWREG(PIN_CON_BASE + ulRegAddr) = ulTmpReg; + +} + +//***************************************************************************** +// +//! \brief Configure GPIO mode. +//! This function configure gpio mode, includes open-drain/pull-push/ +//! input/output. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! \param [in] ulPins is the bit-packed representation of the pin(s). +//! \param [in] ulCfg is the GPIO configure parameter, which can be one of +//! the following value; +//! - \ref PIN_MODE_OD_DIS +//! - \ref PIN_MODE_OD_EN +//! - \ref PIN_MODE_PULL_UP +//! - \ref PIN_MODE_REPEATER +//! - \ref PIN_MODE_NONE +//! - \ref PIN_MODE_PULL_DOWN +//! - \ref PIN_MODE_INPUT +//! - \ref PIN_MODE_OUTPUT +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinModeCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulCfg) +{ + unsigned long ulRegAddr = 0; + unsigned long ulTmp = 0; + unsigned long ulTmpReg = 0; + unsigned long ulTmpMode = 0; + + /******************* Configure Input/Output Mode ****************/ + if(ulCfg & BIT_32_1) // Need to configure Input/Output Mode. + { + if(ulCfg & BIT_32_0) // OutPut Mode. + { + xHWREG(ulPort + FIODIR) |= ulPin; + } + else // Input Mode + { + xHWREG(ulPort + FIODIR) &= ~ulPin; + } + } + + /***************** Configure pull-up/pull-down Resister ****************/ + if(ulCfg & BIT_32_4) // Need to configure Pull-up/Pull-down + { + switch(ulPort) // + { + case GPIOA_BASE: + { + ulRegAddr = PINMODE0; + break; + } + case GPIOB_BASE: + { + ulRegAddr = PINMODE2; + break; + } + case GPIOC_BASE: + { + ulRegAddr = PINMODE4; + break; + } + case GPIOD_BASE: + { + ulRegAddr = PINMODE6; + break; + } + case GPIOE_BASE: + { + ulRegAddr = PINMODE8; + break; + } + } + + ulTmp = PinIDToPos(ulPin); + if(ulTmp >= 16) + { + ulRegAddr += 4; + ulTmp -= 16; + } + + ulTmpReg = xHWREG(PIN_CON_BASE + ulRegAddr); + ulTmpReg &= ~((unsigned long)0x03<< (2*ulTmp)); + ulTmpMode = ulCfg & BIT_MASK(32, 3, 2); + ulTmpMode = (ulTmpMode >> 2) << (2 * ulTmp); + ulTmpReg |= ulTmpMode; + xHWREG(PIN_CON_BASE + ulRegAddr) = ulTmpReg; + + } + + /************************** Configure OD Mode **************************/ + if(ulCfg & BIT_32_6) // Configure OD + { + switch(ulPort) + { + case GPIOA_BASE: + { + ulRegAddr = PINMODE_OD0; + break; + } + case GPIOB_BASE: + { + ulRegAddr = PINMODE_OD1; + break; + } + case GPIOC_BASE: + { + ulRegAddr = PINMODE_OD2; + break; + } + case GPIOD_BASE: + { + ulRegAddr = PINMODE_OD3; + break; + } + case GPIOE_BASE: + { + ulRegAddr = PINMODE_OD4; + break; + } + } + + if(ulCfg & BIT_32_5) // OD Enable + { + xHWREG(PIN_CON_BASE + ulRegAddr) |= ulPin; + } + else // OD Disable + { + xHWREG(PIN_CON_BASE + ulRegAddr) &= ~ulPin; + } + } +} + +//***************************************************************************** +// +//! \brief Write 1 to gpio pins. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! \param [in] ulPins is the bit-packed representation of the pin(s). +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinSet(unsigned long ulPort, unsigned long ulPins) +{ + xHWREG(ulPort + FIOMASK) =~ulPins; + xHWREG(ulPort + FIOSET) = ulPins; +} + +//***************************************************************************** +// +//! \brief Write 0 to gpio pins. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! \param [in] ulPins is the bit-packed representation of the pin(s). +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinClr(unsigned long ulPort, unsigned long ulPins) +{ + xHWREG(ulPort + FIOMASK) =~ulPins; + xHWREG(ulPort + FIOCLR) = ulPins; +} + +//***************************************************************************** +// +//! \brief Write 0 or 1 to select gpio pins. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! \param [in] ulPins is the bit-packed representation of the pin(s). +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinWrite(unsigned long ulPort, unsigned long ulPins, unsigned long ulVal) +{ + xHWREG(ulPort + FIOMASK) = ~ulPins; + if(0 != ulVal) + { + xHWREG(ulPort + FIOSET) = ulPins; + } + else + { + xHWREG(ulPort + FIOCLR) = ulPins; + } +} + +//***************************************************************************** +// +//! \brief Read selected gpio pin value. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! \param [in] ulPins is the bit-packed representation of the pin(s). +//! +//! \return The value of gpio pin. +// +//***************************************************************************** +unsigned long GPIOPinRead(unsigned long ulPort, unsigned long ulPin) +{ + xHWREG(ulPort + FIOMASK) = ~ulPin; + return xHWREG(ulPort + FIOPIN); +} + +//***************************************************************************** +// +//! \brief Read selected gpio port value. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! +//! \return The value of gpio port. +// +//***************************************************************************** +unsigned long GPIOPortRead(unsigned long ulPort) +{ + xHWREG(ulPort + FIOMASK) = (unsigned long) 0x00; + return xHWREG(ulPort + FIOPIN); +} + +//***************************************************************************** +// +//! \brief Write value to gpio port. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! +//! \return The value of gpio port. +// +//***************************************************************************** +void GPIOPortWrite(unsigned long ulPort, unsigned long ulVal) +{ + xHWREG(ulPort + FIOMASK) = (unsigned long) 0x00; + xHWREG(ulPort + FIOPIN) = ulVal; +} + +//***************************************************************************** +// +//! \brief Configure gpio pin interrupt mode. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! \param [in] ulPin is the bit-packed representation of the pin(s). +//! \param [in] ulCfg is the interrupts configure parameter, which can be logical +//! OR of the following value: +//! - \ref INT_TYPE_RISING +//! - \ref INT_TYPE_FALLING +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinIntCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulCfg) +{ + switch(ulPort) + { + case GPIOA_BASE: // Port 0 + { + if(ulCfg & GPIO_RISING_EDGE) // GPIO Rising Int Type + { + xHWREG(GPIO_INT_BASE + IO0IntEnR) |= ulPin; + } + + if(ulCfg & GPIO_FALLING_EDGE) // GPIO Falling Int Type + { + xHWREG(GPIO_INT_BASE + IO0IntEnF) |= ulPin; + } + + break; + } + + case GPIOC_BASE: // Port 2 + { + if(ulCfg & GPIO_RISING_EDGE) // GPIO Rising Int Type + { + xHWREG(GPIO_INT_BASE + IO2IntEnR) |= ulPin; + } + + if(ulCfg & GPIO_FALLING_EDGE) // GPIO Falling Int Type + { + xHWREG(GPIO_INT_BASE + IO2IntEnF) |= ulPin; + } + break; + } + default: + { + while(1); // Error + } + } +} + +//***************************************************************************** +// +//! \brief Enable GPIO interrupt. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! +//! \param [in] ulPin is the bit-packed representation of the pin(s). +//! +//! \return None. +//! +//! \note For LPC17xx, The pins belong to the same port share the same interrupt +//! source. +// +//***************************************************************************** +void GPIOPinIntEnable(unsigned long ulPort, unsigned long ulPin) +{ + // Avoid Compiler warning + (void) ulPort; + (void) ulPin; + + xIntEnable(INT_GPIO); +} + +//***************************************************************************** +// +//! \brief Disable GPIO interrupt. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! +//! \param [in] ulPin is the bit-packed representation of the pin(s). +//! +//! \return None. +//! +//! \note For LPC17xx, The pins belong to the same port share the same interrupt +//! source. +// +//***************************************************************************** +void GPIOPinIntDisable(unsigned long ulPort, unsigned long ulPin) +{ + // Avoid Compiler warning + (void) ulPort; + (void) ulPin; + + xIntDisable(INT_GPIO); +} + +//***************************************************************************** +// +//! \brief Get GPIO pin interrupt flag. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! +//! \param [in] ulPin is the bit-packed representation of the pin(s). +//! +//! \return The interrupt status of the gpio pin, which is the logical OR of the +//! following value: +//! - \ref INT_TYPE_RISING +//! - \ref INT_TYPE_FALLING +// +//***************************************************************************** +unsigned long GPIOPinIntFlagGet(unsigned long ulPort, unsigned long ulPin) +{ + unsigned long ulResult = 0; + + switch(ulPort) + { + case GPIOA_BASE: // Port 0 + { + + if(xHWREG(GPIO_INT_BASE + IO0IntEnR) & ulPin) // GPIO Rising Int Type + { + ulResult |= GPIO_RISING_EDGE; + } + + if(xHWREG(GPIO_INT_BASE + IO0IntEnF) & ulPin) // GPIO Falling Int Type + { + ulResult |= GPIO_FALLING_EDGE; + } + + break; + } + + case GPIOC_BASE: // Port 2 + { + if(xHWREG(GPIO_INT_BASE + IO2IntEnR) & ulPin) // GPIO Rising Int Type + { + ulResult |= GPIO_RISING_EDGE; + } + + if(xHWREG(GPIO_INT_BASE + IO2IntEnF) & ulPin) // GPIO Falling Int Type + { + ulResult |= GPIO_FALLING_EDGE; + } + break; + } + default: + { + ulResult = 0; // Error + } + } + + return (ulResult); +} + +//***************************************************************************** +// +//! \brief Clear GPIO pin interrupt flag. +//! +//! \param [in] ulPort is the base address of the GPIO port +//! +//! \param [in] ulPin is the bit-packed representation of the pin(s). +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinIntFlagClear(unsigned long ulPort, unsigned long ulPin) +{ + + switch(ulPort) + { + case GPIOA_BASE: // Port 0 + { + xHWREG(GPIO_INT_BASE + IO0IntClr) |= ulPin; + break; + } + + case GPIOC_BASE: // Port 2 + { + xHWREG(GPIO_INT_BASE + IO2IntClr) |= ulPin; + break; + } + default: + { + while(1); + } + } +} + +//***************************************************************************** +// +//! \brief Set the direction and mode of the specified pin(s). +//! This function will set the specified pin(s) on the selected GPIO +//! port as either an input or output under software control, or it +//! will set the pin to be under hardware control. +//! +//! \param [in] ulPort is the base address of the GPIO port, this value can +//! be one of the following value: +//! - \ref GPIOA_BASE +//! - \ref GPIOB_BASE +//! - ... +//! More Information, please refer to \ref xLowLayer_Peripheral_Memmap. +//! +//! \param [in] ulPins is the bit-packed representation of the pin(s). +//! elemnt can be one of the following value: +//! - \ref GPIO_PIN0 +//! - \ref GPIO_PIN1 +//! - \ref ... +//! More Information, please refer to \ref xGPIO_General_Pin_IDs. +//! +//! \param [in] ulPinIO is the pin direction and/or mode. +//! This parameter can be one of the following value: +//! Where \ref xGPIO_DIR_MODE_IN specifies that the pin will be +//! programmed a software controlled input, \ref xGPIO_DIR_MODE_OUT +//! specifies that the pin will be programmed as a software +//! controlled output, and \ref xGPIO_DIR_MODE_HW specifies that +//! the pin will be placed under hardware control. +//! +//! \return None. +//! +//! \note \ref xGPIOPadConfigSet() must also be used to configure the corresponding +//! pad(s) in order for them to propagate the signal to/from the GPIO. +// +//***************************************************************************** +void xGPIODirModeSet(unsigned long ulPort, unsigned long ulPins, unsigned long ulPinIO) +{ + unsigned long i = 0; + + for(i = 0; i < 32; i++) + { + if(ulPins & (0x01 << i)) + { + if(0 != ulPinIO) + { + GPIOPinModeCfg(ulPort, 0x01< nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef _LPC17XX_GPIO_H__ +#define _LPC17XX_GPIO_H__ + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_GPIO +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_GPIO_General_Pin_IDs LPC17xx GPIO General Pin ID +//! \brief The following values define the bit field for the ucPins argument +//! to several of the APIs. +//! @{ +// +//***************************************************************************** + +// +//! GPIO pin 0 +// +#define GPIO_PIN_0 0x00000001 + +// +//! GPIO pin 1 +// +#define GPIO_PIN_1 0x00000002 + +// +//! GPIO pin 2 +// +#define GPIO_PIN_2 0x00000004 + +// +//! GPIO pin 3 +// +#define GPIO_PIN_3 0x00000008 + +// +//! GPIO pin 4 +// +#define GPIO_PIN_4 0x00000010 + +// +//! GPIO pin 5 +// +#define GPIO_PIN_5 0x00000020 + +// +//! GPIO pin 6 +// +#define GPIO_PIN_6 0x00000040 + +// +//! GPIO pin 7 +// +#define GPIO_PIN_7 0x00000080 + +// +//! GPIO pin 8 +// +#define GPIO_PIN_8 0x00000100 + +// +//! GPIO pin 9 +// +#define GPIO_PIN_9 0x00000200 + +// +//! GPIO pin 10 +// +#define GPIO_PIN_10 0x00000400 + +// +//! GPIO pin 11 +// +#define GPIO_PIN_11 0x00000800 + +// +//! GPIO pin 12 +// +#define GPIO_PIN_12 0x00001000 + +// +//! GPIO pin 13 +// +#define GPIO_PIN_13 0x00002000 + +// +//! GPIO pin 14 +// +#define GPIO_PIN_14 0x00004000 + +// +//! GPIO pin 15 +// +#define GPIO_PIN_15 0x00008000 + +// +//! GPIO Pin 16 +// +#define GPIO_PIN_16 0x00010000 + +// +//! GPIO Pin 17 +// +#define GPIO_PIN_17 0x00020000 + +// +//! GPIO Pin 18 +// +#define GPIO_PIN_18 0x00040000 + +// +//! GPIO Pin 19 +// +#define GPIO_PIN_19 0x00080000 + +// +//! GPIO Pin 20 +// +#define GPIO_PIN_20 0x00100000 + +// +//! GPIO Pin 21 +// +#define GPIO_PIN_21 0x00200000 + +// +//! GPIO Pin 22 +// +#define GPIO_PIN_22 0x00400000 + +// +//! GPIO Pin 23 +// +#define GPIO_PIN_23 0x00800000 + +// +//! GPIO Pin 24 +// +#define GPIO_PIN_24 0x01000000 + +// +//! GPIO Pin 25 +// +#define GPIO_PIN_25 0x02000000 + +// +//! GPIO Pin 26 +// +#define GPIO_PIN_26 0x04000000 + +// +//! GPIO Pin 27 +// +#define GPIO_PIN_27 0x08000000 + +// +//! GPIO Pin 28 +// +#define GPIO_PIN_28 0x10000000 + +// +//! GPIO Pin 29 +// +#define GPIO_PIN_29 0x20000000 + +// +//! GPIO Pin 30 +// +#define GPIO_PIN_30 0x40000000 + +// +//! GPIO Pin 31 +// +#define GPIO_PIN_31 0x80000000 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_GPIO_General_Pin_Bits LPC17xx GPIO General Pin Bits +//! \brief The following values define the bit field for the ucBit argument to +//! GPIODirModeSet() API. +//! @{ +// +//***************************************************************************** + +// +//! GPIO BIT 0 +// +#define GPIO_BIT_0 0x00000000 + +// +//! GPIO BIT 1 +// +#define GPIO_BIT_1 0x00000001 + +// +//! GPIO BIT 2 +// +#define GPIO_BIT_2 0x00000002 + +// +//! GPIO BIT 3 +// +#define GPIO_BIT_3 0x00000003 + +// +//! GPIO BIT 4 +// +#define GPIO_BIT_4 0x00000004 + +// +//! GPIO BIT 5 +// +#define GPIO_BIT_5 0x00000005 + +// +//! GPIO BIT 6 +// +#define GPIO_BIT_6 0x00000006 + +// +//! GPIO BIT 7 +// +#define GPIO_BIT_7 0x00000007 + +// +//! GPIO BIT 8 +// +#define GPIO_BIT_8 0x00000008 + +// +//! GPIO BIT 9 +// +#define GPIO_BIT_9 0x00000009 + +// +//! GPIO BIT 10 +// +#define GPIO_BIT_10 0x0000000A + +// +//! GPIO BIT 11 +// +#define GPIO_BIT_11 0x0000000B + +// +//! GPIO BIT 12 +// +#define GPIO_BIT_12 0x0000000C + +// +//! GPIO BIT 13 +// +#define GPIO_BIT_13 0x0000000D + +// +//! GPIO BIT 14 +// +#define GPIO_BIT_14 0x0000000E + +// +//! GPIO BIT 15 +// +#define GPIO_BIT_15 0x0000000F + +// +//! GPIO BIT 16 +// +#define GPIO_BIT_16 0x00000010 + +// +//! GPIO BIT 17 +// +#define GPIO_BIT_17 0x00000011 + +// +//! GPIO BIT 18 +// +#define GPIO_BIT_18 0x00000012 + +// +//! GPIO BIT 19 +// +#define GPIO_BIT_19 0x00000013 + +// +//! GPIO BIT 20 +// +#define GPIO_BIT_20 0x00000014 + +// +//! GPIO BIT 21 +// +#define GPIO_BIT_21 0x00000015 + +// +//! GPIO BIT 22 +// +#define GPIO_BIT_22 0x00000016 + +// +//! GPIO BIT 23 +// +#define GPIO_BIT_23 0x00000017 + +// +//! GPIO BIT 24 +// +#define GPIO_BIT_24 0x00000018 + +// +//! GPIO BIT 25 +// +#define GPIO_BIT_25 0x00000019 + +// +//! GPIO BIT 26 +// +#define GPIO_BIT_26 0x0000001A + +// +//! GPIO BIT 27 +// +#define GPIO_BIT_27 0x0000001B + +// +//! GPIO BIT 28 +// +#define GPIO_BIT_28 0x0000001C + +// +//! GPIO BIT 29 +// +#define GPIO_BIT_29 0x0000001D + +// +//! GPIO BIT 30 +// +#define GPIO_BIT_30 0x0000001E + +// +//! GPIO BIT 31 +// +#define GPIO_BIT_31 0x0000001F + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_GPIO_Dir_Mode LPC17xx GPIO Dir Mode +//! \brief Values that can be passed to GPIODirModeSet as the ulPinIO parameter, +//! and returned from GPIODirModeGet. +//! @{ +// +//***************************************************************************** + +//! Disable Open-Drain function. +#define PIN_MODE_OD_DIS (BIT_32_6 ) + +//! Enable Open-Drain function. +#define PIN_MODE_OD_EN (BIT_32_6 | BIT_32_5 ) + +//! Enable pull-up function. +#define PIN_MODE_PULL_UP (BIT_32_4 ) + +//! Enable repeater function. +#define PIN_MODE_REPEATER (BIT_32_4 | BIT_32_2 ) + +//! No pull-up, No pull-down. +#define PIN_MODE_NONE (BIT_32_4 | BIT_32_3 ) + +//! Enable pull-down function. +#define PIN_MODE_PULL_DOWN (BIT_32_4 | BIT_32_3 | BIT_32_2 ) + +//! Input mode. +#define PIN_MODE_INPUT (BIT_32_1 ) + +//! Output mode. +#define PIN_MODE_OUTPUT (BIT_32_1 | BIT_32_0 ) + +/////////////////////////////////////////////////////////////////////////////// +// define for port to cox 'x' prefixed interface +/////////////////////////////////////////////////////////////////////////////// +// +//! Pin is a GPIO input +// +#define GPIO_DIR_MODE_IN PIN_MODE_INPUT + +// +//! Pin is a GPIO output +// +#define GPIO_DIR_MODE_OUT PIN_MODE_OUTPUT + +// +//! Pin is in Open-Drain mode. +// +#define GPIO_DIR_MODE_OD PIN_MODE_OD_EN + +// +//! Pin is in a peripheral function. +// +#define GPIO_DIR_MODE_HW 0 + +// +//! Pin is in Quasi-bidirectional mode. +// +#define GPIO_DIR_MODE_QB 0 + + +#define GPIO_PIN_TYPE_PU PIN_MODE_PULL_UP +#define GPIO_PIN_TYPE_PD PIN_MODE_PULL_DOWN +#define GPIO_PIN_TYPE_NP PIN_MODE_NONE + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_GPIO_Int_Types LPC17xx GPIO Int Type +//! \brief Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, +//! and returned from GPIOIntTypeGet. +//! @{ +// +//***************************************************************************** + +// +//! Interrupt on falling edge +// +#define GPIO_FALLING_EDGE 0x00000002 + +// +//! Interrupt on rising edge +// +#define GPIO_RISING_EDGE 0x00000001 + +// +//! Interrupt on both edges +// +#define GPIO_BOTH_EDGES 0x00000003 + +// +//! Interrupt on low level(LPC17xx not support) +// +#define GPIO_LOW_LEVEL 0 + +// +//! Interrupt on high level(LPC17xx not support) +// +#define GPIO_HIGH_LEVEL 0 + +// +//! Interrupt on both level(LPC17xx not support) +// +#define GPIO_BOTH_LEVEL 0 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xGPIO_GP_Short_Pin xGPIO General Purpose Short Pin +//! @{ +// +//***************************************************************************** + +//! PortA +//! For LPC17xx mcu, Port A is equal to Port 0 +#define GPA0 GPIOA_BASE, GPIO_PIN_0 +#define GPA1 GPIOA_BASE, GPIO_PIN_1 +#define GPA2 GPIOA_BASE, GPIO_PIN_2 +#define GPA3 GPIOA_BASE, GPIO_PIN_3 +#define GPA4 GPIOA_BASE, GPIO_PIN_4 +#define GPA5 GPIOA_BASE, GPIO_PIN_5 +#define GPA6 GPIOA_BASE, GPIO_PIN_6 +#define GPA7 GPIOA_BASE, GPIO_PIN_7 +#define GPA8 GPIOA_BASE, GPIO_PIN_8 +#define GPA9 GPIOA_BASE, GPIO_PIN_9 +#define GPA10 GPIOA_BASE, GPIO_PIN_10 +#define GPA11 GPIOA_BASE, GPIO_PIN_11 +#define GPA12 GPIOA_BASE, GPIO_PIN_12 +#define GPA13 GPIOA_BASE, GPIO_PIN_13 +#define GPA14 GPIOA_BASE, GPIO_PIN_14 +#define GPA15 GPIOA_BASE, GPIO_PIN_15 +#define GPA16 GPIOA_BASE, GPIO_PIN_16 +#define GPA17 GPIOA_BASE, GPIO_PIN_17 +#define GPA18 GPIOA_BASE, GPIO_PIN_18 +#define GPA19 GPIOA_BASE, GPIO_PIN_19 +#define GPA20 GPIOA_BASE, GPIO_PIN_20 +#define GPA21 GPIOA_BASE, GPIO_PIN_21 +#define GPA22 GPIOA_BASE, GPIO_PIN_22 +#define GPA23 GPIOA_BASE, GPIO_PIN_23 +#define GPA24 GPIOA_BASE, GPIO_PIN_24 +#define GPA25 GPIOA_BASE, GPIO_PIN_25 +#define GPA26 GPIOA_BASE, GPIO_PIN_26 +#define GPA27 GPIOA_BASE, GPIO_PIN_27 +#define GPA28 GPIOA_BASE, GPIO_PIN_28 +#define GPA29 GPIOA_BASE, GPIO_PIN_29 +#define GPA30 GPIOA_BASE, GPIO_PIN_30 +#define GPA31 GPIOA_BASE, GPIO_PIN_31 + +//! PortB +//! For LPC17xx mcu, Port B is equal to Port 1 +#define GPB0 GPIOB_BASE, GPIO_PIN_0 +#define GPB1 GPIOB_BASE, GPIO_PIN_1 +#define GPB2 GPIOB_BASE, GPIO_PIN_2 +#define GPB3 GPIOB_BASE, GPIO_PIN_3 +#define GPB4 GPIOB_BASE, GPIO_PIN_4 +#define GPB5 GPIOB_BASE, GPIO_PIN_5 +#define GPB6 GPIOB_BASE, GPIO_PIN_6 +#define GPB7 GPIOB_BASE, GPIO_PIN_7 +#define GPB8 GPIOB_BASE, GPIO_PIN_8 +#define GPB9 GPIOB_BASE, GPIO_PIN_9 +#define GPB10 GPIOB_BASE, GPIO_PIN_10 +#define GPB11 GPIOB_BASE, GPIO_PIN_11 +#define GPB12 GPIOB_BASE, GPIO_PIN_12 +#define GPB13 GPIOB_BASE, GPIO_PIN_13 +#define GPB14 GPIOB_BASE, GPIO_PIN_14 +#define GPB15 GPIOB_BASE, GPIO_PIN_15 +#define GPB16 GPIOB_BASE, GPIO_PIN_16 +#define GPB17 GPIOB_BASE, GPIO_PIN_17 +#define GPB18 GPIOB_BASE, GPIO_PIN_18 +#define GPB19 GPIOB_BASE, GPIO_PIN_19 +#define GPB20 GPIOB_BASE, GPIO_PIN_20 +#define GPB21 GPIOB_BASE, GPIO_PIN_21 +#define GPB22 GPIOB_BASE, GPIO_PIN_22 +#define GPB23 GPIOB_BASE, GPIO_PIN_23 +#define GPB24 GPIOB_BASE, GPIO_PIN_24 +#define GPB25 GPIOB_BASE, GPIO_PIN_25 +#define GPB26 GPIOB_BASE, GPIO_PIN_26 +#define GPB27 GPIOB_BASE, GPIO_PIN_27 +#define GPB28 GPIOB_BASE, GPIO_PIN_28 +#define GPB29 GPIOB_BASE, GPIO_PIN_29 +#define GPB30 GPIOB_BASE, GPIO_PIN_30 +#define GPB31 GPIOB_BASE, GPIO_PIN_31 + +//! PortC +//! For LPC17xx mcu, Port C is equal to Port 2 +#define GPC0 GPIOC_BASE, GPIO_PIN_0 +#define GPC1 GPIOC_BASE, GPIO_PIN_1 +#define GPC2 GPIOC_BASE, GPIO_PIN_2 +#define GPC3 GPIOC_BASE, GPIO_PIN_3 +#define GPC4 GPIOC_BASE, GPIO_PIN_4 +#define GPC5 GPIOC_BASE, GPIO_PIN_5 +#define GPC6 GPIOC_BASE, GPIO_PIN_6 +#define GPC7 GPIOC_BASE, GPIO_PIN_7 +#define GPC8 GPIOC_BASE, GPIO_PIN_8 +#define GPC9 GPIOC_BASE, GPIO_PIN_9 +#define GPC10 GPIOC_BASE, GPIO_PIN_10 +#define GPC11 GPIOC_BASE, GPIO_PIN_11 +#define GPC12 GPIOC_BASE, GPIO_PIN_12 +#define GPC13 GPIOC_BASE, GPIO_PIN_13 +#define GPC14 GPIOC_BASE, GPIO_PIN_14 +#define GPC15 GPIOC_BASE, GPIO_PIN_15 +#define GPC16 GPIOC_BASE, GPIO_PIN_16 +#define GPC17 GPIOC_BASE, GPIO_PIN_17 +#define GPC18 GPIOC_BASE, GPIO_PIN_18 +#define GPC19 GPIOC_BASE, GPIO_PIN_19 +#define GPC20 GPIOC_BASE, GPIO_PIN_20 +#define GPC21 GPIOC_BASE, GPIO_PIN_21 +#define GPC22 GPIOC_BASE, GPIO_PIN_22 +#define GPC23 GPIOC_BASE, GPIO_PIN_23 +#define GPC24 GPIOC_BASE, GPIO_PIN_24 +#define GPC25 GPIOC_BASE, GPIO_PIN_25 +#define GPC26 GPIOC_BASE, GPIO_PIN_26 +#define GPC27 GPIOC_BASE, GPIO_PIN_27 +#define GPC28 GPIOC_BASE, GPIO_PIN_28 +#define GPC29 GPIOC_BASE, GPIO_PIN_29 +#define GPC30 GPIOC_BASE, GPIO_PIN_30 +#define GPC31 GPIOC_BASE, GPIO_PIN_31 + +//! PortD +//! For LPC17xx mcu, Port D is equal to Port 3 +#define GPD0 GPIOD_BASE, GPIO_PIN_0 +#define GPD1 GPIOD_BASE, GPIO_PIN_1 +#define GPD2 GPIOD_BASE, GPIO_PIN_2 +#define GPD3 GPIOD_BASE, GPIO_PIN_3 +#define GPD4 GPIOD_BASE, GPIO_PIN_4 +#define GPD5 GPIOD_BASE, GPIO_PIN_5 +#define GPD6 GPIOD_BASE, GPIO_PIN_6 +#define GPD7 GPIOD_BASE, GPIO_PIN_7 +#define GPD8 GPIOD_BASE, GPIO_PIN_8 +#define GPD9 GPIOD_BASE, GPIO_PIN_9 +#define GPD10 GPIOD_BASE, GPIO_PIN_10 +#define GPD11 GPIOD_BASE, GPIO_PIN_11 +#define GPD12 GPIOD_BASE, GPIO_PIN_12 +#define GPD13 GPIOD_BASE, GPIO_PIN_13 +#define GPD14 GPIOD_BASE, GPIO_PIN_14 +#define GPD15 GPIOD_BASE, GPIO_PIN_15 +#define GPD16 GPIOD_BASE, GPIO_PIN_16 +#define GPD17 GPIOD_BASE, GPIO_PIN_17 +#define GPD18 GPIOD_BASE, GPIO_PIN_18 +#define GPD19 GPIOD_BASE, GPIO_PIN_19 +#define GPD20 GPIOD_BASE, GPIO_PIN_20 +#define GPD21 GPIOD_BASE, GPIO_PIN_21 +#define GPD22 GPIOD_BASE, GPIO_PIN_22 +#define GPD23 GPIOD_BASE, GPIO_PIN_23 +#define GPD24 GPIOD_BASE, GPIO_PIN_24 +#define GPD25 GPIOD_BASE, GPIO_PIN_25 +#define GPD26 GPIOD_BASE, GPIO_PIN_26 +#define GPD27 GPIOD_BASE, GPIO_PIN_27 +#define GPD28 GPIOD_BASE, GPIO_PIN_28 +#define GPD29 GPIOD_BASE, GPIO_PIN_29 +#define GPD30 GPIOD_BASE, GPIO_PIN_30 +#define GPD31 GPIOD_BASE, GPIO_PIN_31 + +//! PortE +//! For LPC17xx mcu, Port E is equal to Port 4 +#define GPE0 GPIOE_BASE, GPIO_PIN_0 +#define GPE1 GPIOE_BASE, GPIO_PIN_1 +#define GPE2 GPIOE_BASE, GPIO_PIN_2 +#define GPE3 GPIOE_BASE, GPIO_PIN_3 +#define GPE4 GPIOE_BASE, GPIO_PIN_4 +#define GPE5 GPIOE_BASE, GPIO_PIN_5 +#define GPE6 GPIOE_BASE, GPIO_PIN_6 +#define GPE7 GPIOE_BASE, GPIO_PIN_7 +#define GPE8 GPIOE_BASE, GPIO_PIN_8 +#define GPE9 GPIOE_BASE, GPIO_PIN_9 +#define GPE10 GPIOE_BASE, GPIO_PIN_10 +#define GPE11 GPIOE_BASE, GPIO_PIN_11 +#define GPE12 GPIOE_BASE, GPIO_PIN_12 +#define GPE13 GPIOE_BASE, GPIO_PIN_13 +#define GPE14 GPIOE_BASE, GPIO_PIN_14 +#define GPE15 GPIOE_BASE, GPIO_PIN_15 +#define GPE16 GPIOE_BASE, GPIO_PIN_16 +#define GPE17 GPIOE_BASE, GPIO_PIN_17 +#define GPE18 GPIOE_BASE, GPIO_PIN_18 +#define GPE19 GPIOE_BASE, GPIO_PIN_19 +#define GPE20 GPIOE_BASE, GPIO_PIN_20 +#define GPE21 GPIOE_BASE, GPIO_PIN_21 +#define GPE22 GPIOE_BASE, GPIO_PIN_22 +#define GPE23 GPIOE_BASE, GPIO_PIN_23 +#define GPE24 GPIOE_BASE, GPIO_PIN_24 +#define GPE25 GPIOE_BASE, GPIO_PIN_25 +#define GPE26 GPIOE_BASE, GPIO_PIN_26 +#define GPE27 GPIOE_BASE, GPIO_PIN_27 +#define GPE28 GPIOE_BASE, GPIO_PIN_28 +#define GPE29 GPIOE_BASE, GPIO_PIN_29 +#define GPE30 GPIOE_BASE, GPIO_PIN_30 +#define GPE31 GPIOE_BASE, GPIO_PIN_31 + +//! PortF +//! For LPC17xx mcu, Port E is equal to Port 5 +#define GPF0 GPIOF_BASE, GPIO_PIN_0 +#define GPF1 GPIOF_BASE, GPIO_PIN_1 +#define GPF2 GPIOF_BASE, GPIO_PIN_2 +#define GPF3 GPIOF_BASE, GPIO_PIN_3 +#define GPF4 GPIOF_BASE, GPIO_PIN_4 +#define GPF5 GPIOF_BASE, GPIO_PIN_5 +#define GPF6 GPIOF_BASE, GPIO_PIN_6 +#define GPF7 GPIOF_BASE, GPIO_PIN_7 +#define GPF8 GPIOF_BASE, GPIO_PIN_8 +#define GPF9 GPIOF_BASE, GPIO_PIN_9 +#define GPF10 GPIOF_BASE, GPIO_PIN_10 +#define GPF11 GPIOF_BASE, GPIO_PIN_11 +#define GPF12 GPIOF_BASE, GPIO_PIN_12 +#define GPF13 GPIOF_BASE, GPIO_PIN_13 +#define GPF14 GPIOF_BASE, GPIO_PIN_14 +#define GPF15 GPIOF_BASE, GPIO_PIN_15 +#define GPF16 GPIOF_BASE, GPIO_PIN_16 +#define GPF17 GPIOF_BASE, GPIO_PIN_17 +#define GPF18 GPIOF_BASE, GPIO_PIN_18 +#define GPF19 GPIOF_BASE, GPIO_PIN_19 +#define GPF20 GPIOF_BASE, GPIO_PIN_20 +#define GPF21 GPIOF_BASE, GPIO_PIN_21 +#define GPF22 GPIOF_BASE, GPIO_PIN_22 +#define GPF23 GPIOF_BASE, GPIO_PIN_23 +#define GPF24 GPIOF_BASE, GPIO_PIN_24 +#define GPF25 GPIOF_BASE, GPIO_PIN_25 +#define GPF26 GPIOF_BASE, GPIO_PIN_26 +#define GPF27 GPIOF_BASE, GPIO_PIN_27 +#define GPF28 GPIOF_BASE, GPIO_PIN_28 +#define GPF29 GPIOF_BASE, GPIO_PIN_29 +#define GPF30 GPIOF_BASE, GPIO_PIN_30 +#define GPF31 GPIOF_BASE, GPIO_PIN_31 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_GPIO_General_Pin_IDs LPC17xx GPIO General Pin ID +//! \brief The following values define the bit field for the ucPins argument +//! to several of the APIs. +//! @{ +// +//***************************************************************************** +#if defined(LPC_175x) || defined (LPC_176x) + +#define GPIO_PA0_PA0 ((unsigned long)0x00 << 0 ) +#define GPIO_PA0_CAN1RX ((unsigned long)0x01 << 0 ) +#define GPIO_PA0_UART3TX ((unsigned long)0x02 << 0 ) +#define GPIO_PA0_I2C1SDA ((unsigned long)0x03 << 0 ) +#define GPIO_PA1_PA1 ((unsigned long)0x00 << 2 ) +#define GPIO_PA1_CAN1TX ((unsigned long)0x01 << 2 ) +#define GPIO_PA1_UART3RX ((unsigned long)0x02 << 2 ) +#define GPIO_PA1_I2C1SCK ((unsigned long)0x03 << 2 ) +#define GPIO_PA2_PA2 ((unsigned long)0x00 << 4 ) +#define GPIO_PA2_UART0TX ((unsigned long)0x01 << 4 ) +#define GPIO_PA2_ADC7 ((unsigned long)0x02 << 4 ) +#define GPIO_PA3_PA3 ((unsigned long)0x00 << 6 ) +#define GPIO_PA3_UART0RX ((unsigned long)0x01 << 6 ) +#define GPIO_PA3_ADC6 ((unsigned long)0x02 << 6 ) +#define GPIO_PA4_PA4 ((unsigned long)0x00 << 8 ) +#define GPIO_PA4_I2SRX_CLK ((unsigned long)0x01 << 8 ) +#define GPIO_PA4_CAN2RX ((unsigned long)0x02 << 8 ) +#define GPIO_PA4_TIMCCP0 ((unsigned long)0x03 << 8 ) +#define GPIO_PA5_PA5 ((unsigned long)0x00 << 10) +#define GPIO_PA5_I2SRX_WS ((unsigned long)0x01 << 10) +#define GPIO_PA5_CAN2TX ((unsigned long)0x02 << 10) +#define GPIO_PA5_TIMCCP1 ((unsigned long)0x03 << 10) +#define GPIO_PA6_PA6 ((unsigned long)0x00 << 12) +#define GPIO_PA6_I2SRX_SDA ((unsigned long)0x01 << 12) +#define GPIO_PA6_SSEL1 ((unsigned long)0x02 << 12) +#define GPIO_PA6_TIM_MAT0 ((unsigned long)0x03 << 12) +#define GPIO_PA7_PA7 ((unsigned long)0x00 << 14) +#define GPIO_PA7_I2STX_CLK ((unsigned long)0x01 << 14) +#define GPIO_PA7_SCK1 ((unsigned long)0x02 << 14) +#define GPIO_PA7_TIM_MAT1 ((unsigned long)0x03 << 14) +#define GPIO_PA8_PA8 ((unsigned long)0x00 << 16) +#define GPIO_PA8_I2STX_WS ((unsigned long)0x01 << 16) +#define GPIO_PA8_MISO1 ((unsigned long)0x02 << 16) +#define GPIO_PA8_TIM_MAT2 ((unsigned long)0x03 << 16) +#define GPIO_PA9_PA9 ((unsigned long)0x00 << 18) +#define GPIO_PA9_I2STX_SDA ((unsigned long)0x01 << 18) +#define GPIO_PA9_MOSI1 ((unsigned long)0x02 << 18) +#define GPIO_PA9_TIM_MAT3 ((unsigned long)0x03 << 18) +#define GPIO_PA10_PA10 ((unsigned long)0x00 << 20) +#define GPIO_PA10_UART2TX ((unsigned long)0x01 << 20) +#define GPIO_PA10_I2C2SDA ((unsigned long)0x02 << 20) +#define GPIO_PA10_TIM_MAT0 ((unsigned long)0x03 << 20) +#define GPIO_PA11_PA11 ((unsigned long)0x00 << 22) +#define GPIO_PA11_UART2RX ((unsigned long)0x01 << 22) +#define GPIO_PA11_I2C2SCK ((unsigned long)0x02 << 22) +#define GPIO_PA11_TIM_MAT1 ((unsigned long)0x03 << 22) +#define GPIO_PA15_PA15 ((unsigned long)0x00 << 30) +#define GPIO_PA15_UART1TX ((unsigned long)0x01 << 30) +#define GPIO_PA15_SCK0 ((unsigned long)0x02 << 30) +#define GPIO_PA15_SPI0CLK ((unsigned long)0x03 << 30) +#define GPIO_PA16_PA16 ((unsigned long)0x00 << 0 ) +#define GPIO_PA16_UART1RX ((unsigned long)0x01 << 0 ) +#define GPIO_PA16_SSEL0 ((unsigned long)0x02 << 0 ) +#define GPIO_PA16_SPI0CS ((unsigned long)0x03 << 0 ) +#define GPIO_PA17_PA17 ((unsigned long)0x00 << 2 ) +#define GPIO_PA17_UART1CTS ((unsigned long)0x01 << 2 ) +#define GPIO_PA17_MISO0 ((unsigned long)0x02 << 2 ) +#define GPIO_PA17_SPI0MISO ((unsigned long)0x03 << 2 ) +#define GPIO_PA18_PA18 ((unsigned long)0x00 << 4 ) +#define GPIO_PA18_UART1DCD ((unsigned long)0x01 << 4 ) +#define GPIO_PA18_MOSI0 ((unsigned long)0x02 << 4 ) +#define GPIO_PA18_SPI0MOSI ((unsigned long)0x03 << 4 ) +#define GPIO_PA19_PA19 ((unsigned long)0x00 << 6 ) +#define GPIO_PA19_UART1DSR ((unsigned long)0x01 << 6 ) +#define GPIO_PA19_I2C1SDA ((unsigned long)0x03 << 6 ) +#define GPIO_PA20_PA20 ((unsigned long)0x00 << 8 ) +#define GPIO_PA20_UART1DTR ((unsigned long)0x01 << 8 ) +#define GPIO_PA20_I2C1SCK ((unsigned long)0x03 << 8 ) +#define GPIO_PA21_PA21 ((unsigned long)0x00 << 10) +#define GPIO_PA21_UART1RI ((unsigned long)0x01 << 10) +#define GPIO_PA21_CAN1RX ((unsigned long)0x03 << 10) +#define GPIO_PA22_PA22 ((unsigned long)0x00 << 12) +#define GPIO_PA22_UART1RTS ((unsigned long)0x01 << 12) +#define GPIO_PA22_CAN1TX ((unsigned long)0x03 << 12) +#define GPIO_PA23_PA23 ((unsigned long)0x00 << 14) +#define GPIO_PA23_ADC0 ((unsigned long)0x01 << 14) +#define GPIO_PA23_I2SRX_CLK ((unsigned long)0x02 << 14) +#define GPIO_PA23_TIMCCP0 ((unsigned long)0x03 << 14) +#define GPIO_PA24_PA24 ((unsigned long)0x00 << 16) +#define GPIO_PA24_ADC1 ((unsigned long)0x01 << 16) +#define GPIO_PA24_I2SRX_WS ((unsigned long)0x02 << 16) +#define GPIO_PA24_TIMCCP1 ((unsigned long)0x03 << 16) +#define GPIO_PA25_PA25 ((unsigned long)0x00 << 18) +#define GPIO_PA25_ADC2 ((unsigned long)0x01 << 18) +#define GPIO_PA25_I2SRX_SDA ((unsigned long)0x02 << 18) +#define GPIO_PA25_UART3TX ((unsigned long)0x03 << 18) +#define GPIO_PA26_PA26 ((unsigned long)0x00 << 20) +#define GPIO_PA26_ADC3 ((unsigned long)0x01 << 20) +#define GPIO_PA26_DACOUT1 ((unsigned long)0x02 << 20) +#define GPIO_PA26_UART3RX ((unsigned long)0x03 << 20) +#define GPIO_PA27_PA27 ((unsigned long)0x00 << 22) +#define GPIO_PA27_I2C0SDA ((unsigned long)0x01 << 22) +#define GPIO_PA27_USB_SDA ((unsigned long)0x02 << 22) +#define GPIO_PA28_PA28 ((unsigned long)0x00 << 24) +#define GPIO_PA28_I2C0SCK ((unsigned long)0x01 << 24) +#define GPIO_PA28_USB_SCL ((unsigned long)0x02 << 24) +#define GPIO_PA29_PA29 ((unsigned long)0x00 << 26) +#define GPIO_PA29_USB_D_P ((unsigned long)0x01 << 26) +#define GPIO_PA30_PA30 ((unsigned long)0x00 << 28) +#define GPIO_PA30_USB_D_N ((unsigned long)0x01 << 28) +#define GPIO_PB0_PB0 ((unsigned long)0x00 << 0 ) +#define GPIO_PB0_ETH_TXD0 ((unsigned long)0x01 << 0 ) +#define GPIO_PB1_PB1 ((unsigned long)0x00 << 2 ) +#define GPIO_PB1_ETH_TXD1 ((unsigned long)0x01 << 2 ) +#define GPIO_PB4_PB4 ((unsigned long)0x00 << 8 ) +#define GPIO_PB4_ETH_TX_EN ((unsigned long)0x01 << 8 ) +#define GPIO_PB8_PB8 ((unsigned long)0x00 << 16) +#define GPIO_PB8_ETH_CRS ((unsigned long)0x01 << 16) +#define GPIO_PB9_PB9 ((unsigned long)0x00 << 18) +#define GPIO_PB9_ETH_RXD0 ((unsigned long)0x01 << 18) +#define GPIO_PB10_PB10 ((unsigned long)0x00 << 20) +#define GPIO_PB10_ETH_RXD1 ((unsigned long)0x01 << 20) +#define GPIO_PB14_PB14 ((unsigned long)0x00 << 28) +#define GPIO_PB14_ETH_RX_ER ((unsigned long)0x01 << 28) +#define GPIO_PB15_PB15 ((unsigned long)0x00 << 30) +#define GPIO_PB15_ETH_REF_CLK ((unsigned long)0x01 << 30) +#define GPIO_PB16_PB16 ((unsigned long)0x00 << 0 ) +#define GPIO_PB16_ENET_MDC ((unsigned long)0x01 << 0 ) +#define GPIO_PB17_PB17 ((unsigned long)0x00 << 2 ) +#define GPIO_PB17_ENET_MDIO ((unsigned long)0x01 << 2 ) +#define GPIO_PB18_PB18 ((unsigned long)0x00 << 4 ) +#define GPIO_PB18_USB_UP_LED ((unsigned long)0x01 << 4 ) +#define GPIO_PB18_PWM1 ((unsigned long)0x02 << 4 ) +#define GPIO_PB18_TIMCCP0 ((unsigned long)0x03 << 4 ) +#define GPIO_PB19_PB19 ((unsigned long)0x00 << 6 ) +#define GPIO_PB19_MCOA0 ((unsigned long)0x01 << 6 ) +#define GPIO_PB19_USB_PPWR ((unsigned long)0x02 << 6 ) +#define GPIO_PB19_TIMCCP1 ((unsigned long)0x03 << 6 ) +#define GPIO_PB20_PB20 ((unsigned long)0x00 << 8 ) +#define GPIO_PB20_MCI0 ((unsigned long)0x01 << 8 ) +#define GPIO_PB20_PWM2 ((unsigned long)0x02 << 8 ) +#define GPIO_PB20_SCK0 ((unsigned long)0x03 << 8 ) +#define GPIO_PB21_PB21 ((unsigned long)0x00 << 10) +#define GPIO_PB21_MCABORT ((unsigned long)0x01 << 10) +#define GPIO_PB21_PWM3 ((unsigned long)0x02 << 10) +#define GPIO_PB21_SSEL0 ((unsigned long)0x03 << 10) +#define GPIO_PB22_PB22 ((unsigned long)0x00 << 12) +#define GPIO_PB22_MCOB0 ((unsigned long)0x01 << 12) +#define GPIO_PB22_USB_PWRD ((unsigned long)0x02 << 12) +#define GPIO_PB22_TIM_MAT0 ((unsigned long)0x03 << 12) +#define GPIO_PB23_PB23 ((unsigned long)0x00 << 14) +#define GPIO_PB23_MCI1 ((unsigned long)0x01 << 14) +#define GPIO_PB23_PWM4 ((unsigned long)0x02 << 14) +#define GPIO_PB23_MISO0 ((unsigned long)0x03 << 14) +#define GPIO_PB24_PB24 ((unsigned long)0x00 << 16) +#define GPIO_PB24_MCI2 ((unsigned long)0x01 << 16) +#define GPIO_PB24_PWM5 ((unsigned long)0x02 << 16) +#define GPIO_PB24_MOSI0 ((unsigned long)0x03 << 16) +#define GPIO_PB25_PB25 ((unsigned long)0x00 << 18) +#define GPIO_PB25_MCOA1 ((unsigned long)0x01 << 18) +#define GPIO_PB25_TIM_MAT1 ((unsigned long)0x03 << 18) +#define GPIO_PB26_PB26 ((unsigned long)0x00 << 20) +#define GPIO_PB26_MCOB1 ((unsigned long)0x01 << 20) +#define GPIO_PB26_PWM6 ((unsigned long)0x02 << 20) +#define GPIO_PB26_TIMCCP0 ((unsigned long)0x03 << 20) +#define GPIO_PB27_PB27 ((unsigned long)0x00 << 22) +#define GPIO_PB27_CLKOUT ((unsigned long)0x01 << 22) +#define GPIO_PB27_USB_OVRCR ((unsigned long)0x02 << 22) +#define GPIO_PB27_TIMCCP1 ((unsigned long)0x03 << 22) +#define GPIO_PB28_PB28 ((unsigned long)0x00 << 24) +#define GPIO_PB28_MCOA2 ((unsigned long)0x01 << 24) +#define GPIO_PB28_PWM_CAP_CH0 ((unsigned long)0x02 << 24) +#define GPIO_PB28_TIM_MAT0 ((unsigned long)0x03 << 24) +#define GPIO_PB29_PB29 ((unsigned long)0x00 << 26) +#define GPIO_PB29_MCOB2 ((unsigned long)0x01 << 26) +#define GPIO_PB29_PWM_CAP_CH1 ((unsigned long)0x02 << 26) +#define GPIO_PB29_TIM_MAT1 ((unsigned long)0x03 << 26) +#define GPIO_PB30_PB30 ((unsigned long)0x00 << 28) +#define GPIO_PB30_VBUS ((unsigned long)0x02 << 28) +#define GPIO_PB30_ADC4 ((unsigned long)0x03 << 28) +#define GPIO_PB31_PB31 ((unsigned long)0x00 << 30) +#define GPIO_PB31_SCK1 ((unsigned long)0x02 << 30) +#define GPIO_PB31_ADC5 ((unsigned long)0x03 << 30) +#define GPIO_PC0_PC0 ((unsigned long)0x00 << 0 ) +#define GPIO_PC0_PWM1 ((unsigned long)0x01 << 0 ) +#define GPIO_PC0_UART1TX ((unsigned long)0x02 << 0 ) +#define GPIO_PC1_PC1 ((unsigned long)0x00 << 2 ) +#define GPIO_PC1_PWM2 ((unsigned long)0x01 << 2 ) +#define GPIO_PC1_UART1RX ((unsigned long)0x02 << 2 ) +#define GPIO_PC2_PC2 ((unsigned long)0x00 << 4 ) +#define GPIO_PC2_PWM3 ((unsigned long)0x01 << 4 ) +#define GPIO_PC2_UART1CTS ((unsigned long)0x02 << 4 ) +#define GPIO_PC3_PC3 ((unsigned long)0x00 << 6 ) +#define GPIO_PC3_PWM4 ((unsigned long)0x01 << 6 ) +#define GPIO_PC3_UART1DCD ((unsigned long)0x02 << 6 ) +#define GPIO_PC4_PC4 ((unsigned long)0x00 << 8 ) +#define GPIO_PC4_PWM5 ((unsigned long)0x01 << 8 ) +#define GPIO_PC4_UART1DSR ((unsigned long)0x02 << 8 ) +#define GPIO_PC5_PC5 ((unsigned long)0x00 << 10) +#define GPIO_PC5_PWM6 ((unsigned long)0x01 << 10) +#define GPIO_PC5_UART1DTR ((unsigned long)0x02 << 10) +#define GPIO_PC6_PC6 ((unsigned long)0x00 << 12) +#define GPIO_PC6_PWM_CAP_CH0 ((unsigned long)0x01 << 12) +#define GPIO_PC6_UART1RI ((unsigned long)0x02 << 12) +#define GPIO_PC7_PC7 ((unsigned long)0x00 << 14) +#define GPIO_PC7_CAN2RX ((unsigned long)0x01 << 14) +#define GPIO_PC7_UART1RTS ((unsigned long)0x02 << 14) +#define GPIO_PC8_PC8 ((unsigned long)0x00 << 16) +#define GPIO_PC8_CAN2TX ((unsigned long)0x01 << 16) +#define GPIO_PC8_UART2TX ((unsigned long)0x02 << 16) +#define GPIO_PC8_ENET_MDC ((unsigned long)0x03 << 16) +#define GPIO_PC9_PC9 ((unsigned long)0x00 << 18) +#define GPIO_PC9_USB_CONNECT ((unsigned long)0x01 << 18) +#define GPIO_PC9_UART2RX ((unsigned long)0x02 << 18) +#define GPIO_PC9_ENET_MDIO ((unsigned long)0x03 << 18) +#define GPIO_PC10_PC10 ((unsigned long)0x00 << 20) +#define GPIO_PC10_EINT0 ((unsigned long)0x01 << 20) +#define GPIO_PC10_NMI ((unsigned long)0x02 << 20) +#define GPIO_PC11_PC11 ((unsigned long)0x00 << 22) +#define GPIO_PC11_EINT1 ((unsigned long)0x01 << 22) +#define GPIO_PC11_I2STX_CLK ((unsigned long)0x03 << 22) +#define GPIO_PC12_PC12 ((unsigned long)0x00 << 24) +#define GPIO_PC12_EINT2 ((unsigned long)0x01 << 24) +#define GPIO_PC12_I2STX_WS ((unsigned long)0x03 << 24) +#define GPIO_PC13_PC13 ((unsigned long)0x00 << 26) +#define GPIO_PC13_EINT3 ((unsigned long)0x01 << 26) +#define GPIO_PC13_I2STX_SDA ((unsigned long)0x03 << 26) +#define GPIO_PD25_PD25 ((unsigned long)0x00 << 18) +#define GPIO_PD25_TIM_MAT0 ((unsigned long)0x02 << 18) +#define GPIO_PD25_PWM2 ((unsigned long)0x03 << 18) +#define GPIO_PD26_PD26 ((unsigned long)0x00 << 20) +#define GPIO_PD26_STCLK ((unsigned long)0x01 << 20) +#define GPIO_PD26_TIM_MAT1 ((unsigned long)0x02 << 20) +#define GPIO_PD26_PWM3 ((unsigned long)0x03 << 20) +#define GPIO_PE28_PE28 ((unsigned long)0x00 << 24) +#define GPIO_PE28_RX_MCLK ((unsigned long)0x01 << 24) +#define GPIO_PE28_TIM_MAT0 ((unsigned long)0x02 << 24) +#define GPIO_PE28_UART3TX ((unsigned long)0x03 << 24) +#define GPIO_PE29_PE29 ((unsigned long)0x00 << 26) +#define GPIO_PE29_TX_MCLK ((unsigned long)0x01 << 26) +#define GPIO_PE29_TIM_MAT1 ((unsigned long)0x02 << 26) +#define GPIO_PE29_UART3RX ((unsigned long)0x03 << 26) + +#elif defined(LPC_177x) || defined (LPC_178x) +#define GPIO_PA0_PA0 0x00 +#define GPIO_PA0_CAN1RX 0x01 +#define GPIO_PA0_UART3TX 0x02 +#define GPIO_PA0_I2C1SDA 0x03 +#define GPIO_PA0_UART0TX 0x04 +#define GPIO_PA1_PA1 0x00 +#define GPIO_PA1_CAN1TX 0x01 +#define GPIO_PA1_UART3RX 0x02 +#define GPIO_PA1_I2C1SCK 0x03 +#define GPIO_PA1_UART0RX 0x04 +#define GPIO_PA2_PA2 0x00 +#define GPIO_PA2_UART0TX 0x01 +#define GPIO_PA2_UART3TX 0x02 +#define GPIO_PA3_PA3 0x00 +#define GPIO_PA3_UART0RX 0x01 +#define GPIO_PA3_UART3RX 0x02 +#define GPIO_PA4_PA4 0x00 +#define GPIO_PA4_I2SRX_CLK 0x01 +#define GPIO_PA4_CAN2RX 0x02 +#define GPIO_PA4_TIMCCP0 0x03 +#define GPIO_PA5_PA5 0x00 +#define GPIO_PA5_I2SRX_WS 0x01 +#define GPIO_PA5_CAN2TX 0x02 +#define GPIO_PA5_TIMCCP1 0x03 +#define GPIO_PA6_PA6 0x00 +#define GPIO_PA6_I2SRX_SDA 0x01 +#define GPIO_PA6_SPI1CS 0x02 +#define GPIO_PA6_TIM_MAT0 0x03 +#define GPIO_PA6_UART1RTS 0x04 +#define GPIO_PA10_PA10 0x00 +#define GPIO_PA10_UART2TX 0x01 +#define GPIO_PA10_I2C2SDA 0x02 +#define GPIO_PA10_TIM_MAT0 0x03 +#define GPIO_PA11_PA11 0x00 +#define GPIO_PA11_UART2RX 0x01 +#define GPIO_PA11_I2C2SCK 0x02 +#define GPIO_PA11_TIM_MAT1 0x03 +#define GPIO_PA14_PA14 0x00 +#define GPIO_PA14_USBHST2 0x01 +#define GPIO_PA14_SPI1CS 0x02 +#define GPIO_PA14_USBCNT2 0x03 +#define GPIO_PA15_PA15 0x00 +#define GPIO_PA15_UART1TX 0x01 +#define GPIO_PA15_SCK0 0x02 +#define GPIO_PA15_SPI0CLK 0x03 +#define GPIO_PA16_PA16 0x00 +#define GPIO_PA16_UART1RX 0x01 +#define GPIO_PA16_SPI0CS 0x02 +#define GPIO_PA17_PA17 0x00 +#define GPIO_PA17_UART1CTS 0x01 +#define GPIO_PA17_SPI0MISO 0x02 +#define GPIO_PA18_PA18 0x00 +#define GPIO_PA18_UART1DCD 0x01 +#define GPIO_PA18_SPI0MOSI 0x02 +#define GPIO_PA19_PA19 0x00 +#define GPIO_PA19_UART1DSR 0x01 +#define GPIO_PA19_SDCLK 0x02 +#define GPIO_PA19_I2C1SDA 0x03 +#define GPIO_PA20_PA20 0x00 +#define GPIO_PA20_UART1DTR 0x01 +#define GPIO_PA20_I2C1SCK 0x03 +#define GPIO_PA21_PA21 0x00 +#define GPIO_PA21_UART1RI 0x01 +#define GPIO_PA21_CAN1RX 0x03 +#define GPIO_PA22_PA22 0x00 +#define GPIO_PA22_UART1RTS 0x01 +#define GPIO_PA22_CAN1TX 0x03 +#define GPIO_PB0_PB0 0x00 +#define GPIO_PB0_ETH_TXD0 0x01 +#define GPIO_PB1_PB1 0x00 +#define GPIO_PB1_ETH_TXD1 0x01 +#define GPIO_PB1_PWM1 0x03 +#define GPIO_PB2_PB2 0x00 +#define GPIO_PB2_ETH_TXD2 0x01 +#define GPIO_PB2_PWM2 0x03 +#define GPIO_PB3_PB3 0x00 +#define GPIO_PB3_ETH_TXD3 0x01 +#define GPIO_PB4_PB4 0x00 +#define GPIO_PB4_ETH_TX_EN 0x01 +#define GPIO_PB4_TIM_MAT2 0x03 +#define GPIO_PB4_SPI2MISO 0x04 +#define GPIO_PB5_PB5 0x00 +#define GPIO_PB5_ETH_TX_ER 0x01 +#define GPIO_PB5_PWM3 0x03 +#define GPIO_PB6_PB6 0x00 +#define GPIO_PB6_ETH_TX_CLK 0x01 +#define GPIO_PB6_PWM4 0x03 +#define GPIO_PB7_PB7 0x00 +#define GPIO_PB7_ETH_COL 0x01 +#define GPIO_PB7_PWM5 0x03 +#define GPIO_PB8_PB8 0x00 +#define GPIO_PB8_ETH_CRS 0x01 +#define GPIO_PB8_TIM_MAT1 0x03 +#define GPIO_PB8_SPI2CS 0x04 +#define GPIO_PB9_PB9 0x00 +#define GPIO_PB9_ETH_RXD0 0x01 +#define GPIO_PB8_TIM_MAT0 0x03 +#define GPIO_PB10_PB10 0x00 +#define GPIO_PB10_ETH_RXD1 0x01 +#define GPIO_PB10_TIMCCP 0x03 +#define GPIO_PB11_PB11 0x00 +#define GPIO_PB11_ETH_RXD2 0x01 +#define GPIO_PB11_PWM6 0x03 +#define GPIO_PB12_PB12 0x00 +#define GPIO_PB12_ETH_RXD3 0x01 +#define GPIO_PB12_PWM7 0x03 +#define GPIO_PB13_PB13 0x00 +#define GPIO_PB13_ETH_RX_DV 0x01 +#define GPIO_PB14_PB14 0x00 +#define GPIO_PB14_ETH_RX_ER 0x01 +#define GPIO_PB14_TIMCCP 0x03 +#define GPIO_PB15_PB15 0x00 +#define GPIO_PB15_ETH_REF_CLK 0x01 +#define GPIO_PB15_I2C2SDA 0x03 +#define GPIO_PB16_PB16 0x00 +#define GPIO_PB16_ENET_MDC 0x01 +#define GPIO_PB16_I2S_TX_MCLK 0x02 +#define GPIO_PB17_PB17 0x00 +#define GPIO_PB17_ENET_MDIO 0x01 +#define GPIO_PB17_I2S_RX_MCLK 0x02 +#define GPIO_PB18_PB18 0x00 +#define GPIO_PB18_USB_UP_LED 0x01 +#define GPIO_PB18_PWM1 0x02 +#define GPIO_PB18_TIMCCP0 0x03 +#define GPIO_PB19_PB19 0x00 +#define GPIO_PB19_USB_TX_E 0x01 +#define GPIO_PB19_USB_PPWR 0x02 +#define GPIO_PB19_TIMCCP1 0x03 +#define GPIO_PB19_MCOA0 0x04 +#define GPIO_PB19_SPI1SCK 0x05 +#define GPIO_PB20_PB20 0x00 +#define GPIO_PB20_USB_TX_DP 0x01 +#define GPIO_PB20_PWM2 0x02 +#define GPIO_PB20_SPI0CLK 0x03 +#define GPIO_PB21_PB21 0x00 +#define GPIO_PB21_USB_TX_DM 0x01 +#define GPIO_PB21_PWM3 0x02 +#define GPIO_PB21_SPI0CS 0x03 +#define GPIO_PB22_PB22 0x00 +#define GPIO_PB22_USB_RCV 0x01 +#define GPIO_PB22_USB_PWRD 0x02 +#define GPIO_PB22_TIM_MAT0 0x03 +#define GPIO_PB22_SPI1MOSI 0x05 +#define GPIO_PB23_PB23 0x00 +#define GPIO_PB23_USB_RX_DP 0x01 +#define GPIO_PB23_PWM4 0x02 +#define GPIO_PB23_SPI0MISO 0x05 +#define GPIO_PB24_PB24 0x00 +#define GPIO_PB24_USB_RX_DM 0x01 +#define GPIO_PB24_PWM5 0x02 +#define GPIO_PB24_SPI0MOSI 0x05 +#define GPIO_PB25_PB25 0x00 +#define GPIO_PB25_USB_LS 0x01 +#define GPIO_PB25_USB_HST 0x02 +#define GPIO_PB25_TIM_MAT1 0x03 +#define GPIO_PB26_PB26 0x00 +#define GPIO_PB26_USB_SSPND 0x01 +#define GPIO_PB26_PWM6 0x02 +#define GPIO_PB26_TIMCCP0 0x03 +#define GPIO_PB26_SPI1CS 0x05 +#define GPIO_PB27_PB27 0x00 +#define GPIO_PB27_USB_INT 0x01 +#define GPIO_PB27_USB_OVRCR 0x02 +#define GPIO_PB27_TIMCCP1 0x03 +#define GPIO_PB28_PB28 0x00 +#define GPIO_PB28_USB_SCL 0x01 +#define GPIO_PB28_PWM_CAP_CH0 0x02 +#define GPIO_PB28_TIM_MAT0 0x03 +#define GPIO_PB28_SPI0CS 0x05 +#define GPIO_PB29_PB29 0x00 +#define GPIO_PB29_USB_SDA 0x01 +#define GPIO_PB29_PWM_CAP_CH1 0x02 +#define GPIO_PB29_TIM_MAT1 0x03 +#define GPIO_PB29_UART4TX 0x05 +#define GPIO_PC0_GPIO 0x00 +#define GPIO_PC0_PWM1 0x01 +#define GPIO_PC0_UART1TX 0x02 +#define GPIO_PC1_GPIO 0x00 +#define GPIO_PC1_PWM2 0x01 +#define GPIO_PC1_UART1RX 0x02 +#define GPIO_PC2_GPIO 0x00 +#define GPIO_PC2_PWM3 0x01 +#define GPIO_PC2_UART1CTS 0x02 +#define GPIO_PC2_TIM_MAT3 0x03 +#define GPIO_PC3_GPIO 0x00 +#define GPIO_PC3_PWM4 0x01 +#define GPIO_PC3_UART1DCD 0x02 +#define GPIO_PC3_TIM_MAT2 0x03 +#define GPIO_PC4_PC4 0x00 +#define GPIO_PC4_PWM5 0x01 +#define GPIO_PC4_UART1DSR 0x02 +#define GPIO_PC4_TIM_MAT1 0x03 +#define GPIO_PC5_PC5 0x00 +#define GPIO_PC5_PWM6 0x01 +#define GPIO_PC5_UART1DTR 0x02 +#define GPIO_PC5_TIM_MAT0 0x03 +#define GPIO_PC6_PC6 0x00 +#define GPIO_PC6_PWM_CAP_CH0 0x01 +#define GPIO_PC6_UART1RI 0x02 +#define GPIO_PC2_TIMCCP0 0x03 +#define GPIO_PC7_PC7 0x00 +#define GPIO_PC7_CAN2RX 0x01 +#define GPIO_PC7_UART1RTS 0x02 +#define GPIO_PC8_PC8 0x00 +#define GPIO_PC8_CAN2TX 0x01 +#define GPIO_PC8_UART2TX 0x02 +#define GPIO_PC8_UART1CTS 0x03 +#define GPIO_PC8_ENET_MDC 0x04 +#define GPIO_PC9_PC9 0x00 +#define GPIO_PC9_USB_CONNECT 0x01 +#define GPIO_PC9_UART2RX 0x02 +#define GPIO_PC9_UART4RX 0x03 +#define GPIO_PC9_ENET_MDIO 0x04 +#define GPIO_PC10_PC10 0x00 +#define GPIO_PC10_EINT0 0x01 +#define GPIO_PC10_NMI 0x02 +#define GPIO_PC11_PC11 0x00 +#define GPIO_PC11_EINT1 0x01 +#define GPIO_PC11_I2STX_CLK 0x03 +#define GPIO_PC12_PC12 0x00 +#define GPIO_PC12_EINT2 0x01 +#define GPIO_PC12_I2STX_WS 0x03 +#define GPIO_PC13_PC13 0x00 +#define GPIO_PC13_EINT3 0x01 +#define GPIO_PC13_I2STX_SDA 0x03 +#define GPIO_PC14_PC14 0x00 +#define GPIO_PC14_EMCCS2 0x01 +#define GPIO_PC14_I2C1SDA 0x02 +#define GPIO_PC14_TIMCCP0 0x03 +#define GPIO_PC15_PC15 0x00 +#define GPIO_PC15_EMCCS3 0x01 +#define GPIO_PC15_I2C1SCL 0x02 +#define GPIO_PC15_TIMCCP1 0x03 +#define GPIO_PC16_PC16 0x00 +#define GPIO_PC16_EMCCAS 0x01 +#define GPIO_PC17_PC17 0x00 +#define GPIO_PC17_EMCRAS 0x01 +#define GPIO_PC18_PC18 0x00 +#define GPIO_PC18_CLK 0x01 +#define GPIO_PC19_PC19 0x00 +#define GPIO_PC19_CLK 0x01 +#define GPIO_PC20_PC20 0x00 +#define GPIO_PC20_EMCDYCS 0x01 +#define GPIO_PC21_PC21 0x00 +#define GPIO_PC21_EMCDYCS 0x01 +#define GPIO_PC22_PC22 0x00 +#define GPIO_PC22_EMCDYCS 0x01 +#define GPIO_PC22_SPI0CLK 0x02 +#define GPIO_PC22_TIM_CAP 0x03 +#define GPIO_PC23_PC23 0x00 +#define GPIO_PC23_EMCDYCS 0x01 +#define GPIO_PC23_SPI0CS 0x02 +#define GPIO_PC23_TIM_CAP 0x03 +#define GPIO_PC24_PC24 0x00 +#define GPIO_PC24_EMCCKE 0x01 +#define GPIO_PC25_PC25 0x00 +#define GPIO_PC25_EMCCKE 0x01 +#define GPIO_PC26_PC26 0x00 +#define GPIO_PC26_EMCCKE 0x01 +#define GPIO_PC26_SPI0MISO 0x02 +#define GPIO_PC26_TIM_MAT0 0x03 +#define GPIO_PC27_PC27 0x00 +#define GPIO_PC27_EMCCKE 0x01 +#define GPIO_PC27_SPI0MOSI 0x02 +#define GPIO_PC27_TIM_MAT1 0x03 +#define GPIO_PC28_PC28 0x00 +#define GPIO_PC28_EMCDQM 0x01 +#define GPIO_PC29_PC29 0x00 +#define GPIO_PC29_EMCDQM 0x01 +#define GPIO_PC30_PC30 0x00 +#define GPIO_PC30_EMCDQM 0x01 +#define GPIO_PC30_I2C2SDA 0x02 +#define GPIO_PC30_TIM_MAT2 0x03 +#define GPIO_PC31_PC31 0x00 +#define GPIO_PC31_EMCDQM 0x01 +#define GPIO_PC31_I2C2SCK 0x02 +#define GPIO_PC31_TIM_MAT3 0x03 +#define GPIO_PD0_PD0 0x00 +#define GPIO_PD1_PD1 0x00 +#define GPIO_PD2_PD2 0x00 +#define GPIO_PD3_PD3 0x00 +#define GPIO_PD4_PD4 0x00 +#define GPIO_PD5_PD5 0x00 +#define GPIO_PD6_PD6 0x00 +#define GPIO_PD7_PD7 0x00 +#define GPIO_PD8_PD8 0x00 +#define GPIO_PD9_PD9 0x00 +#define GPIO_PD10_PD10 0x00 +#define GPIO_PD11_PD11 0x00 +#define GPIO_PD12_PD12 0x00 +#define GPIO_PD13_PD13 0x00 +#define GPIO_PD14_PD14 0x00 +#define GPIO_PD15_PD15 0x00 +#define GPIO_PD16_PD16 0x00 +#define GPIO_PD16_PWM1 0x02 +#define GPIO_PD16_UART1TX 0x03 +#define GPIO_PD17_PD17 0x00 +#define GPIO_PD17_PWM2 0x02 +#define GPIO_PD17_UART1RX 0x03 +#define GPIO_PD18_PD18 0x00 +#define GPIO_PD18_PWM3 0x02 +#define GPIO_PD18_UART1CTS 0x03 +#define GPIO_PD19_PD19 0x00 +#define GPIO_PD19_PWM4 0x02 +#define GPIO_PD19_UART1DCD 0x03 +#define GPIO_PD20_PD20 0x00 +#define GPIO_PD20_PWM5 0x02 +#define GPIO_PD20_UART1DSR 0x03 +#define GPIO_PD21_PD21 0x00 +#define GPIO_PD21_PWM7 0x02 +#define GPIO_PD21_UART1DSR 0x03 + + +#define GPIO_PD25_PD25 0x00 +#define GPIO_PD25_TIM_MAT0 0x02 +#define GPIO_PD25_PWM2 0x03 +#define GPIO_PD26_PD26 0x00 +#define GPIO_PD26_STCLK 0x01 +#define GPIO_PD26_TIM_MAT1 0x02 +#define GPIO_PD26_PWM3 0x03 +#define GPIO_PE28_PE28 0x00 +#define GPIO_PE28_RX_MCLK 0x01 +#define GPIO_PE28_TIM_MAT0 0x02 +#define GPIO_PE28_UART3TX 0x03 +#define GPIO_PE29_PE29 0x00 +#define GPIO_PE29_TX_MCLK 0x01 +#define GPIO_PE29_TIM_MAT1 0x02 +#define GPIO_PE29_UART3RX 0x03 + +#endif + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup GPIO +//! @{ +// +//***************************************************************************** + +//! Auxiliary function. +#define GPIOSPinConfigure(ePeripheralPin, eShortPin) \ + GPIOPinFunCfg(ePeripheralPin, eShortPin) + +// GPIOPinFunCfg(G##eShortPin, GPIO_##eShortPin##_##ePeripheralPin) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +#endif // _LPC17XX_GPIO_H__ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_rtc.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_rtc.h new file mode 100644 index 00000000..237c0a84 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_rtc.h @@ -0,0 +1,465 @@ +//***************************************************************************** +// +//! \file hw_rtc.h +//! \brief Macros used when accessing the RTC hardware. +//! \version V3.0.0.0 +//! \date $CURRENTTIME$ +//! \author CooCox +//! \copyright +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + + +#ifndef __XHW_RTC_H__ +#define __XHW_RTC_H__ + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup RTC +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register RTC Register Hardware Layer. +//! \brief Here are detail register information. +//! it contains: +//! - Register offset. +//! - detailed bit-field of the registers. +//! - Enum and mask of the registers. +//! +//! Users can read or write the registers via xHWREG(). +//! +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_Offsets RTC Register Offset(Map) +//! \brief Here is the register offset, users can get the register address +//! via RTC_BASE + offset. +//! @{ +// +//***************************************************************************** + +//! Interrupt Location Register +#define RTC_ILR ((unsigned long)0x00000000) + +//! Clock Control Register +#define RTC_CCR ((unsigned long)0x00000008) + +//! Counter Increment Interrupt Register +#define RTC_CIIR ((unsigned long)0x0000000C) + +//! Alarm Mask Register +#define RTC_AMR ((unsigned long)0x00000010) + +//! RTC Auxiliary control register +#define RTC_RTC_AUX ((unsigned long)0x0000005C) + +//! RTC Auxiliary Enable register +#define RTC_RTC_AUXEN ((unsigned long)0x00000058) + +//! Consolidated Time Register 0 +#define RTC_CTIME0 ((unsigned long)0x00000014) + +//! Consolidated Time Register 1 +#define RTC_CTIME1 ((unsigned long)0x00000018) + +//! Consolidated Time Register 2 +#define RTC_CTIME2 ((unsigned long)0x0000001C) + +//! Seconds Counter +#define RTC_SEC ((unsigned long)0x00000020) + +//! Minutes Register +#define RTC_MIN ((unsigned long)0x00000024) + +//! Hours Register +#define RTC_HOUR ((unsigned long)0x00000028) + +//! Day of Month Register +#define RTC_DOM ((unsigned long)0x0000002C) + +//! Day of Week Register +#define RTC_DOW ((unsigned long)0x00000030) + +//! Day of Year Register +#define RTC_DOY ((unsigned long)0x00000034) + +//! Months Register +#define RTC_MONTH ((unsigned long)0x00000038) + +//! Years Register +#define RTC_YEAR ((unsigned long)0x0000003C) + +//! Calibration Value Register +#define RTC_CALIBRATION ((unsigned long)0x00000040) + +//! General Purpose Register 0 +#define RTC_GPREG0 ((unsigned long)0x00000044) + +//! General Purpose Register 1 +#define RTC_GPREG1 ((unsigned long)0x00000048) + +//! General Purpose Register 2 +#define RTC_GPREG2 ((unsigned long)0x0000004C) + +//! General Purpose Register 3 +#define RTC_GPREG3 ((unsigned long)0x00000050) + +//! General Purpose Register 4 +#define RTC_GPREG4 ((unsigned long)0x00000054) + +//! Alarm value for Seconds +#define RTC_ALSEC ((unsigned long)0x00000060) + +//! Alarm value for Minutes +#define RTC_ALMIN ((unsigned long)0x00000064) + +//! Alarm value for Hours +#define RTC_ALHOUR ((unsigned long)0x00000068) + +//! Alarm value for Day of Month +#define RTC_ALDOM ((unsigned long)0x0000006C) + +//! Alarm value for Day of Week +#define RTC_ALDOW ((unsigned long)0x00000070) + +//! Alarm value for Day of Year +#define RTC_ALDOY ((unsigned long)0x00000074) + +//! Alarm value for Months +#define RTC_ALMONTH ((unsigned long)0x00000078) + +//! Alarm value for Year +#define RTC_ALYEAR ((unsigned long)0x0000007C) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_ILR RTC Register ILR. +//! \brief WDT ILR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! RTC counter increment interrupt flag. +#define ILR_CIF BIT_32_0 + +//! RTC alarm registers interrupt flag. +#define ILR_CALF BIT_32_1 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_CCR RTC Register CCR. +//! \brief WDT CCR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! RTC Clock Enable. +#define CCR_CLKEN BIT_32_0 + +//! CTC reset. +#define CCR_CTCRST BIT_32_1 + +//! Calibration counter enable. +#define CCR_CCALEN BIT_32_4 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_CIIR RTC Register CIIR. +//! \brief WDT CIIR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Second increment interrupt. +#define CIIR_IMSEC BIT_32_0 + +//! Minute increment interrupt. +#define CIIR_IMMIN BIT_32_1 + +//! Hour increment interrupt. +#define CIIR_IMHOUR BIT_32_2 + +//! Day of month increment interrupt. +#define CIIR_IMDOM BIT_32_3 + +//! Week of month increment interrupt. +#define CIIR_IMDOW BIT_32_4 + +//! Year of month increment interrupt. +#define CIIR_IMDOY BIT_32_5 + +//! Month increment interrupt. +#define CIIR_IMMON BIT_32_6 + +//! Year increment interrupt. +#define CIIR_IMYEAR BIT_32_7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_AMR RTC Register AMR. +//! \brief WDT AMR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Second increment interrupt. +#define AMR_SEC BIT_32_0 + +//! Minute increment interrupt. +#define AMR_MIN BIT_32_1 + +//! Hour increment interrupt. +#define AMR_HOUR BIT_32_2 + +//! Day of month increment interrupt. +#define AMR_DOM BIT_32_3 + +//! Week of month increment interrupt. +#define AMR_DOW BIT_32_4 + +//! Year of month increment interrupt. +#define AMR_DOY BIT_32_5 + +//! Month increment interrupt. +#define AMR_MON BIT_32_6 + +//! Year increment interrupt. +#define AMR_YEAR BIT_32_7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_AUX RTC Register AUX. +//! \brief WDT AUR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! RTC Oscillator fail detect flag. +#define RTC_AUX_OSCF BIT_32_4 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_AUXEN RTC Register AUXEN. +//! \brief WDT AUREN Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Oscillator fail detect interrupt enable. +#define RTC_AUXEN_OSCFEN BIT_32_4 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_CTIME0 RTC Register CTIME0. +//! \brief WDT CTIME0 Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Second value mask +#define CTIME0_SEC_M BIT_MASK(32, 5, 0) +//! Second value shift +#define CTIME0_SEC_S 0 + +//! Minutes value mask +#define CTIME0_MIN_M BIT_MASK(32, 13, 8) +//! Minutes value shift +#define CTIME0_MIN_S 8 + +//! Hours value mask +#define CTIME0_HOUR_M BIT_MASK(32, 20, 16) +//! Hours value shift +#define CTIME0_HOUR_S 16 + +//! Day of week value mask +#define CTIME0_DOW_M BIT_MASK(32, 26, 24) +//! Day of week value shift +#define CTIME0_DOW_S 24 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_CTIME1 RTC Register CTIME1. +//! \brief WDT CTIME1 Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Day of month value mask +#define CTIME1_DOM_M BIT_MASK(32, 4, 0) +//! Day of month value shift +#define CTIME1_DOM_S 0 + +//! Month value mask +#define CTIME1_MON_M BIT_MASK(32, 11, 8) +//! Month value shift +#define CTIME1_MON_S 8 + +//! Year value mask +#define CTIME1_YEAR_M BIT_MASK(32, 27, 16) +//! Year value shift +#define CTIME1_YEAR_S 16 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_CTIME2 RTC Register CTIME2. +//! \brief WDT CTIME2 Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Day of year value mask +#define CTIME2_DOY_M BIT_MASK(32, 11, 0) +//! Day of year value shift +#define CTIME2_DOY_S 0 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_Register_CALI RTC Register CALI. +//! \brief WDT CALI Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Calibration counter value mask +#define CALI_VAL_M BIT_MASK(32, 16, 0) +//! Calibration counter value shift +#define CALI_VAL_S 0 + +//! Calibration counter value. +#define CALI_DIR BIT_32_17 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +#endif // __HW_RTC_H__ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_spi.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_spi.h new file mode 100644 index 00000000..404b7e24 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_spi.h @@ -0,0 +1,575 @@ +//***************************************************************************** +// +//! \file hw_spi.h +//! \brief Macros used when accessing the SPI hardware. +//! \version V3.0.0.0 +//! \date $CURRENTTIME$ +//! \author CooCox +//! \copyright +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + + +#ifndef __LPC17XX_HW_SPI_H__ +#define __LPX17XX_HW_SPI_H__ + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup SPI +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SPI_Register SPI Register Hardware Layer. +//! \brief Here are detail register information. +//! it contains: +//! - Register offset. +//! - detailed bit-field of the registers. +//! - Enum and mask of the registers. +//! +//! \note Users can read or write the registers via xHWREG(). +//! +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_Offsets SSP Register Offset(Map) +//! \brief Here is the register offset, users can get the register address +//! via SPIn_BASE(n = 0, 1) + offset. +//! @{ +// +//***************************************************************************** + +// +//! SSP Control Register 0. Selects the serial clock rate, bus type, and data size. +// +#define SSP_CR0 0x00000000 + + +// +//! SSP Control Register 1. Selects master/slave and other modes. +// +#define SSP_CR1 0x00000004 + +// +//! SSP Data Register. +// +#define SSP_DR 0x00000008 + +// +//! SSP Status Register. +// +#define SSP_SR 0x0000000C + +// +//! SSP Clock Prescale Register. +// +#define SSP_CPSR 0x00000010 + +// +//! SSP Interrupt Mask Set and Clear Register. +// +#define SSP_IMSC 0x00000014 + +// +//! SSP Raw Interrupt Status Register +// +#define SSP_RIS 0x00000018 + +// +//! SSP Masked Interrupt Status Register +// +#define SSP_MIS 0x0000001C + +// +//! SSP Interrupt Clear Register +// +#define SSP_ICR 0x00000020 + +// +//! SSP DMA Control Register +// +#define SSP_DMACR 0x00000024 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_CR0 SSP Register SSP_CR0 +//! \brief SSP SSP_CR0 Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Data Size Select mask. +#define SSP_CR0_DSS_M BIT_MASK(32, 3, 0) + +//! Data Size Select shift. +#define SSP_CR0_DSS_S 0 + +//! Frame Format Select mask. +#define SSP_CR0_FRF_M BIT_MASK(32, 5, 4) + +//! Frame Format Select shift. +#define SSP_CR0_FRF_S 4 + +//! Clock Polarity control +#define SSP_CR0_CPOL BIT_32_6 + +//! Clock Phase control +#define SSP_CR0_CPHA BIT_32_7 + +//! Serial Clock Rate mask +#define SSP_CR0_SCR_M BIT_MASK(32, 15, 8) + +//! Serial Clock Rate shift +#define SSP_CR0_SCR_S 8 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_CR1 SSP Register SSP_CR1 +//! \brief SSP SSP_CR1 Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Loop Back Mode. +#define SSP_CR1_LBM BIT_32_0 + +//! SSP Enable. +#define SSP_CR1_SSE BIT_32_1 + +//! Master/Slave Mode. +#define SSP_CR1_MS BIT_32_2 + +//! Slave Output Disable +#define SSP_CR1_SOD BIT_32_3 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_DR SSP Register SSP_DR +//! \brief SSP SSP_DR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! SSP data mask. +#define SSP_DR_DATA_M BIT_MASK(32, 15, 0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_SR SSP Register SSP_SR +//! \brief SSP SSP_SR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Transmit FIFO Empty. +#define SSP_SR_TFE BIT_32_0 + +//! Transmit FIFO Not Full. +#define SSP_SR_TNF BIT_32_1 + +//! Receive FIFO Not Empty. +#define SSP_SR_RNE BIT_32_2 + +//! Receive FIFO Full +#define SSP_SR_RFF BIT_32_3 + +//! Busy Flag. +#define SSP_SR_BSY BIT_32_4 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_CPSR SSP Register SSP_CPSR +//! \brief SPI SSP_CPSR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! SSPn Clock Prescale. +#define SSP_CPSR_CPSDVSR_M BIT_MASK(32, 7, 0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_IMSC SSP Register SSP_IMSC +//! \brief SSP SSP_IMSC Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Receive Overrun Interrupt. +#define SSP_IMSC_ROR BIT_32_0 + +//! Receive Timeout Interrupt. +#define SSP_IMSC_RT BIT_32_1 + +//! Rx FIFO half full Interrupt. +#define SSP_IMSC_RX BIT_32_2 + +//! Tx FIFO half empty Interrupt +#define SSP_IMSC_TX BIT_32_3 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_RIS SSP Register SSP_RIS +//! \brief SSP SSP_RIS Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Receive Overrun. +#define SSP_RIS_ROR BIT_32_0 + +//! Receive Timeout. +#define SSP_RIS_RT BIT_32_1 + +//! Rx FIFO half full. +#define SSP_RIS_RX BIT_32_2 + +//! Tx FIFO half empty +#define SSP_RIS_TX BIT_32_3 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_MIS SSP Register SSP_MIS +//! \brief SSP SSP_MIS Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Receive Overrun. +#define SSP_MIS_ROR BIT_32_0 + +//! Receive Timeout. +#define SSP_MIS_RT BIT_32_1 + +//! Rx FIFO half full. +#define SSP_MIS_RX BIT_32_2 + +//! Tx FIFO half empty +#define SSP_MIS_TX BIT_32_3 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_ICR SSP Register SSP_ICR +//! \brief SSP SSP_ICR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Clear Receive Overrun flag. +#define SSP_ICR_ROR BIT_32_0 + +//! Clear Receive Timeout flag. +#define SSP_ICR_RT BIT_32_1 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SSP_Register_SSP_DMACR SSP Register SSP_DMACR +//! \brief SSP SSP_DMACR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Receive DMA Enable. +#define SSP_DMACR_RXDMAE BIT_32_0 + +//! Transmit DMA Enable. +#define SSP_DMACR_TXDMAE BIT_32_1 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + + + +//***************************************************************************** +// +//! \addtogroup LPC175x_6x_SPI_Register_Offsets SPI Register Offset(Map) +//! \brief Here is the register offset, users can get the register address +//! via SPI2_BASE + offset. +//! @{ +// +//***************************************************************************** + +//! SPI Control Register. +//! This register controls the operation of the SPI. +#define SPI_CR 0x00000000 + +//! SPI Status Register. +//! This register shows the status of the SPI. +#define SPI_SR 0x00000004 + +//! SPI Data Register. +//! This bi-directional register provides the transmit and receive data for the SPI. +//! Transmit data is provided to the SPI0 by writing to this register. +//! Data received by the SPI0 can be read from this register. +#define SPI_DR 0x00000008 + +//! SPI Clock Counter Register. +//! This register controls the frequency of a master¡¯s SCK0. +#define SPI_CCR 0x0000000C + +//! SPI Interrupt Flag. +//! This register contains the interrupt flag for the SPI interface. +#define SPI_INT 0x0000001C + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC175x_6x_SPI_Register_S0SPCR SPI Register S0SPCR +//! \brief SPI SPI_CR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! SPI BIt control. +//! When set, SPI controller send 8-->16 bit data according to other register bits. +//! When Clear, SPI data length is fixed to 8-bit. +#define SPI_CR_BIT_EN BIT_32_2 + +//! Clock Phase control +#define SPI_CR_CPHA BIT_32_3 + +//! Clock Polarity control +#define SPI_CR_CPOL BIT_32_4 + +//! Master Mode Select +#define SPI_CR_MSTR BIT_32_5 + +//! LSB First controls which direction each byte is shifted when transferred. +#define SPI_CR_LSBF BIT_32_6 + +//! Enable serial peripheral interrupt +#define SPI_CR_SPIE BIT_32_7 + +//! SPI data length mask +#define SPI_CR_BITS_M BIT_MASK(32, 11, 8) + +//! SPI data length shift +#define SPI_CR_BITS_S 8 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC175x_6x_SPI_Register_SPI_SR SPI Register SPI_SR +//! \brief SPI SPI_SR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Slave abort +#define SPI_SR_ABRT BIT_32_3 + +//! Mode Fault +#define SPI_SR_MODF BIT_32_4 + +//! Read overrun +#define SPI_SR_ROVR BIT_32_5 + +//! Write collision +#define SPI_SR_WCOL BIT_32_6 + +//! Transfer complete +#define SPI_SR_SPIF BIT_32_7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC175x_6x_SPI_Register_SPI_DR SPI Register SPI_DR +//! \brief SPI SPI_DR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! SPI data mask +#define SPI_DR_DATA_M BIT_MASK(32, 15, 0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC175x_6x_SPI_Register_SPI_CCR SPI Register SPI_CCR +//! \brief SPI SPI_CCR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! SPI Clock counter setting +#define SPI_CCR_CNT_M BIT_MASK(32, 7, 0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC175x_6x_SPI_Register_SPI_INT SPI Register SPI_INT +//! \brief SPI SPI_INT Register description. +//! +//! @{ +// +//***************************************************************************** + +//! SPI interrupt flag. +#define SPI_INT_SPIF BIT_32_0 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +#endif // __LPC17XX_HW_SPI_H__ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_uart.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_uart.h new file mode 100644 index 00000000..86aa0393 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_uart.h @@ -0,0 +1,704 @@ +//***************************************************************************** +// +//! \file hw_uart.h +//! \brief Macros used when accessing the UART hardware. +//! \version V3.0.0.0 +//! \date $CURRENTTIME$ +//! \author CooCox +//! \copyright +//! +//! Copyright (c) 2014, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __LPC17XX_HW_UART_H__ +#define __LPC17XX_HW_UART_H__ + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup UART +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register UART Register Hardware Layer. +//! \brief Here are detail register information. +//! it contains: +//! - Register offset. +//! - detailed bit-field of the registers. +//! - Enum and mask of the registers. +//! +//! \note Users can read or write the registers via xHWREG(). +//! +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_Uart_Register_Offsets Uart Register Offset(Map) +//! \brief Here is the register offset, users can get the register address +//! via UARTn_BASE + offset, (n=0/1/...) +//! @{ +// +//***************************************************************************** + +//! RBR (DLAB =0) Receiver Buffer Register. Contains the next received +//! character to be read. +#define RBR ((unsigned long)0x00000000) + +//! THR (DLAB =0) Transmit Holding Register. The next character to be +//! transmitted is written here. +#define THR ((unsigned long)0x00000000) + +//! DLL (DLAB =1) Divisor Latch LSB. Least significant byte of the baud rate +//! divisor value. The full divisor is used to generate a baud rate from the +//! fractional rate divider. +#define DLL ((unsigned long)0x00000000) + +//! DLM (DLAB =1) Divisor Latch MSB. Most significant byte of the baud rate +//! divisor value. The full divisor is used to generate a baud rate from the +//! fractional rate divider. +#define DLM ((unsigned long)0x00000004) + +//! IER (DLAB =0) Interrupt Enable Register. Contains individual interrupt +//! enable bits for the 7 potential UART interrupts. +#define IER ((unsigned long)0x00000004) + +//! IIR Interrupt ID Register. Identifies which interrupt(s) are pending. +#define IIR ((unsigned long)0x00000008) + +//! FCR FIFO Control Register. Controls UART FIFO usage and modes. +#define FCR ((unsigned long)0x00000008) + +//! LCR Line Control Register. Contains controls for frame formatting and break +//! generation. +#define LCR ((unsigned long)0x0000000C) + +//! Modem Control Register. Contains controls for flow control +//! handshaking and loopback mode. +#define MCR ((unsigned long)0x00000010) + +//! LSR Line Status Register. Contains flags for transmit and receive status, +//! including line errors. +#define LSR ((unsigned long)0x00000014) + +//! Modem Status Register. Contains handshake signal status flags +#define MSR ((unsigned long)0x00000018) + +//! SCR Scratch Pad Register. 8-bit temporary storage for software. +#define SCR ((unsigned long)0x0000001C) + +//! ACR Auto-baud Control Register. Contains controls for the auto-baud feature. +#define ACR ((unsigned long)0x00000020) + +//! ICR IrDA Control Register. Enables and configures the IrDA mode. +#define ICR ((unsigned long)0x00000024) + +//! FDR Fractional Divider Register. Generates a clock input for the baud rate +//! divider. +#define FDR ((unsigned long)0x00000028) + +//! TER Transmit Enable Register. Turns off UART transmitter for use with +//! software flow control. +#define TER ((unsigned long)0x00000030) + + +//! RS-485/EIA-485 Control. Contains controls to configure various +//! aspects of RS-485/EIA-485 modes. +#define RS485CTRL ((unsigned long)0x0000004C) + +//! RS-485/EIA-485 address match. Contains the address match value +//! for RS-485/EIA-485 mode. +#define ADRMATCH ((unsigned long)0x00000050) + +//! RS-485/EIA-485 direction control delay. +#define RS485DLY ((unsigned long)0x00000054) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_DLL UART Register DLL +//! \brief UART DLL Register description. +//! +//! @{ +// +//***************************************************************************** + +//! The UARTn Divisor Latch LSB Register, along with the UnDLM +//! register, determines the baud rate of the UARTn. +#define DLL_SB_M BIT_MASK(32, 7, 0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_DLM UART Register DLM +//! \brief UART DLM Register description. +//! +//! @{ +// +//***************************************************************************** + +//! The UARTn Divisor Latch MSB Register, along with the U0DLL register, +//! determines the baud rate of the UARTn. +#define DLM_SB_M BIT_MASK(32, 7, 0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_IER UART Register IER +//! \brief UART IER Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Enables the Receive Data Available interrupt for UARTn. It also controls +//! the Character Receive Time-out interrupt +#define IER_RBR_INT_EN BIT_32_0 + +//! Enables the THRE interrupt for UARTn. The status of this can be read +//! from UnLSR[5]. +#define IER_THRE_INT_EN BIT_32_1 + +//! Enables the UARTn RX line status interrupts. The status of this interrupt +//! can be read from UnLSR[4:1]. +#define IER_RX_LINE_STAT_INT_EN BIT_32_2 + +//! Modem Status Interrupt Enable +#define IER_MODEM_STAT_INT_EN BIT_32_3 + +//! CTS Interrupt Enable +#define IER_CTS_INT_EN BIT_32_7 + +//! Enables the end of auto-baud interrupt. +#define IER_ABEO_INT_EN BIT_32_8 + +//! Enables the auto-baud time-out interrupt. +#define IER_ABTO_INT_EN BIT_32_9 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_IIR UART Register IIR +//! \brief UART IIR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can +//! be determined by evaluating UnIIR[3:1]. +//! 0 At least one interrupt is pending. +//! 1 No interrupt is pending. +#define IIR_INT_STAT BIT_32_0 + +//! Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the +//! UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below +//! are reserved (000,100,101,111). +//! 011 1 - Receive Line Status (RLS). +//! 010 2a - Receive Data Available (RDA). +//! 110 2b - Character Time-out Indicator (CTI). +//! 001 3 - THRE Interrupt +#define IIR_INT_ID_M BIT_MASK(32, 3, 1) + +//! Receive Line Status +#define IIR_INT_ID_RLS (BIT_32_2 | BIT_32_1) + +//! Receive Data Available +#define IIR_INT_ID_RDA BIT_32_2 + +//! Character Time-Out Indicator +#define IIR_INT_ID_CTI BIT_32_3 | BIT_32_2 + +//! THRE Interrupt +#define IIR_INT_ID_THRE BIT_32_1 + +//! Modem Interrupt +#define IIR_INT_ID_MODEM BIT_32_ALL_0 + +//! Copies of UnFCR +#define IIR_FIFO_EN_M BIT_MASK(32, 7, 6) + +//! End of auto-baud interrupt. +#define IIR_ABEO_INT BIT_32_8 + +//! Auto-baud time-out interrupt. +#define IIR_ABTO_INT BIT_32_9 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_FCR UART Register FCR +//! \brief UART FCR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! FIFO Enable +#define FCR_FIFO_EN BIT_32_0 + +//! Reset RX FIFO +#define FCR_RX_FIFO_RESET BIT_32_1 + +//! Reset TX FIFO +#define FCR_TX_FIFO_RESET BIT_32_2 + +//! DMA Mode Select +#define FCR_DMA_MODE BIT_32_3 + +//! RX Trigger Level. +#define FCR_RX_TRI_LEVEL_M BIT_MASK(32, 7, 6) + +//! Trigger level 0 (1 character) +#define FCR_RX_TRI_LEVEL_0 BIT_32_ALL_0 + +//! Trigger level 1 (4 character) +#define FCR_RX_TRI_LEVEL_1 BIT_32_6 + +//! Trigger level 2 (8 character) +#define FCR_RX_TRI_LEVEL_2 BIT_32_7 + +//! Trigger level 3 (14 character) +#define FCR_RX_TRI_LEVEL_3 (BIT_32_7 | BIT_32_6) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_LCR UART Register LCR +//! \brief UART LCR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Character Length +#define LCR_WORD_LEN_M BIT_MASK(32, 1, 0) + +//! 5-bit length +#define LCR_WORD_LEN_5_BIT BIT_32_ALL_0 + +//! 6-bit length +#define LCR_WORD_LEN_6_BIT BIT_32_0 + +//! 7-bit length +#define LCR_WORD_LEN_7_BIT BIT_32_1 + +//! 8-bit length +#define LCR_WORD_LEN_8_BIT (BIT_32_1 | BIT_32_0) + +//! Stop Bit +#define LCR_STOP_BIT BIT_32_2 + +//! Parity Enable +#define LCR_PARITY_EN BIT_32_3 + +//! Parity Select +#define LCR_PARITY_SEL_M BIT_MASK(32, 5, 4) + +//! Odd parity +#define LCR_PARITY_ODD BIT_32_ALL_0 + +//! Even parity +#define LCR_PARITY_EVEN BIT_32_4 + +//! Stick to 1 parity +#define LCR_PARITY_1 BIT_32_5 + +//! Stick to 0 parity +#define LCR_PARITY_0 (BIT_32_5 | BIT_32_4) + +//! Break Control +#define LCR_BREAK_CTL BIT_32_6 + +//! Divisor Latch Acess Bit(DLAB) +#define LCR_DLAB BIT_32_7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_MCR UART Register MCR +//! \brief UART MCR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode +//! is active. +#define MCR_DTR_CTL BIT_32_0 + +//! Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is +//! active. +#define MCR_RTS_CTL BIT_32_1 + +//! Loopback Mode Select +#define MCR_LOOPBACK_SEL BIT_32_4 + +//! Auto-RTS Flow control +#define MCR_RTS_EN BIT_32_6 + +//! Auto-CTS Flow control +#define MCR_CTS_EN BIT_32_7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_LSR UART Register LSR +//! \brief UART LSR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Receiver Data Ready +#define LSR_RDR BIT_32_0 + +//! Overrun Error +#define LSR_OE BIT_32_1 + +//! Parity Error +#define LSR_PE BIT_32_2 + +//! Framing Error +#define LSR_FE BIT_32_3 + +//! Break Interrupt +#define LSR_BI BIT_32_4 + +//! Transmitter Holding Register Empty +#define LSR_THRE BIT_32_5 + +//! Transmitter Empty +#define LSR_TEMT BIT_32_6 + +//! Error in RX FIFO +#define LSR_RXFE BIT_32_7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_MSR UART Register MSR +//! \brief UART MSR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Delta CTS +#define MSR_DELTA_CTS BIT_32_0 + +//! Delta DSR +#define MSR_DELTA_DSR BIT_32_1 + +//! Trailing Edge RI +//! Set upon low to high transition of input RI. Cleared on an U1MSR read +#define MSR_TRAIL_EDGE_RI BIT_32_2 + +//! Delta DCD +#define MSR_DELTA_DCD BIT_32_3 + +//! Clear to Send State. +#define MSR_CTS BIT_32_4 + +//! Data Set Ready State. +#define MSR_DSR BIT_32_5 + +//! Ring Indicator State. +#define MSR_RI BIT_32_6 + +//! Data Carrier Detect State. +#define MSR_DCD BIT_32_7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_SCR UART Register SCR +//! \brief UART SCR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! UART Scratch Pad Mask +#define SCR_PAD_M BIT_MASK(32, 7, 0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_ACR UART Register ACR +//! \brief UART ACR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Start Auto-Baud +#define ACR_START BIT_32_0 + +//! Auto-Baud Mode Select bit. +#define ACR_MODE BIT_32_1 + +//! Auto ReStart +#define ACR_AUTO_RESTART BIT_32_2 + +//! End of auto-baud interrupt clear bit. +#define ACR_ABEO_INT_CLR BIT_32_8 + +//! Auto-baud time-out interrupt clear bit. +#define ACR_ABTO_INT_CLR BIT_32_9 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_ICR UART Register ICR +//! \brief UART ICR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! IrDA Enable +#define ICR_IRDA_EN BIT_32_0 + +//! IrDA Invert +#define ICR_IRDA_INV BIT_32_1 + +//! Enable IrDA Fixed Pulse width mode. +#define ICR_FIX_PULSE_EN BIT_32_2 + +//! Pulse Divider. +#define ICR_PULSE_DIV_M BIT_MASK(32, 5, 3) +#define ICR_PULSE_DIV_S 3 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_FDR UART Register FDR +//! \brief UART FDR Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Baud-rate generation pre-scaler divisor value. +#define FDR_DIVADDVAL_M BIT_MASK(32, 3, 0) +#define FDR_DIVADDVAL_S 0 + +//! Baud-rate pre-scaler multiplier value. +#define FDR_MULVAL_M BIT_MASK(32, 7, 4) +#define FDR_MULVAL_S 4 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_TER UART Register TER +//! \brief UART TER Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Transmitter Enable +#define TER_TX_EN BIT_32_7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_RS485CTRL UART Register RS485CTRL +//! \brief UART RS485CTRL Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Normal Mulitdrop Mode. +#define RS485CTRL_NMMEN BIT_32_0 + +//! Receive Disable. +#define RS485CTRL_RXDIS BIT_32_1 + +//! Auto Address Detect +#define RS485CTRL_AADEN BIT_32_2 + +//! Direct pin select +#define RS485CTRL_SEL BIT_32_3 + +//! Direction control +#define RS485CTRL_DCTRL BIT_32_4 + +//! Direction Control Invert +#define RS485CTRL_OINV BIT_32_5 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_RS485ADRMATCH UART Register RS485ADRMATCH +//! \brief UART RS485ADRMATCH Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Address match value. +#define RS485ADRMATCH_ADRMATCH_M BIT_MASK(32, 7, 0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Register_RS485DLY UART Register RS485DLY +//! \brief UART RS485DLY Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Direction control delay value. +#define RS485DLY_DLY_M BIT_MASK(32, 7, 0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +#endif // __LPC17XX_HW_UART_H__ + diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_wdt.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_wdt.h new file mode 100644 index 00000000..e6868cb4 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/hw_wdt.h @@ -0,0 +1,181 @@ +//***************************************************************************** +// +//! \file hw_wdt.h +//! \brief Macros used when accessing the WDT hardware. +//! \version V3.0.0.0 +//! \date $CURRENTTIME$ +//! \author CooCox +//! \copyright +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __LPC17XX_HW_WDT_H__ +#define __LPC17XX_HW_WDT_H__ + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup WDT +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_WDT_Register WDT Register Hardware Layer. +//! \brief Here are detail register information. +//! it contains: +//! - Register offset. +//! - detailed bit-field of the registers. +//! - Enum and mask of the registers. +//! +//! \note Users can read or write the registers via xHWREG(). +//! +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_Wdt_Register_Offsets Wdt Register Offset(Map) +//! \brief Here is the register offset, users can get the register address +//! via WDT_BASE + offset. +//! @{ +// +//***************************************************************************** + +//! Watchdog mode register. +//! This register contains the basic mode and status of the Watchdog Timer. +#define WDT_MOD ((unsigned long)0x00000000) + +//! Watchdog timer constant register. +//! This register determines the time-out value. +#define WDT_TC ((unsigned long)0x00000004) + +//! Watchdog feed sequence register. +//! Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer +//! with the value contained in WDTC. +#define WDT_FEED ((unsigned long)0x00000008) + +//! Watchdog timer value register. +//! This register reads out the current value of the Watchdog timer. +#define WDT_TV ((unsigned long)0x0000000C) + +//! Watchdog clock source selection register. +#define WDT_CLKSEL ((unsigned long)0x00000010) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_WDT_Register_WDMOD WDMOD Register CLKSEL +//! \brief WDT WDMOD Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Enable Watchdog +#define WDMOD_EN BIT_32_0 + +//! Reset Mode. +#define WDMOD_RESET BIT_32_1 + +//! Watchdog time-out flag. +#define WDMOD_TOF BIT_32_2 + +//! Watchdog interrupt flag. +#define WDMOD_INT BIT_32_3 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_WDT_Register_CLKSEL WDT Register CLKSEL +//! \brief WDT CLKSEL Register description. +//! +//! @{ +// +//***************************************************************************** + +//! Watchdog clock source. +#define WDCLKSEL_WDSEL_M BIT_MASK(32, 1, 0) + +//! Use internal RC clock as wdt clock source. +#define WDCLKSEL_WDSEL_IRC BIT_32_ALL_0 + +//! Use APB clock as wdt clock source. +#define WDCLKSEL_WDSEL_APB BIT_32_0 + +//! Use RTC clock as wdt clock source. +#define WDCLKSEL_WDSEL_RTC BIT_32_1 + +//! Lock watchdog register. +#define WDCLKSEL_WDLOCK BIT_32_31 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +#endif // __LPC17XX_HW_WDT_H__ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/lowlayer.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/lowlayer.h new file mode 100644 index 00000000..94db59ad --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/lowlayer.h @@ -0,0 +1,277 @@ +//***************************************************************************** +// +//! \file lowlayer.h +//! \brief Macros defining of Peripehral Base and interrupt assignments for LPC17xx. +//! \version V3.0.0.0 +//! \date $CURRENTTIME$ +//! \author CooCox +//! \copyright +//! +//! Copyright (c) 2014, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __LPC17XX_LOWLAYER__ +#define __LPC17XX_LOWLAYER__ + + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_LowLayer +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_owLayer_Peripheral_Memmap LPC17xx Peripheral Memmap +//! \brief The following are definitions for the base addresses of the memories +//! and peripherals. +//! +//! They are always used as ulBase parameters in the peripheral library. +//! The name of a macro for the base address of a peripheral is in general +//! format as $Namen$_BASE, e.g. UART0_BASE. +//! +//! @{ +// +//***************************************************************************** + +#define FLASH_BASE 0x08000000 // Flash memory +#define SRAM_BASE 0x20000000 // SRAM memory + +#if 0 +//LPC17nx AHB (n = 5/6) +#define ETH_BASE 0x50000000 // Ethernet MAC +#define DMA0_BASE 0x50004000 // General Purpose DMA controller +#define USBD_BASE 0x5000C000 // USB interface + +#define GPIOA_BASE 0x2009C000 // GPIO Port A +#define GPIOB_BASE 0x2009C020 // GPIO Port B +#define GPIOC_BASE 0x2009C040 // GPIO Port C +#define GPIOD_BASE 0x2009C060 // GPIO Port D +#define GPIOE_BASE 0x2009C080 // GPIO Port E +#endif + +// LPC17nx AHB (n = 7/8) +#define DMA0_BASE 0x20080000 // General Purpose DMA controller +#define ETH_BASE 0x20084000 // Ethernet MAC +#define LCD_BASE 0x20088000 // LCD controller +#define USBD_BASE 0x2008C000 // USB interface +#define CRC_BASE 0x20090000 // CRC engine +#define GPIOA_BASE 0x20098000 // GPIO Port A +#define GPIOB_BASE 0x20098020 // GPIO Port B +#define GPIOC_BASE 0x20098040 // GPIO Port C +#define GPIOD_BASE 0x20098060 // GPIO Port D +#define GPIOE_BASE 0x20098080 // GPIO Port E +#define GPIOF_BASE 0x200980A0 // GPIO Port F +#define EMC_BASE 0x2009C000 // External Memory Controller + +//APB0 +#define WDT_BASE 0x40000000 // Watchdog Timer +#define TIMER0_BASE 0x40004000 // Timer 0 +#define TIMER1_BASE 0x40008000 // Timer 1 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x40010000 // UART1 +#define PWMA_BASE 0x40014000 // PWMA +#define PWMB_BASE 0x40018000 // PWMB +#define I2C0_BASE 0x4001C000 // I2C0 +#define SPI_BASE 0x40020000 // SPI +#define RTC_BASE 0x40024000 // RTC and Event Monitor/Recorder +#define GPIO_INT_BASE 0x40028000 // GPIO interrupts +#define PIN_CON_BASE 0x4002C000 // Pin Connect Block +#define SSP1_BASE 0x40030000 // SSP1 +#define ADC0_BASE 0x40034000 // ADC +#define CAN_AF_RAM_BASE 0x40038000 // CAN Acceptance Filter RAM +#define CAN_AF_REG_BASE 0x4003C000 // CAN Acceptance Filter Registers +#define CAN_COMM_BASE 0x40040000 // CAN Common Registers +#define CAN1_BASE 0x40044000 // CAN Controller 1 +#define CAN2_BASE 0x40048000 // CAN Controller 2 +#define I2C1_BASE 0x4005C000 // I2C1 + +//APB1 +#define SSP0_BASE 0x40088000 // SSP0 +#define DAC0_BASE 0x4008C000 // DAC +#define TIMER2_BASE 0x40090000 // Timer 2 +#define TIMER3_BASE 0x40094000 // Timer 3 +#define UART2_BASE 0x40098000 // UART2 +#define UART3_BASE 0x4009C000 // UART3 +#define I2C2_BASE 0x400A0000 // I2C2 +#define UART4_BASE 0x400A4000 // UART4 +#define I2S0_BASE 0x400A8000 // I2S +#define SSP2_BASE 0x400AC000 // SSP2 +#define RIT_BASE 0x400B0000 // Repetitive interrupt timer +#define MCPWM_BASE 0x400B8000 // Motor control PWM +#define QEI_BASE 0x400BC000 // Quadrature Encoder Interface +#define SDC_BASE 0x400C0000 // SD card interface +#define SYSCTL_BASE 0x400FC000 // System control + +//Core components +#define ITM_BASE 0xE0000000 // +#define DWT_BASE 0xE0001000 // +#define FPB_BASE 0xE0002000 // +#define NVIC_BASE 0xE000E000 // +#define TPIU_BASE 0xE0040000 // +#define COREDEBUG_BASE 0xE000EDF0 // + +#define SPI0_BASE SSP0_BASE +#define SPI1_BASE SSP1_BASE +#if (defined (LPC_175x) || defined (LPC_176x)) +#define SPI2_BASE SPI_BASE +#elif (defined (LPC_177x) || defined (LPC_178x)) +#define SPI2_BASE SSP2_BASE +#endif +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_Interrupt_Assignments LPC17xx Interrupt Assignments +//! \brief Macro definitions for the fault/interrupt assignments. +//! +//! They can be used as ulInterrupt parameters with xIntEnable(), xIntDisable() +//! to enable/disable the interrupt at the core/NVIC level. +//! +//! @{ +// +//***************************************************************************** + +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +#define INT_WDT 16 // Watchdog timer +#define INT_TIMER0 17 // Timer 0 +#define INT_TIMER1 18 // Timer 1 +#define INT_TIMER2 19 // Timer 2 +#define INT_TIMER3 20 // Timer 3 +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_UART2 23 // UART2 Rx and Tx +#define INT_UART3 24 // UART3 Rx and Tx +#define INT_PWMB 25 // PWM Generator 1 +#define INT_I2C0 26 // I2C0 Master and Slave +#define INT_I2C1 27 // I2C1 Master and Slave +#define INT_I2C2 28 // I2C2 Master and Slave +#define INT_SPI 29 // SPI +#define INT_SSP0 30 // SSP0 Rx and Tx +#define INT_SSP1 31 // SSP1 Rx and Tx +#define INT_PLL0 32 // PLL0 Lock (PLOCK0) +#define INT_RTC 33 // RTC & EV0, EV1, EV2 +#define INT_EINT0 34 // External Line0 Interrupt +#define INT_EINT1 35 // External Line1 Interrupt +#define INT_EINT2 36 // External Line2 Interrupt +#define INT_EINT3 37 // External Line3 Interrupt +#define INT_ADC0 38 // ADC +#define INT_BOD 39 // Brown Out detect +#define INT_USB 40 // USB Controller +#define INT_CAN 41 // CAN 0 Interrupts +#define INT_DMA 42 // DMA controller +#define INT_I2S 43 // I2S +#define INT_ETH 44 // Ethernet +#define INT_RIT 45 // RIT +#define INT_MCPWM 46 // Motor Control PWM +#define INT_QEI 47 // Quadrature Encoder Interface +#define INT_PLL1 48 // PLL1 Lock (Alt PLL) +#define INT_USBACT 49 // USB Activity Interrupt +#define INT_CANWAKE 50 // CAN Activity Interrupt +#define INT_UART4 51 // UART4 Rx and Tx +#define INT_SSP2 52 // SSP1 Rx and Tx +#define INT_LCD 53 // LCD controller +#define INT_GPIO 54 // GPIO interrupts +#define INT_PWMA 55 // PWM0 +#define INT_EEPROM 56 // EEPROM + + +#define INT_CAN1 INT_CAN +#define INT_CAN2 INT_CAN +#define INT_DMA0 INT_DMA +#define INT_I2S0 INT_I2S +#define INT_USBD INT_USB +#define INT_USBH INT_USB +#define INT_SPI0 INT_SSP0 +#define INT_SPI1 INT_SSP1 +#define INT_SPI2 INT_SPI + +#define INT_GPIOA INT_GPIO +#define INT_GPIOB INT_GPIO +#define INT_GPIOC INT_GPIO +#define INT_GPIOD INT_GPIO +#define INT_GPIOE INT_GPIO +#define INT_GPIOF INT_GPIO + +// +//! The total number of interrupts. +// +#define NUM_INTERRUPTS 58 + +// +//! The total number of priority levels +// +#define NUM_PRIORITY 8 + +// +//! The Total number of priority levels (bits) +// +#define NUM_PRIORITY_BITS 5 + + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +#endif // __LPC17XX_LOWLAYER__ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/rtc.c b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/rtc.c new file mode 100644 index 00000000..0ebfacb9 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/rtc.c @@ -0,0 +1,472 @@ +//***************************************************************************** +// +//! \file rtc.c +//! \brief Driver for the RTC +//! \version V2.2.1.0 +//! \date 8/15/2014 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2014, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +#include "CoX.h" +#include "hw_rtc.h" + +//***************************************************************************** +// +// An array is RTC callback function point +// +//***************************************************************************** +static xtEventCallback g_pfnRTCHandlerCallbacks = 0; + +// RTC Mask code +// Note: Only for internal use! +#define SEC_MASK BIT_MASK(32, 5, 0) +#define MIN_MASK BIT_MASK(32, 5, 0) +#define HOUR_MASK BIT_MASK(32, 4, 0) +#define DOM_MASK BIT_MASK(32, 4, 0) +#define DOW_MASK BIT_MASK(32, 2, 0) +#define DOY_MASK BIT_MASK(32, 8, 0) +#define MONTH_MASK BIT_MASK(32, 3, 0) +#define YEAR_MASK BIT_MASK(32, 11, 0) + +//***************************************************************************** +// +//! \brief RTC interrupt handler. +//! +//! This function is the RTC interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! \return None. +//! +// +//***************************************************************************** +void RTCIntHandler(void) +{ + if(g_pfnRTCHandlerCallbacks != 0) + { + g_pfnRTCHandlerCallbacks(0, 0, 0, 0); + } +} + +//***************************************************************************** +// +//! \brief Register user's interrupt callback function for the RTC. +//! +//! \param [in] xtPortCallback is user callback for the RTC. +//! +//! \return None. +// +//***************************************************************************** +void xRTCIntCallbackInit(xtEventCallback pfnCallback) +{ + // Check the parameters. + xASSERT(pfnCallback != 0); + + g_pfnRTCHandlerCallbacks = pfnCallback; +} + +//***************************************************************************** +// +//! \brief Get RTC Interrupt status. +//! This function is used to get RTC interrupt status. +//! +//! \param None. +//! +//! \return The status of RTC interrupt, which contains of the OR of following value: +//! - \ref RTC_INT_INC +//! - \ref RTC_INT_ALARM +//! +// +//***************************************************************************** +unsigned long RTCIntFlagGet(void) +{ + return xHWREG(RTC_BASE + RTC_ILR); +} + +//***************************************************************************** +// +//! \brief Check RTC status flag. +//! This function is used to check whether special flag is set or not. +//! +//! \param [in] ulFlags is the flag you want to check +//! This value is the OR of the following value: +//! - \ref RTC_INT_INC +//! - \ref RTC_INT_ALARM +//! +//! \return The status of special flag. +//! - xtrue The check flag has been set. +//! - xflase The check flag has not been set. +//! +// +//***************************************************************************** +xtBoolean RTCIntFlagCheck(unsigned long ulFlags) +{ + xASSERT( !(ulFlags & ~( RTC_INT_INC | RTC_INT_ALARM ))); + + if(xHWREG(RTC_BASE + RTC_ILR) & ulFlags) + { + return (xtrue); + } + else + { + return (xfalse); + } +} + +//***************************************************************************** +// +//! \brief Clear RTC interrupt status flag. +//! This function can be used to clear special RTC interrupt status flag. +//! +//! \param [in] ulFlags is RTC interrupt status flag. +//! This parameter can be OR of the following value: +//! - \ref RTC_INT_INC +//! - \ref RTC_INT_ALARM +//! +//! \return None. +//! +// +//***************************************************************************** +void RTCIntFlagClear(unsigned long ulFlags) +{ + xASSERT( !(ulFlags & ~( RTC_INT_INC | RTC_INT_ALARM ))); + xHWREG(RTC_BASE + RTC_ILR) |= ulFlags; +} + +//***************************************************************************** +// +//! \brief Enable RTC function and start counter. +//! +//! \param None. +//! +//! \return None. +// +//***************************************************************************** +void xRTCStart(void) +{ + xHWREG(RTC_BASE + RTC_CCR) |= CCR_CLKEN; +} + +//***************************************************************************** +// +//! \brief Disable RTC function and start counter. +//! +//! \param None. +//! +//! \return None. +// +//***************************************************************************** +void xRTCStop(void) +{ + xHWREG(RTC_BASE + RTC_CCR) &= ~CCR_CLKEN; +} + +//***************************************************************************** +// +//! \brief Reset and Initializes RTC counter and time value. +//! +//! \param None. +//! +//! \return The result of operation. +//! - xtrue Initializes successfully +//! - xfalse Initializes fail +// +//***************************************************************************** +xtBoolean xRTCTimeInit(void) +{ + xHWREG(RTC_BASE + RTC_CCR) |= CCR_CTCRST; + xHWREG(RTC_BASE + RTC_CCR) &= ~CCR_CTCRST; + + return 1; +} + +//***************************************************************************** +// +//! \brief Configure RTC interrupt mode. +//! This function can be used to enable/disable rtc time/alarm interrupt. +//! +//! \param [in] ulCfg is interrupt configure parameters. +//! This value can be the logical OR of the following value: +//! - \ref INT_SEC_EN Enable second interrupt +//! - \ref INT_MIN_EN Enable minute interrupt +//! - \ref INT_HOUR_EN Enable hour interrupt +//! - \ref INT_DOM_EN Enable day of month interrupt +//! - \ref INT_DOW_EN Enable day of week interrupt +//! - \ref INT_DOY_EN Enable day of year interrupt +//! - \ref INT_MON_EN Enable month interrupt +//! - \ref INT_YEAR_EN Enable year interrupt +//! - \ref INT_SEC_DIS Disable second interrupt +//! - \ref INT_MIN_DIS Disable minute interrupt +//! - \ref INT_HOUR_DIS Disable hour interrupt +//! - \ref INT_DOM_DIS Disable day of month interrupt +//! - \ref INT_DOW_DIS Disable day of week interrupt +//! - \ref INT_DOY_DIS Disable day of year interrupt +//! - \ref INT_MON_DIS Disable month interrupt +//! - \ref INT_YEAR_DIS Disable year interrupt +//! - \ref INT_ALARM_SEC_EN Enable second alarm interrupt +//! - \ref INT_ALARM_MIN_EN Enable minute alarm interrupt +//! - \ref INT_ALARM_HOUR_EN Enable hour alarm interrupt +//! - \ref INT_ALARM_DOM_EN Enable day of month alarm interrupt +//! - \ref INT_ALARM_DOW_EN Enable day of week alarm interrupt +//! - \ref INT_ALARM_DOY_EN Enable day of year alarm interrupt +//! - \ref INT_ALARM_MON_EN Enable month alarm interrupt +//! - \ref INT_ALARM_YEAR_EN Enable year alarm interrupt +//! - \ref INT_ALARM_SEC_DIS Disable second alarm interrupt +//! - \ref INT_ALARM_MIN_DIS Disable minute alarm interrupt +//! - \ref INT_ALARM_HOUR_DIS Disable hour alarm interrupt +//! - \ref INT_ALARM_DOM_DIS Disable day of month alarm interrupt +//! - \ref INT_ALARM_DOW_DIS Disable day of week alarm interrupt +//! - \ref INT_ALARM_DOY_DIS Disable day of year alarm interrupt +//! - \ref INT_ALARM_MON_DIS Disable month alarm interrupt +//! - \ref INT_ALARM_YEAR_DIS Disable year alarm interrupt +//! +//! \return None. +// +//***************************************************************************** +void RTCIntCfg(unsigned long ulCfg) +{ + unsigned long ulTmpReg = 0; + + // Check the parameters. + xASSERT(ulCfg != 0); + + // Configure Increment Interrupt. + if(ulCfg & 0x0000FFFF) + { + ulTmpReg = xHWREG(RTC_BASE + RTC_CIIR); + ulTmpReg &= ~((ulCfg >> 8) & 0xFF); + ulTmpReg |= ((ulCfg >> 0) & 0xFF); + xHWREG(RTC_BASE + RTC_CIIR) = ulTmpReg; + } + + // Configure Alarm Interrupt. + if(ulCfg & 0xFFFF0000) + { + ulTmpReg = xHWREG(RTC_BASE + RTC_AMR); + ulTmpReg &= ~((ulCfg >> 24) & 0xFF); + ulTmpReg |= ((ulCfg >> 16) & 0xFF); + xHWREG(RTC_BASE + RTC_AMR) = ulTmpReg; + } +} + +//***************************************************************************** +// +//! \brief Enable the time tick or alarm interrupt of RTC. +//! This function is to enable the time tick or alarm interrupt of RTC. +//! +//! \param [in] ulIntType is the bit mask of the interrupt sources to be enabled. +//! This value can be the logical OR of the following value: +//! - \ref xRTC_INT_SECOND Tick interrupt +//! - \ref xRTC_INT_ALARM Alarm interrupt +//! +//! \return None. +// +//***************************************************************************** +void xRTCIntEnable(unsigned long ulIntType) +{ + // Check parameters valid. + xASSERT(( ulIntType == xRTC_INT_SECOND ) || + ( ulIntType == xRTC_INT_ALARM ) || + ( ulIntType == (xRTC_INT_SECOND | xRTC_INT_ALARM) )); + + // Enable RTC second interrupt. + if(ulIntType & xRTC_INT_SECOND) + { + RTCIntCfg((INT_SEC_EN | INT_MIN_DIS | INT_HOUR_DIS | INT_DOM_DIS | + INT_DOW_DIS | INT_DOY_DIS | INT_MON_DIS | INT_YEAR_DIS )); + } + + // Enable RTC alarm interrupt. + if(ulIntType & xRTC_INT_ALARM) + { + RTCIntCfg((INT_ALARM_SEC_EN | INT_ALARM_MIN_EN | + INT_ALARM_HOUR_EN | INT_ALARM_DOM_EN | + INT_ALARM_DOW_EN | INT_ALARM_DOY_EN | + INT_ALARM_MON_EN | INT_ALARM_YEAR_EN )); + } +} + +//***************************************************************************** +// +//! \brief Disable the time tick or alarm interrupt of RTC. +//! This function is to disable the time tick or alarm interrupt of RTC. +//! +//! \param [in] ulIntType is the bit mask of the interrupt sources to be enabled. +//! This value can be the logical OR of the following value: +//! - \ref xRTC_INT_SECOND Tick interrupt +//! - \ref xRTC_INT_ALARM Alarm interrupt +//! +//! \return None. +// +//***************************************************************************** +void xRTCIntDisable(unsigned long ulIntType) +{ + // Check parameters valid. + xASSERT(( ulIntType == xRTC_INT_SECOND ) || + ( ulIntType == xRTC_INT_ALARM ) || + ( ulIntType == (xRTC_INT_SECOND | xRTC_INT_ALARM) )); + + // Disable RTC second interrupt. + if(ulIntType & xRTC_INT_SECOND) + { + RTCIntCfg((INT_SEC_DIS | INT_MIN_DIS | INT_HOUR_DIS | INT_DOM_DIS | + INT_DOW_DIS | INT_DOY_DIS | INT_MON_DIS | INT_YEAR_DIS )); + } + + // Disable RTC alarm interrupt. + if(ulIntType & xRTC_INT_ALARM) + { + RTCIntCfg((INT_ALARM_SEC_DIS | INT_ALARM_MIN_DIS | + INT_ALARM_HOUR_DIS | INT_ALARM_DOM_DIS | + INT_ALARM_DOW_DIS | INT_ALARM_DOY_DIS | + INT_ALARM_MON_DIS | INT_ALARM_YEAR_DIS )); + } +} + +//***************************************************************************** +// +//! \brief Read current date/time or alarm date/time from RTC setting. +//! This function is to Read current date/time or alarm date/time from RTC +//! setting. +//! +//! \param [out] xtTime specifies the point of time and data. +//! \param [in] ulTimeAlarm specifies which will be read current time or alarm time. +//! This parameter is the one of any of the following: +//! - \ref xRTC_TIME_CURRENT Get Current time. +//! - \ref xRTC_TIME_ALARM Get System Alarm. +//! +//! \return None. +//! \todo Finish this function. +// +//***************************************************************************** +void xRTCTimeRead(xtTime * pxtTime, unsigned long ulTimeAlarm) +{ + // Check parameters valid. + xASSERT(pxtTime != 0); + xASSERT((ulTimeAlarm == xRTC_TIME_CURRENT) || (ulTimeAlarm == xRTC_TIME_ALARM)); + + switch(ulTimeAlarm) + { + case xRTC_TIME_CURRENT: + { + pxtTime->ulSecond = xHWREG(RTC_BASE + RTC_SEC) & SEC_MASK;; + pxtTime->ulMinute = xHWREG(RTC_BASE + RTC_MIN) & MIN_MASK; + pxtTime->ulHour = xHWREG(RTC_BASE + RTC_HOUR) & HOUR_MASK; + pxtTime->ulWDay = xHWREG(RTC_BASE + RTC_DOW) & DOW_MASK; + pxtTime->ulMDay = xHWREG(RTC_BASE + RTC_DOM) & DOM_MASK; + //pxtTime->ulYear = xHWREG(RTC_BASE + RTC_DOY) & DOY_MASK; + pxtTime->ulMonth = xHWREG(RTC_BASE + RTC_MONTH) & MONTH_MASK; + pxtTime->ulYear = xHWREG(RTC_BASE + RTC_YEAR) & YEAR_MASK; + break; + } + + case xRTC_TIME_ALARM: + { + pxtTime->ulSecond = xHWREG(RTC_BASE + RTC_ALSEC) & SEC_MASK;; + pxtTime->ulMinute = xHWREG(RTC_BASE + RTC_ALMIN) & MIN_MASK; + pxtTime->ulHour = xHWREG(RTC_BASE + RTC_ALHOUR) & HOUR_MASK; + pxtTime->ulWDay = xHWREG(RTC_BASE + RTC_ALDOW) & DOW_MASK; + pxtTime->ulMDay = xHWREG(RTC_BASE + RTC_ALDOM) & DOM_MASK; + //pxtTime->ulYear = xHWREG(RTC_BASE + RTC_ALDOY) & DOY_MASK; + pxtTime->ulMonth = xHWREG(RTC_BASE + RTC_ALMONTH) & MONTH_MASK; + pxtTime->ulYear = xHWREG(RTC_BASE + RTC_ALYEAR) & YEAR_MASK; + break; + } + default: // Error + { + while(1); + } + } +} + +//***************************************************************************** +// +//! \brief Write current date/time or alarm date/time to RTC Module. +//! This function is to configure current date/time or alarm date/time. +//! +//! \param [out] xtTime specifies the point of time and data. +//! \param [in] ulTimeAlarm specifies which will be read current time or alarm time. +//! This parameter is the one of any of the following: +//! - \ref xRTC_TIME_CURRENT Get Current time. +//! - \ref xRTC_TIME_ALARM Get System Alarm. +//! +//! \return None. +//! \todo Finish this function. +// +//***************************************************************************** +void xRTCTimeWrite(xtTime * pxtTime, unsigned long ulTimeAlarm) +{ + // Check parameters valid. + xASSERT(pxtTime != 0); + xASSERT((ulTimeAlarm == xRTC_TIME_CURRENT) || (ulTimeAlarm == xRTC_TIME_ALARM)); + + if(pxtTime->ulSecond > 59) pxtTime->ulSecond = 59; + if(pxtTime->ulMinute > 59) pxtTime->ulMinute = 59; + if(pxtTime->ulHour > 23) pxtTime->ulHour = 23; + if(pxtTime->ulWDay > 6) pxtTime->ulWDay = 6; + if(pxtTime->ulMDay > 31) pxtTime->ulMDay = 31; + //if(pxtTime->ulYear > 59) pxtTime->ulYear = 59; + if(pxtTime->ulMonth > 12) pxtTime->ulMonth = 12; + + switch(ulTimeAlarm) + { + case xRTC_TIME_CURRENT: + { + xHWREG(RTC_BASE + RTC_SEC) = pxtTime->ulSecond; + xHWREG(RTC_BASE + RTC_MIN) = pxtTime->ulMinute; + xHWREG(RTC_BASE + RTC_HOUR) = pxtTime->ulHour; + xHWREG(RTC_BASE + RTC_DOW) = pxtTime->ulWDay; + xHWREG(RTC_BASE + RTC_DOM) = pxtTime->ulMDay; + //xHWREG(RTC_BASE + RTC_DOY) = pxtTime->ulYear; + xHWREG(RTC_BASE + RTC_MONTH) = pxtTime->ulMonth; + xHWREG(RTC_BASE + RTC_YEAR) = pxtTime->ulYear; + break; + } + + case xRTC_TIME_ALARM: + { + xHWREG(RTC_BASE + RTC_ALSEC) = pxtTime->ulSecond; + xHWREG(RTC_BASE + RTC_ALMIN) = pxtTime->ulMinute; + xHWREG(RTC_BASE + RTC_ALHOUR) = pxtTime->ulHour; + xHWREG(RTC_BASE + RTC_ALDOW) = pxtTime->ulWDay; + xHWREG(RTC_BASE + RTC_ALDOM) = pxtTime->ulMDay; + //xHWREG(RTC_BASE + RTC_ALDOY) = pxtTime->ulYear; + xHWREG(RTC_BASE + RTC_ALMONTH) = pxtTime->ulMonth; + xHWREG(RTC_BASE + RTC_ALYEAR) = pxtTime->ulYear; + break; + } + default: // Error + { + while(1); + } + } +} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/rtc.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/rtc.h new file mode 100644 index 00000000..0fb5301d --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/rtc.h @@ -0,0 +1,296 @@ +//***************************************************************************** +// +//! \file rtc.h +//! \brief Prototypes for the RTC Driver. +//! \version V2.2.1.0 +//! \date 11/15/2013 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __LPC17XX_RTC_H__ +#define __LPC17XX_RTC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup RTC +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup RTC_INT_Type RTC Interrupt Type +//! \brief Values that show RTC Interrupt Type +//! Values that can be passed to RTCIntEnable(),RTCIntDisable() and +//! RTCIntClear(). +//! @{ +// +//***************************************************************************** + +// +//! Time Tick Interrupt +// +#define RTC_INT_SECOND 0x00000001 + +// +//! Alarm Interrupt +// +#define RTC_INT_ALARM 0x00000002 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup RTC_Time_Type RTC Time Type +//! \brief Values that show RTC Time Type +//! Values that can be passed to RTCTimeRead() and RTCTimeWrite(). +//! @{ +// +//***************************************************************************** + +// +//! Read or write current time and date +// +#define RTC_TIME_CURRENT 0x00000001 + +// +//! Read or write alarm time and date +// +#define RTC_TIME_ALARM 0x00000002 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup RTC_Time_Format RTC Time Format +//! \brief Values that show RTC Time Format +//! Values that can be passed to RTCTimeRead() and RTCTimeWrite(). +//! @{ +// +//***************************************************************************** + +// +//! 24-hour time scale +// +#define RTC_TIME_24H 0x00000001 + +// +//! 12-hour time scale am +// +#define RTC_TIME_12H_AM 0x00000000 + +// +//! 12-hour time scale pm +// +#define RTC_TIME_12H_PM 0x00000010 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_RTC_INT_CFG RTC interrupt configure mode. +//! \brief Values that show RTC Interrupt Status +//! Values that can be passed to RTCIntCfg() . +//! @{ +// +//***************************************************************************** + +//! Enable second increment interrupt. +#define INT_SEC_EN BIT_32_0 + +//! Enable minute increment interrupt. +#define INT_MIN_EN BIT_32_1 + +//! Enable hour increment interrupt. +#define INT_HOUR_EN BIT_32_2 + +//! Enable day of month increment interrupt. +#define INT_DOM_EN BIT_32_3 + +//! Enable day of week increment interrupt. +#define INT_DOW_EN BIT_32_4 + +//! Enable day of year increment interrupt. +#define INT_DOY_EN BIT_32_5 + +//! Enable month increment interrupt. +#define INT_MON_EN BIT_32_6 + +//! Enable year increment interrupt. +#define INT_YEAR_EN BIT_32_7 + +//! Disable second increment interrupt. +#define INT_SEC_DIS BIT_32_8 + +//! Disable minute increment interrupt. +#define INT_MIN_DIS BIT_32_9 + +//! Disable hour increment interrupt. +#define INT_HOUR_DIS BIT_32_10 + +//! Disable day of month increment interrupt. +#define INT_DOM_DIS BIT_32_11 + +//! Disable day of week increment interrupt. +#define INT_DOW_DIS BIT_32_12 + +//! Disable day of year increment interrupt. +#define INT_DOY_DIS BIT_32_13 + +//! Disable month increment interrupt. +#define INT_MON_DIS BIT_32_14 + +//! Disable year increment interrupt. +#define INT_YEAR_DIS BIT_32_15 + + +//! Enable second alarm match interrupt. +#define INT_ALARM_SEC_EN BIT_32_24 + +//! Enable minute alarm match interrupt. +#define INT_ALARM_MIN_EN BIT_32_25 + +//! Enable hour alarm match interrupt. +#define INT_ALARM_HOUR_EN BIT_32_26 + +//! Enable day of month alarm match interrupt. +#define INT_ALARM_DOM_EN BIT_32_27 + +//! Enable day of week alarm match interrupt. +#define INT_ALARM_DOW_EN BIT_32_28 + +//! Enable day of year alarm match interrupt. +#define INT_ALARM_DOY_EN BIT_32_29 + +//! Enable month alarm match interrupt. +#define INT_ALARM_MON_EN BIT_32_30 + +//! Enable year alarm match interrupt. +#define INT_ALARM_YEAR_EN BIT_32_31 + + +//! Disable second alarm match interrupt. +#define INT_ALARM_SEC_DIS BIT_32_16 + +//! Disable minute alarm match interrupt. +#define INT_ALARM_MIN_DIS BIT_32_17 + +//! Disable hour alarm match interrupt. +#define INT_ALARM_HOUR_DIS BIT_32_18 + +//! Disable day of month alarm match interrupt. +#define INT_ALARM_DOM_DIS BIT_32_19 + +//! Disable day of week alarm match interrupt. +#define INT_ALARM_DOW_DIS BIT_32_20 + +//! Disable day of year alarm match interrupt. +#define INT_ALARM_DOY_DIS BIT_32_21 + +//! Disable month alarm match interrupt. +#define INT_ALARM_MON_DIS BIT_32_22 + +//! Disable year alarm match interrupt. +#define INT_ALARM_YEAR_DIS BIT_32_23 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __LPC17XX_RTC_H__ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/spi.c b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/spi.c new file mode 100644 index 00000000..3e944c85 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/spi.c @@ -0,0 +1,1098 @@ +//***************************************************************************** +// +//! \file spi.c +//! \brief Driver for the SPI controller +//! \version V3.0.0.0 +//! \date 8/15/2014 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2014, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#include "CoX.h" +#include "hw_sysctl.h" +#include "hw_spi.h" +#include "spi.h" + +//***************************************************************************** +// +// An array is Watchdog callback function point +// +//***************************************************************************** +static xtEventCallback g_pfnSPIHandlerCallbacks[3] = {0}; + +//***************************************************************************** +// +//! \brief SSP0 interrupt handler. +//! This function is the SSP0 interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void SSP0IntHandler(void) +{ + if(g_pfnSPIHandlerCallbacks[0] != 0) + { + g_pfnSPIHandlerCallbacks[0](0, 0, 0, 0); + } +} + +//***************************************************************************** +// +//! \brief SSP1 interrupt handler. +//! This function is the SSP1 interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void SSP1IntHandler(void) +{ + if(g_pfnSPIHandlerCallbacks[1] != 0) + { + g_pfnSPIHandlerCallbacks[1](0, 0, 0, 0); + } +} + +#if defined(LPC_177x) || defined (LPC_178x) +//***************************************************************************** +// +//! \brief SSP2 interrupt handler. +//! This function is the SSP2 interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void SSP2IntHandler(void) +{ + if(g_pfnSPIHandlerCallbacks[2] != 0) + { + g_pfnSPIHandlerCallbacks[2](0, 0, 0, 0); + } +} + +#elif defined(LPC_175x) || defined (LPC_176x) +//***************************************************************************** +// +//! \brief SPI interrupt handler. +//! This function is the SPI interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void SPIIntHandler(void) +{ + if(g_pfnSPIHandlerCallbacks[2] != 0) + { + g_pfnSPIHandlerCallbacks[2](0, 0, 0, 0); + } +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a SPI base address. +//! +//! \param ulBase is the base address of the SPI port. +//! +//! This function determines if a SPI port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef xDEBUG +static xtBoolean +SPIBaseValid(unsigned long ulBase) +{ + return((ulBase == xSPI0_BASE) || + (ulBase == xSPI1_BASE) || + (ulBase == xSPI2_BASE)); +} +#endif + +//***************************************************************************** +// +//! \brief Register user interrupts callback function for the SPI. +//! +//! \param [in] xtPortCallback is user callback for the SPI. +//! +//! \return None. +// +//***************************************************************************** +void xSPIIntCallbackInit(unsigned long ulBase, xtEventCallback pfnCallback) +{ + // + // Check the arguments. + // + xASSERT(UARTBaseValid(ulBase)); + xASSERT(pfnCallback != 0); + + switch (ulBase) + { + case xSPI0_BASE: g_pfnSPIHandlerCallbacks[0] = pfnCallback; break; + case xSPI1_BASE: g_pfnSPIHandlerCallbacks[1] = pfnCallback; break; + case xSPI2_BASE: g_pfnSPIHandlerCallbacks[2] = pfnCallback; break; + default: break; + } +} + +//***************************************************************************** +// +//! \brief SPI single write and read data. +//! +//! \param [in] ulBase specifies the SPI module base address. +//! \param [in] ulVal is the data ready to send via spi bus. +//! +//! \return The receive data from spi slave. +// +//***************************************************************************** +unsigned long xSPISingleDataReadWrite(unsigned long ulBase, unsigned long ulVal) +{ +#if (defined (LPC_175x) || defined (LPC_176x)) + // SPI (only for LPC175x_6x) + if(ulBase == xSPI2_BASE){ + while(0 == (xHWREG(ulBase + SPI_SR) & SPI_SR_SPIF)); + xHWREG(ulBase + SPI_DR) = ulVal & SPI_DR_DATA_M; + return xHWREG(ulBase + SPI_DR); + } + else +#endif + // SSPn(LPC175x_6x: n = 0, 1; LPC177x_8x: n = 0, 1, 2) + { + while(0 == (xHWREG(ulBase + SSP_SR) & SSP_SR_TFE)); + xHWREG(ulBase + SSP_DR) = ulVal & SSP_DR_DATA_M; + return xHWREG(ulBase + SSP_DR); + } +} + +//***************************************************************************** +// +//! \brief Configure SPI Module. +//! +//! \param [in] ulBase specifies the SPI module base address. which can be one +//! of the following value: +//! - \ref SPI0_BASE +//! +//! \param [in] ulClk is SPI bus clock frequency. +//! +//! \param [in] ulConfig is SPI configure parameters. +//! which can be OR of the following value: +//! - \ref SPI_DATA_LEN_4 +//! - \ref SPI_DATA_LEN_5 +//! - \ref SPI_DATA_LEN_6 +//! - \ref SPI_DATA_LEN_7 +//! - \ref SPI_DATA_LEN_8 +//! - \ref SPI_DATA_LEN_9 +//! - \ref SPI_DATA_LEN_10 +//! - \ref SPI_DATA_LEN_11 +//! - \ref SPI_DATA_LEN_12 +//! - \ref SPI_DATA_LEN_13 +//! - \ref SPI_DATA_LEN_14 +//! - \ref SPI_DATA_LEN_15 +//! - \ref SPI_DATA_LEN_16 +//! - \ref SPI_MODE_MASTER +//! - \ref SPI_MODE_SLAVE +//! - \ref SPI_FORMAT_MODE_0 +//! - \ref SPI_FORMAT_MODE_1 +//! - \ref SPI_FORMAT_MODE_2 +//! - \ref SPI_FORMAT_MODE_3 +//! - \ref SPI_TI_FORMAT_MODE +//! - \ref SPI_NMW_FORMAT_MODE +//! - \ref SPI_LSB_FIRST +//! - \ref SPI_MSB_FIRST +//! +//! \return None. +// +//***************************************************************************** +void xSPIConfigSet(unsigned long ulBase, unsigned long ulClk, unsigned long ulConfig) +{ + unsigned long ulActClk = 0; + + // Check the parameters. + xASSERT(SPIBaseValid(ulBase)); + xASSERT((ulConfig & ~( SPI_DATA_LEN_4 | + SPI_DATA_LEN_5 | + SPI_DATA_LEN_6 | + SPI_DATA_LEN_7 | + SPI_DATA_LEN_8 | + SPI_DATA_LEN_9 | + SPI_DATA_LEN_10 | + SPI_DATA_LEN_11 | + SPI_DATA_LEN_12 | + SPI_DATA_LEN_13 | + SPI_DATA_LEN_14 | + SPI_DATA_LEN_15 | + SPI_DATA_LEN_16 | + SPI_MODE_MASTER | + SPI_MODE_SLAVE | + SPI_FORMAT_MODE_0 | + SPI_FORMAT_MODE_1 | + SPI_FORMAT_MODE_2 | + SPI_FORMAT_MODE_3 | + SPI_TI_FORMAT_MODE | + SPI_NMW_FORMAT_MODE | + SPI_LSB_FIRST | + SPI_MSB_FIRST + ) + ) == 0); + + /********************* Configure SPI Clock frequency ***********************/ + //ulActClk = SysCtlPeripheralClockGet(PCLKSEL_SPI); + ulActClk /= ulClk; + + // ulActClk/ulClk must be an even number greater than or equal to 8. + // Violations of this can result in unpredictable behavior. + if( ((ulActClk/ulClk) < 8) || ((ulActClk/ulClk)%2 != 0)) + { + while(1); //Error + } +#if (defined (LPC_175x) || defined (LPC_176x)) + xHWREG(ulBase + S0SPCCR) = ulActClk/ulClk; +#elif (defined (LPC_177x) || defined (LPC_178x)) + xHWREG(ulBase + SSP_CPSR) = ulActClk/ulClk; +#endif + + /********************* Configure SPI Mode, PHA, POL, DataLen ***************/ +#if (defined (LPC_175x) || defined (LPC_176x)) + // SPI (only for LPC175x_6x) + if(ulBase == xSPI2_BASE){ + unsigned long ulTmpReg = xHWREG(ulBase + SPI_CR); + ulTmpReg &= ((~ulConfig) >> 16); + ulTmpReg |= (ulConfig & 0xFFFF); + xHWREG(ulBase + SPI_CR) = ulTmpReg; + } + else +#endif + // SSPn(LPC175x_6x: n = 0, 1; LPC177x_8x: n = 0, 1, 2) + { + xHWREG(ulBase + SSP_CR1) = 0x00; + xHWREG(ulBase + SSP_CR0) |= ulConfig & 0xFF; + xHWREG(ulBase + SSP_CR0) |= ((ulConfig >> 8) & 0xFF); + xHWREG(ulBase + SSP_CR1) &= ~SSP_CR1_MS; + xHWREG(ulBase + SSP_CR1) |= (((ulConfig >> 16) & 0x1) << 2); + } +} + +//***************************************************************************** +// +//! \brief Enable SPI interrupt. +//! +//! \param [in] ulBase specifies the SPI module base address. which can be one +//! of the following value: +//! - \ref SPI0_BASE +//! \param [in] ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! \return None. +// +//***************************************************************************** +void xSPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + xASSERT((ulFlags == SPI_INT_EOT) || + (ulFlags == SPI_INT_RX) || + (ulFlags == SPI_INT_TX) || + (ulFlags == SPI_INT_ERROR)); + + // Clear interrupt flag. +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == xSPI2_BASE) + { + xHWREG(ulBase + SPI_CR) |= SPI_CR_SPIE; + } +#endif + xHWREG(ulBase + SSP_IMSC) |= ulIntFlags; +} + +//***************************************************************************** +// +//! \brief Disable SPI interrupt. +//! +//! \param [in] ulBase specifies the SPI module base address. which can be one +//! of the following value: +//! - \ref SPI0_BASE +//! \param [in] ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! \return None. +// +//***************************************************************************** +void xSPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + xASSERT((ulFlags == SPI_INT_EOT) || + (ulFlags == SPI_INT_RX) || + (ulFlags == SPI_INT_TX) || + (ulFlags == SPI_INT_ERROR)); + + // Clear interrupt flag. +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == xSPI2_BASE) + { + xHWREG(ulBase + SPI_CR) &= ~SPI_CR_SPIE; + } +#endif + xHWREG(ulBase + SSP_IMSC) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! \brief Get SPI Interrupt flag. +//! +//! \param [in] ulBase specifies the SPI module base address. +//! \param [in] xbMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! \return The interrupt status of SPI. +// +//***************************************************************************** +unsigned long xSPIStatusGet(unsigned long ulBase, xtBoolean xbMasked) +{ + unsigned long ulRegTmp; + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + xASSERT((ulFlags == SPI_INT_EOT) || + (ulFlags == SPI_INT_RX) || + (ulFlags == SPI_INT_TX) || + (ulFlags == SPI_INT_ERROR)); + + // Clear interrupt flag. +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == xSPI2_BASE) + { + return xHWREG(ulBase + SPI_INT); + } +#endif + if(xbMasked){ + ulRegTmp = xHWREG(ulBase + SSP_MIS); + } else { + ulRegTmp = xHWREG(ulBase + SSP_RIS); + } + return ulRegTmp; +} + +//***************************************************************************** +// +//! \brief Check interrupt status flag. +//! This function is used to check whether special flag is set or not. +//! +//! \param [in] ulBase specifies the SPI module base address. +//! \param [in] ulFlags is the flag you want to check +//! +//! \return The status of special flag. +//! - xtrue The check flag has been set. +//! - xflase The check flag has not been set. +// +//***************************************************************************** +xtBoolean SPIIntFlagCheck(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + xASSERT((ulFlags == SPI_INT_EOT) || + (ulFlags == SPI_INT_RX) || + (ulFlags == SPI_INT_TX) || + (ulFlags == SPI_INT_ERROR)); + + // Clear interrupt flag. +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == xSPI2_BASE) + { + return (xHWREG(ulBase + SPI_INT) & SPI_INT_SPIF) ? xtrue : xfalse; + } +#endif + return (xHWREG(ulBase + SSP_RIS) & ulFlags) ? xtrue : xfalse; +} + +//***************************************************************************** +// +//! \brief Clear SPI interrupt status flag. +//! This function can be used to clear special SPI interrupt status flag. +//! +//! \param [in] ulBase specifies the SPI module base address. which can be one +//! of the following value: +//! - \ref xSPI0_BASE +//! - \ref xSPI1_BASE +//! - \ref xSPI2_BASE +//! +//! \param [in] ulFlags is SPI interrupt status flag. +//! This parameter can be OR of the following value: +//! - \ref SPI_INT_SPIF +//! +//! \return None. +// +//***************************************************************************** +void SPIIntFlagClear(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + xASSERT((ulFlags == SPI_INT_EOT) || + (ulFlags == SPI_INT_RX) || + (ulFlags == SPI_INT_TX) || + (ulFlags == SPI_INT_ERROR)); + + // Clear interrupt flag. +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == xSPI2_BASE) + { + xHWREG(ulBase + SPI_INT) |= SPI_INT_SPIF; + } +#endif + xHWREG(ulBase + SPI_INT) |= ulFlags; +} + +//***************************************************************************** +// +//! \brief Gets the number of bits transferred per frame. +//! This function gets the number of bits transferred per frame. +//! +//! \param [in] ulBase specifies the SPI module base address. This value can +//! be one of the following value: +//! - \ref xSPI0_BASE +//! - \ref xSPI1_BASE +//! - \ref xSPI2_BASE +//! +//! \return The number of bits transferred per frame. +//! For LPC175x/6x, this value can be 8/9/../16. +//! For LPC177x/8x, this value can be 4/5/../16. +// +//***************************************************************************** +unsigned char xSPIBitLengthGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == xSPI2_BASE) + { + return ((xHWREG(ulBase + SPI_CR) & SPI_CR_BITS_M) >> SPI_CR_BITS_S); + } +#endif + return (xHWREG(ulBase + SSP_CR0) & SSP_CR0_DSS_M); +} + +//***************************************************************************** +// +//! \brief Gets a data element from the SPI interface. +//! This function gets received data from the interface of the specified +//! SPI module and places that data into the location specified by the +//! pulData parameter. +//! +//! \param [in] ulBase specifies the SPI module base address. This value can +//! be one of the following value: +//! - \ref xSPI0_BASE +//! - \ref xSPI1_BASE +//! - \ref xSPI2_BASE +//! +//! \param [out] pulData is a pointer to a storage location for data that was +//! received over the SPI interface. +//! \param [in] ulLen specifies the length of data will be read. +//! +//! \return None. +//! +//! \note Only the lower N bits of the value written to pulData contain +//! valid data, where N is the data width as configured by xSPIConfigSet(). +//! For example, if the interface is configured for 8-bit data width, +//! only the lower 8 bits of the value written to pulData contain valid +//! data. +// +//***************************************************************************** +void xSPIDataRead(unsigned long ulBase, void *pulRData, unsigned long ulLen) +{ + unsigned long i = 0; + unsigned char ucBitLength = xSPIBitLengthGet(ulBase); + + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + xASSERT(pulData != 0); + + for(i = 0; i < ulLen; i++) + { + if (ucBitLength <= 8) + { + ((unsigned char*)pulRData)[i] = xSPISingleDataReadWrite(ulBase, 0xFF); + } + else if (ucBitLength >= 8 && ucBitLength <= 16) + { + ((unsigned short*)pulRData)[i] = xSPISingleDataReadWrite(ulBase, 0xFFFF); + } + else + { + ((unsigned long*)pulRData)[i] = xSPISingleDataReadWrite(ulBase, 0xFFFFFF); + } + } +} + +//***************************************************************************** +// +//! \brief Write datas element to the SPI interface. +//! This function transmitted data to the interface of the specified +//! SPI module . +//! +//! \param [in] ulBase specifies the SPI module base address. +//! \param [in] pulWData is a pointer to a storage location for data that was +//! transmitted over the SPI interface. +//! \param [in] ulLen specifies the length of data will be write. +//! +//! \return None. +//! +//! \note Only the lower N bits of the value written to pulData contain +//! valid data, where N is the data width as configured by xSPIConfigSet(). +//! For example, if the interface is configured for 8-bit data width, +//! only the lower 8 bits of the value written to pulData contain valid +//! data. +// +//***************************************************************************** +void xSPIDataWrite(unsigned long ulBase, void *pulWData, unsigned long ulLen) +{ + unsigned long i = 0; + unsigned char ucBitLength = xSPIBitLengthGet(ulBase); + + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + xASSERT(pulData != 0); + + for(i = 0; i < ulLen; i++) + { + if (ucBitLength <= 8) + { + xSPISingleDataReadWrite(ulBase, ((unsigned char*)pulWData)[i]); + } + else if (ucBitLength >= 8 && ucBitLength <= 16) + { + xSPISingleDataReadWrite(ulBase, ((unsigned short*)pulWData)[i]); + } + else + { + xSPISingleDataReadWrite(ulBase, ((unsigned long*)pulWData)[i]); + } + } +} + +//***************************************************************************** +// +//! \brief Write data element to the SPI interface with block. +//! This function transmitted data to the interface of the specified SPI +//! module with block. when the TX and TX shift are both empty or in FIFO +//! mode the TX FIFO depth is equal to or less than the trigger level, +//! the data element can be transmitted, otherwise the data element will +//! be blocked until can be transmitted. +//! +//! \param [in] ulBase specifies the SPI module base address. This value can +//! be one of the following value: +//! - \ref xSPI0_BASE +//! - \ref xSPI1_BASE +//! - \ref xSPI2_BASE +//! +//! \param [in] ulData is data that was transmitted over the SPI interface. +//! +//! \return None. +//! +//! \note Only the lower N bits of the value written to pulData contain +//! valid data, where N is the data width as configured by xSPIConfigSet(). +//! For example, if the interface is configured for 8-bit data width, +//! only the lower 8 bits of the value written to pulData contain valid +//! data. +// +//***************************************************************************** +void xSPIDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == xSPI2_BASE) + { + // Wait last transmit done then write data to SPI data register. + while(0 == (xHWREG(ulBase + SPI_SR) & SPI_SR_SPIF)); + xHWREG(ulBase + SPI_DR) = ulData & SPI_DR_DATA_M; + } +#endif + // Wait last transmit done then write data to SSPn data register. + while(0 != (xHWREG(ulBase + SSP_SR) & SSP_SR_TFE)); + xHWREG(ulBase + SSP_DR) = ulData & SSP_DR_DATA_M; +} + +//***************************************************************************** +// +//! \brief Write data element to the SPI interface with Noblock. +//! This function transmitted data to the interface of the specified +//! SPI module with Noblock. +//! +//! \param [in] ulBase specifies the SPI module base address. This value can +//! be one of the following value: +//! - \ref xSPI0_BASE +//! - \ref xSPI1_BASE +//! - \ref xSPI2_BASE +//! +//! \param [in] ulData is data that was transmitted over the SPI interface. +//! +//! \return The number of data that has been transfered.. +//! +//! \note Only the lower N bits of the value written to pulData contain +//! valid data, where N is the data width as configured by xSPIConfigSet(). +//! For example, if the interface is configured for 8-bit data width, +//! only the lower 8 bits of the value written to pulData contain valid +//! data. +//! +// +//***************************************************************************** +long xSPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == xSPI2_BASE) + { + // Write Data to SPI Data register. + xHWREG(ulBase + SPI_DR) = ulData & SPI_DR_DATA_M; + } +#endif + // Write Data to SSPn Data register. + xHWREG(ulBase + SSP_DR) = ulData & SSP_DR_DATA_M; + + return 1; +} + +//***************************************************************************** +// +//! \brief Gets a data element from the SPI interface with block. +//! This function gets received data from the interface of the specified +//! SPI module with block. when the RX not empty flag is set, the data +//! element can be transmitted, otherwise the data element will be +//! blocked until can be transmitted. +//! +//! \param [in] ulBase specifies the SPI module base address. This value can +//! be one of the following value: +//! - \ref xSPI0_BASE +//! - \ref xSPI1_BASE +//! - \ref xSPI2_BASE +//! +//! \param [out] pulData is a pointer to a storage location for data that was +//! received over the SPI interface. +//! +//! \note Only the lower N bits of the value written to pulData contain +//! valid data, where N is the data width as configured by xSPIConfigSet(). +//! For example, if the interface is configured for 8-bit data width, +//! only the lower 8 bits of the value written to pulData contain valid +//! data. +//! +//! \return None. +// +//***************************************************************************** +void xSPIDataGet(unsigned long ulBase, unsigned long * pulData) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + xASSERT(pulData != 0); + +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == SPI2_BASE) + { + while(0 == (xHWREG(ulBase + SPI_SR) & SPI_SR_SPIF)); + *pulData = xHWREG(ulBase + SPI_DR) & SPI_DR_DATA_M; + } +#endif + // Wait until receive one byte, then read data from SPI Data register. + while(0 != (xHWREG(ulBase + SSP_SR) & SSP_SR_RNE)); + *pulData = xHWREG(ulBase + SSP_DR) & SSP_DR_DATA_M; +} + +//***************************************************************************** +// +//! \brief Gets a data element from the SPI interface with Noblock. +//! This function gets received data from the interface of the specified +//! SPI module with Noblock. +//! +//! \param [in] ulBase specifies the SPI module base address. This value can +//! be one of the following value: +//! - \ref xSPI0_BASE +//! - \ref xSPI1_BASE +//! - \ref xSPI2_BASE +//! +//! \param [out] pulData is a pointer to a storage location for data that was +//! received over the SPI interface. +//! +//! \note Only the lower N bits of the value written to pulData contain +//! valid data, where N is the data width as configured by xSPIConfigSet(). +//! For example, if the interface is configured for 8-bit data width, +//! only the lower 8 bits of the value written to pulData contain valid +//! data. +//! +//! \return None. +// +//***************************************************************************** +long xSPIDataGetNonBlocking(unsigned long ulBase, unsigned long * pulData) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + xASSERT(pulData != 0); + +#if defined(LPC_175x) || defined (LPC_176x) + if(ulBase == xSPI2_BASE) + { + *pulData = xHWREG(ulBase + SPI_DR) & SPI_DR_DATA_M; + } +#endif + // Read data from SPI Data register. + *pulData = xHWREG(ulBase + SSP_DR) & SSP_DR_DATA_M; + + return 1; +} + +//***************************************************************************** +// +//! \brief Check the busy status of the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! +//! This function Check the busy status of the specified SPI module. +//! +//! \return Returns the busy status of the specified SPI port. +//! \b xtrue The SPI port is in busy,or \b xfalse The SPI port is not in busy. +// +//***************************************************************************** +xtBoolean xSPIIsBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT(SPIBaseValid(ulBase)); + +#if defined(LPC_175x) || defined(LPC_176x) + if(ulBase == xSPI2_BASE) + { + return (xHWREG(ulBase + SPI_SR) & SPI_SR_SPIF); + } +#endif + return (xHWREG(ulBase + SSP_SR) & SSP_SR_BSY); +} + +//***************************************************************************** +// +//! \brief Check the status of the Rx buffer of the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! +//! This function Check the Rx buffer status of the specified SPI module. +//! +//! \return Returns the Rx buffer status of the specified SPI port. +//! \b xtrue The Rx buffer is empty,or \b xfalse The Rx buffer is not empty. +// +//***************************************************************************** +xtBoolean xSPIIsRxEmpty(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == xSPI0_BASE) || +#if defined(LPC_177x) || defined(LPC_178x) + (ulBase == xSPI2_BASE) || +#endif + (ulBase == xSPI1_BASE)); + + return (!(xHWREG(ulBase + SSP_SR) & SSP_SR_TFE)); +} + +//***************************************************************************** +// +//! \brief Check the status of the Tx buffer of the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! +//! This function Check the Tx buffer status of the specified SPI module. +//! +//! \return Returns the Tx buffer status of the specified SPI port. +//! \b xtrue The Tx buffer is in empty,or \b xfalse The Tx buffer is not empty. +// +//***************************************************************************** +xtBoolean xSPIIsTxEmpty(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == xSPI0_BASE) || +#if defined(LPC_177x) || defined(LPC_178x) + (ulBase == xSPI2_BASE) || +#endif + (ulBase == xSPI1_BASE)); + + return (xHWREG(ulBase + SSP_SR) & SSP_SR_TFE); +} + +//***************************************************************************** +// +//! \brief Check the status of the Rx buffer of the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! +//! This function Check the Rx buffer status of the specified SPI module. +//! +//! \return Returns the Rx buffer status of the specified SPI port. +//! \b xtrue The Rx buffer is full,or \b xfalse The Rx buffer is not full. +// +//***************************************************************************** +xtBoolean xSPIIsRxFull(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == xSPI0_BASE) || +#if defined(LPC_177x) || defined(LPC_178x) + (ulBase == xSPI2_BASE) || +#endif + (ulBase == xSPI1_BASE)); + + return (xHWREG(ulBase + SSP_SR) & SSP_SR_RFF); +} + +//***************************************************************************** +// +//! \brief Check the status of the Tx buffer of the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! +//! This function Check the Tx buffer status of the specified SPI module. +//! +//! \return Returns the Tx buffer status of the specified SPI port. +//! \b xtrue The Tx buffer is in full,or \b xfalse The Tx buffer is not full. +// +//***************************************************************************** +xtBoolean xSPIIsTxFull(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == xSPI0_BASE) || +#if defined(LPC_177x) || defined(LPC_178x) + (ulBase == xSPI2_BASE) || +#endif + (ulBase == xSPI1_BASE)); + + return (!(xHWREG(ulBase + SSP_SR) & SSP_SR_TNF)); +} + +//***************************************************************************** +// +//! \brief Enable the DMA of the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! \param ulDmaMode specifies the SPI module base address. +//! Details please refer to \ref xSPI_DMA. +//! +//! This function enable the DMA of the specified SPI port. +//! +//! The \e ulDmaMode parameter can be one of the following values: +//! \b xSPI_DMA_RX, \b xSPI_DMA_TX ,or \b xSPI_DMA_BOTH. +//! Details please refer to \ref xSPI_DMA_CoX. +//! +//! \return None. +// +//***************************************************************************** +void xSPIDMAEnable(unsigned long ulBase, unsigned long ulDmaMode) +{ + // + // Check the arguments. + // + xASSERT((ulBase == xSPI0_BASE) || +#if defined(LPC_177x) || defined(LPC_178x) + (ulBase == xSPI2_BASE) || +#endif + (ulBase == xSPI1_BASE)); + + if(ulDmaMode & SPI_DMA_RX) + { + xHWREG(ulBase + SSP_DMACR) |= SSP_DMACR_RXDMAE; + } + if(ulDmaMode & SPI_DMA_TX) + { + xHWREG(ulBase + SSP_DMACR) |= SSP_DMACR_TXDMAE; + } +} + +//***************************************************************************** +// +//! \brief Disable the DMA of the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! \param ulDmaMode specifies the SPI module base address. +//! Details please refer to \ref xSPI_DMA. +//! +//! This function disable the DMA of the specified SPI port. +//! +//! The \e ulDmaMode parameter can be one of the following values: +//! \b SPI_DMA_RX, \b SPI_DMA_TX ,or \b SPI_DMA_BOTH. +//! Details please refer to \ref xSPI_DMA_CoX. +//! +//! \return None. +// +//***************************************************************************** +void xSPIDMADisable(unsigned long ulBase, unsigned long ulDmaMode) +{ + // + // Check the arguments. + // + xASSERT((ulBase == xSPI0_BASE) || +#if defined(LPC_177x) || defined(LPC_178x) + (ulBase == xSPI2_BASE) || +#endif + (ulBase == xSPI1_BASE)); + + if(ulDmaMode & SPI_DMA_RX) + { + xHWREG(ulBase + SSP_DMACR) &= ~SSP_DMACR_RXDMAE; + } + if(ulDmaMode & SPI_DMA_TX) + { + xHWREG(ulBase + SSP_DMACR) &= ~SSP_DMACR_TXDMAE; + } +} + +//***************************************************************************** +// +//! \brief Enable the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! +//! This function enable the specified SPI port. +//! +//! \return None. +// +//***************************************************************************** +void xSPIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == xSPI0_BASE) || +#if defined(LPC_177x) || defined(LPC_178x) + (ulBase == xSPI2_BASE) || +#endif + (ulBase == xSPI1_BASE)); + + xHWREG(ulBase + SSP_CR1) |= SSP_CR1_SSE; +} + +//***************************************************************************** +// +//! \brief Disable the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! +//! This function disable the specified SPI port. +//! +//! \return None. +// +//***************************************************************************** +void xSPIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + xASSERT((ulBase == xSPI0_BASE) || +#if defined(LPC_177x) || defined(LPC_178x) + (ulBase == xSPI2_BASE) || +#endif + (ulBase == xSPI1_BASE)); + + xHWREG(ulBase + SSP_CR1) &= ~SSP_CR1_SSE; +} + +//***************************************************************************** +// +//! \brief Set the slave select pins of the specified SPI port. +//! +//! \param ulBase specifies the SPI module base address. +//! \param ulSSMode specifies the SS is hardware control or software control. +//! Details please reference to \ref xSPI_SlaveSelMode. +//! \param ulSlaveSel specifies the slave select pins which will be used. +//! Details please reference to \ref xSPI_SlaveSel. +//! +//! This function is to Set the slave select pins of the +//! specified SPI port. +//! +//! The \e ulSSMode can be one of the following values: +//! \b xSPI_SS_HARDWARE. +//! Details please reference to \ref xSPI_SlaveSelMode_CoX. +//! +//! The \e ulSlaveSel can be one of the following values: +//! \b xSPI_SS0, Details please reference to \ref xSPI_SlaveSel_CoX. +//! +//! \note this is only for master. +//! +//! \return None. +// +//***************************************************************************** +void xSPISSSet(unsigned long ulBase, unsigned long ulSSMode, unsigned long ulSlaveSel) +{ + +} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/spi.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/spi.h new file mode 100644 index 00000000..72994bf8 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/spi.h @@ -0,0 +1,294 @@ +//***************************************************************************** +// +//! \file spi.h +//! \brief Prototypes for the SPI Driver. +//! \version V3.0.0.0 +//! \date $CURRENTTIME$ +//! \author CooCox +//! \copyright +//! +//! Copyright (c) 2014, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSPIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef _LPC17XX_SPI_H_ +#define _LPC17XX_SPI_H_ + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup SPI +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SPI +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SPI_Ints SPI Interrupts +//! \brief Values show that LPC17xx SPI Interrupts +//! Values that can be passed to xSPIIntEnable, xSPIIntDisable +//! as the ulIntFlags parameter. +//! @{ +// +//***************************************************************************** + +// +//! All Interrupt Mask +// +#define SPI_INT_EOT 0x00000001 +#define SPI_INT_RX 0x00000004 +#define SPI_INT_TX 0x00000008 +#define SPI_INT_ERROR 0x00000002 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SPI_Config LPC17xx SPI Configure +//! \brief Values show that LPC17xx SPI Configure +//! Values that can be passed to xSPIConfigSet. +//! @{ +// +//***************************************************************************** + +// +//! polarity 0, +//! Tx changed at rising edge +//! Rx latched at rising edge +// +#define SPI_FORMAT_MODE_0 0x00000000 + +// +//! Moto Format, polarity 0, phase 0 M0 +//! Tx changed at falling edge +//! Rx latched at rising edge +// +#define SPI_FORMAT_MODE_1 0x00000800 + +// +//! Moto Format, polarity 0, phase 1 M1 +//! Tx changed at rising edge +//! Rx latched at falling edge +// +#define SPI_FORMAT_MODE_2 0x00000400 + +// +//! polarity 0 +//! Tx changed at falling edge +//! Rx latched at falling edge +// +#define SPI_FORMAT_MODE_3 0x00000C00 + +// +//! TI frame format +// +#define SPI_TI_FORMAT_MODE 0x00000100 + +// +//! National MicroWire frame format +// +#define SPI_NMW_FORMAT_MODE 0x00000200 + +// +//£¡ SPI master +// +#define SPI_MODE_MASTER 0x00000000 + +// +//! SPI slave +// +#define SPI_MODE_SLAVE 0x00010000 + +// +//! SPI MSB First +// +#define SPI_MSB_FIRST 0x00000000 + +// +//! SPI LSB First +// +#define SPI_LSB_FIRST 0x00100000 + +// +//! data width 4 bit +// +#define SPI_DATA_WIDTH4 0x00000003 + +// +//! data width 5 bit +// +#define SPI_DATA_WIDTH5 0x00000004 + +// +//! data width 6 bit +// +#define SPI_DATA_WIDTH6 0x00000005 + +// +//! data width 7 bit +// +#define SPI_DATA_WIDTH7 0x00000006 + +// +//! data width 8 bit +// +#define SPI_DATA_WIDTH8 0x00000007 + +// +//! data width 9 bit +// +#define SPI_DATA_WIDTH9 0x00000008 + +// +//! data width 10 bit +// +#define SPI_DATA_WIDTH10 0x00000009 + +// +//! data width 11 bit +// +#define SPI_DATA_WIDTH11 0x0000000A + +// +//! data width 12 bit +// +#define SPI_DATA_WIDTH12 0x0000000B + +// +//! data width 13 bit +// +#define SPI_DATA_WIDTH13 0x0000000C + +// +//! data width 14 bit +// +#define SPI_DATA_WIDTH14 0x0000000D + +// +//! data width 15 bit +// +#define SPI_DATA_WIDTH15 0x0000000E + +// +//! data width 16 bit +// +#define SPI_DATA_WIDTH16 0x0000000F + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SPI_SlaveSel_Config LPC17xx SPI Slave Select Configure +//! \brief Values that show LPC17xx SPI Slave Select Configure +//! Values that can be passed to SPIAutoSSEnable() SPISSSet() SPISSClear() +//! SPISSConfig(). +//! @{ +// +//***************************************************************************** + +#define SPI_SS_HARDWARE 0x00000001 +#define SPI_SS_SOFTWARE 0x00000000 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_SPI_DMA SPI DMA +//! \brief Values that show LPC17xx SPI DMA +//! +//! \note For LPC17xx, There is only one SPI module and not support DMA operation. +//! +//! @{ +// +//***************************************************************************** + +// +//! Enable DMA for transmit +// +#define SPI_DMA_TX 0x00000002 + +// +//! Enable DMA for receive +// +#define SPI_DMA_RX 0x00000001 + +// +//! Enable DMA for transfer and receive +// +#define SPI_DMA_BOTH 0x00000003 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +#endif // _LPC17XX_SPI_H_ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/uart.c b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/uart.c new file mode 100644 index 00000000..a2a45393 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/uart.c @@ -0,0 +1,1430 @@ +#include "CoX.h" +#include "hw_uart.h" + +//***************************************************************************** +// +// An array for uart callback function point +// +//***************************************************************************** +static xtEventCallback g_pfnUARTHandlerCallbacks[4] = {0}; + +//***************************************************************************** +// +//! \internal +//! Checks a uart base address. +//! +//! \param ulBase is the base address of the uart port. +//! +//! This function determines if a uart port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef xDEBUG +static xtBoolean +UARTBaseValid(unsigned long ulBase) +{ + return((ulBase == UART0_BASE) || + (ulBase == UART1_BASE) || + (ulBase == UART2_BASE) || + (ulBase == UART3_BASE)); +} +#endif + +//***************************************************************************** +// +//! \brief UART 0 interrupt handler. +//! This function is the UART interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void UART0IntHandler(void) +{ + if(g_pfnUARTHandlerCallbacks[0] != 0) + { + g_pfnUARTHandlerCallbacks[0](0, 0, 0, 0); + } +} + +//***************************************************************************** +// +//! \brief UART 1 interrupt handler. +//! This function is the UART interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void UART1IntHandler(void) +{ + if(g_pfnUARTHandlerCallbacks[1] != 0) + { + g_pfnUARTHandlerCallbacks[1](0, 0, 0, 0); + } +} + +//***************************************************************************** +// +//! \brief UART 2 interrupt handler. +//! This function is the UART interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void UART2IntHandler(void) +{ + if(g_pfnUARTHandlerCallbacks[2] != 0) + { + g_pfnUARTHandlerCallbacks[2](0, 0, 0, 0); + } +} + +//***************************************************************************** +// +//! \brief UART 3 interrupt handler. +//! This function is the UART interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void UART3IntHandler(void) +{ + if(g_pfnUARTHandlerCallbacks[3] != 0) + { + g_pfnUARTHandlerCallbacks[3](0, 0, 0, 0); + } +} + +//***************************************************************************** +// +//! \internal +//! \brief Configure UART baud rate. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [in] ulBaudrate is target baud rate. which can be most common value +//! e.g. 9600/115200. +//! +//! \return Show whether configure baud rate or not. +//! - xtrue configure success. +//! - xflase configure failure. +//! +//! \note This function is only for internal use! +// +//***************************************************************************** +static xtBoolean UartSetDivisors(unsigned long ulBase, unsigned long ulBaudrate) +{ + unsigned long ulPeriClk = 0; + unsigned long d = 0; + unsigned long m = 0; + unsigned long bestd = 0; + unsigned long bestm = 0; + unsigned long tmp = 0; + unsigned long current_error = 0; + unsigned long best_error = 0; + unsigned long max_error = 3; + unsigned long recalcbaud = 0; + unsigned long long best_divisor = 0; + unsigned long long divisor = 0; + + xASSERT(UARTBaseValid(ulBase)); + + switch(ulBase) + { + case UART0_BASE: + { + //ulPeriClk = SysCtlPeripheralClockGet(PCLKSEL_UART0); + break; + } + + case UART1_BASE: + { + //ulPeriClk = SysCtlPeripheralClockGet(PCLKSEL_UART1); + break; + } + + case UART2_BASE: + { + //ulPeriClk = SysCtlPeripheralClockGet(PCLKSEL_UART2); + break; + } + + case UART3_BASE: + { + //ulPeriClk = SysCtlPeripheralClockGet(PCLKSEL_UART3); + break; + } + default: // Error + { + while(1); + } + } + + + // In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers + // The formula is : + // BaudRate= uPeriClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL) + // It involves floating point calculations. That's the reason the formulae are adjusted with + // Multiply and divide method. + // The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions: + // 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 + + // Worst case + best_error = 0xFFFFFFFF; + bestd = 0; + bestm = 0; + best_divisor = 0; + + for (m = 1 ; m <= 15 ;m++) + { + for (d = 0 ; d < m ; d++) + { + divisor = ((unsigned long long)ulPeriClk<<28)*m/(ulBaudrate*(m+d)); + current_error = divisor & 0xFFFFFFFF; + + tmp = divisor>>32; + + // Adjust error + if(current_error > ((unsigned long)1<<31)) + { + current_error = -current_error; + tmp++; + } + + if(tmp<1 || tmp>65536) + { + continue; + } + + if( current_error < best_error) + { + best_error = current_error; + best_divisor = tmp; + bestd = d; + bestm = m; + if(best_error == 0) + { + break; + } + } + } + + if (best_error == 0) + { + break; + } + } + + // Can not find best match + if(best_divisor == 0) + { + return xfalse; + } + + recalcbaud = (ulPeriClk>>4) * bestm/(best_divisor * (bestm + bestd)); + + // Reuse best_error to evaluate baud error + if(ulBaudrate > recalcbaud) + { + best_error = ulBaudrate - recalcbaud; + } + else + { + best_error = recalcbaud -ulBaudrate; + } + + best_error = best_error * 100 / ulBaudrate; + + if (best_error < max_error) + { + if(ulBase == UART1_BASE) + { + // Nothing to do Now. + } + else + { + //Configure DLM/DLL + xHWREG(ulBase + LCR) |= LCR_DLAB; + xHWREG(ulBase + DLM) = (best_divisor >> 8) & 0xFF; + xHWREG(ulBase + DLL) = (best_divisor >> 0) & 0xFF; + + // DLAB Must be zero. + xHWREG(ulBase + LCR) &= ~LCR_DLAB; + bestd &= (unsigned long)0x0F; + bestm = (bestm << 4) & (unsigned long)0xF0; + xHWREG(ulBase + FDR) = bestd | bestm; + } + + return (xtrue); // Success configure Baud registers. + } + + return (xfalse); // Failure to configure Baud registers. +} + +//***************************************************************************** +// +//! \brief Receive an byte via uart. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \return The byte received. +//! +//! \note This function will exit unless receive an byte successfully. +// +//***************************************************************************** +unsigned char UARTByteRead(unsigned long ulBase) +{ + unsigned long ulTmpReg = 0; + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + // DLAB MUST be zero. + xHWREG(ulBase + LCR) &= ~LCR_DLAB; + + // Waiting UART receive one byte. + do + { + ulTmpReg = xHWREG(ulBase + LSR); + ulTmpReg &= LSR_RDR; + }while(0 == ulTmpReg); + + // Read the byte. + ulTmpReg = xHWREG(ulBase + RBR); + + return (ulTmpReg); +} + +//***************************************************************************** +// +//! \brief Transmit an byte via uart. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [in] ucData is the byte you want to transmit. +//! +//! \return None. +//! +//! \note This function will exit unless transmit an byte successfully. +// +//***************************************************************************** +void UARTByteWrite(unsigned long ulBase, unsigned char ucData) +{ + unsigned long ulTmpReg = 0; + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + // DLAB MUST be zero. + xHWREG(ulBase + LCR) &= ~LCR_DLAB; + + // Waiting UART receive one byte. + do + { + ulTmpReg = xHWREG(ulBase + LSR); + ulTmpReg &= LSR_THRE; + }while(0 == ulTmpReg); + + // Write Byte into FIFO. + xHWREG(ulBase + THR) = (unsigned long) ucData; // UART Data register. +} + +//***************************************************************************** +// +//! \brief Send string. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [out] pStr is the target string. +//! +//! \return None. +//! +//! \note This function will continue transmit until meet '\0' in string. +// +//***************************************************************************** +void UARTStrSend(unsigned long ulBase, unsigned char * pStr) +{ + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + while(0 != *pStr) + { + UARTByteWrite(ulBase, *pStr++); + } +} + +//***************************************************************************** +// +//! \brief Transmit a block of data via uart. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [in] pBuf is the buffer address. +//! +//! \param [in] ulLen is the size of buffer, ulLen Bytes. +//! +//! \return None. +// +//***************************************************************************** +void UARTBufWrite(unsigned long ulBase, unsigned char * pBuf, unsigned long ulLen) +{ + unsigned long i = 0; + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + for(i = 0; i < ulLen; i++) + { + UARTByteWrite(ulBase, pBuf[i]); + } +} + +//***************************************************************************** +// +//! \brief Receive a block of data via uart. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [out] pBuf is the buffer address. +//! +//! \param [in] ulLen is the size of buffer, ulLen Bytes. +//! +//! \return None. +// +//***************************************************************************** +void UARTBufRead(unsigned long ulBase, unsigned char * pBuf, unsigned long ulLen) +{ + unsigned long i = 0; + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + for(i = 0; i < ulLen; i++) + { + pBuf[i] = UARTByteRead(ulBase); + } +} + +//***************************************************************************** +// +//! \brief Get uart interrupt status. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \return The interrupt status which consist of the logical OR the following value: +//! - \ref INT_RDA +//! - \ref INT_THRE +//! - \ref INT_RLS +//! - \ref INT_MODEM +//! - \ref INT_CTS +//! - \ref INT_ABEO +//! - \ref INT_ABTO +//! +// +//***************************************************************************** +unsigned long UARTIntStatusGet(unsigned long ulBase) +{ + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + // Read status register. + return xHWREG(ulBase + IIR); +} + +//***************************************************************************** +// +//! \brief Check UART Interrupt Flag. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [in] ulIntFlags is the interrupt flag to be checked. +//! which can be one of the following value: +//! - \ref INT_RDA +//! - \ref INT_THRE +//! - \ref INT_RLS +//! - \ref INT_MODEM +//! - \ref INT_CTS +//! - \ref INT_ABEO +//! - \ref INT_ABTO +//! +//! \return +//! - xtrue The checked flag has been set. +//! - xflase The checked flag has not been set. +// +//***************************************************************************** +xtBoolean UARTIntStatusCheck(unsigned long ulBase, unsigned long ulIntFlags) +{ + unsigned long ulTmpReg = 0; + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + xASSERT( (ulIntFlags & ~( + INT_FLAG_RLS | + INT_FLAG_RDA | + INT_FLAG_CTI | + INT_FLAG_THRE | + INT_FLAG_MODEM| + INT_FLAG_ABEO | + INT_FLAG_ABTO + ) + ) == 0); + + switch(ulIntFlags) + { + case INT_FLAG_ABEO: + case INT_FLAG_ABTO: + case INT_FLAG_ABEO | INT_FLAG_ABTO: + { + if(xHWREG(ulBase + IIR) & ulIntFlags) + { + return (xtrue); + } + else + { + return (xfalse); + } + } + case INT_FLAG_RLS : + case INT_FLAG_RDA : + case INT_FLAG_CTI : + case INT_FLAG_THRE : + case INT_FLAG_MODEM : + { + ulTmpReg = xHWREG(ulBase + IIR); + + // Is there a pending interrupt? + if(ulTmpReg & IIR_INT_STAT) // No + { + return (xfalse); + } + else + { + ulTmpReg = (ulTmpReg & BIT_MASK(32, 3, 1)) >> 1; + if (ulTmpReg == ulIntFlags) + { + return (xtrue); + } + else + { + return (xfalse); + } + } + } + default: // Error + { + while (1); + } + } +} + +//***************************************************************************** +// +//! \brief Clear interrupt flag. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [in] ulFlags is the Modem status flag that you want to check. +//! This value must be logical OR of the following value: +//! - \ref INT_ABEO +//! - \ref INT_ABTO +//! +//! \return None. +// +//***************************************************************************** +void UARTIntFlagClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + xASSERT( (ulIntFlags & ~(INT_ABEO | INT_ABTO)) == 0); + + switch(ulIntFlags) + { + case INT_ABEO: + case INT_ABTO: + case INT_ABEO | INT_ABTO: + { + xHWREG(ulBase + ACR) |= ulIntFlags; + break; + } + + default: // Error + { + while(1); + } + } +} + +//***************************************************************************** +// +//! \brief Configure uart FIFO. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [in] ulCfg is the parameters to configure FIFO. +//! which can be the OR of the following value: +//! - \ref FIFO_CFG_FIFO_EN +//! - \ref FIFO_CFG_FIFO_DIS +//! - \ref FIFO_CFG_RX_FIFO_RESET +//! - \ref FIFO_CFG_TX_FIFO_RESET +//! - \ref FIFO_CFG_DMA_EN +//! - \ref FIFO_CFG_DMA_DIS +//! - \ref FIFO_CFG_RX_TRI_LVL_0 +//! - \ref FIFO_CFG_RX_TRI_LVL_1 +//! - \ref FIFO_CFG_RX_TRI_LVL_2 +//! - \ref FIFO_CFG_RX_TRI_LVL_3 +//! +//! \return None. +// +//***************************************************************************** +void UARTFIFOCfg(unsigned long ulBase, unsigned long ulCfg) +{ + unsigned long ulTmpReg = 0; + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + xASSERT( (ulCfg & ~( + FIFO_CFG_FIFO_EN | + FIFO_CFG_FIFO_DIS | + FIFO_CFG_RX_FIFO_RESET | + FIFO_CFG_TX_FIFO_RESET | + FIFO_CFG_DMA_EN | + FIFO_CFG_DMA_DIS | + FIFO_CFG_RX_TRI_LVL_0 | + FIFO_CFG_RX_TRI_LVL_1 | + FIFO_CFG_RX_TRI_LVL_2 | + FIFO_CFG_RX_TRI_LVL_3 + ) + ) == 0); + + // Configure FIFO + ulTmpReg = xHWREG(ulBase + FCR); + ulTmpReg &= ((~ulCfg) >> 16); + ulTmpReg |= (ulCfg & 0xFFFF); + xHWREG(ulBase + FCR) = ulTmpReg; +} + +//***************************************************************************** +// +//! \brief Start transmit function. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \return None. +// +//***************************************************************************** +void UARTTransStart(unsigned long ulBase) +{ + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + xHWREG(ulBase + TER) |= TER_TX_EN; +} + +//***************************************************************************** +// +//! \brief Stop transmit function. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \return None. +// +//***************************************************************************** +void UARTTransStop(unsigned long ulBase) +{ + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + xHWREG(ulBase + TER) &= ~TER_TX_EN; +} + +//***************************************************************************** +// +//! \brief Check UART status flag. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART1_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [in] ulFlags is the checked flag, which consist of the following +//! value: +//! - \ref RX_FIFO_NOT_EMPTY +//! - \ref OVERRUN_ERR +//! - \ref PARITY_ERR +//! - \ref FRAMING_ERR +//! - \ref BREAK_INT +//! - \ref TX_FIFO_EMPTY +//! - \ref TX_EMPTY +//! - \ref RX_FIFO_ERR +//! +//! \return +//! - xtrue The checked flag has been set. +//! - xflase The checked flag has not been set. +// +//***************************************************************************** +xtBoolean UARTStatCheck(unsigned long ulBase, unsigned long ulFlags) +{ + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + xASSERT( (ulFlags & ~( + RX_FIFO_NOT_EMPTY | + OVERRUN_ERR | + PARITY_ERR | + FRAMING_ERR | + BREAK_INT | + TX_FIFO_EMPTY | + TX_EMPTY | + RX_FIFO_ERR + ) + ) == 0); + + if(xHWREG(ulBase + LSR) & ulFlags) + { + return (xtrue); + } + else + { + return (xfalse); + } +} + +//***************************************************************************** +// +//! \brief Configure IrDA. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \param [in] ulCfg is the checked flag, which consist of the OR of following +//! value: +//! - \ref IRDA_INV_EN +//! - \ref IRDA_INV_DIS +//! - \ref IRDA_FIX_PULSE_DIS +//! - \ref IRDA_FIX_PULSE_2 +//! - \ref IRDA_FIX_PULSE_4 +//! - \ref IRDA_FIX_PULSE_8 +//! - \ref IRDA_FIX_PULSE_16 +//! - \ref IRDA_FIX_PULSE_32 +//! - \ref IRDA_FIX_PULSE_64 +//! - \ref IRDA_FIX_PULSE_128 +//! - \ref IRDA_FIX_PULSE_256 +//! +//! \return None. +//! +//! \note This function is only suit for UART0/2/3. +// +//***************************************************************************** +void UARTIrDACfg(unsigned long ulBase, unsigned long ulCfg) +{ + unsigned long ulTmpReg = 0; + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + xASSERT( (ulCfg & ~( + IRDA_INV_EN | + IRDA_INV_DIS | + IRDA_FIX_PULSE_DIS | + IRDA_FIX_PULSE_2 | + IRDA_FIX_PULSE_4 | + IRDA_FIX_PULSE_8 | + IRDA_FIX_PULSE_16 | + IRDA_FIX_PULSE_32 | + IRDA_FIX_PULSE_64 | + IRDA_FIX_PULSE_128 | + IRDA_FIX_PULSE_256 + ) + ) == 0); + + + // Configure IrDA Invert, Fixed Pulse width. + ulTmpReg = xHWREG(ulBase + ICR); + ulTmpReg &= ((~ulCfg) >> 16); + ulTmpReg |= (ulCfg & 0xFFFF); + xHWREG(ulBase + ICR) = ulTmpReg; + +} + +//***************************************************************************** +// +//! \brief Enable IrDA Function. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \return None. +//! +//! \note This function is only suit for UART0/2/3. +// +//***************************************************************************** +void UARTIrDAEnable(unsigned long ulBase) +{ + xHWREG(ulBase + ICR) |= ICR_IRDA_EN; +} + +//***************************************************************************** +// +//! \brief Disable IrDA Function. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART0_BASE +//! - \ref UART2_BASE +//! - \ref UART3_BASE +//! +//! \return None. +//! +//! \note This function is only suit for UART0/2/3. +// +//***************************************************************************** +void UARTIrDADisable(unsigned long ulBase) +{ + xASSERT(UARTBaseValid(ulBase)); + xHWREG(ulBase + ICR) &= ~ICR_IRDA_EN; +} + +//***************************************************************************** +// +//! \brief Configure Modem function. +//! This function configure uart modem. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART1_BASE +//! +//! \param [in] ulCfg is uart modem configure parameters. which can be the logical +//! OR of the following value: +//! - \ref LOOPBACK_MODE_EN +//! - \ref LOOPBACK_MODE_DIS +//! - \ref AUTO_RTS_EN +//! - \ref AUTO_RTS_DIS +//! - \ref AUTO_CTS_EN +//! - \ref AUTO_CTS_DIS +//! +//! \return None. +// +//***************************************************************************** +void UARTModemCfg(unsigned long ulBase, unsigned long ulCfg) +{ + unsigned long ulTmpReg = 0; + + // Check input parameters. + xASSERT(ulBase == UART1_BASE); + xASSERT( (ulCfg & ~( + LOOPBACK_MODE_EN | LOOPBACK_MODE_DIS | + AUTO_RTS_EN | AUTO_RTS_DIS | + AUTO_CTS_EN | AUTO_CTS_DIS + ) + ) == 0); + + // Configure UART Modem. + ulTmpReg = xHWREG(ulBase + MCR); + ulTmpReg &= ((~ulCfg) >> 16); + ulTmpReg |= (ulCfg & 0xFFFF); + xHWREG(ulBase + MCR) = ulTmpReg; + +} + +//***************************************************************************** +// +//! \brief Configure RS485 function. +//! This function configure uart rs485. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART1_BASE +//! +//! \param [in] ulCfg is uart modem configure parameters. which can be the logical +//! OR of the following value: +//! - \ref RS485_NMM_DIS +//! - \ref RS485_NMM_EN +//! - \ref RS485_RX_EN +//! - \ref RS485_RX_DIS +//! - \ref RS485_AUTO_ADDR_EN +//! - \ref RS485_AUTO_ADDR_DIS +//! - \ref RS485_AUTO_DIR_DIS +//! - \ref RS485_AUTO_DIR_RTS +//! - \ref RS485_AUTO_DIR_DTR +//! - \ref RS485_AUTO_DIR_INV_EN +//! - \ref RS485_AUTO_DIR_INV_DIS +//! +//! \return None. +// +//***************************************************************************** +void UARTRS485Cfg(unsigned long ulBase, unsigned long ulCfg) +{ + unsigned long ulTmpReg = 0; + + // Check input parameters. + xASSERT(ulBase == UART1_BASE); + xASSERT( (ulCfg & ~( + RS485_NMM_DIS | RS485_NMM_EN | + RS485_RX_EN | RS485_RX_DIS | + RS485_AUTO_ADDR_EN | RS485_AUTO_ADDR_DIS | + RS485_AUTO_DIR_DIS | + RS485_AUTO_DIR_RTS | + RS485_AUTO_DIR_DTR | + RS485_AUTO_DIR_INV_EN | RS485_AUTO_DIR_INV_DIS + ) + ) == 0); + + + + // Configure RS485 + ulTmpReg = xHWREG(ulBase + RS485CTRL); + ulTmpReg &= ((~ulCfg) >> 16); + ulTmpReg |= (ulCfg & 0xFFFF); + xHWREG(ulBase + RS485CTRL) = ulTmpReg; +} + +//***************************************************************************** +// +//! \brief Configure RS485 slave address. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART1_BASE +//! +//! \param [in] uladdr is rs485 slave address. +//! +//! \return None. +// +//***************************************************************************** +void UARTRS485AddrSet(unsigned long ulBase, unsigned long ulAddr) +{ + // Check input parameters. + xASSERT(ulBase == UART1_BASE); + xASSERT((ulAddr & ~RS485ADRMATCH_ADRMATCH_M) == 0); + + xHWREG(ulBase + ADRMATCH) = (ulAddr & RS485ADRMATCH_ADRMATCH_M); +} + +//***************************************************************************** +// +//! \brief Configure RS485 Delay Time value. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART1_BASE +//! +//! \param [in] uladdr is rs485 delay time value. +//! +//! \return None. +// +//***************************************************************************** +void UARTRS485DlyTimeSet(unsigned long ulBase, unsigned long ulVal) +{ + // Check input parameters. + xASSERT(ulBase == UART1_BASE); + xASSERT((ulVal & ~RS485DLY_DLY_M) == 0); + + xHWREG(ulBase + RS485DLY) = (ulVal & RS485DLY_DLY_M); +} + +//***************************************************************************** +// +//! \brief Get Modem status. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART1_BASE +//! +//! \return The Modem status value. +// +//***************************************************************************** +unsigned long UARTModemStatGet(unsigned long ulBase) +{ + // Check input parameters. + xASSERT(ulBase == UART1_BASE); + + return (xHWREG(ulBase + MSR)); +} + +//***************************************************************************** +// +//! \brief Check Modem status Flag. +//! +//! \param [in] ulBase is the uart module base address. +//! This value can be one of the following value: +//! - \ref UART1_BASE +//! +//! \param [in] ulFlags is the Modem status flag that you want to check. +//! This value must be logical OR of the following value: +//! - \ref xxx +//! +//! \return +//! - xtrue The checked flag has been set. +//! - xflase The checked flag has not been set. +// +//***************************************************************************** +xtBoolean UARTModemStatCheck(unsigned long ulBase, unsigned long ulFlags) +{ + + // Check input parameters. + xASSERT(ulBase == UART1_BASE); + + // Check Status Bit. + if(xHWREG(ulBase + MSR) & ulFlags) // Set + { + return (xtrue); + } + else // Unset + { + return (xfalse); + } +} + +//***************************************************************************** +// +//! \brief Sets the configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the UART for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter and the data +//! format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b xUART_CONFIG_WLEN_7, \b xUART_CONFIG_WLEN_6, and \b xUART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b xUART_CONFIG_STOP_1 and \b xUART_CONFIG_STOP_2 select one or two stop +//! bits (respectively). \b xUART_CONFIG_PAR_NONE, \b xUART_CONFIG_PAR_EVEN, +//! \b xUART_CONFIG_PAR_ODD, \b xUART_CONFIG_PAR_ONE, and +//! \b xUART_CONFIG_PAR_ZERO select the parity mode (no parity bit, +//! even parity bit, odd parity bit, parity bit always one, and parity bit +//! always zero, respectively). +//! +//! +//! \return None. +// +//***************************************************************************** + +void +xUARTConfigSet(unsigned long ulBase, unsigned long ulBaud, unsigned long ulConfig) +{ + unsigned long ulTmpReg = 0; + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase));; + xASSERT( (ulConfig & ~( + UART_CFG_LEN_5_BIT | + UART_CFG_LEN_6_BIT | + UART_CFG_LEN_7_BIT | + UART_CFG_LEN_8_BIT | + UART_CFG_STOP_1_BIT | + UART_CFG_STOP_2_BIT | + UART_CFG_PARITY_NONE | + UART_CFG_PARITY_ODD | + UART_CFG_PARITY_EVEN | + UART_CFG_PARITY_1 | + UART_CFG_PARITY_0 | + UART_CFG_BREAK_EN | + UART_CFG_BREAK_DIS + ) + ) == 0); + + // Configure UART Data length, Parity, stop bit, break. + ulTmpReg = xHWREG(ulBase + LCR); + ulTmpReg &= ((~ulConfig) >> 16); + ulTmpReg |= (ulConfig & 0xFFFF); + xHWREG(ulBase + LCR) = ulTmpReg; + + // Configure UART baud + UartSetDivisors(ulBase, ulBaud); +} + +//***************************************************************************** +// +//! \brief Receives a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. +//! +//! This function replaces the original UARTCharNonBlockingGet() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 is returned if there are no characters present in the +//! receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +long xUARTCharGetNonBlocking(unsigned long ulBase) +{ + xASSERT(UARTBaseValid(ulBase)); + // DLAB MUST be zero. + xHWREG(ulBase + LCR) &= ~LCR_DLAB; + + // Receive one byte ? + if( xHWREG(ulBase + LSR) & LSR_RDR) // Yes + { + // Read the byte. + return xHWREG(ulBase + RBR); + } + else // No + { + return (-1); + } +} + +//***************************************************************************** +// +//! \brief Waits for a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function waits until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. +// +//***************************************************************************** +long xUARTCharGet(unsigned long ulBase) +{ + xASSERT(UARTBaseValid(ulBase)); + return UARTByteRead(ulBase); +} + +//***************************************************************************** +// +//! \brief Sends a character to the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Writes the character \e ucData to the transmit FIFO for the specified port. +//! This function does not block, so if there is no space available, then a +//! \b false is returned, and the application must retry the function later. +//! +//! This function replaces the original UARTCharNonBlockingPut() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO or \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +xtBoolean xUARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) +{ + unsigned long ulTmpReg = 0; + + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + // DLAB MUST be zero. + xHWREG(ulBase + LCR) &= ~LCR_DLAB; + + // Transmitter FIFO is empty ? + ulTmpReg = xHWREG(ulBase + LSR); + if(ulTmpReg & LSR_THRE) // Yes + { + // Write Byte into FIFO. + xHWREG(ulBase + THR) = (unsigned long)ucData; + return (xtrue); + } + else // No + { + return (xfalse); + } +} + +//***************************************************************************** +// +//! \brief Waits to send a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Sends the character \e ucData to the transmit FIFO for the specified port. +//! If there is no space available in the transmit FIFO, this function waits +//! until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +void xUARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + xASSERT(UARTBaseValid(ulBase)); + UARTByteWrite(ulBase, ucData); +} + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b xUART_INT_ERROR - All Error interrupt +//! - \b xUART_INT_RT - Receive Timeout interrupt +//! - \b xUART_INT_TX - Transmit interrupt +//! - \b xUART_INT_RX - Receive interrupt +//! +//! \return None. +// +//***************************************************************************** +void xUARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + xASSERT( (ulIntFlags & ~( + INT_RDA | + INT_THRE | + INT_RLS | + INT_MODEM | + INT_CTS | + INT_ABEO | + INT_ABTO + ) + ) == 0); + + + // DLAB MUST be zero. + xHWREG(ulBase + LCR) &= ~LCR_DLAB; + + // Set interrupt control bit. + xHWREG(ulBase + IER) |= ulIntFlags; +} + +//***************************************************************************** +// +//! \brief Init interrupts callback for the specified UART Port. +//! +//! \param ulPort is the base address of the UART port. +//! \param xtI2CCallback is callback for the specified UART Port. +//! +//! Init interrupts callback for the specified UART Port. +//! +//! \return None. +// +//***************************************************************************** +void xUARTIntCallbackInit(unsigned long ulBase, xtEventCallback xtUARTCallback) +{ + // Check the parameters. + xASSERT(UARTBaseValid(ulBase)); + xASSERT(pfnCallback != 0); + + // Register user call back function. + switch(ulBase) + { + case UART0_BASE: + { + g_pfnUARTHandlerCallbacks[0] = xtUARTCallback; + break; + } + + case UART1_BASE: + { + g_pfnUARTHandlerCallbacks[1] = xtUARTCallback; + break; + } + + case UART2_BASE: + { + g_pfnUARTHandlerCallbacks[2] = xtUARTCallback; + break; + } + + case UART3_BASE: + { + g_pfnUARTHandlerCallbacks[3] = xtUARTCallback; + break; + } + } +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to UARTIntEnable(). +//! +//! - \b xUART_INT_ERROR - All Error interrupt +//! - \b xUART_INT_RT - Receive Timeout interrupt +//! - \b xUART_INT_TX - Transmit interrupt +//! - \b xUART_INT_RX - Receive interrupt +//! +//! \return None. +// +//***************************************************************************** +void xUARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + xASSERT( (ulIntFlags & ~( + INT_RDA | + INT_THRE | + INT_RLS | + INT_MODEM | + INT_CTS | + INT_ABEO | + INT_ABTO + ) + ) == 0); + + // DLAB MUST be zero. + //xHWREG(ulBase + LCR) &= ~LCR_DLAB; + + // Clear interrupt control bit. + xHWREG(ulBase + IER) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! \brief Gets current receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \return Returns a logical OR combination of the receiver error flags, +//! \b xUART_RXERROR_FRAMING, \b xUART_RXERROR_PARITY, \b xUART_RXERROR_BREAK +//! and \b xUART_RXERROR_OVERRUN. +// +//***************************************************************************** +unsigned long xUARTRxErrorGet(unsigned long ulBase) +{ + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + return( xHWREG(ulBase + LSR) ); +} + +//***************************************************************************** +// +//! \brief Clears all reported receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function is used to clear all receiver error conditions reported via +//! UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \return None. +// +//***************************************************************************** +void xUARTRxErrorClear(unsigned long ulBase) +{ + // Check input parameters. + xASSERT(UARTBaseValid(ulBase)); + + xHWREG(ulBase + LSR) |= xHWREG(ulBase + LSR); +} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/uart.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/uart.h new file mode 100644 index 00000000..6a0c75bb --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/uart.h @@ -0,0 +1,407 @@ +//***************************************************************************** +// +//! \file uart.h +//! \brief The uart implementation port file. +//! \version V3.0.0.1 +//! \date $CURRENTTIME$ +//! \author CooCox +//! \copyright +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __XUART_H__ +#define __XUART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup UART +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_UART_Cfg UART configure parameters. +//! Values that can be passed to uart general APIs +//! @{ +// +//***************************************************************************** + +//! Enable FIFO. +#define FIFO_CFG_FIFO_EN BIT_32_0 + +//! Disable FIFO. +#define FIFO_CFG_FIFO_DIS BIT_32_16 + +//! Flush Rx FIFO. +#define FIFO_CFG_RX_FIFO_RESET BIT_32_1 + +//! Flush Tx FIFO. +#define FIFO_CFG_TX_FIFO_RESET BIT_32_2 + +//! Enable DMA Mode. +#define FIFO_CFG_DMA_EN BIT_32_3 + +//! Disable DMA Mode. +#define FIFO_CFG_DMA_DIS BIT_32_19 + +//! Trigger level 0 (1 character) +#define FIFO_CFG_RX_TRI_LVL_0 (BIT_32_23 | BIT_32_22) + +//! Trigger level 1 (4 characters) +#define FIFO_CFG_RX_TRI_LVL_1 (BIT_32_23 | BIT_32_6) + +//! Trigger level 2 (8 characters) +#define FIFO_CFG_RX_TRI_LVL_2 (BIT_32_22 | BIT_32_7) + +//! Trigger level 3 (14 characters) +#define FIFO_CFG_RX_TRI_LVL_3 (BIT_32_7 | BIT_32_6) + +//! The UART receiver FIFO is not empty. +#define RX_FIFO_NOT_EMPTY BIT_32_0 + +//! Overrun error. +#define OVERRUN_ERR BIT_32_1 + +//! Parity error. +#define PARITY_ERR BIT_32_2 + +//! Framing error. +#define FRAMING_ERR BIT_32_3 + +//! Break interrupt. +#define BREAK_INT BIT_32_4 + +//! Transmitter holding register empty. +//! \note THRE is set immediately upon detection of an empty UART THR and +//! is cleared on a THR write. +#define TX_FIFO_EMPTY BIT_32_5 + +//! Transmitter empty. +//! \note TEMT is set when both THR and TSR are empty; TEMT is cleared when +//! either the TSR or the THR contain valid data. +#define TX_EMPTY BIT_32_6 + +//! Error in Rx FIFO +#define RX_FIFO_ERR BIT_32_7 + +//! Invert input serial. +#define IRDA_INV_EN BIT_32_1 + +//! Not Invert input serial. +#define IRDA_INV_DIS BIT_32_17 + +//! Disable fixed pulse width mode. +#define IRDA_FIX_PULSE_DIS BIT_32_18 + +//! Fixed pulse width: 2*Tpclk. +#define IRDA_FIX_PULSE_2 (BIT_32_2 | BIT_32_21 | BIT_32_20 | BIT_32_19) + +//! Fixed pulse width: 4*Tpclk. +#define IRDA_FIX_PULSE_4 (BIT_32_2 | BIT_32_21 | BIT_32_20 | BIT_32_3) + +//! Fixed pulse width: 8*Tpclk. +#define IRDA_FIX_PULSE_8 (BIT_32_2 | BIT_32_21 | BIT_32_4 | BIT_32_19) + +//! Fixed pulse width: 16*Tpclk. +#define IRDA_FIX_PULSE_16 (BIT_32_2 | BIT_32_21 | BIT_32_4 | BIT_32_3) + +//! Fixed pulse width: 32*Tpclk. +#define IRDA_FIX_PULSE_32 (BIT_32_2 | BIT_32_5 | BIT_32_20 | BIT_32_19) + +//! Fixed pulse width: 64*Tpclk. +#define IRDA_FIX_PULSE_64 (BIT_32_2 | BIT_32_5 | BIT_32_20 | BIT_32_3) + +//! Fixed pulse width: 128*Tpclk. +#define IRDA_FIX_PULSE_128 (BIT_32_2 | BIT_32_5 | BIT_32_4 | BIT_32_19) + +//! Fixed pulse width: 256*Tpclk. +#define IRDA_FIX_PULSE_256 (BIT_32_2 | BIT_32_5 | BIT_32_4 | BIT_32_3) + +//! UART Data Length 5-bit. +#define UART_CFG_LEN_5_BIT (BIT_32_17 | BIT_32_16) + +//! UART Data Length 6-bit. +#define UART_CFG_LEN_6_BIT (BIT_32_17 | BIT_32_0) + +//! UART Data Length 7-bit. +#define UART_CFG_LEN_7_BIT (BIT_32_1 | BIT_32_16) + +//! UART Data Length 8-bit. +#define UART_CFG_LEN_8_BIT (BIT_32_1 | BIT_32_0) + +//! UART Stop 1-bit. +#define UART_CFG_STOP_1_BIT BIT_32_18 + +//! UART Stop 2-bit. +#define UART_CFG_STOP_2_BIT BIT_32_2 + +//! UART None Parity. +#define UART_CFG_PARITY_NONE (BIT_32_21 | BIT_32_20 | BIT_32_19) + +//! UART odd parity. +#define UART_CFG_PARITY_ODD (BIT_32_21 | BIT_32_20 | BIT_32_3) + +//! UART even parity. +#define UART_CFG_PARITY_EVEN (BIT_32_21 | BIT_32_4 | BIT_32_3) + +//! UART forced 1 stick parity. +#define UART_CFG_PARITY_1 (BIT_32_5 | BIT_32_20 | BIT_32_3) + +//! UART forced 0 stick parity. +#define UART_CFG_PARITY_0 (BIT_32_5 | BIT_32_4 | BIT_32_3) + +//! Enable break transmission. +#define UART_CFG_BREAK_EN BIT_32_6 + +//! Disable break transmission. +#define UART_CFG_BREAK_DIS BIT_32_22 + +//! Enable Modem loopback mode. +#define LOOPBACK_MODE_EN BIT_32_4 + +//! Disable Modem loopback mode. +#define LOOPBACK_MODE_DIS BIT_32_20 + +//! Enable Auto-RTS Flow control. +#define AUTO_RTS_EN BIT_32_6 + +//! Disable Auto-RTS Flow control. +#define AUTO_RTS_DIS BIT_32_22 + +//! Enable Auto-CTS Flow control. +#define AUTO_CTS_EN BIT_32_7 + +//! Disable Auto-CTS Flow control. +#define AUTO_CTS_DIS BIT_32_23 + +//! RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled +#define RS485_NMM_DIS BIT_32_16 + +//! RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled.In this mode, +//! an address is detected when a received byte causes the UART to set +//! the parity error and generate an interrupt +#define RS485_NMM_EN BIT_32_0 + +//! Enable receiver. +#define RS485_RX_EN BIT_32_17 + +//! Disable receiver. +#define RS485_RX_DIS BIT_32_1 + +//! Enable Auto Address detect. +#define RS485_AUTO_ADDR_EN BIT_32_2 + +//! Disable Auto Address detect. +#define RS485_AUTO_ADDR_DIS BIT_32_18 + +//! Disable Auto Direction Control. +#define RS485_AUTO_DIR_DIS BIT_32_20 + +//! Enable Auto Direction Control, use pin RTS as direction control. +#define RS485_AUTO_DIR_RTS (BIT_32_4 | BIT_32_19) + +//! Enable Auto Direction Control, use pin DTR as direction control. +#define RS485_AUTO_DIR_DTR (BIT_32_4 | BIT_32_3) + +//! The direction control pin will be driven to logic '1' when the +//! transmitter has data to be sent.It will be driven to logic '0' +//! after the last bit of data has been transmitted +#define RS485_AUTO_DIR_INV_EN BIT_32_5 + +//! The direction control pin will be driven to logic '0' when the +//! transmitter has data to be sent.It will be driven to logic '1' +//! after the last bit of data has been transmitted. +#define RS485_AUTO_DIR_INV_DIS BIT_32_21 + +//! State change detected on modem input CTS. +#define MODEM_DELTA_CTS BIT_32_0 + +//! State change detected on modem input DSR. +#define MODEM_DELTA_DSR BIT_32_1 + +//! State change detected on modem input RI. +#define MODEM_TRIL_EDGE_RI BIT_32_2 + +//! State change detected on modem input DCD. +#define MODEM_DELTA_DCD BIT_32_3 + +//! Clear To Send State. +#define MODEM_CTS BIT_32_4 + +//! Data Set Ready State. +#define MODEM_DSR BIT_32_5 + +//! Ring indicator state. +#define MODEM_RI BIT_32_6 + +//! Data carrier detect state. +#define MODEM_DCD BIT_32_7 + + +//! Receive data available interrupt. +#define INT_RDA BIT_32_0 + +//! Transfer hold register empty interrupt. +#define INT_THRE BIT_32_1 + +//! Receive line status interrupt. +#define INT_RLS BIT_32_2 + +//! UART modem interrupt. +//! \note This parameter is only suit for UART1. +#define INT_MODEM BIT_32_3 + +//! Clear to send interrupt. +#define INT_CTS BIT_32_7 + +//! Auto-baud end interrupt. +#define INT_ABEO BIT_32_8 + +//! Auto-baud time-out interrupt. +#define INT_ABTO BIT_32_9 + +//! \note Those parameters is only suit for UARTIntCheck function. +//! Receive Line Status +#define INT_FLAG_RLS ((unsigned long)0x03) + +//! Receive Data Available +#define INT_FLAG_RDA ((unsigned long)0x02) + +//! Character Time-Out Indicator +#define INT_FLAG_CTI ((unsigned long)0x06) + +//! THRE Interrupt +#define INT_FLAG_THRE ((unsigned long)0x01) + +//! Modem Interrupt +#define INT_FLAG_MODEM ((unsigned long)0x00) + +//! End of auto-baud interrupt. +#define INT_FLAG_ABEO BIT_32_8 + +//! Auto-baud time-out interrupt. +#define INT_FLAG_ABTO BIT_32_9 + +/////////////////////////////////////////////////////////////////////////////// +// define for port to cox 'x' prefixed interface +/////////////////////////////////////////////////////////////////////////////// +#define UART_INT_ERROR INT_RLS +#define UART_INT_RT INT_RLS +#define UART_INT_TX INT_THRE +#define UART_INT_RX INT_RDA + +#define UART_RXERROR_OVERRUN OVERRUN_ERR +#define UART_RXERROR_BREAK BREAK_INT +#define UART_RXERROR_PARITY PARITY_ERR +#define UART_RXERROR_FRAMING FRAMING_ERR + +#define UART_CONFIG_WLEN_8 UART_CFG_LEN_8_BIT +#define UART_CONFIG_WLEN_7 UART_CFG_LEN_7_BIT +#define UART_CONFIG_WLEN_6 UART_CFG_LEN_6_BIT +#define UART_CONFIG_WLEN_5 UART_CFG_LEN_5_BIT + +#define UART_CONFIG_STOP_1 UART_CFG_STOP_1_BIT +#define UART_CONFIG_STOP_2 UART_CFG_STOP_2_BIT + +#define UART_CONFIG_PAR_ONE UART_CFG_PARITY_1 +#define UART_CONFIG_PAR_ZERO UART_CFG_PARITY_0 + +#define UART_BLOCK_UART BIT_32_0 +#define UART_BLOCK_TX BIT_32_1 +#define UART_BLOCK_RX BIT_32_2 + +#define UART_FIFO_RX_1 FIFO_CFG_RX_TRI_LVL_0 +#define UART_FIFO_RX_4 FIFO_CFG_RX_TRI_LVL_1 +#define UART_FIFO_RX_8 FIFO_CFG_RX_TRI_LVL_2 +#define UART_FIFO_RX_14 FIFO_CFG_RX_TRI_LVL_3 + + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __XUART_H__ + diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/wdt.c b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/wdt.c new file mode 100644 index 00000000..784f4138 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/wdt.c @@ -0,0 +1,340 @@ +//***************************************************************************** +// +//! \file wdt.c +//! \brief Driver for the WDT +//! \version V3.0.0.0 +//! \date 8/15/2014 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2014, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +#include "CoX.h" +#include "hw_sysctl.h" +#include "hw_wdt.h" + +#define WDT_CFG_MODE_M (BIT_32_1 | BIT_32_0) +#define WDT_CFG_CLKSRC_M (BIT_32_3 | BIT_32_2) + +static unsigned long _PreValue = 0; + +//***************************************************************************** +// +// An array is Watchdog callback function point +// +//***************************************************************************** +static xtEventCallback g_pfnWDTHandlerCallbacks = 0; + +//***************************************************************************** +// +//! \brief WDT interrupt handler. +//! This function is the WDT interrupt handler, it simple execute the +//! callback function if there be one. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void WDTIntHandler(void) +{ + if(g_pfnWDTHandlerCallbacks != 0) + { + g_pfnWDTHandlerCallbacks(0, 0, 0, 0); + } + else + { + while(1); + } +} + +//***************************************************************************** +// +//! \brief Register user interrupts callback function for the WDT. +//! +//! \param [in] xtPortCallback is user callback for the WDT. +//! +//! \return None. +// +//***************************************************************************** +void xWDTIntCallbackInit(unsigned long ulBase, xtEventCallback xtWDTCallback) +{ + // Check the parameters. + xASSERT(pfnCallback != 0); + + g_pfnWDTHandlerCallbacks = xtWDTCallback; +} + +//***************************************************************************** +// +//! \brief Configurate The WatchDog Timer Module. +//! This function is to configure The WatchDog Timer(WDT) clock source +//! and mode. +//! +//! \param [in] ulConfig is the WDT clock source Selection and Mode. +//! This value can be OR of two type of value: +//! - clock source +//! - \ref WDT_CFG_CLKSRC_IRC +//! - \ref WDT_CFG_CLKSRC_APB +//! - \ref WDT_CFG_CLKSRC_RTC +//! - clock source +//! - \ref WDT_CFG_INT_MODE +//! - \ref WDT_CFG_RESET_MODE +//! +//! \param [in] ulValue is the Timer's reload value. +//! 0xFF <= ulReload <= 0xFFFFFFFF +//! +//! \return None. +//! +//! \note xWDTInit(ulBase, ulConfig, ulReload) must be called before function: +//! \ref xWDTEnable and \ref xWDTFunctionEnable. +//! +// +//***************************************************************************** +static void WDTCfg(unsigned long ulCfg, unsigned long ulValue) +{ + unsigned long ulTmpReg = 0; + +/************ Configure Watchdog Mode and Clock source **************/ + switch(ulCfg & WDT_CFG_MODE_M) + { + case WDT_INT_FUNCTION: // Triggle Interrupt when underflow. + { + ulTmpReg = xHWREG(WDT_BASE + WDT_MOD); + //ulTmpReg |= WDMOD_EN; + ulTmpReg &= ~WDMOD_RESET; + xHWREG(WDT_BASE + WDT_MOD) = ulTmpReg; + break; + } + case WDT_RESET_FUNCTION: // Reset MCU when underflow. + { + ulTmpReg = xHWREG(WDT_BASE + WDT_MOD); + ulTmpReg |= /*WDMOD_EN |*/ WDMOD_RESET; + xHWREG(WDT_BASE + WDT_MOD) = ulTmpReg; + break; + } + } + + switch(ulCfg & WDT_CFG_CLKSRC_M) + { + case WDT_S_INTSL: // Internal RC clock. + { + ulTmpReg = xHWREG(WDT_BASE + WDT_CLKSEL); + ulTmpReg &= ~WDCLKSEL_WDSEL_M; + ulTmpReg |= WDCLKSEL_WDSEL_IRC; + xHWREG(WDT_BASE + WDT_CLKSEL) = ulTmpReg; + break; + } + case WDT_S_HCLK_DIV: // APB Clock source. + { + ulTmpReg = xHWREG(WDT_BASE + WDT_CLKSEL); + ulTmpReg &= ~WDCLKSEL_WDSEL_M; + ulTmpReg |= WDCLKSEL_WDSEL_APB; + xHWREG(WDT_BASE + WDT_CLKSEL) = ulTmpReg; + break; + } + case WDT_S_EXTSL: // RTC Clock source. + { + ulTmpReg = xHWREG(WDT_BASE + WDT_CLKSEL); + ulTmpReg &= ~WDCLKSEL_WDSEL_M; + ulTmpReg |= WDCLKSEL_WDSEL_RTC; + xHWREG(WDT_BASE + WDT_CLKSEL) = ulTmpReg; + break; + } + } + + +/************* Configure Watchdog const value register **************/ + if(ulValue < (unsigned long)0xFF) + { + ulValue = 0xFF; + } + + xHWREG(WDT_BASE + WDT_TC) = ulValue; + + // Feed watchdog. + xHWREG(WDT_BASE + WDT_FEED) = (unsigned long) 0xAA; + xHWREG(WDT_BASE + WDT_FEED) = (unsigned long) 0x55; +} + +//***************************************************************************** +// +//! \brief Enable WDT Module. +//! This function is used to Enable WDT module and start counter. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void xWDTEnable(unsigned long ulBase) +{ + // Avoid Compiler warning. + (void) ulBase; + + // Enable Watchdog bit. + xHWREG(WDT_BASE + WDT_MOD) |= WDMOD_EN; + + // Feed dog to clock the watchdog. + xHWREG(WDT_BASE + WDT_FEED) = (unsigned long) 0xAA; + xHWREG(WDT_BASE + WDT_FEED) = (unsigned long) 0x55; +} + +//***************************************************************************** +// +//! \brief Disable WDT Module. +//! This function is used to Disable WDT module and Stop counter. +//! +//! \param None. +//! +//! \return None. +//! +// +//***************************************************************************** +void xWDTDisable(unsigned long ulBase) +{ + // Avoid Compiler warning. + (void) ulBase; + + // Enable Watchdog bit. + xHWREG(WDT_BASE + WDT_MOD) &= ~WDMOD_EN; + + // Feed dog to clock the watchdog. + xHWREG(WDT_BASE + WDT_FEED) = (unsigned long) 0xAA; + xHWREG(WDT_BASE + WDT_FEED) = (unsigned long) 0x55; +} + +//***************************************************************************** +// +//! \brief Configurate The WatchDog Timer(WDT)'s Timer Interval. +//! This function is to configureThe WatchDog Timer(WDT)'s Timer Interval. +//! There are three factors to determine the Timer Interval, they are: +//! - clock source +//! - Prescaler divider +//! - reload value +//! +//! \param [in] ulBase is the base address of the WatchDog Timer(WDT) module. +//! This value must be \ref xWDT_BASE. +//! +//! \param [in] ulConfig is the Timer's Prescaler divider and clock source Selection. +//! - \ref xWDT_S_INTSL +//! - \ref xWDT_S_EXTSL +//! +//! \param [in] ulReload is the Timer's reload value. +//! 0xFF <= ulReload <= 0xFFFFFFFF +//! +//! \return None. +//! +//! \note xWDTInit(ulBase, ulConfig, ulReload) must be called before function: +//! \ref xWDTEnable and \ref xWDTFunctionEnable. +//! +// +//***************************************************************************** +void xWDTInit(unsigned long ulBase, unsigned long ulConfig, unsigned long ulReload) +{ + // Avoid Compiler warning. + (void) ulBase; + + // Configure WDT clock source. + _PreValue = ulReload; + WDTCfg(ulConfig, ulReload); +} + +//***************************************************************************** +// +//! \brief Enable the watch dog timer's function. +//! This function is to Enable the watch dog timer's function such as +//! Interrupt reset. +//! +//! \param [in] ulBase is the base address of the WatchDog Timer(WDT) module. +//! This value must be \ref xWDT_BASE. +//! +//! \param [in] ulFunction is the watch dog timer's function. +//! This parameter is the OR value of any of the following: +//! - \ref xWDT_INT_FUNCTION +//! - \ref xWDT_RESET_FUNCTION +//! +//! \note xWDTInit(ulBase, ulConfig, ulReload) must be called before function: +//! \ref xWDTEnable and \ref xWDTFunctionEnable. +// +//***************************************************************************** +void xWDTFunctionEnable(unsigned long ulBase, unsigned long ulFunction) +{ + // Avoid Compiler warning. + (void) ulBase; + + // User must call xWDTInit function to set reload value at first! + if(_PreValue == 0) + { + while(1); + } + + // Configure WDT interrupt/reset mode. + WDTCfg(ulFunction, _PreValue); +} + +//***************************************************************************** +// +//! \brief Disable the watch dog timer's function. +//! This function is to disable the watch dog timer's function such as +//! Interrupt reset. +//! +//! \param [in] ulBase is the base address of the WatchDog Timer(WDT) module. +//! This value must be \ref xWDT_BASE. +//! +//! \param [in] ulFunction is the watch dog timer's function. +//! This parameter is the OR value of any of the following: +//! - \ref xWDT_INT_FUNCTION +//! - \ref xWDT_RESET_FUNCTION +//! +//! \return None. +//! +//! \note For LPC17xx, You can't Disable Those functions. +// +//***************************************************************************** +void xWDTFunctionDisable(unsigned long ulBase, unsigned long ulFunction) +{ + // Avoid compiler warning + (void) ulBase; + (void) ulFunction; + + // Check input parameters valid. + xASSERT(ulBase == xWDT_BASE); + xASSERT((ulFunction == xWDT_INT_FUNCTION) || (ulFunction == xWDT_RESET_FUNCTION)); + + // Set watch dog mode register to default value. + xHWREG(WDT_BASE + WDT_MOD) = 0x00; + + // Feed watchdog. + xHWREG(WDT_BASE + WDT_FEED) = (unsigned long) 0xAA; + xHWREG(WDT_BASE + WDT_FEED) = (unsigned long) 0x55; +} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xdebug.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/wdt.h similarity index 56% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xdebug.h rename to CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/wdt.h index 96e09a3a..9bfe0fac 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xdebug.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC/libcox/wdt.h @@ -1,44 +1,55 @@ //***************************************************************************** // -//! \file xdebug.h -//! \brief Macros for assisting debug of the peripheral library. -//! \version V2.1.1.1 -//! \date 11/14/2011 +//! \file wdt.h +//! \brief Prototypes for the WDT Driver. +//! \version V3.0.0.0 +//! \date 8/15/2014 //! \author CooCox //! \copy //! -//! Copyright (c) 2011, CooCox +//! Copyright (c) 2014, CooCox //! All rights reserved. -//! -//! Redistribution and use in source and binary forms, with or without -//! modification, are permitted provided that the following conditions -//! are met: -//! -//! * Redistributions of source code must retain the above copyright -//! notice, this list of conditions and the following disclaimer. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. //! * Redistributions in binary form must reproduce the above copyright //! notice, this list of conditions and the following disclaimer in the -//! documentation and/or other materials provided with the distribution. -//! * Neither the name of the nor the names of its -//! contributors may be used to endorse or promote products derived -//! from this software without specific prior written permission. -//! +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! //! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF //! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF //! THE POSSIBILITY OF SUCH DAMAGE. // //***************************************************************************** -#ifndef __xDEBUG_H__ -#define __xDEBUG_H__ +#ifndef __LPC17XX_WDT_H__ +#define __LPC17XX_WDT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // @@ -49,67 +60,67 @@ //***************************************************************************** // -//! \addtogroup xDebug xDebug -//! \brief Provided some assert macros to help debug. -//! -//! This module provides a macro called \ref xASSERT, Used to assert -//! some conditions if is correct. -//! -//! \section xDebug_When When User the Debug feature? -//! - Verify the legitimacy of the parameters -//! - Judge execution of the accuracy of the results -//! - where you want to determine if actual == expected ? -//! . -//! -//! \section xDebug_How How to use the Debug Feature? -//! -# Enable the debug feature by doing a \b xDEBUG build. -//! -# add the \ref xASSERT where you want. -//! . -//! -//! We strongly recommend you to open the debug characteristics in your -//! development process. This way can find out the questions as soon -//! as possible. -//! -//! When release the code, you should shut down the debug characteristics, -//! because they also take up CPU time, and you have ensured the condition -//! is ok in the debug process. -//! +//! \addtogroup WDT +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_WDT //! @{ // //***************************************************************************** //***************************************************************************** // -//! \addtogroup xDebug_Exported_APIs xDebug API -//! \brief xDebug API Reference. +//! \addtogroup WDT_Function_Type WDT Function Type +//! \brief Values that can be passed to WDTimerFunctionEnable(), +//! WDTimerFunctionDisable(). //! @{ // //***************************************************************************** -extern void __xerror__(char *pcFilename, unsigned long ulLine); +// +//! Generate Interrupt when watch dog time out +// +#define WDT_INT_FUNCTION 0x00000001 + +// +//! Reset CPU when watch dog time out +// +#define WDT_RESET_FUNCTION 0x00000003 //***************************************************************************** // -//! \brief The ASSERT macro. -//! -//! \param expr is the expression to be check. -//! -//! It does the actual assertion checking. Typically, this will be for -//! procedure arguments. -//! -//! \return None. -// -//***************************************************************************** -#ifdef xDEBUG -#define xASSERT(expr) { \ - if(!(expr)) \ - { \ - __xerror__(__FILE__, __LINE__); \ - } \ - } -#else -#define xASSERT(expr) -#endif +//! @} +// +//***************************************************************************** + + +//***************************************************************************** +// +//! \addtogroup WDT_Time_Interval_Config WDT Time Interval Configuration +//! \brief Values that can be passed to WDTimerInit(). +//! @{ +// +//***************************************************************************** + +// +//! Internal RC Clock +// +#define WDT_S_INTSL 0x00000004 + +// +//! Select APB as WDT clock source +// +#define WDT_S_HCLK_DIV 0x00000008 + +// +//! External RTC Clock +// +#define WDT_S_EXTSL 0x0000000C + //***************************************************************************** // @@ -129,6 +140,19 @@ extern void __xerror__(char *pcFilename, unsigned long ulLine); // //***************************************************************************** -#endif // __xDEBUG_H__ +//***************************************************************************** +// +//! @} +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif +#endif // __LPC17XX_WDT_H__ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/hw_usb.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/hw_usb.h new file mode 100644 index 00000000..40dea845 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/hw_usb.h @@ -0,0 +1,396 @@ +//***************************************************************************** +// +//! \file xhw_usb.h +//! \brief Macros used when accessing the usb control hardware. +//! \version V2.2.1.0 +//! \date $CURRENTTIME$ +//! \author CooCox +//! \copyright +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __XHW_USB_H__ +#define __XHW_USB_H__ + +#include "xhw_types.h" +#include "xhw_ints.h" +#include "xcore.h" +#include "xhw_memmap.h" +#include "xhw_nvic.h" +#include "xhw_sysctl.h" +#include "xdebug.h" +#include "xsysctl.h" + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup USBD +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_usb_Register usb Register Hardware Layer. +//! \brief Here are detail register information. +//! it contains: +//! - Register offset. +//! - detailed bit-field of the registers. +//! - Enum and mask of the registers. +//! +//! \note Users can read or write the registers through xHWREG(). +//! +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_usb_Register_Offsets usb Register Offset(Map) +//! \brief Here is the register offset, users can get the register address +//! via usbx_BASE + offset, (x=A/B/C...). +//! @{ +// +//***************************************************************************** + +//! USB Clock Control +#define USB_CLK_CTRL ((unsigned long)0x5000CFF4) + +//! USB Clock Status +#define USB_CLK_ST ((unsigned long)0x5000CFF8) + +//! USB Interrupt Status +#define USB_INT_ST ((unsigned long)0x400FC1C0) + +//! USB Device Interrupt Status +#define USB_DEV_INT_ST ((unsigned long)0x5000C200) + +//! USB Device Interrupt Enable +#define USB_DEV_INT_EN ((unsigned long)0x5000C204) + +//! USB Device Interrupt Clear +#define USB_DEV_INT_CLR ((unsigned long)0x5000C208) + +//! USB Device Interrupt Set +#define USB_DEV_INT_SET ((unsigned long)0x5000C20C) + +//! USB Device Interrupt Priority +#define USB_DEV_INT_PRI ((unsigned long)0x5000C22C) + +//! USB Endpoint Interrupt Status +#define USB_EP_INT_ST ((unsigned long)0x5000C230) + +//! USB Endpoint Interrupt Enable +#define USB_EP_INT_EN ((unsigned long)0x5000C234) + +//! USB Endpoint Interrupt Clear +#define USB_EP_INT_CLR ((unsigned long)0x5000C238) + +//! USB Endpoint Interrupt Set +#define USB_EP_INT_SET ((unsigned long)0x5000C23C) + +//! USB Endpoint Priority +#define USB_EP_INT_PRI ((unsigned long)0x5000C240) + +//! USB Realize Endpoint +#define USB_RE_EP ((unsigned long)0x5000C244) + +//! USB Endpoint Index +#define USB_EP_INDEX ((unsigned long)0x5000C248) + +//! USB MaxPacketSize +#define USB_MAX_PSIZE ((unsigned long)0x5000C24C) + +//! USB Receive Data +#define USB_RX_DATA ((unsigned long)0x5000C218) + +//! USB Receive Packet Length +#define USB_RX_PLEN ((unsigned long)0x5000C220) + +//! USB Transmit Data +#define USB_TX_DATA ((unsigned long)0x5000C21C) + +//! USB Transmit Packet Length +#define USB_TX_PLEN ((unsigned long)0x5000C224) + +//! USB Control +#define USB_CTRL ((unsigned long)0x5000C228) + + +//! USB Command Code +#define USB_CMD_CODE ((unsigned long)0x5000C210) + +//! USB Command Data +#define USB_CMD_DATA ((unsigned long)0x5000C214) + +//! USB DMA Request Status +#define USB_DMA_RST ((unsigned long)0x5000C250) + +//! USB DMA Request Clear +#define USB_DMA_RCLR ((unsigned long)0x5000C254) + +//! USB DMA Request Set +#define USB_DMA_RSET ((unsigned long)0x5000C258) + +//! USB UDCA Head +#define USB_UDCAH ((unsigned long)0x5000C280) + +//! USB Endpoint DMA Status +#define USB_EP_DMA_ST ((unsigned long)0x5000C284) + +//! USB Endpoint DMA Enable +#define USB_EP_DMA_EN ((unsigned long)0x5000C288) + +//! USB Endpoint DMA Disable +#define USB_EP_DMA_DIS ((unsigned long)0x5000C28C) + +//! USB DMA Interrupt Status +#define USB_DMA_INT_ST ((unsigned long)0x5000C290) + +//! USB DMA Interrupt Enable +#define USB_DMA_INT_EN ((unsigned long)0x5000C294) + +//! USB End of Transfer Interrupt Status +#define USB_EOT_INT_ST ((unsigned long)0x5000C2A0) + +//! USB End of Transfer Interrupt Clear +#define USB_EOT_INT_CLR ((unsigned long)0x5000C2A4) + +//! USB End of Transfer Interrupt Set +#define USB_EOT_INT_SET ((unsigned long)0x5000C2A8) + +//! USB New DD Request Interrupt Status +#define USB_NDDR_INT_ST ((unsigned long)0x5000C2AC) + +//! USB New DD Request Interrupt Clear +#define USB_NDDR_INT_CLR ((unsigned long)0x5000C2B0) + +//! USB New DD Request Interrupt Set +#define USB_NDDR_INT_SET ((unsigned long)0x5000C2B4) + +//! USB System Error Interrupt Status +#define USB_SYS_ERR_INT_ST ((unsigned long)0x5000C2B8) + +//! USB System Error Interrupt Clear +#define USB_SYS_ERR_INT_CLR ((unsigned long)0x5000C2BC) + +//! USB System Error Interrupt Set +#define USB_SYS_ERR_INT_SET ((unsigned long)0x5000C2C0) + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup LPC17xx_usb_Register_Mcrio usb Register usefull mcrio +//! @{ +// +//***************************************************************************** + +/* Device Interrupt Bit Definitions */ +#define FRAME_INT 0x00000001 +#define EP_FAST_INT 0x00000002 +#define EP_SLOW_INT 0x00000004 +#define DEV_STAT_INT 0x00000008 +#define CCEMTY_INT 0x00000010 +#define CDFULL_INT 0x00000020 +#define RxENDPKT_INT 0x00000040 +#define TxENDPKT_INT 0x00000080 +#define EP_RLZED_INT 0x00000100 +#define ERR_INT 0x00000200 + +/* Rx & Tx Packet Length Definitions */ +#define PKT_LNGTH_MASK 0x000003FF +#define PKT_DV 0x00000400 +#define PKT_RDY 0x00000800 + +/* USB Control Definitions */ +#define CTRL_RD_EN 0x00000001 +#define CTRL_WR_EN 0x00000002 + +/* Command Codes */ +#define CMD_SET_ADDR 0x00D00500 +#define CMD_CFG_DEV 0x00D80500 +#define CMD_SET_MODE 0x00F30500 +#define CMD_RD_FRAME 0x00F50500 +#define DAT_RD_FRAME 0x00F50200 +#define CMD_RD_TEST 0x00FD0500 +#define DAT_RD_TEST 0x00FD0200 +#define CMD_SET_DEV_STAT 0x00FE0500 +#define CMD_GET_DEV_STAT 0x00FE0500 +#define DAT_GET_DEV_STAT 0x00FE0200 +#define CMD_GET_ERR_CODE 0x00FF0500 +#define DAT_GET_ERR_CODE 0x00FF0200 +#define CMD_RD_ERR_STAT 0x00FB0500 +#define DAT_RD_ERR_STAT 0x00FB0200 +#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) +#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) +#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) +#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) +#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) +#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) +#define CMD_CLR_BUF 0x00F20500 +#define DAT_CLR_BUF 0x00F20200 +#define CMD_VALID_BUF 0x00FA0500 + +/* Device Address Register Definitions */ +#define DEV_ADDR_MASK 0x7F +#define DEV_EN 0x80 + +/* Device Configure Register Definitions */ +#define CONF_DVICE 0x01 + +/* Device Mode Register Definitions */ +#define AP_CLK 0x01 +#define INAK_CI 0x02 +#define INAK_CO 0x04 +#define INAK_II 0x08 +#define INAK_IO 0x10 +#define INAK_BI 0x20 +#define INAK_BO 0x40 + +/* Device Status Register Definitions */ +#define DEV_CON 0x01 +#define DEV_CON_CH 0x02 +#define DEV_SUS 0x04 +#define DEV_SUS_CH 0x08 +#define DEV_RST 0x10 + +/* Error Code Register Definitions */ +#define ERR_EC_MASK 0x0F +#define ERR_EA 0x10 + +/* Error Status Register Definitions */ +#define ERR_PID 0x01 +#define ERR_UEPKT 0x02 +#define ERR_DCRC 0x04 +#define ERR_TIMOUT 0x08 +#define ERR_EOP 0x10 +#define ERR_B_OVRN 0x20 +#define ERR_BTSTF 0x40 +#define ERR_TGL 0x80 + +/* Endpoint Select Register Definitions */ +#define EP_SEL_F 0x01 +#define EP_SEL_ST 0x02 +#define EP_SEL_STP 0x04 +#define EP_SEL_PO 0x08 +#define EP_SEL_EPN 0x10 +#define EP_SEL_B_1_FULL 0x20 +#define EP_SEL_B_2_FULL 0x40 + +/* Endpoint Status Register Definitions */ +#define EP_STAT_ST 0x01 +#define EP_STAT_DA 0x20 +#define EP_STAT_RF_MO 0x40 +#define EP_STAT_CND_ST 0x80 + +/* Clear Buffer Register Definitions */ +#define CLR_BUF_PO 0x01 + + +/* DMA Interrupt Bit Definitions */ +#define EOT_INT 0x01 +#define NDD_REQ_INT 0x02 +#define SYS_ERR_INT 0x04 + + +/* USB RAM Definitions */ +#define USB_RAM_ADR 0x20080000 /* USB RAM Start Address */ +#define USB_RAM_SZ 0x00004000 /* USB RAM Size (4kB) */ + +/* DMA Endpoint Descriptors */ +#define DD_NISO_CNT 16 /* Non-Iso EP DMA Descr. Count (max. 32) */ +#define DD_ISO_CNT 8 /* Iso EP DMA Descriptor Count (max. 32) */ +#define DD_NISO_SZ (DD_NISO_CNT * 16) /* Non-Iso DMA Descr. Size */ +#define DD_ISO_SZ (DD_ISO_CNT * 20) /* Iso DMA Descriptor Size */ +#define DD_NISO_ADR (USB_RAM_ADR + 128) /* Non-Iso DMA Descr. Address */ +#define DD_ISO_ADR (DD_NISO_ADR + DD_NISO_SZ) /* Iso DMA Descr. Address */ +#define DD_SZ (128 + DD_NISO_SZ + DD_ISO_SZ) /* Descr. Size */ + +/* DMA Buffer Memory Definitions */ +#define DMA_BUF_ADR (USB_RAM_ADR + DD_SZ) /* DMA Buffer Start Address */ +#define DMA_BUF_SZ (USB_RAM_SZ - DD_SZ) /* DMA Buffer Size */ + +/* USB Error Codes */ +#define USB_ERR_PID 0x0001 /* PID Error */ +#define USB_ERR_UEPKT 0x0002 /* Unexpected Packet */ +#define USB_ERR_DCRC 0x0004 /* Data CRC Error */ +#define USB_ERR_TIMOUT 0x0008 /* Bus Time-out Error */ +#define USB_ERR_EOP 0x0010 /* End of Packet Error */ +#define USB_ERR_B_OVRN 0x0020 /* Buffer Overrun */ +#define USB_ERR_BTSTF 0x0040 /* Bit Stuff Error */ +#define USB_ERR_TGL 0x0080 /* Toggle Bit Error */ + +/* USB DMA Status Codes */ +#define USB_DMA_INVALID 0x0000 /* DMA Invalid - Not Configured */ +#define USB_DMA_IDLE 0x0001 /* DMA Idle - Waiting for Trigger */ +#define USB_DMA_BUSY 0x0002 /* DMA Busy - Transfer in progress */ +#define USB_DMA_DONE 0x0003 /* DMA Transfer Done (no Errors)*/ +#define USB_DMA_OVER_RUN 0x0004 /* Data Over Run */ +#define USB_DMA_UNDER_RUN 0x0005 /* Data Under Run (Short Packet) */ +#define USB_DMA_ERROR 0x0006 /* Error */ +#define USB_DMA_UNKNOWN 0xFFFF /* Unknown State */ + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** +#endif // __XHW_usb_H__ + diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xgpio.c b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xgpio.c index 9f3a2c8a..16b5d4c8 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xgpio.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xgpio.c @@ -34,7 +34,7 @@ static xtEventCallback g_psGPIOPinIntAssignTable[64] = //***************************************************************************** void EINT3IntHandler(void) { - unsigned long i = 0; + unsigned char i; //Find and call any interrupt function. for(i = 0; i < 64; i++) @@ -46,6 +46,34 @@ void EINT3IntHandler(void) } } +//***************************************************************************** +// +//! \internal +//! Checks a GPIO base address. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function determines if a GPIO port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef xDEBUG +static xtBoolean +GPIOBaseValid(unsigned long ulPort) +{ + return((ulPort == GPIOA_BASE) || + (ulPort == GPIOB_BASE) || + (ulPort == GPIOC_BASE) || + (ulPort == GPIOD_BASE) || +#if defined(LPC_177x) && defined (LPC_178x) + (ulPort == GPIOF_BASE) || +#endif + (ulPort == GPIOE_BASE)); +} +#endif + //***************************************************************************** // //! \internal @@ -66,10 +94,10 @@ void EINT3IntHandler(void) //! // //***************************************************************************** -static unsigned long PinIDToPos(unsigned long ulPin) +static char PinIDToPos(unsigned long ulPin) { - unsigned long i = 0; - unsigned long ulFlag = 0; + unsigned char i; + unsigned long ulFlag; for(i = 0; i < 32; i++) { @@ -120,7 +148,7 @@ static unsigned long PinIDToPos(unsigned long ulPin) //***************************************************************************** void xGPIODirModeSet(unsigned long ulPort, unsigned long ulPins, unsigned long ulPinIO) { - unsigned long i = 0; + unsigned char i; for(i = 0; i < 32; i++) { @@ -155,6 +183,10 @@ void xGPIODirModeSet(unsigned long ulPort, unsigned long ulPins, unsigned long u //***************************************************************************** unsigned long GPIOPinToPeripheralId(unsigned long ulPort, unsigned long ulPin) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); switch (ulPort) { @@ -183,6 +215,13 @@ unsigned long GPIOPinToPeripheralId(unsigned long ulPort, unsigned long ulPin) return (SYSCTL_PERIPH_GPIOE); break; } +#if defined(LPC_177x) || defined (LPC_178x) + case GPIOF_BASE: + { + return (SYSCTL_PERIPH_GPIOF); + break; + } +#endif } return (0); // Error @@ -199,6 +238,10 @@ unsigned long GPIOPinToPeripheralId(unsigned long ulPort, unsigned long ulPin) //***************************************************************************** unsigned long GPIOPinToPort(unsigned long ulPort, unsigned long ulPin) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); return (ulPort); } @@ -214,7 +257,9 @@ unsigned long GPIOPinToPort(unsigned long ulPort, unsigned long ulPin) //***************************************************************************** unsigned long GPIOPinToPin(unsigned long ulPort, unsigned long ulPin) { - + // Avoid Compiler warning + (void) ulPort; + return (ulPin); } @@ -240,8 +285,21 @@ unsigned long GPIOPinToPin(unsigned long ulPort, unsigned long ulPin) //***************************************************************************** unsigned long xGPIODirModeGet(unsigned long ulPort, unsigned long ulPin) { - //! \todo Finish this function. - return (0); + unsigned long ulRegAddr, ulTmpReg; + + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + +#if defined(LPC_175x) || defined (LPC_176x) + +#elif defined(LPC_177x) || defined (LPC_178x) + ulPin = PinIDToPos(ulPin); + ulRegAddr = (ulPort - GPIOA_BASE) * 4 + ulPin * 4; + ulTmpReg = xHWREG(PIN_CON_BASE + ulRegAddr) & 0x0418; +#endif + return ulTmpReg; } //***************************************************************************** @@ -274,7 +332,6 @@ void xGPIOPinIntCallbackInit(unsigned long ulPort, unsigned long ulPin, { while(1); } - } //***************************************************************************** @@ -295,7 +352,7 @@ void xGPIOPinIntCallbackInit(unsigned long ulPort, unsigned long ulPin, //***************************************************************************** void xGPIOPinIntEnable(unsigned long ulPort, unsigned long ulPins, unsigned long ulIntType) { - unsigned long i = 0; + unsigned char i; for(i = 0; i < 32; i++) { @@ -319,7 +376,7 @@ void xGPIOPinIntEnable(unsigned long ulPort, unsigned long ulPins, unsigned long //***************************************************************************** void xGPIOPinIntDisable(unsigned long ulPort, unsigned long ulPins) { - unsigned long i = 0; + unsigned char i; for(i = 0; i < 32; i++) { @@ -351,7 +408,7 @@ void xGPIOPinIntDisable(unsigned long ulPort, unsigned long ulPins) //***************************************************************************** void xGPIOPinIntClear(unsigned long ulPort, unsigned long ulPins) { - unsigned long i = 0; + unsigned char i; for(i = 0; i < 32; i++) { @@ -380,8 +437,13 @@ void xGPIOPinIntClear(unsigned long ulPort, unsigned long ulPins) //***************************************************************************** unsigned long xGPIOPinRead(unsigned long ulPort, unsigned long ulPins) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + xHWREG(ulPort + FIOMASK) = ~ulPins; - return xHWREG(ulPort + FIOPIN); + return (xHWREG(ulPort + FIOPIN) & ulPins); } //***************************************************************************** @@ -398,10 +460,17 @@ unsigned long xGPIOPinRead(unsigned long ulPort, unsigned long ulPins) // //***************************************************************************** void xGPIOPinWrite(unsigned long ulPort, unsigned long ulPins, - unsigned long ulVal) + unsigned char ucVal) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + xHWREG(ulPort + FIOMASK) = ~ulPins; - xHWREG(ulPort + FIOPIN) = ulVal; + xHWREG(ulPort + FIOSET) = ((ucVal & 1) ? + (xHWREG(ulPort + FIOSET) | ulPins) : + (xHWREG(ulPort + FIOSET) & ~(ulPins))); } //////////////////////////////////////////////////////////////////// @@ -428,9 +497,14 @@ void xGPIOPinWrite(unsigned long ulPort, unsigned long ulPins, //***************************************************************************** void GPIOPinFunCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulCfg) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + unsigned long ulRegAddr = 0; unsigned long ulTmpReg = 0; - +#if defined(LPC_175x) || defined (LPC_176x) switch(ulPort) { case GPIOA_BASE: // Port 0 @@ -477,7 +551,14 @@ void GPIOPinFunCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulCf ulTmpReg &= ~(0x03 << (2*ulPin)); ulTmpReg |= ulCfg; xHWREG(PIN_CON_BASE + ulRegAddr) = ulTmpReg; - +#elif defined(LPC_177x) || defined (LPC_178x) + ulPin = PinIDToPos(ulPin); + ulRegAddr = (ulPort - GPIOA_BASE) * 4 + ulPin * 4; + ulTmpReg = xHWREG(PIN_CON_BASE + ulRegAddr); + ulTmpReg &= ~0x07; + ulTmpReg |= ulCfg; + xHWREG(PIN_CON_BASE + ulRegAddr) |= ulTmpReg; +#endif } //***************************************************************************** @@ -504,10 +585,15 @@ void GPIOPinFunCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulCf //***************************************************************************** void GPIOPinModeCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulCfg) { - unsigned long ulRegAddr = 0; - unsigned long ulTmp = 0; - unsigned long ulTmpReg = 0; - unsigned long ulTmpMode = 0; + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + + unsigned long ulRegAddr, ulTmpReg; +#if defined(LPC_175x) || defined (LPC_176x) + unsigned long ulTmp, ulTmpMode; +#endif /******************* Configure Input/Output Mode ****************/ if(ulCfg & BIT_32_1) // Need to configure Input/Output Mode. @@ -525,6 +611,7 @@ void GPIOPinModeCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulC /***************** Configure pull-up/pull-down Resister ****************/ if(ulCfg & BIT_32_4) // Need to configure Pull-up/Pull-down { +#if defined(LPC_175x) || defined (LPC_176x) switch(ulPort) // { case GPIOA_BASE: @@ -567,12 +654,20 @@ void GPIOPinModeCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulC ulTmpMode = (ulTmpMode >> 2) << (2 * ulTmp); ulTmpReg |= ulTmpMode; xHWREG(PIN_CON_BASE + ulRegAddr) = ulTmpReg; - +#elif defined(LPC_177x) || defined (LPC_178x) + ulPin = PinIDToPos(ulPin); + ulRegAddr = (ulPort - GPIOA_BASE) * 4 + ulPin * 4; + ulTmpReg = xHWREG(PIN_CON_BASE + ulRegAddr); + ulTmpReg &= ~0x18; + ulTmpReg |= ulCfg; + xHWREG(PIN_CON_BASE + ulRegAddr) |= ulTmpReg; +#endif } /************************** Configure OD Mode **************************/ if(ulCfg & BIT_32_6) // Configure OD { +#if defined(LPC_175x) || defined (LPC_176x) switch(ulPort) { case GPIOA_BASE: @@ -610,6 +705,12 @@ void GPIOPinModeCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulC { xHWREG(PIN_CON_BASE + ulRegAddr) &= ~ulPin; } +#elif defined(LPC_177x) || defined (LPC_178x) + ulPin = PinIDToPos(ulPin); + ulRegAddr = (ulPort - GPIOA_BASE) * 4 + ulPin * 4; + xHWREG(PIN_CON_BASE + ulRegAddr) &= ~ BIT_32_10; + xHWREG(PIN_CON_BASE + ulRegAddr) |= ulCfg & BIT_32_10; +#endif } } @@ -625,8 +726,13 @@ void GPIOPinModeCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulC //***************************************************************************** void GPIOPinSet(unsigned long ulPort, unsigned long ulPins) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + xHWREG(ulPort + FIOMASK) =~ulPins; - xHWREG(ulPort + FIOSET) = ulPins; + xHWREG(ulPort + FIOSET) |= ulPins; } //***************************************************************************** @@ -641,6 +747,11 @@ void GPIOPinSet(unsigned long ulPort, unsigned long ulPins) //***************************************************************************** void GPIOPinClr(unsigned long ulPort, unsigned long ulPins) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + xHWREG(ulPort + FIOMASK) =~ulPins; xHWREG(ulPort + FIOCLR) = ulPins; } @@ -657,6 +768,11 @@ void GPIOPinClr(unsigned long ulPort, unsigned long ulPins) //***************************************************************************** void GPIOPinWrite(unsigned long ulPort, unsigned long ulPins, unsigned long ulVal) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + xHWREG(ulPort + FIOMASK) = ~ulPins; if(0 != ulVal) { @@ -680,6 +796,11 @@ void GPIOPinWrite(unsigned long ulPort, unsigned long ulPins, unsigned long ulVa //***************************************************************************** unsigned long GPIOPinRead(unsigned long ulPort, unsigned long ulPin) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + xHWREG(ulPort + FIOMASK) = ~ulPin; return xHWREG(ulPort + FIOPIN); } @@ -695,6 +816,11 @@ unsigned long GPIOPinRead(unsigned long ulPort, unsigned long ulPin) //***************************************************************************** unsigned long GPIOPortRead(unsigned long ulPort) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + xHWREG(ulPort + FIOMASK) = (unsigned long) 0x00; return xHWREG(ulPort + FIOPIN); } @@ -710,6 +836,11 @@ unsigned long GPIOPortRead(unsigned long ulPort) //***************************************************************************** void GPIOPortWrite(unsigned long ulPort, unsigned long ulVal) { + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + xHWREG(ulPort + FIOMASK) = (unsigned long) 0x00; xHWREG(ulPort + FIOPIN) = ulVal; } @@ -730,6 +861,11 @@ void GPIOPortWrite(unsigned long ulPort, unsigned long ulVal) //***************************************************************************** void GPIOPinIntCfg(unsigned long ulPort, unsigned long ulPin, unsigned long ulCfg) { + // + // Check the arguments. + // + xASSERT((ulPort == GPIOA_BASE) || (ulPort == GPIOC_BASE)); + switch(ulPort) { case GPIOA_BASE: // Port 0 @@ -831,6 +967,11 @@ unsigned long GPIOPinIntFlagGet(unsigned long ulPort, unsigned long ulPin) { unsigned long ulResult = 0; + // + // Check the arguments. + // + xASSERT((ulPort == GPIOA_BASE) || (ulPort == GPIOC_BASE)); + switch(ulPort) { case GPIOA_BASE: // Port 0 @@ -884,7 +1025,11 @@ unsigned long GPIOPinIntFlagGet(unsigned long ulPort, unsigned long ulPin) //***************************************************************************** void GPIOPinIntFlagClear(unsigned long ulPort, unsigned long ulPin) { - + // + // Check the arguments. + // + xASSERT((ulPort == GPIOA_BASE) || (ulPort == GPIOC_BASE)); + switch(ulPort) { case GPIOA_BASE: // Port 0 @@ -904,4 +1049,3 @@ void GPIOPinIntFlagClear(unsigned long ulPort, unsigned long ulPin) } } } - diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xgpio.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xgpio.h index fbc3b1b0..b06e2f54 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xgpio.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xgpio.h @@ -45,7 +45,7 @@ // have a C binding. // //***************************************************************************** -#ifdef __cplusplu +#ifdef __cplusplus extern "C" { #endif @@ -515,6 +515,41 @@ extern "C" #define GPE30 GPIOE_BASE, GPIO_PIN_30 #define GPE31 GPIOE_BASE, GPIO_PIN_31 +//! PortF +//! For LPC17xx mcu, Port E is equal to Port 5 +#define GPF0 GPIOF_BASE, GPIO_PIN_0 +#define GPF1 GPIOF_BASE, GPIO_PIN_1 +#define GPF2 GPIOF_BASE, GPIO_PIN_2 +#define GPF3 GPIOF_BASE, GPIO_PIN_3 +#define GPF4 GPIOF_BASE, GPIO_PIN_4 +#define GPF5 GPIOF_BASE, GPIO_PIN_5 +#define GPF6 GPIOF_BASE, GPIO_PIN_6 +#define GPF7 GPIOF_BASE, GPIO_PIN_7 +#define GPF8 GPIOF_BASE, GPIO_PIN_8 +#define GPF9 GPIOF_BASE, GPIO_PIN_9 +#define GPF10 GPIOF_BASE, GPIO_PIN_10 +#define GPF11 GPIOF_BASE, GPIO_PIN_11 +#define GPF12 GPIOF_BASE, GPIO_PIN_12 +#define GPF13 GPIOF_BASE, GPIO_PIN_13 +#define GPF14 GPIOF_BASE, GPIO_PIN_14 +#define GPF15 GPIOF_BASE, GPIO_PIN_15 +#define GPF16 GPIOF_BASE, GPIO_PIN_16 +#define GPF17 GPIOF_BASE, GPIO_PIN_17 +#define GPF18 GPIOF_BASE, GPIO_PIN_18 +#define GPF19 GPIOF_BASE, GPIO_PIN_19 +#define GPF20 GPIOF_BASE, GPIO_PIN_20 +#define GPF21 GPIOF_BASE, GPIO_PIN_21 +#define GPF22 GPIOF_BASE, GPIO_PIN_22 +#define GPF23 GPIOF_BASE, GPIO_PIN_23 +#define GPF24 GPIOF_BASE, GPIO_PIN_24 +#define GPF25 GPIOF_BASE, GPIO_PIN_25 +#define GPF26 GPIOF_BASE, GPIO_PIN_26 +#define GPF27 GPIOF_BASE, GPIO_PIN_27 +#define GPF28 GPIOF_BASE, GPIO_PIN_28 +#define GPF29 GPIOF_BASE, GPIO_PIN_29 +#define GPF30 GPIOF_BASE, GPIO_PIN_30 +#define GPF31 GPIOF_BASE, GPIO_PIN_31 + //***************************************************************************** // //! @} @@ -726,6 +761,41 @@ extern "C" #define PE30 PE30 #define PE31 PE31 +//! PortE +//! For LPC17xx mcu, Port E is equal to Port 4 +#define PF0 PF0 +#define PF1 PF1 +#define PF2 PF2 +#define PF3 PF3 +#define PF4 PF4 +#define PF5 PF5 +#define PF6 PF6 +#define PF7 PF7 +#define PF8 PF8 +#define PF9 PF9 +#define PF10 PF10 +#define PF11 PF11 +#define PF12 PF12 +#define PF13 PF13 +#define PF14 PF14 +#define PF15 PF15 +#define PF16 PF16 +#define PF17 PF17 +#define PF18 PF18 +#define PF19 PF19 +#define PF20 PF20 +#define PF21 PF21 +#define PF22 PF22 +#define PF23 PF23 +#define PF24 PF24 +#define PF25 PF25 +#define PF26 PF26 +#define PF27 PF27 +#define PF28 PF28 +#define PF29 PF29 +#define PF30 PF30 +#define PF31 PF31 + //***************************************************************************** // //! @} @@ -794,6 +864,8 @@ extern "C" #define UART2RX UART2RX #define UART3TX UART3TX #define UART3RX UART3RX +#define UART4TX UART4TX +#define UART4RX UART4RX //! I2C Pin Type #define I2C0SDA I2C0SDA @@ -827,6 +899,10 @@ extern "C" #define SPI0MOSI SPI0MOSI #define SPI0MISO SPI0MISO #define SPI0CS SPI0CS +#define SPI1CLK SPI1CLK +#define SPI1MOSI SPI1MOSI +#define SPI1MISO SPI1MISO +#define SPI1CS SPI1CS //! DAC Pin Type #define DACOUT1 DACOUT1 @@ -1223,7 +1299,7 @@ extern unsigned long xGPIOPinRead(unsigned long ulPort, unsigned long ulPins); // //***************************************************************************** extern void xGPIOPinWrite(unsigned long ulPort, unsigned long ulPins, - unsigned long ucVal); + unsigned char ucVal); //***************************************************************************** // @@ -1845,6 +1921,7 @@ extern void xGPIOPinWrite(unsigned long ulPort, unsigned long ulPins, //! @{ // //***************************************************************************** +#if defined(LPC_175x) && defined (LPC_176x) #define GPIO_PA0_PA0 ((unsigned long)0x00 << 0 ) #define GPIO_PA0_CAN1RX ((unsigned long)0x01 << 0 ) #define GPIO_PA0_UART3TX ((unsigned long)0x02 << 0 ) @@ -2077,6 +2154,343 @@ extern void xGPIOPinWrite(unsigned long ulPort, unsigned long ulPins, #define GPIO_PE29_TX_MCLK ((unsigned long)0x01 << 26) #define GPIO_PE29_TIM_MAT1 ((unsigned long)0x02 << 26) #define GPIO_PE29_UART3RX ((unsigned long)0x03 << 26) + +#elif defined(LPC_177x) && defined (LPC_178x) + +#define GPIO_PA0_PA0 0x00 +#define GPIO_PA0_CAN1RX 0x01 +#define GPIO_PA0_UART3TX 0x02 +#define GPIO_PA0_I2C1SDA 0x03 +#define GPIO_PA0_UART0TX 0x04 +#define GPIO_PA1_PA1 0x00 +#define GPIO_PA1_CAN1TX 0x01 +#define GPIO_PA1_UART3RX 0x02 +#define GPIO_PA1_I2C1SCK 0x03 +#define GPIO_PA1_UART0RX 0x04 +#define GPIO_PA2_PA2 0x00 +#define GPIO_PA2_UART0TX 0x01 +#define GPIO_PA2_UART3TX 0x02 +#define GPIO_PA3_PA3 0x00 +#define GPIO_PA3_UART0RX 0x01 +#define GPIO_PA3_UART3RX 0x02 +#define GPIO_PA4_PA4 0x00 +#define GPIO_PA4_I2SRX_CLK 0x01 +#define GPIO_PA4_CAN2RX 0x02 +#define GPIO_PA4_TIMCCP0 0x03 +#define GPIO_PA5_PA5 0x00 +#define GPIO_PA5_I2SRX_WS 0x01 +#define GPIO_PA5_CAN2TX 0x02 +#define GPIO_PA5_TIMCCP1 0x03 +#define GPIO_PA6_PA6 0x00 +#define GPIO_PA6_I2SRX_SDA 0x01 +#define GPIO_PA6_SPI1CS 0x02 +#define GPIO_PA6_TIM_MAT0 0x03 +#define GPIO_PA6_UART1RTS 0x04 +#define GPIO_PA10_PA10 0x00 +#define GPIO_PA10_UART2TX 0x01 +#define GPIO_PA10_I2C2SDA 0x02 +#define GPIO_PA10_TIM_MAT0 0x03 +#define GPIO_PA11_PA11 0x00 +#define GPIO_PA11_UART2RX 0x01 +#define GPIO_PA11_I2C2SCK 0x02 +#define GPIO_PA11_TIM_MAT1 0x03 +#define GPIO_PA14_PA14 0x00 +#define GPIO_PA14_USBHST2 0x01 +#define GPIO_PA14_SPI1CS 0x02 +#define GPIO_PA14_USBCNT2 0x03 +#define GPIO_PA15_PA15 0x00 +#define GPIO_PA15_UART1TX 0x01 +#define GPIO_PA15_SCK0 0x02 +#define GPIO_PA15_SPI0CLK 0x03 +#define GPIO_PA16_PA16 0x00 +#define GPIO_PA16_UART1RX 0x01 +#define GPIO_PA16_SPI0CS 0x02 +#define GPIO_PA16_SPI0CS 0x03 +#define GPIO_PA17_PA17 0x00 +#define GPIO_PA17_UART1CTS 0x01 +#define GPIO_PA17_MISO0 0x02 +#define GPIO_PA17_SPI0MISO 0x03 +#define GPIO_PA18_PA18 0x00 +#define GPIO_PA18_UART1DCD 0x01 +#define GPIO_PA18_MOSI0 0x02 +#define GPIO_PA18_SPI0MOSI 0x03 +#define GPIO_PA19_PA19 0x00 +#define GPIO_PA19_UART1DSR 0x01 +#define GPIO_PA19_SDCLK 0x02 +#define GPIO_PA19_I2C1SDA 0x03 +#define GPIO_PA20_PA20 0x00 +#define GPIO_PA20_UART1DTR 0x01 +#define GPIO_PA20_I2C1SCK 0x03 +#define GPIO_PA21_PA21 0x00 +#define GPIO_PA21_UART1RI 0x01 +#define GPIO_PA21_CAN1RX 0x03 +#define GPIO_PA22_PA22 0x00 +#define GPIO_PA22_UART1RTS 0x01 +#define GPIO_PA22_CAN1TX 0x03 +#define GPIO_PB0_PB0 0x00 +#define GPIO_PB0_ETH_TXD0 0x01 +#define GPIO_PB1_PB1 0x00 +#define GPIO_PB1_ETH_TXD1 0x01 +#define GPIO_PB1_PWM1 0x03 +#define GPIO_PB2_PB2 0x00 +#define GPIO_PB2_ETH_TXD2 0x01 +#define GPIO_PB2_PWM2 0x03 +#define GPIO_PB3_PB3 0x00 +#define GPIO_PB3_ETH_TXD3 0x01 +#define GPIO_PB4_PB4 0x00 +#define GPIO_PB4_ETH_TX_EN 0x01 +#define GPIO_PB4_TIM_MAT2 0x03 +#define GPIO_PB4_SPI2MISO 0x04 +#define GPIO_PB5_PB5 0x00 +#define GPIO_PB5_ETH_TX_ER 0x01 +#define GPIO_PB5_PWM3 0x03 +#define GPIO_PB6_PB6 0x00 +#define GPIO_PB6_ETH_TX_CLK 0x01 +#define GPIO_PB6_PWM4 0x03 +#define GPIO_PB7_PB7 0x00 +#define GPIO_PB7_ETH_COL 0x01 +#define GPIO_PB7_PWM5 0x03 +#define GPIO_PB8_PB8 0x00 +#define GPIO_PB8_ETH_CRS 0x01 +#define GPIO_PB8_TIM_MAT1 0x03 +#define GPIO_PB8_SPI2CS 0x04 +#define GPIO_PB9_PB9 0x00 +#define GPIO_PB9_ETH_RXD0 0x01 +#define GPIO_PB8_TIM_MAT0 0x03 +#define GPIO_PB10_PB10 0x00 +#define GPIO_PB10_ETH_RXD1 0x01 +#define GPIO_PB10_TIMCCP 0x03 +#define GPIO_PB11_PB11 0x00 +#define GPIO_PB11_ETH_RXD2 0x01 +#define GPIO_PB11_PWM6 0x03 +#define GPIO_PB12_PB12 0x00 +#define GPIO_PB12_ETH_RXD3 0x01 +#define GPIO_PB12_PWM7 0x03 +#define GPIO_PB13_PB13 0x00 +#define GPIO_PB13_ETH_RX_DV 0x01 +#define GPIO_PB14_PB14 0x00 +#define GPIO_PB14_ETH_RX_ER 0x01 +#define GPIO_PB14_TIMCCP 0x03 +#define GPIO_PB15_PB15 0x00 +#define GPIO_PB15_ETH_REF_CLK 0x01 +#define GPIO_PB15_I2C2SDA 0x03 +#define GPIO_PB16_PB16 0x00 +#define GPIO_PB16_ENET_MDC 0x01 +#define GPIO_PB16_I2S_TX_MCLK 0x02 +#define GPIO_PB17_PB17 0x00 +#define GPIO_PB17_ENET_MDIO 0x01 +#define GPIO_PB17_I2S_RX_MCLK 0x02 +#define GPIO_PB18_PB18 0x00 +#define GPIO_PB18_USB_UP_LED 0x01 +#define GPIO_PB18_PWM1 0x02 +#define GPIO_PB18_TIMCCP0 0x03 +#define GPIO_PB19_PB19 0x00 +#define GPIO_PB19_USB_TX_E 0x01 +#define GPIO_PB19_USB_PPWR 0x02 +#define GPIO_PB19_TIMCCP1 0x03 +#define GPIO_PB19_MCOA0 0x04 +#define GPIO_PB19_SPI1SCK 0x05 +#define GPIO_PB20_PB20 0x00 +#define GPIO_PB20_USB_TX_DP 0x01 +#define GPIO_PB20_PWM2 0x02 +#define GPIO_PB20_SPI0CLK 0x03 +#define GPIO_PB21_PB21 0x00 +#define GPIO_PB21_USB_TX_DM 0x01 +#define GPIO_PB21_PWM3 0x02 +#define GPIO_PB21_SPI0CS 0x03 +#define GPIO_PB22_PB22 0x00 +#define GPIO_PB22_USB_RCV 0x01 +#define GPIO_PB22_USB_PWRD 0x02 +#define GPIO_PB22_TIM_MAT0 0x03 +#define GPIO_PB22_SPI1MOSI 0x05 +#define GPIO_PB23_PB23 0x00 +#define GPIO_PB23_USB_RX_DP 0x01 +#define GPIO_PB23_PWM4 0x02 +#define GPIO_PB23_SPI0MISO 0x05 +#define GPIO_PB24_PB24 0x00 +#define GPIO_PB24_USB_RX_DM 0x01 +#define GPIO_PB24_PWM5 0x02 +#define GPIO_PB24_SPI0MOSI 0x05 +#define GPIO_PB25_PB25 0x00 +#define GPIO_PB25_USB_LS 0x01 +#define GPIO_PB25_USB_HST 0x02 +#define GPIO_PB25_TIM_MAT1 0x03 +#define GPIO_PB26_PB26 0x00 +#define GPIO_PB26_USB_SSPND 0x01 +#define GPIO_PB26_PWM6 0x02 +#define GPIO_PB26_TIMCCP0 0x03 +#define GPIO_PB26_SPI1CS 0x05 +#define GPIO_PB27_PB27 0x00 +#define GPIO_PB27_USB_INT 0x01 +#define GPIO_PB27_USB_OVRCR 0x02 +#define GPIO_PB27_TIMCCP1 0x03 +#define GPIO_PB28_PB28 0x00 +#define GPIO_PB28_USB_SCL 0x01 +#define GPIO_PB28_PWM_CAP_CH0 0x02 +#define GPIO_PB28_TIM_MAT0 0x03 +#define GPIO_PB28_SPI0CS 0x05 +#define GPIO_PB29_PB29 0x00 +#define GPIO_PB29_USB_SDA 0x01 +#define GPIO_PB29_PWM_CAP_CH1 0x02 +#define GPIO_PB29_TIM_MAT1 0x03 +#define GPIO_PB29_UART4TX 0x05 +#define GPIO_PC0_PC0 0x00 +#define GPIO_PC0_PWM1 0x01 +#define GPIO_PC0_UART1TX 0x02 +#define GPIO_PC1_PC1 0x00 +#define GPIO_PC1_PWM2 0x01 +#define GPIO_PC1_UART1RX 0x02 +#define GPIO_PC2_PC2 0x00 +#define GPIO_PC2_PWM3 0x01 +#define GPIO_PC2_UART1CTS 0x02 +#define GPIO_PC2_TIM_MAT3 0x03 +#define GPIO_PC3_PC3 0x00 +#define GPIO_PC3_PWM4 0x01 +#define GPIO_PC3_UART1DCD 0x02 +#define GPIO_PC3_TIM_MAT2 0x03 +#define GPIO_PC4_PC4 0x00 +#define GPIO_PC4_PWM5 0x01 +#define GPIO_PC4_UART1DSR 0x02 +#define GPIO_PC4_TIM_MAT1 0x03 +#define GPIO_PC5_PC5 0x00 +#define GPIO_PC5_PWM6 0x01 +#define GPIO_PC5_UART1DTR 0x02 +#define GPIO_PC5_TIM_MAT0 0x03 +#define GPIO_PC6_PC6 0x00 +#define GPIO_PC6_PWM_CAP_CH0 0x01 +#define GPIO_PC6_UART1RI 0x02 +#define GPIO_PC2_TIMCCP0 0x03 +#define GPIO_PC7_PC7 0x00 +#define GPIO_PC7_CAN2RX 0x01 +#define GPIO_PC7_UART1RTS 0x02 +#define GPIO_PC8_PC8 0x00 +#define GPIO_PC8_CAN2TX 0x01 +#define GPIO_PC8_UART2TX 0x02 +#define GPIO_PC8_UART1CTS 0x03 +#define GPIO_PC8_ENET_MDC 0x04 +#define GPIO_PC9_PC9 0x00 +#define GPIO_PC9_USB_CONNECT 0x01 +#define GPIO_PC9_UART2RX 0x02 +#define GPIO_PC9_UART4RX 0x03 +#define GPIO_PC9_ENET_MDIO 0x04 +#define GPIO_PC10_PC10 0x00 +#define GPIO_PC10_EINT0 0x01 +#define GPIO_PC10_NMI 0x02 +#define GPIO_PC11_PC11 0x00 +#define GPIO_PC11_EINT1 0x01 +#define GPIO_PC11_I2STX_CLK 0x03 +#define GPIO_PC12_PC12 0x00 +#define GPIO_PC12_EINT2 0x01 +#define GPIO_PC12_I2STX_WS 0x03 +#define GPIO_PC13_PC13 0x00 +#define GPIO_PC13_EINT3 0x01 +#define GPIO_PC13_I2STX_SDA 0x03 +#define GPIO_PC14_PC14 0x00 +#define GPIO_PC14_EMCCS2 0x01 +#define GPIO_PC14_I2C1SDA 0x02 +#define GPIO_PC14_TIMCCP0 0x03 +#define GPIO_PC15_PC15 0x00 +#define GPIO_PC15_EMCCS3 0x01 +#define GPIO_PC15_I2C1SCL 0x02 +#define GPIO_PC15_TIMCCP1 0x03 +#define GPIO_PC16_PC16 0x00 +#define GPIO_PC16_EMCCAS 0x01 +#define GPIO_PC17_PC17 0x00 +#define GPIO_PC17_EMCRAS 0x01 +#define GPIO_PC18_PC18 0x00 +#define GPIO_PC18_CLK 0x01 +#define GPIO_PC19_PC19 0x00 +#define GPIO_PC19_CLK 0x01 +#define GPIO_PC20_PC20 0x00 +#define GPIO_PC20_EMCDYCS 0x01 +#define GPIO_PC21_PC21 0x00 +#define GPIO_PC21_EMCDYCS 0x01 +#define GPIO_PC22_PC22 0x00 +#define GPIO_PC22_EMCDYCS 0x01 +#define GPIO_PC22_SPI0CLK 0x02 +#define GPIO_PC22_TIM_CAP 0x03 +#define GPIO_PC23_PC23 0x00 +#define GPIO_PC23_EMCDYCS 0x01 +#define GPIO_PC23_SPI0CS 0x02 +#define GPIO_PC23_TIM_CAP 0x03 +#define GPIO_PC24_PC24 0x00 +#define GPIO_PC24_EMCCKE 0x01 +#define GPIO_PC25_PC25 0x00 +#define GPIO_PC25_EMCCKE 0x01 +#define GPIO_PC26_PC26 0x00 +#define GPIO_PC26_EMCCKE 0x01 +#define GPIO_PC26_SPI0MISO 0x02 +#define GPIO_PC26_TIM_MAT0 0x03 +#define GPIO_PC27_PC27 0x00 +#define GPIO_PC27_EMCCKE 0x01 +#define GPIO_PC27_SPI0MOSI 0x02 +#define GPIO_PC27_TIM_MAT1 0x03 +#define GPIO_PC28_PC28 0x00 +#define GPIO_PC28_EMCDQM 0x01 +#define GPIO_PC29_PC29 0x00 +#define GPIO_PC29_EMCDQM 0x01 +#define GPIO_PC30_PC30 0x00 +#define GPIO_PC30_EMCDQM 0x01 +#define GPIO_PC30_I2C2SDA 0x02 +#define GPIO_PC30_TIM_MAT2 0x03 +#define GPIO_PC31_PC31 0x00 +#define GPIO_PC31_EMCDQM 0x01 +#define GPIO_PC31_I2C2SCK 0x02 +#define GPIO_PC31_TIM_MAT3 0x03 +#define GPIO_PD0_PD0 0x00 +#define GPIO_PD1_PD1 0x00 +#define GPIO_PD2_PD2 0x00 +#define GPIO_PD3_PD3 0x00 +#define GPIO_PD4_PD4 0x00 +#define GPIO_PD5_PD5 0x00 +#define GPIO_PD6_PD6 0x00 +#define GPIO_PD7_PD7 0x00 +#define GPIO_PD8_PD8 0x00 +#define GPIO_PD9_PD9 0x00 +#define GPIO_PD10_PD10 0x00 +#define GPIO_PD11_PD11 0x00 +#define GPIO_PD12_PD12 0x00 +#define GPIO_PD13_PD13 0x00 +#define GPIO_PD14_PD14 0x00 +#define GPIO_PD15_PD15 0x00 +#define GPIO_PD16_PD16 0x00 +#define GPIO_PD16_PWM1 0x02 +#define GPIO_PD16_UART1TX 0x03 +#define GPIO_PD17_PD17 0x00 +#define GPIO_PD17_PWM2 0x02 +#define GPIO_PD17_UART1RX 0x03 +#define GPIO_PD18_PD18 0x00 +#define GPIO_PD18_PWM3 0x02 +#define GPIO_PD18_UART1CTS 0x03 +#define GPIO_PD19_PD19 0x00 +#define GPIO_PD19_PWM4 0x02 +#define GPIO_PD19_UART1DCD 0x03 +#define GPIO_PD20_PD20 0x00 +#define GPIO_PD20_PWM5 0x02 +#define GPIO_PD20_UART1DSR 0x03 +#define GPIO_PD21_PD21 0x00 +#define GPIO_PD21_PWM7 0x02 +#define GPIO_PD21_UART1DSR 0x03 + + +#define GPIO_PD25_PD25 0x00 +#define GPIO_PD25_TIM_MAT0 0x02 +#define GPIO_PD25_PWM2 0x03 +#define GPIO_PD26_PD26 0x00 +#define GPIO_PD26_STCLK 0x01 +#define GPIO_PD26_TIM_MAT1 0x02 +#define GPIO_PD26_PWM3 0x03 +#define GPIO_PE28_PE28 0x00 +#define GPIO_PE28_RX_MCLK 0x01 +#define GPIO_PE28_TIM_MAT0 0x02 +#define GPIO_PE28_UART3TX 0x03 +#define GPIO_PE29_PE29 0x00 +#define GPIO_PE29_TX_MCLK 0x01 +#define GPIO_PE29_TIM_MAT1 0x02 +#define GPIO_PE29_UART3RX 0x03 + +#endif + //***************************************************************************** // //! @} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_ints.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_ints.h index 05f10b2f..20a83a46 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_ints.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_ints.h @@ -92,7 +92,7 @@ #define xINT_UART1 INT_UART1 // 22 UART1 Rx and Tx #define xINT_UART2 INT_UART2 // 23 UART2 Rx and Tx #define xINT_UART3 INT_UART3 // 24 UART3 Rx and Tx -#define xINT_PWM0 INT_PWM1 // 25 PWM Generator 1 +#define xINT_PWM1 INT_PWM1 // 25 PWM Generator 1 #define xINT_I2C0 INT_I2C0 // 26 I2C0 Master and Slave #define xINT_I2C1 INT_I2C1 // 27 I2C1 Master and Slave #define xINT_I2C2 INT_I2C2 // 28 I2C2 Master and Slave @@ -105,12 +105,11 @@ #define xINT_EINT1 INT_EINT1 // 35 External Interrupt 1 #define xINT_EINT2 INT_EINT2 // 36 External Interrupt 2 #define xINT_EINT3 INT_EINT3 // 37 External Interrupt 3 -#define xINT_GPIOA INT_EINT3 // 37 GPIO Int0, Share with External Int 3 -#define xINT_GPIOC INT_EINT3 // 37 GPIO Int2, Share with External Int 3 #define xINT_ADC INT_ADC // 38 ADC #define xINT_BOD INT_BOD // 39 Brown Out detect #define xINT_USB INT_USB // 40 USB Controller -#define xINT_CAN0 INT_CAN // 41 CAN 0 +#define xINT_CAN1 INT_CAN // 41 CAN 1 +#define xINT_CAN2 INT_CAN // 41 CAN 2 #define xINT_DMA0 INT_DMA // 42 DMA controller #define xINT_I2S INT_I2S // 43 I2S #define xINT_ETH INT_ETH // 44 Ethernet @@ -119,6 +118,15 @@ #define xINT_QEI INT_QEI // 47 Quadrature Encoder Interface #define xINT_PLL1 INT_PLL1 // 48 PLL1 Lock (Alt PLL) #define xINT_USBACT INT_USBACT // 49 USB Activity Interrupt +#define xINT_UART4 INT_UART4 // 51 UART4 Rx and Tx +#define xINT_SSP2 INT_SSP2 // 52 SSP1 Rx and Tx +#define xINT_LCD INT_LCD // 53 LCD controller +#define xINT_GPIOA INT_GPIO // 54 GPIOA +#define xINT_GPIOB INT_GPIO // 54 GPIOB +#define xINT_GPIOC INT_GPIO // 54 GPIOC +#define xINT_GPIOD INT_GPIO // 54 GPIOD +#define xINT_GPIOE INT_GPIO // 54 GPIOE +#define xINT_PWM0 INT_PWM0 // 55 PWM0 //***************************************************************************** // @@ -199,10 +207,7 @@ #define INT_EINT0 34 // External Interrupt 0 #define INT_EINT1 35 // External Interrupt 1 #define INT_EINT2 36 // External Interrupt 2 -#define INT_EINT3 37 // External Interrupt 3, Share with GPIO -#define INT_GPIO 37 // External Interrupt 3, Share with GPIO -#define INT_GPIOA 37 // External Interrupt 3, Share with GPIO -#define INT_GPIOC 37 // External Interrupt 3, Share with GPIO +#define INT_EINT3 37 // External Interrupt 3 #define INT_ADC 38 // ADC #define INT_BOD 39 // Brown Out detect #define INT_USB 40 // USB Controller @@ -215,14 +220,20 @@ #define INT_QEI 47 // Quadrature Encoder Interface #define INT_PLL1 48 // PLL1 Lock (Alt PLL) #define INT_USBACT 49 // USB Activity Interrupt - +#define INT_CANWAKE 50 // CAN Activity Interrupt +#define INT_UART4 51 // UART4 Rx and Tx +#define INT_SSP2 52 // SSP1 Rx and Tx +#define INT_LCD 53 // LCD controller +#define INT_GPIO 54 // GPIO interrupts +#define INT_PWM0 55 // PWM0 +#define INT_EEPROM 56 // EEPROM //***************************************************************************** // //! \brief Defines for the total number of interrupts. // //***************************************************************************** -#define NUM_INTERRUPTS 51 +#define NUM_INTERRUPTS 57 //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_memmap.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_memmap.h index 9931b4e4..e4f365fe 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_memmap.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_memmap.h @@ -74,8 +74,8 @@ // //***************************************************************************** #define xETH_BASE ETH_BASE -#define xDMA0_BASE DMA_BASE -#define xUSB_BASE USB_BASE +#define xDMA0_BASE DMA0_BASE +#define xUSB_BASE USBD_BASE #define xGPIO_PORTA_BASE GPIOA_BASE #define xGPIO_PORTB_BASE GPIOB_BASE #define xGPIO_PORTC_BASE GPIOC_BASE @@ -86,6 +86,7 @@ #define xTIMER1_BASE TIMER1_BASE #define xUART0_BASE UART0_BASE #define xUART1_BASE UART1_BASE +#define xPWM0_BASE PWM0_BASE #define xPWM1_BASE PWM1_BASE #define xI2C0_BASE I2C0_BASE #define xSPI0_BASE SPI0_BASE @@ -102,7 +103,11 @@ #define xUART2_BASE UART2_BASE #define xUART3_BASE UART3_BASE #define xI2C2_BASE I2C2_BASE +#define xUART4_BASE UART4_BASE +#define xCAN1_BASE CAN1_BASE +#define xCAN2_BASE CAN2_BASE #define xI2S_BASE I2S_BASE +#define xSSP2_BASE SSP2_BASE #define xRIT_BASE RIT_BASE #define xMCPWM_BASE MCPWM_BASE #define xQEI_BASE QEI_BASE @@ -137,60 +142,82 @@ // //***************************************************************************** -#define FLASH_BASE ((unsigned long)0x00000000) -#define SRAM_BASE ((unsigned long)0x20000000) -#define ETH_BASE ((unsigned long)0x50000000) -#define DMA_BASE ((unsigned long)0x50004000) -#define USB_BASE ((unsigned long)0x5000C000) - -#define GPIOA_BASE ((unsigned long)0x2009C000) -#define GPIOB_BASE ((unsigned long)0x2009C020) -#define GPIOC_BASE ((unsigned long)0x2009C040) -#define GPIOD_BASE ((unsigned long)0x2009C060) -#define GPIOE_BASE ((unsigned long)0x2009C080) - -//LPC17nx APB0 (n = 5/6) -#define WDT_BASE ((unsigned long)0x40000000) -#define TIMER0_BASE ((unsigned long)0x40004000) -#define TIMER1_BASE ((unsigned long)0x40008000) -#define UART0_BASE ((unsigned long)0x4000C000) -#define UART1_BASE ((unsigned long)0x40010000) -#define PWM1_BASE ((unsigned long)0x40018000) -#define I2C0_BASE ((unsigned long)0x4001C000) -#define SPI0_BASE ((unsigned long)0x40020000) -#define RTC_BASE ((unsigned long)0x40024000) -#define GPIO_INT_BASE ((unsigned long)0x40028000) -#define PIN_CON_BASE ((unsigned long)0x4002C000) -#define SSP1_BASE ((unsigned long)0x40030000) -#define ADC_BASE ((unsigned long)0x40034000) -#define CAN_AF_RAM_BASE ((unsigned long)0x40038000) -#define CAN_AF_REG_BASE ((unsigned long)0x4003C000) -#define CAN_COMM_BASE ((unsigned long)0x40040000) -#define CAN1_BASE ((unsigned long)0x40044000) -#define CAN2_BASE ((unsigned long)0x40048000) -#define I2C1_BASE ((unsigned long)0x4005C000) - -//LPC17nx APB1 (n = 5/6) -#define SSP0_BASE ((unsigned long)0x40088000) -#define DAC_BASE ((unsigned long)0x4008C000) -#define TIMER2_BASE ((unsigned long)0x40090000) -#define TIMER3_BASE ((unsigned long)0x40094000) -#define UART2_BASE ((unsigned long)0x40098000) -#define UART3_BASE ((unsigned long)0x4009C000) -#define I2C2_BASE ((unsigned long)0x400A0000) -#define I2S_BASE ((unsigned long)0x400A8000) -#define RIT_BASE ((unsigned long)0x400B0000) -#define MCPWM_BASE ((unsigned long)0x400B8000) -#define QEI_BASE ((unsigned long)0x400BC000) -#define SYSCTL_BASE ((unsigned long)0x400FC000) +#define FLASH_BASE 0x00000000 +#define SRAM_BASE 0x20000000 + +#if defined(LPC_175x) || defined (LPC_176x) +//LPC17nx AHB (n = 5/6) +#define ETH_BASE 0x50000000 // Ethernet MAC +#define DMA0_BASE 0x50004000 // General Purpose DMA +#define USBD_BASE 0x5000C000 // USB interface +#define GPIOA_BASE 0x2009C000 // GPIOA +#define GPIOB_BASE 0x2009C020 // GPIOB +#define GPIOC_BASE 0x2009C040 // GPIOC +#define GPIOD_BASE 0x2009C060 // GPIOD +#define GPIOE_BASE 0x2009C080 // GPIOE + +//LPC17nx AHB (n = 7/8) +#elif defined(LPC_177x) || defined (LPC_178x) +#define DMA0_BASE 0x20080000 // General Purpose DMA +#define ETH_BASE 0x20084000 // Ethernet MAC +#define LCD_BASE 0x20088000 // LCD controller +#define USBD_BASE 0x2008C000 // USB interface +#define CRC_BASE 0x20090000 // CRC engine +#define GPIOA_BASE 0x20098000 // GPIOA +#define GPIOB_BASE 0x20098020 // GPIOB +#define GPIOC_BASE 0x20098040 // GPIOC +#define GPIOD_BASE 0x20098060 // GPIOD +#define GPIOE_BASE 0x20098080 // GPIOE +#define GPIOF_BASE 0x200980A0 // GPIOF +#define EMC_BASE 0x2009C000 // External Memory Controller +#endif + +//LPC17nx APB0 (n = 5/6/7/8) +#define WDT_BASE 0x40000000 // Watchdog Timer +#define TIMER0_BASE 0x40004000 // Timer 0 +#define TIMER1_BASE 0x40008000 // Timer 1 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x40010000 // UART1 +#define PWM0_BASE 0x40014000 // PWM0 +#define PWM1_BASE 0x40018000 // PWM1 +#define I2C0_BASE 0x4001C000 // I2C0 +#define SPI0_BASE 0x40020000 // SPI +#define RTC_BASE 0x40024000 // RTC and Event Monitor/Recorder +#define GPIO_INT_BASE 0x40028000 // GPIO interrupts +#define PIN_CON_BASE 0x4002C000 // Pin Connect Block +#define SSP1_BASE 0x40030000 // SSP1 +#define ADC_BASE 0x40034000 // ADC +#define CAN_AF_RAM_BASE 0x40038000 // CAN Acceptance Filter RAM +#define CAN_AF_REG_BASE 0x4003C000 // CAN Acceptance Filter Registers +#define CAN_COMM_BASE 0x40040000 // CAN Common Registers +#define CAN1_BASE 0x40044000 // CAN Controller 1 +#define CAN2_BASE 0x40048000 // CAN Controller 2 +#define I2C1_BASE 0x4005C000 // I2C1 + +//LPC17nx APB1 (n = 5/6/7/8) +#define SSP0_BASE 0x40088000 // SSP0 +#define DAC_BASE 0x4008C000 // DAC +#define TIMER2_BASE 0x40090000 // Timer 2 +#define TIMER3_BASE 0x40094000 // Timer 3 +#define UART2_BASE 0x40098000 // UART2 +#define UART3_BASE 0x4009C000 // UART3 +#define I2C2_BASE 0x400A0000 // I2C2 +#define UART4_BASE 0x400A4000 // UART4 +#define I2S_BASE 0x400A8000 // I2S +#define SSP2_BASE 0x400AC000 // SSP2 +#define RIT_BASE 0x400B0000 // Repetitive interrupt timer +#define MCPWM_BASE 0x400B8000 // Motor control PWM +#define QEI_BASE 0x400BC000 // Quadrature Encoder Interface +#define SDC_BASE 0x400C0000 // SD card interface +#define SYSCTL_BASE 0x400FC000 // System control //Core components -#define ITM_BASE ((unsigned long)0xE0000000) -#define DWT_BASE ((unsigned long)0xE0001000) -#define FPB_BASE ((unsigned long)0xE0002000) -#define NVIC_BASE ((unsigned long)0xE000E000) -#define TPIU_BASE ((unsigned long)0xE0040000) -#define COREDEBUG_BASE ((unsigned long)0xE000EDF0) +#define ITM_BASE 0xE0000000 +#define DWT_BASE 0xE0001000 +#define FPB_BASE 0xE0002000 +#define NVIC_BASE 0xE000E000 +#define TPIU_BASE 0xE0040000 +#define COREDEBUG_BASE 0xE000EDF0 //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_sysctl.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_sysctl.h index de7bad41..ec9a904a 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_sysctl.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xhw_sysctl.h @@ -51,10 +51,25 @@ #include "xhw_types.h" #include "xhw_memmap.h" -#define LPC_176x +//#define LPC_176x //! Detect MCU Type. -#if defined(LPC_175x) || defined (LPC_176x) +#if defined(LPC1751) || defined(LPC1752) || defined(LPC1754) || \ + defined(LPC1756) || defined(LPC1758) || defined(LPC1759) +#define LPC_175x +#endif +#if defined(LPC1763) || defined(LPC1764) || defined(LPC1765) || defined(LPC1766) || \ + defined(LPC1767) || defined(LPC1768) || defined(LPC1769) +#define LPC_176x +#endif +#if defined(LPC1774) || defined(LPC1776) || defined(LPC1777) || defined(LPC1778) +#define LPC_177x +#endif +#if defined(LPC1785) || defined(LPC1786) || defined(LPC1787) || defined(LPC1788) +//#define LPC_178x +#endif + +#if defined(LPC_175x) || defined (LPC_176x) || defined(LPC_177x) || defined (LPC_178x) #else #error Please select your LPC MCU first! \ This value can be one of the following value: \ @@ -135,9 +150,6 @@ //! External Memory Controller Clock Selection #define EMCCLKSEL (SYSCTL_BASE + (unsigned long)0x100) -//! CPU Clock Selection -#define CCLKCFG (SYSCTL_BASE + (unsigned long)0x104) - //! CPU Clock Selection #define CCLKSEL (SYSCTL_BASE + (unsigned long)0x104) @@ -365,11 +377,16 @@ #elif defined(LPC_177x) | defined(LPC_178x) -#define PLLSTAT_MSEL_M BIT_MASK(32, 4, 0) -#define PLLSTAT_PSEL_M BIT_MASK(32, 6, 5) -#define PLLSTAT_PLLE_STAT BIT_32_8 -#define PLLSTAT_PLOCK BIT_32_10 +#define PLL0STAT_MSEL_M BIT_MASK(32, 4, 0) +#define PLL0STAT_PSEL_M BIT_MASK(32, 6, 5) +#define PLL0STAT_PLLE_STAT BIT_32_8 +#define PLL0STAT_PLOCK BIT_32_10 +#define PLL1STAT_MSEL_M BIT_MASK(32, 4, 0) +#define PLL1STAT_PSEL_M BIT_MASK(32, 6, 5) +#define PLL1STAT_PLLE_STAT BIT_32_8 +#define PLL1STAT_PLOCK BIT_32_10 + #endif //***************************************************************************** @@ -578,7 +595,16 @@ //***************************************************************************** #if defined(LPC_175x) | defined(LPC_176x) //! Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. -#define CCLKCFG_CCLKSEL_M BIT_MASK(32, 7, 0) +#define CCLKSEL_CCLKSEL_M BIT_MASK(32, 7, 0) +#endif + +#if defined(LPC_177x) | defined(LPC_178x) +//! Selects the divide value for creating the CPU clock (CCLK) from the selected +//! clock source. +#define CCLKSEL_CCLKSEL_M BIT_MASK(32, 4, 0) + +//! Selects the input clock for the CPU clock divider. +#define CCLKSEL_CCLKSEL BIT_32_8 #endif //***************************************************************************** // @@ -593,15 +619,7 @@ //! @{ // //***************************************************************************** -#if defined(LPC_177x) | defined(LPC_178x) - -//! Selects the divide value for creating the CPU clock (CCLK) from the selected -//! clock source. -#define CCLKSEL_CCLKDIV BIT_MASK(32, 4, 0) -//! Selects the input clock for the CPU clock divider. -#define CCLKSEL_CCLKSEL BIT_32_8 -#endif //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xspi.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xspi.h index 491a10c3..46bd3d8b 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xspi.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xspi.h @@ -447,7 +447,7 @@ extern "C" // //***************************************************************************** #define xSPIConfigSet(ulBase, ulBitRate, ulConfig) \ - SPICfg(lBase, ulBitRate, ulConfig) + SPICfg(ulBase, ulBitRate, ulConfig) //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xsysctl.c b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xsysctl.c index d53b94d0..0c40f052 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xsysctl.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xsysctl.c @@ -45,9 +45,7 @@ #include "xdebug.h" #include "xsysctl.h" -static unsigned long PLLMNCal(unsigned long Fin, - unsigned long Fout, unsigned long * pM, unsigned long *pN, unsigned long *pDiv); - +static unsigned long s_ulExtClockMHz = 12000000; static unsigned long g_ulSystemClk = 0; // System Clock frequency static unsigned long g_ulAHBClk = 0; // AHB Clock frequency //static unsigned long g_ulAPB1Clk = 0; // APB1 Clock frequency @@ -75,39 +73,40 @@ tPeripheralTable; static const tPeripheralTable g_pPeripherals[] = { - { xTIMER0_BASE , xSYSCTL_PERIPH_TIMER0 , 0 }, - { xTIMER1_BASE , xSYSCTL_PERIPH_TIMER1 , 0 }, - { xUART0_BASE , xSYSCTL_PERIPH_UART0 , 0 }, - { xUART1_BASE , xSYSCTL_PERIPH_UART1 , 0 }, - { xPWM1_BASE , xSYSCTL_PERIPH_PWM1 , 0 }, - { xI2C0_BASE , xSYSCTL_PERIPH_I2C0 , 0 }, - { xSPI0_BASE , xSYSCTL_PERIPH_SPI , 0 }, - { xRTC_BASE , xSYSCTL_PERIPH_RTC , 0 }, - { xSSP1_BASE , xSYSCTL_PERIPH_SSP1 , 0 }, - { xADC0_BASE , xSYSCTL_PERIPH_ADC0 , 0 }, - { xCAN1_BASE , xSYSCTL_PERIPH_CAN1 , 0 }, - { xCAN2_BASE , xSYSCTL_PERIPH_CAN2 , 0 }, - { xGPIO_PORTA_BASE , xSYSCTL_PERIPH_GPIOA , 0 }, - { xGPIO_PORTB_BASE , xSYSCTL_PERIPH_GPIOB , 0 }, - { xGPIO_PORTC_BASE , xSYSCTL_PERIPH_GPIOC , 0 }, - { xGPIO_PORTD_BASE , xSYSCTL_PERIPH_GPIOD , 0 }, - { xGPIO_PORTE_BASE , xSYSCTL_PERIPH_GPIOE , 0 }, - { xRIT_BASE , xSYSCTL_PERIPH_RIT , 0 }, - { xMCPWM_BASE , xSYSCTL_PERIPH_MCPWM , 0 }, - { xQEI_BASE , xSYSCTL_PERIPH_QEI , 0 }, - { xI2C1_BASE , xSYSCTL_PERIPH_I2C1 , 0 }, - { xSSP0_BASE , xSYSCTL_PERIPH_SSP0 , 0 }, - { xTIMER2_BASE , xSYSCTL_PERIPH_TIMER2 , 0 }, - { xTIMER3_BASE , xSYSCTL_PERIPH_TIMER3 , 0 }, - { xUART2_BASE , xSYSCTL_PERIPH_UART2 , 0 }, - { xUART3_BASE , xSYSCTL_PERIPH_UART3 , 0 }, - { xI2C2_BASE , xSYSCTL_PERIPH_I2C2 , 0 }, - { xI2S_BASE , xSYSCTL_PERIPH_I2S , 0 }, - { xDMA0_BASE , xSYSCTL_PERIPH_DMA , 0 }, - { xETH_BASE , xSYSCTL_PERIPH_ETH , 0 }, - { xUSB_BASE , xSYSCTL_PERIPH_USB , 0 }, - { 0 , 0 , 0 }, - + { xTIMER0_BASE , xSYSCTL_PERIPH_TIMER0 , xINT_TIMER0 }, + { xTIMER1_BASE , xSYSCTL_PERIPH_TIMER1 , xINT_TIMER1 }, + { xUART0_BASE , xSYSCTL_PERIPH_UART0 , xINT_UART0 }, + { xUART1_BASE , xSYSCTL_PERIPH_UART1 , xINT_UART1 }, + { xPWM0_BASE , xSYSCTL_PERIPH_PWM0 , xINT_PWM0 }, + { xPWM1_BASE , xSYSCTL_PERIPH_PWM1 , xINT_PWM1 }, + { xI2C0_BASE , xSYSCTL_PERIPH_I2C0 , xINT_I2C0 }, + { xSPI0_BASE , xSYSCTL_PERIPH_SPI , xINT_SPI0 }, + { xRTC_BASE , xSYSCTL_PERIPH_RTC , xINT_RTC }, + { xSSP1_BASE , xSYSCTL_PERIPH_SSP1 , xINT_SSP1 }, + { xADC0_BASE , xSYSCTL_PERIPH_ADC0 , xINT_ADC }, + { xCAN1_BASE , xSYSCTL_PERIPH_CAN1 , xINT_CAN1 }, + { xCAN2_BASE , xSYSCTL_PERIPH_CAN2 , xINT_CAN2 }, + { xGPIO_PORTA_BASE , xSYSCTL_PERIPH_GPIOA , xINT_GPIOA }, + { xGPIO_PORTB_BASE , xSYSCTL_PERIPH_GPIOB , xINT_GPIOB }, + { xGPIO_PORTC_BASE , xSYSCTL_PERIPH_GPIOC , xINT_GPIOC }, + { xGPIO_PORTD_BASE , xSYSCTL_PERIPH_GPIOD , xINT_GPIOD }, + { xGPIO_PORTE_BASE , xSYSCTL_PERIPH_GPIOE , xINT_GPIOE }, + { xRIT_BASE , xSYSCTL_PERIPH_RIT , 0 }, + { xMCPWM_BASE , xSYSCTL_PERIPH_MCPWM , 0 }, + { xQEI_BASE , xSYSCTL_PERIPH_QEI , 0 }, + { xI2C1_BASE , xSYSCTL_PERIPH_I2C1 , xINT_I2C1 }, + { xSSP0_BASE , xSYSCTL_PERIPH_SSP0 , xINT_SSP0 }, + { xTIMER2_BASE , xSYSCTL_PERIPH_TIMER2 , xINT_TIMER2 }, + { xTIMER3_BASE , xSYSCTL_PERIPH_TIMER3 , xINT_TIMER3 }, + { xUART2_BASE , xSYSCTL_PERIPH_UART2 , xINT_UART2 }, + { xUART3_BASE , xSYSCTL_PERIPH_UART3 , xINT_UART3 }, + { xI2C2_BASE , xSYSCTL_PERIPH_I2C2 , xINT_I2C2 }, + { xUART4_BASE , xSYSCTL_PERIPH_UART4 , xINT_UART4 }, + { xI2S_BASE , xSYSCTL_PERIPH_I2S , xINT_I2S }, + { xDMA0_BASE , xSYSCTL_PERIPH_DMA , xINT_DMA0 }, + { xETH_BASE , xSYSCTL_PERIPH_ETH , xINT_ETH }, + { xUSB_BASE , xSYSCTL_PERIPH_USB , xINT_USB }, + { 0 , 0 , 0 }, }; //***************************************************************************** @@ -289,12 +288,12 @@ SysCtlDelay(unsigned long ulCount) void SysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig) { - unsigned long ulTmpReg = 0; // Temporary register - unsigned long ulRes = 0; // Store Result value - unsigned long ulM = 0; // PLL Multiplier - unsigned long ulN = 0; // PLL Divider - unsigned long ulDiv = 0; // System clock divider - unsigned long ulFin = 0; // Input Clock frequency + unsigned long ulTmpReg; // Temporary register + unsigned long ulRes; // Store Result value + unsigned long ulM; // PLL Multiplier + unsigned long ulN; // PLL Divider + unsigned long ulDiv; // System clock divider + unsigned long ulFin; // Input Clock frequency /************** Check input parameters valid ********************/ // ulSysClk clock range: 0 --> 12MHz @@ -315,7 +314,6 @@ void SysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig) // Need Enable Main Oscillator ? if(ulConfig & SYSCTL_OSC_MAIN) // Enable Main Osc { - // Get Input Frequency (unit: Hz) ulTmpReg = (ulConfig & SYSCTL_XTAL_nMHZ_MASK) * 1000000; @@ -390,7 +388,6 @@ void SysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig) // Get Input Frequency (unit: Hz) // For IRC, there is 4MHz ulFin = 4 * 1000000; - } // @@ -406,6 +403,7 @@ void SysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig) // //Do Nothing Here // } + s_ulExtClockMHz = ulFin; ulRes = PLLMNCal(ulFin, ulSysClk, &ulM, &ulN, &ulDiv); if(!ulRes) // Configure Failure { @@ -415,8 +413,8 @@ void SysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig) // Check PLL Enable/Connect Status // if Enable and Connect, then disconnect it. // At last, Reconfigure PLL and connect to system clock. - - // PLL Connected ? +#if defined(LPC_175x) && defined (LPC_176x) + // PLL0 Connected ? ulTmpReg = xHWREG(PLL0STAT); if(ulTmpReg & PLL0STAT_PLLC_STAT) // Connected to System Clock { @@ -426,8 +424,8 @@ void SysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig) xHWREG(PLL0CON) = ulTmpReg; // Write key to PLL Feed register - xHWREG(PLL0FEED) = (unsigned long)0xAA; - xHWREG(PLL0FEED) = (unsigned long)0x55; + xHWREG(PLL0FEED) = 0xAA; + xHWREG(PLL0FEED) = 0x55; // waiting for disconnect do @@ -437,19 +435,20 @@ void SysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig) }while(ulTmpReg); } +#endif - // PLL Enable ? + // PLL0 Enable ? ulTmpReg = xHWREG(PLL0STAT); if(ulTmpReg & PLL0STAT_PLLE_STAT) // PLL Have Been Enabled, we need to Disable it. { - // Disable PLL + // Disable PLL0 ulTmpReg = xHWREG(PLL0CON); ulTmpReg &= ~PLL0CON_PLLE; xHWREG(PLL0CON) = ulTmpReg; - // Write key to PLL Feed register - xHWREG(PLL0FEED) = (unsigned long)0xAA; - xHWREG(PLL0FEED) = (unsigned long)0x55; + // Write key to PLL0 Feed register + xHWREG(PLL0FEED) = 0xAA; + xHWREG(PLL0FEED) = 0x55; // Waitting for Disable do @@ -458,65 +457,91 @@ void SysCtlClockSet(unsigned long ulSysClk, unsigned long ulConfig) ulTmpReg &= PLL0STAT_PLLE_STAT; }while(ulTmpReg); } - - xHWREG(CCLKCFG) = (ulDiv - 1); - xHWREG(PCLKSEL0) = (unsigned long)0x00; // APB clock is equal to AHB/4 - xHWREG(PCLKSEL1) = (unsigned long)0x00; - - // Updata private clock data. - g_ulSystemClk = ulSysClk; - g_ulAHBClk = ulSysClk; - //g_ulAPB1Clk = ulSysClk/4; - //g_ulAPB2Clk = g_ulAPB1Clk; - - // Configure PLL Multiplier/Divider + + // Configure PLL0 Multiplier/Divider ulM -= 1; ulN -= 1; ulTmpReg = (ulN << PLL0CFG_PSEL_S) | ulM; - xHWREG(PLL0CFG) = ulTmpReg; - - // Write key to PLL Feed register - xHWREG(PLL0FEED) = (unsigned long)0xAA; - xHWREG(PLL0FEED) = (unsigned long)0x55; + xHWREG(PLL0CFG) = 0x09; //ulTmpReg; - //ReEnable PLL and Wait Locked + //ReEnable PLL0 and Wait Locked ulTmpReg = xHWREG(PLL0CON); ulTmpReg |= PLL0CON_PLLE; xHWREG(PLL0CON) = ulTmpReg; - // Write key to PLL Feed register - xHWREG(PLL0FEED) = (unsigned long)0xAA; - xHWREG(PLL0FEED) = (unsigned long)0x55; + // Write key to PLL0 Feed register + xHWREG(PLL0FEED) = 0xAA; + xHWREG(PLL0FEED) = 0x55; - // Waitting for Enable + // Waitting for PLL0 Enable and Locked do { ulTmpReg = xHWREG(PLL0STAT); - ulTmpReg &= PLL0STAT_PLLE_STAT; + ulTmpReg &= (PLL0STAT_PLLE_STAT | PLL0STAT_PLOCK); }while(ulTmpReg == 0); - // Waitting for Locked + // + //! Configure PLL1 Multiplier/Divider for USB Clock + // + xHWREG(PLL1CFG) = 0x23; + + //ReEnable PLL1 and Wait Locked + ulTmpReg = xHWREG(PLL1CON); + ulTmpReg |= PLL1CON_PLLE; + xHWREG(PLL1CON) = ulTmpReg; + + // Write key to PLL1 Feed register + xHWREG(PLL1FEED) = 0xAA; + xHWREG(PLL1FEED) = 0x55; + + // Waitting for PLL1 Enable do { - ulTmpReg = xHWREG(PLL0STAT); - ulTmpReg &= PLL0STAT_PLOCK; + ulTmpReg = xHWREG(PLL1STAT); + ulTmpReg &= PLL1STAT_PLLE_STAT ; }while(ulTmpReg == 0); - + + // Waitting for PLL1 Locked + do + { + ulTmpReg = xHWREG(PLL1STAT); + ulTmpReg &= PLL1STAT_PLOCK; + }while(ulTmpReg == 0); + +#if defined(LPC_175x) || defined (LPC_176x) // Connect It ulTmpReg = xHWREG(PLL0CON); ulTmpReg |= PLL0CON_PLLC; xHWREG(PLL0CON) = ulTmpReg; // Write key to PLL Feed register - xHWREG(PLL0FEED) = (unsigned long)0xAA; - xHWREG(PLL0FEED) = (unsigned long)0x55; - + xHWREG(PLL0FEED) = 0xAA; + xHWREG(PLL0FEED) = 0x55; + // Waitting for Enable do { ulTmpReg = xHWREG(PLL0STAT); ulTmpReg &= PLL0STAT_PLLC_STAT; }while(ulTmpReg == 0); +#endif + + // Setup Clock Divider + xHWREG(CCLKSEL) = (1<<8)|(ulDiv - 1); + + // Select PLL1 for USB clock and Setup USB Clock Divider + xHWREG(USBCLKSEL) = 0x01|(0x02 << 8); + + // EMC Clock Selection + xHWREG(EMCCLKSEL) = 0x01; + + // Peripheral Clock Selection, APB clock is equal to AHB/2 +#if defined(LPC_177x) | defined(LPC_178x) + xHWREG(PCLKSEL) = 0x02; +#else + xHWREG(PCLKSEL0) = (unsigned long)0x00; + xHWREG(PCLKSEL1) = (unsigned long)0x00; +#endif } //***************************************************************************** @@ -591,7 +616,6 @@ void SysCtlExtIntCfg(unsigned long ulPin, unsigned long ulCfg) // Write back to mode/polar register xHWREG(EXTMODE) = ulTmpReg1; // Mode register xHWREG(EXTPOLAR) = ulTmpReg2; // Polar register - } //***************************************************************************** @@ -678,11 +702,8 @@ void SysCtlExtIntFlagClear(unsigned long ulFlag) xASSERT( (ulFlag & EXT_INT_MASK) != 0 ); xHWREG(EXTINT) |= ulFlag; - } - - //***************************************************************************** // //! \brief Get the reset source flag. @@ -939,6 +960,7 @@ unsigned long SysCtlPeripheralClockGet(unsigned long ulPeri) //! - \ref SYSCTL_PERIPH_TIMER1 //! - \ref SYSCTL_PERIPH_UART0 //! - \ref SYSCTL_PERIPH_UART1 +//! - \ref SYSCTL_PERIPH_PWM0 //! - \ref SYSCTL_PERIPH_PWM1 //! - \ref SYSCTL_PERIPH_I2C0 //! - \ref SYSCTL_PERIPH_SPI @@ -962,6 +984,7 @@ unsigned long SysCtlPeripheralClockGet(unsigned long ulPeri) //! - \ref SYSCTL_PERIPH_UART2 //! - \ref SYSCTL_PERIPH_UART3 //! - \ref SYSCTL_PERIPH_I2C2 +//! - \ref SYSCTL_PERIPH_UART4 //! - \ref SYSCTL_PERIPH_I2S //! - \ref SYSCTL_PERIPH_GPDMA //! - \ref SYSCTL_PERIPH_ETH @@ -974,7 +997,6 @@ unsigned long SysCtlPeripheralClockGet(unsigned long ulPeri) //***************************************************************************** void SysCtlPeripheralReset(unsigned long ulPeripheral) { - // Note: Not for LPC 17nx (n=5/6) #if defined(LPC_175x) | defined(LPC_176x) @@ -1261,7 +1283,14 @@ unsigned long SysCtlPeripheraIntNumGet(unsigned long ulPeripheralBase) //***************************************************************************** unsigned long SysCtlClockGet(void) { - return (g_ulSystemClk); + //return (g_ulSystemClk); + unsigned long ulM, ulP, ulDiv; + unsigned long ulTmpReg = xHWREG(PLL0CFG); + ulM = (ulTmpReg & 0x1F) + 1; + ulP = ((ulTmpReg & PLL0CFG_PSEL_M) >> PLL0CFG_PSEL_S) + 1; + ulDiv = xHWREG(CCLKSEL) & 0x1F; + return ((s_ulExtClockMHz * ulM) / (ulP * ulDiv)); + //return (s_ulExtClockMHz * ((ulTmpReg & 0x1F) + 1) / ((((ulTmpReg&PLL0CFG_PSEL_M)>>PLL0CFG_PSEL_S)+1) * (xHWREG(CCLKSEL) & 0x1F))); } //***************************************************************************** diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xsysctl.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xsysctl.h index b9d98eb7..ca126bad 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xsysctl.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xsysctl.h @@ -152,6 +152,9 @@ extern "C" //! UART 1 #define xSYSCTL_PERIPH_UART1 SYSCTL_PERIPH_UART1 +//! PWM 0 +#define xSYSCTL_PERIPH_PWM0 SYSCTL_PERIPH_PWM0 + //! PWM 1 #define xSYSCTL_PERIPH_PWM1 SYSCTL_PERIPH_PWM1 @@ -221,6 +224,9 @@ extern "C" //! I2C 2 #define xSYSCTL_PERIPH_I2C2 SYSCTL_PERIPH_I2C2 +//! UART 4 +#define xSYSCTL_PERIPH_UART4 SYSCTL_PERIPH_UART4 + //! I2S #define xSYSCTL_PERIPH_I2S SYSCTL_PERIPH_I2S @@ -799,6 +805,8 @@ extern "C" //! \ref xUART2_BASE //! \ref xUART3_BASE //! \ref xI2C2_BASE +//! \ref xCAN1_BASE +//! \ref xCAN2_BASE //! \ref xI2S_BASE //! \ref xRIT_BASE //! \ref xMCPWM_BASE @@ -851,6 +859,8 @@ extern "C" //! \ref xUART2_BASE //! \ref xUART3_BASE //! \ref xI2C2_BASE +//! \ref xCAN1_BASE +//! \ref xCAN2_BASE //! \ref xI2S_BASE //! \ref xRIT_BASE //! \ref xMCPWM_BASE @@ -1416,6 +1426,9 @@ extern "C" // //***************************************************************************** +//! LCD controller +#define SYSCTL_PERIPH_LCD 0 + //! Timer 0 #define SYSCTL_PERIPH_TIMER0 1 @@ -1428,14 +1441,20 @@ extern "C" //! UART 1 #define SYSCTL_PERIPH_UART1 4 +//! PWM 0 +#define SYSCTL_PERIPH_PWM0 5 + //! PWM 1 #define SYSCTL_PERIPH_PWM1 6 //! I2C 0 #define SYSCTL_PERIPH_I2C0 7 -//! The SPI +//! The SPI (only for LPC175x/6x) #define SYSCTL_PERIPH_SPI 8 + +//! The UART4 (only for LPC177x/8x) +#define SYSCTL_PERIPH_UART4 8 //! RTC #define SYSCTL_PERIPH_RTC 9 @@ -1443,6 +1462,9 @@ extern "C" //! SSP 1 #define SYSCTL_PERIPH_SSP1 10 +//! External Memory Controller +#define SYSCTL_PERIPH_EMC 11 + //! ADC #define SYSCTL_PERIPH_ADC 12 @@ -1500,6 +1522,9 @@ extern "C" //! I2S #define SYSCTL_PERIPH_I2S 27 +//! SD Card interface +#define SYSCTL_PERIPH_SDC 28 + //! General Purpose DMA #define SYSCTL_PERIPH_GPDMA 29 @@ -1523,6 +1548,11 @@ extern "C" //! GPIO E --> P4 #define SYSCTL_PERIPH_GPIOE 36 + +#if defined(LPC_177x) || defined (LPC_178x) +//! GPIO F --> P5 +#define SYSCTL_PERIPH_GPIOF 37 +#endif //***************************************************************************** // //! @} @@ -1704,6 +1734,11 @@ extern unsigned long SysCtlPeripheralClockGet(unsigned long ulPeri); extern void SysCtlPeripheralReset(unsigned long ulPeripheral); extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset2(unsigned long ulPeripheralBase); +extern void SysCtlPeripheralEnable2(unsigned long ulPeripheralBase); +extern void SysCtlPeripheralDisable2(unsigned long ulPeripheral); + +extern unsigned long SysCtlPeripheraIntNumGet(unsigned long ulPeripheralBase); extern unsigned long SysCtlClockGet(void); extern unsigned long SysCtlHClockGet(void); diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xusb.c b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xusb.c new file mode 100644 index 00000000..dce2b3c6 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xusb.c @@ -0,0 +1,803 @@ +//***************************************************************************** +// +//! \file xusb.c +//! \brief Driver for the USB driver. +//! \version V2.2.1.0 +//! \date 09/20/2014 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2014, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +#include "xhw_types.h" +#include "xhw_ints.h" +#include "xcore.h" +#include "xhw_memmap.h" +#include "hw_usb.h" +#include "xhw_gpio.h" +#include "xusb.h" +#include "usb_com_config.h" +#include "cox_config.h" +#include "xhw_types.h" + +xtBoolean xUSBReset (void); +xtBoolean xUSBSetAddress (unsigned long ulAddr); + +static xtEventCallback g_pfnUSBEndPointEvent[USB_LOGIC_EP_NUM] = {0}; + +static xtEventCallback g_pfnUSBWakeUpEvent = NULL; +static xtEventCallback g_pfnUSBResetEvent = NULL; +static xtEventCallback g_pfnUSBSuspendEvent = NULL; +static xtEventCallback g_pfnUSBResumeEvent = NULL; +static xtEventCallback g_pfnUSBErrorEvent = NULL; +static xtEventCallback g_pfnUSBSOFEvent = NULL; + +static void *vpUSBEndPointEventData[USB_LOGIC_EP_NUM]={NULL}; + +#define EP_MSK_CTRL 0x0001 /* Control Endpoint Logical Address Mask */ +#define EP_MSK_BULK 0xC924 /* Bulk Endpoint Logical Address Mask */ +#define EP_MSK_INT 0x4492 /* Interrupt Endpoint Logical Address Mask */ +#define EP_MSK_ISO 0x1248 /* Isochronous Endpoint Logical Address Mask */ + +//***************************************************************************** +// +//! \brief Get Endpoint Physical Address +//! +//! \param ulEPNum Endpoint Number. +//! ulEPNum.0..3: Address +//! ulEPNum.7: Dir +//! +//! \return Endpoint Physical Address. +// +//***************************************************************************** +unsigned long EndPointAddressGet (unsigned long ulEPNum) { + unsigned long ulVal; + + ulVal = (ulEPNum & 0x0F) << 1; + if (ulEPNum & 0x80) { + ulVal += 1; + } + return (ulVal); +} + +/* + * Write Command + * Parameters: cmd: Command + * Return Value: None + */ +//***************************************************************************** +// +//! \brief Write Command +//! +//! \param cmd: Command +//! +//! \return None +// +//***************************************************************************** +void USBCommandCodeWrite (unsigned long cmd) { + + xHWREG(USB_DEV_INT_CLR) = CCEMTY_INT; + xHWREG(USB_CMD_CODE) = cmd; + while ((xHWREG(USB_DEV_INT_ST) & CCEMTY_INT) == 0); +} + +void USBCommandDataWrite (unsigned long cmd, unsigned long val) { + + xHWREG(USB_DEV_INT_CLR) = CCEMTY_INT; + xHWREG(USB_CMD_CODE) = cmd; + while ((xHWREG(USB_DEV_INT_ST) & CCEMTY_INT) == 0); + xHWREG(USB_DEV_INT_CLR) = CCEMTY_INT; + xHWREG(USB_CMD_CODE) = val; + while ((xHWREG(USB_DEV_INT_ST) & CCEMTY_INT) == 0); +} + +void USBCommandEndPointWrite (unsigned long EPNum, unsigned long cmd){ + + xHWREG(USB_DEV_INT_ST) = CCEMTY_INT; + xHWREG(USB_CMD_CODE)= CMD_SEL_EP(EndPointAddressGet(EPNum)); + while ((xHWREG(USB_DEV_INT_ST) & CCEMTY_INT) == 0); + xHWREG(USB_DEV_INT_CLR) = CCEMTY_INT; + xHWREG(USB_CMD_CODE) = cmd; + while ((xHWREG(USB_DEV_INT_ST) & CCEMTY_INT) == 0); +} +unsigned long USBCommandDataRead (unsigned long cmd) { + + xHWREG(USB_DEV_INT_CLR) = CCEMTY_INT | CDFULL_INT; + xHWREG(USB_CMD_CODE) = cmd; + while ((xHWREG(USB_DEV_INT_ST) & CDFULL_INT) == 0); + return (xHWREG(USB_CMD_DATA)); +} + +xtBoolean xUSBIOClkConfig(void) +{ + xHWREG(SCS) = 0x20; + if (xHWREG(SCS) & (1 << 5)) { /* If Main Oscillator is enabled */ + while ((xHWREG(SCS) & (1<<6)) == 0);/* Wait for Oscillator to be ready */ + } + + xHWREG(CCLKCFG) = 0x07; /* Setup Clock Divider */ + /* Periphral clock must be selected before PLL0 enabling and connecting + * - according errata.lpc1768-16.March.2010 - + */ + xHWREG(PCLKSEL0) = 0; /* Peripheral Clock Selection */ + xHWREG(PCLKSEL1) = 0; + + xHWREG(CLKSRCSEL) = 1; /* Select Clock Source for PLL0 */ + + xHWREG(PLL0CFG) = 0x2003f; /* configure PLL0 */ + xHWREG(PLL0FEED) = 0xAA; + xHWREG(PLL0FEED) = 0x55; + + xHWREG(PLL0CON) = 0x01; /* PLL0 Enable */ + xHWREG(PLL0FEED) = 0xAA; + xHWREG(PLL0FEED) = 0x55; + while (!(xHWREG(PLL0STAT) & (1<<26)));/* Wait for PLOCK0 */ + + xHWREG(PLL0CON) = 0x03; /* PLL0 Enable & Connect */ + xHWREG(PLL0FEED) = 0xAA; + xHWREG(PLL0FEED) = 0x55; + while (!(xHWREG(PLL0STAT) & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ + + /* Enable AHB clock to the GPIO domain. */ + xHWREG(PLL1CFG) = 0x00000023; + xHWREG(PLL1FEED) = 0xAA; + xHWREG(PLL1FEED) = 0x55; + + xHWREG(PLL1CON) = 0x01; /* PLL1 Enable */ + xHWREG(PLL1FEED) = 0xAA; + xHWREG(PLL1FEED) = 0x55; + while (!(xHWREG(PLL1STAT) & (1<<10)));/* Wait for PLOCK1 */ + + xHWREG(PLL1CON) = 0x03; /* PLL1 Enable & Connect */ + xHWREG(PLL1FEED) = 0xAA; + xHWREG(PLL1FEED) = 0x55; + while (!(xHWREG(PLL1STAT) & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ + + + xHWREG(PCONP) = 0x042887DE; /* Power Control for Peripherals */ + + xHWREG(CLKOUTCFG) = 0; /* Clock Output Configuration */ + return xtrue; +} + +//***************************************************************************** +// +//! \brief USB Initialize Function +//! +//! \return None. +// +//***************************************************************************** +void xUSBInit(void) +{ + //! P0.29 D+, P0.30 D- + xHWREG(PIN_CON_BASE + PINSEL1) &= ~((3<<26)|(3<<28)); + // PINSEL1 26.27, 28.29 = 01 + xHWREG(PIN_CON_BASE + PINSEL1) |= ((1<<26)|(1<<28)); + + + // P1.18 GoodLink, P1.30 VBUS + xHWREG(PIN_CON_BASE + PINSEL3) &= ~((3<< 4)|(3<<28)); + // PINSEL3 4.5 = 01, 28.29 = 10 + xHWREG(PIN_CON_BASE + PINSEL3) |= ((1<< 4)|(2<<28)); + + + // P2.9 SoftConnect + xHWREG(PIN_CON_BASE + PINSEL4) &= ~((3<<18) ); + xHWREG(PIN_CON_BASE + PINSEL4) |= ((1<<18) ); + + // USB PCLK -> enable USB Per. + xHWREG(PCONP) |= (1UL<<31); + xHWREG(USB_CLK_CTRL) = 0x1A; + while ((xHWREG(USB_CLK_ST) & 0x1A) != 0x1A); + + xIntEnable(xINT_USB); + + xUSBReset(); + xUSBSetAddress(0); +} + +//***************************************************************************** +// +//! \brief Disables the USB master block. +//! This function will disable operation of the USB Master block. +//! +//! \param [in] ulBase is the USB Connect/Disconnect. +//! - \ref xUSB_CONNECT +//! - \ref xUSB_DISCONNECT +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +xtBoolean xUSBConnect (unsigned long ulConnect) { + USBCommandDataWrite(CMD_SET_DEV_STAT, DAT_WR_BYTE(ulConnect ? DEV_CON : 0)); + return xtrue; +} + +//***************************************************************************** +// +//! \brief USB Reset Function +//! +//! \param None +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +xtBoolean xUSBReset(void) +{ + + xHWREG(USB_EP_INDEX) = 0; + xHWREG(USB_MAX_PSIZE) = USB_MAX_PACKET0; + xHWREG(USB_EP_INDEX) = 1; + xHWREG(USB_MAX_PSIZE) = USB_MAX_PACKET0; + while ((xHWREG(USB_DEV_INT_ST) & EP_RLZED_INT) == 0); + + xHWREG(USB_EP_INT_CLR) = 0xFFFFFFFF; + xHWREG(USB_EP_INT_EN) = 0xFFFFFFFF ^ 0; + xHWREG(USB_DEV_INT_CLR) = 0xFFFFFFFF; + xHWREG(USB_DEV_INT_EN) = DEV_STAT_INT | EP_SLOW_INT | + (USB_SOF_EVENT ? FRAME_INT : 0) | + (USB_ERROR_EVENT ? ERR_INT : 0); + return xtrue; + +} +//***************************************************************************** +// +//! \brief USB Suspend Function +//! +//! \param None +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +xtBoolean xUSBSuspend(void) +{ + return xtrue; +} + +//***************************************************************************** +// +//! \brief USB Resume Function +//! +//! \param None +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +xtBoolean xUSBResume(void) +{ + return xtrue; +} + +//***************************************************************************** +// +//! \brief USB Wakeup Function +//! +//! \param None +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +xtBoolean xUSBWakeUp(void) +{ + +// if (USB_DeviceStatus & USB_GETSTATUS_REMOTE_WAKEUP) { + USBCommandDataWrite(CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON)); +// } + return xtrue; +} + +//***************************************************************************** +// +//! \brief USB Remote Wakeup Enbale Function +//! +//! \param None +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBWakeUpEnable(void) +{ + return xtrue; +} + +//***************************************************************************** +// +//! \brief USB Remote Wakeup Disable Function +//! +//! \param None +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBWakeUpDisable(void) +{ + return xtrue; +} + +//***************************************************************************** +// +//! \brief USB Set Address Function. +//! +//! \param [in] ulBase is the USB Address. +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBSetAddress(unsigned long ulAddr) +{ + USBCommandDataWrite(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | ulAddr)); + USBCommandDataWrite(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | ulAddr)); + return xtrue; +} + +//***************************************************************************** +// +//! \brief USB Set Configure Function. +//! +//! \param [in] ulBase is the USB Configure/Deconfigure. +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBConfigure(unsigned long ulConfig) +{ + USBCommandDataWrite(CMD_CFG_DEV, DAT_WR_BYTE(ulConfig ? CONF_DVICE : 0)); + + xHWREG(USB_RE_EP) = 0x00000003; + while ((xHWREG(USB_DEV_INT_ST) & EP_RLZED_INT) == 0); + xHWREG(USB_DEV_INT_CLR) = EP_RLZED_INT; + return xtrue; +} + + +//***************************************************************************** +// +//! \brief Configure USB Endpoint according to Descriptor +//! +//! \param [in] ulBase Pointer to Endpoint Descriptor +//! ulDir: Out (dir == 0), In (dir <> 0) +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBEndpointConfig(USB_ENDPOINT_DESCRIPTOR *epConfig, unsigned long ulDir) +{ + unsigned long num; + + num = EndPointAddressGet(epConfig->bEndpointAddress); + xHWREG(USB_RE_EP) |= (1 << num); + xHWREG(USB_EP_INDEX) = num; + xHWREG(USB_MAX_PSIZE) = epConfig->wMaxPacketSize; + while ((xHWREG(USB_DEV_INT_ST) & EP_RLZED_INT) == 0); + xHWREG(USB_DEV_INT_CLR) = EP_RLZED_INT; + return xtrue; +} +xtBoolean xUSBEndpointDirCtr(unsigned long ulDir) +{ + return xtrue; +} + +//***************************************************************************** +// +//! \brief Enable USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBEndpointEnable(unsigned long ulNum) +{ + USBCommandDataWrite(CMD_SET_EP_STAT(EndPointAddressGet(ulNum)), DAT_WR_BYTE(0)); + return xtrue; +} + +//***************************************************************************** +// +//! \brief Disable USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBEndpointDisable(unsigned long ulNum) +{ + USBCommandDataWrite(CMD_SET_EP_STAT(EndPointAddressGet(ulNum)), DAT_WR_BYTE(EP_STAT_DA)); + return xtrue; +} + +//***************************************************************************** +// +//! \brief Reset USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBEndpointReset(unsigned long ulNum) +{ + USBCommandDataWrite(CMD_SET_EP_STAT(EndPointAddressGet(ulNum)), DAT_WR_BYTE(0)); + return xtrue; +} + +//***************************************************************************** +// +//! \brief Set Stall for USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBEndpointStallSet(unsigned long ulNum) +{ + USBCommandDataWrite(CMD_SET_EP_STAT(EndPointAddressGet(ulNum)), DAT_WR_BYTE(EP_STAT_ST)); + return xtrue; +} + +//***************************************************************************** +// +//! \brief Clear Stall for USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBEndpointStallClear(unsigned long ulNum) +{ + USBCommandDataWrite(CMD_SET_EP_STAT(EndPointAddressGet(ulNum)), DAT_WR_BYTE(0)); + return xtrue; +} + +//***************************************************************************** +// +//! \brief Set max packet size for control out +//! +//! \param [in] None +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBControlOutEnble(void) +{ + return xtrue; +} + +//***************************************************************************** +// +//! \brief Clear USB Endpoint Buffer +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBEndpointBufferClear(unsigned long ulNum) +{ + return xtrue; +} + +//***************************************************************************** +// +//! \brief Read USB Endpoint Data +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! ucpData: Pointer to Data Buffer +//! +//! \return Number of bytes read +// +//***************************************************************************** +unsigned long xUSBEndpointRead(unsigned long ulNum,unsigned char *ucpData) +{ + unsigned long cnt, n; + + xHWREG(USB_CTRL) = ((ulNum & 0x0F) << 2) | CTRL_RD_EN; + + do { + cnt = xHWREG(USB_RX_PLEN); + } while ((cnt & PKT_RDY) == 0); + cnt &= PKT_LNGTH_MASK; + + for (n = 0; n < (cnt + 3) / 4; n++) { + *((__attribute__((packed)) unsigned long *)ucpData) = xHWREG(USB_RX_DATA); + ucpData += 4; + } + xHWREG(USB_CTRL) = 0; + + if (((EP_MSK_ISO >> ulNum) & 1) == 0) { /* Non-Isochronous Endpoint */ + USBCommandCodeWrite(CMD_SEL_EP(EndPointAddressGet(ulNum))); + USBCommandCodeWrite(CMD_CLR_BUF); + } + return (cnt); +} + +//***************************************************************************** +// +//! \brief Write USB Endpoint Data +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! ucpData: Pointer to Data Buffer +//! ulLen Number of bytes +//! +//! \return Number of bytes written +// +//***************************************************************************** +unsigned long xUSBEndpointWrite(unsigned long ulNum,unsigned char *ucpData, + unsigned long ulLen) +{ + unsigned long n; + + xHWREG(USB_CTRL) = ((ulNum & 0x0F) << 2) | CTRL_WR_EN; + + xHWREG(USB_TX_PLEN) = ulLen; + + for (n = 0; n < (ulLen + 3) / 4; n++) { + xHWREG(USB_TX_DATA) = *((__attribute__((packed)) unsigned long *)ucpData); + ucpData += 4; + } + xHWREG(USB_CTRL) = 0; + + USBCommandCodeWrite(CMD_SEL_EP(EndPointAddressGet(ulNum))); + USBCommandCodeWrite(CMD_VALID_BUF); + return (ulLen); +} + +//***************************************************************************** +// +//! \brief Get USB Last Frame Number +//! +//! \param [in] None +//! +//! \return number of last frame +// +//***************************************************************************** +unsigned long xUSBFrameGet(void) +{ + unsigned long val; + + USBCommandCodeWrite(CMD_RD_FRAME); + val = USBCommandDataRead(DAT_RD_FRAME); + val = val | (USBCommandDataRead(DAT_RD_FRAME) << 8); + return (val); +} + + +//***************************************************************************** +// +//! \brief Set max packet size for control out +//! +//! \param [in] event: The logic number of USB endpoint +//! handler: The callback function of USB endpoint +//! data: The extern type which is using here +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +xtBoolean xUSBEventHandler(unsigned char event, xtEventCallback handler, void *data) +{ + xtBoolean err = xfalse; + if(event == 0) + { + g_pfnUSBEndPointEvent[0] = handler; + vpUSBEndPointEventData[0] = data; + err = xtrue; + return err; + } + switch(event) + { + case USB_EVENT_EP1 : + g_pfnUSBEndPointEvent[1] = handler; + vpUSBEndPointEventData[1] = data; + err = xtrue; + break; + case USB_EVENT_EP2 : + g_pfnUSBEndPointEvent[2] = handler; + vpUSBEndPointEventData[2] = data; + err = xtrue; + break; + case USB_EVENT_EP3 : + g_pfnUSBEndPointEvent[3] = handler; + vpUSBEndPointEventData[3] = data; + err = xtrue; + break; + case USB_EVENT_EP4 : + g_pfnUSBEndPointEvent[4] = handler; + vpUSBEndPointEventData[4] = data; + err = xtrue; + break; + case USB_EVENT_EP5 : + g_pfnUSBEndPointEvent[5] = handler; + vpUSBEndPointEventData[5] = data; + err = xtrue; + break; + case USB_EVENT_EP6 : + g_pfnUSBEndPointEvent[6] = handler; + vpUSBEndPointEventData[6] = data; + err = xtrue; + break; + case USB_EVENT_EP7 : + g_pfnUSBEndPointEvent[7] = handler; + vpUSBEndPointEventData[7] = data; + err = xtrue; + break; + } + return err; + +} + +unsigned long ulTest[100] = {0}; +int testIndex = 0; + +void USBIntHandler(void) { + unsigned long disr, val, n, m; + unsigned long episr, episrCur; + + disr = xHWREG(USB_DEV_INT_ST); /* Device Interrupt Status */ + xHWREG(USB_DEV_INT_CLR) = disr; + if(testIndex<100) + ulTest[testIndex++] = disr; + + /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */ + if (disr & DEV_STAT_INT) { +// LPC_USB->DevIntClr = DEV_STAT_INT; + USBCommandCodeWrite(CMD_GET_DEV_STAT); + val = USBCommandDataRead(DAT_GET_DEV_STAT); /* Device Status */ + if (val & DEV_RST) { /* Reset */ + ulTest[testIndex++] = 0xFF01; + xUSBReset(); +#if USB_RESET_EVENT + USB_Reset_Event(); +#endif + } + if (val & DEV_CON_CH) { /* Connect change */ +#if USB_POWER_EVENT + USB_Power_Event(val & DEV_CON); +#endif + } + if (val & DEV_SUS_CH) { /* Suspend/Resume */ + if (val & DEV_SUS) { /* Suspend */ + ulTest[testIndex++] = 0xFF02; + xUSBSuspend(); +#if USB_SUSPEND_EVENT + USB_Suspend_Event(); +#endif + } else { /* Resume */ + ulTest[testIndex++] = 0xFF03; + xUSBResume(); +#if USB_RESUME_EVENT + USB_Resume_Event(); +#endif + } + } + goto isr_end; + } + +#if USB_SOF_EVENT + /* Start of Frame Interrupt */ + if (disr & FRAME_INT) { + USB_SOF_Event(); + } +#endif + +#if USB_ERROR_EVENT + /* Error Interrupt */ + if (disr & ERR_INT) { + USBCommandCodeWrite(CMD_RD_ERR_STAT); + val = USBCommandDataRead(DAT_RD_ERR_STAT); + USB_Error_Event(val); + } +#endif + + /* Endpoint's Slow Interrupt */ + if (disr & EP_SLOW_INT) { +// while (LPC_USB->USBEpIntSt) { /* Endpoint Interrupt Status */ + episrCur = 0; + episr = xHWREG(USB_EP_INT_ST); + for (n = 0; n < USB_EP_NUM; n++) { /* Check All Endpoints */ + if (episr == episrCur) break; /* break if all EP interrupts handled */ + if (episr & (1 << n)) { + episrCur |= (1 << n); + m = n >> 1; + + xHWREG(USB_EP_INT_CLR) = (1 << n); + while ((xHWREG(USB_DEV_INT_ST) & CDFULL_INT) == 0); + val = xHWREG(USB_CMD_DATA); + + if ((n & 1) == 0) { /* OUT Endpoint */ + if (n == 0) { /* Control OUT Endpoint */ + if (val & EP_SEL_STP) { /* Setup Packet */ + if (g_pfnUSBEndPointEvent[0]) { + g_pfnUSBEndPointEvent[0](vpUSBEndPointEventData[0],USB_EVT_SETUP,0,0); + continue; + } + } + } + if (g_pfnUSBEndPointEvent[m]) { + g_pfnUSBEndPointEvent[m](vpUSBEndPointEventData[m],USB_EVT_OUT,0,0); + } + } else { /* IN Endpoint */ + if (g_pfnUSBEndPointEvent[m]) { + g_pfnUSBEndPointEvent[m](vpUSBEndPointEventData[m],USB_EVT_IN,0,0); + } + } + } + } + xHWREG(USB_DEV_INT_CLR) = EP_SLOW_INT; + } + + + +isr_end: + return; +} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xusb_config.h b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xusb_config.h new file mode 100644 index 00000000..0c9ca0ce --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_LPC17xx/libcox/xusb_config.h @@ -0,0 +1,40 @@ +/***************************************************************************** + * U S B - N U C - C O X - C O M P O N E N T + ****************************************************************************/ +/** + * @file : cox_config.h + * @brief : config file + * @version : 1.0 + * @date : 28. Dec. 2010 + * @author : CooCox + ****************************************************************************/ + +#ifndef __COX_CONFIG_H +#define __COX_CONFIG_H + + +#define USB_EP_NUM 32 /*!< Max Number of Endpoints <1-32>*/ +#define USB_LOGIC_EP_NUM 16 /*! */ +#define USB_MAX_PACKET0 64 +//#define USB_DMA 1 +#define USB_DMA_EP 0x00000000 + +#define CTRL_EP_NUM 0 /*!< control Endpoint number <0> */ + + +#define USB_POWER_EVENT 0 +#define USB_RESET_EVENT 0 +#define USB_SUSPEND_EVENT 0 +#define USB_RESUME_EVENT 0 +#define USB_WAKEUP_EVENT 0 +#define USB_SOF_EVENT 0 +#define USB_ERROR_EVENT 0 +#define USB_EP_EVENT 0x0005 +#define USB_CONFIGURE_EVENT 0 +#define USB_INTERFACE_EVENT 0 +#define USB_FEATURE_EVENT 0 + + + + +#endif /* __COX_CONFIG_H */ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/all/project/template/coide/main.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/all/project/template/coide/main.c index bf6465a0..991ebc69 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/all/project/template/coide/main.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/all/project/template/coide/main.c @@ -1,5 +1,6 @@ - +#include "CoX.h" int main() { + xSysCtlDelay(1000); while(1); } diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/all/project/template/coide/template.coproj b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/all/project/template/coide/template.coproj index 1149b443..ea0df44f 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/all/project/template/coide/template.coproj +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/all/project/template/coide/template.coproj @@ -1,7 +1,7 @@ - + @@ -22,10 +22,11 @@ - + - - - - - - - + + + - + + + + - - - + + + + - + + + - + + + - - + + - + + - - + - + - - + + + - \ No newline at end of file diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xacmp.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/acmp.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xacmp.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/acmp.c index 78b7f308..0e3b7962 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xacmp.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/acmp.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xacmp.c +//! \file acmp.c //! \brief Driver for the analog comparator. //! \version V2.1.1.0 //! \date 1/3/2012 @@ -11,7 +11,7 @@ // //***************************************************************************** -#include "xhw_acmp.h" +#include "hw_acmp.h" #include "CoX.h" diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xadc.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/adc.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xadc.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/adc.c index 49bb17a1..af7b7418 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xadc.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/adc.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xadc.c +//! \file adc.c //! \brief Driver for the ADC Controller. //! \version V2.1.1.0 //! \date 12/29/2011 @@ -37,7 +37,7 @@ // //***************************************************************************** -#include "xhw_adc.h" +#include "hw_adc.h" #include "CoX.h" static xtEventCallback g_pfnADCHandlerCallbacks[1] = {0}; diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xcore.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/core.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xcore.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/core.c index 2d3f92c8..ff7604e5 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xcore.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/core.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xcore.c +//! \file core.c //! \brief Instruction wrappers for special CPU instructions. //! Driver for the NVIC Interrupt Controller. //! Driver for the SysTick driver. diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xdebug.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/debug.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xdebug.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/debug.c index 96d15b10..4de3236d 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xdebug.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/debug.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xdebug.h +//! \file debug.h //! \brief Drivers for assisting debug of the peripheral library. //! \version V2.1.1.0 //! \date 12/20/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xgpio.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/gpio.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xgpio.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/gpio.c index dab80b37..ea8e558f 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xgpio.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/gpio.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xgpio.c +//! \file gpio.c //! \brief Driver for the GPIO controller //! \version V2.1.1.0 //! \date 12/27/2011 @@ -38,8 +38,8 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_gpio.h" +#include "hw_sysctl.h" +#include "hw_gpio.h" typedef struct diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/gpio.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/gpio.h index 49fd6dfd..16fb4c8f 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/gpio.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/gpio.h @@ -315,6 +315,63 @@ extern "C" // //***************************************************************************** +//***************************************************************************** +// +//! \addtogroup M051_GP_Short_Pin M051 General Purpose Short Pin +//! @{ +// +//***************************************************************************** +#define GPA0 GPIO_PORTA_BASE, GPIO_PIN_0 +#define GPA1 GPIO_PORTA_BASE, GPIO_PIN_1 +#define GPA2 GPIO_PORTA_BASE, GPIO_PIN_2 +#define GPA3 GPIO_PORTA_BASE, GPIO_PIN_3 +#define GPA4 GPIO_PORTA_BASE, GPIO_PIN_4 +#define GPA5 GPIO_PORTA_BASE, GPIO_PIN_5 +#define GPA6 GPIO_PORTA_BASE, GPIO_PIN_6 +#define GPA7 GPIO_PORTA_BASE, GPIO_PIN_7 + +#define GPB0 GPIO_PORTB_BASE, GPIO_PIN_0 +#define GPB1 GPIO_PORTB_BASE, GPIO_PIN_1 +#define GPB2 GPIO_PORTB_BASE, GPIO_PIN_2 +#define GPB3 GPIO_PORTB_BASE, GPIO_PIN_3 +#define GPB4 GPIO_PORTB_BASE, GPIO_PIN_4 +#define GPB5 GPIO_PORTB_BASE, GPIO_PIN_5 +#define GPB6 GPIO_PORTB_BASE, GPIO_PIN_6 +#define GPB7 GPIO_PORTB_BASE, GPIO_PIN_7 + +#define GPC0 GPIO_PORTC_BASE, GPIO_PIN_0 +#define GPC1 GPIO_PORTC_BASE, GPIO_PIN_1 +#define GPC2 GPIO_PORTC_BASE, GPIO_PIN_2 +#define GPC3 GPIO_PORTC_BASE, GPIO_PIN_3 +#define GPC4 GPIO_PORTC_BASE, GPIO_PIN_4 +#define GPC5 GPIO_PORTC_BASE, GPIO_PIN_5 +#define GPC6 GPIO_PORTC_BASE, GPIO_PIN_6 +#define GPC7 GPIO_PORTC_BASE, GPIO_PIN_7 + +#define GPD0 GPIO_PORTD_BASE, GPIO_PIN_0 +#define GPD1 GPIO_PORTD_BASE, GPIO_PIN_1 +#define GPD2 GPIO_PORTD_BASE, GPIO_PIN_2 +#define GPD3 GPIO_PORTD_BASE, GPIO_PIN_3 +#define GPD4 GPIO_PORTD_BASE, GPIO_PIN_4 +#define GPD5 GPIO_PORTD_BASE, GPIO_PIN_5 +#define GPD6 GPIO_PORTD_BASE, GPIO_PIN_6 +#define GPD7 GPIO_PORTD_BASE, GPIO_PIN_7 + +#define GPE0 GPIO_PORTE_BASE, GPIO_PIN_0 +#define GPE1 GPIO_PORTE_BASE, GPIO_PIN_1 +#define GPE2 GPIO_PORTE_BASE, GPIO_PIN_2 +#define GPE3 GPIO_PORTE_BASE, GPIO_PIN_3 +#define GPE4 GPIO_PORTE_BASE, GPIO_PIN_4 +#define GPE5 GPIO_PORTE_BASE, GPIO_PIN_5 +#define GPE6 GPIO_PORTE_BASE, GPIO_PIN_6 +#define GPE7 GPIO_PORTE_BASE, GPIO_PIN_7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + //***************************************************************************** // //! \addtogroup M051_GPIO_Pin_Config M051 GPIO Pin Config diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_acmp.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_acmp.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_acmp.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_acmp.h index ccdb889c..c79bd0be 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_acmp.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_acmp.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_acmp.h +//! \file hw_acmp.h //! \brief Macros used when accessing the comparator hardware. //! \version V2.1.1.0 //! \date 1/3/2012 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_adc.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_adc.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_adc.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_adc.h index 43880eda..bda15ba4 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_adc.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_adc.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_adc.h +//! \file hw_adc.h //! \brief Macros used when accessing the ADC hardware. //! \version V2.1.1.0 //! \date 12/29/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_gpio.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_gpio.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_gpio.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_gpio.h index bfa16ca9..be8cf99d 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_gpio.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_gpio.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_gpio.h +//! \file hw_gpio.h //! \brief Macros used when accessing the GPIO control hardware. //! \version V2.1.1.0 //! \date 12/23/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_i2c.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_i2c.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_i2c.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_i2c.h index dc05e3fe..d42877bf 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_i2c.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_i2c.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_i2c.h +//! \file hw_i2c.h //! \brief Macros and defines used when accessing the I2C hardware. //! \version V2.1.1.0 //! \date 12/30/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_pwm.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_pwm.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_pwm.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_pwm.h index 2eb4b24a..36e1a986 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_pwm.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_pwm.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_pwm.h +//! \file hw_pwm.h //! \brief Macros and defines used when accessing the PWM hardware. //! \version V2.1.1.0 //! \date 12/27/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_spi.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_spi.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_spi.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_spi.h index 1f5cb117..39fc7f34 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_spi.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_spi.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_spi.h +//! \file hw_spi.h //! \brief Macros used when accessing the SPI hardware. //! \version V2.1.1.0 //! \date 12/27/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_sysctl.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_sysctl.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_sysctl.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_sysctl.h index 147ed93f..a9babb00 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_sysctl.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_sysctl.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_sysctl.h +//! \file hw_sysctl.h //! \brief Macros used when accessing the system control hardware. //! \version V2.1.1.0 //! \date 12/26/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_timer.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_timer.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_timer.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_timer.h index b6c50b0f..7a05528b 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_timer.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_timer.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_timer.h +//! \file hw_timer.h //! \brief Macros and defines used when accessing the TIMER hardware. //! \version V2.1.1.0 //! \date 12/31/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_uart.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_uart.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_uart.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_uart.h index f69177ac..15bd5803 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_uart.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_uart.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_uart.h +//! \file hw_uart.h //! \brief Macros used when accessing the UART hardware. //! \version V2.1.1.0 //! \date 12/28/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_wdt.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_wdt.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_wdt.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_wdt.h index f94fd110..9bb19e9e 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xhw_wdt.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/hw_wdt.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_wdt.h +//! \file hw_wdt.h //! \brief Macros and defines used when accessing the WATCHDOG hardware. //! \version V2.1.1.0 //! \date 1/3/2012 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xi2c.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/i2c.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xi2c.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/i2c.c index 7c8beefc..95e142bc 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xi2c.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/i2c.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xi2c.c +//! \file i2c.c //! \brief Driver for the I2C //! \version V2.2.1.0 //! \date 11/15/2013 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_i2c.h" +#include "hw_sysctl.h" +#include "hw_i2c.h" //***************************************************************************** diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xpwm.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/pwm.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xpwm.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/pwm.c index d554d7e5..d116ac75 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xpwm.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/pwm.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xpwm.c +//! \file pwm.c //! \brief Driver for the PWM //! \version V2.2.1.0 //! \date 11/15/2013 @@ -38,8 +38,8 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_pwm.h" +#include "hw_sysctl.h" +#include "hw_pwm.h" diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xspi.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/spi.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xspi.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/spi.c index c3e6077d..b4b42a4d 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xspi.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/spi.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xspi.c +//! \file spi.c //! \brief Driver for the SPI //! \version V2.2.1.0 //! \date 11/15/2013 @@ -38,8 +38,8 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_spi.h" +#include "hw_sysctl.h" +#include "hw_spi.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xsysctl.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/sysctl.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xsysctl.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/sysctl.c index cf32e0b3..30ba6230 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xsysctl.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/sysctl.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xsysctl.c +//! \file sysctl.c //! \brief Driver for the system controller //! \version V2.1.1.0 //! \date 12/26/2011 @@ -37,7 +37,7 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" +#include "hw_sysctl.h" static unsigned long s_ulExtClockMHz = 12; diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xtimer.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/timer.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xtimer.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/timer.c index 19c7c5c2..4ec18153 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xtimer.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/timer.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xtimer.c +//! \file timer.c //! \brief Driver for the Timer //! \version V2.1.1.0 //! \date 12/31/2011 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_timer.h" +#include "hw_sysctl.h" +#include "hw_timer.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xuart.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/uart.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xuart.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/uart.c index 707072ae..622658d4 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xuart.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/uart.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xuart.c +//! \file uart.c //! \brief Driver for the UART //! \version V2.1.1.0 //! \date 12/28/2011 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_uart.h" +#include "hw_sysctl.h" +#include "hw_uart.h" //***************************************************************************** diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xwdt.c b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/wdt.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xwdt.c rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/wdt.c index 21bc3027..c23ad18c 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xwdt.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/wdt.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xwdt.c +//! \file wdt.c //! \brief Driver for the WDT //! \version V2.1.1.0 //! \date 1/3/2012 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_wdt.h" +#include "hw_sysctl.h" +#include "hw_wdt.h" //***************************************************************************** diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/CoX_base.h b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xPort.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/CoX_base.h rename to CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xPort.h index 7c7a5a53..ce91ed26 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/CoX_base.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_M051DN/libcox/xPort.h @@ -1,5 +1,5 @@ -#ifndef _M051DNDE_COX_BASE_H_ -#define _M051DNDE_COX_BASE_H_ +#ifndef _M051DNDE_X_PORT_H_ +#define _M051DNDE_X_PORT_H_ #include "lowlayer.h" #include "acmp.h" diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xacmp.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/acmp.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xacmp.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/acmp.c index a9a0b449..4ba8e0a4 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xacmp.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/acmp.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xacmp.c +//! \file acmp.c //! \brief Driver for the analog comparator. //! \version V2.1.1.1 //! \date 11/14/2011 @@ -12,7 +12,7 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_acmp.h" +#include "hw_acmp.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xadc.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/adc.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xadc.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/adc.c index 98578c14..4cf54feb 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xadc.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/adc.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xadc.c +//! \file adc.c //! \brief Driver for the ADC Controller. //! \version V2.1.1.1 //! \date 11/14/2011 @@ -38,7 +38,7 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_adc.h" +#include "hw_adc.h" static xtEventCallback g_pfnADCHandlerCallbacks[1] = {0}; diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xcore.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/core.c similarity index 100% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xcore.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/core.c diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xdma.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/dma.c similarity index 100% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xdma.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/dma.c diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xgpio.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/gpio.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xgpio.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/gpio.c index 52015a62..baff2f6e 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xgpio.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/gpio.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xgpio.c +//! \file gpio.c //! \brief Driver for the GPIO controller //! \version V2.1.1.1 //! \date 11/14/2011 @@ -38,8 +38,8 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_gpio.h" +#include "hw_sysctl.h" +#include "hw_gpio.h" typedef struct { diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/gpio.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/gpio.h index ee160f33..539cd439 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/gpio.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/gpio.h @@ -337,6 +337,103 @@ // //***************************************************************************** +//***************************************************************************** +// +//! \addtogroup NUC1xx_GPIO_GP_Short_Pin NUC1xx General Purpose Short Pin +//! @{ +// +//***************************************************************************** +#define GPA0 GPIO_PORTA_BASE, GPIO_PIN_0 +#define GPA1 GPIO_PORTA_BASE, GPIO_PIN_1 +#define GPA2 GPIO_PORTA_BASE, GPIO_PIN_2 +#define GPA3 GPIO_PORTA_BASE, GPIO_PIN_3 +#define GPA4 GPIO_PORTA_BASE, GPIO_PIN_4 +#define GPA5 GPIO_PORTA_BASE, GPIO_PIN_5 +#define GPA6 GPIO_PORTA_BASE, GPIO_PIN_6 +#define GPA7 GPIO_PORTA_BASE, GPIO_PIN_7 +#define GPA8 GPIO_PORTA_BASE, GPIO_PIN_8 +#define GPA9 GPIO_PORTA_BASE, GPIO_PIN_9 +#define GPA10 GPIO_PORTA_BASE, GPIO_PIN_10 +#define GPA11 GPIO_PORTA_BASE, GPIO_PIN_11 +#define GPA12 GPIO_PORTA_BASE, GPIO_PIN_12 +#define GPA13 GPIO_PORTA_BASE, GPIO_PIN_13 +#define GPA14 GPIO_PORTA_BASE, GPIO_PIN_14 +#define GPA15 GPIO_PORTA_BASE, GPIO_PIN_15 + +#define GPB0 GPIO_PORTB_BASE, GPIO_PIN_0 +#define GPB1 GPIO_PORTB_BASE, GPIO_PIN_1 +#define GPB2 GPIO_PORTB_BASE, GPIO_PIN_2 +#define GPB3 GPIO_PORTB_BASE, GPIO_PIN_3 +#define GPB4 GPIO_PORTB_BASE, GPIO_PIN_4 +#define GPB5 GPIO_PORTB_BASE, GPIO_PIN_5 +#define GPB6 GPIO_PORTB_BASE, GPIO_PIN_6 +#define GPB7 GPIO_PORTB_BASE, GPIO_PIN_7 +#define GPB8 GPIO_PORTB_BASE, GPIO_PIN_8 +#define GPB9 GPIO_PORTB_BASE, GPIO_PIN_9 +#define GPB10 GPIO_PORTB_BASE, GPIO_PIN_10 +#define GPB11 GPIO_PORTB_BASE, GPIO_PIN_11 +#define GPB12 GPIO_PORTB_BASE, GPIO_PIN_12 +#define GPB13 GPIO_PORTB_BASE, GPIO_PIN_13 +#define GPB14 GPIO_PORTB_BASE, GPIO_PIN_14 +#define GPB15 GPIO_PORTB_BASE, GPIO_PIN_15 + +#define GPC0 GPIO_PORTC_BASE, GPIO_PIN_0 +#define GPC1 GPIO_PORTC_BASE, GPIO_PIN_1 +#define GPC2 GPIO_PORTC_BASE, GPIO_PIN_2 +#define GPC3 GPIO_PORTC_BASE, GPIO_PIN_3 +#define GPC4 GPIO_PORTC_BASE, GPIO_PIN_4 +#define GPC5 GPIO_PORTC_BASE, GPIO_PIN_5 +#define GPC6 GPIO_PORTC_BASE, GPIO_PIN_6 +#define GPC7 GPIO_PORTC_BASE, GPIO_PIN_7 +#define GPC8 GPIO_PORTC_BASE, GPIO_PIN_8 +#define GPC9 GPIO_PORTC_BASE, GPIO_PIN_9 +#define GPC10 GPIO_PORTC_BASE, GPIO_PIN_10 +#define GPC11 GPIO_PORTC_BASE, GPIO_PIN_11 +#define GPC12 GPIO_PORTC_BASE, GPIO_PIN_12 +#define GPC13 GPIO_PORTC_BASE, GPIO_PIN_13 +#define GPC14 GPIO_PORTC_BASE, GPIO_PIN_14 +#define GPC15 GPIO_PORTC_BASE, GPIO_PIN_15 + +#define GPD0 GPIO_PORTD_BASE, GPIO_PIN_0 +#define GPD1 GPIO_PORTD_BASE, GPIO_PIN_1 +#define GPD2 GPIO_PORTD_BASE, GPIO_PIN_2 +#define GPD3 GPIO_PORTD_BASE, GPIO_PIN_3 +#define GPD4 GPIO_PORTD_BASE, GPIO_PIN_4 +#define GPD5 GPIO_PORTD_BASE, GPIO_PIN_5 +#define GPD6 GPIO_PORTD_BASE, GPIO_PIN_6 +#define GPD7 GPIO_PORTD_BASE, GPIO_PIN_7 +#define GPD8 GPIO_PORTD_BASE, GPIO_PIN_8 +#define GPD9 GPIO_PORTD_BASE, GPIO_PIN_9 +#define GPD10 GPIO_PORTD_BASE, GPIO_PIN_10 +#define GPD11 GPIO_PORTD_BASE, GPIO_PIN_11 +#define GPD12 GPIO_PORTD_BASE, GPIO_PIN_12 +#define GPD13 GPIO_PORTD_BASE, GPIO_PIN_13 +#define GPD14 GPIO_PORTD_BASE, GPIO_PIN_14 +#define GPD15 GPIO_PORTD_BASE, GPIO_PIN_15 + +#define GPE0 GPIO_PORTE_BASE, GPIO_PIN_0 +#define GPE1 GPIO_PORTE_BASE, GPIO_PIN_1 +#define GPE2 GPIO_PORTE_BASE, GPIO_PIN_2 +#define GPE3 GPIO_PORTE_BASE, GPIO_PIN_3 +#define GPE4 GPIO_PORTE_BASE, GPIO_PIN_4 +#define GPE5 GPIO_PORTE_BASE, GPIO_PIN_5 +#define GPE6 GPIO_PORTE_BASE, GPIO_PIN_6 +#define GPE7 GPIO_PORTE_BASE, GPIO_PIN_7 +#define GPE8 GPIO_PORTE_BASE, GPIO_PIN_8 +#define GPE9 GPIO_PORTE_BASE, GPIO_PIN_9 +#define GPE10 GPIO_PORTE_BASE, GPIO_PIN_10 +#define GPE11 GPIO_PORTE_BASE, GPIO_PIN_11 +#define GPE12 GPIO_PORTE_BASE, GPIO_PIN_12 +#define GPE13 GPIO_PORTE_BASE, GPIO_PIN_13 +#define GPE14 GPIO_PORTE_BASE, GPIO_PIN_14 +#define GPE15 GPIO_PORTE_BASE, GPIO_PIN_15 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + //***************************************************************************** // //! \addtogroup NUC1xx_GPIO_Pin_Config NUC1xx GPIO Pin Config diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_acmp.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_acmp.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_acmp.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_acmp.h index 3cf4f39d..97a083b4 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_acmp.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_acmp.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_acmp.h +//! \file hw_acmp.h //! \brief Macros used when accessing the comparator hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_adc.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_adc.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_adc.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_adc.h index d4278d72..fd9ab243 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_adc.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_adc.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_adc.h +//! \file hw_adc.h //! \brief Macros used when accessing the ADC hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_dma.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_dma.h similarity index 100% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_dma.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_dma.h diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_gpio.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_gpio.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_gpio.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_gpio.h index af0c1848..bacefbf6 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_gpio.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_gpio.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_gpio.h +//! \file hw_gpio.h //! \brief Macros used when accessing the GPIO control hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_i2c.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_i2c.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_i2c.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_i2c.h index 69fe82bc..22542902 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_i2c.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_i2c.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_i2c.h +//! \file hw_i2c.h //! \brief Macros and defines used when accessing the I2C hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_pwm.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_pwm.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_pwm.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_pwm.h index 713a7f4d..10155e5a 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_pwm.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_pwm.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_pwm.h +//! \file hw_pwm.h //! \brief Macros and defines used when accessing the PWM hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_rtc.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_rtc.h similarity index 100% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_rtc.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_rtc.h diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_spi.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_spi.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_spi.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_spi.h index 79d6c4fc..fd2cf232 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_spi.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_spi.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_spi.h +//! \file hw_spi.h //! \brief Macros used when accessing the SPI hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_sysctl.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_sysctl.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_sysctl.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_sysctl.h index 610d4f7e..5d18b6ff 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_sysctl.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_sysctl.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_sysctl.h +//! \file hw_sysctl.h //! \brief Macros used when accessing the system control hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_timer.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_timer.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_timer.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_timer.h index fcc4282b..5cebb575 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_timer.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_timer.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_timer.h +//! \file hw_timer.h //! \brief Macros and defines used when accessing the TIMER hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_uart.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_uart.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_uart.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_uart.h index 7ea50e13..a62a4e5d 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_uart.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_uart.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_uart.h +//! \file hw_uart.h //! \brief Macros used when accessing the UART hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_wdt.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_wdt.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_wdt.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_wdt.h index 86619c4b..67ca9e39 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xhw_wdt.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/hw_wdt.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_wdt.h +//! \file hw_wdt.h //! \brief Macros and defines used when accessing the WATCHDOG hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xi2c.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/i2c.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xi2c.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/i2c.c index c74459a7..56e742b0 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xi2c.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/i2c.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xi2c.c +//! \file i2c.c //! \brief Driver for the I2C //! \version V2.1.1.1 //! \date 6/14/2014 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_i2c.h" +#include "hw_sysctl.h" +#include "hw_i2c.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xpwm.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/pwm.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xpwm.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/pwm.c index ea5762f9..750c77e3 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xpwm.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/pwm.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xpwm.c +//! \file pwm.c //! \brief Driver for the PWM //! \version V2.1.1.1 //! \date 11/14/2011 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_pwm.h" +#include "hw_sysctl.h" +#include "hw_pwm.h" //***************************************************************************** diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xrtc.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/rtc.c similarity index 100% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xrtc.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/rtc.c diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xspi.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/spi.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xspi.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/spi.c index 25335cbf..1e95350a 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xspi.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/spi.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xspi.c +//! \file spi.c //! \brief Driver for the SPI //! \version V2.1.1.1 //! \date 11/14/2011 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_spi.h" +#include "hw_sysctl.h" +#include "hw_spi.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xsysctl.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/sysctl.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xsysctl.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/sysctl.c index c293d259..5110da92 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xsysctl.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/sysctl.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xsysctl.c +//! \file sysctl.c //! \brief Driver for the system controller //! \version V2.1.1.1 //! \date 11/14/2011 @@ -37,7 +37,7 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" +#include "hw_sysctl.h" static unsigned long s_ulExtClockMHz = 12; diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xtimer.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/timer.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xtimer.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/timer.c index 8dece6ed..1375e0f7 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xtimer.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/timer.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xtimer.c +//! \file timer.c //! \brief Driver for the Timer //! \version V2.1.1.1 //! \date 11/14/2011 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_timer.h" +#include "hw_sysctl.h" +#include "hw_timer.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xuart.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/uart.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xuart.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/uart.c index e6021ec6..f9b79a68 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xuart.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/uart.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xuart.c +//! \file uart.c //! \brief Driver for the UART //! \version V2.1.1.1 //! \date 11/14/2011 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_uart.h" +#include "hw_sysctl.h" +#include "hw_uart.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xwdt.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/wdt.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xwdt.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/wdt.c index e68d41a8..5e632c9e 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xwdt.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/wdt.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xwdt.c +//! \file wdt.c //! \brief Driver for the WDT //! \version V2.1.1.1 //! \date 11/14/2011 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_wdt.h" +#include "hw_sysctl.h" +#include "hw_wdt.h" //***************************************************************************** diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xdebug.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xdebug.c deleted file mode 100644 index 6f0e6d74..00000000 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC1xxDN/libcox/xdebug.c +++ /dev/null @@ -1,66 +0,0 @@ -//***************************************************************************** -// -//! \file xdebug.h -//! \brief Drivers for assisting debug of the peripheral library. -//! \version V2.1.1.1 -//! \date 11/14/2011 -//! \author CooCox -//! \copy -//! -//! Copyright (c) 2011, CooCox -//! All rights reserved. -//! -//! Redistribution and use in source and binary forms, with or without -//! modification, are permitted provided that the following conditions -//! are met: -//! -//! * Redistributions of source code must retain the above copyright -//! notice, this list of conditions and the following disclaimer. -//! * Redistributions in binary form must reproduce the above copyright -//! notice, this list of conditions and the following disclaimer in the -//! documentation and/or other materials provided with the distribution. -//! * Neither the name of the nor the names of its -//! contributors may be used to endorse or promote products derived -//! from this software without specific prior written permission. -//! -//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -//! THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Error Function to be called when assert runs false. -//! -//! \param pcFilename is the current file name. -//! \param ulLine is the current line number. -//! -//! This is just an default error handler function, Users should implement -//! this function with your own way when debug. -//! -//! \note This is only used when doing a \b xDEBUG build. -//! -//! \return None. -// -//***************************************************************************** -#ifdef xDEBUG -void __xerror__(char *pcFilename, unsigned long ulLine) -{ - // - // Add your own error handling - // - while(1) - { - - } -} -#endif diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/acmp.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/acmp.c new file mode 100644 index 00000000..8c4b205e --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/acmp.c @@ -0,0 +1,548 @@ +//***************************************************************************** +// +//! \file acmp.c +//! \brief Driver for the analog comparator. +//! \version V2.1.1.0 +//! \date 1/3/2012 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2009-2011 CooCox. All rights reserved. +// +//***************************************************************************** + +#include "hw_acmp.h" +#include "CoX.h" + + +//***************************************************************************** +// +// The Interrupt Callback functions +// +//***************************************************************************** +static xtEventCallback g_pfnACMPHandlerCallbacks[2] = {0}; + +//***************************************************************************** +// +//! \brief Init the Comp n Interrupt Callback function. +//! +//! \param ulBase is the base address of the ADC. +//! \param ulCompID is the ID(index) of the comparator. +//! Refrence \ref xACMP_Comparator_IDs. +//! \param pfnCallback is the callback function. +//! +//! When there is any ADC interrupt occrus, Interrupt Handler will +//! call the callback function. +//! +//! param of pfnCallback +//! - pvCBData not used, always 0. +//! - ulEvent not used, always 0. +//! - ulMsgParam not used, always 0. +//! - pvMsgData not used, always 0. +//! . +//! +//! \return None. +// +//***************************************************************************** +void +xACMPIntCallbackInit(unsigned long ulBase, unsigned long ulCompID, + xtEventCallback pfnCallback) +{ + unsigned long Base; + // + // Check the arguments. + // + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulCompID == xACMP_0) || (ulCompID == xACMP_1)); + Base = ((ulBase == ACMP_BASE) ? 0 : 2); + + switch(ulCompID) + { + case xACMP_0: + { + g_pfnACMPHandlerCallbacks[Base+0] = pfnCallback; + break; + } + case xACMP_1: + { + g_pfnACMPHandlerCallbacks[Base+1] = pfnCallback; + break; + } + } +} + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \brief Comparator Interrupt Handler. +//! +//! If users want to user the ACMP Interrupt Callback feature, Users should +//! promise that the ACMP Handle in the vector table is ACMPIntHandler. +//! +//! \return None. +// +//***************************************************************************** +void +ACMP_IRQHandler(void) +{ + unsigned long ulBase = ACMP_BASE; + unsigned long ulIntFlags; + + // + // Get the Interrupt flags + // + ulIntFlags = xHWREG(ulBase + ACMP_SR); + + // + // Clear the Interrrupt flags + // + xHWREG(ulBase + ACMP_SR) = ulIntFlags; + + // + // Call user event callback function + // + if((ulIntFlags & ACMP_SR_CMPF0) && g_pfnACMPHandlerCallbacks[0]) + { + g_pfnACMPHandlerCallbacks[0](0, 0, 0, 0); + } + + if((ulIntFlags & ACMP_SR_CMPF1) && g_pfnACMPHandlerCallbacks[1]) + { + g_pfnACMPHandlerCallbacks[1](0, 0, 0, 0); + } +} +// +////***************************************************************************** +//// +////! \brief Comparator Interrupt Handler. +////! +////! If users want to user the ACMP Interrupt Callback feature, Users should +////! promise that the ACMP Handle in the vector table is ACMPIntHandler. +////! +////! \return None. +//// +////***************************************************************************** +//void +//ACMP23IntHandler(void) +//{ +// unsigned long ulBase = ACMP23_BASE; +// unsigned long ulIntFlags; +// +// // +// // Get the Interrupt flags +// // +// ulIntFlags = xHWREG(ulBase + ACMP_SR); +// +// // +// // Clear the Interrrupt flags +// // +// xHWREG(ulBase + ACMP_SR) = ulIntFlags; +// +// // +// // Call user event callback function +// // +// if((ulIntFlags & ACMP_SR_CMPF0) && g_pfnACMPHandlerCallbacks[0]) +// { +// g_pfnACMPHandlerCallbacks[3](0, 0, 0, 0); +// } +// +// if((ulIntFlags & ACMP_SR_CMPF1) && g_pfnACMPHandlerCallbacks[1]) +// { +// g_pfnACMPHandlerCallbacks[4](0, 0, 0, 0); +// } +//} +#ifdef __cplusplus +} +#endif +//***************************************************************************** +// +//! \brief Select the ACMP- input source of the comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index(0 - 1) of the comparator to configure. +//! \param ulSource is the source of Comp- input. +//! Refrence \ref M051_ACMP_Analog_Src_negative. +//! +//! This function configures the Comp- input source of a comparator. +//! +//! \return None. +// +//***************************************************************************** +void +ACMPNegativeSrcSet(unsigned long ulBase, unsigned long ulComp, + unsigned long ulSource) +{ + unsigned long ulCRAddr; + + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulComp >= 0) && (ulComp < 2)); + xASSERT((ulSource == ACMP_ASRCN_PIN) || (ulSource == ACMP_ASRCN_REF)); + + // + // Get the corresponding CR register address + // + ulCRAddr = ulBase + ACMP_CR0 + (4 * ulComp); + + // + // Set the comp- input source + // + xHWREG(ulCRAddr) &= ~ACMP_CR_CN; + xHWREG(ulCRAddr) |= ulSource; +} + +//***************************************************************************** +// +//! \brief Enable the comparator hysteresis function. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index(0 - 1) of the comparator. +//! +//! This function enables hysteresis function of the comparator. +//! +//! \return None. +// +//***************************************************************************** +void +ACMPHysEnable(unsigned long ulBase, unsigned long ulComp) +{ + unsigned long ulCRAddr; + + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulComp >= 0) && (ulComp < 2)); + + // + // Get the corresponding CR register address + // + ulCRAddr = ulBase + ACMP_CR0 + (4 * ulComp); + + // + // Enable hysteresis function. The typical range is 20mV. + // + xHWREG(ulCRAddr) |= ACMP_CR_HYSEN; +} + +//***************************************************************************** +// +//! \brief Disable the comparator hysteresis function. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index(0 - 1) of the comparator. +//! +//! This function disables hysteresis function of the comparator. +//! +//! \return None. +// +//***************************************************************************** +void +ACMPHysDisable(unsigned long ulBase, unsigned long ulComp) +{ + unsigned long ulCRAddr; + + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulComp >= 0) && (ulComp < 2)); + + // + // Get the corresponding CR register address + // + ulCRAddr = ulBase + ACMP_CR0 + (4 * ulComp); + + // + // Enable hysteresis function. The typical range is 20mV. + // + xHWREG(ulCRAddr) &= ~ACMP_CR_HYSEN; + +} + +//***************************************************************************** +// +//! \brief Enable the comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index(0 - 1) of the comparator. +//! +//! This function enables comparator. +//! +//! \return None. +// +//***************************************************************************** +void +ACMPEnable(unsigned long ulBase, unsigned long ulComp) +{ + unsigned long ulCRAddr; + + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulComp >= 0) && (ulComp < 2)); + + // + // Get the corresponding CR register address + // + ulCRAddr = ulBase + ACMP_CR0 + (4 * ulComp); + + // + // Enable the comparator + // + xHWREG(ulCRAddr) |= ACMP_CR_CMPEN; +} + +//***************************************************************************** +// +//! \brief Disable the comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index(0 - 1) of the comparator. +//! +//! This function disables comparator. +//! +//! \return None. +// +//***************************************************************************** +void +ACMPDisable(unsigned long ulBase, unsigned long ulComp) +{ + unsigned long ulCRAddr; + + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulComp >= 0) && (ulComp < 2)); + + // + // Get the corresponding CR register address + // + ulCRAddr = ulBase + ACMP_CR0 + (4 * ulComp); + + // + // Disable the comparator + // + xHWREG(ulCRAddr) &= ~ACMP_CR_CMPEN; +} + +//***************************************************************************** +// +//! \brief Enable the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index(0 - 1) of the comparator. +//! +//! This function enables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +ACMPIntEnable(unsigned long ulBase, unsigned long ulComp) +{ + unsigned long ulCRAddr; + + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulComp >= 0) && (ulComp < 2)); + + // + // Get the corresponding CR register address + // + ulCRAddr = ulBase + ACMP_CR0 + (4 * ulComp); + + // + // Enable the comparator interrupt + // + xHWREG(ulCRAddr) |= ACMP_CR_CMPIE; + +} + +//***************************************************************************** +// +//! \brief Disable the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index(0 - 1) of the comparator. +//! +//! This function disables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +ACMPIntDisable(unsigned long ulBase, unsigned long ulComp) +{ + unsigned long ulCRAddr; + + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulComp >= 0) && (ulComp < 2)); + + // + // Get the corresponding CR register address + // + ulCRAddr = ulBase + ACMP_CR0 + (4 * ulComp); + + // + // Disable the comparator interrupt + // + xHWREG(ulCRAddr) &= ~ACMP_CR_CMPIE; +} + +//***************************************************************************** +// +//! \brief Get the current interrupt status. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index(0 - 1) of the comparator. +//! +//! This returns the interrupt status for the comparator. +//! +//! \return \b xtrue if the comp flag is asserted and \b xfalse if it is not +//! asserted. +// +//***************************************************************************** +xtBoolean +ACMPIntStatus(unsigned long ulBase, unsigned long ulComp) +{ + unsigned long ulStatus; + + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulComp >= 0) && (ulComp < 2)); + + // + // Get the comp flag + // + ulStatus = xHWREG(ulBase + ACMP_SR) & (1 << ulComp); + + return (ulStatus ? xtrue : xfalse); +} + +//***************************************************************************** +// +//! \brief Clear a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index(0 - 1) of the comparator. +//! +//! The comparator interrupt is cleared, so that it no longer asserts. This +//! fucntion must be called in the interrupt handler to keep the handler from +//! being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +void +ACMPIntClear(unsigned long ulBase, unsigned long ulComp) +{ + xASSERT((ulBase == ACMP_BASE)); + xASSERT((ulComp >= 0) && (ulComp < 2)); + + // + // Wirte 1 to clear the comp flag + // + xHWREG(ulBase + ACMP_SR) |= (1 << ulComp); +} + + +//***************************************************************************** +// +//! \brief Configures a comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulCompID is the ID(index) of the comparator to configure. +//! Refrence \ref xACMP_Comparator_IDs. +//! \param ulConfig is the configuration of the comparator. +//! +//! This function configures a comparator. The \e ulConfig parameter is the +//! result of a logical OR operation between the \b ACMP_ASRCP_xxx, +//! and \b ACMP_ASRCN_xxx values. +//! +//! The \b ACMP_ASRCP_xxx is determines the ACMP+ source, +//! values refrence \ref xACMP_Analog_Src_Positive. +//! +//! The \b ACMP_ASRCP_xxx is determines the ACMP- source: +//! values refrence \ref xACMP_Analog_Src_Negative. +//! +//! \return None. +// +//***************************************************************************** + +void xACMPConfigure(unsigned long ulBase, unsigned long ulCompID, + unsigned long ulConfig) +{ + ACMPNegativeSrcSet(ulBase, ulCompID, ulConfig); +} + +//***************************************************************************** +// +//! \brief Enable the comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulCompID is the ID of the comparator. +//! Refrence \ref xACMP_Comparator_IDs. +//! +//! This function enables a comparator. +//! +//! \return None. +// +//***************************************************************************** +void xACMPEnable(unsigned long ulBase, unsigned long ulCompID) +{ + ACMPEnable(ulBase, ulCompID); +} + +//***************************************************************************** +// +//! \brief Disable the comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulCompID is the ID of the comparator. +//! Refrence \ref xACMP_Comparator_IDs. +//! +//! This function disables a comparator. +//! +//! \return None. +// +//***************************************************************************** +void xACMPDisable(unsigned long ulBase, unsigned long ulCompID) +{ + ACMPDisable(ulBase, ulCompID); +} + +//***************************************************************************** +// +//! \brief Enable the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulCompID is the ID(index) of the comparator. +//! Refrence \ref xACMP_Comparator_IDs. +//! +//! This function enables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void xACMPIntEnable(unsigned long ulBase, unsigned long ulCompID) +{ + ACMPIntEnable(ulBase, ulCompID); +} + +//***************************************************************************** +// +//! \brief Disable the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulCompID is the ID(index) of the comparator. +//! Refrence \ref xACMP_Comparator_IDs. +//! +//! This function disables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void xACMPIntDisable(unsigned long ulBase, unsigned long ulCompID) +{ + ACMPIntDisable(ulBase, ulCompID); +} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/acmp.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/acmp.h index a63afc76..091b27a1 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/acmp.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/acmp.h @@ -67,14 +67,14 @@ extern "C" //***************************************************************************** // -//! \addtogroup M051_ACMP +//! \addtogroup NUC4xx_ACMP //! @{ // //***************************************************************************** //***************************************************************************** // -//! \addtogroup M051_ACMP_Analog_Src_negative M051 negative(ACMP-) Input Source +//! \addtogroup NUC4xx_ACMP_Analog_Src_negative NUC4xx negative(ACMP-) Input Source //! \brief Analog comparator negative input select. //! @{ // @@ -98,7 +98,7 @@ extern "C" //***************************************************************************** // -//! \addtogroup M051_ACMP_Comparator_IDs M051_ACMP Analog Comparator ID +//! \addtogroup NUC4xx_ACMP_Comparator_IDs NUC4xx_ACMP Analog Comparator ID //! \brief Analog Comparator ID (index). //! //! The ID index is always like 0-1, and so on. @@ -119,8 +119,8 @@ extern "C" //***************************************************************************** // -//! \addtogroup M051_ACMP_Exported_APIs M051 ACMP API -//! \brief M051 ACMP API Reference. +//! \addtogroup NUC4xx_ACMP_Exported_APIs NUC4xx ACMP API +//! \brief NUC4xx ACMP API Reference. //! @{ // //***************************************************************************** diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xadc.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/adc.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xadc.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/adc.c index 4c2db1dc..0b677816 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xadc.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/adc.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xadc.c +//! \file adc.c //! \brief Driver for the ADC Controller. //! \version V2.1.1.1 //! \date 6/28/2014 @@ -38,7 +38,7 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_adc.h" +#include "hw_adc.h" static xtEventCallback g_pfnADCHandlerCallbacks[2] = {0}; @@ -300,7 +300,7 @@ xADCIntCallbackInit(unsigned long ulBase, // //***************************************************************************** void -ADCIntHandler(void) +ADC_IRQHandler(void) { unsigned long ulBase = ADC0_BASE; unsigned long ulIntFlags; diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/adc.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/adc.h index 2679cf7c..e8f7ae7c 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/adc.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/adc.h @@ -1,6 +1,21 @@ #ifndef _NUC4XX_ADC_H_ #define _NUC4XX_ADC_H_ + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ADC +//! @{ +// +//***************************************************************************** + //***************************************************************************** // //! \addtogroup NUC4xx_ADC @@ -408,6 +423,17 @@ extern void ADCCompConfigure(unsigned long ulBase, unsigned long ulComp, // //***************************************************************************** +//***************************************************************************** +// +//! @} +// +//***************************************************************************** +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + //***************************************************************************** // //! @} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xcore.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/core.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xcore.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/core.c index 4a9c3aef..dc2cbebf 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xcore.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/core.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xcore.c +//! \file core.c //! \brief Instruction wrappers for special CPU instructions. //! Driver for the NVIC Interrupt Controller. //! Driver for the SysTick driver. diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xdma.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/dma.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xdma.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/dma.c index eb98b31b..709bf6f6 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xdma.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/dma.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xdma.c +//! \file dma.c //! \brief Driver for the DMA Controller. //! \version V2.1.1.1 //! \date 11/14/2011 @@ -38,7 +38,7 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_dma.h" +#include "hw_dma.h" typedef struct { @@ -341,6 +341,7 @@ xDMAChannelIntDisable(unsigned long ulChannelID, unsigned long ulIntFlags) xHWREG(DMA0_BASE + DMA_IER) &= ~(1 << ulChannelID); } + //***************************************************************************** // //! \brief Dynamic assign a channel through the request. diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/dma.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/dma.h index 7ffc2fc2..74a13cfc 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/dma.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/dma.h @@ -1,6 +1,21 @@ #ifndef _NUC4XX_DMA_H_ #define _NUC4XX_DMA_H_ + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup DMA +//! @{ +// +//***************************************************************************** + //***************************************************************************** // //! \addtogroup NUC4xx_DMA @@ -198,6 +213,17 @@ extern unsigned long DMARemainTransferCountGet(unsigned long ulChannelID); // //***************************************************************************** +//***************************************************************************** +// +//! @} +// +//***************************************************************************** +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + //***************************************************************************** // //! @} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xgpio.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/gpio.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xgpio.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/gpio.c index c4908fef..20791076 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xgpio.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/gpio.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xgpio.c +//! \file gpio.c //! \brief Driver for the GPIO controller //! \version V2.2.1.0 //! \date 11/15/2013 @@ -38,8 +38,8 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_gpio.h" -#include "xhw_sysctl.h" +#include "hw_gpio.h" +#include "hw_sysctl.h" int test0,test1; @@ -1885,7 +1885,7 @@ inline unsigned long xGPIOPinRead(unsigned long ulPort, unsigned long ulPins) // //***************************************************************************** inline void xGPIOPinWrite(unsigned long ulPort, unsigned long ulPins, - unsigned long ucVal) + unsigned char ucVal) { // // Check the arguments. diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/gpio.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/gpio.h index 382f815a..9f79f4cf 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/gpio.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/gpio.h @@ -396,6 +396,172 @@ extern "C" // //***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup GPIO_GP_Short_Pin NUC4xx General Purpose Short Pin +//! @{ +// +//***************************************************************************** +#define GPA0 GPIO_PORTA_BASE, GPIO_PIN_0 +#define GPA1 GPIO_PORTA_BASE, GPIO_PIN_1 +#define GPA2 GPIO_PORTA_BASE, GPIO_PIN_2 +#define GPA3 GPIO_PORTA_BASE, GPIO_PIN_3 +#define GPA4 GPIO_PORTA_BASE, GPIO_PIN_4 +#define GPA5 GPIO_PORTA_BASE, GPIO_PIN_5 +#define GPA6 GPIO_PORTA_BASE, GPIO_PIN_6 +#define GPA7 GPIO_PORTA_BASE, GPIO_PIN_7 +#define GPA8 GPIO_PORTA_BASE, GPIO_PIN_8 +#define GPA9 GPIO_PORTA_BASE, GPIO_PIN_9 +#define GPA10 GPIO_PORTA_BASE, GPIO_PIN_10 +#define GPA11 GPIO_PORTA_BASE, GPIO_PIN_11 +#define GPA12 GPIO_PORTA_BASE, GPIO_PIN_12 +#define GPA13 GPIO_PORTA_BASE, GPIO_PIN_13 +#define GPA14 GPIO_PORTA_BASE, GPIO_PIN_14 +#define GPA15 GPIO_PORTA_BASE, GPIO_PIN_15 + +#define GPB0 GPIO_PORTB_BASE, GPIO_PIN_0 +#define GPB1 GPIO_PORTB_BASE, GPIO_PIN_1 +#define GPB2 GPIO_PORTB_BASE, GPIO_PIN_2 +#define GPB3 GPIO_PORTB_BASE, GPIO_PIN_3 +#define GPB4 GPIO_PORTB_BASE, GPIO_PIN_4 +#define GPB5 GPIO_PORTB_BASE, GPIO_PIN_5 +#define GPB6 GPIO_PORTB_BASE, GPIO_PIN_6 +#define GPB7 GPIO_PORTB_BASE, GPIO_PIN_7 +#define GPB8 GPIO_PORTB_BASE, GPIO_PIN_8 +#define GPB9 GPIO_PORTB_BASE, GPIO_PIN_9 +#define GPB10 GPIO_PORTB_BASE, GPIO_PIN_10 +#define GPB11 GPIO_PORTB_BASE, GPIO_PIN_11 +#define GPB12 GPIO_PORTB_BASE, GPIO_PIN_12 +#define GPB13 GPIO_PORTB_BASE, GPIO_PIN_13 +#define GPB14 GPIO_PORTB_BASE, GPIO_PIN_14 +#define GPB15 GPIO_PORTB_BASE, GPIO_PIN_15 + +#define GPC0 GPIO_PORTC_BASE, GPIO_PIN_0 +#define GPC1 GPIO_PORTC_BASE, GPIO_PIN_1 +#define GPC2 GPIO_PORTC_BASE, GPIO_PIN_2 +#define GPC3 GPIO_PORTC_BASE, GPIO_PIN_3 +#define GPC4 GPIO_PORTC_BASE, GPIO_PIN_4 +#define GPC5 GPIO_PORTC_BASE, GPIO_PIN_5 +#define GPC6 GPIO_PORTC_BASE, GPIO_PIN_6 +#define GPC7 GPIO_PORTC_BASE, GPIO_PIN_7 +#define GPC8 GPIO_PORTC_BASE, GPIO_PIN_8 +#define GPC9 GPIO_PORTC_BASE, GPIO_PIN_9 +#define GPC10 GPIO_PORTC_BASE, GPIO_PIN_10 +#define GPC11 GPIO_PORTC_BASE, GPIO_PIN_11 +#define GPC12 GPIO_PORTC_BASE, GPIO_PIN_12 +#define GPC13 GPIO_PORTC_BASE, GPIO_PIN_13 +#define GPC14 GPIO_PORTC_BASE, GPIO_PIN_14 +#define GPC15 GPIO_PORTC_BASE, GPIO_PIN_15 + +#define GPD0 GPIO_PORTD_BASE, GPIO_PIN_0 +#define GPD1 GPIO_PORTD_BASE, GPIO_PIN_1 +#define GPD2 GPIO_PORTD_BASE, GPIO_PIN_2 +#define GPD3 GPIO_PORTD_BASE, GPIO_PIN_3 +#define GPD4 GPIO_PORTD_BASE, GPIO_PIN_4 +#define GPD5 GPIO_PORTD_BASE, GPIO_PIN_5 +#define GPD6 GPIO_PORTD_BASE, GPIO_PIN_6 +#define GPD7 GPIO_PORTD_BASE, GPIO_PIN_7 +#define GPD8 GPIO_PORTD_BASE, GPIO_PIN_8 +#define GPD9 GPIO_PORTD_BASE, GPIO_PIN_9 +#define GPD10 GPIO_PORTD_BASE, GPIO_PIN_10 +#define GPD11 GPIO_PORTD_BASE, GPIO_PIN_11 +#define GPD12 GPIO_PORTD_BASE, GPIO_PIN_12 +#define GPD13 GPIO_PORTD_BASE, GPIO_PIN_13 +#define GPD14 GPIO_PORTD_BASE, GPIO_PIN_14 +#define GPD15 GPIO_PORTD_BASE, GPIO_PIN_15 + +#define GPE0 GPIO_PORTE_BASE, GPIO_PIN_0 +#define GPE1 GPIO_PORTE_BASE, GPIO_PIN_1 +#define GPE2 GPIO_PORTE_BASE, GPIO_PIN_2 +#define GPE3 GPIO_PORTE_BASE, GPIO_PIN_3 +#define GPE4 GPIO_PORTE_BASE, GPIO_PIN_4 +#define GPE5 GPIO_PORTE_BASE, GPIO_PIN_5 +#define GPE6 GPIO_PORTE_BASE, GPIO_PIN_6 +#define GPE7 GPIO_PORTE_BASE, GPIO_PIN_7 +#define GPE8 GPIO_PORTE_BASE, GPIO_PIN_8 +#define GPE9 GPIO_PORTE_BASE, GPIO_PIN_9 +#define GPE10 GPIO_PORTE_BASE, GPIO_PIN_10 +#define GPE11 GPIO_PORTE_BASE, GPIO_PIN_11 +#define GPE12 GPIO_PORTE_BASE, GPIO_PIN_12 +#define GPE13 GPIO_PORTE_BASE, GPIO_PIN_13 +#define GPE14 GPIO_PORTE_BASE, GPIO_PIN_14 +#define GPE15 GPIO_PORTE_BASE, GPIO_PIN_15 + +#define GPF0 GPIO_PORTF_BASE, GPIO_PIN_0 +#define GPF1 GPIO_PORTF_BASE, GPIO_PIN_1 +#define GPF2 GPIO_PORTF_BASE, GPIO_PIN_2 +#define GPF3 GPIO_PORTF_BASE, GPIO_PIN_3 +#define GPF4 GPIO_PORTF_BASE, GPIO_PIN_4 +#define GPF5 GPIO_PORTF_BASE, GPIO_PIN_5 +#define GPF6 GPIO_PORTF_BASE, GPIO_PIN_6 +#define GPF7 GPIO_PORTF_BASE, GPIO_PIN_7 +#define GPF8 GPIO_PORTF_BASE, GPIO_PIN_8 +#define GPF9 GPIO_PORTF_BASE, GPIO_PIN_9 +#define GPF10 GPIO_PORTF_BASE, GPIO_PIN_10 +#define GPF11 GPIO_PORTF_BASE, GPIO_PIN_11 +#define GPF12 GPIO_PORTF_BASE, GPIO_PIN_12 +#define GPF13 GPIO_PORTF_BASE, GPIO_PIN_13 +#define GPF14 GPIO_PORTF_BASE, GPIO_PIN_14 +#define GPF15 GPIO_PORTF_BASE, GPIO_PIN_15 + +#define GPG0 GPIO_PORTG_BASE, GPIO_PIN_0 +#define GPG1 GPIO_PORTG_BASE, GPIO_PIN_1 +#define GPG2 GPIO_PORTG_BASE, GPIO_PIN_2 +#define GPG3 GPIO_PORTG_BASE, GPIO_PIN_3 +#define GPG4 GPIO_PORTG_BASE, GPIO_PIN_4 +#define GPG5 GPIO_PORTG_BASE, GPIO_PIN_5 +#define GPG6 GPIO_PORTG_BASE, GPIO_PIN_6 +#define GPG7 GPIO_PORTG_BASE, GPIO_PIN_7 +#define GPG8 GPIO_PORTG_BASE, GPIO_PIN_8 +#define GPG9 GPIO_PORTG_BASE, GPIO_PIN_9 +#define GPG10 GPIO_PORTG_BASE, GPIO_PIN_10 +#define GPG11 GPIO_PORTG_BASE, GPIO_PIN_11 +#define GPG12 GPIO_PORTG_BASE, GPIO_PIN_12 +#define GPG13 GPIO_PORTG_BASE, GPIO_PIN_13 +#define GPG14 GPIO_PORTG_BASE, GPIO_PIN_14 +#define GPG15 GPIO_PORTG_BASE, GPIO_PIN_15 + +#define GPH0 GPIO_PORTH_BASE, GPIO_PIN_0 +#define GPH1 GPIO_PORTH_BASE, GPIO_PIN_1 +#define GPH2 GPIO_PORTH_BASE, GPIO_PIN_2 +#define GPH3 GPIO_PORTH_BASE, GPIO_PIN_3 +#define GPH4 GPIO_PORTH_BASE, GPIO_PIN_4 +#define GPH5 GPIO_PORTH_BASE, GPIO_PIN_5 +#define GPH6 GPIO_PORTH_BASE, GPIO_PIN_6 +#define GPH7 GPIO_PORTH_BASE, GPIO_PIN_7 +#define GPH8 GPIO_PORTH_BASE, GPIO_PIN_8 +#define GPH9 GPIO_PORTH_BASE, GPIO_PIN_9 +#define GPH10 GPIO_PORTH_BASE, GPIO_PIN_10 +#define GPH11 GPIO_PORTH_BASE, GPIO_PIN_11 +#define GPH12 GPIO_PORTH_BASE, GPIO_PIN_12 +#define GPH13 GPIO_PORTH_BASE, GPIO_PIN_13 +#define GPH14 GPIO_PORTH_BASE, GPIO_PIN_14 +#define GPH15 GPIO_PORTH_BASE, GPIO_PIN_15 + +#define GPI0 GPIO_PORTI_BASE, GPIO_PIN_0 +#define GPI1 GPIO_PORTI_BASE, GPIO_PIN_1 +#define GPI2 GPIO_PORTI_BASE, GPIO_PIN_2 +#define GPI3 GPIO_PORTI_BASE, GPIO_PIN_3 +#define GPI4 GPIO_PORTI_BASE, GPIO_PIN_4 +#define GPI5 GPIO_PORTI_BASE, GPIO_PIN_5 +#define GPI6 GPIO_PORTI_BASE, GPIO_PIN_6 +#define GPI7 GPIO_PORTI_BASE, GPIO_PIN_7 +#define GPI8 GPIO_PORTI_BASE, GPIO_PIN_8 +#define GPI9 GPIO_PORTI_BASE, GPIO_PIN_9 +#define GPI10 GPIO_PORTI_BASE, GPIO_PIN_10 +#define GPI11 GPIO_PORTI_BASE, GPIO_PIN_11 +#define GPI12 GPIO_PORTI_BASE, GPIO_PIN_12 +#define GPI13 GPIO_PORTI_BASE, GPIO_PIN_13 +#define GPI14 GPIO_PORTI_BASE, GPIO_PIN_14 +#define GPI15 GPIO_PORTI_BASE, GPIO_PIN_15 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + //***************************************************************************** // //! \addtogroup NUC4xx_GPIO_Pin_Config NUC4xx GPIO Pin Config diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_acmp.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_acmp.h new file mode 100644 index 00000000..dffc9aeb --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_acmp.h @@ -0,0 +1,190 @@ +//***************************************************************************** +// +//! \file hw_acmp.h +//! \brief Macros used when accessing the comparator hardware. +//! \version V2.1.1.0 +//! \date 1/3/2012 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __XHW_ACMP_H__ +#define __XHW_ACMP_H__ + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ACMP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup NUC4xx_ACMP_Register NUC4xx Analog Comparator Register +//! \brief Here are the detailed info of ACMP registers. +//! +//! it contains: +//! - Register offset. +//! - detailed bit-field of the registers. +//! - Enum and mask of the registers. +//! . +//! Users can read or write the registers through xHWREG(). +//! +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup NUC4xx_ACMP_Register_Offset ACMP Register Offset(Map) +//! \brief Here is the ACMP register offset, users can get the register address +//! through ACMP_BASE + offset. +//! @{ +// +//***************************************************************************** + +// +//! Comparator0 Control Register +// +#define ACMP_CR0 0x00000000 + +// +//! Comparator1 Control Register +// +#define ACMP_CR1 0x00000004 + +// +//! Comparator Status Register +// +#define ACMP_SR 0x00000008 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup NUC4xx_ACMP_Register_CR Comparator Control Register(ACMP_CR0/1) +//! \brief Definition for the bit fields in the ACMP_O_CR0 or ACMP_O_CR1 register. +//! @{ +// +//***************************************************************************** + +// +//! Comparator0 negative input select +// +#define ACMP_CR_CN 0x00000010 + +// +//! Comparator0 Hysteresis Enable +// +#define ACMP_CR_HYSEN 0x00000004 + +// +//! Comparator0 Interrupt Enable +// +#define ACMP_CR_CMPIE 0x00000002 + +// +//! Comparator0 Enable +// +#define ACMP_CR_CMPEN 0x00000001 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup NUC4xx_ACMP_Register_SR Comparator Status Register(ACMP_SR) +//! \brief Definition for the bit fields in the ACMP_O_SR register. +//! @{ +// +//***************************************************************************** + +// +//! Comparator1 Output +// +#define ACMP_SR_CO1 0x00000008 + +// +//! Comparator0 Output +// +#define ACMP_SR_CO0 0x00000004 + +// +//! Comparator1 Flag +// +#define ACMP_SR_CMPF1 0x00000002 + +// +//! Comparator0 Flag +// +#define ACMP_SR_CMPF0 0x00000001 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +#endif // __XHW_ACMP_H__ + diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_adc.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_adc.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_adc.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_adc.h index 1b76e7f4..c42ea0a7 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_adc.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_adc.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_adc.h +//! \file hw_adc.h //! \brief Macros used when accessing the ADC hardware. //! \version V2.1.1.1 //! \date 11/14/2011 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_dma.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_dma.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_dma.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_dma.h index 4171d48e..799281c5 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_dma.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_dma.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_dma.h +//! \file hw_dma.h //! \brief Macros and defines used when accessing the DMA hardware. //! \version V2.1.1.1 //! \date 7/1/2014 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_gpio.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_gpio.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_gpio.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_gpio.h index 860ddc67..c0bb63b5 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_gpio.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_gpio.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_gpio.h +//! \file hw_gpio.h //! \brief Macros used when accessing the GPIO control hardware. //! \version V2.2.1.0 //! \date 11/15/2013 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_i2c.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_i2c.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_i2c.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_i2c.h index c711a75d..77582f3f 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_i2c.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_i2c.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_i2c.h +//! \file hw_i2c.h //! \brief Macros and defines used when accessing the I2C hardware. //! \version V2.1.1.1 //! \date 6/14/2014 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_pwm.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_pwm.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_pwm.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_pwm.h index 941c4ec7..d9eca9e2 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_pwm.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_pwm.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_pwm.h +//! \file hw_pwm.h //! \brief Macros and defines used when accessing the PWM hardware. //! \version V2.2.1.0 //! \date 11/15/2013 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_rtc.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_rtc.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_rtc.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_rtc.h index ab582f0d..93aa91ba 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_rtc.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_rtc.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_rtc.h +//! \file hw_rtc.h //! \brief Macros and defines used when accessing the RTC hardware. //! \version V2.2.1.0 //! \date 11/15/2013 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_spi.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_spi.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_spi.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_spi.h index 4bbf96a0..861500c6 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_spi.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_spi.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_spi.h +//! \file hw_spi.h //! \brief Macros used when accessing the SPI hardware. //! \version V2.2.1.0 //! \date 6/15/2014 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_sysctl.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_sysctl.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_sysctl.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_sysctl.h index b32614b1..ccaebe7b 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_sysctl.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_sysctl.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_sysctl.h +//! \file hw_sysctl.h //! \brief Macros used when accessing the system control hardware. //! \version V2.2.1.0 //! \date 6/15/2014 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_timer.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_timer.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_timer.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_timer.h index e8f65442..deb7e473 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_timer.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_timer.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_timer.h +//! \file hw_timer.h //! \brief Macros and defines used when accessing the TIMER hardware. //! \version V2.2.1.0 //! \date 11/15/2013 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_uart.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_uart.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_uart.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_uart.h index 74ffafa4..04947d63 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_uart.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_uart.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_uart.h +//! \file hw_uart.h //! \brief Macros used when accessing the UART hardware. //! \version V2.2.1.0 //! \date 6/15/2014 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_wdt.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_wdt.h similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_wdt.h rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_wdt.h index 293e1922..87f03060 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xhw_wdt.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/hw_wdt.h @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xhw_wdt.h +//! \file hw_wdt.h //! \brief Macros and defines used when accessing the WATCHDOG hardware. //! \version V2.2.1.0 //! \date 11/15/2013 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xi2c.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/i2c.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xi2c.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/i2c.c index 807116fa..7a5081aa 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xi2c.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/i2c.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xi2c.c +//! \file i2c.c //! \brief Driver for the I2C //! \version V2.1.1.1 //! \date 6/14/2014 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_i2c.h" +#include "hw_sysctl.h" +#include "hw_i2c.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/i2c.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/i2c.h index 8ead9723..62951daf 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/i2c.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/i2c.h @@ -1,6 +1,20 @@ #ifndef _NUC4XX_I2C_H_ #define _NUC4XX_I2C_H_ +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup I2C +//! @{ +// +//***************************************************************************** + //***************************************************************************** // //! \addtogroup NUC4xx_I2C @@ -417,4 +431,16 @@ extern xtBoolean I2CWakeupStatusGet(unsigned long ulBase); // //***************************************************************************** +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + #endif diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/lowlayer.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/lowlayer.h index 8ee1616c..28e7c506 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/lowlayer.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/lowlayer.h @@ -49,7 +49,7 @@ //***************************************************************************** // -//! \addtogroup NUC4xx_LowLayer +//! \addtogroup LowLayer //! @{ // //***************************************************************************** @@ -150,7 +150,7 @@ //***************************************************************************** // -//! \addtogroup STM32F1xx_Interrupt_Assignments STM32F1xx Interrupt Assignments +//! \addtogroup NUC4xx_Interrupt_Assignments NUC4xx Interrupt Assignments //! \brief Macro definitions for the fault/interrupt assignments. //! //! They can be used as ulInterrupt parameters with xIntEnable(), xIntDisable() diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xpwm.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/pwm.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xpwm.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/pwm.c index 4a2d4a7c..ad3c697b 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xpwm.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/pwm.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xpwm.c +//! \file pwm.c //! \brief Driver for the PWM //! \version V2.2.1.0 //! \date 11/15/2013 @@ -37,9 +37,9 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_gpio.h" -#include "xhw_sysctl.h" -#include "xhw_pwm.h" +#include "hw_gpio.h" +#include "hw_sysctl.h" +#include "hw_pwm.h" diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xrtc.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/rtc.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xrtc.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/rtc.c index 14a63455..681df708 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xrtc.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/rtc.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xrtc.c +//! \file rtc.c //! \brief Driver for the RTC //! \version V2.2.1.0 //! \date 11/15/2013 @@ -37,9 +37,9 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" +#include "hw_sysctl.h" #include "sysctl.h" -#include "xhw_rtc.h" +#include "hw_rtc.h" //***************************************************************************** @@ -272,7 +272,7 @@ xRTCConvertCounterToTime(xtTime *xtTime, unsigned long ultimeCounter) // //***************************************************************************** void -RTCIntHandler(void) +RTC_IRQHandler(void) { unsigned long ulEventFlags; diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xspi.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/spi.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xspi.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/spi.c index 1a9ac0d6..4da3299e 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xspi.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/spi.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xspi.c +//! \file spi.c //! \brief Driver for the SPI //! \version V2.2.1.0 //! \date 6/15/2014 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_spi.h" +#include "hw_sysctl.h" +#include "hw_spi.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/spi.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/spi.h index f2953b54..40b70c8f 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/spi.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/spi.h @@ -1,6 +1,20 @@ #ifndef _NUC4XX_SPI_H_ #define _NUC4XX_SPI_H_ +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup SPI +//! @{ +// +//***************************************************************************** + //***************************************************************************** // //! \addtogroup NUC4xx_SPI @@ -487,4 +501,16 @@ extern void SPIPDuadIODisable(unsigned long ulBase); // //***************************************************************************** +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + #endif diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xsysctl.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/sysctl.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xsysctl.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/sysctl.c index 881a3da3..3f64df81 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xsysctl.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/sysctl.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xsysctl.c +//! \file sysctl.c //! \brief Driver for the system controller //! \version V2.2.1.0 //! \date 6/15/2014 @@ -37,7 +37,7 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" +#include "hw_sysctl.h" static unsigned long s_ulExtClockMHz = 12; diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/sysctl.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/sysctl.h index 640363f9..55d1b45a 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/sysctl.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/sysctl.h @@ -1,6 +1,20 @@ #ifndef _NUC4XX_SYSCTL_H_ #define _NUC4XX_SYSCTL_H_ +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup SysCtl +//! @{ +// +//***************************************************************************** + //***************************************************************************** // //! \addtogroup NUC4xx_SysCtl @@ -857,4 +871,16 @@ extern void SysCtlHClockSet(unsigned long ulConfig); // //***************************************************************************** +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + #endif diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xtimer.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/timer.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xtimer.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/timer.c index d05b1800..88dc4348 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xtimer.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/timer.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xtimer.c +//! \file timer.c //! \brief Driver for the Timer //! \version V2.2.1.0 //! \date 11/15/2013 @@ -37,9 +37,9 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_gpio.h" -#include "xhw_sysctl.h" -#include "xhw_timer.h" +#include "hw_gpio.h" +#include "hw_sysctl.h" +#include "hw_timer.h" //***************************************************************************** // @@ -64,7 +64,7 @@ static unsigned long ulEXTClockFreq; // //***************************************************************************** void -TIMER0IntHandler(void) +TMR0_IRQHandler(void) { unsigned long ulBase = TIMER0_BASE; unsigned long ulTemp0,ulTemp1; @@ -96,7 +96,7 @@ TIMER0IntHandler(void) // //***************************************************************************** void -TIMER1IntHandler(void) +TMR1_IRQHandler(void) { unsigned long ulBase = TIMER1_BASE; unsigned long ulTemp0,ulTemp1; @@ -129,7 +129,7 @@ TIMER1IntHandler(void) // //***************************************************************************** void -TIMER2IntHandler(void) +TMR2_IRQHandler(void) { unsigned long ulBase = TIMER2_BASE; unsigned long ulTemp0,ulTemp1; @@ -162,7 +162,7 @@ TIMER2IntHandler(void) // //***************************************************************************** void -TIMER3IntHandler(void) +TMR3_IRQHandler(void) { unsigned long ulBase = TIMER3_BASE; unsigned long ulTemp0,ulTemp1; @@ -1277,9 +1277,9 @@ void xTimerPrescaleSet(unsigned long ulBase, unsigned long ulChannel, //! \return the Prescale Value will be get. // //***************************************************************************** -void xTimerPrescaleGet(unsigned long ulBase, unsigned long ulChannel) +unsigned long xTimerPrescaleGet(unsigned long ulBase, unsigned long ulChannel) { - TimerPrescaleGet(ulBase); + return TimerPrescaleGet(ulBase); } //***************************************************************************** @@ -1315,9 +1315,9 @@ void xTimerLoadSet(unsigned long ulBase, unsigned long ulChannel, //! \return the counter Value will be get. // //***************************************************************************** -void xTimerLoadGet(unsigned long ulBase, unsigned long ulChannel) +unsigned long xTimerLoadGet(unsigned long ulBase, unsigned long ulChannel) { - return; + return 0; } diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xuart.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/uart.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xuart.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/uart.c index 7ef5a582..bc020cfe 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xuart.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/uart.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xuart.c +//! \file uart.c //! \brief Driver for the UART //! \version V2.2.1.0 //! \date 6/15/2014 @@ -38,8 +38,8 @@ //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_uart.h" +#include "hw_sysctl.h" +#include "hw_uart.h" //***************************************************************************** // diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/uart.h b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/uart.h index 6baa211c..ca7827ed 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/uart.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/uart.h @@ -1,6 +1,20 @@ #ifndef _NUC4XX_UART_H_ #define _NUC4XX_UART_H_ +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup UART +//! @{ +// +//***************************************************************************** + //***************************************************************************** // //! \addtogroup NUC4xx_UART @@ -328,4 +342,15 @@ extern void UART485Config(unsigned long ulBase, unsigned long ulBaud, // //***************************************************************************** +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** #endif diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xwdt.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/wdt.c similarity index 99% rename from CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xwdt.c rename to CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/wdt.c index ad09e977..c4cd31e2 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/xwdt.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/libcox/wdt.c @@ -1,6 +1,6 @@ //***************************************************************************** // -//! \file xwdt.c +//! \file wdt.c //! \brief Driver for the WDT //! \version V2.2.1.0 //! \date 11/15/2013 @@ -37,8 +37,8 @@ // //***************************************************************************** #include "CoX.h" -#include "xhw_sysctl.h" -#include "xhw_wdt.h" +#include "hw_sysctl.h" +#include "hw_wdt.h" @@ -62,7 +62,7 @@ static xtEventCallback g_pfnWATCHDOGHandlerCallbacks[1]={0}; // //***************************************************************************** void -WDTIntHandler(void) +WDT_IRQHandler(void) { // // Clear the WDT INT Flag diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/pwm/example/led/src/led.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/pwm/example/led/src/led.c new file mode 100644 index 00000000..7f97fc4f --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/pwm/example/led/src/led.c @@ -0,0 +1,25 @@ +#include "CoX.h" + +void uartprinntf() +{ + xSysCtlClockSet(84000000, xSYSCTL_OSC_MAIN | xSYSCTL_XTAL_12MHZ); + xSysCtlDelay(10000); + + xSPinTypeUART(UART0RX,PG1); + xSPinTypeUART(UART0TX,PG2); + + xSysCtlPeripheralReset(xSYSCTL_PERIPH_UART0); + xSysCtlPeripheralEnable(xSYSCTL_PERIPH_UART0); + + // + // Config 8 bit word length, 1 stop bit, + // and none parity bit, receive FIFO 1 byte. + // + xUARTConfigSet(xUART0_BASE, 115200, (xUART_CONFIG_WLEN_8 | \ + xUART_CONFIG_STOP_1 | \ + xUART_CONFIG_PAR_NONE)); + + xUARTEnable(xUART0_BASE, (xUART_BLOCK_UART | xUART_BLOCK_TX | xUART_BLOCK_RX)); + + UARTBufferWrite(UART0_BASE, "NUC1xx.UART.BAUDRATE EXAMPLE \r\n", sizeof("NUC1xx.UART.BAUDRATE EXAMPLE \r\n")); +} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/pwm/example/led/src/main.c b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/pwm/example/led/src/main.c new file mode 100644 index 00000000..e8d4676a --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_NUC4xx/pwm/example/led/src/main.c @@ -0,0 +1,6 @@ +extern void uartprinntf(); + +int main() +{ + uartprinntf(); +} \ No newline at end of file diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xgpio.c b/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xgpio.c index 89d42a6c..03da12d7 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xgpio.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xgpio.c @@ -1191,6 +1191,27 @@ unsigned long GPIOPinToPort(unsigned long ulPort, unsigned long ulPin){ return ulPort; } +//***************************************************************************** +// +//! \brief Get the GPIO port from a short Pin. +//! +//! \param eShortPin is the base address of the GPIO port +//! +//! \note None. +//! +//! \return GPIO port address which is used by GPIO API. +// +//***************************************************************************** +unsigned long GPIOPinToPort(unsigned long ulPort, unsigned long ulPin){ + (void)ulPin; + // + // Check the arguments. + // + xASSERT(GPIOBaseValid(ulPort)); + + return ulPort; +} + //***************************************************************************** // //! \brief Get the GPIO pin number from a short Pin. @@ -1212,4 +1233,4 @@ GPIOPinToPin(unsigned long ulPort, unsigned long ulPin) xASSERT(GPIOBaseValid(ulPort)); return ulPin; -} \ No newline at end of file +} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xuart.c b/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xuart.c index 00d507c5..c80394fb 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xuart.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xuart.c @@ -1818,4 +1818,4 @@ UARTBusy(unsigned long ulBase) xASSERT(UARTBaseValid(ulBase)); return (!(xHWREG(ulBase + USART_SR) & USART_SR_TC)); -} \ No newline at end of file +} diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xuart.h b/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xuart.h index 6b8bbd03..e5180692 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xuart.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_STM32F1xx/libcox/xuart.h @@ -1969,3 +1969,1972 @@ extern void UARTModemControlClear(unsigned long ulBase, unsigned long ulControl) #endif // __xUART_H__ +======= +//***************************************************************************** +// +//! \file xuart.h +//! \brief Prototypes for the UART Driver. +//! \version V2.2.1.0 +//! \date 11/14/2011 +//! \author CooCox +//! \copy +//! +//! Copyright (c) 2011, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __xUART_H__ +#define __xUART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Lib +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup UART +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_Ints xUART Interrupt +//! \brief Values that show xUART Interrupt +//! \n +//! \section xUART_Ints_Section 1. Where to use this group +//! Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +//! as the ulIntFlags parameter, and returned from UARTIntStatus. +//! \n +//! \section xUART_Ints_CoX 2. CoX Port Details +//! \verbatim +//! +------------------------+----------------+------------------------+ +//! |xUART Interrupts | CoX | STM32F1xx | +//! |------------------------|----------------|------------------------| +//! |xUART_INT_ERROR | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_INT_RT | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_INT_TX | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_INT_RX | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_INT_DSR | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_INT_DCD | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_INT_CTS | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_INT_RI | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_INT_LMSB | Non-Mandatory | N | +//! +------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +// +//! All Error Interrupt Mask +// +#define xUART_INT_ERROR UART_INT_ERR + +// +//! Receive Timeout Interrupt Mask +// +#define xUART_INT_RT UART_INT_RTO + +// +//! Transmit Interrupt Mask +// +#define xUART_INT_TX UART_INT_TXE + +// +//! Receive Interrupt Mask +// +#define xUART_INT_RX UART_INT_RXNE + +// +//! DSR Modem Interrupt Mask +// +#define xUART_INT_DSR 0 + +// +//! DCD Modem Interrupt Mask +// +#define xUART_INT_DCD 0 + +// +//! CTS Modem Interrupt Mask +// +#define xUART_INT_CTS UART_INT_CTS + +// +//! RI Modem Interrupt Mask +// +#define xUART_INT_RI 0 + +// +//! LIN Mode Sync Break Interrupt Mask +// +#define xUART_INT_LMSB UART_INT_LIN + + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_Event_Flag xUART Event Flags +//! \brief Values that show xUART Event Flags +//! \n +//! \section xUART_Event_Flag_Section 1. Where to use this group +//! Uart Event/Error Flag, Used by IntHandle's Event Callback Function as +//! ulMsgParam parmeter. User Callback function can user this to detect what +//! event happened. +//! \n +//! \section xUART_Event_Flag_CoX 2. CoX Port Details +//! \verbatim +//! +------------------------+----------------+------------------------+ +//! |xUART Events | CoX | STM32F1xx | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_TX | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_RX | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_OE | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_FE | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_RT | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_PE | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_DSR | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_DCD | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_CTS | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_RI | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_EVENT_LMSB | Non-Mandatory | N | +//! +------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +// +//! Transmit Event Mask +// +#define xUART_EVENT_TX UART_INT_TXE + +// +//! Receive Event Mask +// +#define xUART_EVENT_RX UART_INT_RXNE + +// +//! Overrun Error Event Mask +// +#define xUART_EVENT_OE UART_RXERROR_OVERRUN + +// +//! Parity Error Event Mask +// +#define xUART_EVENT_PE UART_RXERROR_PARITY + +// +//! Framing Error Event Mask +// +#define xUART_EVENT_FE UART_RXERROR_FRAMING + +// +//! Receive Timeout Event Mask +// +#define xUART_EVENT_RT 0 + +// +//! DSR Modem Event Mask +// +#define xUART_EVENT_DSR 0 + +// +//! DCD Modem Event Mask +// +#define xUART_EVENT_DCD 0 + +// +//! CTS Modem Event Mask +// +#define xUART_EVENT_CTS 0 + +// +//! RI Modem Event Mask +// +#define xUART_EVENT_RI 0 + +// +//! LIN Mode Sync Break Event Mask +// +#define xUART_EVENT_LMSB 0 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_Error xUART Error +//! \brief Values that show xUART Error +//! \n +//! \section xUART_Event_Flag_Section 1. Where to use this group +//! Values returned from xUARTRxErrorGet(). +//! \n +//! \section xUART_Event_Flag_CoX 2. CoX Port Details +//! \verbatim +//! +------------------------+----------------+------------------------+ +//! |xUART Error | CoX | STM32F1xx | +//! |------------------------|----------------|------------------------| +//! |xUART_RXERROR_OVERRUN | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_RXERROR_BREAK | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_RXERROR_PARITY | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_RXERROR_FRAMING | Mandatory | Y | +//! +------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +#define xUART_RXERROR_OVERRUN UART_RXERROR_OVERRUN +#define xUART_RXERROR_BREAK UART_RXERROR_BREAK +#define xUART_RXERROR_PARITY UART_RXERROR_PARITY +#define xUART_RXERROR_FRAMING UART_RXERROR_FRAMING + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_Frame_Configs xUART Frame Configuration +//! \brief Values that show xUART Frame Configuration +//! \n +//! \section xUART_Frame_Configs_Section 1. Where to use this group +//! Uart Data Frame Configs. Such as Word Length, Parity, Stop bit. +//! Values that can be passed to xUARTConfig as the ulConfig parameter +//! and returned by UARTConfigGetExpClk in the pulConfig parameter. +//! Additionally, the UART_CONFIG_PAR_* subset can be passed to +//! UARTParityModeSet as the ulParity parameter, and are returned by +//! UARTParityModeGet. +//! \n +//! \section xUART_Frame_Configs_CoX 2. CoX Port Details +//! \verbatim +//! +------------------------+----------------+------------------------+ +//! |xUART Frame Config | CoX | STM32F1xx | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_WLEN_MASK | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_WLEN_n | Mandatory | xUART_CONFIG_WLEN_9 | +//! | | |------------------------| +//! | | | xUART_CONFIG_WLEN_8 | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_PAR_MASK | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_PAR_NONE | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_PAR_EVEN | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_PAR_ODD | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_PAR_ONE | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_PAR_ZERO | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_STOP_MASK | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_STOP_1 | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_STOP_2 | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_STOP_0_5 | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_CONFIG_STOP_1_5 | Non-Mandatory | N | +//! +------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** +// +// Mask for extracting word length +// +#define xUART_CONFIG_WLEN_MASK UART_CONFIG_WLEN_MASK + +// +//! 9 bit data +// +#define xUART_CONFIG_WLEN_9 UART_CONFIG_WLEN_9 + +// +//! 8 bit data +// +#define xUART_CONFIG_WLEN_8 UART_CONFIG_WLEN_8 + +// +//! Mask for extracting stop bits +// +#define xUART_CONFIG_STOP_MASK UART_CONFIG_STOP_MASK + +// +//! One stop bit +// +#define xUART_CONFIG_STOP_1 UART_CONFIG_STOP_ONE + +// +//! Two stop bits +// +#define xUART_CONFIG_STOP_2 UART_CONFIG_STOP_TWO + +#define xUART_CONFIG_STOP_0_5 0 +#define xUART_CONFIG_STOP_1_5 0 + +// +//! Mask for extracting parity +// +#define xUART_CONFIG_PAR_MASK UART_CONFIG_PAR_MASK + +// +//! No parity +// +#define xUART_CONFIG_PAR_NONE UART_CONFIG_PAR_NONE + +// +//! Even parity +// +#define xUART_CONFIG_PAR_EVEN UART_CONFIG_PAR_EVEN + +// +//! Odd parity +// +#define xUART_CONFIG_PAR_ODD UART_CONFIG_PAR_ODD + +// +//! Parity bit is one / marked +// +#define xUART_CONFIG_PAR_ONE UART_CONFIG_PAR_ONE + +// +//! Parity bit is zero / space +// +#define xUART_CONFIG_PAR_ZERO UART_CONFIG_PAR_ZERO + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_IrDA_Mode xUART IrDA Mode +//! \brief Values that show xUART IrDA Mode +//! \n +//! \section xUART_IrDA_Mode_Section 1. Where to use this group +//! Uart IrDA mode that con be passed to UARTIrDAConfig as the +//! ulMode parameter. +//! \n +//! \section xUART_IrDA_Mode_CoX 2. CoX Port Details +//! \verbatim +//! +-------------------------+----------------+------------------------+ +//! |xUART IrDA Mode | CoX | STM32F1xx | +//! |-------------------------|----------------|------------------------| +//! |xUART_IRDA_MODE_NORMAL | Non-Mandatory | Y | +//! |-------------------------|----------------|------------------------| +//! |xUART_IRDA_MODE_LOW_POWER| Non-Mandatory | Y | +//! +-------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +// +//! IrDA Normal Mode +// +#define xUART_IRDA_MODE_NORMAL 0x00000000 + +// +//! IrDA Low-Power Mode +// +#define xUART_IRDA_MODE_LOW_POWER \ + 0x00000004 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_Enable_Blocks xUART Enable Blocks +//! \brief Values that show xUART Enable Blocks +//! \n +//! \section xUART_Enable_Blocks_Section 1. Where to use this group +//! Uart logic blocks that can be passed to UARTEnable() or UARTDisable() as +//! the ulBlock parameter. +//! \n +//! \section xUART_Enable_Blocks_CoX 2. CoX Port Details +//! \verbatim +//! +------------------------+----------------+------------------------+ +//! |xUART Enable Block | CoX | STM32F1xx | +//! |------------------------|----------------|------------------------| +//! |xUART_BLOCK_UART | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_BLOCK_RX | Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_BLOCK_TX | Mandatory | Y | +//! +------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +// +//! Uart logic block +// +#define xUART_BLOCK_UART 0x00002000 + +// +//! Uart transmit logic block +// +#define xUART_BLOCK_TX 0x00000008 + +// +//! uart receive logic block +// +#define xUART_BLOCK_RX 0x00000004 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_FIFO_Rx_Tiggle_Level xUART FIFO Rx Tiggle Level +//! \brief Values that show xUART FIFO Rx Tiggle Level +//! \n +//! \section xUART_FIFO_Rx_Tiggle_Level_Section 1. Where to use this group +//! Values that can be passed to UARTFIFORxLevelSet as the ulRxLevel parameter. +//! \n +//! \section xUART_FIFO_Rx_Tiggle_Level_CoX 2. CoX Port Details +//! \verbatim +//! +------------------------+----------------+------------------------+ +//! |FIFO Rx Tiggle Level | CoX | STM32F1xx | +//! |------------------------|----------------|------------------------| +//! |xUART_FIFO_RX_n | Non-Mandatory | N | +//! | | |------------------------| +//! | | | N | +//! | | |------------------------| +//! | | | N | +//! | | |------------------------| +//! | | | N | +//! | | |------------------------| +//! | | | N | +//! | | |------------------------| +//! | | | N | +//! | | |------------------------| +//! | | | N | +//! +------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +// +//! (1 character) +// +#define xUART_FIFO_RX_1 0 + +// +//! (4 character) +// +#define xUART_FIFO_RX_4 0 + +// +//! (8 character) +// +#define xUART_FIFO_RX_8 0 + +// +//! (14 character) +// +#define xUART_FIFO_RX_14 0 + +// +//! (30 character) +// +#define xUART_FIFO_RX_30 0 + +// +//! (46 character) +// +#define xUART_FIFO_RX_46 0 + +// +//! (62 character) +// +#define xUART_FIFO_RX_62 0 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_Modem_Output xUART Modem Output +//! \brief Values that show xUART Modem Output +//! \n +//! \section xUART_Modem_Output_Section 1. Where to use this group +//! Values that can be passed to UARTModemControlSet(), UARTModemControlClear() +//! or returned from UARTModemControlGet(). +//! \n +//! \section xUART_Modem_Output_CoX 2. CoX Port Details +//! \verbatim +//! +------------------------+----------------+------------------------+ +//! |xUART Modem Output | CoX | STM32F1xx | +//! |------------------------|----------------|------------------------| +//! |xUART_OUTPUT_RTS | Non-Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_OUTPUT_DTR | Non-Mandatory | N | +//! +------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +#define xUART_OUTPUT_RTS UART_OUTPUT_RTS_SET + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_Modem_Intput xUART Modem Input +//! \brief Values that show xUART Modem Input +//! \n +//! \section xUART_Modem_Intput_Section 1. Where to use this group +//! Values that can be returned from UARTModemStatusGet(). +//! \n +//! \section xUART_Modem_Intput_CoX 2. CoX Port Details +//! \verbatim +//! +------------------------+----------------+------------------------+ +//! |xUART Modem Input | CoX | STM32F1xx | +//! |------------------------|----------------|------------------------| +//! |xUART_INPUT_CTS | Non-Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_INPUT_RI | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_INPUT_DCD | Non-Mandatory | N | +//! |------------------------|----------------|------------------------| +//! |xUART_INPUT_DSR | Non-Mandatory | N | +//! +------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +#define xUART_INPUT_CTS UART_INPUT_CTS_L + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + + +//***************************************************************************** +// +//! \addtogroup xUART_Flow_Control xUART Flow Control +//! \brief Values that show xUART Flow Control +//! \n +//! \section xUART_Flow_Control_Section 1. Where to use this group +//! Values that can be passed to UARTFlowControlSet() or returned from +//! UARTFlowControlGet(). +//! \n +//! \section xUART_Flow_Control_CoX 2. CoX Port Details +//! \verbatim +//! +------------------------+----------------+------------------------+ +//! |xUART Flow Control | CoX | STM32F1xx | +//! |------------------------|----------------|------------------------| +//! |xUART_FLOWCONTROL_TX | Non-Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_FLOWCONTROL_RX | Non-Mandatory | Y | +//! |------------------------|----------------|------------------------| +//! |xUART_FLOWCONTROL_NONE | Non-Mandatory | Y | +//! +------------------------+----------------+------------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +#define xUART_FLOWCONTROL_TX UART_FLOWCONTROL_TX +#define xUART_FLOWCONTROL_RX UART_FLOWCONTROL_RX +#define xUART_FLOWCONTROL_NONE UART_FLOWCONTROL_NONE + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_LIN_Config xUART LIN Configuration +//! \brief Values that show xUART LIN Configuration +//! \n +//! \section xUART_LIN_Config_Section 1. Where to use this group +//! Values that can be passed to xUARTLINConfig(). +//! \n +//! \section xUART_LIN_Config_CoX 2. CoX Port Details +//! \verbatim +//! +-----------------------------+----------------+-------------------+ +//! |xUART LIN Configuration | CoX | STM32F1xx | +//! |-----------------------------|----------------|-------------------| +//! |xUART_LIN_MODE_MASK | Non-Mandatory | N | +//! |-----------------------------|----------------|-------------------| +//! |xUART_LIN_MODE_MASTER | Non-Mandatory | N | +//! |-----------------------------|----------------|-------------------| +//! |xUART_LIN_MODE_SLAVE | Non-Mandatory | N | +//! |-----------------------------|----------------|-------------------| +//! |xUART_LIN_SYNC_BREAK_LEN_MASK| Non-Mandatory | Y | +//! |-----------------------------|----------------|-------------------| +//! |xUART_LIN_SYNC_BREAK_LEN_10 | Non-Mandatory | Y | +//! |-----------------------------|----------------|-------------------| +//! |xUART_LIN_SYNC_BREAK_LEN_11 | Non-Mandatory | Y | +//! |-----------------------------|----------------|-------------------| +//! |xUART_LIN_SYNC_BREAK_LEN_15 | Non-Mandatory | N | +//! |-----------------------------|----------------|-------------------| +//! |xUART_LIN_SYNC_BREAK_LEN_16 | Non-Mandatory | N | +//! +-----------------------------+----------------+-------------------+ +//! \endverbatim +//! @{ +// +//***************************************************************************** + +#define xUART_LIN_SYNC_BREAK_LEN_MASK \ + UART_CONFIG_BKFL_MASK + +#define xUART_LIN_SYNC_BREAK_LEN_10 \ + UART_CONFIG_BKFL_10 + +#define xUART_LIN_SYNC_BREAK_LEN_11 \ + UART_CONFIG_BKFL_11 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUART_Exported_APIs xUART API +//! \brief UART API Reference. +//! \section xUART_Exported_APIs_Port CoX Port Details +//! \verbatim +//! +------------------------+----------------+-----------+ +//! |xUART API | CoX | STM32F1xx | +//! |------------------------|----------------|-----------| +//! |xUARTConfigSet | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTEnable | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTDisable | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTFIFOEnable | Non-Mandatory | N | +//! |------------------------|----------------|-----------| +//! |xUARTFIFODisable | Non-Mandatory | N | +//! |------------------------|----------------|-----------| +//! |xUARTFIFORxLevelSet | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTCharsAvail | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTSpaceAvail | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTCharGetNonBlocking | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTCharGet | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTCharPutNonBlocking | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTCharPut | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTBusy | Non-Mandatory | N | +//! |------------------------|----------------|-----------| +//! |xUARTIntEnable | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTIntCallbackInit | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTIntDisable | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTRxErrorGet | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTRxErrorClear | Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTModemControlSet | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTModemControlClear | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTModemControlGet | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTModemStatusGet | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTFlowControlSet | Non-Mandatory | N | +//! |------------------------|----------------|-----------| +//! |xUARTFlowControlGet | Non-Mandatory | N | +//! |------------------------|----------------|-----------| +//! |xUARTIrDAConfig | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTIrDAEnable | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTIrDADisable | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTLINConfig | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTLINEnable | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! |xUARTLINDisable | Non-Mandatory | Y | +//! |------------------------|----------------|-----------| +//! \endverbatim +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets the configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the UART for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter and the data +//! format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_9, +//! \b xUART_CONFIG_WLEN_8. +//! \b xUART_CONFIG_STOP_1 and \b xUART_CONFIG_STOP_2 select one or two stop +//! bits (respectively). \b xUART_CONFIG_PAR_NONE, \b xUART_CONFIG_PAR_EVEN, +//! \b xUART_CONFIG_PAR_ODD, \b xUART_CONFIG_PAR_ONE, and +//! \b xUART_CONFIG_PAR_ZERO select the parity mode (no parity bit, +//! even parity bit, odd parity bit, parity bit always one, and parity bit +//! always zero, respectively). +//! +//! \return None. +// +//***************************************************************************** + +#define xUARTConfigSet(ulBase, ulBaud, ulConfig) \ + UARTConfigSet(ulBase, ulBaud, ulConfig) + + +//***************************************************************************** +// +//! \brief Enables transmitting or receiving. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulBlock is the block to enable. it is the logical OR of +//! these values: \b xUART_BLOCK_TX, \b xUART_BLOCK_RX. +//! +//! Sets the UARTEN, or TXE or RXE bits. +//! +//! \note Do nothing in UART,In IrDA and LIN mode will set the Tx or Rx enable +//! +//! \return None. +// +//***************************************************************************** +#define xUARTEnable(ulBase, ulBlock) \ + UARTEnable(ulBase, ulBlock) + +//***************************************************************************** +// +//! \brief Disables transmitting or receiving. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulBlock is the block to disable. it is the logical OR of +//! these values: \b xUART_BLOCK_UART, \b xUART_BLOCK_TX, \b xUART_BLOCK_RX. +//! +//! Waits for the end ofransmission of the current character, +//! Clears the UARTEN or TXE or RXE bits. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTDisable(ulBase, ulBlock) + +//***************************************************************************** +// +//! \brief Enables the transmit and receive FIFOs. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTFIFOEnable(ulBase) 0 + +//***************************************************************************** +// +//! \brief Disables the transmit and receive FIFOs. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \note Do nothing in STM32F1xx +//! +//! \return None. +// +//***************************************************************************** +#define xUARTFIFODisable(ulBase) 0 + +//***************************************************************************** +// +//! \brief Sets the Rx FIFO level at which interrupts are generated. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulRxLevel is the receive FIFO interrupt level +//! +//! \note Do nothing in STM32F1xx +//! +//! \return None. +// +//***************************************************************************** +#define xUARTFIFORxLevelSet(ulBase, ulRxLevel) \ \ + UARTFIFOTriggerLevelSet(ulBase, ulRxLevel) + +//***************************************************************************** +// +//! \brief Determines if there are any characters in the receive FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \note Do nothing in STM32F1xx +//! +//! \return Returns \b true if there is data in the receive FIFO or \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +#define xUARTCharsAvail(ulBase) \ + UARTFIFORxIsEmpty(ulBase) + +//***************************************************************************** +// +//! \brief Determines if there is any space in the transmit FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \note Do nothing in STM32F1xx +//! +//! \return Returns \b true if there is space available in the transmit FIFO +//! or \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +#define xUARTSpaceAvail(ulBase) \ + UARTFIFOTxIsEmpty(ulBase) + + +//***************************************************************************** +// +//! \brief Receives a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. +//! +//! This function replaces the original UARTCharNonBlockingGet() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 is returned if there are no characters present in the +//! receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +#define xUARTCharGetNonBlocking(ulBase) \ + UARTCharGetNonBlocking(ulBase) + +//***************************************************************************** +// +//! \brief Waits for a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function waits until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. +// +//***************************************************************************** +#define xUARTCharGet(ulBase) \ + UARTCharGet(ulBase) + +//***************************************************************************** +// +//! \brief Sends a character to the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Writes the character \e ucData to the transmit FIFO for the specified port. +//! This function does not block, so if there is no space available, then a +//! \b false is returned, and the application must retry the function later. +//! +//! This function replaces the original UARTCharNonBlockingPut() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO or \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +#define xUARTCharPutNonBlocking(ulBase, ucData) \ + UARTCharPutNonBlocking(ulBase, ucData) + +//***************************************************************************** +// +//! \brief Waits to send a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Sends the character \e ucData to the transmit FIFO for the specified port. +//! If there is no space available in the transmit FIFO, this function waits +//! until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTCharPut(ulBase, ucData) \ + UARTCharPut(ulBase, ucData) + +//***************************************************************************** +// +//! \brief Determines whether the UART transmitter is busy or not. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \b false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \return Returns \b true if the UART is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +#define xUARTBusy(ulBase) + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b xUART_INT_ERROR - All Error interrupt +//! - \b xUART_INT_RT - Receive Timeout interrupt +//! - \b xUART_INT_TX - Transmit interrupt +//! - \b xUART_INT_RX - Receive interrupt +//! +//! \return None. +// +//***************************************************************************** +#define xUARTIntEnable(ulBase, ulIntFlags) \ + UARTIntEnable(ulBase, ulIntFlags) + +//***************************************************************************** +// +//! \brief Init interrupts callback for the specified UART Port. +//! +//! \param ulPort is the base address of the UART port. +//! \param xtI2CCallback is callback for the specified UART Port. +//! +//! Init interrupts callback for the specified UART Port. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTIntCallbackInit(ulBase, xtUARTCallback) \ + UARTIntCallbackInit(ulBase, xtUARTCallback) + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to UARTIntEnable(). +//! +//! - \b xUART_INT_ERROR - All Error interrupt +//! - \b xUART_INT_RT - Receive Timeout interrupt +//! - \b xUART_INT_TX - Transmit interrupt +//! - \b xUART_INT_RX - Receive interrupt +//! +//! \return None. +// +//***************************************************************************** +#define xUARTIntDisable(ulBase, ulIntFlags) \ + UARTIntDisable(ulBase, ulIntFlags) + +//***************************************************************************** +// +//! \brief Gets current receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \return Returns a logical OR combination of the receiver error flags, +//! \b xUART_RXERROR_FRAMING, \b xUART_RXERROR_PARITY, \b xUART_RXERROR_BREAK +//! and \b xUART_RXERROR_OVERRUN. +// +//***************************************************************************** +#define xUARTRxErrorGet(ulBase) \ + UARTRxErrorGet(ulBase) + +//***************************************************************************** +// +//! \brief Clears all reported receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function is used to clear all receiver error conditions reported via +//! UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTRxErrorClear(ulBase) \ + UARTRxErrorClear(ulBase) + +//***************************************************************************** +// +//! \brief Sets the states of the DTR and/or RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulControl is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! Sets the states of the DTR or RTS modem handshake outputs from the UART. +//! +//! The \e ulControl parameter is the logical OR of any of the following: +//! +//! - \b xUART_OUTPUT_RTS - The Modem Control RTS signal +//! +//! \note It is not available on UART4 and UART5. +//! +//! \return None. +// +//***************************************************************************** + +#define xUARTModemControlSet(ulBase, ulControl) \ + UARTModemControlSet(ulBase, ulControl) + +//***************************************************************************** +// +//! \brief Clears the states of the DTR and/or RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulControl is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! Clears the states of the DTR or RTS modem handshake outputs from the UART. +//! +//! The \e ulControl parameter is the logical OR of any of the following: +//! +//! - \b xUART_OUTPUT_RTS - The Modem Control RTS signal +//! +//! \note It is not available on UART4 and UART5 +//! +//! \return None. +// +//***************************************************************************** +#define xUARTModemControlClear(ulBase, ulControl) \ + UARTModemControlClear(ulBase, ulControl) + +//***************************************************************************** +// +//! \brief Gets the states of the DTR and RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Returns the current states of each of the two UART modem control signals, +//! DTR and RTS. +//! +//! \note It is not available on UART4 and UART5 +//! +//! \return Returns the states of the handshake output signals. This will be a +//! logical logical OR combination of values \b xUART_OUTPUT_RTS +//! where the presence of each flag indicates that the +//! associated signal is asserted. +// +//***************************************************************************** +#define xUARTModemControlGet(ulBase, ulControl) \ + UARTModemControlGet(ulBase, ulControl) + +//***************************************************************************** +// +//! \brief Gets the states of the RI, DCD, DSR and CTS modem status signals. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Returns the current states of each of the four UART modem status signals, +//! RI, DCD, DSR and CTS. +//! +//! \note It is not available on UART4 and UART5 +//! +//! \return Returns the states of the handshake output signals. This will be a +//! logical logical OR combination of values \b xUART_INPUT_CTS, where the +//! presence of each flag indicates that the associated signal is asserted. +// +//***************************************************************************** +#define xUARTModemStatusGet(ulBase) \ + UARTModemStatusGet(ulBase) + +//***************************************************************************** +// +//! \brief Sets the UART hardware flow control mode to be used. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulMode indicates the flow control modes to be used. This is a +//! logical OR combination of values \b xUART_FLOWCONTROL_TX and \b +//! xUART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) +//! flow control or \b xUART_FLOWCONTROL_NONE to disable hardware flow control. +//! +//! Sets the required hardware flow control modes. If \e ulMode contains +//! flag \b xUART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS +//! signal is asserted. If \e ulMode contains flag \b xUART_FLOWCONTROL_RX, +//! the RTS output is controlled by the hardware and is asserted only when +//! there is space available in the receive FIFO. If no hardware flow control +//! is required, xUART_FLOWCONTROL_NONE should be passed. +//! +//! \note The availability of hardware flow control varies with the STM32F1xx +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTFlowControlSet(ulBase, ulMode) 0 + +//***************************************************************************** +// +//! \brief Returns the UART hardware flow control mode currently in use. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Returns the current hardware flow control mode. +//! +//! \note The availability of hardware flow control varies with the STM32F1xx +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns the current flow control mode in use. This is a +//! logical OR combination of values \b xUART_FLOWCONTROL_TX if transmit +//! (CTS) flow control is enabled and \b xUART_FLOWCONTROL_RX if receive (RTS) +//! flow control is in use. If hardware flow control is disabled, \b +//! xUART_FLOWCONTROL_NONE will be returned. +// +//***************************************************************************** +#define xUARTFlowControlGet(ulBase) 0 + +//***************************************************************************** +// +//! \brief Enables SIR (IrDA) mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! \param ulMode is the IrDA mode. +//! +//! This function configures the UART IrDA for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter, the data +//! format in the \e ulConfig parameter, and the ulMode is provided in the +//! \e ulMode parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b xUART_CONFIG_WLEN_9, +//! \b xUART_CONFIG_WLEN_8. +//! select from eight to five data bits per byte (respectively). +//! \bX UART_CONFIG_STOP_1 and \b xUART_CONFIG_STOP_2 select one or two stop +//! bits (respectively). \b xUART_CONFIG_PAR_NONE, \b xUART_CONFIG_PAR_EVEN, +//! \b xUART_CONFIG_PAR_ODD, \b xUART_CONFIG_PAR_ONE, and +//! \b xUART_CONFIG_PAR_ZERO select the parity mode (no parity bit, +//! even parity bit, odd parity bit, parity bit always one, and +//! parity bit always zero, respectively). +//! +//! The \e ulMode parameter can be values: +//! - \b xUART_IRDA_MODE_NORMAL - IrDA normal mode +//! - \b xUART_IRDA_MODE_LOW_POWER - low power mpde +//! +//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices. +//! +//! \return None. +// +//***************************************************************************** +extern void xUARTIrDAConfig(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig, unsigned long ulMode); + +//***************************************************************************** +// +//! \brief Enables SIR (IrDA) mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Enables the SIREN control bit for IrDA mode on the UART. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTIrDAEnable(ulBase) \ + UARTEnableIrDA(ulBase) + +//***************************************************************************** +// +//! \brief Disables SIR (IrDA) mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Clears the SIREN (IrDA) bits. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTIrDADisable(ulBase) \ + UARTDisableIrDA(ulBase) + +//***************************************************************************** +// +//! \brief Open LIN mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulConfig is the Config of the UART port in LIN mode. +//! +//! Open the LIN mode for the UART. +//! +//! The \e ulConfig parameter is the logical OR of three values: the LIN Tx or Rx +//! Mode, the LIN Break Field Length. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTLINConfig(ulBase, ulBaud, ulConfig) \ + UARTLINConfig(ulBase, ulBaud, ulConfig) + +//***************************************************************************** +// +//! \brief Enables LIN Function mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Enables the SIREN control bit for LIN Function on the UART. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTLINEnable(ulBase) \ + UARTEnableLIN(ulBase) + +//***************************************************************************** +// +//! \brief Disables LIN Function mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Clears the LIN Function bits. +//! +//! \return None. +// +//***************************************************************************** +#define xUARTLINDisable(ulBase) \ + UARTDisableLIN(ulBase) + + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_INT_Type STM32F1xx UART Interrupt Type +//! Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +//! as the ulIntFlags parameter, and returned from UARTIntStatus. +//! @{ +// +//***************************************************************************** + +// +//! PE interrupt +// +#define UART_INT_PE 0x00010100 + +// +//! TXE interrupt +// +#define UART_INT_TXE 0x00800080 + +// +//! Transmission complete interrupt +// +#define UART_INT_TC 0x00400040 + +// +//! RXNE interrupt +// +#define UART_INT_RXNE 0x00200020 + +// +//! IDLE interrupt +// +#define UART_INT_IDLE 0x00100010 + +// +//! LIN break detection interrupt +// +#define UART_INT_LIN 0x01001020 + +// +//! Error interrupt +// +#define UART_INT_ERR 0x000E2001 + +// +//! CTS interrupt +// +#define UART_INT_CTS 0x02002400 + + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_Line_Config STM32F1xx UART Line Configuration +//! Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter +//! and returned by UARTConfigGetExpClk in the pulConfig parameter. +//! Additionally, the UART_CONFIG_PAR_* subset can be passed to +//! UARTParityModeSet as the ulParity parameter, and are returned by +//! UARTParityModeGet. +//! @{ +// +//***************************************************************************** + +// +//! Mask for extracting word length +// +#define UART_CONFIG_WLEN_MASK 0x00001000 + +// +//! 8 bit data +// +#define UART_CONFIG_WLEN_8 0x00000000 + +// +//! 9 bit data +// +#define UART_CONFIG_WLEN_9 0x00001000 + +// +//! Mask for extracting stop bits +// +#define UART_CONFIG_STOP_MASK 0x00003000 + +// +//! One stop bit +// +#define UART_CONFIG_STOP_ONE 0x00000000 + +// +//! Two stop bits +// +#define UART_CONFIG_STOP_TWO 0x00002000 + +// +//! 0.5 stop bits +// +#define UART_CONFIG_STOP_0P5 0x00001000 + +// +//! 1.5 stop bits +// +#define UART_CONFIG_STOP_1P5 0x00003000 + +// +//! Mask for extracting parity +// +#define UART_CONFIG_PAR_MASK 0x00000600 + +// +//! No parity +// +#define UART_CONFIG_PAR_NONE 0x00000000 + +// +//! Even parity +// +#define UART_CONFIG_PAR_EVEN 0x00000400 + +// +//! Odd parity +// +#define UART_CONFIG_PAR_ODD 0x00000600 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_Enable_Blocks STM32F1xx UART Enable Blocks +//! Uart logic blocks that can be passed to UARTEnable or UARTDisable as +//! the ulBlock parameter. +//! @{ +// +//***************************************************************************** + +// +//! Uart block +// +#define UART_BLOCK_UART 0x00002000 + +// +//! Uart transmit block +// +#define UART_BLOCK_TX 0x00000008 + +// +//! uart receive block +// +#define UART_BLOCK_RX 0x00000004 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_Clock_Config STM32F1xx UART clock Configuration +//! Values that can be passed to UARTClockConfig as the ulClkConfig parameter. +//! @{ +// +//***************************************************************************** + +// +//! Clock pin enable +// +#define UART_CLK_EN 0x00000800 + +// +//! Clock pin disabled +// +#define UART_CLK_DIS 0x00000000 + +// +//! Steady low value on CK pin outside transmission window. +// +#define UART_CPOL_LOW 0x00000800 + +// +//! Steady high value on CK pin outside transmission window. +// +#define UART_CPOL_HIGH 0x00000400 + +// +//! The first clock transition is the first data capture edge. +// +#define UART_CPHA_1EDHGE 0x00000000 + +// +//! The second clock transition is the first data capture edge. +// +#define UART_CPHA_2EDHGE 0x00000200 + +// +//! The clock pulse of the last data bit is output to the CK pin +// +#define UART_LASTBIT_EN 0x00000100 + +// +//! The clock pulse of the last data bit is not output to the CK pin +// +#define UART_LASTBIT_DIS 0x00000000 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_DMA_Flag STM32F1xx UART DMA Flag +//! Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +//! @{ +// +//***************************************************************************** + +// +//! Enable DMA for transmit +// +#define UART_DMA_TX 0x00000080 + +// +//! Enable DMA for receive +// +#define UART_DMA_RX 0x00000040 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_SMARTCARD_Flag STM32F1xx UART Smartcard Flag +//! Values that can be passed to UARTSmartCardEnable(). +//! @{ +// +//***************************************************************************** + +// +//! Enable Smartcard for transmit +// +#define UART_SC_TX 0x00000080 + +// +//! Enable Smartcard for receive +// +#define UART_SC_RX 0x00000040 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_SYN_CONFIG STM32F1xx UART synchronous mode configuration +//! Values that can be passed to UARTSynModeSet(). +//! @{ +// +//***************************************************************************** + +// +//! Clock polarity +// +#define UART_SYN_CPOL 0x00000400 + +// +//! Clock phase +// +#define UART_SYN_CPHA 0x00000200 + +// +//! Last bit clock pulse +// +#define UART_SYN_LBCL 0x00000100 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_Wake_Up STM32F1xx UART Wake Up +//! Values that can be passed to UARTWakeUpConfig(). +//! @{ +// +//***************************************************************************** + +// +//! WakeUp by an idle line detection +// +#define UART_WAKEUP_IDLE 0x00000000 + +// +//! WakeUp by an address mark +// +#define UART_WAKEUP_ADDRESS 0x00000800 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_Modem_Mode STM32F1xx UART Modem Mode +//! Values that can be passed to UARTModemSet(). +//! @{ +// +//***************************************************************************** + +// +//! RTS +// +#define UART_MODEM_RTS 0x00000100 + +// +//! CTS +// +#define UART_MODEM_CTS 0x00000200 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_Flow_Control STM32F1xx UART Flow Control +//! Values that can be passed to UARTFlowControlSet() or returned from +//! UARTFlowControlGet(). +//! @{ +// +//***************************************************************************** + +// +//! RTS enable +// +#define UART_FLOWCONTROL_TX 0x00000100 + +// +//! CTS enable +// +#define UART_FLOWCONTROL_RX 0x00000200 + +// +//! RTS CTS disable +// +#define UART_FLOWCONTROL_NONE 0x00000000 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_Error STM32F1xx UART Error +//! Values returned from UARTRxErrorGet(). +//! @{ +// +//***************************************************************************** + +// +//! Overrun error +// +#define UART_RXERROR_OVERRUN 0x00000008 + +// +//! Noise error flag +// +#define UART_RXERROR_NE 0x00000004 + +// +//! Parity error +// +#define UART_RXERROR_PARITY 0x00000001 + +// +//! Framing error +// +#define UART_RXERROR_FRAMING 0x00000002 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_LIN_Config STM32F1xx UART LIN Configuration +//! Values that can be passed to UARTLINConfig as the ulConfig parameter +//! @{ +// +//***************************************************************************** + +// +//! Mask for LIN Break Field Length +// +#define UART_CONFIG_BKFL_MASK 0x00000020 + +// +//! LIN Break Field Length 10 +// +#define UART_CONFIG_BKFL_10 0x00000000 + +// +//! LIN Break Field Length 11 +// +#define UART_CONFIG_BKFL_11 0x00000020 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_IrDA_Mode STM32F1xx UART IrDA mode Configuration +//! Values that can be passed to UARTIrDAConfig as the ulMode parameter +//! @{ +// +//***************************************************************************** + +// +// IrDA Mode Mask +// +#define UART_IRDA_MODE_MASK 0x80000000 + +// +//! IrDA low-power mode +// +#define UART_IRDA_MODE_LPM 0x80000000 + +// +//! Normal mode +// +#define UART_IRDA_MODE_NORMAL 0x00000000 + +// +// IrDA Mode Prescaler value Mask +// +#define UART_IRDA_PRES_MASK 0x000000FF + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup STM32F1xx_UART_Exported_APIs STM32F1xx UART API +//! \brief STM32F1xx UART API Reference. +//! @{ +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTEnable(unsigned long ulBase, unsigned long ulBlock); +extern void UARTDisable(unsigned long ulBase, unsigned long ulBlock); +extern void UARTEnableIrDA(unsigned long ulBase); +extern void UARTDisableIrDA(unsigned long ulBase); +extern void UARTIrDAConfig(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig, unsigned long ulMode, unsigned long ulPrescaler); +extern void UARTEnableLIN(unsigned long ulBase); +extern void UARTDisableLIN(unsigned long ulBase); +extern void UARTLINConfig(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern xtBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBufferWrite(unsigned long ulBase, unsigned char *ucBuffer, + unsigned long ulLength); +extern void UARTBreakCtl(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntCallbackInit(unsigned long ulBase, + xtEventCallback xtUARTCallback); +extern unsigned long UARTIntStatus(unsigned long ulBase); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTRxErrorGet(unsigned long ulBase); +extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void UARTAddressSet(unsigned long ulBase, unsigned long ulAddress); +extern void UARTWakeUpConfig(unsigned long ulBase, unsigned long ulWakeup); +extern void UARTGuardTimeSet(unsigned long ulBase, unsigned long ulGuardTime); +extern void UARTHalfDuplexEnable(unsigned long ulBase); +extern void UARTHalfDuplexDisable(unsigned long ulBase); +extern void UARTSmartCardEnable(unsigned long ulBase, unsigned long ulSCMode); +extern void UARTSmartCardDisable(unsigned long ulBase); +extern void UARTSynModeSet(unsigned long ulBase, unsigned long ulConfig); +extern void UARTSYNDisable(unsigned long ulBase); +extern void UARTModemControlSet(unsigned long ulBase, unsigned long ulControl); +extern void UARTModemControlClear(unsigned long ulBase, unsigned long ulControl); +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __xUART_H__ + +>>>>>>> 155e4b7604743f3cd44fb23da94084f98bd4fa27 diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/mainpage.md b/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/mainpage.md index a84d0cfd..185b8570 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/mainpage.md +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/mainpage.md @@ -26,7 +26,10 @@ CoX develop manual - \ref xSPI_page - \ref xPWM_page - \ref xADC_page + - [xRTC](@ref xRTC_document_md) . + +more please refer to [xGPIO interrupt number config ID in MD file](@ref xRTC_document_md). Features ---------- diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/xGPIO_General_Pin_IDs.md b/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/xGPIO_General_Pin_IDs.md index 1f687151..bf1507ac 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/xGPIO_General_Pin_IDs.md +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/xGPIO_General_Pin_IDs.md @@ -5,7 +5,7 @@ -xGPIO document +xGPIO document {#xGPIO_document_md} ====== 本篇文章主è¦è®²è§£ï¼ŒCoX.GPIO的规范，包括： - å®å‚æ•° @@ -558,6 +558,8 @@ NUC4xx GPIO UART MAP | | UART5RX | PB10 PD15 | + + xGPIO DAC MAP {#CoX_DAC_MAP} ========= diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/xrtc.md b/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/xrtc.md index 435e6056..d1a6cf8e 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/xrtc.md +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/doc/xrtc.md @@ -1,33 +1,33 @@ -\page xRTC_page xRTC page + [TOC] -xRTC document +xRTC document {#xRTC_document_md} ====== -±¾ÆªÎÄÕÂÖ÷Òª½²½â£¬CoX.RTCµÄ¹æ·¶£¬°üÀ¨£º -- ºê²ÎÊý - - ²ÎÊýµÄÒâÒ壿 - - ´«¸øÄĸöAPI£¿ - - ²ÎÊýµÄÐÎʽ - - ¸÷¸ö³§ÉÌϵÁеÄʵÏÖÇé¿ö -- APIº¯Êý - - º¯ÊýÔ­ÐÍ - - ÐèҪʵÏֵŦÄܺÍÿ¸ö²ÎÊýµÄÒâÒå - - º¯ÊýÖ®¼äµÄ×éºÏÓ¦Ó㨹¦ÄÜ£© +本篇文章主è¦è®²è§£ï¼ŒCoX.RTC的规范，包括： +- å®å‚æ•° + - å‚æ•°çš„æ„义？ + - 传给哪个API？ + - å‚æ•°çš„å½¢å¼ + - å„个厂商系列的实现情况 +- API函数 + - 函数原型 + - 需è¦å®žçŽ°çš„功能和æ¯ä¸ªå‚æ•°çš„æ„义 + - 函数之间的组åˆåº”用（功能） xRTC Interrupt Type {#xRTC_INT_Type_md} ================ -Õâ¸ö²ÎÊý¶¨ÒåÖжϵÄÀàÐÍ£º¶ÔÓÚRTCÀ´Ëµ£¬ÖжÏÓÐÈýÖÖÀàÐÍ£¬Ê±¼äÖжϣ¨CoX½«Õâ¸öÖж϶¨ÒåΪһÃ룩¡¢ÄÖÖÓÖжϺÍÒç³öÖжϡ£ -²ÎÊýµÄÐÎʽΪ¹Ì¶¨µÄºêÃû³Æ£º +这个å‚数定义中断的类型：对于RTCæ¥è¯´ï¼Œä¸­æ–­æœ‰ä¸‰ç§ç±»åž‹ï¼Œæ—¶é—´ä¸­æ–­ï¼ˆCoX将这个中断定义为一秒）ã€é—¹é’Ÿä¸­æ–­å’Œæº¢å‡ºä¸­æ–­ã€‚ +å‚æ•°çš„å½¢å¼ä¸ºå›ºå®šçš„å®å称： - \ref xRTC_INT_SECOND - \ref xRTC_INT_ALARM - \ref xRTC_INT_OVERFLOW -Õâ¸ö²ÎÊýÊÇ API \ref xRTCIntEnable() ºÍ API \ref xRTCIntDisable() µÄ ulIntType²ÎÊý¡£ -ÓÐЩϵÁÐʵÏÖÁËÕâÈý¸ö¹¦ÄÜ£¬È»ºóÓÐЩϵÁÐÖ»ÓÐÇ°Á½¸ö¹¦ÄÜ£¬ÏÂÃæÊǸ÷¸öϵÁеÄʵÏÖµÄÇé¿ö¡£ +这个å‚数是 API \ref xRTCIntEnable() å’Œ API \ref xRTCIntDisable() çš„ ulIntTypeå‚数。 +有些系列实现了这三个功能，然åŽæœ‰äº›ç³»åˆ—åªæœ‰å‰ä¸¤ä¸ªåŠŸèƒ½ï¼Œä¸‹é¢æ˜¯å„个系列的实现的情况。 | xRTC Interrupts |LPC17xx|STM32F1xx|NUC1xx/NUC2xx/M051/Mini51|KLx |HT32F125x|HT32F175x| |:----------------:|:-----:|:-------:|:-----------------------:|:-------:|:-------:|:-------:| @@ -38,16 +38,16 @@ xRTC Interrupt Type {#xRTC_INT_Type_md} xRTC Interrupt Event {#xRTC_INT_Event_md} ======== -Õâ¸ö²ÎÊýÊÇÖжϵÄʼþ£¬µ±RTC·¢Éúʱ ÓÃÕâ¸ö²ÎÊýÀ´ÅÐ¶Ï µ±Ç°µÄ ÖжÏÔ´ ÊÇʲô¡£ -ÖжÏʼþºÍÀàÐÍ£¬»ù±¾±£³ÖÒ»Ö¡£ -²ÎÊýµÄÐÎʽΪ¹Ì¶¨µÄºêÃû³Æ£º +这个å‚数是中断的事件，当RTCå‘生时 用这个å‚æ•°æ¥åˆ¤æ–­ 当å‰çš„ ä¸­æ–­æº æ˜¯ä»€ä¹ˆã€‚ +中断事件和类型，基本ä¿æŒä¸€è‡´ã€‚ +å‚æ•°çš„å½¢å¼ä¸ºå›ºå®šçš„å®å称： - \ref xRTC_EVENT_SECOND - \ref xRTC_EVENT_ALARM - \ref xRTC_EVENT_OVERFLOW -Õâ¸ö½«Ôڻص÷º¯ÊýÖÐʹÓã¬ÒÔÅжÏÒѾ­·¢ÉúµÄÖжÏÔ´¡£ +这个将在回调函数中使用，以判断已ç»å‘生的中断æºã€‚ -ÓÐЩϵÁÐʵÏÖÁËÕâÈý¸ö¹¦ÄÜ£¬È»ºóÓÐЩϵÁÐÖ»ÓÐÇ°Á½¸ö¹¦ÄÜ£¬ÏÂÃæÊǸ÷¸öϵÁеÄʵÏÖµÄÇé¿ö¡£ +有些系列实现了这三个功能，然åŽæœ‰äº›ç³»åˆ—åªæœ‰å‰ä¸¤ä¸ªåŠŸèƒ½ï¼Œä¸‹é¢æ˜¯å„个系列的实现的情况。 | xRTC Event |LPC17xx|STM32F1xx|NUC1xx/NUC2xx/M051/Mini51|KLx |HT32F125x|HT32F175x| |:------------------:|:-----:|:-------:|:-----------------------:|:-------:|:-------:|:-------:| @@ -58,9 +58,9 @@ xRTC Interrupt Event {#xRTC_INT_Event_md} xRTC Day Week {#xRTC_Day_Week_md} ======== -Õâ×éºêÓÃÓÚ¶¨ÒåÐÇÆÚ£¬Ã¶¾Ù ÐÇÆÚÈÕ µ½ ÐÇÆÚÁù +这组å®ç”¨äºŽå®šä¹‰æ˜ŸæœŸï¼Œæžšä¸¾ 星期日 到 星期六 -²ÎÊýµÄÐÎʽΪ¹Ì¶¨µÄºêÃû³Æ£º +å‚æ•°çš„å½¢å¼ä¸ºå›ºå®šçš„å®å称： - \ref xRTC_WEEK_SUNDAY - \ref xRTC_WEEK_MONDAY - \ref xRTC_WEEK_TUESDAY @@ -69,7 +69,7 @@ xRTC Day Week {#xRTC_Day_Week_md} - \ref xRTC_WEEK_FRIDAY - \ref xRTC_WEEK_SATURDAY -Õâ×éºì½«×÷Ϊ xtTime.ulWDay ²ÎÊý´«Èë º¯Êý \ref xRTCTimeRead(), \ref xRTCTimeWrite() +这组红将作为 xtTime.ulWDay å‚æ•°ä¼ å…¥ 函数 \ref xRTCTimeRead(), \ref xRTCTimeWrite() | tTime.ulWDay | All Series | |--------------------------|------------------------| @@ -85,19 +85,19 @@ xRTC Day Week {#xRTC_Day_Week_md} xRTC Year Offset {#xRTC_Year_Offset_md} ======= -ÓÉÓÚÓÐЩ RTC ʵ¼ÊÉϾÍÊÇÒ»¸ö 32 λµÄ¼ÆÊýÆ÷£¬ËùÒÔΪÁ˽«Õâ¸ö¹í¼ÆÊýÆ÷ת»¯Îª¾ßÌåµÄʱ¼ä£¬ÐèÒª -Ò»¸öת»»¹ý³Ì£¬¶ø 32 λÊý¾ÝÄܱíʾµÄÄê·ÝÓÐÏÞ£¨×î¶àÄܱíʾ136Äê¶à£©£¬ËùÒÔΪÁËÄܱíʾµ±Ç°¹«Àú£¨±ÈÈç2014£© -ÐèÒª¶¨ÒåÒ»¸ö ¹Ì¶¨Æ«ÒÆÁ¿¡£±ÈÈ磬ƫÒÆÁ¿Îª2000£¬Ôòµ±¼ÆÊýֵΪ14Äêʱ£¬±íʾ2014Äê1ÔÂ1ÈÕ0ʱ0·Ö0Ãë¡£ -Õâ¸öÆ«Òƽ«Ó°Ïì 32 λµÄ¼ÆÊýÆ÷ ÀàÐÍRTCµÄʱ¼äµ÷½Ú·¶Î§¡£ +由于有些 RTC 实际上就是一个 32 ä½çš„è®¡æ•°å™¨ï¼Œæ‰€ä»¥ä¸ºäº†å°†è¿™ä¸ªé¬¼è®¡æ•°å™¨è½¬åŒ–ä¸ºå…·ä½“çš„æ—¶é—´ï¼Œéœ€è¦ +一个转æ¢è¿‡ç¨‹ï¼Œè€Œ 32 ä½æ•°æ®èƒ½è¡¨ç¤ºçš„年份有é™ï¼ˆæœ€å¤šèƒ½è¡¨ç¤º136年多），所以为了能表示当å‰å…¬åŽ†ï¼ˆæ¯”如2014） +需è¦å®šä¹‰ä¸€ä¸ª 固定å移é‡ã€‚比如，å移é‡ä¸º2000，则当计数值为14年时，表示2014å¹´1月1æ—¥0æ—¶0分0秒。 +这个åç§»å°†å½±å“ 32 ä½çš„计数器 类型RTC的时间调节范围。 -²ÎÊýµÄÐÎʽΪ¹Ì¶¨µÄºêÃû³Æ£º +å‚æ•°çš„å½¢å¼ä¸ºå›ºå®šçš„å®å称： - \ref xRTC_YEAR_OFFSET -ʱ¼äµÄµ÷½Ú·ÖΪ xRTC_YEAR_OFFSET <= time <= xRTC_YEAR_OFFSET+136 +时间的调节分为 xRTC_YEAR_OFFSET <= time <= xRTC_YEAR_OFFSET+136 -CoX ¶¨ÒåÁËÒ»¸öĬÈÏֵΪ2000 +CoX 定义了一个默认值为2000 -ÏÂÃæÊǸ÷¸öϵÁеÄʵÏÖÇé¿ö +下é¢æ˜¯å„个系列的实现情况 | xRTC_Year_Offset | LPC17xx |STM32F1xx|NUC1xx/NUC2xx/M051/Mini51|KLx |HT32F125x|HT32F175x| |--------------------------|---------|:-------:|:-----------------------:|:-------:|:-------:|:-------:| | xRTC_YEAR_OFFSET | N | **Y** | **Y** | **Y** | **Y** | **Y** | @@ -105,9 +105,9 @@ CoX xRTC Time Type {#xRTC_Time_Type_md} ====== -ÔÚÉèÖà µ±Ç°Ê±¼ä ºÍ ÉèÖà ÄÖÖÓµÄʱºò£¬ÓÉÓÚÉèÖ÷½Ê½Ò»Ñù£¬ËùÒÔ ÓÃÁËÒ»¸ö²ÎÊý±íʾ£¬µ±Ç°¾¿¾¹ÊÇʲô²Ù×÷£¨ÊÇÔÚÉèÖà ʱ¼ä »¹ÊÇÄÖÖÓ£©£¿ +在设置 当å‰æ—¶é—´ å’Œ 设置 闹钟的时候，由于设置方å¼ä¸€æ ·ï¼Œæ‰€ä»¥ 用了一个å‚数表示，当å‰ç©¶ç«Ÿæ˜¯ä»€ä¹ˆæ“作（是在设置 时间 还是闹钟）？ -²ÎÊýµÄÐÎʽΪ¹Ì¶¨µÄºêÃû³Æ£º +å‚æ•°çš„å½¢å¼ä¸ºå›ºå®šçš„å®å称： - \ref xRTC_TIME_CURRENT - \ref xRTC_TIME_ALARM @@ -119,7 +119,7 @@ xRTC Time Type {#xRTC_Time_Type_md} xRTC Exported Types {#xRTC_Exported_Types_md} ========== -CoX ΪRTC¶¨ÒåÁËÒ»¸ö xtime µÄ½á¹¹Ì壬¸Ã½á¹¹Ìå°üº¬ÁË×é³É ʱ¼äµÄ ÄêÔÂÈÕ Ê±·ÖÃë ºÍÐÇÆÚ¡£ +CoX 为RTC定义了一个 xtime 的结构体，该结构体包å«äº†ç»„æˆ æ—¶é—´çš„ 年月日 时分秒 和星期。 xRTC API {#xRTC_Exported_APIs_md} @@ -136,9 +136,9 @@ xRTC API {#xRTC_Exported_APIs_md} | \ref xRTCStart | Y | | \ref xRTCStop | Y | -\note xRTCTimeInit ÔÚʵÏÖµÄʱºòÒª½«RTC µÄʱ¼ä Öжϼä¸ôÉèÖÃΪһÃë¡£ +\note xRTCTimeInit 在实现的时候è¦å°†RTC 的时间 中断间隔设置为一秒。 -\note ÓÐЩϵÁÐ ²»ÐèÒª xRTCStart ºÍ xRTCStop£¬ÄÇô ÕâÁ½¸öº¯Êý¿ÕʵÏÖ¼´¿É¡£ +\note 有些系列 ä¸éœ€è¦ xRTCStart å’Œ xRTCStop，那么 这两个函数空实现å³å¯ã€‚ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/CoX.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/CoX.h index 1c59e700..b46e37db 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/CoX.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/CoX.h @@ -2,8 +2,8 @@ // //! \file CoX.h //! \brief Include all the h files in this file. -//! \version V2.1.1.1 -//! \date 11/14/2011 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xacmp.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xacmp.h index 14aadca9..7f5fced0 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xacmp.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xacmp.h @@ -2,8 +2,8 @@ // //! \file xacmp.h //! \brief Defines and Macros for the analog comparator API. -//! \version V2.2.1.0 -//! \date 7/22/2014 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xadc.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xadc.h index 3e4e738c..0bd36cc6 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xadc.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xadc.h @@ -2,8 +2,8 @@ // //! \file xadc.h //! \brief Defines and Macros for ADC API. -//! \version V3.0 -//! \date 7/16/2014 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xcore.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xcore.h index 6f99851e..a1c7b129 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xcore.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xcore.h @@ -4,8 +4,8 @@ //! \brief Prototypes for the CPU instruction wrapper functions. //! \brief Prototypes for the NVIC Interrupt Controller Driver. //! \brief Prototypes for the SysTick driver. -//! \version V2.2 -//! \date 5/17/2012 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdebug.c b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdebug.c index cb21e8d7..d1b8ccf2 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdebug.c +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdebug.c @@ -2,9 +2,8 @@ // //! \file xdebug.h //! \brief Drivers for assisting debug of the peripheral library. -//! \version V2.1.1.0 -//! \date 11/14/2011 -//! \todo Update this time information. +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdebug.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdebug.h index 764ecd63..af28edd0 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdebug.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdebug.h @@ -2,8 +2,8 @@ // //! \file xdebug.h //! \brief Macros for assisting debug of the peripheral library. -//! \version V2.1.1.0 -//! \date $CURRENTTIME$ +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copyright //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdma.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdma.h index 48c1e726..4ab7c284 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdma.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xdma.h @@ -2,8 +2,8 @@ // //! \file xdma.h //! \brief Defines and Macros for DMA API. -//! \version V2.2.1.0 -//! \date 11/14/2011 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! @@ -235,6 +235,8 @@ extern "C" #define xDMA_REQUEST_ADC_RX DMA_REQUEST_ADC_RX +#define xDMA_REQUEST_DAC_TX DMA_REQUEST_DAC_TX + // ADC, timer will be added in the further //***************************************************************************** diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xgpio.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xgpio.h index fb4e1ab2..6db767ca 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xgpio.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xgpio.h @@ -2,9 +2,8 @@ // //! \file xgpio.h //! \brief Prototypes for the GPIO Driver. -//! \brief Prototypes for the AFIO Driver. -//! \version V2.1.1.1 -//! \date 11/14/2011 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! @@ -51,7 +50,7 @@ // have a C binding. // //***************************************************************************** -#ifdef __cplusplu +#ifdef __cplusplus extern "C" { #endif @@ -471,389 +470,6 @@ extern "C" // //***************************************************************************** -//***************************************************************************** -// -//! \addtogroup xGPIO_Short_Pin xGPIO Short Pin ID -//! -//! \section xGPIO_Short_Pin_S1 1. Where to use this group -//! The following values define the short pin argument(dShortPin) -//! to several of the \b XPinTypexxx APIs and all the API which have -//! a eShortPin argument. -//! Such as -//! \ref xGPIOSPinRead() -//! \ref xGPIOSPinWrite() -//! -//! \section xGPIO_Short_Pin_CoX 2.CoX Port Details -//! ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -//! +-------------------------+----------------+ -//! | xGPIO Short Pin ID | CoX | -//! |-------------------------|----------------| -//! | PXn | Mandatory | -//! | (X = A/B/...) | | -//! | (n = 0/1/...) | | -//! | | | -//! | | | -//! | | | -//! | | | -//! +-------------------------+----------------+ -//! ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -//! more please refer to [xGPIO Short Pin ID in MD file](@ref xGPIO_Short_Pin_md). -//! @{ -// -//***************************************************************************** - -//! PortA -//! For LPC17xx mcu, Port A is equal to Port 0 -#define PA0 PA0 -#define PA1 PA1 -#define PA2 PA2 -#define PA3 PA3 -#define PA4 PA4 -#define PA5 PA5 -#define PA6 PA6 -#define PA7 PA7 -#define PA8 PA8 -#define PA9 PA9 -#define PA10 PA10 -#define PA11 PA11 -#define PA12 PA12 -#define PA13 PA13 -#define PA14 PA14 -#define PA15 PA15 -#define PA16 PA16 -#define PA17 PA17 -#define PA18 PA18 -#define PA19 PA19 -#define PA20 PA20 -#define PA21 PA21 -#define PA22 PA22 -#define PA23 PA23 -#define PA24 PA24 -#define PA25 PA25 -#define PA26 PA26 -#define PA27 PA27 -#define PA28 PA28 -#define PA29 PA29 -#define PA30 PA30 -#define PA31 PA31 - -//! PortB -//! For LPC17xx mcu, Port B is equal to Port 1 -#define PB0 PB0 -#define PB1 PB1 -#define PB2 PB2 -#define PB3 PB3 -#define PB4 PB4 -#define PB5 PB5 -#define PB6 PB6 -#define PB7 PB7 -#define PB8 PB8 -#define PB9 PB9 -#define PB10 PB10 -#define PB11 PB11 -#define PB12 PB12 -#define PB13 PB13 -#define PB14 PB14 -#define PB15 PB15 -#define PB16 PB16 -#define PB17 PB17 -#define PB18 PB18 -#define PB19 PB19 -#define PB20 PB20 -#define PB21 PB21 -#define PB22 PB22 -#define PB23 PB23 -#define PB24 PB24 -#define PB25 PB25 -#define PB26 PB26 -#define PB27 PB27 -#define PB28 PB28 -#define PB29 PB29 -#define PB30 PB30 -#define PB31 PB31 - -//! PortC -//! For LPC17xx mcu, Port C is equal to Port 2 -#define PC0 PC0 -#define PC1 PC1 -#define PC2 PC2 -#define PC3 PC3 -#define PC4 PC4 -#define PC5 PC5 -#define PC6 PC6 -#define PC7 PC7 -#define PC8 PC8 -#define PC9 PC9 -#define PC10 PC10 -#define PC11 PC11 -#define PC12 PC12 -#define PC13 PC13 -#define PC14 PC14 -#define PC15 PC15 -#define PC16 PC16 -#define PC17 PC17 -#define PC18 PC18 -#define PC19 PC19 -#define PC20 PC20 -#define PC21 PC21 -#define PC22 PC22 -#define PC23 PC23 -#define PC24 PC24 -#define PC25 PC25 -#define PC26 PC26 -#define PC27 PC27 -#define PC28 PC28 -#define PC29 PC29 -#define PC30 PC30 -#define PC31 PC31 - -//! PortD -//! For LPC17xx mcu, Port D is equal to Port 3 -#define PD0 PD0 -#define PD1 PD1 -#define PD2 PD2 -#define PD3 PD3 -#define PD4 PD4 -#define PD5 PD5 -#define PD6 PD6 -#define PD7 PD7 -#define PD8 PD8 -#define PD9 PD9 -#define PD10 PD10 -#define PD11 PD11 -#define PD12 PD12 -#define PD13 PD13 -#define PD14 PD14 -#define PD15 PD15 -#define PD16 PD16 -#define PD17 PD17 -#define PD18 PD18 -#define PD19 PD19 -#define PD20 PD20 -#define PD21 PD21 -#define PD22 PD22 -#define PD23 PD23 -#define PD24 PD24 -#define PD25 PD25 -#define PD26 PD26 -#define PD27 PD27 -#define PD28 PD28 -#define PD29 PD29 -#define PD30 PD30 -#define PD31 PD31 - -//! PortE -//! For LPC17xx mcu, Port E is equal to Port 4 -#define PE0 PE0 -#define PE1 PE1 -#define PE2 PE2 -#define PE3 PE3 -#define PE4 PE4 -#define PE5 PE5 -#define PE6 PE6 -#define PE7 PE7 -#define PE8 PE8 -#define PE9 PE9 -#define PE10 PE10 -#define PE11 PE11 -#define PE12 PE12 -#define PE13 PE13 -#define PE14 PE14 -#define PE15 PE15 -#define PE16 PE16 -#define PE17 PE17 -#define PE18 PE18 -#define PE19 PE19 -#define PE20 PE20 -#define PE21 PE21 -#define PE22 PE22 -#define PE23 PE23 -#define PE24 PE24 -#define PE25 PE25 -#define PE26 PE26 -#define PE27 PE27 -#define PE28 PE28 -#define PE29 PE29 -#define PE30 PE30 -#define PE31 PE31 - -//! PortF -//! For LPC17xx mcu, Port F is equal to Port 5 -#define PF0 PF0 -#define PF1 PF1 -#define PF2 PF2 -#define PF3 PF3 -#define PF4 PF4 -#define PF5 PF5 -#define PF6 PF6 -#define PF7 PF7 -#define PF8 PF8 -#define PF9 PF9 -#define PF10 PF10 -#define PF11 PF11 -#define PF12 PF12 -#define PF13 PF13 -#define PF14 PF14 -#define PF15 PF15 -#define PF16 PF16 -#define PF17 PF17 -#define PF18 PF18 -#define PF19 PF19 -#define PF20 PF20 -#define PF21 PF21 -#define PF22 PF22 -#define PF23 PF23 -#define PF24 PF24 -#define PF25 PF25 -#define PF26 PF26 -#define PF27 PF27 -#define PF28 PF28 -#define PF29 PF29 -#define PF30 PF30 -#define PF31 PF31 - -//! PortG -//! For LPC17xx mcu, Port G is equal to Port 6 -#define PG0 PG0 -#define PG1 PG1 -#define PG2 PG2 -#define PG3 PG3 -#define PG4 PG4 -#define PG5 PG5 -#define PG6 PG6 -#define PG7 PG7 -#define PG8 PG8 -#define PG9 PG9 -#define PG10 PG10 -#define PG11 PG11 -#define PG12 PG12 -#define PG13 PG13 -#define PG14 PG14 -#define PG15 PG15 -#define PG16 PG16 -#define PG17 PG17 -#define PG18 PG18 -#define PG19 PG19 -#define PG20 PG20 -#define PG21 PG21 -#define PG22 PG22 -#define PG23 PG23 -#define PG24 PG24 -#define PG25 PG25 -#define PG26 PG26 -#define PG27 PG27 -#define PG28 PG28 -#define PG29 PG29 -#define PG30 PG30 -#define PG31 PG31 - - -#define PH0 PH0 -#define PH1 PH1 -#define PH2 PH2 -#define PH3 PH3 -#define PH4 PH4 -#define PH5 PH5 -#define PH6 PH6 -#define PH7 PH7 -#define PH8 PH8 -#define PH9 PH9 -#define PH10 PH10 -#define PH11 PH11 -#define PH12 PH12 -#define PH13 PH13 -#define PH14 PH14 -#define PH15 PH15 -#define PH16 PH16 -#define PH17 PH17 -#define PH18 PH18 -#define PH19 PH19 -#define PH20 PH20 -#define PH21 PH21 -#define PH22 PH22 -#define PH23 PH23 -#define PH24 PH24 -#define PH25 PH25 -#define PH26 PH26 -#define PH27 PH27 -#define PH28 PH28 -#define PH29 PH29 -#define PH30 PH30 -#define PH31 PH31 - - -#define PI0 PI0 -#define PI1 PI1 -#define PI2 PI2 -#define PI3 PI3 -#define PI4 PI4 -#define PI5 PI5 -#define PI6 PI6 -#define PI7 PI7 -#define PI8 PI8 -#define PI9 PI9 -#define PI10 PI10 -#define PI11 PI11 -#define PI12 PI12 -#define PI13 PI13 -#define PI14 PI14 -#define PI15 PI15 -#define PI16 PI16 -#define PI17 PI17 -#define PI18 PI18 -#define PI19 PI19 -#define PI20 PI20 -#define PI21 PI21 -#define PI22 PI22 -#define PI23 PI23 -#define PI24 PI24 -#define PI25 PI25 -#define PI26 PI26 -#define PI27 PI27 -#define PI28 PI28 -#define PI29 PI29 -#define PI30 PI30 -#define PI31 PI31 - -#define PJ0 PJ0 -#define PJ1 PJ1 -#define PJ2 PJ2 -#define PJ3 PJ3 -#define PJ4 PJ4 -#define PJ5 PJ5 -#define PJ6 PJ6 -#define PJ7 PJ7 -#define PJ8 PJ8 -#define PJ9 PJ9 -#define PJ10 PJ10 -#define PJ11 PJ11 -#define PJ12 PJ12 -#define PJ13 PJ13 -#define PJ14 PJ14 -#define PJ15 PJ15 -#define PJ16 PJ16 -#define PJ17 PJ17 -#define PJ18 PJ18 -#define PJ19 PJ19 -#define PJ20 PJ20 -#define PJ21 PJ21 -#define PJ22 PJ22 -#define PJ23 PJ23 -#define PJ24 PJ24 -#define PJ25 PJ25 -#define PJ26 PJ26 -#define PJ27 PJ27 -#define PJ28 PJ28 -#define PJ29 PJ29 -#define PJ30 PJ30 -#define PJ31 PJ31 - -//***************************************************************************** -// -//! @} -// -//***************************************************************************** - //***************************************************************************** // @@ -1349,7 +965,7 @@ extern unsigned long xGPIOPinRead(unsigned long ulPort, unsigned long ulPins); // //***************************************************************************** extern void xGPIOPinWrite(unsigned long ulPort, unsigned long ulPins, - unsigned long ucVal); + unsigned char ucVal); //***************************************************************************** diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xhw_nvic.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xhw_nvic.h index fb3652ca..9600baf6 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xhw_nvic.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xhw_nvic.h @@ -2,8 +2,8 @@ // //! \file xhw_nvic.h //! \brief Macros used when accessing the NVIC hardware.For M4 -//! \version V2.2.1.0 -//! \date 5/28/2014 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xhw_types.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xhw_types.h index 6607850d..b566c960 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xhw_types.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xhw_types.h @@ -2,8 +2,8 @@ // //! \file xhw_types.h //! \brief Common types and macros. -//! \version V2.1.1.0 -//! \date $CURRENTTIME$ +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copyright //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xi2c.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xi2c.h index 0ef031c8..946ff66d 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xi2c.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xi2c.h @@ -2,8 +2,8 @@ // //! \file xi2c.h //! \brief Prototypes for the I2C Driver. -//! \version V2.2.1.0 -//! \date $CURRENTTIME$ +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copyright //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xlowlayer.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xlowlayer.h index c26f58d1..02f191d7 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xlowlayer.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xlowlayer.h @@ -2,8 +2,8 @@ // //! \file xlowlayer.h //! \brief Macros defining of Peripehral Base and interrupt assignments. -//! \version V2.1.1.0 -//! \date $CURRENTTIME$ +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copyright //! @@ -278,7 +278,8 @@ #define xINT_SPI2 INT_SPI2 #define xINT_SPI3 INT_SPI3 #define xINT_CAN0 INT_CAN0 -#define xINT_CAN1 INT_CAN1 +#define xINT_CAN1 INT_CAN1 +#define xINT_CAN2 INT_CAN2 #define xINT_I2S0 INT_I2S0 #define xINT_I2S1 INT_I2S1 #define xINT_USBD INT_USBD diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xpwm.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xpwm.h index c3752d7b..f0c6d9a0 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xpwm.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xpwm.h @@ -2,8 +2,8 @@ // //! \file xpwm.h //! \brief Prototypes for the PWM Driver. -//! \version V2.2.1.0 -//! \date 5/2/2012 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xrtc.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xrtc.h index 267854f1..26963a25 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xrtc.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xrtc.h @@ -2,8 +2,8 @@ // //! \file xrtc.h //! \brief Prototypes for the RTC Driver. -//! \version V2.2.1.0 -//! \date $CURRENTTIME$ +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copyright //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xspi.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xspi.h index 1c6b2d3f..f5d7ac24 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xspi.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xspi.h @@ -2,8 +2,8 @@ // //! \file xspi.h //! \brief Prototypes for the SPI Driver. -//! \version V2.1.1.0 -//! \date 3/6/2012 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! @@ -763,6 +763,8 @@ extern void xSPIIntCallbackInit(unsigned long ulBase, xtEventCallback xtSPICallb //! \brief Disable the SPI interrupt of the specified SPI port. //! //! \param ulBase specifies the SPI module base address. +//! \param ulIntFlags specifies the type of SPI interrupt. +//! Details please refer to \ref xSPI_Ints. //! //! This function is to disable the SPI interrupt of the specified SPI port //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xsysctl.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xsysctl.h index 20d025e3..ae075a98 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xsysctl.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xsysctl.h @@ -2,8 +2,8 @@ // //! \file xsysctl.h //! \brief Prototypes for the System Control Driver. -//! \version V2.2.1.0 -//! \date $CURRENTTIME$ +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copyright //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xtimer.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xtimer.h index 80d001f9..622f22cb 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xtimer.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xtimer.h @@ -2,8 +2,8 @@ // //! \file xtimer.h //! \brief Prototypes for the TIMER Driver. -//! \version V2.2.1.0 -//! \date 7/16/2014 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xuart.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xuart.h index 39710d8d..b2374e06 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xuart.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xuart.h @@ -2,8 +2,8 @@ // //! \file xuart.h //! \brief Prototypes for the UART Driver. -//! \version V2.2 -//! \date 5/17/2012 +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copy //! diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xusb.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xusb.h new file mode 100644 index 00000000..b0eb1074 --- /dev/null +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xusb.h @@ -0,0 +1,546 @@ +//***************************************************************************** +// +//! \file xusb.h +//! \brief Prototypes for the USB Driver. +//! \version V2.3 +//! \date 08/01/2014 +//! \author CooCox +//! \copyright +//! +//! Copyright (c) 2014, CooCox +//! All rights reserved. +//! +//! Redistribution and use in source and binary forms, with or without +//! modification, are permitted provided that the following conditions +//! are met: +//! * Redistributions of source code must retain the above copyright +//! notice, this list of conditions and the following disclaimer. +//! * Redistributions in binary form must reproduce the above copyright +//! notice, this list of conditions and the following disclaimer in the +//! documentation and/or other materials provided with the distribution. +//! * Neither the name of the nor the names of its +//! contributors may be used to endorse or promote products derived +//! from this software without specific prior written permission. +//! +//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +//! THE POSPIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __XUSB_H__ +#define __XUSB_H__ + +//#include "usb.h" +//#include "xPort.h" +#include "xhw_types.h" + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup CoX_Peripheral_Interface +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUSB +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUSB_Event xUSB Event +//! +//! more please refer to [xUSB Event in MD file](@ref xUSB_Event_md). +//! +//! @{ +// +//***************************************************************************** + +// +// Setup Packet +// +#define xUSB_EVENT_SETUP 1 + +// +// OUT Packet +// +#define xUSB_EVENT_OUT 2 + +// +// In Packet +// +#define xUSB_EVENT_IN 3 + +// +// OUT Packet - Not Acknowledged +// +#define xUSB_EVENT_OUT_NAK 4 + +// +// IN Packet - Not Acknowledged +// +#define xUSB_EVENT_IN_NAK 5 + +// +// OUT Packet - Stalled +// +#define xUSB_EVENT_OUT_STALL 6 + +// +// IN Packet - Stalled +// +#define xUSB_EVENT_IN_STALL 7 + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUSB_Endpoint_Descriptor xUSB Standard Endpoint Descriptor +//! \brief Define the type of Standard Endpoint Descriptor +//! +//! more please refer to [xUSB Standard Endpoint Descriptor](@ref xUSB_Endpoint_Descriptor_md). +//! +//! @{ +// +//***************************************************************************** + +typedef struct _USB_ENDPOINT_DESCRIPTOR { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bEndpointAddress; + unsigned char bmAttributes; + unsigned short wMaxPacketSize; + unsigned char bInterval; +} __attribute__((packed)) USB_ENDPOINT_DESCRIPTOR; + +#define USB_EVENT_EP0 0 +#define USB_EVENT_EP1 1 +#define USB_EVENT_EP2 2 +#define USB_EVENT_EP3 3 +#define USB_EVENT_EP4 4 +#define USB_EVENT_EP5 5 +#define USB_EVENT_EP6 6 +#define USB_EVENT_EP7 7 +#define USB_EVENT_EP8 8 +#define USB_EVENT_EP9 9 +#define USB_EVENT_EP10 10 +#define USB_EVENT_EP11 11 + +#define USB_EVT_SETUP 1 /* Setup Packet */ +#define USB_EVT_OUT 2 /* OUT Packet */ +#define USB_EVT_IN 3 /* IN Packet */ +#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */ +#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */ +#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */ +#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */ +#define USB_EVT_OUT_DMA_EOT 8 /* DMA OUT EP - End of Transfer */ +#define USB_EVT_IN_DMA_EOT 9 /* DMA IN EP - End of Transfer */ +#define USB_EVT_OUT_DMA_NDR 10 /* DMA OUT EP - New Descriptor Request */ +#define USB_EVT_IN_DMA_NDR 11 /* DMA IN EP - New Descriptor Request */ +#define USB_EVT_OUT_DMA_ERR 12 /* DMA OUT EP - Error */ +#define USB_EVT_IN_DMA_ERR 13 /* DMA IN EP - Error */ + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup xUSB_Exported_APIs xUSB API +//! \brief xUSB API Reference. +//! +//! \section xUSB_Exported_APIs_Port CoX Port Details +//! +//! | xUSB API | CoX | +//! |------------------------------------|--------------| +//! | \ref xUSBIOClkConfig | Mandatory | +//! | \ref xUSBInit | Mandatory | +//! | \ref xUSBConnect | Mandatory | +//! | \ref xUSBReset | Mandatory | +//! | \ref xUSBSuspend | Mandatory | +//! | \ref xUSBResume | Mandatory | +//! | \ref xUSBWakeUp | Mandatory | +//! | \ref xUSBWakeUpEnable | Mandatory | +//! | \ref xUSBWakeUpDisable | Mandatory | +//! | \ref xUSBSetAddress | Mandatory | +//! | \ref xUSBConfigure | Mandatory | +//! | \ref xUSBEndpointConfig | Mandatory | +//! | \ref xUSBEndpointDirCtr | Mandatory | +//! | \ref xUSBEndpointEnable | Mandatory | +//! | \ref xUSBEndpointDisable | Mandatory | +//! | \ref xUSBEndpointReset | Mandatory | +//! | \ref xUSBEndpointStallSet | Mandatory | +//! | \ref xUSBEndpointStallClear | Mandatory | +//! | \ref xUSBControlOutEnble | Mandatory | +//! | \ref xUSBEndpointBufferClear | Mandatory | +//! | \ref xUSBEndpointRead | Mandatory | +//! | \ref xUSBEndpointWrite | Mandatory | +//! | \ref xUSBFrameGet | Mandatory | +//! | \ref xUSBEventHandler | Mandatory | +//! more please refer to [xUSB API in MD file](@ref xUSB_Exported_APIs_md). +//! +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief USB and IO Clock configuration only. +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +extern xtBoolean xUSBIOClkConfig(void); + +//***************************************************************************** +// +//! \brief USB Initialize Function +//! +//! \return None. +// +//***************************************************************************** +extern void xUSBInit(void); + +//***************************************************************************** +// +//! \brief Disables the USB master block. +//! This function will disable operation of the USB Master block. +//! +//! \param [in] ulBase is the USB Connect/Disconnect. +//! - \ref xUSB_CONNECT +//! - \ref xUSB_DISCONNECT +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +extern xtBoolean xUSBConnect(unsigned long ulConnect); + +//***************************************************************************** +// +//! \brief USB Reset Function +//! +//! \param None +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +extern xtBoolean xUSBReset(void); + +//***************************************************************************** +// +//! \brief USB Suspend Function +//! +//! \param None +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +extern xtBoolean xUSBSuspend(void); + +//***************************************************************************** +// +//! \brief USB Wakeup Function +//! +//! \param None +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +extern xtBoolean xUSBWakeUp(void); + +//***************************************************************************** +// +//! \brief USB Resume Function +//! +//! \param None +//! +//! \return xtrue or xfalse. +// +//***************************************************************************** +extern xtBoolean xUSBResume(void); + +//***************************************************************************** +// +//! \brief USB Remote Wakeup Enbale Function +//! +//! \param None +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBWakeUpEnable(void); + +//***************************************************************************** +// +//! \brief USB Remote Wakeup Disable Function +//! +//! \param None +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBWakeUpDisable(void); + +//***************************************************************************** +// +//! \brief USB Set Address Function. +//! +//! \param [in] ulBase is the USB Address. +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBSetAddress(unsigned long ulAddr); + +//***************************************************************************** +// +//! \brief USB Set Configure Function. +//! +//! \param [in] ulBase is the USB Configure/Deconfigure. +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBConfigure(unsigned long ulConfig); + +//***************************************************************************** +// +//! \brief Configure USB Endpoint according to Descriptor +//! +//! \param [in] ulBase Pointer to Endpoint Descriptor +//! ulDir: Out (dir == 0), In (dir <> 0) +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBEndpointConfig(USB_ENDPOINT_DESCRIPTOR *epConfig, unsigned long ulDir); + +extern xtBoolean xUSBEndpointDirCtr(unsigned long ulDir); + +//***************************************************************************** +// +//! \brief Enable USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBEndpointEnable(unsigned long ulNum); + +//***************************************************************************** +// +//! \brief Disable USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBEndpointDisable(unsigned long ulNum); + +//***************************************************************************** +// +//! \brief Reset USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBEndpointReset(unsigned long ulNum); + +//***************************************************************************** +// +//! \brief Set Stall for USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBEndpointStallSet(unsigned long ulNum); + +//***************************************************************************** +// +//! \brief Clear Stall for USB Endpoint +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBEndpointStallClear(unsigned long ulNum); + +//***************************************************************************** +// +//! \brief Set max packet size for control out +//! +//! \param [in] None +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBControlOutEnble(void); + +//***************************************************************************** +// +//! \brief Clear USB Endpoint Buffer +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBEndpointBufferClear(unsigned long ulNum); + +//***************************************************************************** +// +//! \brief Read USB Endpoint Data +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! ucpData: Pointer to Data Buffer +//! +//! \return Number of bytes read +// +//***************************************************************************** +extern unsigned long xUSBEndpointRead(unsigned long ulNum,unsigned char *ucpData); + +//***************************************************************************** +// +//! \brief Write USB Endpoint Data +//! +//! \param [in] ulBase Endpoint Number. +//! bit 0-3 Address +//! bit 7 Dir +//! ucpData: Pointer to Data Buffer +//! ulLen Number of bytes +//! +//! \return Number of bytes written +// +//***************************************************************************** +extern unsigned long xUSBEndpointWrite(unsigned long ulNum,unsigned char *ucpData, + unsigned long ulLen); + +//***************************************************************************** +// +//! \brief Get USB Last Frame Number +//! +//! \param [in] None +//! +//! \return number of last frame +// +//***************************************************************************** +extern unsigned long xUSBFrameGet(void); + +//***************************************************************************** +// +//! \brief Set max packet size for control out +//! +//! \param [in] event: The logic number of USB endpoint +//! handler: The callback function of USB endpoint +//! data: The extern type which is using here +//! +//! \return The status: +//! - xtrue +//! - xfalse +// +//***************************************************************************** +extern xtBoolean xUSBEventHandler(unsigned char event, xtEventCallback handler, void *data); + + + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __XUSB_H__ diff --git a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xwdt.h b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xwdt.h index 3cdc979c..106bfabd 100644 --- a/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xwdt.h +++ b/CoX/CoX_Peripheral/CoX_Peripheral_Template/inc/xwdt.h @@ -2,8 +2,8 @@ // //! \file xwdt.h //! \brief Prototypes for the WDT Driver. -//! \version V2.2.1.0 -//! \date $CURRENTTIME$ +//! \version V2.3 +//! \date 07/01/2014 //! \author CooCox //! \copyright //! diff --git a/CoX/middleware/USB_CLASS/USB_ADC/adc_callback.c b/CoX/middleware/USB_CLASS/USB_ADC/adc_callback.c new file mode 100644 index 00000000..33e990a4 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_ADC/adc_callback.c @@ -0,0 +1,255 @@ +/***************************************************************************** + * U S B - A D C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : adc_callback.c + * @brief : USB Audio Device Class call back componet + * @version : 1.1 + * @date : 13. Mar. 2011 + * @author : CooCox + ****************************************************************************/ +#include "adc_callback.h" + +//void Audio_Event(USBADC_Dev *dev); + + +/********************************************************************************************************//** + * @brief Audio Device Class Interface Get Request Callback + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint8_t ADC_IF_GetRequest (USBADC_Dev *dev) { + + /* + Interface = SetupPacket.wIndex.WB.L; + EntityID = SetupPacket.wIndex.WB.H; + Request = SetupPacket.bRequest; + Value = SetupPacket.wValue.W; + ... + */ + if (dev->usb_enu.SetupPacket.wIndex.W == 0x0200) + { + /* Feature Unit: Interface = 0, ID = 2 */ + if (dev->usb_enu.SetupPacket.wValue.WB.L == 0) + { + /* Master Channel */ + switch (dev->usb_enu.SetupPacket.wValue.WB.H) + { + case AUDIO_FU_MUTE_CONTROL: + switch (dev->usb_enu.SetupPacket.bRequest) + { + case AUDIO_REQUEST_GET_CUR: + dev->usb_enu.EP0Buf[0] = dev->Mute; + return (TRUE); + } + break; + case AUDIO_FU_VOLUME_CONTROL: + switch (dev->usb_enu.SetupPacket.bRequest) + { + case AUDIO_REQUEST_GET_CUR: + *((__attribute__((packed)) uint16_t *)dev->usb_enu.EP0Buf) = dev->VolCur; + return (TRUE); + case AUDIO_REQUEST_GET_MIN: + *((__attribute__((packed)) uint16_t *)dev->usb_enu.EP0Buf) = dev->VolMin; + return (TRUE); + case AUDIO_REQUEST_GET_MAX: + *((__attribute__((packed)) uint16_t *)dev->usb_enu.EP0Buf) = dev->VolMax; + return (TRUE); + case AUDIO_REQUEST_GET_RES: + *((__attribute__((packed)) uint16_t *)dev->usb_enu.EP0Buf) = dev->VolRes; + return (TRUE); + } + break; + } + } + } + + return (FALSE); /* Not Supported */ +} + + +/********************************************************************************************************//** + * @brief Audio Device Class Interface Set Request Callback + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint8_t ADC_IF_SetRequest (USBADC_Dev *dev) +{ + + /* + Interface = SetupPacket.wIndex.WB.L; + EntityID = SetupPacket.wIndex.WB.H; + Request = SetupPacket.bRequest; + Value = SetupPacket.wValue.W; + ... + */ + if (dev->usb_enu.SetupPacket.wIndex.W == 0x0200) + { + /* Feature Unit: Interface = 0, ID = 2 */ + if (dev->usb_enu.SetupPacket.wValue.WB.L == 0) + { + /* Master Channel */ + switch (dev->usb_enu.SetupPacket.wValue.WB.H) + { + case AUDIO_FU_MUTE_CONTROL: + switch (dev->usb_enu.SetupPacket.bRequest) + { + case AUDIO_REQUEST_SET_CUR: + dev->Mute = dev->usb_enu.EP0Buf[0]; + return (TRUE); + } + break; + case AUDIO_FU_VOLUME_CONTROL: + switch (dev->usb_enu.SetupPacket.bRequest) + { + case AUDIO_REQUEST_SET_CUR: + dev->VolCur = *((__attribute__((packed)) uint16_t *)dev->usb_enu.EP0Buf); + return (TRUE); + } + break; + } + } + } + + return (FALSE); /* Not Supported */ +} + + +/********************************************************************************************************//** + * @brief Audio Device Class EndPoint Get Request Callback + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint8_t ADC_EP_GetRequest (USBADC_Dev *dev) +{ + + /* + EndPoint = SetupPacket.wIndex.WB.L; + Request = SetupPacket.bRequest; + Value = SetupPacket.wValue.W; + ... + */ + //TODO:Not Supported + return (FALSE); /* Not Supported */ +} + + +/********************************************************************************************************//** + * @brief Audio Device Class EndPoint Set Request Callback + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint8_t ADC_EP_SetRequest (USBADC_Dev *dev) +{ + + /* + EndPoint = SetupPacket.wIndex.WB.L; + Request = SetupPacket.bRequest; + Value = SetupPacket.wValue.W; + ... + */ + //TODO:Not Supported + return (FALSE); /* Not Supported */ +} + +/********************************************************************************************************//** + * @brief ADC ISO output + * @param[in] dev : a point which contains all the global variables which using in this function + * Event : event type of endpoint + * @return None +************************************************************************************************************/ +void ADC_ISOOut(USBADC_Dev *dev,uint32_t Event) +{ + uint32_t len; + uint8_t wbuf[ADC_EP_MAXPAKET]; + len = dev->usb_enu.usb->USB_ReadEP(ADC_EP_OUT, wbuf); + if(dev->Audio_write != NULL) + { + dev->Audio_write(dev->Audio_device, wbuf, len); + } +} + +/********************************************************************************************************//** + * @brief ADC read,data transfer from host to device + * @param[in] dev : a point which contains all the global variables which using in this function + * wbuf : buffer of read + * len : byte length of read + * @return None +************************************************************************************************************/ +uint32_t Audio_Read (USBADC_Dev *dev, uint8_t *rbuf, uint32_t *len) +{ + //TODO: + *len = dev->usb_enu.usb->USB_ReadEP(ADC_EP_OUT, rbuf); + return *len; +} + +/********************************************************************************************************//** + * @brief ADC write,data transfer from device to host + * @param[in] dev : a point which contains all the global variables which using in this function + * wbuf : buffer of write + * len : byte length of write + * @return None +************************************************************************************************************/ +uint32_t Audio_Write (USBADC_Dev *dev, uint8_t *wbuf, uint32_t len) +{ + //TODO: + uint32_t wlen; + wlen = dev->usb_enu.usb->USB_WriteEP(ADC_EP_OUT, wbuf, len); + return wlen; +} + +/********************************************************************************************************//** + * @brief Initialization of the USB ADC + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void Audio_Init (USBADC_Dev *dev) +{ + dev->usb_enu.adc_data = dev; + dev->usb_enu.g_pfn_adc_ep_getrequestt = (PFN_ADC_CALLBACK *)ADC_EP_GetRequest; + dev->usb_enu.g_pfn_adc_ep_setrequestt = (PFN_ADC_CALLBACK *)ADC_EP_SetRequest; + dev->usb_enu.g_pfn_adc_if_getrequestt = (PFN_ADC_CALLBACK *)ADC_IF_GetRequest; + dev->usb_enu.g_pfn_adc_if_setrequestt = (PFN_ADC_CALLBACK *)ADC_IF_SetRequest; + + dev->VolCur = 0x0100; + dev->VolMin = 0x0000; + dev->VolMax = 0x0100; + dev->VolRes = 0x0004; + if (dev->Audio_Init != NULL) + { + dev->Audio_Init(dev->Audio_device); + } + + USB_Init(&dev->usb_enu); +} + +/********************************************************************************************************//** + * @brief Connect ADC to the host + * @param[in] dev : a point which contains all the global variables which using in this function + * con : TRUE \FALSE + * @return None +************************************************************************************************************/ +void Audio_Connect(USBADC_Dev *dev,uint32_t con) +{ + dev->usb_enu.usb->USB_Connect(con); +} + +/********************************************************************************************************//** + * @brief Get ADC Configuration statue + * @param[in] dev : a point which contains all the global variables which using in this function + * @return Configuration statue +************************************************************************************************************/ +uint8_t Audio_Configurated(USBADC_Dev *dev) +{ + return dev->usb_enu.USB_Configuration; +} + +/********************************************************************************************************//** + * @brief ADC event callback setup + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void Audio_Event(USBADC_Dev *dev) +{ + dev->usb_enu.usb->USB_Event((ADC_EP_OUT&0xf),(USB_Event_Handler)ADC_ISOOut,(void *)dev); +} diff --git a/CoX/middleware/USB_CLASS/USB_ADC/adc_callback.h b/CoX/middleware/USB_CLASS/USB_ADC/adc_callback.h new file mode 100644 index 00000000..8fb96c2d --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_ADC/adc_callback.h @@ -0,0 +1,56 @@ +/***************************************************************************** + * U S B - A D C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : ADC_CALLBACK.h + * @brief : USB Audio Device Class Call Back Definitions + * @version : 1.1 + * @date : 13. Mar. 2011 + * @author : CooCox + ****************************************************************************/ + + +#ifndef __ADC_CALLBACK_H__ +#define __ADC_CALLBACK_H__ + +#include "usb_enumerate.h" + +/*********************************************************************** + * USB ADC call back function definition + **********************************************************************/ +typedef uint32_t (PFN_AUDIO_INIT_CALLBACK) (void *dev); +typedef uint32_t (PFN_AUDIO_READ_CALLBACK) (void *dev, uint8_t *rbuf, uint32_t rlen); +typedef uint32_t (PFN_AUDIO_WRITE_CALLBACK) (void *dev, uint8_t *wbuf, uint32_t wlen); + +/** + * @brief USB ADC Structure + */ +typedef struct +{ + USB_ENU_Dev usb_enu; + PFN_AUDIO_INIT_CALLBACK *Audio_Init; + PFN_AUDIO_READ_CALLBACK *Audio_Read; + PFN_AUDIO_WRITE_CALLBACK *Audio_write; + PFN_AUDIO_INIT_CALLBACK *Audio_DeInit; + + void *Audio_device; + + uint16_t VolCur; /* Volume Current Value */ + uint16_t VolMin; /* Volume Minimum Value */ + uint16_t VolMax; /* Volume Maximum Value */ + uint16_t VolRes; /* Volume Resolution */ + uint8_t Mute; +} USBADC_Dev; + + +/*********************************************************************** + * extern API of this component + **********************************************************************/ +extern uint32_t Audio_Read (USBADC_Dev *dev, uint8_t *rbuf, uint32_t *len); +extern uint32_t Audio_Write (USBADC_Dev *dev, uint8_t *wbuf, uint32_t len); +extern void Audio_Init (USBADC_Dev *dev); +extern void Audio_Connect(USBADC_Dev *dev,uint32_t con); +extern uint8_t Audio_Configurated(USBADC_Dev *dev); +extern void Audio_Event(USBADC_Dev *dev); + +#endif /* __ADC_CALLBACK_H__ */ diff --git a/CoX/middleware/USB_CLASS/USB_ADC/usb_adc_config.h b/CoX/middleware/USB_CLASS/USB_ADC/usb_adc_config.h new file mode 100644 index 00000000..22b6d136 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_ADC/usb_adc_config.h @@ -0,0 +1,20 @@ +/***************************************************************************** + * U S B - A D C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : usb_adc_config.h + * @brief : config + * @version : 1.1 + * @date : 13. Mar. 2011 + * @author : CooCox + ****************************************************************************/ +#ifndef __USB_ADC_CONFIG_H__ +#define __USB_ADC_CONFIG_H__ + +/********************************************************************** + * Audio Device In/Out Endpoint Address + **********************************************************************/ +#define ADC_EP_OUT 0x03 +#define ADC_EP_MAXPAKET 0x40 + +#endif /* __USB_ADC_CONFIG_H__ */ diff --git a/CoX/middleware/USB_CLASS/USB_ADC/usb_audio.h b/CoX/middleware/USB_CLASS/USB_ADC/usb_audio.h new file mode 100644 index 00000000..0c602acc --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_ADC/usb_audio.h @@ -0,0 +1,903 @@ +/***************************************************************************** + * U S B - C D C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : ADC_Audio.h + * @brief : USB Audio Device Class Definitions + * @version : 1.1 + * @date : 13. Mar. 2011 + * @author : CooCox + ****************************************************************************/ + + +#ifndef __USB_AUDIO_H__ +#define __USB_AUDIO_H__ + + +/********************************************************************** + * Audio Interface Class Code in audio20 final.pdf A.1 + **********************************************************************/ +#define AUDIO 0x01 + + +/********************************************************************** + * Audio Function Class Code + **********************************************************************/ +#define AUDIO_FUNCTION AUDIO + + +/********************************************************************** + * Audio Function Subclass Codes + **********************************************************************/ +#define AUDIO_FUNCTION_SUBCLASS_UNDEFINED 0x00 + + +/********************************************************************** + * Audio Function Protocol Codes + **********************************************************************/ +#define AUDIO_FUNCTION_PROTOCOL_UNDEFINED 0x00 +#define AUDIO_AF_VERSION_02_00 0x0200 + +/********************************************************************** + * Audio Interface Subclass Codes + **********************************************************************/ +#define AUDIO_SUBCLASS_UNDEFINED 0x00 +#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01 +#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 +#define AUDIO_SUBCLASS_MIDISTREAMING 0x03 + +/********************************************************************** + * Audio Interface Protocol Codes + **********************************************************************/ +#define AUDIO_PROTOCOL_UNDEFINED 0x00 +#define AUDIO_PROTOCOL_IP_VERSION_02_00 0x20 + +/********************************************************************** + * Audio Function Category Codes + **********************************************************************/ +#define AUDIO_FUNCTION_SUBCLASS_UNDEFINED 0x00 +#define AUDIO_FUNCTION_DESKTOP_SPEAKER 0x01 +#define AUDIO_FUNCTION_HOME_THEATER 0x02 +#define AUDIO_FUNCTION_MICROPHONE 0x03 +#define AUDIO_FUNCTION_HEADSET 0x04 +#define AUDIO_FUNCTION_TELEPHONE 0x05 +#define AUDIO_FUNCTION_CONVERTER 0x06 +#define AUDIO_FUNCTION_SOUND_RECORDER 0x07 +#define AUDIO_FUNCTION_IO_BOX 0x08 +#define AUDIO_FUNCTION_MUSICAL_INSTRUMENT 0x09 +#define AUDIO_FUNCTION_PRO_AUDIO 0x0A +#define AUDIO_FUNCTION_AUDIO_VIDEO 0x0B +#define AUDIO_FUNCTION_CONTROL_PANEL 0x0C +#define AUDIO_FUNCTION_OTHER 0xFF + +/********************************************************************** + * Audio Class-Specific Descriptor Types + **********************************************************************/ +#define AUDIO_UNDEFINED_DESCRIPTOR_TYPE 0x20 +#define AUDIO_DEVICE_DESCRIPTOR_TYPE 0x21 +#define AUDIO_CONFIGURATION_DESCRIPTOR_TYPE 0x22 +#define AUDIO_STRING_DESCRIPTOR_TYPE 0x23 +#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24 +#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25 + + +/********************************************************************** + * Audio Class-Specific AC Interface Descriptor Subtypes + **********************************************************************/ +#define AUDIO_CONTROL_UNDEFINED 0x00 +#define AUDIO_CONTROL_HEADER 0x01 +#define AUDIO_CONTROL_INPUT_TERMINAL 0x02 +#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03 +#define AUDIO_CONTROL_MIXER_UNIT 0x04 +#define AUDIO_CONTROL_SELECTOR_UNIT 0x05 +#define AUDIO_CONTROL_FEATURE_UNIT 0x06 +#define AUDIO_CONTROL_EFFECT_UNIT 0x07 +#define AUDIO_CONTROL_PROCESSING_UNIT 0x08 +#define AUDIO_CONTROL_EXTENSION_UNIT 0x09 +#define AUDIO_CONTROL_CLOCK_SOURCE 0x0A +#define AUDIO_CONTROL_CLOCK_SELECTOR 0x0B +#define AUDIO_CONTROL_CLOCK_MULTIPLIER 0x0C +#define AUDIO_CONTROL_SAMPLE_RATE_CONVERTER 0x0D + +/********************************************************************** + * Audio Class-Specific AS Interface Descriptor Subtypes + **********************************************************************/ +#define AUDIO_STREAMING_UNDEFINED 0x00 +#define AUDIO_STREAMING_GENERAL 0x01 +#define AUDIO_STREAMING_FORMAT_TYPE 0x02 +#define AUDIO_STREAMING_FORMAT_SPECIFIC 0x03 +#define AUDIO_STREAMING_FORMAT_DECODER 0x04 + +/********************************************************************** + * Effect Unit Effect Types + **********************************************************************/ +#define AUDIO_EFFECT_UNDEFINED 0x00 +#define AUDIO_EFFECT_PARAM_EQ_SECTION_EFFECT 0x01 +#define AUDIO_EFFECT_REVERBERATION_EFFECT 0x02 +#define AUDIO_EFFECT_MOD_DELAY_EFFECT 0x03 +#define AUDIO_EFFECT_DYN_RANGE_COMP_EFFECT 0x04 + +/********************************************************************** + * Processing Unit Process Types + **********************************************************************/ +#define AUDIO_PROCESS_UNDEFINED 0x00 +#define AUDIO_PROCESS_UP_DOWNMIX_PROCESS 0x01 +#define AUDIO_PROCESS_DOLBY_PROLOGIC_PROCESS 0x02 +#define AUDIO_PROCESS_STEREO_EXTENDER_PROCESS 0x03 + +/********************************************************************** + * Audio Class-Specific Endpoint Descriptor Subtypes + **********************************************************************/ +#define AUDIO_ENDPOINT_UNDEFINED 0x00 +#define AUDIO_ENDPOINT_GENERAL 0x01 + + +/* Audio Descriptor Sizes */ +//Table 4-1: Audio Channel Cluster Descriptor 6 +//Table 4-1: Dolby Prologic Cluster Descriptor 6 +//Table 4-2: Left Group Cluster Descriptor 6 +//Table 4-3: Standard Interface Association Descriptor 8 +//Table 4-4: Standard AC Interface Descriptor 9 +//Table 4-5: Class-Specific AC Interface Header Descriptor 9 +//Table 4-6: Clock Source Descriptor 8 +//Table 4-7: Clock Selector Descriptor 7+p +//Table 4-8: Clock Multiplier Descriptor 7 +//Table 4-9: Input Terminal Descriptor 17 +//Table 4-10: Output Terminal Descriptor 12 +//Table 4-11: Mixer Unit Descriptor 13+p+n +//Table 4-12: Selector Unit Descriptor 7+p +//Table 4-13: Feature Unit Descriptor 6+(ch+1)*4 +//Table 4-14: Sampling Rate Converter Unit Descriptor 8 +//Table 4-15: Common Part of the Effect Unit Descriptor 16+(ch*4) +//Table 4-16: Parametric Equalizer Section Effect Unit Descriptor 16+(ch*4) +//Table 4-17: Reverberation Effect Unit Descriptor 16+(ch*4) +//Table 4-18: Modulation Delay Effect Unit Descriptor 16+(ch*4) +//Table 4-19: Dynamic Range Compressor Effect Unit Descriptor 16+(ch*4) +//Table 4-20: Common Part of the Processing Unit Descriptor 17+p+x +//Table 4-21: Up/Down-mix Processing Unit Descriptor 18+4*m +//Table 4-22: Dolby Prologic Processing Unit Descriptor 18+4*m +//Table 4-23: Stereo Extender Processing Unit Descriptor 17 +//Table 4-24: Extension Unit Descriptor 16+p +//Table 4-25: Standard AC Interrupt Endpoint Descriptor 7 +//Table 4-26: Standard AS Interface Descriptor 9 +//Table 4-27: Class-Specific AS Interface Descriptor 16 +//Table 4-28: Encoder Descriptor 21 +//Table 4-29: MPEG Decoder Descriptor 10 +//Table 4-30: AC-3 Decoder Descriptor 12 +//Table 4-31: WMA Decoder Descriptor 9 +//Table 4-32: DTS Decoder Descriptor 8 +//Table 4-33: Standard AS Isochronous Audio Data Endpoint Descriptor 7 +//Table 4-34: Class-Specific AS Isochronous Audio Data Endpoint Descriptor 8 +//Table 4-35: Standard AS Isochronous Feedback Endpoint Descriptor 7 + +#define AUDIO_CONTROL_INTERFACE_DESC_SZ(n) 0x08+n +#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07 +#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C +#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09 +#define AUDIO_MIXER_UNIT_DESC_SZ(p,n) 0x0A+p+n +#define AUDIO_SELECTOR_UNIT_DESC_SZ(p) 0x06+p +#define AUDIO_FEATURE_UNIT_DESC_SZ(ch,n) 0x07+(ch+1)*n +#define AUDIO_PROCESSING_UNIT_DESC_SZ(p,n,x) 0x0D+p+n+x +#define AUDIO_EXTENSION_UNIT_DESC_SZ(p,n) 0x0D+p+n +#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09 +#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07 + + +/* Audio Processing Unit Process Types */ +/*#define AUDIO_UNDEFINED_PROCESS 0x00 +#define AUDIO_UP_DOWN_MIX_PROCESS 0x01 +#define AUDIO_DOLBY_PROLOGIC_PROCESS 0x02 +#define AUDIO_3D_STEREO_PROCESS 0x03 +#define AUDIO_REVERBERATION_PROCESS 0x04 +#define AUDIO_CHORUS_PROCESS 0x05 +#define AUDIO_DYN_RANGE_COMP_PROCESS 0x06*/ + + +/********************************************************************** + * Audio Request Codes + **********************************************************************/ +#define AUDIO_REQUEST_UNDEFINED 0x00 +#define AUDIO_REQUEST_CUR 0x01 +#define AUDIO_REQUEST_RANGE 0x02 +#define AUDIO_REQUEST_MEM 0x03 + +#define AUDIO_REQUEST_UNDEFINED 0x00 +#define AUDIO_REQUEST_SET_CUR 0x01 +#define AUDIO_REQUEST_GET_CUR 0x81 +#define AUDIO_REQUEST_SET_MIN 0x02 +#define AUDIO_REQUEST_GET_MIN 0x82 +#define AUDIO_REQUEST_SET_MAX 0x03 +#define AUDIO_REQUEST_GET_MAX 0x83 +#define AUDIO_REQUEST_SET_RES 0x04 +#define AUDIO_REQUEST_GET_RES 0x84 +#define AUDIO_REQUEST_SET_MEM 0x05 +#define AUDIO_REQUEST_GET_MEM 0x85 +#define AUDIO_REQUEST_GET_STAT 0xFF + +/********************************************************************** + * Encoder Type Codes + **********************************************************************/ +#define AUDIO_ENCODER_UNDEFINED 0x00 +#define AUDIO_OTHER_ENCODER 0x01 +#define AUDIO_MPEG_ENCODER 0x02 +#define AUDIO_AC_3_ENCODER 0x03 +#define AUDIO_WMA_ENCODER 0x04 +#define AUDIO_DTS_ENCODER 0x05 + +/********************************************************************** + * Decoder Type Codes in audio20 final.pdf A.16 + **********************************************************************/ +#define AUDIO_DECODER_UNDEFINED 0x00 +#define AUDIO_OTHER_DECODER 0x01 +#define AUDIO_MPEG_DECODER 0x02 +#define AUDIO_AC_3_DECODER 0x03 +#define AUDIO_WMA_DECODER 0x04 +#define AUDIO_DTS_DECODER 0x05 + +/********************************************************************** + * Audio Control Selector Codes in audio20 final.pdf A.17 + **********************************************************************/ +#define AUDIO_CONTROL_UNDEFINED 0x00 /* Common Selector */ + +/********************************************************************** + * Clock Source Control Selectors Codes in audio20 final.pdf A.17.1 + **********************************************************************/ +#define AUDIO_CS_CONTROL_UNDEFINED 0x00 /* Common Selector */ +#define AUDIO_CS_SAM_FREQ_CONTROL 0x01 +#define AUDIO_CS_CLOCK_VALID_CONTROL 0x02 + + +/********************************************************************** + * Clock Selector Control Selectors Codes in audio20 final.pdf A.17.2 + **********************************************************************/ +#define AUDIO_CX_CONTROL_UNDEFINED 0x00 /* Common Selector */ +#define AUDIO_CX_CLOCK_SELECTOR_CONTROL 0x01 + + +/********************************************************************** + * Clock Multiplier Control Selectors Codes in audio20 final.pdf A.17.3 + **********************************************************************/ +#define AUDIO_CM_CONTROL_UNDEFINED 0x00 /* Common Selector */ +#define AUDIO_CM_NUMERATOR_CONTROL 0x01 +#define AUDIO_CM_DENOMINATOR_CONTROL 0x02 + +/********************************************************************** + * Terminal Control Selectors Codes in audio20 final.pdf A.17.4 + **********************************************************************/ +#define AUDIO_TE_CONTROL_UNDEFINED 0x00 +#define AUDIO_TE_COPY_PROTECT_CONTROL 0x01 +#define AUDIO_TE_CONNECTOR_CONTROL 0x02 +#define AUDIO_TE_OVERLOAD_CONTROL 0x03 +#define AUDIO_TE_CLUSTER_CONTROL 0x04 +#define AUDIO_TE_UNDERFLOW_CONTROL 0x05 +#define AUDIO_TE_OVERFLOW_CONTROL 0x06 +#define AUDIO_TE_LATENCY_CONTROL 0x07 + +/********************************************************************** + * Mixer Control Selectors Codes in audio20 final.pdf A.17.5 + **********************************************************************/ +#define AUDIO_MU_CONTROL_UNDEFINED 0x00 +#define AUDIO_MU_MIXER_CONTROL 0x01 +#define AUDIO_MU_CLUSTER_CONTROL 0x02 +#define AUDIO_MU_UNDERFLOW_CONTROL 0x03 +#define AUDIO_MU_OVERFLOW_CONTROL 0x04 +#define AUDIO_MU_LATENCY_CONTROL 0x05 + + +/********************************************************************** + * Selector Control Selectors Codes in audio20 final.pdf A.17.6 + **********************************************************************/ +#define AUDIO_SU_CONTROL_UNDEFINED 0x00 +#define AUDIO_SU_SELECTOR_CONTROL 0x01 +#define AUDIO_SU_LATENCY_CONTROL 0x02 + +/********************************************************************** + * Feature Unit Control Selectors Codes in audio20 final.pdf A.17.7 + **********************************************************************/ +#define AUDIO_FU_CONTROL_UNDEFINED 0x00 +#define AUDIO_FU_MUTE_CONTROL 0x01 +#define AUDIO_FU_VOLUME_CONTROL 0x02 +#define AUDIO_FU_BASS_CONTROL 0x03 +#define AUDIO_FU_MID_CONTROL 0x04 +#define AUDIO_FU_TREBLE_CONTROL 0x05 +#define AUDIO_FU_GRAPHIC_EQUALIZER_CONTROL 0x06 +#define AUDIO_FU_AUTOMATIC_GAIN_CONTROL 0x07 +#define AUDIO_FU_DELAY_CONTROL 0x08 +#define AUDIO_FU_BASS_BOOST_CONTROL 0x09 +#define AUDIO_FU_LOUDNESS_CONTROL 0x0A +#define AUDIO_FU_INPUT_GAIN_CONTROL 0x0B +#define AUDIO_FU_INPUT_GAIN_PAD_CONTROL 0x0C +#define AUDIO_FU_PHASE_INVERTER_CONTROL 0x0D +#define AUDIO_FU_UNDERFLOW_CONTROL 0x0E +#define AUDIO_FU_OVERFLOW_CONTROL 0x0F +#define AUDIO_FU_LATENCY_CONTROL 0x10 + +/* Effect Unit Control Selectors Codes in audio20 final.pdf A.17.8*/ + +/********************************************************************** + * Parametric Equalizer Section Effect Unit Control Selectors Codes + * in audio20 final.pdf A.17.8.1 + **********************************************************************/ +#define AUDIO_PE_CONTROL_UNDEFINED 0x00 +#define AUDIO_PE_ENABLE_CONTROL 0x01 +#define AUDIO_PE_CENTERFREQ_CONTROL 0x02 +#define AUDIO_PE_QFACTOR_CONTROL 0x03 +#define AUDIO_PE_GAIN_CONTROL 0x04 +#define AUDIO_PE_UNDERFLOW_CONTROL 0x05 +#define AUDIO_PE_OVERFLOW_CONTROL 0x06 +#define AUDIO_PE_LATENCY_CONTROL 0x07 + +/********************************************************************** + * Reverberation Effect Unit Control Selectors Codes in + * audio20 final.pdf A.17.8.2 + **********************************************************************/ +#define AUDIO_RV_CONTROL_UNDEFINED 0x00 +#define AUDIO_RV_ENABLE_CONTROL 0x01 +#define AUDIO_RV_TYPE_CONTROL 0x02 +#define AUDIO_RV_LEVEL_CONTROL 0x03 +#define AUDIO_RV_TIME_CONTROL 0x04 +#define AUDIO_RV_FEEDBACK_CONTROL 0x05 +#define AUDIO_RV_PREDELAY_CONTROL 0x06 +#define AUDIO_RV_DENSITY_CONTROL 0x07 +#define AUDIO_RV_HIFREQ_ROLLOFF_CONTROL 0x08 +#define AUDIO_RV_UNDERFLOW_CONTROL 0x09 +#define AUDIO_RV_OVERFLOW_CONTROL 0x0A +#define AUDIO_RV_LATENCY_CONTROL 0x0B + + +/********************************************************************** + * Modulation Delay Effect Unit Control Selectors Codes in + * audio20 final.pdf A.17.8.3 + **********************************************************************/ +#define AUDIO_MD_CONTROL_UNDEFINED 0x00 +#define AUDIO_MD_ENABLE_CONTROL 0x01 +#define AUDIO_MD_BALANCE_CONTROL 0x02 +#define AUDIO_MD_RATE_CONTROL 0x03 +#define AUDIO_MD_DEPTH_CONTROL 0x04 +#define AUDIO_MD_TIME_CONTROL 0x05 +#define AUDIO_MD_FEEDBACK_CONTROL 0x06 +#define AUDIO_MD_UNDERFLOW_CONTROL 0x07 +#define AUDIO_MD_OVERFLOW_CONTROL 0x08 +#define AUDIO_MD_LATENCY_CONTROL 0x09 + + +/********************************************************************** + * Dynamic Range Compressor Effect Unit Control Selectors Codes in + * audio20 final.pdf A.17.8.4 + **********************************************************************/ +#define AUDIO_DR_CONTROL_UNDEFINED 0x00 +#define AUDIO_DR_ENABLE_CONTROL 0x01 +#define AUDIO_DR_COMPRESSION_RATE_CONTROL 0x02 +#define AUDIO_DR_MAXAMPL_CONTROL 0x03 +#define AUDIO_DR_THRESHOLD_CONTROL 0x04 +#define AUDIO_DR_ATTACK_TIME_CONTROL 0x05 +#define AUDIO_DR_RELEASE_TIME_CONTROL 0x06 +#define AUDIO_DR_UNDERFLOW_CONTROL 0x07 +#define AUDIO_DR_OVERFLOW_CONTROL 0x08 +#define AUDIO_DR_LATENCY_CONTROL 0x09 + + +/* Processing Unit Control Selectors Codes in audio20 final.pdf A.17.9 */ + +/********************************************************************** + * Up/Down-mix Processing Unit Control Selectors Codes in + * audio20 final.pdf A.17.9.1 + **********************************************************************/ +#define AUDIO_UD_CONTROL_UNDEFINED 0x00 +#define AUDIO_UD_ENABLE_CONTROL 0x01 +#define AUDIO_UD_MODE_SELECT_CONTROL 0x02 +#define AUDIO_UD_CLUSTER_CONTROL 0x03 +#define AUDIO_UD_UNDERFLOW_CONTROL 0x04 +#define AUDIO_UD_OVERFLOW_CONTROL 0x05 +#define AUDIO_UD_LATENCY_CONTROL 0x06 + + +/********************************************************************** + * Dolby Prologic Processing Unit Control Selectors Codes in + * audio20 final.pdf A.17.9.2 + **********************************************************************/ +#define AUDIO_DP_CONTROL_UNDEFINED 0x00 +#define AUDIO_DP_ENABLE_CONTROL 0x01 +#define AUDIO_DP_MODE_SELECT_CONTROL 0x02 +#define AUDIO_DP_CLUSTER_CONTROL 0x03 +#define AUDIO_DP_UNDERFLOW_CONTROL 0x04 +#define AUDIO_DP_OVERFLOW_CONTROL 0x05 +#define AUDIO_DP_LATENCY_CONTROL 0x06 + + +/********************************************************************** + * Stereo Extender Processing Unit Control Selectors Codes in + * audio20 final.pdf A.17.9.3 + **********************************************************************/ +#define AUDIO_ST_EXT_CONTROL_UNDEFINED 0x00 +#define AUDIO_ST_EXT_ENABLE_CONTROL 0x01 +#define AUDIO_ST_EXT_WIDTH_CONTROL 0x02 +#define AUDIO_ST_EXT_UNDERFLOW_CONTROL 0x03 +#define AUDIO_ST_EXT_OVERFLOW_CONTROL 0x04 +#define AUDIO_ST_EXT_LATENCY_CONTROL 0x05 + + +/********************************************************************** + * Extension Unit Control Selectors Codes in audio20 final.pdf A.17.10 + **********************************************************************/ +#define AUDIO_XU_CONTROL_UNDEFINED 0x00 +#define AUDIO_XU_ENABLE_CONTROL 0x01 +#define AUDIO_XU_CLUSTER_CONTROL 0x02 +#define AUDIO_XU_UNDERFLOW_CONTROL 0x03 +#define AUDIO_XU_OVERFLOW_CONTROL 0x04 +#define AUDIO_XU_LATENCY_CONTROL 0x05 + + +/********************************************************************** + * AudioStreaming Interface Control Selectors Codes in + * audio20 final.pdf A.17.11 + **********************************************************************/ +#define AUDIO_AS_CONTROL_UNDEFINED 0x00 +#define AUDIO_AS_ACT_ALT_SETTING_CONTROL 0x01 +#define AUDIO_AS_VAL_ALT_SETTINGS_CONTROL 0x02 +#define AUDIO_AS_AUDIO_DATA_FORMAT_CONTROL 0x03 + +/********************************************************************** + * Encoder Control Selectors Codes in audio20 final.pdf A.17.12 + **********************************************************************/ +#define AUDIO_EN_CONTROL_UNDEFINED 0x00 +#define AUDIO_EN_BIT_RATE_CONTROL 0x01 +#define AUDIO_EN_QUALITY_CONTROL 0x02 +#define AUDIO_EN_VBR_CONTROL 0x03 +#define AUDIO_EN_TYPE_CONTROL 0x04 +#define AUDIO_EN_UNDERFLOW_CONTROL 0x05 +#define AUDIO_EN_OVERFLOW_CONTROL 0x06 +#define AUDIO_EN_ENCODER_ERROR_CONTROL 0x07 +#define AUDIO_EN_PARAM1_CONTROL 0x08 +#define AUDIO_EN_PARAM2_CONTROL 0x09 +#define AUDIO_EN_PARAM3_CONTROL 0x0A +#define AUDIO_EN_PARAM4_CONTROL 0x0B +#define AUDIO_EN_PARAM5_CONTROL 0x0C +#define AUDIO_EN_PARAM6_CONTROL 0x0D +#define AUDIO_EN_PARAM7_CONTROL 0x0E +#define AUDIO_EN_PARAM8_CONTROL 0x0F + +/* Decoder Control Selectors Codes in audio20 final.pdf A.17.13 */ + +/********************************************************************** + * MPEG Decoder Control Selectors Codes in audio20 final.pdf A.17.13.1 + **********************************************************************/ +#define AUDIO_MD_CONTROL_UNDEFINED 0x00 +#define AUDIO_MD_DUAL_CHANNEL_CONTROL 0x01 +#define AUDIO_MD_SECOND_STEREO_CONTROL 0x02 +#define AUDIO_MD_MULTILINGUAL_CONTROL 0x03 +#define AUDIO_MD_DYN_RANGE_CONTROL 0x04 +#define AUDIO_MD_SCALING_CONTROL 0x05 +#define AUDIO_MD_HILO_SCALING_CONTROL 0x06 +#define AUDIO_MD_UNDERFLOW_CONTROL 0x07 +#define AUDIO_MD_OVERFLOW_CONTROL 0x08 +#define AUDIO_MD_DECODER_ERROR_CONTROL 0x09 + +/********************************************************************** + * AC-3 Decoder Control Selectors Codes in audio20 final.pdf A.17.13.2 + **********************************************************************/ +#define AUDIO_AD_CONTROL_UNDEFINED 0x00 +#define AUDIO_AD_MODE_CONTROL 0x01 +#define AUDIO_AD_DYN_RANGE_CONTROL 0x02 +#define AUDIO_AD_SCALING_CONTROL 0x03 +#define AUDIO_AD_HILO_SCALING_CONTROL 0x04 +#define AUDIO_AD_UNDERFLOW_CONTROL 0x05 +#define AUDIO_AD_OVERFLOW_CONTROL 0x06 +#define AUDIO_AD_DECODER_ERROR_CONTROL 0x07 + +/********************************************************************** + * WMA Decoder Control Selectors Codes in audio20 final.pdf A.17.13.3 + **********************************************************************/ +#define AUDIO_WD_CONTROL_UNDEFINED 0x00 +#define AUDIO_WD_UNDERFLOW_CONTROL 0x01 +#define AUDIO_WD_OVERFLOW_CONTROL 0x02 +#define AUDIO_WD_DECODER_ERROR_CONTROL 0x03 + +/********************************************************************** + * DTS Decoder Control Selectors Codes in audio20 final.pdf A.17.13.4 + **********************************************************************/ +#define AUDIO_DD_CONTROL_UNDEFINED 0x00 +#define AUDIO_DD_UNDERFLOW_CONTROL 0x01 +#define AUDIO_DD_OVERFLOW_CONTROL 0x02 +#define AUDIO_DD_DECODER_ERROR_CONTROL 0x03 + + +/********************************************************************** + * Endpoint Control Selectors Codes in audio20 final.pdf A.17.14 + **********************************************************************/ +#define AUDIO_EP_CONTROL_UNDEFINED 0x00 +#define AUDIO_EP_PITCH_CONTROL 0x01 +#define AUDIO_EP_DATA_OVERRUN_CONTROL 0x02 +#define AUDIO_EP_DATA_UNDERRUN_CONTROL 0x03 + + + +#define AUDIO_ENABLE_CONTROL 0x01 /* Common Selector */ +#define AUDIO_MODE_SELECT_CONTROL 0x02 /* Common Selector */ + +/* - Up/Down-mix Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */ + +/* - Dolby Prologic Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */ + +/* - 3D Stereo Extender Control Selectors */ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +#define AUDIO_SPACIOUSNESS_CONTROL 0x02 + +/********************************************************************** + * Reverberation Control Selectors + **********************************************************************/ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +#define AUDIO_REVERB_LEVEL_CONTROL 0x02 +#define AUDIO_REVERB_TIME_CONTROL 0x03 +#define AUDIO_REVERB_FEEDBACK_CONTROL 0x04 + +/********************************************************************** + * Chorus Control Selectors + **********************************************************************/ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +#define AUDIO_CHORUS_LEVEL_CONTROL 0x02 +#define AUDIO_SHORUS_RATE_CONTROL 0x03 +#define AUDIO_CHORUS_DEPTH_CONTROL 0x04 + +/********************************************************************** + * Dynamic Range Compressor Control Selectors + **********************************************************************/ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ +#define AUDIO_COMPRESSION_RATE_CONTROL 0x02 +#define AUDIO_MAX_AMPL_CONTROL 0x03 +#define AUDIO_THRESHOLD_CONTROL 0x04 +#define AUDIO_ATTACK_TIME_CONTROL 0x05 +#define AUDIO_RELEASE_TIME_CONTROL 0x06 + +/********************************************************************** + * Extension Unit Control Selectors + **********************************************************************/ +/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */ + + +/********************************************************************** + * Endpoint Control Selectors + **********************************************************************/ +#define AUDIO_SAMPLING_FREQ_CONTROL 0x01 +#define AUDIO_PITCH_CONTROL 0x02 + + +/* Audio Format Specific Control Selectors */ + +/********************************************************************** + * MPEG Control Selectors + **********************************************************************/ +#define AUDIO_MPEG_CONTROL_UNDEFINED 0x00 +#define AUDIO_MPEG_DUAL_CHANNEL_CONTROL 0x01 +#define AUDIO_MPEG_SECOND_STEREO_CONTROL 0x02 +#define AUDIO_MPEG_MULTILINGUAL_CONTROL 0x03 +#define AUDIO_MPEG_DYN_RANGE_CONTROL 0x04 +#define AUDIO_MPEG_SCALING_CONTROL 0x05 +#define AUDIO_MPEG_HILO_SCALING_CONTROL 0x06 + + +/********************************************************************** + * AC-3 Control Selectors + **********************************************************************/ +#define AUDIO_AC3_CONTROL_UNDEFINED 0x00 +#define AUDIO_AC3_MODE_CONTROL 0x01 +#define AUDIO_AC3_DYN_RANGE_CONTROL 0x02 +#define AUDIO_AC3_SCALING_CONTROL 0x03 +#define AUDIO_AC3_HILO_SCALING_CONTROL 0x04 + + +/********************************************************************** + * Audio Format Type Descriptor Sizes + **********************************************************************/ +#define AUDIO_FORMAT_TYPE_I_DESC_SZ(n) 0x08+(n*3) +#define AUDIO_FORMAT_TYPE_II_DESC_SZ(n) 0x09+(n*3) +#define AUDIO_FORMAT_TYPE_III_DESC_SZ(n) 0x08+(n*3) +#define AUDIO_FORMAT_MPEG_DESC_SIZE 0x09 +#define AUDIO_FORMAT_AC3_DESC_SIZE 0x0A + + +/* Audio Data Format Codes */ + +/********************************************************************** + * Audio Format Types in Frmts20 final.pdf Appendix A A.1: + **********************************************************************/ +#define AUDIO_FORMAT_TYPE_UNDEFINED 0x00 +#define AUDIO_FORMAT_TYPE_I 0x01 +#define AUDIO_FORMAT_TYPE_II 0x02 +#define AUDIO_FORMAT_TYPE_III 0x03 +#define AUDIO_EXT_FORMAT_TYPE_I 0x81 +#define AUDIO_EXT_FORMAT_TYPE_II 0x82 +#define AUDIO_EXT_FORMAT_TYPE_III 0x83 + + +/********************************************************************** + * Audio Data Format Type I Bit Allocations in + * Frmts20 final.pdf Appendix A A.2.1: + **********************************************************************/ +#define AUDIO_FORMAT_TYPE_I_UNDEFINED 0x00000000 +#define AUDIO_FORMAT_PCM 0x00000001 +#define AUDIO_FORMAT_PCM8 0x00000002 +#define AUDIO_FORMAT_IEEE_FLOAT 0x00000004 +#define AUDIO_FORMAT_ALAW 0x00000008 +#define AUDIO_FORMAT_MULAW 0x00000010 +#define AUDIO_FORMAT_TYPE_I_RAW_DATA 0x80000000 + + +/********************************************************************** + * Audio Data Format Type II Bit Allocations in + * Frmts20 final.pdf Appendix A A.2.2: + **********************************************************************/ +//THERE IS SOME DEFFIRENT WITH THE KEIL RL +#define AUDIO_FORMAT_TYPE_II_UNDEFINED 0x00000000 +#define AUDIO_FORMAT_MPEG 0x00000001 +#define AUDIO_FORMAT_AC3 0x00000002 +#define AUDIO_FORMAT_WMA 0x00000004 +#define AUDIO_FORMAT_DTS 0x00000008 +#define AUDIO_FORMAT_TYPE_I_RAW_DATA 0x80000000 + + +/********************************************************************** + * Audio Data Format Type III Bit Allocations in + * Frmts20 final.pdf Appendix A A.2.3: + **********************************************************************/ +#define AUDIO_FORMAT_TYPE_III_UNDEFINED 0x00000000 +#define AUDIO_FORMAT_IEC1937_AC3 0x00000001 +#define AUDIO_FORMAT_IEC1937_MPEG1_L1 0x00000002 +#define AUDIO_FORMAT_IEC1937_MPEG1_L2_3_NOEXT 0x00000004 +#define AUDIO_FORMAT_IEC1937_MPEG2_EXT 0x00000008 +#define AUDIO_FORMAT_IEC1937_MPEG2_AAC_ADTS 0x00000010 +#define AUDIO_FORMAT_IEC1937_MPEG2_L1_LS 0x00000020 +#define AUDIO_FORMAT_IEC1937_MPEG2_L2_3 0x00000080 +#define AUDIO_FORMAT_IEC1937_DTS_I 0x00000100 +#define AUDIO_FORMAT_IEC1937_DTS_II 0x00000200 +#define AUDIO_FORMAT_IEC1937_DTS_III 0x00000400 +#define AUDIO_FORMAT_IEC1937_ATRAC 0x00000800 +#define AUDIO_FORMAT_IEC1937_ATRAC2_3 0x00001000 +#define AUDIO_FORMAT_TYPE_III_WMA 0x00002000 + +/********************************************************************** + * Audio Data Format Type IV Bit Allocations in + * Frmts20 final.pdf Appendix A A.2.4: + **********************************************************************/ +#define AUDIO_FORMAT_TYPE_III_UNDEFINED 0x00000000 +#define AUDIO_FORMAT_PCM 0x00000001 +#define AUDIO_FORMAT_PCM8 0x00000002 +#define AUDIO_FORMAT_IEEE_FLOAT 0x00000004 +#define AUDIO_FORMAT_ALAW 0x00000008 +#define AUDIO_FORMAT_MULAW 0x00000010 +#define AUDIO_FORMAT_MPEG_IV 0x00000020 +#define AUDIO_FORMAT_AC_3 0x00000080 +#define AUDIO_FORMAT_WMA_IV 0x00000100 +#define AUDIO_FORMAT_IEC61937_AC_3 0x00000200 +#define AUDIO_FORMAT_IEC61937_MPEG1_L1 0x00000400 +#define AUDIO_FORMAT_IEC61937_MPEG1_L23_NOEX 0x00000800 +#define AUDIO_FORMAT_IEC61937_MPEG2_EXT 0x00001000 +#define AUDIO_FORMAT_IEC61937_MPEG_2_AAC_ADTS 0x00002000 +#define AUDIO_FORMAT_IEC61937_MPEG_2_L1_LS 0x00004000 +#define AUDIO_FORMAT_IEC61937_MPEG_2_L23_LS 0x00008000 +#define AUDIO_FORMAT_IEC61937_DTS_I 0x00010000 +#define AUDIO_FORMAT_IEC61937_DTS_II 0x00020000 +#define AUDIO_FORMAT_IEC61937_DTS_III 0x00040000 +#define AUDIO_FORMAT_IEC61937_ATRAC 0x00080000 +#define AUDIO_FORMAT_IEC61937_ATRAC23 0x00100000 +#define AUDIO_FORMAT_TYPE_III_WMA_IV 0x00200000 +#define AUDIO_FORMAT_IEC60958_PCM 0x00400000 + +/********************************************************************** + * Predefined Audio Channel Configuration Bits In Audio2.0 final.pdf 4.1 + **********************************************************************/ +#define AUDIO_CHANNEL_M 0x00000000 /* Mono */ +#define AUDIO_CHANNEL_L 0x00000001 /* Left Front */ +#define AUDIO_CHANNEL_R 0x00000002 /* Right Front */ +#define AUDIO_CHANNEL_C 0x00000004 /* Center Front */ +#define AUDIO_CHANNEL_LFE 0x00000008 /* Low Freq. Enhance. */ +#define AUDIO_CHANNEL_LS 0x00000010 /* Left Surround */ +#define AUDIO_CHANNEL_RS 0x00000020 /* Right Surround */ +#define AUDIO_CHANNEL_LC 0x00000040 /* Left of Center */ +#define AUDIO_CHANNEL_RC 0x00000080 /* Right of Center */ +#define AUDIO_CHANNEL_S 0x00000100 /* Surround */ +#define AUDIO_CHANNEL_SL 0x00000200 /* Side Left */ +#define AUDIO_CHANNEL_SR 0x00000400 /* Side Right */ +#define AUDIO_CHANNEL_TC 0x00000800 /* Top */ +#define AUDIO_CHANNEL_TFL 0x00001000 +#define AUDIO_CHANNEL_TFC 0x00002000 +#define AUDIO_CHANNEL_TFR 0x00004000 +#define AUDIO_CHANNEL_TBL 0x00008000 +#define AUDIO_CHANNEL_TBC 0x00010000 +#define AUDIO_CHANNEL_TBR 0x00020000 +#define AUDIO_CHANNEL_TFLC 0x00040000 +#define AUDIO_CHANNEL_TFRC 0x00080000 +#define AUDIO_CHANNEL_LLFE 0x00100000 +#define AUDIO_CHANNEL_RLFE 0x00200000 +#define AUDIO_CHANNEL_TSL 0x00400000 +#define AUDIO_CHANNEL_TSR 0x00800000 +#define AUDIO_CHANNEL_BC 0x01000000 +#define AUDIO_CHANNEL_BLC 0x02000000 +#define AUDIO_CHANNEL_BRC 0x04000000 + + +/********************************************************************** + * Feature Unit Control Bits + **********************************************************************/ +#define AUDIO_CONTROL_MUTE 0x0001 +#define AUDIO_CONTROL_VOLUME 0x0002 +#define AUDIO_CONTROL_BASS 0x0004 +#define AUDIO_CONTROL_MID 0x0008 +#define AUDIO_CONTROL_TREBLE 0x0010 +#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020 +#define AUDIO_CONTROL_AUTOMATIC_GAIN 0x0040 +#define AUDIO_CONTROL_DEALY 0x0080 +#define AUDIO_CONTROL_BASS_BOOST 0x0100 +#define AUDIO_CONTROL_LOUDNESS 0x0200 + + +/********************************************************************** + * Processing Unit Control Bits: + **********************************************************************/ +#define AUDIO_CONTROL_ENABLE 0x0001 /* Common Bit */ +#define AUDIO_CONTROL_MODE_SELECT 0x0002 /* Common Bit */ + + +/********************************************************************** + * Up/Down-mix Control Bits + **********************************************************************/ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */ + + +/********************************************************************** + * Dolby Prologic Control Bits + **********************************************************************/ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */ + +/********************************************************************** + * 3D Stereo Extender Control Bits + **********************************************************************/ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +#define AUDIO_CONTROL_SPACIOUSNESS 0x0002 + + +/********************************************************************** + * Reverberation Control Bits + **********************************************************************/ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +#define AUDIO_CONTROL_REVERB_TYPE 0x0002 +#define AUDIO_CONTROL_REVERB_LEVEL 0x0004 +#define AUDIO_CONTROL_REVERB_TIME 0x0008 +#define AUDIO_CONTROL_REVERB_FEEDBACK 0x0010 + + +/********************************************************************** + * Chorus Control Bits + **********************************************************************/ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +#define AUDIO_CONTROL_CHORUS_LEVEL 0x0002 +#define AUDIO_CONTROL_SHORUS_RATE 0x0004 +#define AUDIO_CONTROL_CHORUS_DEPTH 0x0008 + +/********************************************************************** + * Dynamic Range Compressor Control Bits + **********************************************************************/ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ +#define AUDIO_CONTROL_COMPRESSION_RATE 0x0002 +#define AUDIO_CONTROL_MAX_AMPL 0x0004 +#define AUDIO_CONTROL_THRESHOLD 0x0008 +#define AUDIO_CONTROL_ATTACK_TIME 0x0010 +#define AUDIO_CONTROL_RELEASE_TIME 0x0020 + + +/********************************************************************** + * Extension Unit Control Bits + **********************************************************************/ +/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */ + +/********************************************************************** + * Endpoint Control Bits + **********************************************************************/ +#define AUDIO_CONTROL_SAMPLING_FREQ 0x01 +#define AUDIO_CONTROL_PITCH 0x02 +#define AUDIO_MAX_PACKETS_ONLY 0x80 + + +/* Audio Terminal Types *///////////////////////////////////////////////////////////////////////// + +/********************************************************************** + * USB Terminal Types in Termt20 final.pdf 2.1 Table 2-1: + **********************************************************************/ +#define AUDIO_TERMINAL_USB_UNDEFINED 0x0100 +#define AUDIO_TERMINAL_USB_STREAMING 0x0101 +#define AUDIO_TERMINAL_USB_VENDOR_SPECIFIC 0x01FF + +/********************************************************************** + * Input Terminal Types in Termt20 final.pdf 2.2 Table 2-2: + **********************************************************************/ +#define AUDIO_TERMINAL_INPUT_UNDEFINED 0x0200 +#define AUDIO_TERMINAL_MICROPHONE 0x0201 +#define AUDIO_TERMINAL_DESKTOP_MICROPHONE 0x0202 +#define AUDIO_TERMINAL_PERSONAL_MICROPHONE 0x0203 +#define AUDIO_TERMINAL_OMNI_DIR_MICROPHONE 0x0204 +#define AUDIO_TERMINAL_MICROPHONE_ARRAY 0x0205 +#define AUDIO_TERMINAL_PROCESSING_MIC_ARRAY 0x0206 + +/********************************************************************** + * Output Terminal Types in Termt20 final.pdf 2.3 Table 2-3: + **********************************************************************/ +#define AUDIO_TERMINAL_OUTPUT_UNDEFINED 0x0300 +#define AUDIO_TERMINAL_SPEAKER 0x0301 +#define AUDIO_TERMINAL_HEADPHONES 0x0302 +#define AUDIO_TERMINAL_HEAD_MOUNTED_AUDIO 0x0303 +#define AUDIO_TERMINAL_DESKTOP_SPEAKER 0x0304 +#define AUDIO_TERMINAL_ROOM_SPEAKER 0x0305 +#define AUDIO_TERMINAL_COMMUNICATION_SPEAKER 0x0306 +#define AUDIO_TERMINAL_LOW_FREQ_SPEAKER 0x0307 + + +/********************************************************************** + * Bi-directional Terminal Types in Termt20 final.pdf 2.4 Table 2-4: + **********************************************************************/ +#define AUDIO_TERMINAL_BIDIRECTIONAL_UNDEFINED 0x0400 +#define AUDIO_TERMINAL_HANDSET 0x0401 +#define AUDIO_TERMINAL_HEAD_MOUNTED_HANDSET 0x0402 +#define AUDIO_TERMINAL_SPEAKERPHONE 0x0403 +#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOSUPRESS 0x0404 +#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOCANCEL 0x0405 + +/********************************************************************** + * Telephony Terminal Types in Termt20 final.pdf 2.5 Table 2-5: + **********************************************************************/ +#define AUDIO_TERMINAL_TELEPHONY_UNDEFINED 0x0500 +#define AUDIO_TERMINAL_PHONE_LINE 0x0501 +#define AUDIO_TERMINAL_TELEPHONE 0x0502 +#define AUDIO_TERMINAL_DOWN_LINE_PHONE 0x0503 + +/********************************************************************** + * External Terminal Types in Termt20 final.pdf 2.6 Table 2-6: + **********************************************************************/ +#define AUDIO_TERMINAL_EXTERNAL_UNDEFINED 0x0600 +#define AUDIO_TERMINAL_ANALOG_CONNECTOR 0x0601 +#define AUDIO_TERMINAL_DIGITAL_AUDIO_INTERFACE 0x0602 +#define AUDIO_TERMINAL_LINE_CONNECTOR 0x0603 +#define AUDIO_TERMINAL_LEGACY_AUDIO_CONNECTOR 0x0604 +#define AUDIO_TERMINAL_SPDIF_INTERFACE 0x0605 +#define AUDIO_TERMINAL_1394_DA_STREAM 0x0606 +#define AUDIO_TERMINAL_1394_DA_STREAM_TRACK 0x0607 +#define AUDIO_TERMINAL_ADAT_LIGHTPIPE 0x0608 +#define AUDIO_TERMINAL_TDIF 0x0609 +#define AUDIO_TERMINAL_MADI 0x060A + +/********************************************************************** + * Embedded Function Terminal Types in + * Termt20 final.pdf 2.7 Table 2-7: + **********************************************************************/ +#define AUDIO_TERMINAL_EMBEDDED_UNDEFINED 0x0700 +#define AUDIO_TERMINAL_CALIBRATION_NOISE 0x0701 +#define AUDIO_TERMINAL_EQUALIZATION_NOISE 0x0702 +#define AUDIO_TERMINAL_CD_PLAYER 0x0703 +#define AUDIO_TERMINAL_DAT 0x0704 +#define AUDIO_TERMINAL_DCC 0x0705 +#define AUDIO_TERMINAL_MINI_DISK 0x0706 +#define AUDIO_TERMINAL_ANALOG_TAPE 0x0707 +#define AUDIO_TERMINAL_PHONOGRAPH 0x0708 +#define AUDIO_TERMINAL_VCR_AUDIO 0x0709 +#define AUDIO_TERMINAL_VIDEO_DISC_AUDIO 0x070A +#define AUDIO_TERMINAL_DVD_AUDIO 0x070B +#define AUDIO_TERMINAL_TV_TUNER_AUDIO 0x070C +#define AUDIO_TERMINAL_SATELLITE_RECEIVER_AUDIO 0x070D +#define AUDIO_TERMINAL_CABLE_TUNER_AUDIO 0x070E +#define AUDIO_TERMINAL_DSS_AUDIO 0x070F +#define AUDIO_TERMINAL_RADIO_RECEIVER 0x0710 +#define AUDIO_TERMINAL_RADIO_TRANSMITTER 0x0711 +#define AUDIO_TERMINAL_MULTI_TRACK_RECORDER 0x0712 +#define AUDIO_TERMINAL_SYNTHESIZER 0x0713 +#define AUDIO_TERMINAL_PIANO 0x0714 +#define AUDIO_TERMINAL_GUITAR 0x0715 +#define AUDIO_TERMINAL_DRUMS_RHYTHM 0x0716 +#define AUDIO_TERMINAL_OTHER 0x0717 + + +#endif /* __USB_AUDIO_H__ */ diff --git a/CoX/middleware/USB_CLASS/USB_CDC/cdc_callback.c b/CoX/middleware/USB_CLASS/USB_CDC/cdc_callback.c new file mode 100644 index 00000000..bf652082 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_CDC/cdc_callback.c @@ -0,0 +1,909 @@ +/***************************************************************************** + * U S B - C D C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : CDC_CALLBACK.c + * @brief : USB Communication Device Class Call Back module + * @version : 1.1 + * @date : 10. MAR. 2011 + * @author : CooCox + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **********************************************************************/ +#include "usb_Enumerate.h" +#include "cdc_callback.h" + +void CDC_Event(USBCDC_Dev *dev); + +/********************************************************************** + * Buffer masks + **********************************************************************/ +#define CDC_BUF_SIZE (64) /*Output buffer in bytes (power 2)*/ + /*large enough for file transfer */ +#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul) + +/********************************************************************** + * Buffer read / write macros + **********************************************************************/ +#define CDC_BUF_RESET(cdcBuf) (cdcBuf->rdIdx = cdcBuf->wrIdx = 0) +#define CDC_BUF_WR(cdcBuf, dataIn) (cdcBuf->data[CDC_BUF_MASK & cdcBuf->wrIdx++] = (dataIn)) +#define CDC_BUF_RD(cdcBuf) (cdcBuf->data[CDC_BUF_MASK & cdcBuf->rdIdx++]) +#define CDC_BUF_EMPTY(cdcBuf) (cdcBuf->rdIdx == cdcBuf->wrIdx) +#define CDC_BUF_FULL(cdcBuf) (cdcBuf->rdIdx == cdcBuf->wrIdx+1) +#define CDC_BUF_COUNT(cdcBuf) (CDC_BUF_MASK & (cdcBuf->wrIdx - cdcBuf->rdIdx)) + +/********************************************************************** + * Function declaration + **********************************************************************/ +unsigned short CDC_GetSerialState (USBCDC_Dev *dev); + +/********************************************************************************************************//** + * @brief read data from CDC_OutBuf + * @param[out] buffer : buffer for CDC Out data + * @param[in] length : buffer length of CDC Out data + * buf : buffer for CDC Out data + * @return The length of the read byte +************************************************************************************************************/ +int CDC_RdOutBuf (CDC_BUF_T *buf,char *buffer, const int *length) +{ + int bytesToRead, bytesRead; + + /* Read *length bytes, block if *bytes are not avaialable */ + bytesToRead = *length; + bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length); + bytesRead = bytesToRead; + + + // ... add code to check for underrun + + while (bytesToRead--) + { + *buffer++ = CDC_BUF_RD(buf); + } + return (bytesRead); +} + +/********************************************************************************************************//** + * @brief Write data to CDC_OutBuf + * @param[out] buffer : buffer for CDC Out data + * @param[in] length : buffer length of CDC Out data + * buf : buffer for CDC Out data + * @return The length of the write byte +************************************************************************************************************/ +int CDC_WrOutBuf (CDC_BUF_T *buf,const char *buffer, int *length) +{ + int bytesToWrite, bytesWritten; + + // Write *length bytes + bytesToWrite = *length; + bytesWritten = bytesToWrite; + + + // ... add code to check for overwrite + + while (bytesToWrite) + { + CDC_BUF_WR(buf, *buffer++); // Copy Data to buffer + bytesToWrite--; + } + + return (bytesWritten); +} + + +/********************************************************************************************************//** + * @brief Check if character(s) are available at CDC_OutBuf + * @param[out] availChar : The length of the available byte at CDC_OutBuf + * @param[in] buf : buffer for CDC Out data + * @return 0 +************************************************************************************************************/ +int CDC_OutBufAvailChar (CDC_BUF_T *buf,int *availChar) +{ + + *availChar = CDC_BUF_COUNT(buf); + + return (0); +} +/* end Buffer handling */ + + +/********************************************************************************************************//** + * @brief CDC init + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_Init (USBCDC_Dev *dev) +{ + dev->cdc_device_init (dev->cdc_device,(void *)&dev->CDC_LineCoding); + dev->CDC_DepInEmpty = 1; + dev->CDC_SerialState = CDC_GetSerialState(dev); + +// CDC_BUF_RESET((CDC_BUF_T *)(&dev->CDC_OutBuf)); +} + + +/********************************************************************************************************//** + * @brief CDC SendEncapsulatedCommand Request Callback,Called automatically on CDC SEND_ENCAPSULATED_COMMAND Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SendEncapsulatedCommand (USBCDC_Dev *dev) +{ + + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief CDC GetEncapsulatedResponse Request Callback,Called automatically on CDC Get_ENCAPSULATED_RESPONSE Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetEncapsulatedResponse (USBCDC_Dev *dev) +{ + + /* ... add code to handle request */ + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief CDC SetCommFeature Request Callback,Called automatically on CDC Set_COMM_FATURE Request + * @param[in] wFeatureSelector: FeatureSelector + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetCommFeature (USBCDC_Dev *dev, unsigned short wFeatureSelector) +{ + + /* ... add code to handle request */ + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief CDC GetCommFeature Request Callback,Called automatically on CDC Get_COMM_FATURE Request + * @param[in] wFeatureSelector : FeatureSelector + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetCommFeature (USBCDC_Dev *dev, unsigned short wFeatureSelector) +{ + + /* ... add code to handle request */ + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief CDC ClearCommFeature Request Callback,Called automatically on CDC CLEAR_COMM_FATURE Request + * @param[in] wFeatureSelector: FeatureSelector + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_ClearCommFeature (USBCDC_Dev *dev, unsigned short wFeatureSelector) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetAuxLineState Request Callback,Called automatically on CDC SET_AUX_LINE_STATE Request + * @param[in] wIsConnect: + * - 1 Connect + * - 0 Disconnect + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetAuxLineState (USBCDC_Dev *dev, unsigned short wIsConnect) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetHookState Request Callback,Called automatically on CDC SET_HOOK_STATE Request + * @param[in] wRelayConfig: + * ¨C 0 On hook + * ¨C 1 Off hook + * - 2 SNOOPING + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetHookState (USBCDC_Dev *dev, unsigned short wRelayConfig) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC PulseSetup Request Callback,Called automatically on CDC PULSE_SETUP Request + * @param[in] wIsEnable: + * 0 ¨C Disable + * 1 ¨C Enable + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_PulseSetup (USBCDC_Dev *dev, unsigned short wIsEnable) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SendPulse Request Callback,Called automatically on CDC SEND_PULSE Request + * @param[in] wCycles: contains the number of make/break pulse cycles to generate + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SendPulse (USBCDC_Dev *dev, unsigned short wCycles) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetPulseTime Request Callback,Called automatically on CDC SET_PULSE_TIME Request + * @param[in] wTiming: specifies the break time period in the high byte and + * the make time period in the low byte + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetPulseTime (USBCDC_Dev *dev, unsigned short wTiming) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC RingAuxJack Request Callback,Called automatically on CDC RING_AUX_JACK Request + * @param[in] wFeatureSelector: wNumberOfRings: contains the number of ring signals to generate on + * a secondary phone jack of the device. + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_RingAuxJack (USBCDC_Dev *dev, unsigned short wNumberOfRings) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetLineCoding Request Callback, Called automatically on CDC SET_LINE_CODING Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetLineCoding (USBCDC_Dev *dev) +{ + + dev->CDC_LineCoding.dwDTERate = (dev->usb_enu.EP0Buf[0] << 0) + | (dev->usb_enu.EP0Buf[1] << 8) + | (dev->usb_enu.EP0Buf[2] << 16) + | (dev->usb_enu.EP0Buf[3] << 24); + dev->CDC_LineCoding.bCharFormat = dev->usb_enu.EP0Buf[4]; + dev->CDC_LineCoding.bParityType = dev->usb_enu.EP0Buf[5]; + dev->CDC_LineCoding.bDataBits = dev->usb_enu.EP0Buf[6]; + + dev->cdc_device_deinit(dev->cdc_device); + dev->cdc_device_init (dev->cdc_device,(void *)&dev->CDC_LineCoding); +// ser_InitPort (dev->CDC_LineCoding.dwDTERate, +// dev->CDC_LineCoding.bDataBits, +// dev->CDC_LineCoding.bParityType, +// dev->CDC_LineCoding.bCharFormat); + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief CDC GetLineCoding Request Callback,Called automatically on CDC GET_LINE_CODING Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetLineCoding (USBCDC_Dev *dev,uint32_t para) +{ + + dev->usb_enu.EP0Buf[0] = (dev->CDC_LineCoding.dwDTERate >> 0) & 0xFF; + dev->usb_enu.EP0Buf[1] = (dev->CDC_LineCoding.dwDTERate >> 8) & 0xFF; + dev->usb_enu.EP0Buf[2] = (dev->CDC_LineCoding.dwDTERate >> 16) & 0xFF; + dev->usb_enu.EP0Buf[3] = (dev->CDC_LineCoding.dwDTERate >> 24) & 0xFF; + dev->usb_enu.EP0Buf[4] = dev->CDC_LineCoding.bCharFormat; + dev->usb_enu.EP0Buf[5] = dev->CDC_LineCoding.bParityType; + dev->usb_enu.EP0Buf[6] = dev->CDC_LineCoding.bDataBits; + + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetControlLineState Request Callback,Called automatically on CDC SET_CONTROL_LINE_STATE Request + * @param[in] wControlSignalBitmap: + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetControlLineState (USBCDC_Dev *dev,unsigned short wControlSignalBitmap) +{ + + CDC_Event(dev); + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SendBreak Request Callback,Called automatically on CDC Set_COMM_FATURE Request + * @param[in] wDurationOfBreak: + * - 0xFFFF start of Break + * - 0x0000 stop of Break + * - 0x#### Duration of Break + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SendBreak (USBCDC_Dev *dev, unsigned short wDurationOfBreak) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetRingerParms Request Callback,Called automatically on CDC SET_RINGER_PARMS Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetRingerParms (USBCDC_Dev *dev) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC GetRingerParms Request Callback,Called automatically on CDC GET_RINGER_PARMS Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetRingerParms (USBCDC_Dev *dev) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetOperationParms Request Callback,Called automatically on CDC SET_OPERATION_PARMS Request + * @param[in] wOperationMode: + * - 0x2 Host Centric Mode + * - 0x1 Standalone Mode + * - 0x0 Simple Mode + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetOperationParms (USBCDC_Dev *dev, unsigned short wOperationMode) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC GetOperationParms Request Callback,Called automatically on CDC GET_OPERATION_PARMS Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetOperationParms (USBCDC_Dev *dev) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetLineParms Request Callback,Called automatically on CDC SET_LINE_PARMS Request + * @param[in] wLineStateChange: + * - 0x0000 Drop the active call on the line. + * - 0x0001 Start a new call on the line. + * - 0x0002 Apply ringing to the line. + * - 0x0003 Remove ringing from the line. + * - 0x0004 Switch to a specific call on the line. Data is used to + * pass a 1-byte call index that identifies the call. + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetLineParms (USBCDC_Dev *dev, unsigned short wLineStateChange) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC GetLineParms Request Callback,Called automatically on CDC GET_LINE_PARMS Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetLineParms (USBCDC_Dev *dev) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC DialDigits Request Callback,Called automatically on CDC DIAL_DIGITS Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_DialDigits (USBCDC_Dev *dev) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetLineParms Request Callback,Called automatically on CDC SET_LINE_PARMS Request + * @param[in] wUnitParameter: + * - bEntityId Unit Id + * - bParameterIndex A zero based value indicating Unit parameter index. + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetUnitParameter (USBCDC_Dev *dev, unsigned short wUnitParameter) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC GetLineParms Request Callback,Called automatically on CDC GET_LINE_PARMS Request + * @param[in] wUnitParameter: + * - bEntityId Unit Id + * - bParameterIndex A zero based value indicating Unit parameter index. + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetUnitParameter (USBCDC_Dev *dev, unsigned short wUnitParameter) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC ClearUnitParameter Request Callback,Called automatically on CDC CLEAR_UNIT_PARAMETER Request + * @param[in] wUnitParameter: + * - bEntityId Unit Id + * - bParameterIndex A zero based value indicating Unit parameter index. + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_ClearUnitParameter (USBCDC_Dev *dev, unsigned short wUnitParameter) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC GetProfile Request Callback,Called automatically on CDC GET_PROFILE Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetProfile (USBCDC_Dev *dev) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetEthernetMulticastFilters Request Callback,Called automatically on + * CDC SET_ETHERNET_MULTICAST_FILTERS Request + * @param[in] wNumberOfFilters: Number of filters (N) + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetEthernetMulticastFilters (USBCDC_Dev *dev, unsigned short wNumberOfFilters) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetEthernetPowerManagementPatternFilter Request Callback,Called automatically on + * CDC SET_ETHERNET_PMP_FILTER Request + * @param[in] wNumberOfFilters: Number of filters (N) + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetEthernetPowerManagementPatternFilter (USBCDC_Dev *dev, unsigned short wNumberOfFilters) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC GetEthernetPowerManagementPatternFilter Request Callback,Called automatically on + * CDC GET_ETHERNET_PMP_FILTER Request + * @param[in] wNumberOfFilters: Number of filters (N) + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetEthernetPowerManagementPatternFilter (USBCDC_Dev *dev, unsigned short wNumberOfFilters) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetEthernetPacketFilter Request Callback,Called automatically on + * CDC SET_ETHERNET_PACKET_FILTER Request + * @param[in] wPacketFilterBitmap: + * - D0 PACKET_TYPE_PROMISCUOUS + * - D1 PACKET_TYPE_ALL_MULTICAST + * - D2 PACKET_TYPE_DIRECTED + * - D3 PACKET_TYPE_BROADCAST + * - D4 PACKET_TYPE_MULTICAST + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetEthernetPacketFilter (USBCDC_Dev *dev, unsigned short wPacketFilterBitmap) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC GetEthernetStatistic Request Callback,Called automatically on + * CDC GET_ETHERNET_STATISTIC Request + * @param[in] wFeatureSelector: + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetEthernetStatistic (USBCDC_Dev *dev, unsigned short wFeatureSelector) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetATMDataFormat Request Callback,Called automatically on + * CDC SET_ATM_DATA_FORMAT Request + * @param[in] wDataFormat: + * - 1 Type 1 format: concatenated ATM cells + * - 2 Type 2 format: ATM header template + concatenated ATM cell payloads + * - 3 Type 3 format: AAL 5 SDU + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetATMDataFormat (USBCDC_Dev *dev, unsigned short wDataFormat) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC GetATMDeviceStatistics Request Callback,Called automatically on + * CDC GET_ATM_DEVICE_STATISTICS Request + * @param[in] wFeatureSelector: + * - 0 Reserved for future use + * - 1 The number of cells that have been sent upstream to the WAN link by the ATM layer. + * - 2 The number of cells that have been received downstream from the WAN link by the ATM layer. + * - 3 The number of cells that have been received downstream from the WAN link by the ATM layer + * and discarded due to congestion on the USB link. + * - 4 The number of cells that have been received downstream from the WAN link by the ATM layer + * and discarded due to AAL5 CRC errors. + * - 5 The number of cells that have been received downstream from the WAN link and discarded + * due to HEC errors in the cell header. + * - 6 The number of cells that have been received downstream from the WAN link and have been + * detected with HEC errors in the cell header and successfully corrected. + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetATMDeviceStatistics (USBCDC_Dev *dev, unsigned short wFeatureSelector) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC SetATMDefaultVC Request Callback,Called automatically on + * CDC SET_ATM_DEFAULT_VC Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_SetATMDefaultVC (USBCDC_Dev *dev) +{ + + /* ... add code to handle request */ + return (TRUE); +} + +/********************************************************************************************************//** + * @brief CDC GetATMVCStatistics Request Callback,Called automatically on + * CDC GET_ATM_VC_STATISTICS Request + * @param[in] wFeatureSelector : + * - 00 Reserved for future use + * - 01 The number of cells that have been sent upstream to the WAN link for the specified + * VPI/VCI since the device has been powered on or reset. + * - 02 The number of cells that have been received downstream from the WAN link for the + * specified VPI/VCI since the device has been powered on or reset. + * dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t CDC_GetATMVCStatistics (USBCDC_Dev *dev, unsigned short wFeatureSelector) +{ + + /* ... add code to handle request */ + return (TRUE); +} + + + + +/********************************************************************************************************//** + * @brief CDC_BulkIn call on DataIn Request + * @param[in] dev : a point which contains all the global variables which using in this function + * event : usb endpoint event type + * @return None +************************************************************************************************************/ +void bulk_in_handle(USBCDC_Dev *dev,uint32_t Event) +{ +// int numBytesRead, numBytesAvail; +// +// //ser_AvailChar (&numBytesAvail); +// +// // ... add code to check for overwrite +// +// //numBytesRead = ser_Read ((char *)&dev->BulkBufIn[0], &numBytesAvail); +// +// // send over USB +// if (numBytesRead > 0) +// { +// dev->usb_enu.usb->USB_WriteEP (CDC_DEP_IN, &dev->BulkBufIn[0], numBytesRead); +// } +// else +// { +// dev->CDC_DepInEmpty = 1; +// } +} + + +/********************************************************************************************************//** + * @brief CDC_BulkOut call on DataOut Request + * @param[in] dev : a point which contains all the global variables which using in this function + * event : usb endpoint event type + * @return None +************************************************************************************************************/ +void bulk_out_handle(USBCDC_Dev *dev,uint32_t Event) +{ + int numBytesRead; + + // get data from USB into intermediate buffer + numBytesRead = dev->usb_enu.usb->USB_ReadEP(CDC_DEP_OUT, &dev->BulkBufOut[0]); + + // ... add code to check for overwrite + + // store data in a buffer to transmit it over serial interface + CDC_WrOutBuf (&dev->CDC_OutBuf,(char *)&dev->BulkBufOut[0], &numBytesRead); + +} + +/********************************************************************************************************//** + * @brief Send the NETWORK_CONNECTION notification as defined in CDC120.pdf, 6.3.1. + * @param[in] dev : a point which contains all the global variables which using in this function + * wIsConnected : + * @return None +************************************************************************************************************/ +void CDC_NetworkConnection (USBCDC_Dev *dev, unsigned short wIsConnected) +{ + /* ... add code to handle Notifications */ +} + +/********************************************************************************************************//** + * @brief Send the RESPONSE_AVAILABLE notification as defined in CDC120.pdf, 6.3.2. + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_ResponseAvailable (USBCDC_Dev *dev) +{ + /* ... add code to handle Notifications */ +} + +/********************************************************************************************************//** + * @brief Send the CONNECTION_SPEED_CHANGE notification as defined in CDC120.pdf, 6.3.3. + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_ConnectionSpeedChange (USBCDC_Dev *dev) +{ + /* ... add code to handle Notifications */ +} + +/********************************************************************************************************//** + * @brief Send the AUX_JACK_ HOOK_STATE notification as defined in PSTN120.pdf, 6.5.2. + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_AuxJackHookState (USBCDC_Dev *dev) +{ + /* ... add code to handle Notifications */ +} + +/********************************************************************************************************//** + * @brief Send the RING_DETECT notification as defined in PSTN120.pdf, 6.5.3. + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_RingDetect (USBCDC_Dev *dev) +{ + /* ... add code to handle Notifications */ +} + +/********************************************************************************************************//** + * @brief Send the CALL_STATE_CHANGE notification as defined in PSTN120.pdf, 6.5.5. + * @param[in] dev : a point which contains all the global variables which using in this function + * wCallIndex : + * @return None +************************************************************************************************************/ +void CDC_CallStateChange (USBCDC_Dev *dev, unsigned short wCallIndex) +{ + /* ... add code to handle Notifications */ +} + +/********************************************************************************************************//** + * @brief Send the LINE_STATE_CHANGE notification as defined in PSTN120.pdf, 6.5.6. + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_LineStateChange (USBCDC_Dev *dev, unsigned short wLineState) +{ + /* ... add code to handle Notifications */ +} + + + +/********************************************************************************************************//** + * @brief Get the SERIAL_STATE as defined in PSTN120.pdf, 6.5.4, Table 31. + * @param[in] dev : a point which contains all the global variables which using in this function + * @return SerialState as defined in PSTN120.pdf +************************************************************************************************************/ +unsigned short CDC_GetSerialState (USBCDC_Dev *dev) +{ + unsigned short temp; + + dev->CDC_SerialState = 0; + //ser_LineState (&temp); + + if (temp & 0x8000) dev->CDC_SerialState |= CDC_SERIAL_STATE_RX_CARRIER; + if (temp & 0x2000) dev->CDC_SerialState |= CDC_SERIAL_STATE_TX_CARRIER; + if (temp & 0x0010) dev->CDC_SerialState |= CDC_SERIAL_STATE_BREAK; + if (temp & 0x4000) dev->CDC_SerialState |= CDC_SERIAL_STATE_RING; + if (temp & 0x0008) dev->CDC_SerialState |= CDC_SERIAL_STATE_FRAMING; + if (temp & 0x0004) dev->CDC_SerialState |= CDC_SERIAL_STATE_PARITY; + if (temp & 0x0002) dev->CDC_SerialState |= CDC_SERIAL_STATE_OVERRUN; + + return (dev->CDC_SerialState); +} + + +/********************************************************************************************************//** + * @brief Send the SERIAL_STATE notification as defined in PSTN120.pdf, 6.5.4. + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_SerialStateFun (USBCDC_Dev *dev) +{ + + dev->NotificationBuf[0] = 0xA1; // bmRequestType + dev->NotificationBuf[1] = CDC_NOTIFICATION_SERIAL_STATE; // bNotification (SERIAL_STATE) + dev->NotificationBuf[2] = 0x00; // wValue + dev->NotificationBuf[3] = 0x00; + dev->NotificationBuf[4] = 0x00; // wIndex (Interface #, LSB first) + dev->NotificationBuf[5] = 0x00; + dev->NotificationBuf[6] = 0x02; // wLength (Data length = 2 bytes, LSB first) + dev->NotificationBuf[7] = 0x00; + dev->NotificationBuf[8] = (dev->CDC_SerialState >> 0) & 0xFF; // UART State Bitmap (16bits, LSB first) + dev->NotificationBuf[9] = (dev->CDC_SerialState >> 8) & 0xFF; + + dev->usb_enu.usb->USB_WriteEP (CDC_CEP_IN, &dev->NotificationBuf[0], 10); // send notification +} + +/********************************************************************************************************//** + * @brief CDC VCOM open + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_Open(USBCDC_Dev *dev, USBCDC_Dev *user_config) +{ + dev->usb_enu.cdc_data = dev; + dev->usb_enu.g_pfn_cdc_GetLineCoding = (PFN_CDC_CALLBACK *)CDC_GetLineCoding; + dev->usb_enu.g_pfn_cdc_SetLineCoding = (PFN_CDC_CALLBACK *)CDC_SetLineCoding; + dev->usb_enu.g_pfn_cdc_SetCommFeature = (PFN_CDC_CALLBACK *)CDC_SetCommFeature; + dev->usb_enu.g_pfn_cdc_SendEncapsulatedCommand = (PFN_CDC_CALLBACK *)CDC_SendEncapsulatedCommand; + dev->usb_enu.g_pfn_cdc_SendBreak = (PFN_CDC_CALLBACK *)CDC_SendBreak; + dev->usb_enu.g_pfn_cdc_SetControlLineState = (PFN_CDC_CALLBACK *)CDC_SetControlLineState; + + + CDC_Init(dev); + USB_Init(&dev->usb_enu); +} + +/********************************************************************************************************//** + * @brief connect CDC to usb host + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_Connect(USBCDC_Dev *dev,uint32_t con) +{ + dev->usb_enu.usb->USB_Connect(con); +} + +/********************************************************************************************************//** + * @brief Get ADC Configuration statue + * @param[in] dev : a point which contains all the global variables which using in this function + * @return Configuration statue +************************************************************************************************************/ +uint8_t CDC_Configurated(USBCDC_Dev *dev) +{ + return dev->usb_enu.USB_Configuration; +} + +/********************************************************************************************************//** + * @brief ADC event callback setup + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void CDC_Event(USBCDC_Dev *dev) +{ + dev->usb_enu.usb->USB_Event((CDC_DEP_OUT&0xf),(USB_Event_Handler)bulk_out_handle,(void *)dev); + dev->usb_enu.usb->USB_Event((CDC_DEP_IN &0xf),(USB_Event_Handler)bulk_in_handle, (void *)dev); +} + +/********************************************************************************************************//** + * @brief ADC read,data transfer from host to device + * @param[in] dev : a point which contains all the global variables which using in this function + * rbuf : buffer of read + * length : byte length of read + * @return None +************************************************************************************************************/ +uint32_t CDC_Read(USBCDC_Dev *dev, uint8_t *rbuf, uint32_t length) +{ + dev->cdc_device_read(dev->cdc_device, dev->CDC_InBuf.data, length); + return length; +} + +/********************************************************************************************************//** + * @brief CDC write,data transfer from device to host + * @param[in] dev : a point which contains all the global variables which using in this function + * wbuf : buffer of write + * length : byte length of write + * @return None +************************************************************************************************************/ +uint32_t CDC_Write(USBCDC_Dev *dev, uint8_t *wbuf, uint32_t length) +{ + dev->cdc_device_write(dev->cdc_device, wbuf, length); + return length; +} diff --git a/CoX/middleware/USB_CLASS/USB_CDC/cdc_callback.h b/CoX/middleware/USB_CLASS/USB_CDC/cdc_callback.h new file mode 100644 index 00000000..c5351d80 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_CDC/cdc_callback.h @@ -0,0 +1,79 @@ +/***************************************************************************** + * U S B - C D C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : CDC_CALLBACK.h + * @brief : USB Communication Device Class Call Back module Definitions + * @version : 1.1 + * @date : 10. MAR. 2010 + * @author : CooCox + ****************************************************************************/ + +#ifndef __CDC_CALLBACK_H__ +#define __CDC_CALLBACK_H__ + +#include "usb_enumerate.h" + +/*********************************************************************** + * USB CDC call back function definition + **********************************************************************/ +typedef uint32_t (PFN_CDCD_Init_CALLBACK) (void *dev,void *para); +typedef uint32_t (PFN_CDCD_READ_CALLBACK) (void *dev, uint8_t *rbuf, uint32_t rlen); +typedef uint32_t (PFN_CDCD_WRITE_CALLBACK) (void *dev, uint8_t *wbuf, uint32_t wlen); +typedef uint32_t (PFN_CDCD_DeInit_CALLBACK)(void *dev); + +/** + * @brief CDC output buffer + */ +typedef struct __CDC_BUF_T +{ + uint8_t data[CDC_BUF_SIZE]; + unsigned int wrIdx; + unsigned int rdIdx; +} CDC_BUF_T; + +/** + * @brief USB CDC Structure + */ +typedef struct +{ + USB_ENU_Dev usb_enu; + CDC_LINE_CODING CDC_LineCoding; + CDC_BUF_T CDC_OutBuf; + CDC_BUF_T CDC_InBuf; + unsigned short CDC_DepInEmpty; + unsigned char BulkBufIn[USB_CDC_BUFSIZE]; + unsigned char BulkBufOut[USB_CDC_BUFSIZE]; + unsigned short CDC_SerialState; + unsigned char NotificationBuf [10]; + + PFN_CDCD_Init_CALLBACK *cdc_device_init; + PFN_CDCD_READ_CALLBACK *cdc_device_read; + PFN_CDCD_WRITE_CALLBACK *cdc_device_write; + PFN_CDCD_DeInit_CALLBACK *cdc_device_deinit; + void *cdc_device; + void *cdc_para; +} USBCDC_Dev; + +/********************************************************************** + * CDC buffer handling + **********************************************************************/ +extern int CDC_RdOutBuf (CDC_BUF_T *buf,char *buffer, const int *length); +extern int CDC_WrOutBuf (CDC_BUF_T *buf,const char *buffer, int *length); +extern int CDC_OutBufAvailChar (CDC_BUF_T *buf,int *availChar); + + +/*********************************************************************** + * extern API of this component + **********************************************************************/ +extern void CDC_Open(USBCDC_Dev *dev, USBCDC_Dev *user_config); +extern void CDC_Connect(USBCDC_Dev *dev,uint32_t con); +extern uint8_t CDC_Configurated(USBCDC_Dev *dev); +extern void CDC_Event(USBCDC_Dev *dev); +extern uint32_t CDC_Read(USBCDC_Dev *dev, uint8_t *rbuf, uint32_t length); +extern uint32_t CDC_Write(USBCDC_Dev *dev, uint8_t *wbuf, uint32_t length); + + + +#endif /* __CDC_CALLBACK_H__ */ + diff --git a/CoX/middleware/USB_CLASS/USB_CDC/usb_cdc.h b/CoX/middleware/USB_CLASS/USB_CDC/usb_cdc.h new file mode 100644 index 00000000..65c52f46 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_CDC/usb_cdc.h @@ -0,0 +1,846 @@ +/***************************************************************************** + * U S B - C D C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : USB_CDC.h + * @brief : USB Communication Device Class Definitions + * @version : 1.0 + * @date : 10. MAR. 2011 + * @author : CooCox + ****************************************************************************/ + +#ifndef __USB_CDC_H +#define __USB_CDC_H + +/********************************************************************** + * Definitions based on CDC120.pdf (www.usb.org) + **********************************************************************/ + +/********************************************************************** + * Communication device class specification version 1.20 + **********************************************************************/ +#define CDC_V1_20 0x0120 /*!usb_enu.SetupPacket.wValue.WB.H) + { + case HID_REPORT_INPUT: + if(dev->GetInReport !=NULL) + { + dev->GetInReport(dev->hid_device,dev->InReport,3); + } + dev->usb_enu.EP0Buf[0] = dev->InReport[0]; + dev->usb_enu.EP0Buf[1] = dev->InReport[1]; + dev->usb_enu.EP0Buf[2] = dev->InReport[2]; + break; + case HID_REPORT_OUTPUT: + return (FALSE); /* Not Supported */ + case HID_REPORT_FEATURE: + /* EP0Buf[] = ...; */ + /* break; */ + return (FALSE); /* Not Supported */ + } + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief HID Set Report Request Callback,Called automatically on HID Set Report Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t HID_SetReport (USBHID_Dev *dev) +{ + + /* ReportID = SetupPacket.wValue.WB.L; */ + switch (dev->usb_enu.SetupPacket.wValue.WB.H) + { + case HID_REPORT_INPUT: + return (FALSE); /* Not Supported */ + case HID_REPORT_OUTPUT: + *dev->OutReport = dev->usb_enu.EP0Buf[0]; + if(dev->SetOutReport != NULL) + { + dev->SetOutReport(dev->hid_device,dev->OutReport,1); + } + break; + case HID_REPORT_FEATURE: + return (FALSE); /* Not Supported */ + } + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief HID Get Idle Request Callback,Called automatically on HID Get Idle Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t HID_GetIdle (USBHID_Dev *dev) +{ + + dev->usb_enu.EP0Buf[0] = dev->HID_IdleTime[dev->usb_enu.SetupPacket.wValue.WB.L]; + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief HID Set Idle Request Callback,Called automatically on HID Set Idle Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t HID_SetIdle (USBHID_Dev *dev) +{ + + dev->HID_IdleTime[dev->usb_enu.SetupPacket.wValue.WB.L] = dev->usb_enu.SetupPacket.wValue.WB.H; + + /* Idle Handling if needed */ + /* ... */ + + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief HID Get Protocol Request Callback,Called automatically on HID Get Protocol Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t HID_GetProtocol (USBHID_Dev *dev) +{ + + dev->usb_enu.EP0Buf[0] = dev->HID_Protocol; + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief HID Set Protocol Request Callback,Called automatically on HID Set Protocol Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +uint32_t HID_SetProtocol (USBHID_Dev *dev) +{ + + dev->HID_Protocol = dev->usb_enu.SetupPacket.wValue.WB.L; + + /* Protocol Handling if needed */ + /* ... */ + + return (TRUE); +} +/********************************************************************************************************//** + * @brief HID interrupt input + * @param[in] dev : a point which contains all the global variables which using in this function + * Event : event type of endpoint + * @return None +************************************************************************************************************/ +void HID_IntIn (USBHID_Dev *dev,uint32_t Event) +{ + if(dev->GetInReport !=NULL) + { + dev->GetInReport(dev->hid_device,dev->InReport, 3); + } + dev->usb_enu.usb->USB_WriteEP(HID_INPUT, dev->InReport, 3); +} + +/********************************************************************************************************//** + * @brief HID interrupt output + * @param[in] dev : a point which contains all the global variables which using in this function + * Event : event type of endpoint + * @return None +************************************************************************************************************/ +void HID_IntOut(USBHID_Dev *dev,uint32_t Event) +{ + uint32_t len; + len = dev->usb_enu.usb->USB_ReadEP(HID_OUTPUT,dev->OutReport); + if(dev->SetOutReport !=NULL) + { + dev->SetOutReport(dev->hid_device,dev->OutReport, len); + } +} + +/********************************************************************************************************//** + * @brief Initialization of the USB HID + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void HID_Init (USBHID_Dev *dev) +{ + dev->usb_enu.hid_data = dev; + dev->usb_enu.g_pfn_hid_get_idle = (PFN_HID_CALLBACK *)HID_GetIdle; + dev->usb_enu.g_pfn_hid_get_procotol = (PFN_HID_CALLBACK *)HID_GetProtocol; + dev->usb_enu.g_pfn_hid_get_report = (PFN_HID_CALLBACK *)HID_GetReport; + dev->usb_enu.g_pfn_hid_set_idle = (PFN_HID_CALLBACK *)HID_SetIdle; + dev->usb_enu.g_pfn_hid_set_procotol = (PFN_HID_CALLBACK *)HID_SetProtocol; + dev->usb_enu.g_pfn_hid_set_report = (PFN_HID_CALLBACK *)HID_SetReport; + + USB_Init(&dev->usb_enu); +} + +/********************************************************************************************************//** + * @brief Connect HID to the host + * @param[in] dev : a point which contains all the global variables which using in this function + * con : TRUE \FALSE + * @return None +************************************************************************************************************/ +void HID_Connect(USBHID_Dev *dev,uint32_t con) +{ + dev->usb_enu.usb->USB_Connect(con); +} + +/********************************************************************************************************//** + * @brief Get ADC Configuration statue + * @param[in] dev : a point which contains all the global variables which using in this function + * @return Configuration statue +************************************************************************************************************/ +uint8_t HID_Configurated(USBHID_Dev *dev) +{ + return dev->usb_enu.USB_Configuration; +} + +/********************************************************************************************************//** + * @brief HID read,data transfer from host to device + * @param[in] dev : a point which contains all the global variables which using in this function + * rbuf : buffer of read + * len : byte length of read + * @return None +************************************************************************************************************/ +uint32_t HID_Read (USBHID_Dev *dev, uint8_t *rbuf, uint32_t len) +{ + len=dev->usb_enu.usb->USB_ReadEP(HID_OUTPUT,dev->OutReport); + if(dev->SetOutReport !=NULL) + { + dev->SetOutReport(dev->hid_device,dev->OutReport,len); + } + return len; +} + +/********************************************************************************************************//** + * @brief HID write,data transfer from device to host + * @param[in] dev : a point which contains all the global variables which using in this function + * wbuf : buffer of write + * len : byte length of write + * @return None +************************************************************************************************************/ +uint32_t HID_Write (USBHID_Dev *dev, uint8_t *wbuf, uint32_t len) +{ + if(dev->GetInReport != NULL) + { + dev->GetInReport(dev->hid_device,dev->InReport,len); + } + dev->usb_enu.usb->USB_WriteEP(HID_INPUT, dev->InReport, len); + return len; +} + + +/********************************************************************************************************//** + * @brief HID event callback setup + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void HID_Event(USBHID_Dev *dev) +{ + dev->usb_enu.usb->USB_Event((HID_OUTPUT&0xf),(USB_Event_Handler)HID_IntOut,(void *)dev); + dev->usb_enu.usb->USB_Event((HID_INPUT &0xf),(USB_Event_Handler)HID_IntIn, (void *)dev); +} diff --git a/CoX/middleware/USB_CLASS/USB_HID/hid_callback.h b/CoX/middleware/USB_CLASS/USB_HID/hid_callback.h new file mode 100644 index 00000000..24a4f10e --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_HID/hid_callback.h @@ -0,0 +1,53 @@ +/***************************************************************************** + * U S B - H I D - C O M P O N E N T + ****************************************************************************/ +/** + * @file : hid_callback.h + * @brief : HID HID call back Definitions + * @version : 1.1 + * @date : 11. Mar. 2011 + * @author : CooCox + ****************************************************************************/ + +#ifndef __HID_CALLBACK_H__ +#define __HID_CALLBACK_H__ +#include "usb_enumerate.h" + +/********************************************************************************************************//** + * HID Number of Reports +************************************************************************************************************/ +#define HID_REPORT_NUM 1 + +/********************************************************************************************************//** + * HID call back function definition +************************************************************************************************************/ +typedef uint32_t (PFN_HID_REPORT_CALLBACK)(void *dev,uint8_t *report, uint32_t len); + +/** + * @brief USB HID Structure + */ +typedef struct +{ + USB_ENU_Dev usb_enu; + PFN_HID_REPORT_CALLBACK *GetInReport; + PFN_HID_REPORT_CALLBACK *SetOutReport; + void *hid_device; +// void *hid_para; + + uint8_t *InReport; + uint8_t *OutReport; + uint8_t HID_Protocol; + uint8_t HID_IdleTime[HID_REPORT_NUM]; +} USBHID_Dev; + +/********************************************************************************************************//** + * HID extern Functions +************************************************************************************************************/ +extern uint32_t HID_Read (USBHID_Dev *dev, uint8_t *rbuf, uint32_t len); +extern uint32_t HID_Write (USBHID_Dev *dev, uint8_t *wbuf, uint32_t len); +extern void HID_Init (USBHID_Dev *dev); +extern void HID_Connect(USBHID_Dev *dev,uint32_t con); +extern uint8_t HID_Configurated(USBHID_Dev *dev); +extern void HID_Event(USBHID_Dev *dev); + +#endif /* __HID_CALLBACK_H__ */ diff --git a/CoX/middleware/USB_CLASS/USB_HID/usb_hid.h b/CoX/middleware/USB_CLASS/USB_HID/usb_hid.h new file mode 100644 index 00000000..d1597c7f --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_HID/usb_hid.h @@ -0,0 +1,383 @@ +/***************************************************************************** + * U S B - H I D - C O M P O N E N T + ****************************************************************************/ +/** + * @file : usb_hid.h + * @brief : USB HID (Human Interface Device) Definitions + * @version : 1.1 + * @date : 11. Mar. 2011 + * @author : CooCox + ****************************************************************************/ + +#ifndef __USB_HID_H__ +#define __USB_HID_H__ + + +/********************************************************************************************************//** + * HID Subclass Codes +************************************************************************************************************/ +#define HID_SUBCLASS_NONE 0x00 /*!< NO HID SUBCLASS */ +#define HID_SUBCLASS_BOOT 0x01 + + +/********************************************************************************************************//** + * HID Protocol Codes +************************************************************************************************************/ +#define HID_PROTOCOL_NONE 0x00 +#define HID_PROTOCOL_KEYBOARD 0x01 +#define HID_PROTOCOL_MOUSE 0x02 + + +/********************************************************************************************************//** + * HID Descriptor Types +************************************************************************************************************/ +#define HID_HID_DESCRIPTOR_TYPE 0x21 /*!< Hid Description */ +#define HID_REPORT_DESCRIPTOR_TYPE 0x22 /*!< Report Description */ +#define HID_PHYSICAL_DESCRIPTOR_TYPE 0x23 /*!< Physical Description */ + + +/********************************************************************************************************//** + * HID Descriptor +************************************************************************************************************/ +typedef struct _HID_DESCRIPTOR { + uint8_t bLength; /*!< Length of Description */ + uint8_t bDescriptorType; /*!< Type of Description HID = 21H */ + uint16_t bcdHID; /*!< Version of HID */ + uint8_t bCountryCode; /*!< Country Code */ + uint8_t bNumDescriptors; /*!< Number of support's other Description */ + /* Array of one or more descriptors */ + struct _HID_DESCRIPTOR_LIST { + uint8_t bDescriptorType; /*!< Type of attached's Description */ + uint16_t wDescriptorLength; /*!< Length of all of Description */ + } __attribute__ ((packed)) DescriptorList[1]; +} __attribute__ ((packed)) HID_DESCRIPTOR; + + +/********************************************************************************************************//** + * HID Request Codes +************************************************************************************************************/ +#define HID_REQUEST_GET_REPORT 0x01 /*!< Request of Get Report */ +#define HID_REQUEST_GET_IDLE 0x02 /*!< Request of Get Idle speed */ +#define HID_REQUEST_GET_PROTOCOL 0x03 /*!< Request of Get Hid Protocol */ +#define HID_REQUEST_SET_REPORT 0x09 /*!< Request of Set Report */ +#define HID_REQUEST_SET_IDLE 0x0A /*!< Request of Set Idle speed */ +#define HID_REQUEST_SET_PROTOCOL 0x0B /*!< Request of Set Hid Protocol */ + + +/********************************************************************************************************//** + * HID Report Types +************************************************************************************************************/ +#define HID_REPORT_INPUT 0x01 /*!< Report of Hid Input */ +#define HID_REPORT_OUTPUT 0x02 /*!< Report of Hid Output */ +#define HID_REPORT_FEATURE 0x03 /*!< Report of Hid Feature */ + + +/********************************************************************************************************//** + * Usage Pages +************************************************************************************************************/ +#define HID_USAGE_PAGE_UNDEFINED 0x00 +#define HID_USAGE_PAGE_GENERIC 0x01 +#define HID_USAGE_PAGE_SIMULATION 0x02 +#define HID_USAGE_PAGE_VR 0x03 +#define HID_USAGE_PAGE_SPORT 0x04 +#define HID_USAGE_PAGE_GAME 0x05 +#define HID_USAGE_PAGE_DEV_CONTROLS 0x06 +#define HID_USAGE_PAGE_KEYBOARD 0x07 +#define HID_USAGE_PAGE_LED 0x08 +#define HID_USAGE_PAGE_BUTTON 0x09 +#define HID_USAGE_PAGE_ORDINAL 0x0A +#define HID_USAGE_PAGE_TELEPHONY 0x0B +#define HID_USAGE_PAGE_CONSUMER 0x0C +#define HID_USAGE_PAGE_DIGITIZER 0x0D +#define HID_USAGE_PAGE_UNICODE 0x10 +#define HID_USAGE_PAGE_ALPHANUMERIC 0x14 + + + + +/********************************************************************************************************//** + * Generic Desktop Page (0x01) +************************************************************************************************************/ +#define HID_USAGE_GENERIC_POINTER 0x01 +#define HID_USAGE_GENERIC_MOUSE 0x02 +#define HID_USAGE_GENERIC_JOYSTICK 0x04 +#define HID_USAGE_GENERIC_GAMEPAD 0x05 +#define HID_USAGE_GENERIC_KEYBOARD 0x06 +#define HID_USAGE_GENERIC_KEYPAD 0x07 +#define HID_USAGE_GENERIC_X 0x30 +#define HID_USAGE_GENERIC_Y 0x31 +#define HID_USAGE_GENERIC_Z 0x32 +#define HID_USAGE_GENERIC_RX 0x33 +#define HID_USAGE_GENERIC_RY 0x34 +#define HID_USAGE_GENERIC_RZ 0x35 +#define HID_USAGE_GENERIC_SLIDER 0x36 +#define HID_USAGE_GENERIC_DIAL 0x37 +#define HID_USAGE_GENERIC_WHEEL 0x38 +#define HID_USAGE_GENERIC_HATSWITCH 0x39 +#define HID_USAGE_GENERIC_COUNTED_BUFFER 0x3A +#define HID_USAGE_GENERIC_BYTE_COUNT 0x3B +#define HID_USAGE_GENERIC_MOTION_WAKEUP 0x3C +#define HID_USAGE_GENERIC_VX 0x40 +#define HID_USAGE_GENERIC_VY 0x41 +#define HID_USAGE_GENERIC_VZ 0x42 +#define HID_USAGE_GENERIC_VBRX 0x43 +#define HID_USAGE_GENERIC_VBRY 0x44 +#define HID_USAGE_GENERIC_VBRZ 0x45 +#define HID_USAGE_GENERIC_VNO 0x46 +#define HID_USAGE_GENERIC_SYSTEM_CTL 0x80 +#define HID_USAGE_GENERIC_SYSCTL_POWER 0x81 +#define HID_USAGE_GENERIC_SYSCTL_SLEEP 0x82 +#define HID_USAGE_GENERIC_SYSCTL_WAKE 0x83 +#define HID_USAGE_GENERIC_SYSCTL_CONTEXT_MENU 0x84 +#define HID_USAGE_GENERIC_SYSCTL_MAIN_MENU 0x85 +#define HID_USAGE_GENERIC_SYSCTL_APP_MENU 0x86 +#define HID_USAGE_GENERIC_SYSCTL_HELP_MENU 0x87 +#define HID_USAGE_GENERIC_SYSCTL_MENU_EXIT 0x88 +#define HID_USAGE_GENERIC_SYSCTL_MENU_SELECT 0x89 +#define HID_USAGE_GENERIC_SYSCTL_MENU_RIGHT 0x8A +#define HID_USAGE_GENERIC_SYSCTL_MENU_LEFT 0x8B +#define HID_USAGE_GENERIC_SYSCTL_MENU_UP 0x8C +#define HID_USAGE_GENERIC_SYSCTL_MENU_DOWN 0x8D + + + +/********************************************************************************************************//** + * Simulation Controls Page (0x02) +************************************************************************************************************/ +#define HID_USAGE_SIMULATION_RUDDER 0xBA +#define HID_USAGE_SIMULATION_THROTTLE 0xBB + + +/********************************************************************************************************//** + * Error "keys +************************************************************************************************************/ +#define HID_USAGE_KEYBOARD_NOEVENT 0x00 +#define HID_USAGE_KEYBOARD_ROLLOVER 0x01 +#define HID_USAGE_KEYBOARD_POSTFAIL 0x02 +#define HID_USAGE_KEYBOARD_UNDEFINED 0x03 + + +/********************************************************************************************************//** + * Letters +************************************************************************************************************/ +#define HID_USAGE_KEYBOARD_aA 0x04 +#define HID_USAGE_KEYBOARD_zZ 0x1D + + +/********************************************************************************************************//** + * Numbers +************************************************************************************************************/ +#define HID_USAGE_KEYBOARD_ONE 0x1E +#define HID_USAGE_KEYBOARD_ZERO 0x27 + +#define HID_USAGE_KEYBOARD_RETURN 0x28 +#define HID_USAGE_KEYBOARD_ESCAPE 0x29 +#define HID_USAGE_KEYBOARD_DELETE 0x2A + + +/********************************************************************************************************//** + * Funtion keys +************************************************************************************************************/ +#define HID_USAGE_KEYBOARD_F1 0x3A +#define HID_USAGE_KEYBOARD_F12 0x45 + +#define HID_USAGE_KEYBOARD_PRINT_SCREEN 0x46 + + +/********************************************************************************************************//** + * Modifier Keys +************************************************************************************************************/ +#define HID_USAGE_KEYBOARD_LCTRL 0xE0 +#define HID_USAGE_KEYBOARD_LSHFT 0xE1 +#define HID_USAGE_KEYBOARD_LALT 0xE2 +#define HID_USAGE_KEYBOARD_LGUI 0xE3 +#define HID_USAGE_KEYBOARD_RCTRL 0xE4 +#define HID_USAGE_KEYBOARD_RSHFT 0xE5 +#define HID_USAGE_KEYBOARD_RALT 0xE6 +#define HID_USAGE_KEYBOARD_RGUI 0xE7 +#define HID_USAGE_KEYBOARD_SCROLL_LOCK 0x47 +#define HID_USAGE_KEYBOARD_NUM_LOCK 0x53 +#define HID_USAGE_KEYBOARD_CAPS_LOCK 0x39 + + + +/********************************************************************************************************//** + * LED Page (0x08) +************************************************************************************************************/ +#define HID_USAGE_LED_NUM_LOCK 0x01 +#define HID_USAGE_LED_CAPS_LOCK 0x02 +#define HID_USAGE_LED_SCROLL_LOCK 0x03 +#define HID_USAGE_LED_COMPOSE 0x04 +#define HID_USAGE_LED_KANA 0x05 +#define HID_USAGE_LED_POWER 0x06 +#define HID_USAGE_LED_SHIFT 0x07 +#define HID_USAGE_LED_DO_NOT_DISTURB 0x08 +#define HID_USAGE_LED_MUTE 0x09 +#define HID_USAGE_LED_TONE_ENABLE 0x0A +#define HID_USAGE_LED_HIGH_CUT_FILTER 0x0B +#define HID_USAGE_LED_LOW_CUT_FILTER 0x0C +#define HID_USAGE_LED_EQUALIZER_ENABLE 0x0D +#define HID_USAGE_LED_SOUND_FIELD_ON 0x0E +#define HID_USAGE_LED_SURROUND_FIELD_ON 0x0F +#define HID_USAGE_LED_REPEAT 0x10 +#define HID_USAGE_LED_STEREO 0x11 +#define HID_USAGE_LED_SAMPLING_RATE_DETECT 0x12 +#define HID_USAGE_LED_SPINNING 0x13 +#define HID_USAGE_LED_CAV 0x14 +#define HID_USAGE_LED_CLV 0x15 +#define HID_USAGE_LED_RECORDING_FORMAT_DET 0x16 +#define HID_USAGE_LED_OFF_HOOK 0x17 +#define HID_USAGE_LED_RING 0x18 +#define HID_USAGE_LED_MESSAGE_WAITING 0x19 +#define HID_USAGE_LED_DATA_MODE 0x1A +#define HID_USAGE_LED_BATTERY_OPERATION 0x1B +#define HID_USAGE_LED_BATTERY_OK 0x1C +#define HID_USAGE_LED_BATTERY_LOW 0x1D +#define HID_USAGE_LED_SPEAKER 0x1E +#define HID_USAGE_LED_HEAD_SET 0x1F +#define HID_USAGE_LED_HOLD 0x20 +#define HID_USAGE_LED_MICROPHONE 0x21 +#define HID_USAGE_LED_COVERAGE 0x22 +#define HID_USAGE_LED_NIGHT_MODE 0x23 +#define HID_USAGE_LED_SEND_CALLS 0x24 +#define HID_USAGE_LED_CALL_PICKUP 0x25 +#define HID_USAGE_LED_CONFERENCE 0x26 +#define HID_USAGE_LED_STAND_BY 0x27 +#define HID_USAGE_LED_CAMERA_ON 0x28 +#define HID_USAGE_LED_CAMERA_OFF 0x29 +#define HID_USAGE_LED_ON_LINE 0x2A +#define HID_USAGE_LED_OFF_LINE 0x2B +#define HID_USAGE_LED_BUSY 0x2C +#define HID_USAGE_LED_READY 0x2D +#define HID_USAGE_LED_PAPER_OUT 0x2E +#define HID_USAGE_LED_PAPER_JAM 0x2F +#define HID_USAGE_LED_REMOTE 0x30 +#define HID_USAGE_LED_FORWARD 0x31 +#define HID_USAGE_LED_REVERSE 0x32 +#define HID_USAGE_LED_STOP 0x33 +#define HID_USAGE_LED_REWIND 0x34 +#define HID_USAGE_LED_FAST_FORWARD 0x35 +#define HID_USAGE_LED_PLAY 0x36 +#define HID_USAGE_LED_PAUSE 0x37 +#define HID_USAGE_LED_RECORD 0x38 +#define HID_USAGE_LED_ERROR 0x39 +#define HID_USAGE_LED_SELECTED_INDICATOR 0x3A +#define HID_USAGE_LED_IN_USE_INDICATOR 0x3B +#define HID_USAGE_LED_MULTI_MODE_INDICATOR 0x3C +#define HID_USAGE_LED_INDICATOR_ON 0x3D +#define HID_USAGE_LED_INDICATOR_FLASH 0x3E +#define HID_USAGE_LED_INDICATOR_SLOW_BLINK 0x3F +#define HID_USAGE_LED_INDICATOR_FAST_BLINK 0x40 +#define HID_USAGE_LED_INDICATOR_OFF 0x41 +#define HID_USAGE_LED_FLASH_ON_TIME 0x42 +#define HID_USAGE_LED_SLOW_BLINK_ON_TIME 0x43 +#define HID_USAGE_LED_SLOW_BLINK_OFF_TIME 0x44 +#define HID_USAGE_LED_FAST_BLINK_ON_TIME 0x45 +#define HID_USAGE_LED_FAST_BLINK_OFF_TIME 0x46 +#define HID_USAGE_LED_INDICATOR_COLOR 0x47 +#define HID_USAGE_LED_RED 0x48 +#define HID_USAGE_LED_GREEN 0x49 +#define HID_USAGE_LED_AMBER 0x4A +#define HID_USAGE_LED_GENERIC_INDICATOR 0x4B + + +/********************************************************************************************************//** + * Telephony Device Page (0x0B) +************************************************************************************************************/ +#define HID_USAGE_TELEPHONY_PHONE 0x01 +#define HID_USAGE_TELEPHONY_ANSWERING_MACHINE 0x02 +#define HID_USAGE_TELEPHONY_MESSAGE_CONTROLS 0x03 +#define HID_USAGE_TELEPHONY_HANDSET 0x04 +#define HID_USAGE_TELEPHONY_HEADSET 0x05 +#define HID_USAGE_TELEPHONY_KEYPAD 0x06 +#define HID_USAGE_TELEPHONY_PROGRAMMABLE_BUTTON 0x07 + + + +/********************************************************************************************************//** + * Consumer Page (0x0C) +************************************************************************************************************/ +#define HID_USAGE_CONSUMER_CONTROL 0x01 + + +/********************************************************************************************************//** + * Main Items +************************************************************************************************************/ +#define HID_Input(x) 0x81,x +#define HID_Output(x) 0x91,x +#define HID_Feature(x) 0xB1,x +#define HID_Collection(x) 0xA1,x +#define HID_EndCollection 0xC0 + + +/********************************************************************************************************//** + * Data (Input, Output, Feature) +************************************************************************************************************/ +#define HID_Data 0<<0 +#define HID_Constant 1<<0 +#define HID_Array 0<<1 +#define HID_Variable 1<<1 +#define HID_Absolute 0<<2 +#define HID_Relative 1<<2 +#define HID_NoWrap 0<<3 +#define HID_Wrap 1<<3 +#define HID_Linear 0<<4 +#define HID_NonLinear 1<<4 +#define HID_PreferredState 0<<5 +#define HID_NoPreferred 1<<5 +#define HID_NoNullPosition 0<<6 +#define HID_NullState 1<<6 +#define HID_NonVolatile 0<<7 +#define HID_Volatile 1<<7 + + +/********************************************************************************************************//** + * Collection Data +************************************************************************************************************/ +#define HID_Physical 0x00 +#define HID_Application 0x01 +#define HID_Logical 0x02 +#define HID_Report 0x03 +#define HID_NamedArray 0x04 +#define HID_UsageSwitch 0x05 +#define HID_UsageModifier 0x06 + + +/********************************************************************************************************//** + * Global Items +************************************************************************************************************/ +#define HID_UsagePage(x) 0x05,x +#define HID_UsagePageVendor(x) 0x06,x,0xFF +#define HID_LogicalMin(x) 0x15,x +#define HID_LogicalMinS(x) 0x16,(x&0xFF),((x>>8)&0xFF) +#define HID_LogicalMinL(x) 0x17,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_LogicalMax(x) 0x25,x +#define HID_LogicalMaxS(x) 0x26,(x&0xFF),((x>>8)&0xFF) +#define HID_LogicalMaxL(x) 0x27,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_PhysicalMin(x) 0x35,x +#define HID_PhysicalMinS(x) 0x36,(x&0xFF),((x>>8)&0xFF) +#define HID_PhysicalMinL(x) 0x37,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_PhysicalMax(x) 0x45,x +#define HID_PhysicalMaxS(x) 0x46,(x&0xFF),((x>>8)&0xFF) +#define HID_PhysicalMaxL(x) 0x47,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_UnitExponent(x) 0x55,x +#define HID_Unit(x) 0x65,x +#define HID_UnitS(x) 0x66,(x&0xFF),((x>>8)&0xFF) +#define HID_UnitL(x) 0x67,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF) +#define HID_ReportSize(x) 0x75,x +#define HID_ReportID(x) 0x85,x +#define HID_ReportCount(x) 0x95,x +#define HID_Push 0xA0 +#define HID_Pop 0xB0 + + + +/********************************************************************************************************//** + * Local Items +************************************************************************************************************/ +#define HID_Usage(x) 0x09,x +#define HID_UsageMin(x) 0x19,x +#define HID_UsageMax(x) 0x29,x + + +#endif diff --git a/CoX/middleware/USB_CLASS/USB_HID/usb_hid_config.h b/CoX/middleware/USB_CLASS/USB_HID/usb_hid_config.h new file mode 100644 index 00000000..b7920d49 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_HID/usb_hid_config.h @@ -0,0 +1,31 @@ +/***************************************************************************** + * U S B - H I D - C O M P O N E N T + ****************************************************************************/ +/** + * @file : usb_hid_config.h + * @brief : USB hid Configuration + * @version : 1.1 + * @date : 11. Mar. 2011 + * @author : CooCox + ****************************************************************************/ + + +#ifndef __USB_HID_CONFIG_H__ +#define __USB_HID_CONFIG_H__ + +/********************************************************************** + * CDC vendor ID and product ID + **********************************************************************/ +#define USB_VENDOR_ID 0x1234 // Vendor ID +#define USB_PROD_ID 0x0003 // Product ID +#define USB_DEVICE 0x0100 // Device ID +#define HID_FUNCTION HID_PROTOCOL_MOUSE /*!< hid function <0-2> */ + + +/********************************************************************** + * CDC Communication In\Out Endpoint Address + **********************************************************************/ +#define HID_INPUT 0x81 +#define HID_OUTPUT 0x02 + +#endif /* __USB_MSC_CONFIG_H__ */ diff --git a/CoX/middleware/USB_CLASS/USB_MSC/msc_callback.c b/CoX/middleware/USB_CLASS/USB_MSC/msc_callback.c new file mode 100644 index 00000000..22508292 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_MSC/msc_callback.c @@ -0,0 +1,776 @@ + +#include "msc_callback.h" +#include + + +void MSC_SetCSW(USBMSC_Dev *dev); +void MSC_SetStallEP(USBMSC_Dev *dev,uint32_t EPNum); +void MSC_Event(USBMSC_Dev *dev); + +/********************************************************************************************************//** + * @brief USB MSC data in format + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +uint32_t DataInFormat (USBMSC_Dev *dev) +{ + + if (dev->CBW.dDataLength == 0) + { + dev->CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(dev); + return (FALSE); + } + if ((dev->CBW.bmFlags & 0x80) == 0) + { + MSC_SetStallEP(dev,MSC_EP_OUT); + dev->CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(dev); + return (FALSE); + } + return (TRUE); +} + +/********************************************************************************************************//** + * @brief USB MSC data in transfer + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void DataInTransfer (USBMSC_Dev *dev) +{ + + if (dev->BulkLen >= dev->CBW.dDataLength) + { + dev->BulkLen = dev->CBW.dDataLength; + dev->BulkStage = MSC_BS_DATA_IN_LAST; + } + else + { + dev->BulkStage = MSC_BS_DATA_IN_LAST_STALL; /* short or zero packet */ + } + + xUSBEndpointWrite(MSC_EP_IN, dev->BulkBuf, dev->BulkLen); + + dev->CSW.dDataResidue -= dev->BulkLen; + dev->CSW.bStatus = CSW_CMD_PASSED; +} + +/********************************************************************************************************//** + * @brief USB MSC read write setup + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +uint32_t MSC_RWSetup (USBMSC_Dev *dev) +{ + uint32_t n; + + /* Logical Block Address of First Block */ + n = (dev->CBW.CB[2] << 24) | + (dev->CBW.CB[3] << 16) | + (dev->CBW.CB[4] << 8) | + (dev->CBW.CB[5] << 0); + + dev->Offset = n * MSC_BlockSize; + + /* Number of Blocks to transfer */ + switch (dev->CBW.CB[0]) + { + case SCSI_READ10: + case SCSI_WRITE10: + case SCSI_VERIFY10: + n = (dev->CBW.CB[7] << 8) | + (dev->CBW.CB[8] << 0); + break; + + case SCSI_READ12: + case SCSI_WRITE12: + n = (dev->CBW.CB[6] << 24) | + (dev->CBW.CB[7] << 16) | + (dev->CBW.CB[8] << 8) | + (dev->CBW.CB[9] << 0); + break; + } + + dev->Length = n * MSC_BlockSize; + + if (dev->CBW.dDataLength == 0) + { + /* host requests no data */ + dev->CSW.bStatus = CSW_CMD_FAILED; + MSC_SetCSW(dev); + return (FALSE); + } + + if (dev->CBW.dDataLength != dev->Length) + { + if ((dev->CBW.bmFlags & 0x80) != 0) + { + /* stall appropriate EP */ + MSC_SetStallEP(dev,MSC_EP_IN); + } + else + { + MSC_SetStallEP(dev,MSC_EP_IN); + } + + dev->CSW.bStatus = CSW_CMD_FAILED; + MSC_SetCSW(dev); + + return (FALSE); + } + + return (TRUE); +} + +/********************************************************************************************************//** + * @brief USB MSC get CSW + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_SetCSW(USBMSC_Dev *dev) +{ + dev->CSW.dSignature = MSC_CSW_Signature; + xUSBEndpointWrite(MSC_EP_IN, (uint8_t *)&dev->CSW, sizeof(dev->CSW)); + dev->BulkStage = MSC_BS_CSW; +} + +/********************************************************************************************************//** + * @brief Initialization of USB MSC memory + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_InitFlash(USBMSC_Dev *dev) +{ + dev->flash_init(dev->flash_data); +} + +/********************************************************************************************************//** + * @brief USB MSC read memory + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_MemoryRead(USBMSC_Dev *dev) +{ + uint32_t n; + + if (dev->Length > MSC_MAX_PACKET) + { + n = MSC_MAX_PACKET; + } + else + { + n = dev->Length; + } + + if ((dev->Offset + n) > MSC_MemorySize) + { + n = MSC_MemorySize - dev->Offset; + dev->BulkStage = MSC_BS_DATA_IN_LAST_STALL; + } + if(dev->flash_read != NULL) + { + dev->flash_read(dev->flash_data, dev->Offset, dev->BulkBuf, n); + } + xUSBEndpointWrite(MSC_EP_IN, dev->BulkBuf, n); + dev->Offset += n; + dev->Length -= n; + + dev->CSW.dDataResidue -= n; + + if (dev->Length == 0) + { + dev->BulkStage = MSC_BS_DATA_IN_LAST; + } + + if (dev->BulkStage != MSC_BS_DATA_IN) + { + dev->CSW.bStatus = CSW_CMD_PASSED; + } +} + +/********************************************************************************************************//** + * @brief USB MSC write memory + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_MemoryWrite(USBMSC_Dev *dev) +{ + if ((dev->Offset + dev->BulkLen) > MSC_MemorySize) + { + dev->BulkLen = MSC_MemorySize - dev->Offset; + dev->BulkStage = MSC_BS_CSW; + MSC_SetStallEP(dev,MSC_EP_OUT); + } + if(dev->flash_write != NULL) + { + dev->flash_write(dev->flash_data, dev->Offset, dev->BulkBuf, dev->BulkLen); + } + dev->Offset += dev->BulkLen; + dev->Length -= dev->BulkLen; + dev->CSW.dDataResidue -= dev->BulkLen; + if ((dev->Length == 0) || (dev->BulkStage == MSC_BS_CSW)) + { + dev->CSW.bStatus = CSW_CMD_PASSED; + MSC_SetCSW(dev); + + } + +} +/********************************************************************************************************//** + * @brief USB MSC verify memory + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_MemoryVerify(USBMSC_Dev *dev) +{ + uint32_t n,MemOK; + + if ((dev->Offset + dev->BulkLen) > MSC_MemorySize) + { + dev->BulkLen = MSC_MemorySize - dev->Offset; + dev->BulkStage = MSC_BS_CSW; + MSC_SetStallEP(dev, MSC_EP_OUT); + } + if(dev->flash_read != NULL) + { + dev->flash_read(dev->flash_data, dev->Offset, dev->BulkBuf, dev->BulkLen); + } + for (n = 0; n < dev->BulkLen; n++) + { + if (dev->Memory[n] != dev->BulkBuf[n]) + { + MemOK = FALSE; + break; + } + } + + dev->Offset += dev->BulkLen; + dev->Length -= dev->BulkLen; + + dev->CSW.dDataResidue -= dev->BulkLen; + + if ((dev->Length == 0) || (dev->BulkStage == MSC_BS_CSW)) + { + dev->CSW.bStatus = (MemOK) ? CSW_CMD_PASSED : CSW_CMD_FAILED; + MSC_SetCSW(dev); + } +} + +/********************************************************************************************************//** + * @brief USB MSC set stall end point + * @param[in] dev : a point which contains all the global variables which using in this function + * EPNum : logic number of end point + * @return None +************************************************************************************************************/ +void MSC_SetStallEP(USBMSC_Dev *dev,uint32_t EPNum) +{ + + dev->usb_enu.USB_EndPointHalt |= (EPNum & 0x80) ? ((1 << 16) << (EPNum & 0x0F)) : (1 << EPNum); +} + +/********************************************************************************************************//** + * @brief USB MSC test unit ready + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_TestUnitReady(USBMSC_Dev *dev) +{ + if (dev->CBW.dDataLength != 0) + { + if ((dev->CBW.bmFlags & 0x80) != 0) + { + MSC_SetStallEP(dev,MSC_EP_IN); + } + else + { + MSC_SetStallEP(dev,MSC_EP_OUT); + } + } + + dev->CSW.bStatus = CSW_CMD_PASSED; + MSC_SetCSW(dev); +} + +/********************************************************************************************************//** + * @brief USB MSC request sense + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_RequestSense(USBMSC_Dev *dev) +{ + if (!DataInFormat(dev)) return; + + dev->BulkBuf[ 0] = 0x70; /* Response Code */ + dev->BulkBuf[ 1] = 0x00; + dev->BulkBuf[ 2] = 0x00;//0x02; /* Sense Key *///DIFF + dev->BulkBuf[ 3] = 0x00; + dev->BulkBuf[ 4] = 0x00; + dev->BulkBuf[ 5] = 0x00; + dev->BulkBuf[ 6] = 0x00; + dev->BulkBuf[ 7] = 0x0A; /* Additional Length */ + dev->BulkBuf[ 8] = 0x00; + dev->BulkBuf[ 9] = 0x00; + dev->BulkBuf[10] = 0x00; + dev->BulkBuf[11] = 0x00; + dev->BulkBuf[12] = 0x00;//0x30; /* ASC *///diff + dev->BulkBuf[13] = 0x00;//0x01; /* ASCQ *///diff + dev->BulkBuf[14] = 0x00; + dev->BulkBuf[15] = 0x00; + dev->BulkBuf[16] = 0x00; + dev->BulkBuf[17] = 0x00; + + dev->BulkLen = 18; + DataInTransfer(dev); +} + +/********************************************************************************************************//** + * @brief USB MSC inquiry + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_Inquiry(USBMSC_Dev *dev) +{ + if (!DataInFormat(dev)) return; + + dev->BulkBuf[ 0] = 0x00; /* Direct Access Device */ + dev->BulkBuf[ 1] = 0x80; /* RMB = 1: Removable Medium */ + dev->BulkBuf[ 2] = 0x00; /* Version: No conformance claim to standard */ + dev->BulkBuf[ 3] = 0x01; + + dev->BulkBuf[ 4] = 36-4; /* Additional Length */ + dev->BulkBuf[ 5] = 0x80; /* SCCS = 1: Storage Controller Component */ + dev->BulkBuf[ 6] = 0x00; + dev->BulkBuf[ 7] = 0x00; + + dev->BulkBuf[ 8] = 'N'; /* Vendor Identification */ + dev->BulkBuf[ 9] = 'O'; + dev->BulkBuf[10] = 'V'; + dev->BulkBuf[11] = 'O'; + dev->BulkBuf[12] = 'T'; + dev->BulkBuf[13] = 'O'; + dev->BulkBuf[14] = 'N'; + dev->BulkBuf[15] = ' '; + + dev->BulkBuf[16] = 'N'; /* Product Identification */ + dev->BulkBuf[17] = 'U'; + dev->BulkBuf[18] = 'C'; + dev->BulkBuf[19] = '1'; + dev->BulkBuf[20] = '4'; + dev->BulkBuf[21] = 'X'; + dev->BulkBuf[22] = 'x'; + dev->BulkBuf[23] = ' '; + dev->BulkBuf[24] = 'D'; + dev->BulkBuf[25] = 'i'; + dev->BulkBuf[26] = 's'; + dev->BulkBuf[27] = 'k'; + dev->BulkBuf[28] = ' '; + dev->BulkBuf[29] = ' '; + dev->BulkBuf[30] = ' '; + dev->BulkBuf[31] = ' '; + + dev->BulkBuf[32] = '1'; /* Product Revision Level */ + dev->BulkBuf[33] = '.'; + dev->BulkBuf[34] = '0'; + dev->BulkBuf[35] = ' '; + + dev->BulkLen = 36; + DataInTransfer(dev); +} + +/********************************************************************************************************//** + * @brief USB MSC mode sense 6 + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_ModeSense6(USBMSC_Dev *dev) +{ + if (!DataInFormat(dev)) return; + + dev->BulkBuf[ 0] = 0x03; + dev->BulkBuf[ 1] = 0x00; + dev->BulkBuf[ 2] = 0x00; + dev->BulkBuf[ 3] = 0x00; + + dev->BulkLen = 4; + DataInTransfer(dev); +} + +/********************************************************************************************************//** + * @brief USB MSC mode sense 10 + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_ModeSense10(USBMSC_Dev *dev) +{ + + if (!DataInFormat(dev)) return; + + dev->BulkBuf[ 0] = 0x00; + dev->BulkBuf[ 1] = 0x06; + dev->BulkBuf[ 2] = 0x00; + dev->BulkBuf[ 3] = 0x00; + dev->BulkBuf[ 4] = 0x00; + dev->BulkBuf[ 5] = 0x00; + dev->BulkBuf[ 6] = 0x00; + dev->BulkBuf[ 7] = 0x00; + + dev->BulkLen = 8; + DataInTransfer(dev); +} + +/********************************************************************************************************//** + * @brief USB MSC read format capacity + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_ReadFormatCapacity(USBMSC_Dev *dev) +{ + if (!DataInFormat(dev)) return; + + dev->BulkBuf[ 0] = 0x00; + dev->BulkBuf[ 1] = 0x00; + dev->BulkBuf[ 2] = 0x00; + dev->BulkBuf[ 3] = 0x08; /* Capacity List Length */ + + /* Block Count */ + dev->BulkBuf[ 4] = (MSC_BlockCount >> 24) & 0xFF; + dev->BulkBuf[ 5] = (MSC_BlockCount >> 16) & 0xFF; + dev->BulkBuf[ 6] = (MSC_BlockCount >> 8) & 0xFF; + dev->BulkBuf[ 7] = (MSC_BlockCount >> 0) & 0xFF; + + /* Block Length */ + dev->BulkBuf[ 8] = 0x02; /* Descriptor Code: Formatted Media */ + dev->BulkBuf[ 9] = (MSC_BlockSize >> 16) & 0xFF; + dev->BulkBuf[10] = (MSC_BlockSize >> 8) & 0xFF; + dev->BulkBuf[11] = (MSC_BlockSize >> 0) & 0xFF; + + dev->BulkLen = 12; + DataInTransfer(dev); +} + +/********************************************************************************************************//** + * @brief USB MSC read capacity + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_ReadCapacity(USBMSC_Dev *dev) +{ + if (!DataInFormat(dev)) return; + + /* Last Logical Block */ + dev->BulkBuf[ 0] = ((MSC_BlockCount - 1) >> 24) & 0xFF; + dev->BulkBuf[ 1] = ((MSC_BlockCount - 1) >> 16) & 0xFF; + dev->BulkBuf[ 2] = ((MSC_BlockCount - 1) >> 8) & 0xFF; + dev->BulkBuf[ 3] = ((MSC_BlockCount - 1) >> 0) & 0xFF; + + /* Block Length */ + dev->BulkBuf[ 4] = (MSC_BlockSize >> 24) & 0xFF; + dev->BulkBuf[ 5] = (MSC_BlockSize >> 16) & 0xFF; + dev->BulkBuf[ 6] = (MSC_BlockSize >> 8) & 0xFF; + dev->BulkBuf[ 7] = (MSC_BlockSize >> 0) & 0xFF; + + dev->BulkLen = 8; + DataInTransfer(dev); +} + +/********************************************************************************************************//** + * @brief USB MSC get CBW + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_GetCBW(USBMSC_Dev *dev) +{ + + uint32_t n; + + for (n = 0; n < dev->BulkLen; n++) + { + *((uint8_t *)&dev->CBW + n) = dev->BulkBuf[n]; + } + if ((dev->BulkLen == sizeof(dev->CBW)) && (dev->CBW.dSignature == MSC_CBW_Signature)) + { + /* Valid CBW */ + dev->CSW.dTag = dev->CBW.dTag; + dev->CSW.dDataResidue = dev->CBW.dDataLength; + if ((dev->CBW.bLUN != 0) || + (dev->CBW.bCBLength < 1) || + (dev->CBW.bCBLength > 16) ) + { + fail: + dev->CSW.bStatus = CSW_CMD_FAILED; + MSC_SetCSW(dev); + } + else + { + switch (dev->CBW.CB[0]) + { + case SCSI_TEST_UNIT_READY://SCSI_TEST_UNIT_READY! + MSC_TestUnitReady(dev); + break; + case SCSI_REQUEST_SENSE://SCSI_REQUEST_SENSE! + MSC_RequestSense(dev); +// printf(" SCSI_REQUEST_SENSE!\n\r"); + break; + case SCSI_FORMAT_UNIT: + goto fail; + case SCSI_INQUIRY://SCSI_INQUIRY + MSC_Inquiry(dev); + break; + case SCSI_START_STOP_UNIT: + goto fail; + case SCSI_MEDIA_REMOVAL://SCSI_MEDIA_REMOVAL! +// printf(" SCSI_MEDIA_REMOVAL!\n\r"); + dev->CSW.bStatus = CSW_CMD_PASSED; + MSC_SetCSW(dev); + break;//goto fail; + case SCSI_MODE_SELECT6: + goto fail; + case SCSI_MODE_SENSE6://SCSI_MODE_SENSE6! + MSC_ModeSense6(dev); + break; + case SCSI_MODE_SELECT10: + goto fail; + case SCSI_MODE_SENSE10: + MSC_ModeSense10(dev); + break; + case SCSI_READ_FORMAT_CAPACITIES://READ_FORMAT_CAPACITIES! + MSC_ReadFormatCapacity(dev); + break; + case SCSI_READ_CAPACITY://SCSI_READ_CAPACITY! + MSC_ReadCapacity(dev); + break; + case SCSI_READ10://SCSI_READ10! + case SCSI_READ12: +// printf(" SCSI_READ10!\n\r"); + if(MSC_RWSetup(dev)) + { + if ((dev->CBW.bmFlags & 0x80) != 0) + { + dev->BulkStage = MSC_BS_DATA_IN; + MSC_MemoryRead(dev); + } + else + { + /* direction mismatch */ + MSC_SetStallEP(dev,MSC_EP_IN); + dev->CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(dev); + } + } + break; + case SCSI_WRITE10://SCSI_WRITE10! + case SCSI_WRITE12: +// printf(" SCSI_WRITE10!\n\r"); + if (MSC_RWSetup(dev)) + { + if ((dev->CBW.bmFlags & 0x80) == 0) + { + dev->BulkStage = MSC_BS_DATA_OUT; + if(dev->InitOffset!=NULL) + { + *dev->InitOffset = dev->Offset; + } + if(dev->TotalLength!=NULL) + { + *dev->TotalLength = dev->Length; + } + + } + else + { + /* direction mismatch */ + MSC_SetStallEP(dev,MSC_EP_IN); + dev->CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(dev); + } + } + break; + case SCSI_VERIFY10: + if ((dev->CBW.CB[1] & 0x02) == 0) + { + dev->CSW.bStatus = CSW_CMD_PASSED; + MSC_SetCSW(dev); + break; + } + if (MSC_RWSetup(dev)) + { + if ((dev->CBW.bmFlags & 0x80) == 0) + { + dev->BulkStage = MSC_BS_DATA_OUT; + } + else + { + MSC_SetStallEP(dev,MSC_EP_IN); + dev->CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(dev); + } + } + break; + default: + goto fail; + } + } + } + else + { + /* Invalid CBW */ + MSC_SetStallEP(dev,MSC_EP_IN); + /* set EP to stay stalled */ + dev->usb_enu.USB_EndPointStall |= (MSC_EP_IN & 0x80) ? ((1 << 16) << (MSC_EP_IN & 0x0F)) : (1 << MSC_EP_IN); + MSC_SetStallEP(dev,MSC_EP_IN); + /* set EP to stay stalled */ + dev->usb_enu.USB_EndPointStall |= (MSC_EP_OUT & 0x80) ? ((1 << 16) << (MSC_EP_OUT & 0x0F)) : (1 << MSC_EP_OUT); + dev->BulkStage = MSC_BS_ERROR; + } +} + +/********************************************************************************************************//** + * @brief USB MSC reset + * @param[in] dev : a point which contains all the global variables which using in this function + * Event: NULL + * @return None +************************************************************************************************************/ +uint32_t MSC_Reset(USBMSC_Dev *dev, uint32_t Event) +{ + dev->usb_enu.USB_EndPointHalt = 0x00000000; + dev->CSW.dSignature = 0; + dev->BulkStage = MSC_BS_CBW; + + return (TRUE); +} + +/********************************************************************************************************//** + * @brief USB MSC get max LUN + * @param[in] dev : a point which contains all the global variables which using in this function + * Event: NULL + * @return None +************************************************************************************************************/ +uint32_t MSC_GetMaxLUN(USBMSC_Dev *dev, uint32_t Event) +{ + dev->usb_enu.EP0Buf[0] = 0; /* No LUN associated with this device */ + MSC_Event(dev); + return (TRUE); +} + +/********************************************************************************************************//** + * @brief Initialization of the USB MSC + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_Open(USBMSC_Dev *dev) +{ + //dev->di_usb_e = &di_usb_enumerate; + dev->usb_enu.msc_data = dev; + dev->usb_enu.g_pfn_msc_request_reset = (PFN_MSC_CALLBACK *)MSC_Reset; + dev->usb_enu.g_pfn_msc_request_get_max_lun = (PFN_MSC_CALLBACK *)MSC_GetMaxLUN; + + if(dev->flash_init != NULL) + { + dev->flash_init(dev->flash_data); + } + USB_Init(&dev->usb_enu); +} + +/********************************************************************************************************//** + * @brief Connect MSC to the host + * @param[in] dev : a point which contains all the global variables which using in this function + * con : TRUE \FALSE + * @return None +************************************************************************************************************/ +void MSC_Connect(USBMSC_Dev *dev,uint32_t con) +{ + xUSBConnect(con); +} + +/********************************************************************************************************//** + * @brief Get MSC Configuration statue + * @param[in] dev : a point which contains all the global variables which using in this function + * @return Configuration statue +************************************************************************************************************/ +uint8_t MSC_Configurated(USBMSC_Dev *dev) +{ + return dev->usb_enu.USB_Configuration; +} + + +/********************************************************************************************************//** + * @brief MSC bulk in handle + * @param[in] dev : a point which contains all the global variables which using in this function + * event : event type of endpoint + * @return None +************************************************************************************************************/ +void bulk_in_handle(USBMSC_Dev *dev,uint32_t Event, + unsigned long ulMsgParam, + void *pvMsgData) +{ + switch (dev->BulkStage) + { + case MSC_BS_DATA_IN: + switch (dev->CBW.CB[0]) + { + case SCSI_READ10: + case SCSI_READ12: + MSC_MemoryRead(dev); + break; + } + break; + case MSC_BS_DATA_IN_LAST: + MSC_SetCSW(dev); + break; + case MSC_BS_DATA_IN_LAST_STALL: + MSC_SetStallEP(dev,MSC_EP_OUT); + MSC_SetCSW(dev); + break; + case MSC_BS_CSW: + dev->BulkStage = MSC_BS_CBW; + break; + } +} +/********************************************************************************************************//** + * @brief MSC bulk out handle + * @param[in] dev : a point which contains all the global variables which using in this function + * event : event type of endpoint + * @return None +************************************************************************************************************/ +void bulk_out_handle(USBMSC_Dev *dev,uint32_t Event, + unsigned long ulMsgParam, + void *pvMsgData) +{ + dev->BulkLen = xUSBEndpointRead(MSC_EP_OUT, dev->BulkBuf); + switch (dev->BulkStage) + { + case MSC_BS_CBW: + MSC_GetCBW(dev); + break; + case MSC_BS_DATA_OUT: + switch (dev->CBW.CB[0]) + { + case SCSI_WRITE10: + case SCSI_WRITE12: + MSC_MemoryWrite(dev); + break; + case SCSI_VERIFY10: + MSC_MemoryVerify(dev); + break; + } + break; + default: + MSC_SetStallEP(dev,MSC_EP_OUT); + dev->CSW.bStatus = CSW_PHASE_ERROR; + MSC_SetCSW(dev); + break; + } +} + +/********************************************************************************************************//** + * @brief MSC event callback setup + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void MSC_Event(USBMSC_Dev *dev) +{ + xUSBEventHandler((MSC_EP_OUT&0xf),(xtEventCallback)bulk_out_handle,(void *)dev); + xUSBEventHandler((MSC_EP_IN &0xf),(xtEventCallback)bulk_in_handle, (void *)dev); +} + + diff --git a/CoX/middleware/USB_CLASS/USB_MSC/msc_callback.h b/CoX/middleware/USB_CLASS/USB_MSC/msc_callback.h new file mode 100644 index 00000000..3601cfb5 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_MSC/msc_callback.h @@ -0,0 +1,58 @@ +/***************************************************************************** + * U S B - M S C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : msc_callback.h + * @brief : Mass Storage Class call back Definitions + * @version : 1.0 + * @date : 28. Dec. 2010 + * @author : CooCox + ****************************************************************************/ + +#ifndef __MSC_CALLBACK_H__ +#define __MSC_CALLBACK_H__ +#include "usb_enumerate.h" + +/*********************************************************************** + * USB MSC call back function definition + **********************************************************************/ +typedef uint32_t (PFN_FLASH_Init_CALLBACK) (void *dev); +typedef uint32_t (PFN_FLASH_READ_CALLBACK) (void *dev, uint32_t addr, uint8_t *rbuf, uint32_t rlen); +typedef uint32_t (PFN_FLASH_WRITE_CALLBACK)(void *dev, uint32_t addr, uint8_t *wbuf, uint32_t wlen); +typedef uint32_t (PFN_FLASH_ERASE_CALLBACK)(void *dev, uint32_t addr); + + +/** + * @brief USB MSC Structure + */ +typedef struct +{ + USB_ENU_Dev usb_enu; + + PFN_FLASH_Init_CALLBACK *flash_init; + PFN_FLASH_READ_CALLBACK *flash_read; + PFN_FLASH_WRITE_CALLBACK *flash_write; + uint32_t *TotalLength; /* R/W Length */ + uint32_t *InitOffset; /* R/W Offset */ + void *flash_data; + + MSC_CBW CBW; /* Command Block Wrapper */ + MSC_CSW CSW; /* Command Status Wrapper */ + uint8_t BulkStage; /* Bulk Stage */ + uint8_t BulkBuf[MSC_MAX_PACKET]; /* Bulk In/Out Buffer */ + uint8_t BulkLen; /* Bulk In/Out Length */ + uint32_t Length; /* R/W Length */ + + uint32_t Offset; /* R/W Offset */ + uint8_t Memory[65]; +} USBMSC_Dev; + +/*********************************************************************** + * extern API of this component + **********************************************************************/ +extern void MSC_Open(USBMSC_Dev *dev); +extern void MSC_Connect(USBMSC_Dev *dev,uint32_t con); +extern uint8_t MSC_Configurated(USBMSC_Dev *dev); +extern void MSC_Event(USBMSC_Dev *dev); + +#endif /* __MSC_CALLBACK_H__ */ diff --git a/CoX/middleware/USB_CLASS/USB_MSC/usb_msc.h b/CoX/middleware/USB_CLASS/USB_MSC/usb_msc.h new file mode 100644 index 00000000..0deb2f44 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_MSC/usb_msc.h @@ -0,0 +1,149 @@ +/***************************************************************************** + * U S B - M S C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : usb_msc.h + * @brief : USB Mass Storage Class Definitions + * @version : 1.0 + * @date : 28. Dec. 2010 + * @author : CooCox + ****************************************************************************/ + +#ifndef __USB_MSC_H__ +#define __USB_MSC_H__ + + +/*********************************************************************** + * MSC Subclass Codes + **********************************************************************/ +#define MSC_SUBCLASS_RBC 0x01 +#define MSC_SUBCLASS_SFF8020I_MMC2 0x02 +#define MSC_SUBCLASS_QIC157 0x03 +#define MSC_SUBCLASS_UFI 0x04 +#define MSC_SUBCLASS_SFF8070I 0x05 +#define MSC_SUBCLASS_SCSI 0x06 +#define MSC_SUBCLASS_LSD_FS 0x07 +#define MSC_SUBCLASS_IEEE_1667 0x08 + +/*********************************************************************** + * MSC Protocol Codes + **********************************************************************/ +#define MSC_PROTOCOL_CBI_INT 0x00 +#define MSC_PROTOCOL_CBI_NOINT 0x01 +#define MSC_PROTOCOL_OBSKLETE 0x02 +#define MSC_PROTOCOL_BULK_ONLY 0x50 +#define MSC_PROTOCOL_UAS 0x62 + +/*********************************************************************** + * MSC Request Codes + **********************************************************************/ +#define MSC_REQUEST_ADSC 0x00 +#define MSC_REQUEST_GET_REQ 0xFC +#define MSC_REQUEST_PUT_REQ 0xFD +#define MSC_REQUEST_RESET 0xFF +#define MSC_REQUEST_GET_MAX_LUN 0xFE + +/*********************************************************************** + * MSC Bulk-only Stage + **********************************************************************/ +#define MSC_BS_CBW 0 /* Command Block Wrapper */ +#define MSC_BS_DATA_OUT 1 /* Data Out Phase */ +#define MSC_BS_DATA_IN 2 /* Data In Phase */ +#define MSC_BS_DATA_IN_LAST 3 /* Data In Last Phase */ +#define MSC_BS_DATA_IN_LAST_STALL 4 /* Data In Last Phase with Stall */ +#define MSC_BS_CSW 5 /* Command Status Wrapper */ +#define MSC_BS_ERROR 6 /* Error */ + + +/** + * @brief Bulk-only Command Block Wrapper + */ +typedef struct _MSC_CBW { + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataLength; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLength; + uint8_t CB[16]; +} __attribute__((packed)) MSC_CBW; + + +/** + * @brief Bulk-only Command Status Wrapper + */ +typedef struct _MSC_CSW { + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} __attribute__((packed)) MSC_CSW; + +#define MSC_CBW_Signature 0x43425355 +#define MSC_CSW_Signature 0x53425355 + +/*********************************************************************** + * CSW Status Definitions + **********************************************************************/ +#define CSW_CMD_PASSED 0x00 +#define CSW_CMD_FAILED 0x01 +#define CSW_PHASE_ERROR 0x02 + +/*********************************************************************** + * SCSI Commands + **********************************************************************/ +#define SCSI_TEST_UNIT_READY 0x00 +#define SCSI_REQUEST_SENSE 0x03 +#define SCSI_FORMAT_UNIT 0x04 +#define SCSI_INQUIRY 0x12 +#define SCSI_MODE_SELECT6 0x15 +#define SCSI_MODE_SENSE6 0x1A +#define SCSI_START_STOP_UNIT 0x1B +#define SCSI_MEDIA_REMOVAL 0x1E +#define SCSI_READ_FORMAT_CAPACITIES 0x23 +#define SCSI_READ_CAPACITY 0x25 +#define SCSI_READ10 0x28 +#define SCSI_WRITE10 0x2A +#define SCSI_VERIFY10 0x2F +#define SCSI_READ12 0xA8 +#define SCSI_WRITE12 0xAA +#define SCSI_MODE_SELECT10 0x55 +#define SCSI_MODE_SENSE10 0x5A + +/*********************************************************************** + * UFI Commands + **********************************************************************/ +#define UFI_TEST_UNIT_READY 0x00 +#define UFI_REZORE_UNIT 0x01 +#define UFI_REQUEST_SENSE 0x03 +#define UFI_FORMAT_UNIT 0x04 +#define UFI_INQUIRY 0x12 +#define UFI_START_STOP_UNIT 0x1B +#define UFI_SEND_DIAGNOSTIC 0x1D +#define UFI_MEDIA_REMOVAL 0x1E +#define UFI_READ_FORMAT_CAPACITIES 0x23 +#define UFI_READ_CAPACITY 0x25 +#define UFI_READ10 0x28 +#define UFI_WRITE10 0x2A +#define UFI_SEEK10 0x2B +#define UFI_WRITE1_VERIFY 0x2E +#define UFI_VERIFY 0x2F +#define UFI_READ12 0xA8 +#define UFI_WRITE12 0xAA +#define UFI_MODE_SELECT 0x55 +#define UFI_MODE_SENSE 0x5A + +/*********************************************************************** + * Assigned wValue Codes + **********************************************************************/ +#define MSC_REQ_GLI 0x00 +#define MSC_REQ_SPO 0x01 +#define MSC_REQ_MPO 0x02 +#define MSC_REQ_CPO 0x03 +#define MSC_REQ_EPO 0x04 +#define MSC_REQ_EFP 0x05 +#define MSC_REQ_LA 0x06 +#define MSC_REQ_CIAO 0x07 + + +#endif /* __USB_MSC_H__ */ diff --git a/CoX/middleware/USB_CLASS/USB_MSC/usb_msc_config.h b/CoX/middleware/USB_CLASS/USB_MSC/usb_msc_config.h new file mode 100644 index 00000000..e34e2338 --- /dev/null +++ b/CoX/middleware/USB_CLASS/USB_MSC/usb_msc_config.h @@ -0,0 +1,38 @@ +/***************************************************************************** + * U S B - M S C - C O M P O N E N T + ****************************************************************************/ +/** + * @file : usb_msc_config.h + * @brief : USB Custom Configuration + * @version : 1.0 + * @date : 28. Dec. 2010 + * @author : CooCox + ****************************************************************************/ + + +#ifndef __USB_MSC_CONFIG_H__ +#define __USB_MSC_CONFIG_H__ + +/*********************************************************************** + * Mass Storage Memory Layout + **********************************************************************/ +#define MSC_MemorySize 2048*1024 +#define MSC_BlockSize 512 +#define MSC_BlockCount (MSC_MemorySize / MSC_BlockSize) + +/*********************************************************************** + * MSC In/Out Endpoint Logic Address + **********************************************************************/ +#define MSC_EP_IN 0x81 +#define MSC_EP_OUT 0x02 + +/*********************************************************************** + * Max In/Out Packet Size + **********************************************************************/ +#define MSC_MAX_PACKET 64 +#define USB_VENDOR_ID 0x1FC9 // Vendor ID +#define USB_PROD_ID 0x0003 // Product ID +#define USB_DEVICE 0x0100 // Device ID + + +#endif /* __USB_MSC_CONFIG_H__ */ diff --git a/CoX/middleware/USB_ENUMERATE/type.h b/CoX/middleware/USB_ENUMERATE/type.h new file mode 100644 index 00000000..52847a83 --- /dev/null +++ b/CoX/middleware/USB_ENUMERATE/type.h @@ -0,0 +1,54 @@ +/***************************************************************************** + * U S B - C O M M O M - C O M P O N E N T + ****************************************************************************/ +/** + * @file : type.h + * @brief : Type definition Header file for NOVOTON Family + * Microprocessors + * @version : 1.0 + * @date : 28. Dec. 2010 + * @author : CooCox + ****************************************************************************/ +#ifndef __TYPE_H__ +#define __TYPE_H__ + +/********************************************************************** + * CodeRed - ifdef for GNU added to avoid potential clash with stdint.h + **********************************************************************/ +#if defined ( __GNUC__ ) +#include +#else + +/********************************************************************** + * exact-width signed integer types + **********************************************************************/ + +typedef signed char int8_t; +typedef signed short int int16_t; +typedef signed int int32_t; +typedef signed __int64 int64_t; + +/********************************************************************** + * exact-width unsigned integer types + **********************************************************************/ + +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned int uint32_t; +typedef unsigned __int64 uint64_t; + +#endif /* __GNUC__ */ + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifndef FALSE +#define FALSE (0) +#endif + +#ifndef TRUE +#define TRUE (1) +#endif + +#endif /* __TYPE_H__ */ diff --git a/CoX/middleware/USB_ENUMERATE/usb.h b/CoX/middleware/USB_ENUMERATE/usb.h new file mode 100644 index 00000000..fc96d901 --- /dev/null +++ b/CoX/middleware/USB_ENUMERATE/usb.h @@ -0,0 +1,265 @@ +/***************************************************************************** + * U S B - C O M M O M - C O M P O N E N T + ****************************************************************************/ +/** + * @file : usb.h + * @brief : USB Definitions + * @version : 1.0 + * @date : 28. Dec. 2010 + * @author : CooCox + ****************************************************************************/ + +#ifndef __USB_H__ +#define __USB_H__ +#include "type.h" +/** + * @brief word to byte union + */ +typedef union +{ + uint16_t W; + struct + { + uint8_t L; + uint8_t H; + } __attribute__((packed)) WB; +} __attribute__((packed)) WORD_BYTE; + + +/*********************************************************************** + * bmRequestType.Dir + **********************************************************************/ +#define REQUEST_HOST_TO_DEVICE 0 +#define REQUEST_DEVICE_TO_HOST 1 + +/*********************************************************************** + * bmRequestType.Type + **********************************************************************/ +#define REQUEST_STANDARD 0 +#define REQUEST_CLASS 1 +#define REQUEST_VENDOR 2 +#define REQUEST_RESERVED 3 + +/*********************************************************************** + * bmRequestType.Recipient + **********************************************************************/ +#define REQUEST_TO_DEVICE 0 +#define REQUEST_TO_INTERFACE 1 +#define REQUEST_TO_ENDPOINT 2 +#define REQUEST_TO_OTHER 3 + + +/** + * @brief bmRequestType union Definition + */ +typedef union _REQUEST_TYPE +{ + struct _BM + { + uint8_t Recipient : 5; + uint8_t Type : 2; + uint8_t Dir : 1; + } __attribute__((packed)) BM; + uint8_t B; +} __attribute__((packed)) REQUEST_TYPE; + +/*********************************************************************** + * USB Standard Request Codes + **********************************************************************/ +#define USB_REQUEST_GET_STATUS 0 +#define USB_REQUEST_CLEAR_FEATURE 1 +#define USB_REQUEST_SET_FEATURE 3 +#define USB_REQUEST_SET_ADDRESS 5 +#define USB_REQUEST_GET_DESCRIPTOR 6 +#define USB_REQUEST_SET_DESCRIPTOR 7 +#define USB_REQUEST_GET_CONFIGURATION 8 +#define USB_REQUEST_SET_CONFIGURATION 9 +#define USB_REQUEST_GET_INTERFACE 10 +#define USB_REQUEST_SET_INTERFACE 11 +#define USB_REQUEST_SYNC_FRAME 12 + + +/*********************************************************************** + * USB GET_STATUS Bit Values + **********************************************************************/ +#define USB_GETSTATUS_SELF_POWERED 0x01 +#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 +#define USB_GETSTATUS_ENDPOINT_STALL 0x01 + +/*********************************************************************** + * USB Standard Feature selectors + **********************************************************************/ +#define USB_FEATURE_ENDPOINT_STALL 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 + +/** + * @brief USB Default Control Pipe Setup Packet + */ +typedef struct _USB_SETUP_PACKET { + REQUEST_TYPE bmRequestType; + uint8_t bRequest; + WORD_BYTE wValue; + WORD_BYTE wIndex; + uint16_t wLength; +} __attribute__((packed)) USB_SETUP_PACKET; + + +/*********************************************************************** + * USB Descriptor Types + **********************************************************************/ +#define USB_DEVICE_DESCRIPTOR_TYPE 1 +#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2 +#define USB_STRING_DESCRIPTOR_TYPE 3 +#define USB_INTERFACE_DESCRIPTOR_TYPE 4 +#define USB_ENDPOINT_DESCRIPTOR_TYPE 5 +#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6 +#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7 +#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8 +#define USB_OTG_DESCRIPTOR_TYPE 9 +#define USB_DEBUG_DESCRIPTOR_TYPE 10 +#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11 + + +/*********************************************************************** + * USB Device Classes + **********************************************************************/ +#define USB_DEVICE_CLASS_RESERVED 0x00 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02 +#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03 +#define USB_DEVICE_CLASS_MONITOR 0x04 +#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05 +#define USB_DEVICE_CLASS_POWER 0x06 +#define USB_DEVICE_CLASS_PRINTER 0x07 +#define USB_DEVICE_CLASS_STORAGE 0x08 +#define USB_DEVICE_CLASS_HUB 0x09 +#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF +#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF + + +/*********************************************************************** + * bmAttributes in Configuration Descriptor + **********************************************************************/ +#define USB_CONFIG_POWERED_MASK 0x40 +#define USB_CONFIG_BUS_POWERED 0x80 +#define USB_CONFIG_SELF_POWERED 0xC0 +#define USB_CONFIG_REMOTE_WAKEUP 0x20 + +/*********************************************************************** + * bMaxPower in Configuration Descriptor + **********************************************************************/ +#define USB_CONFIG_POWER_MA(mA) ((mA)/2) + +/*********************************************************************** + * bEndpointAddress in Endpoint Descriptor + **********************************************************************/ +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) + +/*********************************************************************** + * bmAttributes in Endpoint Descriptor + **********************************************************************/ +#define USB_ENDPOINT_TYPE_MASK 0x03 +#define USB_ENDPOINT_TYPE_CONTROL 0x00 +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 +#define USB_ENDPOINT_TYPE_BULK 0x02 +#define USB_ENDPOINT_TYPE_INTERRUPT 0x03 +#define USB_ENDPOINT_SYNC_MASK 0x0C +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00 +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04 +#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08 +#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C +#define USB_ENDPOINT_USAGE_MASK 0x30 +#define USB_ENDPOINT_USAGE_DATA 0x00 +#define USB_ENDPOINT_USAGE_FEEDBACK 0x10 +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20 +#define USB_ENDPOINT_USAGE_RESERVED 0x30 + + +/** + * @brief USB Standard Device Descriptor + */ +typedef struct _USB_DEVICE_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} __attribute__((packed)) USB_DEVICE_DESCRIPTOR; + + +/** + * @brief USB 2.0 Device Qualifier Descriptor + */ +typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; +} __attribute__((packed)) USB_DEVICE_QUALIFIER_DESCRIPTOR; + +/** + * @brief USB Standard Configuration Descriptor + */ +typedef struct _USB_CONFIGURATION_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} __attribute__((packed)) USB_CONFIGURATION_DESCRIPTOR; + + +/** + * @brief USB Standard Interface Descriptor + */ +typedef struct _USB_INTERFACE_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} __attribute__((packed)) USB_INTERFACE_DESCRIPTOR; + + +/** + * @brief USB String Descriptor + */ +typedef struct _USB_STRING_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString/*[]*/; +} __attribute__((packed)) USB_STRING_DESCRIPTOR; + +/** + * @brief USB Common Descriptor + */ +typedef struct _USB_COMMON_DESCRIPTOR { + uint8_t bLength; + uint8_t bDescriptorType; +} __attribute__((packed)) USB_COMMON_DESCRIPTOR; + + +#endif /* __USB_H__ */ diff --git a/CoX/middleware/USB_ENUMERATE/usb_Enumerate.c b/CoX/middleware/USB_ENUMERATE/usb_Enumerate.c new file mode 100644 index 00000000..b06d753c --- /dev/null +++ b/CoX/middleware/USB_ENUMERATE/usb_Enumerate.c @@ -0,0 +1,1852 @@ +/***************************************************************************** + * U S B - C O M M O M - C O M P O N E N T + ****************************************************************************/ +/** + * @file : usb_Enumerate.c + * @brief : USB Enumerate Module + * @version : 1.1 + * @date : 3. Mar. 2011 + * @author : CooCox + ****************************************************************************/ +#include "usb_enumerate.h" + +/********************************************************************************************************//** + * @brief Reset USB Core + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void USB_ResetCore (USB_ENU_Dev *dev) +{ + + dev->USB_DeviceStatus = 0; + dev->USB_DeviceAddress = 0; + dev->USB_Configuration = 0; + dev->USB_EndPointMask = 0x00010001; + dev->USB_EndPointHalt = 0x00000000; + dev->USB_EndPointStall = 0x00000000; +} +/********************************************************************************************************//** + * @brief USB Request - Setup Stage + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void USB_SetupStage (USB_ENU_Dev *dev) +{ + xUSBEndpointRead(0x00, (uint8_t *)&(dev->SetupPacket)); +} + +/********************************************************************************************************//** + * @brief USB Request - Data In Stage + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void USB_DataInStage (USB_ENU_Dev *dev) +{ + uint32_t cnt; + + if (dev->EP0Data.Count > USB_MAX_PACKET0) + { + cnt = USB_MAX_PACKET0; + } else + { + cnt = dev->EP0Data.Count; + } + cnt = xUSBEndpointWrite(0x80, dev->EP0Data.pData, cnt); + dev->EP0Data.pData += cnt; + dev->EP0Data.Count -= cnt; +} + +/********************************************************************************************************//** + * @brief USB Request - Data Out Stage + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void USB_DataOutStage (USB_ENU_Dev *dev) +{ + uint32_t cnt; + + cnt = xUSBEndpointRead(0x00, dev->EP0Data.pData); + dev->EP0Data.pData += cnt; + dev->EP0Data.Count -= cnt; +} + +/********************************************************************************************************//** + * @brief USB Request - Status In Stage + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void USB_StatusInStage (USB_ENU_Dev *dev) +{ + xUSBEndpointWrite(0x80, NULL, 0); +} + +/********************************************************************************************************//** + * @brief USB Request - Status Out Stage + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void USB_StatusOutStage (USB_ENU_Dev *dev) +{ + xUSBEndpointRead(0x00, dev->EP0Buf); +} + +/********************************************************************************************************//** + * @brief Get Status USB Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +__inline uint32_t USB_ReqGetStatus (USB_ENU_Dev *dev) +{ + uint32_t n, m; + + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_DEVICE: + dev->EP0Data.pData = (uint8_t *)&(dev->USB_DeviceStatus); + break; + case REQUEST_TO_INTERFACE: + if ((dev->USB_Configuration != 0) && (dev->SetupPacket.wIndex.WB.L < dev->USB_NumInterfaces)) + { + *((uint16_t __attribute__((packed)) *)dev->EP0Buf) = 0; + dev->EP0Data.pData = dev->EP0Buf; + } + else + { + return (FALSE); + } + break; + case REQUEST_TO_ENDPOINT: + n = dev->SetupPacket.wIndex.WB.L & 0x8F; + m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); + if (((dev->USB_Configuration != 0) || ((n & 0x0F) == 0)) && (dev->USB_EndPointMask & m)) + { + *((uint16_t __attribute__((packed)) *)dev->EP0Buf) = (dev->USB_EndPointHalt & m) ? 1 : 0; + dev->EP0Data.pData = dev->EP0Buf; + } + else + { + return (FALSE); + } + break; + default: + return (FALSE); + } + return (TRUE); +} + +/********************************************************************************************************//** + * @brief Set/Clear Feature USB Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @param[in] sc: 0 - Clear, + * 1 - Set + * (global SetupPacket) + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +__inline uint32_t USB_ReqSetClrFeature (USB_ENU_Dev *dev, uint32_t sc) +{ + uint32_t n, m; + + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_DEVICE: + if (dev->SetupPacket.wValue.W == USB_FEATURE_REMOTE_WAKEUP) + { + if (sc) + { + xUSBWakeUpEnable(); + dev->USB_DeviceStatus |= USB_GETSTATUS_REMOTE_WAKEUP; + } + else + { + xUSBWakeUpDisable(); + dev->USB_DeviceStatus &= ~USB_GETSTATUS_REMOTE_WAKEUP; + } + } + else + { + return (FALSE); + } + break; + case REQUEST_TO_INTERFACE: + return (FALSE); + case REQUEST_TO_ENDPOINT: + n = dev->SetupPacket.wIndex.WB.L & 0x8F; + m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); + if ((dev->USB_Configuration != 0) && ((n & 0x0F) != 0) && (dev->USB_EndPointMask & m)) + { + if (dev->SetupPacket.wValue.W == USB_FEATURE_ENDPOINT_STALL) + { + if (sc) + { + xUSBEndpointStallSet(n); + dev->USB_EndPointHalt |= m; + } + else + { + if ((dev->USB_EndPointStall & m) != 0) + { + return (TRUE); + } + xUSBEndpointStallClear(n); +#if (USB_MSC) + if ((n == MSC_EP_IN) && ((dev->USB_EndPointHalt & m) != 0)) + { + /* Compliance Test: rewrite CSW after unstall */ +// if (CSW.dSignature == MSC_CSW_Signature) +// { +// xUSBEndpointWrite(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW)); +// } + } +#endif + dev->USB_EndPointHalt &= ~m; + } + } + else + { + return (FALSE); + } + } + else + { + return (FALSE); + } + break; + default: + return (FALSE); + } + return (TRUE); +} + +/********************************************************************************************************//** + * @brief Set Address USB Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +__inline uint32_t USB_ReqSetAddress (USB_ENU_Dev *dev) +{ + + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_DEVICE: + dev->USB_DeviceAddress = 0x80 | dev->SetupPacket.wValue.WB.L; + break; + default: + return (FALSE); + } + return (TRUE); +} + +/********************************************************************************************************//** + * @brief Get Descriptor USB Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +__inline uint32_t USB_ReqGetDescriptor (USB_ENU_Dev *dev) +{ + uint8_t *pD; + uint32_t len, n; + + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_DEVICE: + switch (dev->SetupPacket.wValue.WB.H) + { + case USB_DEVICE_DESCRIPTOR_TYPE: + dev->EP0Data.pData = (uint8_t *)dev->USB_DeviceDescriptor; + len = USB_DEVICE_DESC_SIZE; + break; + case USB_CONFIGURATION_DESCRIPTOR_TYPE: + pD = (uint8_t *)dev->USB_ConfigDescriptor; + for (n = 0; n != dev->SetupPacket.wValue.WB.L; n++) + { + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) + { + pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; + } + } + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) + { + return (FALSE); + } + dev->EP0Data.pData = pD; + len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; + break; + case USB_STRING_DESCRIPTOR_TYPE: + pD = (uint8_t *)dev->USB_StringDescriptor; + for (n = 0; n != dev->SetupPacket.wValue.WB.L; n++) + { + if (((USB_STRING_DESCRIPTOR *)pD)->bLength != 0) + { + pD += ((USB_STRING_DESCRIPTOR *)pD)->bLength; + } + } + if (((USB_STRING_DESCRIPTOR *)pD)->bLength == 0) + { + return (FALSE); + } + dev->EP0Data.pData = pD; + len = ((USB_STRING_DESCRIPTOR *)dev->EP0Data.pData)->bLength; + break; + default: + return (FALSE); + } + break; + case REQUEST_TO_INTERFACE: + switch (dev->SetupPacket.wValue.WB.H) + { +#if USB_HID + case HID_HID_DESCRIPTOR_TYPE: + if (dev->SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) + { + return (FALSE); /* Only Single HID Interface is supported */ + } + dev->EP0Data.pData = (uint8_t *)dev->USB_ConfigDescriptor + HID_DESC_OFFSET; + len = HID_DESC_SIZE; + break; + case HID_REPORT_DESCRIPTOR_TYPE: + if (dev->SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) + { + return (FALSE); /* Only Single HID Interface is supported */ + } + dev->EP0Data.pData = (uint8_t *)dev->HID_ReportDescriptor; + len = HID_ReportDescSize; + break; + case HID_PHYSICAL_DESCRIPTOR_TYPE: + return (FALSE); /* HID Physical Descriptor is not supported */ +#endif + default: + return (FALSE); + } + break; + default: + return (FALSE); + } + + if (dev->EP0Data.Count > len) + { + dev->EP0Data.Count = len; + } + + return (TRUE); +} + +/********************************************************************************************************//** + * @brief Get Configuration USB Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +__inline uint32_t USB_ReqGetConfiguration (USB_ENU_Dev *dev) +{ + + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_DEVICE: + dev->EP0Data.pData = &dev->USB_Configuration; + break; + default: + return (FALSE); + } + return (TRUE); +} + +/********************************************************************************************************//** + * @brief Add a number of bytes to a pointer's address,Call looks like: AddPtr((void **)&myPointer, 8); + * @param[in] vpptr: void pointer to pointer + * @param[in] n : number of bytes to add to pointer + * @return None +************************************************************************************************************/ +__inline void UsbAddPtr(void **vpptr, uint32_t n) +{ + /* Declare a pointer to a pointer to a byte. Only a byte pointer + * can be incremented by a number of bytes. Other pointers will + * increment by a multiple of what they point to. + */ + uint8_t **bpptr; + + /* Convert our void pointer to a pointer to a byte pointer to a pointer */ + bpptr = (uint8_t **)vpptr; + + /* Add 'n' bytes to our pointer value */ + (*bpptr) += n; +} + +/********************************************************************************************************//** + * @brief Set Configuration USB Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +__inline uint32_t USB_ReqSetConfiguration (USB_ENU_Dev *dev) +{ + USB_COMMON_DESCRIPTOR *pD; + uint32_t alt = 0; + uint32_t n, m; + + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_DEVICE: + + if (dev->SetupPacket.wValue.WB.L) + { + pD = (USB_COMMON_DESCRIPTOR *)dev->USB_ConfigDescriptor; + while (pD->bLength) + { + switch (pD->bDescriptorType) + { + case USB_CONFIGURATION_DESCRIPTOR_TYPE: + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue == dev->SetupPacket.wValue.WB.L) + { + dev->USB_Configuration = dev->SetupPacket.wValue.WB.L; + dev->USB_NumInterfaces = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bNumInterfaces; + for (n = 0; n < USB_IF_NUM; n++) + { + dev->USB_AltSetting[n] = 0; + } + for (n = 1; n < 16; n++) + { + if (dev->USB_EndPointMask & (1 << n)) + { + xUSBEndpointDisable(n); + } + if (dev->USB_EndPointMask & ((1 << 16) << n)) + { + xUSBEndpointDisable(n | 0x80); + } + } + dev->USB_EndPointMask = 0x00010001; + dev->USB_EndPointHalt = 0x00000000; + dev->USB_EndPointStall= 0x00000000; + xUSBConfigure(TRUE); + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bmAttributes & USB_CONFIG_POWERED_MASK) + { + dev->USB_DeviceStatus |= USB_GETSTATUS_SELF_POWERED; + } + else + { + dev->USB_DeviceStatus &= ~USB_GETSTATUS_SELF_POWERED; + } + } + else + { + UsbAddPtr((void **)&pD, ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength); + continue; + } + break; + case USB_INTERFACE_DESCRIPTOR_TYPE: + alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting; + break; + case USB_ENDPOINT_DESCRIPTOR_TYPE: + if (alt == 0) + { + n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F; + m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); + dev->USB_EndPointMask |= m; + xUSBEndpointConfig((USB_ENDPOINT_DESCRIPTOR *)pD,0); + xUSBEndpointEnable(n); + xUSBEndpointReset(n); + } + break; + } + UsbAddPtr((void **)&pD, pD->bLength); + } + } + else + { + dev->USB_Configuration = 0; + for (n = 1; n < 16; n++) + { + if (dev->USB_EndPointMask & (1 << n)) + { + xUSBEndpointDisable(n); + } + if (dev->USB_EndPointMask & ((1 << 16) << n)) + { + xUSBEndpointDisable(n | 0x80); + } + } + dev->USB_EndPointMask = 0x00010001; + dev->USB_EndPointHalt = 0x00000000; + dev->USB_EndPointStall = 0x00000000; + xUSBConfigure(FALSE); + } + + if (dev->USB_Configuration != dev->SetupPacket.wValue.WB.L) + { + return (FALSE); + } + break; + default: + return (FALSE); + } + return (TRUE); +} + + +/********************************************************************************************************//** + * @brief Get Interface USB Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +__inline uint32_t USB_ReqGetInterface (USB_ENU_Dev *dev) +{ + + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_INTERFACE: + if ((dev->USB_Configuration != 0) && (dev->SetupPacket.wIndex.WB.L < dev->USB_NumInterfaces)) + { + dev->EP0Data.pData = dev->USB_AltSetting + dev->SetupPacket.wIndex.WB.L; + } + else + { + return (FALSE); + } + break; + default: + return (FALSE); + } + return (TRUE); +} + +/********************************************************************************************************//** + * @brief Set Interface USB Request + * @param[in] dev : a point which contains all the global variables which using in this function + * @return TRUE - Success, FALSE - Error +************************************************************************************************************/ +__inline uint32_t USB_ReqSetInterface (USB_ENU_Dev *dev) +{ + USB_COMMON_DESCRIPTOR *pD; + uint32_t ifn = 0, alt = 0, old = 0, msk = 0; + uint32_t n, m; + uint32_t set; + + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_INTERFACE: + if (dev->USB_Configuration == 0) return (FALSE); + set = FALSE; + pD = (USB_COMMON_DESCRIPTOR *)dev->USB_ConfigDescriptor; + while (pD->bLength) + { + switch (pD->bDescriptorType) + { + case USB_CONFIGURATION_DESCRIPTOR_TYPE: + if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue != dev->USB_Configuration) + { + UsbAddPtr((void **)&pD, ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength); + continue; + } + break; + case USB_INTERFACE_DESCRIPTOR_TYPE: + ifn = ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber; + alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting; + msk = 0; + if ((ifn == dev->SetupPacket.wIndex.WB.L) && (alt == dev->SetupPacket.wValue.WB.L)) + { + set = TRUE; + old = dev->USB_AltSetting[ifn]; + dev->USB_AltSetting[ifn] = (uint8_t)alt; + } + break; + case USB_ENDPOINT_DESCRIPTOR_TYPE: + if (ifn == dev->SetupPacket.wIndex.WB.L) + { + n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F; + m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); + if (alt == dev->SetupPacket.wValue.WB.L) + { + dev->USB_EndPointMask |= m; + dev->USB_EndPointHalt &= ~m; + xUSBEndpointConfig((USB_ENDPOINT_DESCRIPTOR *)pD,0); + xUSBEndpointEnable(n); + xUSBEndpointReset(n); + msk |= m; + } + else if ((alt == old) && ((msk & m) == 0)) + { + dev->USB_EndPointMask &= ~m; + dev->USB_EndPointHalt &= ~m; + xUSBEndpointDisable(n); + } + } + break; + } + UsbAddPtr((void **)&pD, pD->bLength); + } + break; + default: + return (FALSE); + } + + return (set); +} + +/********************************************************************************************************//** + * @brief USB Endpoint 0 Event Callback + * @param[in] dev : a point which contains all the global variables which using in this function + * @param[in] event: USB_EVT_SETUP\USB_EVT_OUT\USB_EVT_IN\USB_EVT_OUT_NAK\USB_EVT_IN_NAK + * @return None +************************************************************************************************************/ +void USB_EndPoint0 (USB_ENU_Dev *dev, uint32_t event, + unsigned long ulMsgParam, + void *pvMsgData) +{ + + switch (event) + { + case USB_EVT_SETUP: + USB_SetupStage(dev); + xUSBEndpointDirCtr(dev->SetupPacket.bmRequestType.BM.Dir); + dev->EP0Data.Count = dev->SetupPacket.wLength; /* Number of bytes to transfer */ + switch (dev->SetupPacket.bmRequestType.BM.Type) + { + + case REQUEST_STANDARD: + switch (dev->SetupPacket.bRequest) + { + case USB_REQUEST_GET_STATUS: + if (!USB_ReqGetStatus(dev)) + { + goto stall_i; + } + USB_DataInStage(dev); + break; + + case USB_REQUEST_CLEAR_FEATURE: + if (!USB_ReqSetClrFeature(dev,0)) + { + goto stall_i; + } + USB_StatusInStage(dev); +#if USB_FEATURE_EVENT + if(dev->g_pfn_feature_callback !=NULL) + { + dev->g_pfn_feature_callback(0); + } +#endif + break; + + case USB_REQUEST_SET_FEATURE: + if (!USB_ReqSetClrFeature(dev,1)) + { + goto stall_i; + } + USB_StatusInStage(dev); +#if USB_FEATURE_EVENT + if(dev->g_pfn_feature_callback !=NULL) + { + dev->g_pfn_feature_callback(0); + } +#endif + break; + + case USB_REQUEST_SET_ADDRESS: + if (!USB_ReqSetAddress(dev)) + { + goto stall_i; + } + USB_StatusInStage(dev); + break; + + case USB_REQUEST_GET_DESCRIPTOR: + if (!USB_ReqGetDescriptor(dev)) + { + goto stall_i; + } + USB_DataInStage(dev); + break; + + case USB_REQUEST_SET_DESCRIPTOR: + /*stall_o:*/ + xUSBEndpointStallSet(0x00); /* not supported */ + dev->EP0Data.Count = 0; + break; + + case USB_REQUEST_GET_CONFIGURATION: + if (!USB_ReqGetConfiguration(dev)) + { + goto stall_i; + } + USB_DataInStage(dev); + break; + + case USB_REQUEST_SET_CONFIGURATION: + if (!USB_ReqSetConfiguration(dev)) + { + goto stall_i; + } + USB_StatusInStage(dev); +#if USB_CONFIGURE_EVENT + if(dev->g_pfn_config_callback != NULL) + { + dev->g_pfn_config_callback(0); + } +#endif + break; + + case USB_REQUEST_GET_INTERFACE: + if (!USB_ReqGetInterface(dev)) + { + goto stall_i; + } + USB_DataInStage(dev); + break; + + case USB_REQUEST_SET_INTERFACE: + if (!USB_ReqSetInterface(dev)) + { + goto stall_i; + } + USB_StatusInStage(dev); +#if USB_INTERFACE_EVENT + if(dev->g_pfn_interfacec_callback != NULL) + { + dev->g_pfn_interfacec_callback(0); + } +#endif + break; + + default: + goto stall_i; + } + break; /* end case REQUEST_STANDARD */ + +#if USB_CLASS + case REQUEST_CLASS: + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_DEVICE: + goto stall_i; /* not supported */ + + case REQUEST_TO_INTERFACE: +#if USB_HID + if (dev->SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) + { /* IF number correct? */ + switch (dev->SetupPacket.bRequest) + { + case HID_REQUEST_GET_REPORT: + if(dev->g_pfn_hid_get_report!=NULL) + { + if (dev->g_pfn_hid_get_report(dev->hid_data)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case HID_REQUEST_SET_REPORT: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received */ + xUSBControlOutEnble(); + goto setup_class_ok; + case HID_REQUEST_GET_IDLE: + if(dev->g_pfn_hid_get_idle!=NULL) + { + if (dev->g_pfn_hid_get_idle(dev->hid_data)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case HID_REQUEST_SET_IDLE: + if(dev->g_pfn_hid_set_idle!=NULL) + { + if (dev->g_pfn_hid_set_idle(dev->hid_data)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case HID_REQUEST_GET_PROTOCOL: + if(dev->g_pfn_hid_get_procotol!=NULL) + { + if (dev->g_pfn_hid_get_procotol(dev->hid_data)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case HID_REQUEST_SET_PROTOCOL: + if(dev->g_pfn_hid_set_procotol!=NULL) + { + if (dev->g_pfn_hid_set_procotol(dev->hid_data)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + } + } +#endif /* USB_HID */ +#if USB_MSC + if (dev->SetupPacket.wIndex.WB.L == USB_MSC_IF_NUM) + { /* IF number correct? */ + switch (dev->SetupPacket.bRequest) + { + case MSC_REQUEST_RESET: + if ((dev->SetupPacket.wValue.W == 0) && /* RESET with invalid parameters -> STALL */ + (dev->SetupPacket.wLength == 0)) + { + if(dev->g_pfn_msc_request_reset!=NULL) + { + if (dev->g_pfn_msc_request_reset(dev->msc_data,0)) + { + USB_StatusInStage(dev); + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + } + break; + case MSC_REQUEST_GET_MAX_LUN: + if ((dev->SetupPacket.wValue.W == 0) && /* GET_MAX_LUN with invalid parameters -> STALL */ + (dev->SetupPacket.wLength == 1)) + { + if(dev->g_pfn_msc_request_get_max_lun!=NULL) + { + if (dev->g_pfn_msc_request_get_max_lun(dev->msc_data,0)) + { + dev->EP0Data.pData = dev->EP0Buf; + USB_DataInStage(dev); + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + } + break; + case MSC_REQUEST_ADSC: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + break; + case MSC_REQUEST_GET_REQ: + if ( (dev->SetupPacket.wValue.W == MSC_REQ_GLI) ) /* GET_MAX_LUN with invalid parameters -> STALL */ + { + if(dev->g_pfn_msc_request_get_req!=NULL) + { + if (dev->g_pfn_msc_request_get_req(dev->msc_data,0)) + { + dev->EP0Data.pData = dev->EP0Buf; + USB_DataInStage(dev); + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + } + break; + case MSC_REQUEST_PUT_REQ: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + break; + } + } +#endif /* USB_MSC */ +#if USB_AUDIO + if ((dev->SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */ + (dev->SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) || + (dev->SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) + { + switch (dev->SetupPacket.bRequest) + { + case AUDIO_REQUEST_GET_CUR: + case AUDIO_REQUEST_GET_MIN: + case AUDIO_REQUEST_GET_MAX: + case AUDIO_REQUEST_GET_RES: + if(dev->g_pfn_adc_if_getrequestt != NULL) + { + if (dev->g_pfn_adc_if_getrequestt(dev->adc_data)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case AUDIO_REQUEST_SET_CUR: + // case AUDIO_REQUEST_SET_MIN: + // case AUDIO_REQUEST_SET_MAX: + // case AUDIO_REQUEST_SET_RES: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received */ + goto setup_class_ok; + } + } +#endif /* USB_AUDIO */ +#if USB_CDC + if ((dev->SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */ + (dev->SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) + { + switch (dev->SetupPacket.bRequest) + { + case CDC_SEND_ENCAPSULATED_COMMAND://out data + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_GET_ENCAPSULATED_RESPONSE://in data + if(dev->g_pfn_cdc_GetEncapsulatedResponse != NULL) + { + if (dev->g_pfn_cdc_GetEncapsulatedResponse(dev->cdc_data,0)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_COMM_FEATURE://out data + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_GET_COMM_FEATURE://in data + if(dev->g_pfn_cdc_GetCommFeature != NULL) + { + if (dev->g_pfn_cdc_GetCommFeature(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_CLEAR_COMM_FEATURE://out none + if(dev->g_pfn_cdc_ClearCommFeature != NULL) + { + if (dev->g_pfn_cdc_ClearCommFeature(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_AUX_LINE_STATE://out none + if(dev->g_pfn_cdc_SetAuxLineState != NULL) + { + if (dev->g_pfn_cdc_SetAuxLineState(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_HOOK_STATE://out none + if(dev->g_pfn_cdc_SetHookState != NULL) + { + if (dev->g_pfn_cdc_SetHookState(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_PULSE_SETUP://out none + if(dev->g_pfn_cdc_PulseSetup != NULL) + { + if (dev->g_pfn_cdc_PulseSetup(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SEND_PULSE://out none + if(dev->g_pfn_cdc_SendPulse != NULL) + { + if (dev->g_pfn_cdc_SendPulse(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_PULSE_TIME://out none + if(dev->g_pfn_cdc_SetPulseTime != NULL) + { + if (dev->g_pfn_cdc_SetPulseTime(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_RING_AUX_JACK://out none + if(dev->g_pfn_cdc_RingAuxJack != NULL) + { + if (dev->g_pfn_cdc_RingAuxJack(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_LINE_CODING: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_GET_LINE_CODING: + if(dev->g_pfn_cdc_GetLineCoding != NULL) + { + if (dev->g_pfn_cdc_GetLineCoding(dev->cdc_data,0)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_CONTROL_LINE_STATE: + if(dev->g_pfn_cdc_SetControlLineState != NULL) + { + if (dev->g_pfn_cdc_SetControlLineState(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SEND_BREAK: + if(dev->g_pfn_cdc_SendBreak != NULL) + { + if (dev->g_pfn_cdc_SendBreak(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_RINGER_PARMS: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_GET_RINGER_PARMS: + if(dev->g_pfn_cdc_GetRingerParms != NULL) + { + if (dev->g_pfn_cdc_GetRingerParms(dev->cdc_data,0)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_OPERATION_PARMS: + if(dev->g_pfn_cdc_SetOperationParms != NULL) + { + if (dev->g_pfn_cdc_SetOperationParms(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_GET_OPERATION_PARMS: + if(dev->g_pfn_cdc_GetOperationParms != NULL) + { + if (dev->g_pfn_cdc_GetOperationParms(dev->cdc_data,0)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_LINE_PARMS: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_GET_LINE_PARMS: + if(dev->g_pfn_cdc_GetLineParms != NULL) + { + if (dev->g_pfn_cdc_GetLineParms(dev->cdc_data,0)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_DIAL_DIGITS: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_SET_UNIT_PARAMETER: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_GET_UNIT_PARAMETER: + if(dev->g_pfn_cdc_GetUnitParameter != NULL) + { + if (dev->g_pfn_cdc_GetUnitParameter(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_CLEAR_UNIT_PARAMETER: + if(dev->g_pfn_cdc_ClearUnitParameter != NULL) + { + if (dev->g_pfn_cdc_ClearUnitParameter(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_GET_PROFILE: + if(dev->g_pfn_cdc_GetProfile != NULL) + { + if (dev->g_pfn_cdc_GetProfile(dev->cdc_data,0)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_ETHERNET_MULTICAST_FILTERS: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_SET_ETHERNET_PMP_FILTER: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_GET_ETHERNET_PMP_FILTER: + if(dev->g_pfn_cdc_GetEthernetPowerManagementPatternFilter != NULL) + { + if (dev->g_pfn_cdc_GetEthernetPowerManagementPatternFilter(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_ETHERNET_PACKET_FILTER: + if(dev->g_pfn_cdc_SetEthernetPacketFilter != NULL) + { + if (dev->g_pfn_cdc_SetEthernetPacketFilter(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_GET_ETHERNET_STATISTIC: + if(dev->g_pfn_cdc_GetEthernetStatistic != NULL) + { + if (dev->g_pfn_cdc_GetEthernetStatistic(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_ATM_DATA_FORMAT: + if(dev->g_pfn_cdc_SetATMDataFormat != NULL) + { + if (dev->g_pfn_cdc_SetATMDataFormat(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_GET_ATM_DEVICE_STATISTICS: + if(dev->g_pfn_cdc_GetATMDeviceStatistics != NULL) + { + if (dev->g_pfn_cdc_GetATMDeviceStatistics(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_ATM_DEFAULT_VC: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received, see USB_EVT_OUT */ + xUSBControlOutEnble(); + goto setup_class_ok; + case CDC_GET_ATM_VC_STATISTICS: + if(dev->g_pfn_cdc_GetATMVCStatistics != NULL) + { + if (dev->g_pfn_cdc_GetATMVCStatistics(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + } + } +#endif /* USB_CDC */ + goto stall_i; /* not supported */ + /* end case REQUEST_TO_INTERFACE */ + + case REQUEST_TO_ENDPOINT: +#if USB_AUDIO + switch (dev->SetupPacket.bRequest) + { + case AUDIO_REQUEST_GET_CUR: + case AUDIO_REQUEST_GET_MIN: + case AUDIO_REQUEST_GET_MAX: + case AUDIO_REQUEST_GET_RES: + if(dev->g_pfn_adc_ep_getrequestt != NULL) + { + if (dev->g_pfn_adc_ep_getrequestt(dev->adc_data)) + { + dev->EP0Data.pData = dev->EP0Buf; /* point to data to be sent */ + USB_DataInStage(dev); /* send requested data */ + goto setup_class_ok; + } + } + else + { + goto stall_i; + } + break; + case AUDIO_REQUEST_SET_CUR: + // case AUDIO_REQUEST_SET_MIN: + // case AUDIO_REQUEST_SET_MAX: + // case AUDIO_REQUEST_SET_RES: + dev->EP0Data.pData = dev->EP0Buf; /* data to be received */ + goto setup_class_ok; + } +#endif /* USB_AUDIO */ + goto stall_i; + /* end case REQUEST_TO_ENDPOINT */ + + default: + goto stall_i; + } + setup_class_ok: /* request finished successfully */ + break; /* end case REQUEST_CLASS */ +#endif /* USB_CLASS */ + +#if USB_VENDOR + case REQUEST_VENDOR: + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + + case REQUEST_TO_DEVICE: + if(dev->g_pfn_vender_device != NULL) + { + if (!dev->g_pfn_vender_device(dev->vender_data, TRUE)) + { + goto stall_i; /* not supported */ + } + } + else + { + goto stall_i; + } + break; + + case REQUEST_TO_INTERFACE: + if(dev->g_pfn_vender_interface != NULL) + { + if (!dev->g_pfn_vender_interface(dev->vender_data, TRUE)) + { + goto stall_i; /* not supported */ + } + } + else + { + goto stall_i; + } + break; + + case REQUEST_TO_ENDPOINT: + if(dev->g_pfn_vender_endpoint != NULL) + { + if (!dev->g_pfn_vender_endpoint(dev->vender_data, TRUE)) + { + goto stall_i; /* not supported */ + } + } + else + { + goto stall_i; + } + break; + + default: + goto stall_i; + } + + if (dev->SetupPacket.wLength) + { + if (dev->SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) + { + USB_DataInStage(dev); + } + } + else + { + USB_StatusInStage(dev); + } + + break; /* end case REQUEST_VENDOR */ +#endif /* USB_VENDOR */ + + default: +stall_i: + xUSBEndpointStallSet(0x80); + dev->EP0Data.Count = 0; + break; + } + break; /* end case USB_EVT_SETUP */ + + case USB_EVT_OUT: + if (dev->SetupPacket.bmRequestType.BM.Dir == REQUEST_HOST_TO_DEVICE) + { + if (dev->EP0Data.Count) + { /* still data to receive ? */ + USB_DataOutStage(dev); /* receive data */ + if (dev->EP0Data.Count == 0) + { /* data complete ? */ + switch (dev->SetupPacket.bmRequestType.BM.Type) + { + + case REQUEST_STANDARD: + goto stall_i; /* not supported */ + +#if (USB_CLASS) + case REQUEST_CLASS: + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + case REQUEST_TO_DEVICE: + goto stall_i; /* not supported */ + + case REQUEST_TO_INTERFACE: +#if USB_MSC + if (dev->SetupPacket.wIndex.WB.L == USB_MSC_IF_NUM) + { /* IF number correct? */ + switch (dev->SetupPacket.bRequest) + { + case MSC_REQUEST_ADSC: + if(dev->g_pfn_msc_request_adsc != NULL) + { + if (dev->g_pfn_msc_request_adsc(dev->msc_data,0)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case MSC_REQUEST_PUT_REQ: + if(dev->g_pfn_msc_request_put_req != NULL) + { + if (dev->g_pfn_msc_request_put_req(dev->msc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + } + } +#endif /* USB_MSC */ +#if USB_HID + if (dev->SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) + { /* IF number correct? */ + switch (dev->SetupPacket.bRequest) + { + case HID_REQUEST_SET_REPORT: + if(dev->g_pfn_hid_set_report != NULL) + { + if (dev->g_pfn_hid_set_report(dev->hid_data)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + } + } +#endif /* USB_HID */ +#if USB_AUDIO + if ((dev->SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */ + (dev->SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) || + (dev->SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) + { + switch (dev->SetupPacket.bRequest) + { + case AUDIO_REQUEST_SET_CUR: + // case AUDIO_REQUEST_SET_MIN: + // case AUDIO_REQUEST_SET_MAX: + // case AUDIO_REQUEST_SET_RES: + if(dev->g_pfn_adc_if_setrequestt != NULL) + { + if (dev->g_pfn_adc_if_setrequestt(dev->adc_data)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + } + } +#endif /* USB_AUDIO */ +#if USB_CDC + if ((dev->SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */ + (dev->SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) + { + switch (dev->SetupPacket.bRequest) + { + case CDC_SEND_ENCAPSULATED_COMMAND: + if(dev->g_pfn_cdc_SendEncapsulatedCommand != NULL) + { + if (dev->g_pfn_cdc_SendEncapsulatedCommand(dev->cdc_data,0)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_COMM_FEATURE: + if(dev->g_pfn_cdc_SetCommFeature != NULL) + { + if (dev->g_pfn_cdc_SetCommFeature(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_LINE_CODING: + if(dev->g_pfn_cdc_SetLineCoding != NULL) + { + if (dev->g_pfn_cdc_SetLineCoding(dev->cdc_data,0)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_RINGER_PARMS: + if(dev->g_pfn_cdc_SetLineCoding != NULL) + { + if (dev->g_pfn_cdc_SetLineCoding(dev->cdc_data,0)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_LINE_PARMS: + if(dev->g_pfn_cdc_SetLineParms != NULL) + { + if (dev->g_pfn_cdc_SetLineParms(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_DIAL_DIGITS: + if(dev->g_pfn_cdc_DialDigits != NULL) + { + if (dev->g_pfn_cdc_DialDigits(dev->cdc_data,0)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_UNIT_PARAMETER: + if(dev->g_pfn_cdc_SetUnitParameter != NULL) + { + if (dev->g_pfn_cdc_SetUnitParameter(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_ETHERNET_MULTICAST_FILTERS: + if(dev->g_pfn_cdc_SetEthernetMulticastFilters != NULL) + { + if (dev->g_pfn_cdc_SetEthernetMulticastFilters(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_ETHERNET_PMP_FILTER: + if(dev->g_pfn_cdc_SetEthernetPowerManagementPatternFilter != NULL) + { + if (dev->g_pfn_cdc_SetEthernetPowerManagementPatternFilter(dev->cdc_data,dev->SetupPacket.wValue.W)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + case CDC_SET_ATM_DEFAULT_VC: + if(dev->g_pfn_cdc_SetATMDefaultVC != NULL) + { + if (dev->g_pfn_cdc_SetATMDefaultVC(dev->cdc_data,0)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + + } + } +#endif /* USB_CDC */ + goto stall_i; + /* end case REQUEST_TO_INTERFACE */ + + case REQUEST_TO_ENDPOINT: +#if USB_AUDIO + switch (dev->SetupPacket.bRequest) + { + case AUDIO_REQUEST_SET_CUR: + // case AUDIO_REQUEST_SET_MIN: + // case AUDIO_REQUEST_SET_MAX: + // case AUDIO_REQUEST_SET_RES: + if(dev->g_pfn_adc_ep_setrequestt != NULL) + { + if (dev->g_pfn_adc_ep_setrequestt(dev->adc_data)) + { + USB_StatusInStage(dev); /* send Acknowledge */ + goto out_class_ok; + } + } + else + { + goto stall_i; + } + break; + } +#endif /* USB_AUDIO */ + goto stall_i; + /* end case REQUEST_TO_ENDPOINT */ + + default: + goto stall_i; + } +out_class_ok: /* request finished successfully */ + break; /* end case REQUEST_CLASS */ +#endif /* USB_CLASS */ + +#if USB_VENDOR + case REQUEST_VENDOR: + switch (dev->SetupPacket.bmRequestType.BM.Recipient) + { + + case REQUEST_TO_DEVICE: + if(dev->g_pfn_vender_device != NULL) + { + if (!dev->g_pfn_vender_device(dev->vender_data, TRUE)) + { + goto stall_i; /* not supported */ + } + } + else + { + goto stall_i; + } + break; + + case REQUEST_TO_INTERFACE: + if(dev->g_pfn_vender_interface != NULL) + { + if (!dev->g_pfn_vender_interface(dev->vender_data, TRUE)) + { + goto stall_i; /* not supported */ + } + } + else + { + goto stall_i; + } + break; + + case REQUEST_TO_ENDPOINT: + if(dev->g_pfn_vender_endpoint != NULL) + { + if (!dev->g_pfn_vender_endpoint(dev->vender_data, TRUE)) + { + goto stall_i; /* not supported */ + } + } + else + { + goto stall_i; + } + break; + + default: + goto stall_i; + } + + USB_StatusInStage(dev); + + break; /* end case REQUEST_VENDOR */ +#endif /* USB_VENDOR */ + + default: + goto stall_i; + } + } + } + } + else + { + USB_StatusOutStage(dev); /* receive Acknowledge */ + } + break; /* end case USB_EVT_OUT */ + + case USB_EVT_IN : + if (dev->SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) + { + xUSBControlOutEnble(); + USB_DataInStage(dev); /* send data */ + } + else + { + if (dev->USB_DeviceAddress & 0x80) + { + dev->USB_DeviceAddress &= 0x7F; + xUSBSetAddress(dev->USB_DeviceAddress); + } + } + break; /* end case USB_EVT_IN */ + + case USB_EVT_OUT_STALL: + xUSBEndpointStallClear(0x00); + break; + + case USB_EVT_IN_STALL: + xUSBEndpointStallClear(0x80); + break; + + } +} + +/********************************************************************************************************//** + * @brief USB_Init - Initialization of the USB + * @param[in] dev : a point which contains all the global variables which using in this function + * @return None +************************************************************************************************************/ +void USB_Init(USB_ENU_Dev *dev) +{ + xUSBEventHandler(0,(xtEventCallback)USB_EndPoint0,(void *)dev ); + xUSBInit(); +} + +/********************************************************************************************************//** + * @brief USB conecet - pull up the USB to conecet to the host + * @param[in] dev : a point which contains all the global variables which using in this function + * @param[in] con : TRUE \ FALSE + * @return None +************************************************************************************************************/ +void USB_conecet(USB_ENU_Dev *dev, uint32_t con) +{ + xUSBConnect(con); +} + + diff --git a/CoX/middleware/USB_ENUMERATE/usb_Enumerate.h b/CoX/middleware/USB_ENUMERATE/usb_Enumerate.h new file mode 100644 index 00000000..a0c00904 --- /dev/null +++ b/CoX/middleware/USB_ENUMERATE/usb_Enumerate.h @@ -0,0 +1,185 @@ +/***************************************************************************** + * U S B - C O M M O M - C O M P O N E N T + ****************************************************************************/ +/** + * @file : usb_Enumerate.h + * @brief : USB Enumerate Definitions + * @version : 1.1 + * @date : 3. Mar. 2011 + * @author : CooCox + ****************************************************************************/ +#ifndef __USB_ENUMERATE_H__ +#define __USB_ENUMERATE_H__ +#include "xusb.h" +#include "usb.h" +#include "type.h" +#include "usb_desc.h" +#include "usb_com_config.h" + +#if (USB_CLASS) + +#if (USB_AUDIO) +typedef uint32_t (PFN_ADC_CALLBACK)(void *data); +#include "usb_audio.h" +#include "usb_adc_config.h" +#endif + +#if (USB_HID) +typedef uint32_t (PFN_HID_CALLBACK)(void *data); +#include "usb_hid.h" +#include "usb_hid_config.h" +#endif + +#if (USB_MSC) +typedef uint32_t (PFN_MSC_CALLBACK)(void *data,uint32_t para); +#include"usb_msc_config.h" +#include"usb_msc.h" +#endif + +#if (USB_CDC) +typedef uint32_t (PFN_CDC_CALLBACK)(void *data,uint32_t para); +#include "usb_cdc.h" +#include "usb_cdc_config.h" +#endif + +#endif + +#if (USB_VENDOR) +//#include "vendor.h" +typedef uint32_t (PFN_VENDOR_CALLBACK)(void *data,uint32_t para); +#endif + +/*********************************************************************** + * USB BUS event call back function definition + **********************************************************************/ +typedef void (PFN_CONFIG_CALLBACK)(uint32_t event); + +/*********************************************************************** + * USB end point event call back function definition + **********************************************************************/ +typedef void (PFN_EP_CALLBACK)(void *data,uint32_t event); + +/** + * @brief USB End Point Data Structure + */ +typedef struct _USB_EP_DATA { + uint8_t *pData; /**< point of EP data */ + uint16_t Count; /**< count of EP data */ +} USB_EP_DATA; + +/** + * @brief USB Enumerate Structure + */ +typedef struct +{ + //COX_USB_PI *usb; /**< USB Peripheral Interface Used */ + + PFN_CONFIG_CALLBACK *g_pfn_config_callback; + PFN_CONFIG_CALLBACK *g_pfn_reset_callback; + PFN_CONFIG_CALLBACK *g_pfn_suspend_callback; + PFN_CONFIG_CALLBACK *g_pfn_resume_callback; + PFN_CONFIG_CALLBACK *g_pfn_wakeup_callback; + PFN_CONFIG_CALLBACK *g_pfn_interfacec_callback; + PFN_CONFIG_CALLBACK *g_pfn_feature_callback; + + const uint8_t *USB_DeviceDescriptor; + const uint8_t *USB_ConfigDescriptor; + const uint8_t *USB_StringDescriptor; + +#if (USB_AUDIO) + + void *adc_data; + PFN_ADC_CALLBACK *g_pfn_adc_if_getrequestt; + PFN_ADC_CALLBACK *g_pfn_adc_if_setrequestt; + PFN_ADC_CALLBACK *g_pfn_adc_ep_getrequestt; + PFN_ADC_CALLBACK *g_pfn_adc_ep_setrequestt; + +#endif +#if (USB_HID) + const uint8_t *HID_ReportDescriptor; + void *hid_data; + PFN_HID_CALLBACK *g_pfn_hid_get_report; + PFN_HID_CALLBACK *g_pfn_hid_set_report; + PFN_HID_CALLBACK *g_pfn_hid_get_idle; + PFN_HID_CALLBACK *g_pfn_hid_set_idle; + PFN_HID_CALLBACK *g_pfn_hid_get_procotol; + PFN_HID_CALLBACK *g_pfn_hid_set_procotol; + +#endif + +#if (USB_MSC) + void *msc_data; + PFN_MSC_CALLBACK *g_pfn_msc_request_adsc; + PFN_MSC_CALLBACK *g_pfn_msc_request_get_req; + PFN_MSC_CALLBACK *g_pfn_msc_request_put_req; + PFN_MSC_CALLBACK *g_pfn_msc_request_reset; + PFN_MSC_CALLBACK *g_pfn_msc_request_get_max_lun; +#endif +#if (USB_CDC) + void *cdc_data; + PFN_CDC_CALLBACK *g_pfn_cdc_SendEncapsulatedCommand; + PFN_CDC_CALLBACK *g_pfn_cdc_GetEncapsulatedResponse; + PFN_CDC_CALLBACK *g_pfn_cdc_SetCommFeature; + PFN_CDC_CALLBACK *g_pfn_cdc_GetCommFeature; + PFN_CDC_CALLBACK *g_pfn_cdc_ClearCommFeature ; + PFN_CDC_CALLBACK *g_pfn_cdc_SetAuxLineState; + PFN_CDC_CALLBACK *g_pfn_cdc_SetHookState; + PFN_CDC_CALLBACK *g_pfn_cdc_PulseSetup; + PFN_CDC_CALLBACK *g_pfn_cdc_SendPulse; + PFN_CDC_CALLBACK *g_pfn_cdc_SetPulseTime; + PFN_CDC_CALLBACK *g_pfn_cdc_RingAuxJack ; + PFN_CDC_CALLBACK *g_pfn_cdc_GetLineCoding; + PFN_CDC_CALLBACK *g_pfn_cdc_SetLineCoding; + PFN_CDC_CALLBACK *g_pfn_cdc_SetControlLineState; + PFN_CDC_CALLBACK *g_pfn_cdc_SendBreak; + PFN_CDC_CALLBACK *g_pfn_cdc_SetRingerParms; + PFN_CDC_CALLBACK *g_pfn_cdc_GetRingerParms; + PFN_CDC_CALLBACK *g_pfn_cdc_SetOperationParms; + PFN_CDC_CALLBACK *g_pfn_cdc_GetOperationParms; + PFN_CDC_CALLBACK *g_pfn_cdc_SetLineParms; + PFN_CDC_CALLBACK *g_pfn_cdc_GetLineParms; + PFN_CDC_CALLBACK *g_pfn_cdc_DialDigits; + PFN_CDC_CALLBACK *g_pfn_cdc_SetUnitParameter; + PFN_CDC_CALLBACK *g_pfn_cdc_GetUnitParameter; + PFN_CDC_CALLBACK *g_pfn_cdc_ClearUnitParameter; + PFN_CDC_CALLBACK *g_pfn_cdc_GetProfile; + PFN_CDC_CALLBACK *g_pfn_cdc_SetEthernetMulticastFilters; + PFN_CDC_CALLBACK *g_pfn_cdc_SetEthernetPowerManagementPatternFilter; + PFN_CDC_CALLBACK *g_pfn_cdc_GetEthernetPowerManagementPatternFilter; + PFN_CDC_CALLBACK *g_pfn_cdc_SetEthernetPacketFilter; + PFN_CDC_CALLBACK *g_pfn_cdc_GetEthernetStatistic ; + PFN_CDC_CALLBACK *g_pfn_cdc_SetATMDataFormat ; + PFN_CDC_CALLBACK *g_pfn_cdc_GetATMDeviceStatistics ; + PFN_CDC_CALLBACK *g_pfn_cdc_SetATMDefaultVC ; + PFN_CDC_CALLBACK *g_pfn_cdc_GetATMVCStatistics ; + +#endif + +#if (USB_VENDOR) + void *vender_data; + PFN_VENDOR_CALLBACK *g_pfn_vender_device; + PFN_VENDOR_CALLBACK *g_pfn_vender_interface; + PFN_VENDOR_CALLBACK *g_pfn_vender_endpoint; +#endif + + uint16_t USB_DeviceStatus; + uint8_t USB_DeviceAddress; + uint8_t USB_Configuration; + uint32_t USB_EndPointMask; + uint32_t USB_EndPointHalt; + uint32_t USB_EndPointStall; + uint8_t USB_NumInterfaces; + uint8_t USB_AltSetting[1]; + uint8_t EP0Buf[USB_MAX_PACKET0]; + USB_EP_DATA EP0Data; + USB_SETUP_PACKET SetupPacket; + +} USB_ENU_Dev; + + +/*********************************************************************** + * extern API of this component + **********************************************************************/ +extern void USB_Init(USB_ENU_Dev *dev); + +#endif /* __USB_ENUMERATE_H__ */ diff --git a/CoX/middleware/USB_ENUMERATE/usb_com_config.h b/CoX/middleware/USB_ENUMERATE/usb_com_config.h new file mode 100644 index 00000000..9ab0844e --- /dev/null +++ b/CoX/middleware/USB_ENUMERATE/usb_com_config.h @@ -0,0 +1,36 @@ +/***************************************************************************** + * U S B - C O M M O M - C O M P O N E N T + ****************************************************************************/ +/** + * @file : usb_com_config.h + * @brief : usb_com_config + * Microprocessors + * @version : 1.0 + * @date : 28. Dec. 2010 + * @author : CooCox + ****************************************************************************/ +#ifndef __USB_COM_CONFIG_H__ +#define __USB_COM_CONFIG_H__ + +#define USB_POWER 0 /*!<0=> Bus-powered,1=> Self-powered */ +#define USB_IF_NUM 1 /*! */ +#define USB_LOGIC_EP_NUM 16 /*! */ +#define USB_MAX_PACKET0 64 /*! */ +#define USB_MSC 1 /*! */ +#define USB_AUDIO 0 /*!