diff --git a/examples/RISCV-32-Sail-Validation/list.json b/examples/RISCV-32-Sail-Validation/list.json
new file mode 100644
index 00000000..a1f9cebb
--- /dev/null
+++ b/examples/RISCV-32-Sail-Validation/list.json
@@ -0,0 +1,536 @@
+[
+ {
+ "name": "rv32ua-p-lrsc.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-lrsc.elf",
+ "doubleen": false,
+ "vectoren": true
+ },
+ {
+ "name": "rv32ud-p-fmin.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ud-p-fmin.elf",
+ "doubleen": true,
+ "vectoren": true
+ },
+ {
+ "name": "rv32mi-p-breakpoint.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32mi-p-breakpoint.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32mi-p-csr.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32mi-p-csr.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32mi-p-illegal.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32mi-p-illegal.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32mi-p-ma_addr.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32mi-p-ma_addr.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32mi-p-ma_fetch.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32mi-p-ma_fetch.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32mi-p-mcsr.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32mi-p-mcsr.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32mi-p-sbreak.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32mi-p-sbreak.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32mi-p-scall.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32mi-p-scall.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32mi-p-shamt.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32mi-p-shamt.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32si-p-csr.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32si-p-csr.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32si-p-dirty.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32si-p-dirty.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32si-p-ma_fetch.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32si-p-ma_fetch.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32si-p-sbreak.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32si-p-sbreak.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32si-p-scall.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32si-p-scall.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32si-p-wfi.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32si-p-wfi.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ua-p-amoadd_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-amoadd_w.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ua-p-amoand_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-amoand_w.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ua-p-amomaxu_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-amomaxu_w.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ua-p-amomax_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-amomax_w.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ua-p-amominu_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-amominu_w.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ua-p-amomin_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-amomin_w.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ua-p-amoor_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-amoor_w.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ua-p-amoswap_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-amoswap_w.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ua-p-amoxor_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ua-p-amoxor_w.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32uc-p-rvc.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32uc-p-rvc.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ud-p-fadd.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ud-p-fadd.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ud-p-fclass.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ud-p-fclass.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ud-p-fcmp.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ud-p-fcmp.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ud-p-fcvt.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ud-p-fcvt_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt_w.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ud-p-fdiv.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ud-p-fdiv.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ud-p-fmadd.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ud-p-fmadd.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32uf-p-fadd.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32uf-p-fadd.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32uf-p-fclass.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32uf-p-fclass.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32uf-p-fcmp.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32uf-p-fcmp.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32uf-p-fcvt.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32uf-p-fcvt_w.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt_w.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32uf-p-fdiv.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32uf-p-fdiv.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32uf-p-fmadd.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32uf-p-fmadd.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32uf-p-fmin.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32uf-p-fmin.elf",
+ "doubleen": true,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-add.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-add.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-addi.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-addi.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-and.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-and.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-andi.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-andi.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-auipc.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-auipc.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-beq.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-beq.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-bge.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-bge.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-bgeu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-bgeu.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-blt.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-blt.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-bltu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-bltu.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-bne.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-bne.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-fence_i.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-fence_i.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-jal.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-jal.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-jalr.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-jalr.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-lb.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-lb.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-lbu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-lbu.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-lh.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-lh.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-lhu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-lhu.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-lui.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-lui.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-lw.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-lw.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-or.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-or.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-ori.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-ori.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-sb.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-sb.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-sh.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-sh.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-simple.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-simple.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-sll.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-sll.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-slli.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-slli.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-slt.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-slt.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-slti.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-slti.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-sltiu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-sltiu.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-sltu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-sltu.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-sra.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-sra.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-srai.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-srai.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-srl.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-srl.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-srli.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-srli.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-sub.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-sub.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-sw.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-sw.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-xor.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-xor.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32ui-p-xori.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32ui-p-xori.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32um-p-div.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32um-p-div.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32um-p-divu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32um-p-divu.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32um-p-mul.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32um-p-mul.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32um-p-mulh.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32um-p-mulh.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32um-p-mulhsu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32um-p-mulhsu.elf",
+ "doubleen": true,
+ "vectoren": true
+ },
+ {
+ "name": "rv32um-p-mulhu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32um-p-mulhu.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32um-p-rem.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32um-p-rem.elf",
+ "doubleen": false,
+ "vectoren": false
+ },
+ {
+ "name": "rv32um-p-remu.elf",
+ "url": "examples/RISCV-32-Sail-Validation/rv32um-p-remu.elf",
+ "doubleen": false,
+ "vectoren": false
+ }
+]
\ No newline at end of file
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-breakpoint.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-breakpoint.elf
new file mode 100644
index 00000000..b0547375
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32mi-p-breakpoint.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-csr.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-csr.elf
new file mode 100644
index 00000000..bdd015b6
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32mi-p-csr.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-illegal.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-illegal.elf
new file mode 100644
index 00000000..c4175e8c
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32mi-p-illegal.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_addr.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_addr.elf
new file mode 100644
index 00000000..954fccca
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_addr.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_fetch.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_fetch.elf
new file mode 100644
index 00000000..523433e6
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_fetch.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-mcsr.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-mcsr.elf
new file mode 100644
index 00000000..9c15c589
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32mi-p-mcsr.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-sbreak.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-sbreak.elf
new file mode 100644
index 00000000..867e1d76
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32mi-p-sbreak.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-scall.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-scall.elf
new file mode 100644
index 00000000..20c63310
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32mi-p-scall.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-shamt.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-shamt.elf
new file mode 100644
index 00000000..5f4964f8
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32mi-p-shamt.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-csr.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-csr.elf
new file mode 100644
index 00000000..a0f14b7b
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32si-p-csr.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-dirty.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-dirty.elf
new file mode 100644
index 00000000..693451c6
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32si-p-dirty.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-ma_fetch.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-ma_fetch.elf
new file mode 100644
index 00000000..7a5fc3cc
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32si-p-ma_fetch.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-sbreak.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-sbreak.elf
new file mode 100644
index 00000000..13af3541
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32si-p-sbreak.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-scall.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-scall.elf
new file mode 100644
index 00000000..a73522ae
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32si-p-scall.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-wfi.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-wfi.elf
new file mode 100644
index 00000000..b5471c1c
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32si-p-wfi.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoadd_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoadd_w.elf
new file mode 100644
index 00000000..7e01c358
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoadd_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoand_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoand_w.elf
new file mode 100644
index 00000000..0196fd60
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoand_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amomax_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amomax_w.elf
new file mode 100644
index 00000000..b6e91a5b
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-amomax_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amomaxu_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amomaxu_w.elf
new file mode 100644
index 00000000..81eeb29a
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-amomaxu_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amomin_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amomin_w.elf
new file mode 100644
index 00000000..959194f6
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-amomin_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amominu_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amominu_w.elf
new file mode 100644
index 00000000..c8180700
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-amominu_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoor_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoor_w.elf
new file mode 100644
index 00000000..b62c0e82
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoor_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoswap_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoswap_w.elf
new file mode 100644
index 00000000..3094b78b
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoswap_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoxor_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoxor_w.elf
new file mode 100644
index 00000000..a893682f
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoxor_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-lrsc.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-lrsc.elf
new file mode 100644
index 00000000..4f0e3ede
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ua-p-lrsc.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32uc-p-rvc.elf b/examples/RISCV-32-Sail-Validation/rv32uc-p-rvc.elf
new file mode 100644
index 00000000..7813b712
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32uc-p-rvc.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fadd.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fadd.elf
new file mode 100644
index 00000000..d1835614
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ud-p-fadd.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fclass.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fclass.elf
new file mode 100644
index 00000000..7e67e8ba
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ud-p-fclass.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fcmp.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fcmp.elf
new file mode 100644
index 00000000..110986d3
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ud-p-fcmp.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt.elf
new file mode 100644
index 00000000..fda1e44f
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt_w.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt_w.elf
new file mode 100644
index 00000000..77b06c09
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fdiv.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fdiv.elf
new file mode 100644
index 00000000..56fe7eb2
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ud-p-fdiv.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fmadd.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fmadd.elf
new file mode 100644
index 00000000..33a8d124
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ud-p-fmadd.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fmin.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fmin.elf
new file mode 100644
index 00000000..1ff03046
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ud-p-fmin.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fadd.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fadd.elf
new file mode 100644
index 00000000..a783f7ae
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32uf-p-fadd.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fclass.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fclass.elf
new file mode 100644
index 00000000..3a520ad3
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32uf-p-fclass.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fcmp.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fcmp.elf
new file mode 100644
index 00000000..b0f64b18
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32uf-p-fcmp.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt.elf
new file mode 100644
index 00000000..da776a26
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt_w.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt_w.elf
new file mode 100644
index 00000000..05dc1ab0
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt_w.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fdiv.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fdiv.elf
new file mode 100644
index 00000000..48128524
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32uf-p-fdiv.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fmadd.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fmadd.elf
new file mode 100644
index 00000000..e68a2ce8
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32uf-p-fmadd.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fmin.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fmin.elf
new file mode 100644
index 00000000..e1774aa4
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32uf-p-fmin.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-add.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-add.elf
new file mode 100644
index 00000000..a32ea330
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-add.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-addi.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-addi.elf
new file mode 100644
index 00000000..25f1c02c
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-addi.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-and.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-and.elf
new file mode 100644
index 00000000..f1468e41
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-and.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-andi.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-andi.elf
new file mode 100644
index 00000000..5c02664e
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-andi.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-auipc.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-auipc.elf
new file mode 100644
index 00000000..c50a29c1
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-auipc.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-beq.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-beq.elf
new file mode 100644
index 00000000..0d2a410b
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-beq.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-bge.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-bge.elf
new file mode 100644
index 00000000..8979b9ef
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-bge.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-bgeu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-bgeu.elf
new file mode 100644
index 00000000..80510421
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-bgeu.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-blt.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-blt.elf
new file mode 100644
index 00000000..d46af044
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-blt.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-bltu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-bltu.elf
new file mode 100644
index 00000000..e4e90ec3
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-bltu.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-bne.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-bne.elf
new file mode 100644
index 00000000..3c3460bb
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-bne.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-fence_i.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-fence_i.elf
new file mode 100644
index 00000000..5a14522f
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-fence_i.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-jal.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-jal.elf
new file mode 100644
index 00000000..2f309033
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-jal.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-jalr.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-jalr.elf
new file mode 100644
index 00000000..78f985d4
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-jalr.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lb.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lb.elf
new file mode 100644
index 00000000..5e070c89
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-lb.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lbu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lbu.elf
new file mode 100644
index 00000000..b094c86c
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-lbu.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lh.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lh.elf
new file mode 100644
index 00000000..348fa069
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-lh.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lhu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lhu.elf
new file mode 100644
index 00000000..2849a586
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-lhu.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lui.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lui.elf
new file mode 100644
index 00000000..c38c7f20
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-lui.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lw.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lw.elf
new file mode 100644
index 00000000..d28a7f2a
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-lw.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-or.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-or.elf
new file mode 100644
index 00000000..0f505c0d
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-or.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-ori.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-ori.elf
new file mode 100644
index 00000000..eb13ca2d
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-ori.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sb.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sb.elf
new file mode 100644
index 00000000..f51313b3
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-sb.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sh.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sh.elf
new file mode 100644
index 00000000..5d8c2441
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-sh.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-simple.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-simple.elf
new file mode 100644
index 00000000..5880eade
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-simple.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sll.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sll.elf
new file mode 100644
index 00000000..eb8029fc
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-sll.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-slli.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-slli.elf
new file mode 100644
index 00000000..fdaf7c23
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-slli.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-slt.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-slt.elf
new file mode 100644
index 00000000..844410a0
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-slt.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-slti.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-slti.elf
new file mode 100644
index 00000000..faccd513
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-slti.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sltiu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sltiu.elf
new file mode 100644
index 00000000..ada45e2a
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-sltiu.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sltu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sltu.elf
new file mode 100644
index 00000000..893aeb40
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-sltu.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sra.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sra.elf
new file mode 100644
index 00000000..ab4e4fbb
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-sra.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-srai.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-srai.elf
new file mode 100644
index 00000000..9a21c350
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-srai.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-srl.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-srl.elf
new file mode 100644
index 00000000..996dc3bf
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-srl.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-srli.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-srli.elf
new file mode 100644
index 00000000..19c59278
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-srli.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sub.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sub.elf
new file mode 100644
index 00000000..90ed5543
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-sub.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sw.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sw.elf
new file mode 100644
index 00000000..eb1ae2b9
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-sw.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-xor.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-xor.elf
new file mode 100644
index 00000000..1fcbf5b8
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-xor.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-xori.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-xori.elf
new file mode 100644
index 00000000..34f87171
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32ui-p-xori.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-div.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-div.elf
new file mode 100644
index 00000000..121c055e
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32um-p-div.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-divu.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-divu.elf
new file mode 100644
index 00000000..0c3335f4
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32um-p-divu.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-mul.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-mul.elf
new file mode 100644
index 00000000..75eebf3e
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32um-p-mul.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-mulh.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-mulh.elf
new file mode 100644
index 00000000..38e8ca72
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32um-p-mulh.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-mulhsu.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-mulhsu.elf
new file mode 100644
index 00000000..48f64a14
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32um-p-mulhsu.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-mulhu.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-mulhu.elf
new file mode 100644
index 00000000..5010a3de
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32um-p-mulhu.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-rem.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-rem.elf
new file mode 100644
index 00000000..605e403a
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32um-p-rem.elf differ
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-remu.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-remu.elf
new file mode 100644
index 00000000..6814ffa3
Binary files /dev/null and b/examples/RISCV-32-Sail-Validation/rv32um-p-remu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/list.json b/examples/RISCV-64-Sail-Validation/list.json
new file mode 100644
index 00000000..831ac9e7
--- /dev/null
+++ b/examples/RISCV-64-Sail-Validation/list.json
@@ -0,0 +1,490 @@
+[
+ {
+ "name": "rv64mi-p-access.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64mi-p-access.elf"
+ },
+ {
+ "name": "rv64mi-p-breakpoint.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64mi-p-breakpoint.elf"
+ },
+ {
+ "name": "rv64mi-p-csr.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64mi-p-csr.elf"
+ },
+ {
+ "name": "rv64mi-p-illegal.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64mi-p-illegal.elf"
+ },
+ {
+ "name": "rv64mi-p-ma_addr.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64mi-p-ma_addr.elf"
+ },
+ {
+ "name": "rv64mi-p-ma_fetch.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64mi-p-ma_fetch.elf"
+ },
+ {
+ "name": "rv64mi-p-mcsr.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64mi-p-mcsr.elf"
+ },
+ {
+ "name": "rv64mi-p-sbreak.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64mi-p-sbreak.elf"
+ },
+ {
+ "name": "rv64mi-p-scall.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64mi-p-scall.elf"
+ },
+ {
+ "name": "rv64si-p-csr.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64si-p-csr.elf"
+ },
+ {
+ "name": "rv64si-p-dirty.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64si-p-dirty.elf"
+ },
+ {
+ "name": "rv64si-p-ma_fetch.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64si-p-ma_fetch.elf"
+ },
+ {
+ "name": "rv64si-p-sbreak.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64si-p-sbreak.elf"
+ },
+ {
+ "name": "rv64si-p-scall.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64si-p-scall.elf"
+ },
+ {
+ "name": "rv64si-p-wfi.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64si-p-wfi.elf"
+ },
+ {
+ "name": "rv64ua-p-amoadd_d.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_d.elf"
+ },
+ {
+ "name": "rv64ua-p-amoadd_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_w.elf"
+ },
+ {
+ "name": "rv64ua-p-amoand_d.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_d.elf"
+ },
+ {
+ "name": "rv64ua-p-amoand_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_w.elf"
+ },
+ {
+ "name": "rv64ua-p-amomax_d.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_d.elf"
+ },
+ {
+ "name": "rv64ua-p-amomaxu_d.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_d.elf"
+ },
+ {
+ "name": "rv64ua-p-amomaxu_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_w.elf"
+ },
+ {
+ "name": "rv64ua-p-amomax_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_w.elf"
+ },
+ {
+ "name": "rv64ua-p-amomin_d.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_d.elf"
+ },
+ {
+ "name": "rv64ua-p-amominu_d.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_d.elf"
+ },
+ {
+ "name": "rv64ua-p-amominu_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_w.elf"
+ },
+ {
+ "name": "rv64ua-p-amomin_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_w.elf"
+ },
+ {
+ "name": "rv64ua-p-amoor_d.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_d.elf"
+ },
+ {
+ "name": "rv64ua-p-amoor_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_w.elf"
+ },
+ {
+ "name": "rv64ua-p-amoswap_d.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_d.elf"
+ },
+ {
+ "name": "rv64ua-p-amoswap_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_w.elf"
+ },
+ {
+ "name": "rv64ua-p-amoxor_d.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_d.elf"
+ },
+ {
+ "name": "rv64ua-p-amoxor_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_w.elf"
+ },
+ {
+ "name": "rv64ua-p-lrsc.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ua-p-lrsc.elf"
+ },
+ {
+ "name": "rv64uc-p-rvc.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uc-p-rvc.elf"
+ },
+ {
+ "name": "rv64ud-p-fadd.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-fadd.elf"
+ },
+ {
+ "name": "rv64ud-p-fclass.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-fclass.elf"
+ },
+ {
+ "name": "rv64ud-p-fcmp.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-fcmp.elf"
+ },
+ {
+ "name": "rv64ud-p-fcvt.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt.elf"
+ },
+ {
+ "name": "rv64ud-p-fcvt_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt_w.elf"
+ },
+ {
+ "name": "rv64ud-p-fdiv.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-fdiv.elf"
+ },
+ {
+ "name": "rv64ud-p-fmadd.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-fmadd.elf"
+ },
+ {
+ "name": "rv64ud-p-fmin.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-fmin.elf"
+ },
+ {
+ "name": "rv64ud-p-ldst.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-ldst.elf"
+ },
+ {
+ "name": "rv64ud-p-recoding.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-recoding.elf"
+ },
+ {
+ "name": "rv64ud-p-structural.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-structural.elf"
+ },
+ {
+ "name": "rv64uf-p-fadd.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-fadd.elf"
+ },
+ {
+ "name": "rv64uf-p-fclass.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-fclass.elf"
+ },
+ {
+ "name": "rv64ud-p-move.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ud-p-move.elf"
+ },
+ {
+ "name": "rv64uf-p-fcmp.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-fcmp.elf"
+ },
+ {
+ "name": "rv64uf-p-fcvt.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt.elf"
+ },
+ {
+ "name": "rv64uf-p-fcvt_w.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt_w.elf"
+ },
+ {
+ "name": "rv64uf-p-fdiv.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-fdiv.elf"
+ },
+ {
+ "name": "rv64uf-p-fmadd.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-fmadd.elf"
+ },
+ {
+ "name": "rv64uf-p-fmin.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-fmin.elf"
+ },
+ {
+ "name": "rv64uf-p-ldst.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-ldst.elf"
+ },
+ {
+ "name": "rv64uf-p-move.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-move.elf"
+ },
+ {
+ "name": "rv64uf-p-recoding.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64uf-p-recoding.elf"
+ },
+ {
+ "name": "rv64ui-p-add.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-add.elf"
+ },
+ {
+ "name": "rv64ui-p-addi.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-addi.elf"
+ },
+ {
+ "name": "rv64ui-p-addiw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-addiw.elf"
+ },
+ {
+ "name": "rv64ui-p-addw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-addw.elf"
+ },
+ {
+ "name": "rv64ui-p-and.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-and.elf"
+ },
+ {
+ "name": "rv64ui-p-andi.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-andi.elf"
+ },
+ {
+ "name": "rv64ui-p-auipc.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-auipc.elf"
+ },
+ {
+ "name": "rv64ui-p-beq.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-beq.elf"
+ },
+ {
+ "name": "rv64ui-p-bge.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-bge.elf"
+ },
+ {
+ "name": "rv64ui-p-bgeu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-bgeu.elf"
+ },
+ {
+ "name": "rv64ui-p-blt.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-blt.elf"
+ },
+ {
+ "name": "rv64ui-p-bltu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-bltu.elf"
+ },
+ {
+ "name": "rv64ui-p-bne.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-bne.elf"
+ },
+ {
+ "name": "rv64ui-p-fence_i.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-fence_i.elf"
+ },
+ {
+ "name": "rv64ui-p-jal.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-jal.elf"
+ },
+ {
+ "name": "rv64ui-p-jalr.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-jalr.elf"
+ },
+ {
+ "name": "rv64ui-p-lb.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-lb.elf"
+ },
+ {
+ "name": "rv64ui-p-lbu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-lbu.elf"
+ },
+ {
+ "name": "rv64ui-p-ld.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-ld.elf"
+ },
+ {
+ "name": "rv64ui-p-lh.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-lh.elf"
+ },
+ {
+ "name": "rv64ui-p-lhu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-lhu.elf"
+ },
+ {
+ "name": "rv64ui-p-lui.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-lui.elf"
+ },
+ {
+ "name": "rv64ui-p-lw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-lw.elf"
+ },
+ {
+ "name": "rv64ui-p-lwu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-lwu.elf"
+ },
+ {
+ "name": "rv64ui-p-or.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-or.elf"
+ },
+ {
+ "name": "rv64ui-p-ori.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-ori.elf"
+ },
+ {
+ "name": "rv64ui-p-sb.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sb.elf"
+ },
+ {
+ "name": "rv64ui-p-sd.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sd.elf"
+ },
+ {
+ "name": "rv64ui-p-sh.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sh.elf"
+ },
+ {
+ "name": "rv64ui-p-simple.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-simple.elf"
+ },
+ {
+ "name": "rv64ui-p-sll.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sll.elf"
+ },
+ {
+ "name": "rv64ui-p-slli.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-slli.elf"
+ },
+ {
+ "name": "rv64ui-p-slliw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-slliw.elf"
+ },
+ {
+ "name": "rv64ui-p-sllw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sllw.elf"
+ },
+ {
+ "name": "rv64ui-p-slt.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-slt.elf"
+ },
+ {
+ "name": "rv64ui-p-slti.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-slti.elf"
+ },
+ {
+ "name": "rv64ui-p-sltiu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sltiu.elf"
+ },
+ {
+ "name": "rv64ui-p-sltu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sltu.elf"
+ },
+ {
+ "name": "rv64ui-p-sra.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sra.elf"
+ },
+ {
+ "name": "rv64ui-p-srai.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-srai.elf"
+ },
+ {
+ "name": "rv64ui-p-sraiw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sraiw.elf"
+ },
+ {
+ "name": "rv64ui-p-sraw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sraw.elf"
+ },
+ {
+ "name": "rv64ui-p-srl.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-srl.elf"
+ },
+ {
+ "name": "rv64ui-p-srli.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-srli.elf"
+ },
+ {
+ "name": "rv64ui-p-srliw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-srliw.elf"
+ },
+ {
+ "name": "rv64ui-p-srlw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-srlw.elf"
+ },
+ {
+ "name": "rv64ui-p-sub.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sub.elf"
+ },
+ {
+ "name": "rv64ui-p-subw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-subw.elf"
+ },
+ {
+ "name": "rv64ui-p-sw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-sw.elf"
+ },
+ {
+ "name": "rv64ui-p-xor.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-xor.elf"
+ },
+ {
+ "name": "rv64ui-p-xori.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64ui-p-xori.elf"
+ },
+ {
+ "name": "rv64um-p-div.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-div.elf"
+ },
+ {
+ "name": "rv64um-p-divu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-divu.elf"
+ },
+ {
+ "name": "rv64um-p-divuw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-divuw.elf"
+ },
+ {
+ "name": "rv64um-p-divw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-divw.elf"
+ },
+ {
+ "name": "rv64um-p-mul.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-mul.elf"
+ },
+ {
+ "name": "rv64um-p-mulh.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-mulh.elf"
+ },
+ {
+ "name": "rv64um-p-mulhsu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-mulhsu.elf"
+ },
+ {
+ "name": "rv64um-p-mulhu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-mulhu.elf"
+ },
+ {
+ "name": "rv64um-p-mulw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-mulw.elf"
+ },
+ {
+ "name": "rv64um-p-rem.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-rem.elf"
+ },
+ {
+ "name": "rv64um-p-remu.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-remu.elf"
+ },
+ {
+ "name": "rv64um-p-remuw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-remuw.elf"
+ },
+ {
+ "name": "rv64um-p-remw.elf",
+ "url": "examples/RISCV-64-Sail-Validation/rv64um-p-remw.elf"
+ }
+]
\ No newline at end of file
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-access.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-access.elf
new file mode 100755
index 00000000..6335b6c0
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64mi-p-access.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-breakpoint.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-breakpoint.elf
new file mode 100644
index 00000000..571bfd71
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64mi-p-breakpoint.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-csr.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-csr.elf
new file mode 100644
index 00000000..be079225
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64mi-p-csr.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-illegal.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-illegal.elf
new file mode 100644
index 00000000..d3010492
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64mi-p-illegal.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_addr.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_addr.elf
new file mode 100644
index 00000000..e5eadd5c
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_addr.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_fetch.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_fetch.elf
new file mode 100644
index 00000000..4d66e690
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_fetch.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-mcsr.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-mcsr.elf
new file mode 100644
index 00000000..796100bc
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64mi-p-mcsr.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-sbreak.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-sbreak.elf
new file mode 100755
index 00000000..4bcd37ce
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64mi-p-sbreak.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-scall.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-scall.elf
new file mode 100644
index 00000000..f82dea52
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64mi-p-scall.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-csr.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-csr.elf
new file mode 100644
index 00000000..a6290ef6
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64si-p-csr.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-dirty.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-dirty.elf
new file mode 100644
index 00000000..a15a0332
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64si-p-dirty.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-ma_fetch.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-ma_fetch.elf
new file mode 100644
index 00000000..02155e5a
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64si-p-ma_fetch.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-sbreak.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-sbreak.elf
new file mode 100755
index 00000000..cf0a8ca3
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64si-p-sbreak.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-scall.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-scall.elf
new file mode 100644
index 00000000..5eb47e1f
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64si-p-scall.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-wfi.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-wfi.elf
new file mode 100644
index 00000000..46e1115b
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64si-p-wfi.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_d.elf
new file mode 100644
index 00000000..359f6047
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_d.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_w.elf
new file mode 100644
index 00000000..a76f6044
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_d.elf
new file mode 100644
index 00000000..091e7f71
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_d.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_w.elf
new file mode 100644
index 00000000..edf0588f
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_d.elf
new file mode 100644
index 00000000..c8867f8b
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_d.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_w.elf
new file mode 100644
index 00000000..e7d9ea5c
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_d.elf
new file mode 100644
index 00000000..dab40262
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_d.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_w.elf
new file mode 100644
index 00000000..6486fa46
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_d.elf
new file mode 100644
index 00000000..425c72ce
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_d.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_w.elf
new file mode 100644
index 00000000..2cdb17e7
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_d.elf
new file mode 100644
index 00000000..20d1b6fd
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_d.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_w.elf
new file mode 100644
index 00000000..6a73fc4e
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_d.elf
new file mode 100644
index 00000000..71a32159
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_d.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_w.elf
new file mode 100644
index 00000000..33196ad2
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_d.elf
new file mode 100644
index 00000000..2b2200ca
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_d.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_w.elf
new file mode 100644
index 00000000..39ee63f3
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_d.elf
new file mode 100644
index 00000000..cb45e313
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_d.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_w.elf
new file mode 100644
index 00000000..c2d3412c
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-lrsc.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-lrsc.elf
new file mode 100644
index 00000000..c443cf22
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ua-p-lrsc.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uc-p-rvc.elf b/examples/RISCV-64-Sail-Validation/rv64uc-p-rvc.elf
new file mode 100644
index 00000000..ee821eba
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uc-p-rvc.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fadd.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fadd.elf
new file mode 100644
index 00000000..eaa35c67
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-fadd.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fclass.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fclass.elf
new file mode 100644
index 00000000..7c23d499
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-fclass.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fcmp.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fcmp.elf
new file mode 100644
index 00000000..4ae6c9be
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-fcmp.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt.elf
new file mode 100644
index 00000000..995bc818
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt_w.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt_w.elf
new file mode 100644
index 00000000..4db28d5f
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fdiv.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fdiv.elf
new file mode 100644
index 00000000..d62c776c
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-fdiv.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fmadd.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fmadd.elf
new file mode 100644
index 00000000..e1b977b3
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-fmadd.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fmin.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fmin.elf
new file mode 100644
index 00000000..34c1ccbc
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-fmin.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-ldst.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-ldst.elf
new file mode 100755
index 00000000..42e53302
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-ldst.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-move.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-move.elf
new file mode 100755
index 00000000..2f32db96
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-move.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-recoding.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-recoding.elf
new file mode 100755
index 00000000..3fb62d7b
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-recoding.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-structural.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-structural.elf
new file mode 100755
index 00000000..0331e2bf
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ud-p-structural.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fadd.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fadd.elf
new file mode 100644
index 00000000..e4c4a5b7
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-fadd.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fclass.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fclass.elf
new file mode 100644
index 00000000..eae8b278
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-fclass.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fcmp.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fcmp.elf
new file mode 100644
index 00000000..42039b2c
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-fcmp.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt.elf
new file mode 100644
index 00000000..bfcbcf05
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt_w.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt_w.elf
new file mode 100644
index 00000000..2994eb4e
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt_w.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fdiv.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fdiv.elf
new file mode 100644
index 00000000..3501db35
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-fdiv.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fmadd.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fmadd.elf
new file mode 100644
index 00000000..bc5121e9
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-fmadd.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fmin.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fmin.elf
new file mode 100644
index 00000000..b5548fbb
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-fmin.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-ldst.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-ldst.elf
new file mode 100755
index 00000000..d0800236
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-ldst.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-move.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-move.elf
new file mode 100755
index 00000000..5a16f631
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-move.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-recoding.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-recoding.elf
new file mode 100755
index 00000000..b8f54ed8
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64uf-p-recoding.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-add.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-add.elf
new file mode 100644
index 00000000..74330e9e
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-add.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-addi.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-addi.elf
new file mode 100644
index 00000000..d83a9a79
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-addi.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-addiw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-addiw.elf
new file mode 100644
index 00000000..1556eea4
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-addiw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-addw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-addw.elf
new file mode 100644
index 00000000..79496314
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-addw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-and.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-and.elf
new file mode 100644
index 00000000..9dda5d19
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-and.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-andi.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-andi.elf
new file mode 100644
index 00000000..39d71d32
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-andi.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-auipc.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-auipc.elf
new file mode 100644
index 00000000..cf2211ce
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-auipc.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-beq.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-beq.elf
new file mode 100644
index 00000000..5b898658
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-beq.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-bge.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-bge.elf
new file mode 100644
index 00000000..972d7fab
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-bge.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-bgeu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-bgeu.elf
new file mode 100644
index 00000000..cd7e7e34
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-bgeu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-blt.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-blt.elf
new file mode 100644
index 00000000..e3676a33
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-blt.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-bltu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-bltu.elf
new file mode 100644
index 00000000..e4e6077e
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-bltu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-bne.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-bne.elf
new file mode 100644
index 00000000..d28d9aae
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-bne.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-fence_i.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-fence_i.elf
new file mode 100644
index 00000000..682802e0
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-fence_i.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-jal.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-jal.elf
new file mode 100644
index 00000000..8250b755
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-jal.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-jalr.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-jalr.elf
new file mode 100644
index 00000000..4d111a58
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-jalr.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lb.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lb.elf
new file mode 100644
index 00000000..13970acc
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-lb.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lbu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lbu.elf
new file mode 100644
index 00000000..b68b1991
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-lbu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-ld.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-ld.elf
new file mode 100644
index 00000000..b4e65961
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-ld.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lh.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lh.elf
new file mode 100644
index 00000000..5d6b965e
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-lh.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lhu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lhu.elf
new file mode 100644
index 00000000..1b2550d9
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-lhu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lui.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lui.elf
new file mode 100644
index 00000000..300ef0d2
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-lui.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lw.elf
new file mode 100644
index 00000000..6c77ab8c
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-lw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lwu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lwu.elf
new file mode 100644
index 00000000..b920704c
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-lwu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-or.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-or.elf
new file mode 100644
index 00000000..b3772ca7
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-or.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-ori.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-ori.elf
new file mode 100644
index 00000000..d3a6b6d2
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-ori.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sb.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sb.elf
new file mode 100644
index 00000000..20fdd3c0
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sb.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sd.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sd.elf
new file mode 100644
index 00000000..d3e68eae
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sd.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sh.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sh.elf
new file mode 100644
index 00000000..4a38a063
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sh.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-simple.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-simple.elf
new file mode 100644
index 00000000..68457c21
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-simple.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sll.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sll.elf
new file mode 100644
index 00000000..0c615ca2
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sll.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-slli.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-slli.elf
new file mode 100644
index 00000000..c5f99f54
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-slli.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-slliw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-slliw.elf
new file mode 100644
index 00000000..cb8909f4
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-slliw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sllw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sllw.elf
new file mode 100644
index 00000000..e839d1b5
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sllw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-slt.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-slt.elf
new file mode 100644
index 00000000..1feb7df6
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-slt.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-slti.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-slti.elf
new file mode 100644
index 00000000..681c9631
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-slti.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sltiu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sltiu.elf
new file mode 100644
index 00000000..a52072b1
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sltiu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sltu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sltu.elf
new file mode 100644
index 00000000..16264ccd
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sltu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sra.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sra.elf
new file mode 100644
index 00000000..fc9a1d97
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sra.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srai.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srai.elf
new file mode 100644
index 00000000..8efee581
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-srai.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sraiw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sraiw.elf
new file mode 100644
index 00000000..d3a9099b
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sraiw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sraw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sraw.elf
new file mode 100644
index 00000000..2b83afc3
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sraw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srl.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srl.elf
new file mode 100644
index 00000000..1ca26294
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-srl.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srli.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srli.elf
new file mode 100644
index 00000000..a8dd4e3f
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-srli.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srliw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srliw.elf
new file mode 100644
index 00000000..452617c0
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-srliw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srlw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srlw.elf
new file mode 100644
index 00000000..f1e87436
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-srlw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sub.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sub.elf
new file mode 100644
index 00000000..d8676851
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sub.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-subw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-subw.elf
new file mode 100644
index 00000000..d6c7c3b1
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-subw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sw.elf
new file mode 100644
index 00000000..6ca080c5
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-sw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-xor.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-xor.elf
new file mode 100644
index 00000000..7403f053
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-xor.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-xori.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-xori.elf
new file mode 100644
index 00000000..f759bbaf
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64ui-p-xori.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-div.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-div.elf
new file mode 100644
index 00000000..c33b9549
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-div.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-divu.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-divu.elf
new file mode 100644
index 00000000..6c7c9928
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-divu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-divuw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-divuw.elf
new file mode 100644
index 00000000..d28d92d3
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-divuw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-divw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-divw.elf
new file mode 100644
index 00000000..62998ebe
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-divw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mul.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mul.elf
new file mode 100644
index 00000000..7db8e67f
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-mul.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mulh.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mulh.elf
new file mode 100644
index 00000000..9a7009a0
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-mulh.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mulhsu.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mulhsu.elf
new file mode 100644
index 00000000..eb825f7a
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-mulhsu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mulhu.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mulhu.elf
new file mode 100644
index 00000000..b398098e
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-mulhu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mulw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mulw.elf
new file mode 100644
index 00000000..86519609
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-mulw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-rem.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-rem.elf
new file mode 100644
index 00000000..45a427e3
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-rem.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-remu.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-remu.elf
new file mode 100644
index 00000000..ce63b5f6
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-remu.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-remuw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-remuw.elf
new file mode 100644
index 00000000..3e1fea53
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-remuw.elf differ
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-remw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-remw.elf
new file mode 100644
index 00000000..e079595c
Binary files /dev/null and b/examples/RISCV-64-Sail-Validation/rv64um-p-remw.elf differ
diff --git a/src/core/events.mts b/src/core/events.mts
index b98f31e4..02be7245 100644
--- a/src/core/events.mts
+++ b/src/core/events.mts
@@ -39,6 +39,7 @@ export const CoreEventTypes = {
ARDUINO_PIN_CHANGED: "arduino-pin-write",
ARDUINO_RESET: "arduino-reset",
ARDUINO_PIN_INTERRUPT: "arduino-pin-interrupt",
+ VALIDATION_UPDATE: "update-validation",
} as const;
/**
diff --git a/src/core/executor/sailSimRV/sailExecutor.mjs b/src/core/executor/sailSimRV/sailExecutor.mjs
index ed6208cc..7d9b9647 100644
--- a/src/core/executor/sailSimRV/sailExecutor.mjs
+++ b/src/core/executor/sailSimRV/sailExecutor.mjs
@@ -3,7 +3,150 @@ import sail32sim from "./wasm/riscv_sim_RV32.js"
import sail64sim from "./wasm/riscv_sim_RV64.js"
import sail32vdsim from "./wasm/riscv_sim_RV32vd.js"
import { vectoren, doubleen } from "../../assembler/sailAssembler/web/CNAssambler.mjs";
+import { coreEvents } from "../../events.mts";
+
export var sailexec;
+var programs = [];
+
+async function cargarProgramas32(jsonPath) {
+
+ const response = await fetch(jsonPath);
+ const lista = await response.json();
+
+ const programas = await Promise.all(
+ lista.map(async entry => {
+
+ const binResponse = await fetch(entry.url);
+ const buffer = await binResponse.arrayBuffer();
+
+ const programa = {
+ name: entry.name,
+ binary: new Uint8Array(buffer)
+ };
+
+ if ("doubleen" in entry) programa.doubleen = entry.doubleen;
+ if ("vectoren" in entry) programa.vectoren = entry.vectoren;
+
+ return programa;
+ })
+ );
+
+ return programas;
+}
+
+async function cargarProgramas64(jsonPath){
+
+ const response = await fetch(jsonPath);
+ const lista = await response.json();
+
+ const programas = await Promise.all(
+ lista.map(async entry => {
+
+ const binResponse = await fetch(entry.url);
+ const buffer = await binResponse.arrayBuffer();
+
+ const programa = {
+ name: entry.name,
+ binary: new Uint8Array(buffer)
+ };
+
+ return programa;
+ })
+ );
+
+ return programas;
+}
+
+export async function SailTest32(){
+ // Reset de las variables test
+ document.app.$data.passed_test = 0;
+ document.app.$data.failed_test = 0;
+ document.app.$data.testing = true;
+ document.app.$data.c_kernel = false;
+ if (programs.length === 0)
+ programs = await cargarProgramas32("../../../../examples/RISCV-32-Sail-Validation/list.json");
+
+ for (let index = 0; index < programs.length; index++) {
+
+ document.app.$data.execution_mode_run = -1;
+ const element = programs[index];
+ let depsLeft = Infinity;
+ if (element.vectoren && element.doubleen) {
+ sailexec = await sail32vdsim({
+ noInitialRun: true,
+ // print: (t) => console.log('[sim32]', t),
+ // printErr: (t) => console.warn('[sim32:err]', t),
+ // onAbort: (t) => console.error("[sim32:abort]", t),
+ monitorRunDependencies(left) {
+ depsLeft = left;
+ console.log("[sim32] deps pending:", left);
+ },
+ });
+ } else {
+ sailexec = await sail32sim({
+ noInitialRun: true,
+ // print: (t) => console.log('[sim32]', t),
+ // printErr: (t) => console.warn('[sim32:err]', t),
+ // onAbort: (t) => console.error("[sim32:abort]", t),
+ monitorRunDependencies(left) {
+ depsLeft = left;
+ console.log("[sim32] deps pending:", left);
+ },
+ });
+ }
+
+ await new Promise((resolve) => {
+ const check = () => {
+ if (depsLeft === 0) resolve();
+ else setTimeout(check, 100);
+ };
+ check();
+ });
+ document.app.$data.execution_mode_run = 0;
+ sailexec.run([element.binary, "--entry-address", "0x80000000", "--cache-pol", "1", "-p", "output.elf"]);
+ coreEvents.emit("update-validation");
+
+
+ }
+
+ document.app.$data.testing = false;
+
+}
+export async function SailTest64(){
+ var filed_tests = [];
+ document.app.$data.passed_test = 0;
+ document.app.$data.failed_test = 0;
+ document.app.$data.testing = true;
+ document.app.$data.c_kernel = false;
+ if (programs.length === 0)
+ programs = await cargarProgramas64("../../../../examples/RISCV-64-Sail-Validation/list.json");
+
+ for (let index = 0; index < programs.length; index++) {
+
+ document.app.$data.execution_mode_run = -1;
+ const element = programs[index];
+ let depsLeft = Infinity;
+ sailexec = await sail64sim({
+ noInitialRun: true,
+ monitorRunDependencies(left) {
+ depsLeft = left;
+ console.log("[sim64] deps pending:", left);
+ },
+ });
+ await new Promise((resolve) => {
+ const check = () => {
+ if (depsLeft === 0) resolve();
+ else setTimeout(check, 100);
+ };
+ check();
+ });
+ document.app.$data.execution_mode_run = 0;
+ sailexec.run([element.binary, "--entry-address", "0x80000000", "--cache-pol", "1", "-p", "output.elf"]);
+ coreEvents.emit("update-validation");
+ }
+
+ document.app.$data.testing = false;
+}
export async function SailExecute(binary, flags){
let depsLeft = Infinity;
if (architecture.config.name === "SRV32") {
@@ -64,7 +207,6 @@ export async function SailExecute(binary, flags){
// Once it is initialized, lets run the program
// document.app.$data.execution_mode_run = 0;
- console.log(flags);
sailexec.run([binary, ...flags]);
diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js
index 47887970..d801f29b 100644
--- a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js
+++ b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js
@@ -16,7 +16,7 @@ var Module = (() => {
var insn_number;
return function (Module) {
- document.app.$data.is_breakpoint = instructions[0].Break;
+ document.app.$data.is_breakpoint = (instructions.length !== 0) ? instructions[0].Break : false;
var pc_sail = crex_findReg_bytag("program_counter");
var pc_min = architecture.memory_layout.text.start;
var pc_max = architecture.memory_layout.text.end;
@@ -1194,8 +1194,7 @@ var Module = (() => {
console.warn(message);
}
- var out = Module["print"] /*|| console.log.bind(console)*/;
- // var out = console.log.bind(console);
+ var out = (document.app.$data.testing === true ) ? console.log.bind(console) : Module["print"];
var err = Module["printErr"] /*|| console.warn.bind(console)*/;
Object.assign(Module, moduleOverrides);
@@ -7824,27 +7823,33 @@ var Module = (() => {
}
if (keepRuntimeAlive()) {
if (!implicit) {
-
- for (let i = 0; i < instructions.length; i++){
- instructions[i]._rowVariant = '';
- }
- status.run_program = -1; // program finished
- if (statusw !== 0){
- coreEvents.emit("executor-buttons-update", {
- reset_disable: false,
- instruction_disable: true,
- run_disable: true,
- stop_disable: false,
- });
- show_notification("Your program has finished with errors.", "danger");
+ if (!document.app.$data.testing) {
+ for (let i = 0; i < instructions.length; i++){
+ instructions[i]._rowVariant = '';
+ }
+ status.run_program = -1; // program finished
+ if (statusw !== 0){
+ coreEvents.emit("executor-buttons-update", {
+ reset_disable: false,
+ instruction_disable: true,
+ run_disable: true,
+ stop_disable: false,
+ });
+ show_notification("Your program has finished with errors.", "danger");
+ } else {
+ coreEvents.emit("executor-buttons-update", {
+ reset_disable: false,
+ instruction_disable: false,
+ run_disable: false,
+ stop_disable: true,
+ isFinished: true,
+ });
+ }
} else {
- coreEvents.emit("executor-buttons-update", {
- reset_disable: false,
- instruction_disable: false,
- run_disable: false,
- stop_disable: true,
- isFinished: true,
- });
+ if (statusw === 0)
+ document.app.$data.passed_test += 1;
+ else
+ document.app.$data.failed_test += 1;
}
var msg =
"program exited (with status: " +
diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.wasm b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.wasm
index 23c08016..d430dc84 100755
Binary files a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.wasm and b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.wasm differ
diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js
index b119bc7b..650cf91e 100644
--- a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js
+++ b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js
@@ -16,7 +16,8 @@ var Module = (() => {
var _scriptName = import.meta.url;
var insn_number;
- return async function (moduleArg = {}) {document.app.$data.is_breakpoint = instructions[0].Break;
+ return async function (moduleArg = {}) {
+ document.app.$data.is_breakpoint = (instructions.length !== 0) ? instructions[0].Break : false;
var pc_sail = crex_findReg_bytag("program_counter");
var pc_min = architecture.memory_layout.text.start;
var pc_max = architecture.memory_layout.text.end;
@@ -957,8 +958,7 @@ var Module = (() => {
console.warn(message);
}
- var out = Module["print"] /*|| console.log.bind(console)*/;
- // var out = console.log.bind(console);
+ var out = (document.app.$data.testing === true ) ? console.log.bind(console) : Module["print"];
var err = Module["printErr"] /*|| console.warn.bind(console)*/;
@@ -4290,26 +4290,33 @@ var Module = (() => {
EXITSTATUS = statusw;
checkUnflushedContent();
if (keepRuntimeAlive() && !implicit) {
- for (let i = 0; i < instructions.length; i++){
- instructions[i]._rowVariant = '';
- }
- status.run_program = -1; // program finished
- if (statusw !== 0){
- coreEvents.emit("executor-buttons-update", {
- reset_disable: false,
- instruction_disable: true,
- run_disable: true,
- stop_disable: false,
- });
- show_notification("Your program has finished with errors.", "danger");
+ if (!document.app.$data.testing){
+ for (let i = 0; i < instructions.length; i++){
+ instructions[i]._rowVariant = '';
+ }
+ status.run_program = -1; // program finished
+ if (statusw !== 0){
+ coreEvents.emit("executor-buttons-update", {
+ reset_disable: false,
+ instruction_disable: true,
+ run_disable: true,
+ stop_disable: false,
+ });
+ show_notification("Your program has finished with errors.", "danger");
+ } else {
+ coreEvents.emit("executor-buttons-update", {
+ reset_disable: false,
+ instruction_disable: false,
+ run_disable: false,
+ stop_disable: true,
+ isFinished: true,
+ });
+ }
} else {
- coreEvents.emit("executor-buttons-update", {
- reset_disable: false,
- instruction_disable: false,
- run_disable: false,
- stop_disable: true,
- isFinished: true,
- });
+ if (statusw === 0)
+ document.app.$data.passed_test += 1;
+ else
+ document.app.$data.failed_test += 1;
}
var msg = `program exited (with status: ${statusw}), but keepRuntimeAlive() is set (counter=${runtimeKeepaliveCounter}) due to an async operation, so halting execution but not exiting the runtime or preventing further async execution (you can use emscripten_force_exit, if you want to force a true shutdown)`;
readyPromiseReject(msg);
diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.wasm b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.wasm
index b9574ecf..58499326 100755
Binary files a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.wasm and b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.wasm differ
diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js b/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js
index 1ceffd49..1ba5bacf 100644
--- a/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js
+++ b/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js
@@ -16,7 +16,7 @@ var Module = (() => {
var insn_number;
return async function (moduleArg = {}) {
- document.app.$data.is_breakpoint = instructions[0].Break;
+ document.app.$data.is_breakpoint = (instructions.length !== 0) ? instructions[0].Break : false;
var pc_sail = crex_findReg_bytag("program_counter");
var pc_min = architecture.memory_layout.text.start;
var pc_max = architecture.memory_layout.text.end;
@@ -1009,7 +1009,7 @@ var Module = (() => {
}
- var out = Module["print"] /*|| console.log.bind(console)*/;
+ var out = (document.app.$data.testing === true ) ? console.log.bind(console) : Module["print"];
var err = Module["printErr"] /*|| console.error.bind(console)*/;
@@ -4341,27 +4341,33 @@ var Module = (() => {
EXITSTATUS = statusw;
checkUnflushedContent();
if (keepRuntimeAlive() && !implicit) {
-
- for (let i = 0; i < instructions.length; i++){
- instructions[i]._rowVariant = '';
- }
- status.run_program = -1; // program finished
- if (statusw !== 0){
- coreEvents.emit("executor-buttons-update", {
- reset_disable: false,
- instruction_disable: true,
- run_disable: true,
- stop_disable: false,
- });
- show_notification("Your program has finished with errors.", "danger");
+ if (!document.app.$data.testing) {
+ for (let i = 0; i < instructions.length; i++){
+ instructions[i]._rowVariant = '';
+ }
+ status.run_program = -1; // program finished
+ if (statusw !== 0){
+ coreEvents.emit("executor-buttons-update", {
+ reset_disable: false,
+ instruction_disable: true,
+ run_disable: true,
+ stop_disable: false,
+ });
+ show_notification("Your program has finished with errors.", "danger");
+ } else {
+ coreEvents.emit("executor-buttons-update", {
+ reset_disable: false,
+ instruction_disable: false,
+ run_disable: false,
+ stop_disable: true,
+ isFinished: true,
+ });
+ }
} else {
- coreEvents.emit("executor-buttons-update", {
- reset_disable: false,
- instruction_disable: false,
- run_disable: false,
- stop_disable: true,
- isFinished: true,
- });
+ if (statusw === 0)
+ document.app.$data.passed_test += 1;
+ else
+ document.app.$data.failed_test += 1;
}
var msg = `program exited (with status: ${statusw}), but keepRuntimeAlive() is set (counter=${runtimeKeepaliveCounter}) due to an async operation, so halting execution but not exiting the runtime or preventing further async execution (you can use emscripten_force_exit, if you want to force a true shutdown)`;
readyPromiseReject(msg);
diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.wasm b/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.wasm
index eea7771a..9aa1dd73 100755
Binary files a/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.wasm and b/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.wasm differ
diff --git a/src/web/App.vue b/src/web/App.vue
index adbd361d..60ec9a6b 100644
--- a/src/web/App.vue
+++ b/src/web/App.vue
@@ -354,6 +354,14 @@ export default {
target_port: "",
target_location: "~/creator",
flash_url: "http://localhost:8080",
+
+ /* Validation test */
+ // Stats
+ passed_test: 0,
+ failed_test: 0,
+
+ // Check testing execution
+ testing: false,
};
},
diff --git a/src/web/components/ArchitectureView.vue b/src/web/components/ArchitectureView.vue
index dd07d67a..b051cb08 100644
--- a/src/web/components/ArchitectureView.vue
+++ b/src/web/components/ArchitectureView.vue
@@ -30,6 +30,8 @@ import Instructions from "./architecture/instructions/Instructions.vue";
import Directives from "./architecture/directives/Directives.vue";
import Pseudoinstructions from "./architecture/pseudoinstructions/Pseudoinstructions.vue";
import CacheMemory from "./architecture/cache_memory/CacheMemory.vue";
+import { SailTest32, SailTest64 } from "@/core/executor/sailSimRV/sailExecutor.mjs";
+import { coreEvents } from "@/core/events.mts";
export default defineComponent({
props: {
browser: { type: String, required: true },
@@ -55,6 +57,12 @@ export default defineComponent({
return {
architecture,
activeTab: "instructions",
+ validate: false,
+ showValidationModal: false,
+ running: false,
+ runned: 0,
+ result_test: 0,
+ result_log: ""
};
},
computed: {
@@ -71,6 +79,33 @@ export default defineComponent({
return `# yaml-language-server: $schema=${document.URL.replace(/\/#$/, "/")}schema/architecture.json\n${this.arch_code}`;
},
},
+ methods:{
+ runValidationTest(arch_type: Number){
+ this.runned = 0;
+ this.result_test = 0;
+ this.running = true;
+ this.result_log = "";
+ if (arch_type === 32){
+ SailTest32();
+ } else {
+ SailTest64();
+ }
+ },
+ updateState(){
+ this.result_test = document.app.$data.passed_test;
+ if (this.result_test + document.app.$data.failed_test === ((architecture.config.name === 'SRV32' ? 89 : 122)) ){
+ this.result_log = "Validation completed.
Your architecture passed the " + (this.result_test / (architecture.config.name === 'SRV32' ? 89 : 122)) * 100 + "%
of the validation tests."
+ }
+
+ },
+ },
+ mounted(){
+ coreEvents.on("update-validation", this.updateState);
+ },
+ beforeUnmount() {
+ coreEvents.off("update-validation", this.updateState);
+
+ },
});
@@ -174,6 +209,19 @@ export default defineComponent({
Cache Memory
+
+
+
@@ -222,6 +270,36 @@ export default defineComponent({
:cache_policy="$root.$data.cache_policy"
>
+
+ This validation test runs {{(architecture.config.name === 'SRV32' ? 89 : 122)}} RISC-V programs.
+ These programs are taken from the official RISC-V test repository (riscv-tests), where the correct operation
+ of the full instruction set of the RISC-V specification is verified.
+
+
+
+
+ Run tests
+
+
+
+
+ {{ result_log }}
+
+
+
+
+
+
+
diff --git a/src/web/components/simulator/SimulatorControls.vue b/src/web/components/simulator/SimulatorControls.vue
index 51c2d413..0f8a6e89 100644
--- a/src/web/components/simulator/SimulatorControls.vue
+++ b/src/web/components/simulator/SimulatorControls.vue
@@ -302,7 +302,7 @@ function execute_instruction() {
} else if (document.app.$data.execution_mode_run === -1) {
document.app.$data.execution_mode_run = 1;
status.run_program = 1;
- SailExecute(document.app.$data.binary, ["--entry-address", /*"0x80000000"*/ document.app.$data.entry_elf.toString(16), "--disable-compressed", "--cache-pol", "1", "-p", "output.elf"]);
+ SailExecute(document.app.$data.binary, ["--entry-address", document.app.$data.entry_elf.toString(16), "--cache-pol", "1", "-p", "output.elf"]);
// console.log("Ejecutado");
} else if (document.app.$data.execution_mode_run !== -1 && document.app.$data.execution_mode_run !== 2){
document.app.$data.execution_mode_run = 1;
@@ -413,7 +413,7 @@ function execute_program_packed() {
} else if (document.app.$data.execution_mode_run === -1){
status.run_program = 1;
document.app.$data.execution_mode_run = 0;
- SailExecute(document.app.$data.binary, ["--entry-address", /*"0x80000000"*/ document.app.$data.entry_elf.toString(16), "--disable-compressed", "--cache-pol", "1", "-p", "output.elf"]);
+ SailExecute(document.app.$data.binary, ["--entry-address", document.app.$data.entry_elf.toString(16), "--cache-pol", "1", "-p", "output.elf"]);
} else if (document.app.$data.execution_mode_run !== -1 && document.app.$data.execution_mode_run !== 2){
document.app.$data.execution_mode_run = 0;
sailexec._reanudar_ejecucion(parseInt(0,10));