From 23e2a4dbdad778fb757837367f1b9045e7bbb017 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 9 Jun 2026 15:21:34 +0200 Subject: [PATCH] tests: update test snapshots --- .../RISCV-32-interrupts/example1.s.snap | 109 +++++++++++++----- 1 file changed, 78 insertions(+), 31 deletions(-) diff --git a/tests/arch/__snapshots__/examples/RISCV-32-interrupts/example1.s.snap b/tests/arch/__snapshots__/examples/RISCV-32-interrupts/example1.s.snap index 8fd365f2..614ba7ae 100644 --- a/tests/arch/__snapshots__/examples/RISCV-32-interrupts/example1.s.snap +++ b/tests/arch/__snapshots__/examples/RISCV-32-interrupts/example1.s.snap @@ -2,47 +2,94 @@ export const snapshot = {}; snapshot[`examples/RISCV-32-interrupts/example1.s 1`] = ` { - display: "", + display: "x", error: false, keyboard: "", memory: { - "0": 48, "1": 32, - "10": 226, - "11": 147, - "13": 50, - "14": 144, - "15": 115, - "17": 82, - "18": 144, - "19": 115, - "21": 130, - "22": 226, - "23": 147, - "25": 82, - "26": 144, - "27": 115, - "3": 115, + "10": 162, + "102": 128, + "103": 103, + "11": 131, + "13": 32, + "14": 3, + "15": 23, + "16": 255, + "17": 67, + "18": 3, + "19": 19, + "2": 2, + "2097152": 240, + "2097156": 240, + "2097159": 8, + "21": 3, + "22": 35, + "23": 3, + "25": 162, + "26": 160, + "27": 35, + "29": 176, + "3": 151, "30": 2, - "31": 151, - "32": 254, - "33": 66, - "34": 130, - "35": 147, - "37": 34, - "38": 144, + "31": 147, + "33": 83, + "34": 32, + "35": 35, + "36": 48, + "37": 32, "39": 115, + "41": 50, + "42": 144, "43": 115, - "46": 2, + "45": 130, + "46": 226, "47": 147, - "5": 50, - "50": 128, - "51": 103, - "6": 144, - "7": 115, - "9": 130, + "49": 50, + "5": 66, + "50": 144, + "51": 115, + "53": 82, + "54": 144, + "55": 115, + "57": 130, + "58": 226, + "59": 147, + "6": 130, + "61": 82, + "62": 144, + "63": 115, + "66": 2, + "67": 151, + "68": 252, + "69": 2, + "7": 147, + "70": 130, + "71": 147, + "73": 32, + "74": 3, + "75": 19, + "77": 98, + "78": 146, + "79": 179, + "81": 34, + "82": 144, + "83": 115, + "85": 176, + "86": 8, + "87": 147, + "88": 7, + "89": 128, + "9": 2, + "90": 5, + "91": 19, + "95": 115, + "98": 2, + "99": 147, }, registers: { + "x10,a0": "0x78", + "x17,a7": "0xb", + "x6,t1": "0x2", mie: "0x8", mtime: "0x3", pc: "0xfffffffe",