From dd97593c57175fe774df5db935497cc06c11ad2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Paulo=20Conde=C3=A7a?= Date: Thu, 1 Jun 2023 13:11:56 +0100 Subject: [PATCH 01/29] Update tx_port.h removed extra spaces --- ports_smp/cortex_a75_smp/gnu/inc/tx_port.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h index 019db6eb9..c3e26cbc4 100644 --- a/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h @@ -196,7 +196,7 @@ typedef unsigned long long ALIGN_TYPE; /* Define various constants for the ThreadX ARM port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ -#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ /* Define the clock source for trace event entry time stamp. The following two item are port specific. From 4373af728647cf50101487634d0233f3fd07f56e Mon Sep 17 00:00:00 2001 From: Du Huanpeng Date: Wed, 14 Jun 2023 11:52:15 +0800 Subject: [PATCH 02/29] fix link flag to -mcpu=cortex-a9 Signed-off-by: Du Huanpeng --- .../cortex_a9_smp/gnu/example_build/build_threadx_sample.bat | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat b/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat index 22d0a618b..0e2611181 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat +++ b/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat @@ -1,4 +1,4 @@ -arm-none-eabi-gcc -c -g -I../../../../common_smp/inc -I../inc -mcpu=cortex-a5 sample_threadx.c +arm-none-eabi-gcc -c -g -I../../../../common_smp/inc -I../inc -mcpu=cortex-a9 sample_threadx.c arm-none-eabi-gcc -c -g -mcpu=cortex-a9 startup.S arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_GIC.S arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_SCU.S From 5892fe15b5e03fabf021e33747c07cabb31e1c54 Mon Sep 17 00:00:00 2001 From: Du Huanpeng Date: Wed, 14 Jun 2023 16:38:12 +0800 Subject: [PATCH 03/29] Remove duplicate declaration "invalidateCaches_IS" Signed-off-by: Du Huanpeng --- ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h | 1 - ports_smp/cortex_a5_smp/gnu/example_build/v7.h | 1 - ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h | 1 - ports_smp/cortex_a7_smp/gnu/example_build/v7.h | 1 - ports_smp/cortex_a9_smp/gnu/example_build/v7.h | 1 - 5 files changed, 5 deletions(-) diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h index 5a08b43fd..6016ef64f 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h @@ -35,7 +35,6 @@ void disableInterrupts(void); // ------------------------------------------------------------ // Caches -void invalidateCaches_IS(void); void cleanInvalidateDCache(void); void invalidateCaches_IS(void); void enableCaches(void); diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/v7.h b/ports_smp/cortex_a5_smp/gnu/example_build/v7.h index 5a08b43fd..6016ef64f 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/v7.h +++ b/ports_smp/cortex_a5_smp/gnu/example_build/v7.h @@ -35,7 +35,6 @@ void disableInterrupts(void); // ------------------------------------------------------------ // Caches -void invalidateCaches_IS(void); void cleanInvalidateDCache(void); void invalidateCaches_IS(void); void enableCaches(void); diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h index 5a08b43fd..6016ef64f 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h @@ -35,7 +35,6 @@ void disableInterrupts(void); // ------------------------------------------------------------ // Caches -void invalidateCaches_IS(void); void cleanInvalidateDCache(void); void invalidateCaches_IS(void); void enableCaches(void); diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/v7.h b/ports_smp/cortex_a7_smp/gnu/example_build/v7.h index 0fc0183f3..88e88508d 100644 --- a/ports_smp/cortex_a7_smp/gnu/example_build/v7.h +++ b/ports_smp/cortex_a7_smp/gnu/example_build/v7.h @@ -23,7 +23,6 @@ void disableInterrupts(void); // ------------------------------------------------------------ // Caches -void invalidateCaches_IS(void); void cleanInvalidateDCache(void); void invalidateCaches_IS(void); void enableCaches(void); diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/v7.h b/ports_smp/cortex_a9_smp/gnu/example_build/v7.h index 5a08b43fd..6016ef64f 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/v7.h +++ b/ports_smp/cortex_a9_smp/gnu/example_build/v7.h @@ -35,7 +35,6 @@ void disableInterrupts(void); // ------------------------------------------------------------ // Caches -void invalidateCaches_IS(void); void cleanInvalidateDCache(void); void invalidateCaches_IS(void); void enableCaches(void); From 5d619e5c4ba36fdf4fe5bc6ffb34f18dc7076ac5 Mon Sep 17 00:00:00 2001 From: Alex Kiselev Date: Wed, 21 Jun 2023 09:08:45 +0200 Subject: [PATCH 04/29] SysTick initialization problem fixed in tx_initialize_low_level.s Problem with first system tick was detected, it needs much more time for the first tick as it's defined. The reason for this behavior is incorrect initialization of the SysTick timer in the port file for the Cortex-M0. It doesn't reset the SysTick Current Value Register despite the fact that its value is not initialized at startup (see https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/system-timer--systick). So if we have 0xFFFFFF (this register has 24-bit), it means we will get about 256*256*256 / 48000000 for the tact frequency of 48MHz to reach the zero, that makes 350ms delay at startup. --- ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s | 3 +++ ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S | 3 +++ ports/cortex_m0/iar/example_build/tx_initialize_low_level.s | 3 +++ ports/cortex_m0/keil/example_build/tx_initialize_low_level.s | 3 +++ 4 files changed, 12 insertions(+) diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s index 4a4f20db6..0c19cc2fe 100644 --- a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -176,6 +176,9 @@ _tx_initialize_low_level ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOVS r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S index aaf3ece2c..fd08b2822 100644 --- a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S @@ -134,6 +134,9 @@ _tx_initialize_low_level: @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ LDR r0, =0xE000E000 @ Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value LDR r1, =0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s index 3de316e59..09742eccc 100644 --- a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s @@ -125,6 +125,9 @@ _tx_initialize_low_level: ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOVS r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s index 4a4f20db6..0c19cc2fe 100644 --- a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s @@ -176,6 +176,9 @@ _tx_initialize_low_level ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOVS r1, #0x7 ; Build SysTick Control Enable Value From 9d29a9a8de6277b6df1f6f5c5717351a9c75f68c Mon Sep 17 00:00:00 2001 From: Yang Hau Date: Sun, 18 Feb 2024 21:06:56 +0900 Subject: [PATCH 05/29] fix the typos --- test/smp/cmake/regression/CMakeLists.txt | 4 +- test/smp/regression/testcontrol.c | 14 +- .../threadx_mutex_information_test.c | 34 ++--- ...x_mutex_nested_priority_inheritance_test.c | 4 +- ..._smp_resume_suspend_accending_order_test.c | 66 ++++----- ..._smp_resume_suspend_decending_order_test.c | 134 +++++++++--------- .../threadx_thread_basic_execution_test.c | 4 +- .../threadx_thread_delayed_suspension_test.c | 18 +-- .../threadx_thread_simple_suspend_test.c | 2 +- .../threadx_thread_sleep_for_100ticks_test.c | 24 ++-- .../threadx_thread_terminate_delete_test.c | 2 +- test/tx/regression/testcontrol.c | 6 +- .../threadx_mutex_information_test.c | 34 ++--- ...x_mutex_nested_priority_inheritance_test.c | 4 +- .../threadx_thread_basic_execution_test.c | 4 +- .../threadx_thread_delayed_suspension_test.c | 18 +-- .../threadx_thread_simple_suspend_test.c | 2 +- .../threadx_thread_sleep_for_100ticks_test.c | 24 ++-- .../threadx_thread_terminate_delete_test.c | 2 +- 19 files changed, 200 insertions(+), 200 deletions(-) diff --git a/test/smp/cmake/regression/CMakeLists.txt b/test/smp/cmake/regression/CMakeLists.txt index ad002d185..6b68f711e 100644 --- a/test/smp/cmake/regression/CMakeLists.txt +++ b/test/smp/cmake/regression/CMakeLists.txt @@ -74,8 +74,8 @@ set(regression_test_cases ${SOURCE_DIR}/threadx_smp_random_resume_suspend_test.c ${SOURCE_DIR}/threadx_smp_rebalance_exclusion_test.c ${SOURCE_DIR}/threadx_smp_relinquish_test.c - ${SOURCE_DIR}/threadx_smp_resume_suspend_accending_order_test.c - ${SOURCE_DIR}/threadx_smp_resume_suspend_decending_order_test.c + ${SOURCE_DIR}/threadx_smp_resume_suspend_ascending_order_test.c + ${SOURCE_DIR}/threadx_smp_resume_suspend_descending_order_test.c ${SOURCE_DIR}/threadx_smp_time_slice_test.c ${SOURCE_DIR}/threadx_smp_two_threads_one_core_test.c ${SOURCE_DIR}/threadx_thread_basic_execution_test.c diff --git a/test/smp/regression/testcontrol.c b/test/smp/regression/testcontrol.c index 8e3d872e4..ed2991956 100644 --- a/test/smp/regression/testcontrol.c +++ b/test/smp/regression/testcontrol.c @@ -208,7 +208,7 @@ void threadx_semaphore_information_application_define(void *); void threadx_thread_basic_execution_application_define(void *); void threadx_thread_completed_application_define(void *); void threadx_thread_relinquish_application_define(void *); -void threadx_thread_simple_supsend_application_define(void *); +void threadx_thread_simple_suspend_application_define(void *); void threadx_thread_multiple_suspension_application_define(void *); void threadx_thread_multiple_non_current_suspension_application_define(void *); void threadx_thread_multi_level_preemption_threshold_application_define(void *); @@ -249,8 +249,8 @@ void threadx_smp_two_threads_one_core_test(void *first_unused_memory); void threadx_smp_multiple_threads_one_core_test(void *first_unused_memory); void threadx_smp_one_thread_dynamic_exclusion_test(void *first_unused_memory); void threadx_smp_non_trivial_scheduling_test(void *first_unused_memory); -void threadx_smp_resume_suspend_accending_order_test(void *first_unused_memory); -void threadx_smp_resume_suspend_decending_order_test(void *first_unused_memory); +void threadx_smp_resume_suspend_ascending_order_test(void *first_unused_memory); +void threadx_smp_resume_suspend_descending_order_test(void *first_unused_memory); void threadx_smp_preemption_threshold_test(void *first_unused_memory); void threadx_smp_relinquish_test(void *first_unused_memory); void threadx_smp_time_slice_test(void *first_unused_memory); @@ -273,8 +273,8 @@ TEST_ENTRY test_control_tests[] = threadx_smp_multiple_threads_one_core_test, threadx_smp_one_thread_dynamic_exclusion_test, threadx_smp_non_trivial_scheduling_test, - threadx_smp_resume_suspend_accending_order_test, - threadx_smp_resume_suspend_decending_order_test, + threadx_smp_resume_suspend_ascending_order_test, + threadx_smp_resume_suspend_descending_order_test, threadx_smp_preemption_threshold_test, threadx_smp_relinquish_test, threadx_smp_time_slice_test, @@ -351,7 +351,7 @@ TEST_ENTRY test_control_tests[] = threadx_thread_basic_execution_application_define, threadx_thread_completed_application_define, threadx_thread_relinquish_application_define, - threadx_thread_simple_supsend_application_define, + threadx_thread_simple_suspend_application_define, threadx_thread_multiple_suspension_application_define, threadx_thread_multiple_non_current_suspension_application_define, threadx_thread_multi_level_preemption_threshold_application_define, @@ -1428,7 +1428,7 @@ UINT old_posture = TX_INT_ENABLE; if (old_posture == TX_INT_DISABLE) { - /* System error - interrupts should alwasy be enabled in our test threads! */ + /* System error - interrupts should always be enabled in our test threads! */ printf(" ***** SYSTEM ERROR ***** test returned with interrupts disabled!\n"); test_control_system_errors++; } diff --git a/test/smp/regression/threadx_mutex_information_test.c b/test/smp/regression/threadx_mutex_information_test.c index e95c16c6b..76d04e75c 100644 --- a/test/smp/regression/threadx_mutex_information_test.c +++ b/test/smp/regression/threadx_mutex_information_test.c @@ -312,7 +312,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(&mutex_2, &puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -326,7 +326,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(&puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -342,7 +342,7 @@ ULONG inheritances; #else - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(&mutex_2, &puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -354,7 +354,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, &puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -366,7 +366,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -378,7 +378,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -390,7 +390,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -402,7 +402,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &inversions, &inheritances); /* Check status. */ @@ -414,7 +414,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &inheritances); /* Check status. */ @@ -426,7 +426,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); /* Check status. */ @@ -438,7 +438,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(&puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -450,7 +450,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -462,7 +462,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -474,7 +474,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -486,7 +486,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &inversions, &inheritances); /* Check status. */ @@ -498,7 +498,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &inheritances); /* Check status. */ @@ -510,7 +510,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); /* Check status. */ diff --git a/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c b/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c index 7397b4e2d..1738527e4 100644 --- a/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c +++ b/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c @@ -404,7 +404,7 @@ UINT status; tx_mutex_put(&mutex_2); - /* Should reurn us back to priority 15. */ + /* Should return us back to priority 15. */ if (thread_0.tx_thread_priority != 15) { @@ -441,7 +441,7 @@ UINT status; tx_mutex_put(&mutex_2); - /* Should reurn us back to priority 8. */ + /* Should return us back to priority 8. */ if (thread_0.tx_thread_priority != 8) { diff --git a/test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c b/test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c index 3a845878c..35ef18933 100644 --- a/test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c +++ b/test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c @@ -1,4 +1,4 @@ -/* Define the ThreadX SMP resume and suspend threads in accending order test. */ +/* Define the ThreadX SMP resume and suspend threads in ascending order test. */ #include #include "tx_api.h" @@ -71,7 +71,7 @@ static void delay(UINT i) #ifdef CTEST void test_application_define(void *first_unused_memory) #else -void threadx_smp_resume_suspend_accending_order_test(void *first_unused_memory) +void threadx_smp_resume_suspend_ascending_order_test(void *first_unused_memory) #endif { @@ -969,7 +969,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(1); status = tx_thread_suspend(&thread_1); @@ -983,7 +983,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(2); status = tx_thread_suspend(&thread_2); @@ -997,7 +997,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(3); status = tx_thread_suspend(&thread_3); @@ -1011,7 +1011,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(4); status = tx_thread_suspend(&thread_4); @@ -1025,7 +1025,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(5); status = tx_thread_suspend(&thread_5); @@ -1039,7 +1039,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(6); status = tx_thread_suspend(&thread_6); @@ -1053,7 +1053,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(7); status = tx_thread_suspend(&thread_7); @@ -1067,7 +1067,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(8); status = tx_thread_suspend(&thread_8); @@ -1081,7 +1081,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(9); status = tx_thread_suspend(&thread_9); @@ -1095,7 +1095,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(10); status = tx_thread_suspend(&thread_10); @@ -1109,7 +1109,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(11); status = tx_thread_suspend(&thread_11); @@ -1123,7 +1123,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(12); status = tx_thread_suspend(&thread_12); @@ -1137,7 +1137,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(13); status = tx_thread_suspend(&thread_13); @@ -1151,7 +1151,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(14); status = tx_thread_suspend(&thread_14); @@ -1165,7 +1165,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(15); status = tx_thread_suspend(&thread_15); @@ -1179,7 +1179,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(16); status = tx_thread_suspend(&thread_16); @@ -1193,7 +1193,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(17); status = tx_thread_suspend(&thread_17); @@ -1207,7 +1207,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(18); status = tx_thread_suspend(&thread_18); @@ -1221,7 +1221,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(19); status = tx_thread_suspend(&thread_19); @@ -1235,7 +1235,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(20); status = tx_thread_suspend(&thread_20); @@ -1249,7 +1249,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(21); status = tx_thread_suspend(&thread_21); @@ -1263,7 +1263,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(22); status = tx_thread_suspend(&thread_22); @@ -1277,7 +1277,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(23); status = tx_thread_suspend(&thread_23); @@ -1291,7 +1291,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(24); status = tx_thread_suspend(&thread_24); @@ -1305,7 +1305,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(25); status = tx_thread_suspend(&thread_25); @@ -1319,7 +1319,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(26); status = tx_thread_suspend(&thread_26); @@ -1333,7 +1333,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(27); status = tx_thread_suspend(&thread_27); @@ -1347,7 +1347,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(28); status = tx_thread_suspend(&thread_28); @@ -1361,7 +1361,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(29); status = tx_thread_suspend(&thread_29); @@ -1375,7 +1375,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(30); status = tx_thread_suspend(&thread_30); @@ -1389,7 +1389,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ delay(31); status = tx_thread_suspend(&thread_31); diff --git a/test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c b/test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c index 6eae504e7..da159587e 100644 --- a/test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c +++ b/test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c @@ -1,4 +1,4 @@ -/* Define the ThreadX SMP resume and suspend threads in accending order test. */ +/* Define the ThreadX SMP resume and suspend threads in ascending order test. */ #include #include "tx_api.h" @@ -71,7 +71,7 @@ static void delay(UINT i) #ifdef CTEST void test_application_define(void *first_unused_memory) #else -void threadx_smp_resume_suspend_decending_order_test(void *first_unused_memory) +void threadx_smp_resume_suspend_descending_order_test(void *first_unused_memory) #endif { @@ -96,7 +96,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #1\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #1\n"); test_control_return(1); } @@ -110,7 +110,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #2\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #2\n"); test_control_return(1); } @@ -124,7 +124,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #3\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #3\n"); test_control_return(1); } @@ -138,7 +138,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #4\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #4\n"); test_control_return(1); } @@ -152,7 +152,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #5\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #5\n"); test_control_return(1); } @@ -166,7 +166,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #6\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #6\n"); test_control_return(1); } @@ -180,7 +180,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #7\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #7\n"); test_control_return(1); } @@ -194,7 +194,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #8\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #8\n"); test_control_return(1); } @@ -208,7 +208,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #9\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #9\n"); test_control_return(1); } @@ -222,7 +222,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #9\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #9\n"); test_control_return(1); } @@ -236,7 +236,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #11\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #11\n"); test_control_return(1); } @@ -250,7 +250,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #12\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #12\n"); test_control_return(1); } @@ -264,7 +264,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #13\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #13\n"); test_control_return(1); } @@ -278,7 +278,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #14\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #14\n"); test_control_return(1); } @@ -292,7 +292,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #15\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #15\n"); test_control_return(1); } @@ -306,7 +306,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #16\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #16\n"); test_control_return(1); } @@ -320,7 +320,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #17\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #17\n"); test_control_return(1); } @@ -334,7 +334,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #18\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #18\n"); test_control_return(1); } @@ -348,7 +348,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #19\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #19\n"); test_control_return(1); } @@ -362,7 +362,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #20\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #20\n"); test_control_return(1); } @@ -376,7 +376,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #21\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #21\n"); test_control_return(1); } @@ -390,7 +390,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #22\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #22\n"); test_control_return(1); } @@ -404,7 +404,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #23\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #23\n"); test_control_return(1); } @@ -418,7 +418,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #24\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #24\n"); test_control_return(1); } @@ -432,7 +432,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #25\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #25\n"); test_control_return(1); } @@ -446,7 +446,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #26\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #26\n"); test_control_return(1); } @@ -460,7 +460,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #27\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #27\n"); test_control_return(1); } @@ -474,7 +474,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #28\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #28\n"); test_control_return(1); } @@ -488,7 +488,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #29\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #29\n"); test_control_return(1); } @@ -502,7 +502,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #30\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #30\n"); test_control_return(1); } @@ -516,7 +516,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #31\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #31\n"); test_control_return(1); } @@ -530,7 +530,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #32\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #32\n"); test_control_return(1); } @@ -547,7 +547,7 @@ UINT i; if (status != TX_SUCCESS) { - printf("Running SMP Resume-Suspend Decending Priority Order Test............ ERROR #33\n"); + printf("Running SMP Resume-Suspend descending Priority Order Test............ ERROR #33\n"); test_control_return(1); } } @@ -564,7 +564,7 @@ UINT status; /* Inform user. */ - printf("Running SMP Resume-Suspend Decending Priority Order Test............ "); + printf("Running SMP Resume-Suspend descending Priority Order Test............ "); /* Resume all the threads. */ status = tx_thread_resume(&thread_31); @@ -999,7 +999,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in decending priority. */ + /* Suspend thread in descending priority. */ status = tx_thread_suspend(&thread_31); /* Check for the correct results. */ @@ -1012,7 +1012,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_30); /* Check for the correct results. */ @@ -1025,7 +1025,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_29); /* Check for the correct results. */ @@ -1038,7 +1038,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_28); /* Check for the correct results. */ @@ -1051,7 +1051,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_27); /* Check for the correct results. */ @@ -1064,7 +1064,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_26); /* Check for the correct results. */ @@ -1077,7 +1077,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_25); /* Check for the correct results. */ @@ -1090,7 +1090,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_24); /* Check for the correct results. */ @@ -1103,7 +1103,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_23); /* Check for the correct results. */ @@ -1116,7 +1116,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_22); /* Check for the correct results. */ @@ -1129,7 +1129,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_21); /* Check for the correct results. */ @@ -1142,7 +1142,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_20); /* Check for the correct results. */ @@ -1155,7 +1155,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_19); /* Check for the correct results. */ @@ -1168,7 +1168,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_18); /* Check for the correct results. */ @@ -1181,7 +1181,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_17); /* Check for the correct results. */ @@ -1194,7 +1194,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_16); /* Check for the correct results. */ @@ -1207,7 +1207,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_15); /* Check for the correct results. */ @@ -1220,7 +1220,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_14); /* Check for the correct results. */ @@ -1233,7 +1233,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_13); /* Check for the correct results. */ @@ -1246,7 +1246,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_12); /* Check for the correct results. */ @@ -1259,7 +1259,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_11); /* Check for the correct results. */ @@ -1272,7 +1272,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_10); /* Check for the correct results. */ @@ -1285,7 +1285,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_9); /* Check for the correct results. */ @@ -1298,7 +1298,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_8); /* Check for the correct results. */ @@ -1311,7 +1311,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_7); /* Check for the correct results. */ @@ -1324,7 +1324,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_6); /* Check for the correct results. */ @@ -1337,7 +1337,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_5); /* Check for the correct results. */ @@ -1350,7 +1350,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_4); /* Check for the correct results. */ @@ -1363,7 +1363,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_3); /* Check for the correct results. */ @@ -1376,7 +1376,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_2); /* Check for the correct results. */ @@ -1389,7 +1389,7 @@ UINT status; test_control_return(1); } - /* Suspend thread in accending priority. */ + /* Suspend thread in ascending priority. */ status = tx_thread_suspend(&thread_1); /* Check for the correct results. */ diff --git a/test/smp/regression/threadx_thread_basic_execution_test.c b/test/smp/regression/threadx_thread_basic_execution_test.c index 02e18d249..df1070dae 100644 --- a/test/smp/regression/threadx_thread_basic_execution_test.c +++ b/test/smp/regression/threadx_thread_basic_execution_test.c @@ -741,7 +741,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); test_control_return(1); } - /* Attempt a thread termiante with a NULL pointer. */ + /* Attempt a thread terminate with a NULL pointer. */ status = tx_thread_terminate(TX_NULL); /* Check for status. */ @@ -764,7 +764,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); test_control_return(1); } - /* Attempt a thread time-slice chagne with a NULL pointer. */ + /* Attempt a thread time-slice change with a NULL pointer. */ status = tx_thread_time_slice_change(TX_NULL, 1, &old_time_slice); /* Check for status. */ diff --git a/test/smp/regression/threadx_thread_delayed_suspension_test.c b/test/smp/regression/threadx_thread_delayed_suspension_test.c index 6d6d27d0b..4b6955596 100644 --- a/test/smp/regression/threadx_thread_delayed_suspension_test.c +++ b/test/smp/regression/threadx_thread_delayed_suspension_test.c @@ -56,7 +56,7 @@ static volatile ULONG destination = 0; static ULONG start_time; static ULONG lower_bound; static ULONG upper_bound; -static ULONG current_itterations; +static ULONG current_iterations; #ifdef DEBUG_1 static ULONG last_loop_count; #endif @@ -106,8 +106,8 @@ ULONG i; if (upper_bound > max_loop_count) lower_bound = max_loop_count; - if ((current_itterations < lower_bound) || (current_itterations > upper_bound)) - current_itterations = lower_bound; + if ((current_iterations < lower_bound) || (current_iterations > upper_bound)) + current_iterations = lower_bound; #ifdef DEBUG_1 /* Last loop count. */ @@ -350,7 +350,7 @@ ULONG i; lower_bound = lower_bound - 5; upper_bound = max_loop_count + 5; - current_itterations = lower_bound; + current_iterations = lower_bound; /* This thread simply suspends over and over... */ while(1) @@ -366,20 +366,20 @@ ULONG i; /* Call delay function. */ delay_function(); loop_count++; - } while (loop_count < current_itterations); + } while (loop_count < current_iterations); /* Suspend this thread. */ tx_semaphore_get(&semaphore_1, TX_WAIT_FOREVER); - /* Adjust the current itterations. */ - current_itterations++; - if (current_itterations > upper_bound) + /* Adjust the current iterations. */ + current_iterations++; + if (current_iterations > upper_bound) { if (lower_bound > min_loop_count) lower_bound--; if (upper_bound < max_loop_count) upper_bound++; - current_itterations = lower_bound; + current_iterations = lower_bound; } /* Increment the thread counter. */ diff --git a/test/smp/regression/threadx_thread_simple_suspend_test.c b/test/smp/regression/threadx_thread_simple_suspend_test.c index 52215a754..9514de1df 100644 --- a/test/smp/regression/threadx_thread_simple_suspend_test.c +++ b/test/smp/regression/threadx_thread_simple_suspend_test.c @@ -25,7 +25,7 @@ void test_control_return(UINT status); #ifdef CTEST void test_application_define(void *first_unused_memory) #else -void threadx_thread_simple_supsend_application_define(void *first_unused_memory) +void threadx_thread_simple_suspend_application_define(void *first_unused_memory) #endif { diff --git a/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c b/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c index 69eadbc67..7ab8a4710 100644 --- a/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c +++ b/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c @@ -42,7 +42,7 @@ static ULONG array_delay[ARRAY_SIZE]; static ULONG start_time; static ULONG lower_bound; static ULONG upper_bound; -static ULONG current_itterations; +static ULONG current_iterations; #ifdef DEBUG_1 static ULONG last_loop_count; #endif @@ -108,8 +108,8 @@ ULONG i; if (upper_bound > max_loop_count) lower_bound = max_loop_count; - if ((current_itterations < lower_bound) || (current_itterations > upper_bound)) - current_itterations = lower_bound; + if ((current_iterations < lower_bound) || (current_iterations > upper_bound)) + current_iterations = lower_bound; #ifdef DEBUG_1 /* Last loop count. */ @@ -218,7 +218,7 @@ CHAR *pointer; min_loop_count = 0xFFFFFFFF; max_loop_count = 0; loop_count = 0xFFFFFFFF; - current_itterations = 0; + current_iterations = 0; #ifdef DEBUG_1 last_loop_count = 0x0; #endif @@ -305,7 +305,7 @@ volatile ULONG value = 0; upper_bound = max_loop_count; #endif - current_itterations = lower_bound; + current_iterations = lower_bound; #ifdef DEBUG i = 0; #endif @@ -323,7 +323,7 @@ volatile ULONG value = 0; /* Call delay function. */ delay_function(); loop_count++; - } while (loop_count < current_itterations); + } while (loop_count < current_iterations); /* Check for a timer interrupt... if so, just skip the semaphore get. */ if (start_time != _tx_timer_system_clock) @@ -332,15 +332,15 @@ volatile ULONG value = 0; /* Suspend on the semaphore for 20 ticks... */ tx_semaphore_get(&test_semaphore, 20); - /* Adjust the current itterations. */ - current_itterations++; - if (current_itterations > upper_bound) + /* Adjust the current iterations. */ + current_iterations++; + if (current_iterations > upper_bound) { if (lower_bound > min_loop_count) lower_bound--; if (upper_bound < max_loop_count) upper_bound++; - current_itterations = lower_bound; + current_iterations = lower_bound; } /* Set the tick count simply to use value. */ @@ -355,7 +355,7 @@ volatile ULONG value = 0; printf("loop count: NA\n"); else printf("loop count: %lu\n", loop_count); - printf("current: %lu\n", current_itterations); + printf("current: %lu\n", current_iterations); printf("last loop count: %lu\n", last_loop_count); printf("minimum: %lu\n", min_loop_count); printf("maximum: %lu\n", max_loop_count); @@ -373,7 +373,7 @@ volatile ULONG value = 0; printf("loop count: NA\n"); else printf("loop count: %lu\n", loop_count); - printf("current: %lu\n", current_itterations); + printf("current: %lu\n", current_iterations); printf("last loop count: %lu\n", last_loop_count); printf("minimum: %lu\n", min_loop_count); printf("maximum: %lu\n", max_loop_count); diff --git a/test/smp/regression/threadx_thread_terminate_delete_test.c b/test/smp/regression/threadx_thread_terminate_delete_test.c index dbe919f38..4a8661fa3 100644 --- a/test/smp/regression/threadx_thread_terminate_delete_test.c +++ b/test/smp/regression/threadx_thread_terminate_delete_test.c @@ -244,7 +244,7 @@ UINT status; test_control_return(1); } - /* Delete thread 1 (thread 1 alread terminated) and 2. */ + /* Delete thread 1 (thread 1 alreadyterminated) and 2. */ status = tx_thread_delete(&thread_2); /* Check for status. */ diff --git a/test/tx/regression/testcontrol.c b/test/tx/regression/testcontrol.c index a53c50a5c..62d178cf2 100644 --- a/test/tx/regression/testcontrol.c +++ b/test/tx/regression/testcontrol.c @@ -194,7 +194,7 @@ void threadx_semaphore_information_application_define(void *); void threadx_thread_basic_execution_application_define(void *); void threadx_thread_completed_application_define(void *); void threadx_thread_relinquish_application_define(void *); -void threadx_thread_simple_supsend_application_define(void *); +void threadx_thread_simple_suspend_application_define(void *); void threadx_thread_multiple_suspension_application_define(void *); void threadx_thread_multiple_non_current_suspension_application_define(void *); void threadx_thread_multi_level_preemption_threshold_application_define(void *); @@ -310,7 +310,7 @@ TEST_ENTRY test_control_tests[] = threadx_thread_basic_execution_application_define, threadx_thread_completed_application_define, threadx_thread_relinquish_application_define, - threadx_thread_simple_supsend_application_define, + threadx_thread_simple_suspend_application_define, threadx_thread_multiple_suspension_application_define, threadx_thread_multiple_non_current_suspension_application_define, threadx_thread_multi_level_preemption_threshold_application_define, @@ -1230,7 +1230,7 @@ UINT old_posture = TX_INT_ENABLE; if (old_posture == TX_INT_DISABLE) { - /* System error - interrupts should alwasy be enabled in our test threads! */ + /* System error - interrupts should always be enabled in our test threads! */ printf(" ***** SYSTEM ERROR ***** test returned with interrupts disabled!\n"); test_control_system_errors++; } diff --git a/test/tx/regression/threadx_mutex_information_test.c b/test/tx/regression/threadx_mutex_information_test.c index e95c16c6b..76d04e75c 100644 --- a/test/tx/regression/threadx_mutex_information_test.c +++ b/test/tx/regression/threadx_mutex_information_test.c @@ -312,7 +312,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(&mutex_2, &puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -326,7 +326,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(&puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -342,7 +342,7 @@ ULONG inheritances; #else - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(&mutex_2, &puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -354,7 +354,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, &puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -366,7 +366,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -378,7 +378,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -390,7 +390,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -402,7 +402,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &inversions, &inheritances); /* Check status. */ @@ -414,7 +414,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &inheritances); /* Check status. */ @@ -426,7 +426,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the performance inforamtion. */ + /* Now get the performance information. */ status = tx_mutex_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); /* Check status. */ @@ -438,7 +438,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(&puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -450,7 +450,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, &gets, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -462,7 +462,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, &suspensions, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -474,7 +474,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, &timeouts, &inversions, &inheritances); /* Check status. */ @@ -486,7 +486,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &inversions, &inheritances); /* Check status. */ @@ -498,7 +498,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &inheritances); /* Check status. */ @@ -510,7 +510,7 @@ ULONG inheritances; test_control_return(1); } - /* Now get the system performance inforamtion. */ + /* Now get the system performance information. */ status = tx_mutex_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); /* Check status. */ diff --git a/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c b/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c index 7397b4e2d..1738527e4 100644 --- a/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c +++ b/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c @@ -404,7 +404,7 @@ UINT status; tx_mutex_put(&mutex_2); - /* Should reurn us back to priority 15. */ + /* Should return us back to priority 15. */ if (thread_0.tx_thread_priority != 15) { @@ -441,7 +441,7 @@ UINT status; tx_mutex_put(&mutex_2); - /* Should reurn us back to priority 8. */ + /* Should return us back to priority 8. */ if (thread_0.tx_thread_priority != 8) { diff --git a/test/tx/regression/threadx_thread_basic_execution_test.c b/test/tx/regression/threadx_thread_basic_execution_test.c index 7a5ae864a..89ce33526 100644 --- a/test/tx/regression/threadx_thread_basic_execution_test.c +++ b/test/tx/regression/threadx_thread_basic_execution_test.c @@ -813,7 +813,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); test_control_return(1); } - /* Attempt a thread termiante with a NULL pointer. */ + /* Attempt a thread terminate with a NULL pointer. */ status = tx_thread_terminate(TX_NULL); /* Check for status. */ @@ -836,7 +836,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); test_control_return(1); } - /* Attempt a thread time-slice chagne with a NULL pointer. */ + /* Attempt a thread time-slice change with a NULL pointer. */ status = tx_thread_time_slice_change(TX_NULL, 1, &old_time_slice); /* Check for status. */ diff --git a/test/tx/regression/threadx_thread_delayed_suspension_test.c b/test/tx/regression/threadx_thread_delayed_suspension_test.c index 6d6d27d0b..4b6955596 100644 --- a/test/tx/regression/threadx_thread_delayed_suspension_test.c +++ b/test/tx/regression/threadx_thread_delayed_suspension_test.c @@ -56,7 +56,7 @@ static volatile ULONG destination = 0; static ULONG start_time; static ULONG lower_bound; static ULONG upper_bound; -static ULONG current_itterations; +static ULONG current_iterations; #ifdef DEBUG_1 static ULONG last_loop_count; #endif @@ -106,8 +106,8 @@ ULONG i; if (upper_bound > max_loop_count) lower_bound = max_loop_count; - if ((current_itterations < lower_bound) || (current_itterations > upper_bound)) - current_itterations = lower_bound; + if ((current_iterations < lower_bound) || (current_iterations > upper_bound)) + current_iterations = lower_bound; #ifdef DEBUG_1 /* Last loop count. */ @@ -350,7 +350,7 @@ ULONG i; lower_bound = lower_bound - 5; upper_bound = max_loop_count + 5; - current_itterations = lower_bound; + current_iterations = lower_bound; /* This thread simply suspends over and over... */ while(1) @@ -366,20 +366,20 @@ ULONG i; /* Call delay function. */ delay_function(); loop_count++; - } while (loop_count < current_itterations); + } while (loop_count < current_iterations); /* Suspend this thread. */ tx_semaphore_get(&semaphore_1, TX_WAIT_FOREVER); - /* Adjust the current itterations. */ - current_itterations++; - if (current_itterations > upper_bound) + /* Adjust the current iterations. */ + current_iterations++; + if (current_iterations > upper_bound) { if (lower_bound > min_loop_count) lower_bound--; if (upper_bound < max_loop_count) upper_bound++; - current_itterations = lower_bound; + current_iterations = lower_bound; } /* Increment the thread counter. */ diff --git a/test/tx/regression/threadx_thread_simple_suspend_test.c b/test/tx/regression/threadx_thread_simple_suspend_test.c index 52215a754..9514de1df 100644 --- a/test/tx/regression/threadx_thread_simple_suspend_test.c +++ b/test/tx/regression/threadx_thread_simple_suspend_test.c @@ -25,7 +25,7 @@ void test_control_return(UINT status); #ifdef CTEST void test_application_define(void *first_unused_memory) #else -void threadx_thread_simple_supsend_application_define(void *first_unused_memory) +void threadx_thread_simple_suspend_application_define(void *first_unused_memory) #endif { diff --git a/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c b/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c index 69eadbc67..7ab8a4710 100644 --- a/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c +++ b/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c @@ -42,7 +42,7 @@ static ULONG array_delay[ARRAY_SIZE]; static ULONG start_time; static ULONG lower_bound; static ULONG upper_bound; -static ULONG current_itterations; +static ULONG current_iterations; #ifdef DEBUG_1 static ULONG last_loop_count; #endif @@ -108,8 +108,8 @@ ULONG i; if (upper_bound > max_loop_count) lower_bound = max_loop_count; - if ((current_itterations < lower_bound) || (current_itterations > upper_bound)) - current_itterations = lower_bound; + if ((current_iterations < lower_bound) || (current_iterations > upper_bound)) + current_iterations = lower_bound; #ifdef DEBUG_1 /* Last loop count. */ @@ -218,7 +218,7 @@ CHAR *pointer; min_loop_count = 0xFFFFFFFF; max_loop_count = 0; loop_count = 0xFFFFFFFF; - current_itterations = 0; + current_iterations = 0; #ifdef DEBUG_1 last_loop_count = 0x0; #endif @@ -305,7 +305,7 @@ volatile ULONG value = 0; upper_bound = max_loop_count; #endif - current_itterations = lower_bound; + current_iterations = lower_bound; #ifdef DEBUG i = 0; #endif @@ -323,7 +323,7 @@ volatile ULONG value = 0; /* Call delay function. */ delay_function(); loop_count++; - } while (loop_count < current_itterations); + } while (loop_count < current_iterations); /* Check for a timer interrupt... if so, just skip the semaphore get. */ if (start_time != _tx_timer_system_clock) @@ -332,15 +332,15 @@ volatile ULONG value = 0; /* Suspend on the semaphore for 20 ticks... */ tx_semaphore_get(&test_semaphore, 20); - /* Adjust the current itterations. */ - current_itterations++; - if (current_itterations > upper_bound) + /* Adjust the current iterations. */ + current_iterations++; + if (current_iterations > upper_bound) { if (lower_bound > min_loop_count) lower_bound--; if (upper_bound < max_loop_count) upper_bound++; - current_itterations = lower_bound; + current_iterations = lower_bound; } /* Set the tick count simply to use value. */ @@ -355,7 +355,7 @@ volatile ULONG value = 0; printf("loop count: NA\n"); else printf("loop count: %lu\n", loop_count); - printf("current: %lu\n", current_itterations); + printf("current: %lu\n", current_iterations); printf("last loop count: %lu\n", last_loop_count); printf("minimum: %lu\n", min_loop_count); printf("maximum: %lu\n", max_loop_count); @@ -373,7 +373,7 @@ volatile ULONG value = 0; printf("loop count: NA\n"); else printf("loop count: %lu\n", loop_count); - printf("current: %lu\n", current_itterations); + printf("current: %lu\n", current_iterations); printf("last loop count: %lu\n", last_loop_count); printf("minimum: %lu\n", min_loop_count); printf("maximum: %lu\n", max_loop_count); diff --git a/test/tx/regression/threadx_thread_terminate_delete_test.c b/test/tx/regression/threadx_thread_terminate_delete_test.c index dbe919f38..4a8661fa3 100644 --- a/test/tx/regression/threadx_thread_terminate_delete_test.c +++ b/test/tx/regression/threadx_thread_terminate_delete_test.c @@ -244,7 +244,7 @@ UINT status; test_control_return(1); } - /* Delete thread 1 (thread 1 alread terminated) and 2. */ + /* Delete thread 1 (thread 1 alreadyterminated) and 2. */ status = tx_thread_delete(&thread_2); /* Check for status. */ From 416dfac3fd596c6fcc5b299886426eb40a42ecaa Mon Sep 17 00:00:00 2001 From: Alex Kiselev Date: Thu, 5 Sep 2024 15:11:35 +0200 Subject: [PATCH 06/29] Comment style changed according to conversation --- ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s | 4 ++-- ports/cortex_m0/iar/example_build/tx_initialize_low_level.s | 4 ++-- ports/cortex_m0/keil/example_build/tx_initialize_low_level.s | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s index 0c19cc2fe..719b6b8c2 100644 --- a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -177,8 +177,8 @@ _tx_initialize_low_level ; LDR r0, =0xE000E000 ; Build address of NVIC registers LDR r1, =0 - STR r1, [r0, #0x10] // Reset SysTick Control - STR r1, [r0, #0x18] // Reset SysTick Counter Value + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOVS r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s index 09742eccc..49245c6be 100644 --- a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s @@ -126,8 +126,8 @@ _tx_initialize_low_level: ; LDR r0, =0xE000E000 ; Build address of NVIC registers LDR r1, =0 - STR r1, [r0, #0x10] // Reset SysTick Control - STR r1, [r0, #0x18] // Reset SysTick Counter Value + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOVS r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s index 0c19cc2fe..719b6b8c2 100644 --- a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s @@ -177,8 +177,8 @@ _tx_initialize_low_level ; LDR r0, =0xE000E000 ; Build address of NVIC registers LDR r1, =0 - STR r1, [r0, #0x10] // Reset SysTick Control - STR r1, [r0, #0x18] // Reset SysTick Counter Value + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOVS r1, #0x7 ; Build SysTick Control Enable Value From 2f1fc5291827ee1b4279237646a2bc808a299896 Mon Sep 17 00:00:00 2001 From: "shuta.lst" Date: Wed, 4 Mar 2026 10:51:20 +0800 Subject: [PATCH 07/29] RISC-V64 arch. port support RVV Extension; --- ports/risc-v64/gnu/inc/tx_port.h | 12 +- .../gnu/src/tx_thread_context_restore.S | 124 ++++++++++++++++++ .../risc-v64/gnu/src/tx_thread_context_save.S | 75 +++++++++++ ports/risc-v64/gnu/src/tx_thread_schedule.S | 80 +++++++++++ .../risc-v64/gnu/src/tx_thread_stack_build.S | 46 ++++++- .../gnu/src/tx_thread_system_return.S | 36 +++++ 6 files changed, 369 insertions(+), 4 deletions(-) diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h index ed985072e..b146529b5 100644 --- a/ports/risc-v64/gnu/inc/tx_port.h +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -105,7 +105,11 @@ typedef unsigned short USHORT; thread creation is less than this value, the thread create call will return an error. */ #ifndef TX_MINIMUM_STACK -#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ +#if defined(__riscv_vector) +#define TX_MINIMUM_STACK (1024 + 16448) /* Minimum stack size for this port */ +#else +#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ +#endif #endif @@ -113,7 +117,11 @@ typedef unsigned short USHORT; if TX_TIMER_PROCESS_IN_ISR is not defined. */ #ifndef TX_TIMER_THREAD_STACK_SIZE -#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#if defined(__riscv_vector) +#define TX_TIMER_THREAD_STACK_SIZE (1024 + 16448) /* Default timer thread stack size */ +#else +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif #endif #ifndef TX_TIMER_THREAD_PRIORITY diff --git a/ports/risc-v64/gnu/src/tx_thread_context_restore.S b/ports/risc-v64/gnu/src/tx_thread_context_restore.S index 1080e6172..7abd66518 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_restore.S @@ -138,6 +138,34 @@ _tx_thread_context_restore: csrw fcsr, t0 #endif +#if defined(__riscv_vector) + /* Recover vector registers v0-v31 */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, sp, 64*8 +#else + addi t1, sp, 31*8 +#endif + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vle8.v v0, (t2) // Recover v0 ~ v7 + add t2, t2, t3 + vle8.v v8, (t2) // Recover v8 ~ v15 + add t2, t2, t3 + vle8.v v16, (t2) // Recover v16 ~ v23 + add t2, t2, t3 + vle8.v v24, (t2) // Recover v24 ~ v31 + add t2, t2, t3 + + /* Recover vector CSRs */ + ld t2, 0*8(t1) + ld t3, 1*8(t1) + ld t4, 2*8(t1) + vsetvl zero, t4, t3 + csrw vstart, t2 + ld t4, 3*8(t1) + csrw vcsr, t4 +#endif + /* Recover standard registers. */ /* Restore registers, @@ -168,6 +196,10 @@ _tx_thread_context_restore: #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state or t1, t1, t0 +#endif +#if defined(__riscv_vector) + li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state + or t1, t1, t0 #endif csrw mstatus, t1 // Update mstatus safely @@ -194,6 +226,21 @@ _tx_thread_context_restore: #else addi sp, sp, 32*8 // Recover stack frame - without floating point enabled #endif + +#if defined(__riscv_vector) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t0, sp, -65*8 +#else + addi t0, sp, -32*8 +#endif + csrr t1, vlenb // Get vector register byte length + slli t1, t1, 5 // Multiply by 32 (number of vector registers) + addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr + add sp, sp, t1 // Recover vector stack frame + + ld t1, 18*8(t0) // Recover t1 + ld t0, 19*8(t0) // Recover t0 +#endif mret // Return to point of interrupt /* } */ @@ -273,6 +320,34 @@ _tx_thread_no_preempt_restore: csrw fcsr, t0 // Restore fcsr #endif +#if defined(__riscv_vector) + /* Recover vector registers v0-v31 */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, sp, 64*8 +#else + addi t1, sp, 31*8 +#endif + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vle8.v v0, (t2) // Recover v0 ~ v7 + add t2, t2, t3 + vle8.v v8, (t2) // Recover v8 ~ v15 + add t2, t2, t3 + vle8.v v16, (t2) // Recover v16 ~ v23 + add t2, t2, t3 + vle8.v v24, (t2) // Recover v24 ~ v31 + add t2, t2, t3 + + /* Recover vector CSRs */ + ld t2, 0*8(t1) + ld t3, 1*8(t1) + ld t4, 2*8(t1) + vsetvl zero, t4, t3 + csrw vstart, t2 + ld t4, 3*8(t1) + csrw vcsr, t4 +#endif + /* Recover the saved context and return to the point of interrupt. */ /* Recover standard registers. */ @@ -294,6 +369,10 @@ _tx_thread_no_preempt_restore: #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) li t0, 0x2000 // Set FS bits for FP state or t1, t1, t0 +#endif +#if defined(__riscv_vector) + li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state + or t1, t1, t0 #endif csrw mstatus, t1 // Update mstatus safely @@ -320,6 +399,21 @@ _tx_thread_no_preempt_restore: #else addi sp, sp, 32*8 // Recover stack frame - without floating point enabled #endif + +#if defined(__riscv_vector) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t0, sp, -65*8 +#else + addi t0, sp, -32*8 +#endif + csrr t1, vlenb // Get vector register byte length + slli t1, t1, 5 // Multiply by 32 (number of vector registers) + addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr + add sp, sp, t1 // Recover vector stack frame + + ld t1, 18*8(t0) // Recover t1 + ld t0, 19*8(t0) // Recover t0 +#endif mret // Return to point of interrupt /* } @@ -362,6 +456,36 @@ _tx_thread_preempt_restore: fsd f27, 58*8(t0) // Store fs11 #endif +#if defined(__riscv_vector) + /* Store vector registers and CSRs */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, t0, 64*8 +#else + addi t1, t0, 31*8 +#endif + /* Store vector CSRs */ + csrr t2, vstart // Store vstart + sd t2, 0*8(t1) + csrr t2, vtype // Store vtype + sd t2, 1*8(t1) + csrr t2, vl // Store vl + sd t2, 2*8(t1) + csrr t2, vcsr // Store vcsr + sd t2, 3*8(t1) + + /* Store vector registers v0-v31 */ + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vse8.v v0, 0(t2) // Store v0 ~ v7 + add t2, t2, t3 + vse8.v v8, 0(t2) // Store v8 ~ v15 + add t2, t2, t3 + vse8.v v16, 0(t2) // Store v16 ~ v23 + add t2, t2, t3 + vse8.v v24, 0(t2) // Store v24 ~ v31 + add t2, t2, t3 +#endif + /* Store standard preserved registers. */ sd x9, 11*8(t0) // Store s1 diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S index b9aa13c92..5e2b25922 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S @@ -151,6 +151,36 @@ _tx_thread_context_save: sd t0, 63*8(sp) // Store fcsr #endif +#if defined(__riscv_vector) + /* Store vector registers and CSRs */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, sp, 64*8 +#else + addi t1, sp, 31*8 +#endif + /* Store vector CSRs */ + csrr t2, vstart // Store vstart + sd t2, 0*8(t1) + csrr t2, vtype // Store vtype + sd t2, 1*8(t1) + csrr t2, vl // Store vl + sd t2, 2*8(t1) + csrr t2, vcsr // Store vcsr + sd t2, 3*8(t1) + + /* Store vector registers v0-v31 */ + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vse8.v v0, 0(t2) // Store v0 ~ v7 + add t2, t2, t3 + vse8.v v8, 0(t2) // Store v8 ~ v15 + add t2, t2, t3 + vse8.v v16, 0(t2) // Store v16 ~ v23 + add t2, t2, t3 + vse8.v v24, 0(t2) // Store v24 ~ v31 + add t2, t2, t3 +#endif + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY call _tx_execution_isr_enter // Call the ISR execution enter function #endif @@ -241,6 +271,36 @@ _tx_thread_not_nested_save: sd t0, 63*8(sp) // Store fcsr #endif +#if defined(__riscv_vector) + /* Store vector registers and CSRs */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, sp, 64*8 +#else + addi t1, sp, 31*8 +#endif + /* Store vector CSRs */ + csrr t2, vstart // Store vstart + sd t2, 0*8(t1) + csrr t2, vtype // Store vtype + sd t2, 1*8(t1) + csrr t2, vl // Store vl + sd t2, 2*8(t1) + csrr t2, vcsr // Store vcsr + sd t2, 3*8(t1) + + /* Store vector registers v0-v31 */ + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vse8.v v0, 0(t2) // Store v0 ~ v7 + add t2, t2, t3 + vse8.v v8, 0(t2) // Store v8 ~ v15 + add t2, t2, t3 + vse8.v v16, 0(t2) // Store v16 ~ v23 + add t2, t2, t3 + vse8.v v24, 0(t2) // Store v24 ~ v31 + add t2, t2, t3 +#endif + /* Save the current stack pointer in the thread's control block. */ /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ @@ -280,4 +340,19 @@ _tx_thread_idle_system_save: #else addi sp, sp, 32*8 // Recover the reserved stack space #endif + +#if defined(__riscv_vector) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t0, sp, -65*8 +#else + addi t0, sp, -32*8 +#endif + csrr t1, vlenb // Get vector register byte length + slli t1, t1, 5 // Multiply by 32 (number of vector registers) + addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr + add sp, sp, t1 // Recover vector stack frame + + ld t1, 18*8(t0) // Recover t1 + ld t0, 19*8(t0) // Recover t0 +#endif ret // Return to calling ISR diff --git a/ports/risc-v64/gnu/src/tx_thread_schedule.S b/ports/risc-v64/gnu/src/tx_thread_schedule.S index 2618e98bd..947d288d6 100644 --- a/ports/risc-v64/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v64/gnu/src/tx_thread_schedule.S @@ -211,6 +211,34 @@ _tx_thread_schedule_loop: csrw fcsr, t0 // Restore fcsr #endif +#if defined(__riscv_vector) + /* Recover vector registers v0-v31 */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, sp, 64*8 +#else + addi t1, sp, 31*8 +#endif + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vle8.v v0, (t2) // Recover v0 ~ v7 + add t2, t2, t3 + vle8.v v8, (t2) // Recover v8 ~ v15 + add t2, t2, t3 + vle8.v v16, (t2) // Recover v16 ~ v23 + add t2, t2, t3 + vle8.v v24, (t2) // Recover v24 ~ v31 + add t2, t2, t3 + + /* Recover vector CSRs */ + ld t2, 0*8(t1) + ld t3, 1*8(t1) + ld t4, 2*8(t1) + vsetvl zero, t4, t3 + csrw vstart, t2 + ld t4, 3*8(t1) + csrw vcsr, t4 +#endif + /* Recover standard registers. */ ld t0, 30*8(sp) // Recover mepc @@ -219,6 +247,10 @@ _tx_thread_schedule_loop: #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) li t1, 0x2000 // Set FS bits for FP state or t0, t0, t1 +#endif +#if defined(__riscv_vector) + li t1, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state + or t0, t0, t1 #endif csrw mstatus, t0 // Set mstatus @@ -255,6 +287,20 @@ _tx_thread_schedule_loop: addi sp, sp, 65*8 // Recover stack frame - with floating point registers #else addi sp, sp, 32*8 // Recover stack frame - without floating point registers +#endif +#if defined(__riscv_vector) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t0, sp, -65*8 +#else + addi t0, sp, -32*8 +#endif + csrr t1, vlenb // Get vector register byte length + slli t1, t1, 5 // Multiply by 32 (number of vector registers) + addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr + add sp, sp, t1 // Recover vector stack frame + + ld t1, 18*8(t0) // Recover t1 + ld t0, 19*8(t0) // Recover t0 #endif mret // Return to point of interrupt @@ -292,6 +338,34 @@ _tx_thread_synch_return: csrw fcsr, t0 // #endif +#if defined(__riscv_vector) + /* Recover vector registers v0-v31 */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, sp, 28*8 +#else + addi t1, sp, 15*8 +#endif + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vle8.v v0, (t2) // Recover v0 ~ v7 + add t2, t2, t3 + vle8.v v8, (t2) // Recover v8 ~ v15 + add t2, t2, t3 + vle8.v v16, (t2) // Recover v16 ~ v23 + add t2, t2, t3 + vle8.v v24, (t2) // Recover v24 ~ v31 + add t2, t2, t3 + + /* Recover vector CSRs */ + ld t2, 0*8(t1) + ld t3, 1*8(t1) + ld t4, 2*8(t1) + vsetvl zero, t4, t3 + csrw vstart, t2 + ld t4, 3*8(t1) + csrw vcsr, t4 +#endif + /* Recover standard preserved registers. */ /* Recover standard registers. */ @@ -314,6 +388,12 @@ _tx_thread_synch_return: addi sp, sp, 29*8 // Recover stack frame #else addi sp, sp, 16*8 // Recover stack frame +#endif +#if defined(__riscv_vector) + csrr t1, vlenb // Get vector register byte length + slli t1, t1, 5 // Multiply by 32 (number of vector registers) + addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr + add sp, sp, t1 // Recover vector stack frame #endif ret // Return to thread diff --git a/ports/risc-v64/gnu/src/tx_thread_stack_build.S b/ports/risc-v64/gnu/src/tx_thread_stack_build.S index eecfbfece..4dcc30bf2 100644 --- a/ports/risc-v64/gnu/src/tx_thread_stack_build.S +++ b/ports/risc-v64/gnu/src/tx_thread_stack_build.S @@ -133,6 +133,15 @@ If floating point support: f30 61 Inital ft10 f31 62 Inital ft11 fscr 63 Inital fscr +If vector extension support: + vstart 64 Initial vstart + vtype 65 Initial vtype + vl 66 Initial vl + vcsr 67 Initial vcsr + v0 68 Initial v0 + v1 69 Initial v1 + ... + v31 99 Initial v31 Stack Bottom: (higher memory address) */ @@ -147,6 +156,17 @@ If floating point support: #else addi t0, t0, -32*8 // Allocate space for the stack frame #endif + +#if defined(__riscv_vector) + /* Vector extension support: calculate space based on vlenb */ + csrr t4, vlenb // Get vector register byte length + slli t4, t4, 5 // Multiply by 32 (number of vector registers) + addi t4, t4, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr + sub t0, t0, t4 // Allocate vector space for the stack frame +#else + li t4, 0 +#endif + li t1, 1 // Build stack type sd t1, 0*8(t0) // Place stack type on the top sd zero, 1*8(t0) // Initial s11 @@ -213,9 +233,31 @@ If floating point support: sd zero, 62*8(t0) // Initial ft11 csrr a1, fcsr // Read fcsr for initial value sd a1, 63*8(t0) // Initial fcsr - sd zero, 64*8(t0) // Reserved word (0) +#endif + +#if defined(__riscv_vector) + /* Clear vector register space */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t2, t0, 64*8 // t2 = start of vector registers +#else + addi t2, t0, 31*8 // t2 = start of vector registers +#endif + add t3, t2, t4 // t3 = end of vector registers + +vector_clear_loop: + beq t2, t3, vector_clear_done // Done if reached end + sd zero, 0(t2) // Clear 8 bytes + addi t2, t2, 8 // Move to next 8 bytes + j vector_clear_loop + +vector_clear_done: +#endif + + add t2, t0, t4 +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + sd zero, 64*8(t2) // Reserved word (0) #else - sd zero, 31*8(t0) // Reserved word (0) + sd zero, 31*8(t2) // Reserved word (0) #endif /* Setup stack pointer. */ diff --git a/ports/risc-v64/gnu/src/tx_thread_system_return.S b/ports/risc-v64/gnu/src/tx_thread_system_return.S index b7dc9f3aa..2c7a2c011 100644 --- a/ports/risc-v64/gnu/src/tx_thread_system_return.S +++ b/ports/risc-v64/gnu/src/tx_thread_system_return.S @@ -73,6 +73,12 @@ _tx_thread_system_return: #else addi sp, sp, -16*8 // Allocate space on the stack - without floating point enabled #endif +#if defined(__riscv_vector) + csrr t1, vlenb // Get vector register byte length + slli t1, t1, 5 // Multiply by 32 (number of vector registers) + addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr + sub sp, sp, t1 // Allocate vector space on the stack +#endif /* Store floating point preserved registers. */ #if defined(__riscv_float_abi_single) @@ -107,6 +113,36 @@ _tx_thread_system_return: sd t0, 27*8(sp) // Store fcsr #endif +#if defined(__riscv_vector) + /* Store vector registers and CSRs */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, sp, 28*8 +#else + addi t1, sp, 15*8 +#endif + /* Store vector CSRs */ + csrr t2, vstart // Store vstart + sd t2, 0*8(t1) + csrr t2, vtype // Store vtype + sd t2, 1*8(t1) + csrr t2, vl // Store vl + sd t2, 2*8(t1) + csrr t2, vcsr // Store vcsr + sd t2, 3*8(t1) + + /* Store vector registers v0-v31 */ + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vse8.v v0, 0(t2) // Store v0 ~ v7 + add t2, t2, t3 + vse8.v v8, 0(t2) // Store v8 ~ v15 + add t2, t2, t3 + vse8.v v16, 0(t2) // Store v16 ~ v23 + add t2, t2, t3 + vse8.v v24, 0(t2) // Store v24 ~ v31 + add t2, t2, t3 +#endif + sd zero, 0(sp) // Solicited stack type sd ra, 13*8(sp) // Save return address sd s0, 12*8(sp) // Save s0 From dfafc96149630f2a098559aecf69fa49b9565d22 Mon Sep 17 00:00:00 2001 From: "shuta.lst" Date: Tue, 7 Apr 2026 14:03:24 +0800 Subject: [PATCH 08/29] RISC-V64 qemu_virt example support RVV Extension; --- ports/risc-v64/gnu/example_build/qemu_virt/csr.h | 1 + .../gnu/example_build/qemu_virt/demo_threadx.c | 5 +++++ ports/risc-v64/gnu/example_build/qemu_virt/entry.s | 4 ++++ ports/risc-v64/gnu/example_build/qemu_virt/link.lds | 3 +++ .../example_build/qemu_virt/tx_initialize_low_level.S | 11 +++++++++++ 5 files changed, 24 insertions(+) diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/csr.h b/ports/risc-v64/gnu/example_build/qemu_virt/csr.h index 4e222375d..6d35a07f7 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/csr.h +++ b/ports/risc-v64/gnu/example_build/qemu_virt/csr.h @@ -21,6 +21,7 @@ #define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable. #define MSTATUS_MPIE (1L << 7) #define MSTATUS_FS (1L << 13) +#define MSTATUS_VS (1L << 9) // Machine-mode Interrupt Enable #define MIE_MTIE (1L << 7) diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c b/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c index aff197db3..4a7e8b9b8 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c +++ b/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c @@ -4,8 +4,13 @@ #include "tx_api.h" #include "uart.h" +#if defined(__riscv_vector) +#define DEMO_STACK_SIZE (1024 + 16448) /* 16448 for RVV Extension */ +#define DEMO_BYTE_POOL_SIZE (9180 + 148032) /* 148032 for RVV Extension */ +#else #define DEMO_STACK_SIZE 1024 #define DEMO_BYTE_POOL_SIZE 9180 +#endif #define DEMO_BLOCK_POOL_SIZE 100 #define DEMO_QUEUE_SIZE 100 diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/entry.s b/ports/risc-v64/gnu/example_build/qemu_virt/entry.s index 9b202ca16..791d08eb2 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/entry.s +++ b/ports/risc-v64/gnu/example_build/qemu_virt/entry.s @@ -41,7 +41,11 @@ _start: li x30, 0 li x31, 0 la t0, _sysstack_start +#ifdef __riscv_vector + li t1, 0x5000 +#else li t1, 0x1000 +#endif add sp, t0, t1 la t0, _bss_start la t1, _bss_end diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/link.lds b/ports/risc-v64/gnu/example_build/qemu_virt/link.lds index b2d0d2df1..42544da1d 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/link.lds +++ b/ports/risc-v64/gnu/example_build/qemu_virt/link.lds @@ -42,6 +42,9 @@ SECTIONS . = ALIGN(4096); _sysstack_start = .; . += 0x1000; +#ifdef __riscv_vector + . += 0x4000; +#endif _sysstack_end = .; } diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S index 3c4a00af8..e58f8034b 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S +++ b/ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S @@ -70,6 +70,13 @@ #else addi sp, sp, -256 // Allocate space for all registers - without floating point enabled (32*8) #endif +#if defined(__riscv_vector) + /* Allocate space for vector registers */ + csrr t4, vlenb + slli t4, t4, 5 + addi t4, t4, 4*8 + sub sp, sp, t4 +#endif sd x1, 224(sp) // Store RA (28*8 = 224, because call will override ra [ra is a callee register in riscv]) @@ -153,6 +160,10 @@ _tx_initialize_low_level: li t0, MSTATUS_FS csrrs zero, mstatus, t0 // set MSTATUS_FS bit to open f/d isa in riscv fscsr x0 +#endif +#ifdef __riscv_vector + li t0, MSTATUS_VS + csrrs zero, mstatus, t0 // set MSTATUS_VS bit to open vector isa in riscv #endif addi sp, sp, -8 sd ra, 0(sp) From 2cdebde30a5213261313b9cb2a903fa4511435d5 Mon Sep 17 00:00:00 2001 From: Jonathan Blanchard Date: Sun, 12 Apr 2026 10:17:10 -0400 Subject: [PATCH 09/29] Fix default TX_TIMER_TICKS_PER_SECOND default value in tx_user_sample.h Changed default value to TX_16_ULONG. --- common/inc/tx_user_sample.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/inc/tx_user_sample.h b/common/inc/tx_user_sample.h index 9621c30cd..0733c16c4 100644 --- a/common/inc/tx_user_sample.h +++ b/common/inc/tx_user_sample.h @@ -95,7 +95,7 @@ the new value must be a multiple of ULONG. */ /* -#define TX_QUEUE_MESSAGE_MAX_SIZE TX_ULONG_16 +#define TX_QUEUE_MESSAGE_MAX_SIZE TX_16_ULONG */ /* Define the common timer tick reference for use by other middleware components. The default From 98e4754381b24e18b3712d1cc4ff528a93b13a77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Wed, 15 Apr 2026 10:52:14 -0400 Subject: [PATCH 10/29] build: add conditional CMake support for ThreadX SMP - Introduce THREADX_SMP option in root CMakeLists.txt. - Implement conditional source and port directory selection for SMP builds. - Add CMake support for common_smp and Cortex-A9 SMP port. - Fix linker flags in Cortex-A9 SMP sample build script. - Remove duplicate invalidateCaches_IS declarations in v7.h headers. Assisted-by: Gemini (Experimental) --- CMakeLists.txt | 24 +- cmake/cortex_a9.cmake | 13 ++ common_smp/CMakeLists.txt | 218 ++++++++++++++++++ ports/cortex_a12/gnu/example_build/v7.h | 1 - ports/cortex_a15/gnu/example_build/v7.h | 1 - ports/cortex_a17/gnu/example_build/v7.h | 1 - ports/cortex_a5/gnu/example_build/v7.h | 1 - ports/cortex_a7/gnu/example_build/v7.h | 1 - ports/cortex_a8/gnu/example_build/v7.h | 1 - ports/cortex_a9/gnu/example_build/v7.h | 1 - .../threadx/ports/gnu/example_build/v7.h | 1 - ports_smp/cortex_a9_smp/gnu/CMakeLists.txt | 31 +++ .../example_build/build_threadx_sample.bat | 2 +- 13 files changed, 284 insertions(+), 12 deletions(-) create mode 100644 cmake/cortex_a9.cmake create mode 100644 common_smp/CMakeLists.txt create mode 100644 ports_smp/cortex_a9_smp/gnu/CMakeLists.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index 9d348e684..e988d3a60 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -11,6 +11,21 @@ endif() if(NOT DEFINED THREADX_TOOLCHAIN) message(FATAL_ERROR "Error: THREADX_TOOLCHAIN not defined") endif() + +option(THREADX_SMP "Build ThreadX SMP version" OFF) + +if(THREADX_SMP) + set(TX_PORT_DIR "ports_smp") + set(TX_COMMON_DIR "common_smp") + set(TX_ARCH_DIR "${THREADX_ARCH}_smp") + message(STATUS "Building ThreadX SMP version") +else() + set(TX_PORT_DIR "ports") + set(TX_COMMON_DIR "common") + set(TX_ARCH_DIR "${THREADX_ARCH}") + message(STATUS "Building standard ThreadX version") +endif() + message(STATUS "THREADX_ARCH: ${THREADX_ARCH}") message(STATUS "THREADX_TOOLCHAIN: ${THREADX_TOOLCHAIN}") @@ -25,11 +40,11 @@ set(CUSTOM_INC_DIR ${CMAKE_CURRENT_BINARY_DIR}/custom_inc) if(DEFINED THREADX_CUSTOM_PORT) add_subdirectory(${THREADX_CUSTOM_PORT} threadx_port) else() - add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/ports/${THREADX_ARCH}/${THREADX_TOOLCHAIN}) + add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/${TX_PORT_DIR}/${TX_ARCH_DIR}/${THREADX_TOOLCHAIN}) endif() # Pick up the common stuff -add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/common) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/${TX_COMMON_DIR}) # Define the FreeRTOS adaptation layer add_library(freertos-threadx EXCLUDE_FROM_ALL) @@ -46,7 +61,7 @@ target_link_libraries(freertos-threadx PUBLIC threadx) # If the user provided an override, copy it to the custom directory if (NOT TX_USER_FILE) message(STATUS "Using default tx_user.h file") - set(TX_USER_FILE ${CMAKE_CURRENT_LIST_DIR}/common/inc/tx_user_sample.h) + set(TX_USER_FILE ${CMAKE_CURRENT_LIST_DIR}/${TX_COMMON_DIR}/inc/tx_user_sample.h) else() message(STATUS "Using custom tx_user.h file from ${TX_USER_FILE}") endif() @@ -56,6 +71,9 @@ target_include_directories(${PROJECT_NAME} ${CUSTOM_INC_DIR} ) target_compile_definitions(${PROJECT_NAME} PUBLIC "TX_INCLUDE_USER_DEFINE_FILE" ) +if(THREADX_SMP) + target_compile_definitions(${PROJECT_NAME} PUBLIC "TX_MPCORE" ) +endif() # Enable a build target that produces a ZIP file of all sources set(CPACK_SOURCE_GENERATOR "ZIP") diff --git a/cmake/cortex_a9.cmake b/cmake/cortex_a9.cmake new file mode 100644 index 000000000..b84963a47 --- /dev/null +++ b/cmake/cortex_a9.cmake @@ -0,0 +1,13 @@ +# Name of the target +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR cortex-a9) + +set(THREADX_ARCH "cortex_a9") +set(THREADX_TOOLCHAIN "gnu") + +set(MCPU_FLAGS "-marm -mcpu=cortex-a9") +set(VFP_FLAGS "") +set(SPEC_FLAGS "--specs=nosys.specs") +# set(LD_FLAGS "-nostartfiles") + +include(${CMAKE_CURRENT_LIST_DIR}/arm-none-eabi.cmake) diff --git a/common_smp/CMakeLists.txt b/common_smp/CMakeLists.txt new file mode 100644 index 000000000..80b9d3154 --- /dev/null +++ b/common_smp/CMakeLists.txt @@ -0,0 +1,218 @@ +function(target_sources_if_not_overridden filename) + list(FIND TX_SRC_OVERRIDES ${filename} OVERRIDE_FOUND) + if( OVERRIDE_FOUND EQUAL -1 ) + # message(STATUS "** Using original ${filename} from common_smp/src **") + target_sources(${PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/src/${filename}) + endif() +endfunction() + +# These files can be overridden by setting them in the variable list named TX_SRC_OVERRIDES +target_sources_if_not_overridden("tx_thread_delete.c") +target_sources_if_not_overridden("tx_thread_reset.c") + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_allocate.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_pool_cleanup.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_pool_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_pool_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_pool_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_pool_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_pool_performance_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_pool_performance_system_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_pool_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_block_release.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_allocate.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_pool_cleanup.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_pool_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_pool_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_pool_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_pool_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_pool_performance_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_pool_performance_system_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_pool_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_pool_search.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_byte_release.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_cleanup.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_performance_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_performance_system_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_set_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_event_flags_set.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_high_level.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_kernel_enter.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_kernel_setup.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_misra.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_cleanup.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_performance_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_performance_system_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_priority_change.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_mutex_put.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_cleanup.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_flush.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_front_send.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_performance_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_performance_system_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_receive.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_send_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_queue_send.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_ceiling_put.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_cleanup.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_performance_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_performance_system_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_put_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_semaphore_put.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_entry_exit_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_identify.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_performance_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_performance_system_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_preemption_change.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_priority_change.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_relinquish.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_reset.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_resume.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_shell_entry.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_sleep.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_core_exclude_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_core_exclude.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_current_state_set.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_debug_entry_insert.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_high_level_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_rebalance_execute_list.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_utilities.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_analyze.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_error_handler.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_error_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_suspend.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_preempt_check.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_resume.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_suspend.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_terminate.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_time_slice_change.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_time_slice.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_timeout.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_wait_abort.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_time_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_time_set.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_activate.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_change.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_deactivate.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_expiration_process.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_performance_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_performance_system_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_smp_core_exclude_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_smp_core_exclude.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_system_activate.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_system_deactivate.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_thread_entry.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_buffer_full_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_disable.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_enable.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_event_filter.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_event_unfilter.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_interrupt_control.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_isr_enter_insert.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_isr_exit_insert.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_object_register.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_object_unregister.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_trace_user_event_insert.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_block_allocate.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_block_pool_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_block_pool_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_block_pool_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_block_pool_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_block_release.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_byte_allocate.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_byte_pool_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_byte_pool_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_byte_pool_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_byte_pool_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_byte_release.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_event_flags_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_event_flags_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_event_flags_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_event_flags_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_event_flags_set_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_event_flags_set.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_mutex_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_mutex_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_mutex_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_mutex_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_mutex_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_mutex_put.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_queue_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_queue_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_queue_flush.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_queue_front_send.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_queue_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_queue_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_queue_receive.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_queue_send_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_queue_send.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_semaphore_ceiling_put.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_semaphore_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_semaphore_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_semaphore_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_semaphore_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_semaphore_prioritize.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_semaphore_put_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_semaphore_put.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_entry_exit_notify.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_info_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_preemption_change.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_priority_change.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_relinquish.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_reset.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_resume.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_suspend.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_terminate.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_time_slice_change.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_wait_abort.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_timer_activate.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_timer_change.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_timer_create.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_timer_deactivate.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_timer_delete.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_timer_info_get.c + # {{END_TARGET_SOURCES}} +) + +# Add the Common/inc directory to the project include list +target_include_directories(${PROJECT_NAME} + SYSTEM + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/cortex_a12/gnu/example_build/v7.h b/ports/cortex_a12/gnu/example_build/v7.h index c18b945c5..1133b0acc 100644 --- a/ports/cortex_a12/gnu/example_build/v7.h +++ b/ports/cortex_a12/gnu/example_build/v7.h @@ -37,7 +37,6 @@ void disableInterrupts(void); void invalidateCaches_IS(void); void cleanInvalidateDCache(void); -void invalidateCaches_IS(void); void enableCaches(void); void disableCaches(void); void invalidateCaches(void); diff --git a/ports/cortex_a15/gnu/example_build/v7.h b/ports/cortex_a15/gnu/example_build/v7.h index c18b945c5..1133b0acc 100644 --- a/ports/cortex_a15/gnu/example_build/v7.h +++ b/ports/cortex_a15/gnu/example_build/v7.h @@ -37,7 +37,6 @@ void disableInterrupts(void); void invalidateCaches_IS(void); void cleanInvalidateDCache(void); -void invalidateCaches_IS(void); void enableCaches(void); void disableCaches(void); void invalidateCaches(void); diff --git a/ports/cortex_a17/gnu/example_build/v7.h b/ports/cortex_a17/gnu/example_build/v7.h index c18b945c5..1133b0acc 100644 --- a/ports/cortex_a17/gnu/example_build/v7.h +++ b/ports/cortex_a17/gnu/example_build/v7.h @@ -37,7 +37,6 @@ void disableInterrupts(void); void invalidateCaches_IS(void); void cleanInvalidateDCache(void); -void invalidateCaches_IS(void); void enableCaches(void); void disableCaches(void); void invalidateCaches(void); diff --git a/ports/cortex_a5/gnu/example_build/v7.h b/ports/cortex_a5/gnu/example_build/v7.h index c18b945c5..1133b0acc 100644 --- a/ports/cortex_a5/gnu/example_build/v7.h +++ b/ports/cortex_a5/gnu/example_build/v7.h @@ -37,7 +37,6 @@ void disableInterrupts(void); void invalidateCaches_IS(void); void cleanInvalidateDCache(void); -void invalidateCaches_IS(void); void enableCaches(void); void disableCaches(void); void invalidateCaches(void); diff --git a/ports/cortex_a7/gnu/example_build/v7.h b/ports/cortex_a7/gnu/example_build/v7.h index c18b945c5..1133b0acc 100644 --- a/ports/cortex_a7/gnu/example_build/v7.h +++ b/ports/cortex_a7/gnu/example_build/v7.h @@ -37,7 +37,6 @@ void disableInterrupts(void); void invalidateCaches_IS(void); void cleanInvalidateDCache(void); -void invalidateCaches_IS(void); void enableCaches(void); void disableCaches(void); void invalidateCaches(void); diff --git a/ports/cortex_a8/gnu/example_build/v7.h b/ports/cortex_a8/gnu/example_build/v7.h index c18b945c5..1133b0acc 100644 --- a/ports/cortex_a8/gnu/example_build/v7.h +++ b/ports/cortex_a8/gnu/example_build/v7.h @@ -37,7 +37,6 @@ void disableInterrupts(void); void invalidateCaches_IS(void); void cleanInvalidateDCache(void); -void invalidateCaches_IS(void); void enableCaches(void); void disableCaches(void); void invalidateCaches(void); diff --git a/ports/cortex_a9/gnu/example_build/v7.h b/ports/cortex_a9/gnu/example_build/v7.h index c18b945c5..1133b0acc 100644 --- a/ports/cortex_a9/gnu/example_build/v7.h +++ b/ports/cortex_a9/gnu/example_build/v7.h @@ -37,7 +37,6 @@ void disableInterrupts(void); void invalidateCaches_IS(void); void cleanInvalidateDCache(void); -void invalidateCaches_IS(void); void enableCaches(void); void disableCaches(void); void invalidateCaches(void); diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h index c18b945c5..1133b0acc 100644 --- a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h @@ -37,7 +37,6 @@ void disableInterrupts(void); void invalidateCaches_IS(void); void cleanInvalidateDCache(void); -void invalidateCaches_IS(void); void enableCaches(void); void disableCaches(void); void invalidateCaches(void); diff --git a/ports_smp/cortex_a9_smp/gnu/CMakeLists.txt b/ports_smp/cortex_a9_smp/gnu/CMakeLists.txt new file mode 100644 index 000000000..4b13e1a15 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/CMakeLists.txt @@ -0,0 +1,31 @@ +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_irq_nesting_end.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_irq_nesting_start.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_core_get.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_core_preempt.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_current_state_get.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_current_thread_get.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_initialize_wait.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_low_level_initialize.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_protect.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_time_get.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_unprotect.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_vectored_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat b/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat index 0e2611181..07f887eda 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat +++ b/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat @@ -5,4 +5,4 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_SCU.S arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_Mutexes.S arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_PrivateTimer.S arm-none-eabi-gcc -c -g -mcpu=cortex-a9 v7.S -arm-none-eabi-gcc -T sample_threadx.ld -e Vectors -o sample_threadx.axf MP_PrivateTimer.o MP_GIC.o MP_Mutexes.o MP_SCU.o sample_threadx.o startup.o v7.o tx.a -Wl,-M > sample_threadx.map +arm-none-eabi-gcc -T sample_threadx.ld -e Vectors -mcpu=cortex-a9 --specs=nosys.specs -o sample_threadx.axf MP_PrivateTimer.o MP_GIC.o MP_Mutexes.o MP_SCU.o sample_threadx.o startup.o v7.o tx.a -Wl,-M > sample_threadx.map From 33efad3fee3414aef0d99e416361226b8568fd26 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Wed, 29 Apr 2026 09:10:57 -0400 Subject: [PATCH 11/29] Fixed race condition and message loss in Cortex-M ports (#523) * Fixed race condition and message loss in Cortex-M GNU, AC6, and IAR ports (#516) - Added compiler memory barriers to BASEPRI management functions in tx_port.h. - Added architectural barriers (DSB/ISB) to scheduler return paths in tx_port.h and tx_thread_system_return.S to prevent fall-through before context switch. - These changes address spurious thread resumption and lost messages, especially when TX_NOT_INTERRUPTABLE is enabled. - These changes ensure that pending interrupts (specifically PendSV) are recognised before subsequent instructions are executed, following Kairalite's feedback and ARM architectural guidelines. Assisted-by: Gemini (Gemini 2.0 Flash) ----- * Added a comment in common/tx_queue_cleanup to document why the NI path omits revalidation guards - In `TX_NOT_INTERRUPTABLE` mode, the caller keeps interrupts disabled across the entire cleanup call, so the race window that makes the guards necessary in the interruptable path cannot occur. Add a comment explaining this, and noting that all paths that resume a suspended thread clear tx_thread_suspend_cleanup before calling _tx_thread_system_ni_resume, making double-cleanup impossible. This prevents future false-positive suggestions (e.g. from AI tools) to add redundant checks to the NI path. Relates to: eclipse-threadx/threadx#516 Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- common/src/tx_queue_cleanup.c | 13 +++++++++ ports/cortex_m0/gnu/inc/tx_port.h | 4 +++ .../gnu/src/tx_thread_system_return.S | 16 +++++++---- ports/cortex_m0/iar/inc/tx_port.h | 1 + .../iar/src/tx_thread_system_return.s | 7 ++++- ports/cortex_m23/ac6/inc/tx_port.h | 3 +++ .../ac6/src/tx_thread_system_return.S | 4 +++ ports/cortex_m23/gnu/inc/tx_port.h | 4 +++ .../gnu/src/tx_thread_system_return.S | 5 ++++ ports/cortex_m23/iar/inc/tx_port.h | 1 + .../iar/src/tx_thread_system_return.s | 27 +++++++++++-------- ports/cortex_m3/ac6/inc/tx_port.h | 12 +++++---- .../ac6/src/tx_thread_system_return.S | 4 +++ ports/cortex_m3/gnu/inc/tx_port.h | 7 +++-- .../gnu/src/tx_thread_system_return.S | 6 +++++ ports/cortex_m3/iar/inc/tx_port.h | 12 +++++---- .../iar/src/tx_thread_system_return.s | 27 +++++++++++-------- ports/cortex_m33/ac6/inc/tx_port.h | 6 ++++- .../ac6/src/tx_thread_system_return.S | 4 +++ ports/cortex_m33/gnu/inc/tx_port.h | 6 ++++- .../gnu/src/tx_thread_system_return.S | 6 +++++ ports/cortex_m33/iar/inc/tx_port.h | 6 ++++- .../iar/src/tx_thread_system_return.s | 27 +++++++++++-------- ports/cortex_m4/ac6/inc/tx_port.h | 26 +++++++++++++++--- .../ac6/src/tx_thread_system_return.S | 4 +++ ports/cortex_m4/gnu/inc/tx_port.h | 11 +++++--- .../gnu/src/tx_thread_system_return.S | 6 +++++ ports/cortex_m4/iar/inc/tx_port.h | 12 +++++---- .../iar/src/tx_thread_system_return.s | 27 +++++++++++-------- ports/cortex_m55/gnu/inc/tx_port.h | 7 ++++- .../gnu/src/tx_thread_system_return.S | 6 +++++ ports/cortex_m55/iar/inc/tx_port.h | 1 + .../iar/src/tx_thread_system_return.s | 27 +++++++++++-------- ports/cortex_m7/ac6/inc/tx_port.h | 12 +++++---- .../ac6/src/tx_thread_system_return.S | 4 +++ ports/cortex_m7/gnu/inc/tx_port.h | 13 ++++++--- .../gnu/src/tx_thread_system_return.S | 6 +++++ ports/cortex_m7/iar/inc/tx_port.h | 12 +++++---- .../iar/src/tx_thread_system_return.s | 27 +++++++++++-------- ports/cortex_m85/gnu/inc/tx_port.h | 7 ++++- .../gnu/src/tx_thread_system_return.S | 6 +++++ ports/cortex_m85/iar/inc/tx_port.h | 5 +++- .../iar/src/tx_thread_system_return.s | 27 +++++++++++-------- 43 files changed, 327 insertions(+), 127 deletions(-) diff --git a/common/src/tx_queue_cleanup.c b/common/src/tx_queue_cleanup.c index 05a423b38..906071836 100644 --- a/common/src/tx_queue_cleanup.c +++ b/common/src/tx_queue_cleanup.c @@ -109,6 +109,19 @@ TX_THREAD *previous_thread; { #else + /* TX_NOT_INTERRUPTABLE path: the revalidation guards present in the + interruptable path above (cleanup pointer, suspension sequence, NULL + queue pointer, queue ID, and suspended count checks) are intentionally + omitted here. Those guards exist to handle the race window that opens + when the interruptable path calls TX_RESTORE before invoking cleanup, + allowing another context to service or abort the suspension in between. + In TX_NOT_INTERRUPTABLE mode the caller keeps interrupts disabled across + the entire cleanup call, so that race window never exists. Additionally, + every path that resumes a suspended thread (tx_queue_send, tx_queue_receive, + tx_queue_flush, tx_queue_delete) clears tx_thread_suspend_cleanup before + calling _tx_thread_system_ni_resume, making a double-cleanup impossible + under the NI serialisation guarantee. */ + /* Setup pointer to queue control block. */ queue_ptr = TX_VOID_TO_QUEUE_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); #endif diff --git a/ports/cortex_m0/gnu/inc/tx_port.h b/ports/cortex_m0/gnu/inc/tx_port.h index 9b315869f..ddeff5c5e 100644 --- a/ports/cortex_m0/gnu/inc/tx_port.h +++ b/ports/cortex_m0/gnu/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -322,11 +324,13 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); + __asm__ volatile ("isb 0xF " : : : "memory"); } } diff --git a/ports/cortex_m0/gnu/src/tx_thread_system_return.S b/ports/cortex_m0/gnu/src/tx_thread_system_return.S index d798994ea..6019b299d 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m0/gnu/src/tx_thread_system_return.S @@ -5,11 +5,14 @@ @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. @ * -@ * SPDX-License-Identifier: MIT -@ **************************************************************************/ -@ -@ -@/**************************************************************************/ +* SPDX-License-Identifier: MIT +**************************************************************************/ + +// Some portions generated by Gemini (Gemini 2.0 Flash). + + +/**************************************************************************/ + @/**************************************************************************/ @/** */ @/** ThreadX Component */ @@ -72,12 +75,15 @@ _tx_thread_system_return: LDR r0, =0x10000000 @ Load PENDSVSET bit LDR r1, =0xE000ED04 @ Load NVIC base STR r0, [r1] @ Set PENDSVBIT in ICSR + DSB #0xF @ Ensure memory access is complete + ISB #0xF @ Flush pipeline MRS r0, IPSR @ Pickup IPSR CMP r0, #0 @ Is it a thread returning? BNE _isr_context @ If ISR, skip interrupt enable MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK CPSIE i @ Enable interrupts MSR PRIMASK, r1 @ Restore original interrupt posture + ISB #0xF @ Flush pipeline _isr_context: BX lr @ Return to caller @/* } */ diff --git a/ports/cortex_m0/iar/inc/tx_port.h b/ports/cortex_m0/iar/inc/tx_port.h index af5f58bb8..c92c71f81 100644 --- a/ports/cortex_m0/iar/inc/tx_port.h +++ b/ports/cortex_m0/iar/inc/tx_port.h @@ -313,6 +313,7 @@ __istate_t interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_IPSR() == 0) { interrupt_save = __get_interrupt_state(); diff --git a/ports/cortex_m0/iar/src/tx_thread_system_return.s b/ports/cortex_m0/iar/src/tx_thread_system_return.s index da8a481ea..9426a137d 100644 --- a/ports/cortex_m0/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m0/iar/src/tx_thread_system_return.s @@ -1,5 +1,6 @@ -;/*************************************************************************** +;*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,8 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ + +; Some portions generated by Gemini (Gemini 2.0 Flash). ; ; ;/**************************************************************************/ @@ -68,6 +71,8 @@ _tx_thread_system_return: LDR r0, =0x10000000 ; Load PENDSVSET bit LDR r1, =0xE000ED04 ; Load NVIC base STR r0, [r1] ; Set PENDSVBIT in ICSR + DSB SY ; Ensure memory access is complete + ISB SY ; Flush pipeline MRS r0, IPSR ; Pickup IPSR CMP r0, #0 ; Is it a thread returning? BNE _isr_context ; If ISR, skip interrupt enable diff --git a/ports/cortex_m23/ac6/inc/tx_port.h b/ports/cortex_m23/ac6/inc/tx_port.h index 5ae0b62b0..2140af537 100644 --- a/ports/cortex_m23/ac6/inc/tx_port.h +++ b/ports/cortex_m23/ac6/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -376,6 +378,7 @@ unsigned int was_masked; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (_get_ipsr() == 0) { was_masked = __disable_irq(); diff --git a/ports/cortex_m23/ac6/src/tx_thread_system_return.S b/ports/cortex_m23/ac6/src/tx_thread_system_return.S index d85981da1..c0bfe023d 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m23/ac6/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -74,6 +76,8 @@ _tx_thread_system_return: LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m23/gnu/inc/tx_port.h b/ports/cortex_m23/gnu/inc/tx_port.h index b1eab9e38..b66811392 100644 --- a/ports/cortex_m23/gnu/inc/tx_port.h +++ b/ports/cortex_m23/gnu/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -389,11 +391,13 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (_get_ipsr() == 0) { interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); + __asm__ volatile ("isb 0xF " : : : "memory"); } } diff --git a/ports/cortex_m23/gnu/src/tx_thread_system_return.S b/ports/cortex_m23/gnu/src/tx_thread_system_return.S index a14fdba3a..ca5408d74 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m23/gnu/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -74,12 +76,15 @@ _tx_thread_system_return: LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline _isr_context: BX lr // Return to caller // } diff --git a/ports/cortex_m23/iar/inc/tx_port.h b/ports/cortex_m23/iar/inc/tx_port.h index be6bebd55..dee22f50c 100644 --- a/ports/cortex_m23/iar/inc/tx_port.h +++ b/ports/cortex_m23/iar/inc/tx_port.h @@ -399,6 +399,7 @@ __istate_t interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_IPSR() == 0) { interrupt_save = __get_interrupt_state(); diff --git a/ports/cortex_m23/iar/src/tx_thread_system_return.s b/ports/cortex_m23/iar/src/tx_thread_system_return.s index 91ef52c72..da4b6d045 100644 --- a/ports/cortex_m23/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m23/iar/src/tx_thread_system_return.s @@ -1,16 +1,19 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ +;*************************************************************************** +;* Copyright (c) 2024 Microsoft Corporation +;* Copyright (c) 2026-present Eclipse ThreadX contributors +;* +;* This program and the accompanying materials are made available under the +;* terms of the MIT License which is available at +;* https://opensource.org/licenses/MIT. +;* +;* SPDX-License-Identifier: MIT +;************************************************************************** +; Some portions generated by Gemini (Gemini 2.0 Flash). + + +;************************************************************************** -/**************************************************************************/ /**************************************************************************/ /** */ /** ThreadX Component */ @@ -65,6 +68,8 @@ _tx_thread_system_return: LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR + DSB SY // Ensure memory access is complete + ISB SY // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h index 0a25ae64f..32604f3cf 100644 --- a/ports/cortex_m3/ac6/inc/tx_port.h +++ b/ports/cortex_m3/ac6/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -539,20 +541,20 @@ unsigned int posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } -#else +#endif + __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) { __asm__ volatile ("CPSIE i": : : "memory"); } -#endif __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture) { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); - //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory"); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -578,6 +580,7 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_interrupt_posture(); @@ -589,7 +592,6 @@ unsigned int interrupt_save; __restore_interrupt(interrupt_save); } } - #define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupt(interrupt_save); diff --git a/ports/cortex_m3/ac6/src/tx_thread_system_return.S b/ports/cortex_m3/ac6/src/tx_thread_system_return.S index e1c5c2a2c..a8654f6ba 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m3/ac6/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -73,6 +75,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m3/gnu/inc/tx_port.h b/ports/cortex_m3/gnu/inc/tx_port.h index 23affb8bf..391688bd6 100644 --- a/ports/cortex_m3/gnu/inc/tx_port.h +++ b/ports/cortex_m3/gnu/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -539,7 +541,7 @@ unsigned int posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } #else __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) @@ -552,7 +554,6 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); - //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -578,6 +579,7 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_interrupt_posture(); @@ -587,6 +589,7 @@ unsigned int interrupt_save; __enable_interrupts(); #endif __restore_interrupt(interrupt_save); + __asm__ volatile ("isb 0xF " : : : "memory"); } } diff --git a/ports/cortex_m3/gnu/src/tx_thread_system_return.S b/ports/cortex_m3/gnu/src/tx_thread_system_return.S index 9d9a32fc9..92ad3f628 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m3/gnu/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -73,6 +75,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -81,10 +85,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #endif _isr_context: BX lr // Return to caller diff --git a/ports/cortex_m3/iar/inc/tx_port.h b/ports/cortex_m3/iar/inc/tx_port.h index ff8b75ca2..1b298161b 100644 --- a/ports/cortex_m3/iar/inc/tx_port.h +++ b/ports/cortex_m3/iar/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -539,20 +541,20 @@ unsigned int posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } -#else +#endif + __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) { __asm__ volatile ("CPSIE i": : : "memory"); } -#endif __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture) { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); - //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory"); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -578,6 +580,7 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_interrupt_posture(); @@ -589,7 +592,6 @@ unsigned int interrupt_save; __restore_interrupt(interrupt_save); } } - #define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupt(interrupt_save); diff --git a/ports/cortex_m3/iar/src/tx_thread_system_return.s b/ports/cortex_m3/iar/src/tx_thread_system_return.s index 712a6e5ce..8bd4ca820 100644 --- a/ports/cortex_m3/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m3/iar/src/tx_thread_system_return.s @@ -1,16 +1,19 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ +;*************************************************************************** +;* Copyright (c) 2024 Microsoft Corporation +;* Copyright (c) 2026-present Eclipse ThreadX contributors +;* +;* This program and the accompanying materials are made available under the +;* terms of the MIT License which is available at +;* https://opensource.org/licenses/MIT. +;* +;* SPDX-License-Identifier: MIT +;************************************************************************** +; Some portions generated by Gemini (Gemini 2.0 Flash). + + +;************************************************************************** -/**************************************************************************/ /**************************************************************************/ /** */ /** ThreadX Component */ @@ -70,6 +73,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB SY // Ensure memory access is complete + ISB SY // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h index e2a8f6e6a..a706ff62f 100644 --- a/ports/cortex_m33/ac6/inc/tx_port.h +++ b/ports/cortex_m33/ac6/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -541,7 +543,7 @@ UINT posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } #else __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) @@ -554,6 +556,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -579,6 +582,7 @@ UINT interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (_tx_ipsr_get() == 0) { interrupt_save = __get_interrupt_posture(); diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S index 3c97b666f..e57b28ea2 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m33/ac6/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -74,6 +76,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h index 727e9fce5..2b962069f 100644 --- a/ports/cortex_m33/gnu/inc/tx_port.h +++ b/ports/cortex_m33/gnu/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -541,7 +543,7 @@ UINT posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } #else __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) @@ -579,6 +581,7 @@ UINT interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (_tx_ipsr_get() == 0) { interrupt_save = __get_interrupt_posture(); @@ -588,6 +591,7 @@ UINT interrupt_save; __enable_interrupts(); #endif __restore_interrupt(interrupt_save); + __asm__ volatile ("isb 0xF " : : : "memory"); } } diff --git a/ports/cortex_m33/gnu/src/tx_thread_system_return.S b/ports/cortex_m33/gnu/src/tx_thread_system_return.S index 17db56a59..156093933 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m33/gnu/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -74,6 +76,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -82,10 +86,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #endif _isr_context: BX lr // Return to caller diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h index 62f20620a..6298ddcb0 100644 --- a/ports/cortex_m33/iar/inc/tx_port.h +++ b/ports/cortex_m33/iar/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -541,7 +543,7 @@ UINT posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } #else __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) @@ -554,6 +556,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -579,6 +582,7 @@ UINT interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (_tx_ipsr_get() == 0) { interrupt_save = __get_interrupt_posture(); diff --git a/ports/cortex_m33/iar/src/tx_thread_system_return.s b/ports/cortex_m33/iar/src/tx_thread_system_return.s index 442e0e141..83eb4a66a 100644 --- a/ports/cortex_m33/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m33/iar/src/tx_thread_system_return.s @@ -1,16 +1,19 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ +;*************************************************************************** +;* Copyright (c) 2024 Microsoft Corporation +;* Copyright (c) 2026-present Eclipse ThreadX contributors +;* +;* This program and the accompanying materials are made available under the +;* terms of the MIT License which is available at +;* https://opensource.org/licenses/MIT. +;* +;* SPDX-License-Identifier: MIT +;************************************************************************** +; Some portions generated by Gemini (Gemini 2.0 Flash). + + +;************************************************************************** -/**************************************************************************/ /**************************************************************************/ /** */ /** ThreadX Component */ @@ -69,6 +72,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB SY // Ensure memory access is complete + ISB SY // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h index fa109c522..c35bb424a 100644 --- a/ports/cortex_m4/ac6/inc/tx_port.h +++ b/ports/cortex_m4/ac6/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -539,20 +541,20 @@ unsigned int posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } -#else +#endif + __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) { __asm__ volatile ("CPSIE i": : : "memory"); } -#endif __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture) { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); - //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory"); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -574,6 +576,22 @@ unsigned int int_posture; __attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) { +unsigned int interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_interrupt_posture(); +#ifdef TX_PORT_USE_BASEPRI + __set_basepri_value(0); +#else + __enable_interrupts(); +#endif + __restore_interrupt(interrupt_save); + } +} unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ diff --git a/ports/cortex_m4/ac6/src/tx_thread_system_return.S b/ports/cortex_m4/ac6/src/tx_thread_system_return.S index b4348f9db..4c5068ee9 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m4/ac6/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -73,6 +75,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m4/gnu/inc/tx_port.h b/ports/cortex_m4/gnu/inc/tx_port.h index 7c2b04c58..a415dfbeb 100644 --- a/ports/cortex_m4/gnu/inc/tx_port.h +++ b/ports/cortex_m4/gnu/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -539,9 +541,10 @@ unsigned int posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } -#else +#endif + __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) { __asm__ volatile ("CPSIE i": : : "memory"); @@ -552,7 +555,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); - //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory"); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -578,6 +581,7 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_interrupt_posture(); @@ -587,6 +591,7 @@ unsigned int interrupt_save; __enable_interrupts(); #endif __restore_interrupt(interrupt_save); + __asm__ volatile ("isb 0xF " : : : "memory"); } } diff --git a/ports/cortex_m4/gnu/src/tx_thread_system_return.S b/ports/cortex_m4/gnu/src/tx_thread_system_return.S index 8c4a09fd1..4709af37f 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m4/gnu/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -73,6 +75,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -81,10 +85,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #endif _isr_context: BX lr // Return to caller diff --git a/ports/cortex_m4/iar/inc/tx_port.h b/ports/cortex_m4/iar/inc/tx_port.h index 1253befaf..85fe8e6e0 100644 --- a/ports/cortex_m4/iar/inc/tx_port.h +++ b/ports/cortex_m4/iar/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -539,20 +541,20 @@ unsigned int posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } -#else +#endif + __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) { __asm__ volatile ("CPSIE i": : : "memory"); } -#endif __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture) { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); - //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory"); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -578,6 +580,7 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_interrupt_posture(); @@ -589,7 +592,6 @@ unsigned int interrupt_save; __restore_interrupt(interrupt_save); } } - #define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupt(interrupt_save); diff --git a/ports/cortex_m4/iar/src/tx_thread_system_return.s b/ports/cortex_m4/iar/src/tx_thread_system_return.s index 4f8b9870f..f9a668d96 100644 --- a/ports/cortex_m4/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m4/iar/src/tx_thread_system_return.s @@ -1,16 +1,19 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ +;*************************************************************************** +;* Copyright (c) 2024 Microsoft Corporation +;* Copyright (c) 2026-present Eclipse ThreadX contributors +;* +;* This program and the accompanying materials are made available under the +;* terms of the MIT License which is available at +;* https://opensource.org/licenses/MIT. +;* +;* SPDX-License-Identifier: MIT +;************************************************************************** +; Some portions generated by Gemini (Gemini 2.0 Flash). + + +;************************************************************************** -/**************************************************************************/ /**************************************************************************/ /** */ /** ThreadX Component */ @@ -70,6 +73,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB SY // Ensure memory access is complete + ISB SY // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m55/gnu/inc/tx_port.h b/ports/cortex_m55/gnu/inc/tx_port.h index a70426fa6..ff5b001ab 100644 --- a/ports/cortex_m55/gnu/inc/tx_port.h +++ b/ports/cortex_m55/gnu/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -541,7 +543,7 @@ UINT posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } #else __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) @@ -554,6 +556,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -579,6 +582,7 @@ UINT interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (_tx_ipsr_get() == 0) { interrupt_save = __get_interrupt_posture(); @@ -588,6 +592,7 @@ UINT interrupt_save; __enable_interrupts(); #endif __restore_interrupt(interrupt_save); + __asm__ volatile ("isb 0xF " : : : "memory"); } } diff --git a/ports/cortex_m55/gnu/src/tx_thread_system_return.S b/ports/cortex_m55/gnu/src/tx_thread_system_return.S index 0fc717b99..f13f832a6 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m55/gnu/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -74,6 +76,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -82,10 +86,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #endif _isr_context: BX lr // Return to caller diff --git a/ports/cortex_m55/iar/inc/tx_port.h b/ports/cortex_m55/iar/inc/tx_port.h index b8a389f55..c1b94ea0d 100644 --- a/ports/cortex_m55/iar/inc/tx_port.h +++ b/ports/cortex_m55/iar/inc/tx_port.h @@ -579,6 +579,7 @@ UINT interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (_tx_ipsr_get() == 0) { interrupt_save = __get_interrupt_posture(); diff --git a/ports/cortex_m55/iar/src/tx_thread_system_return.s b/ports/cortex_m55/iar/src/tx_thread_system_return.s index 2762f49e7..20493afcb 100644 --- a/ports/cortex_m55/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m55/iar/src/tx_thread_system_return.s @@ -1,16 +1,19 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ +;*************************************************************************** +;* Copyright (c) 2024 Microsoft Corporation +;* Copyright (c) 2026-present Eclipse ThreadX contributors +;* +;* This program and the accompanying materials are made available under the +;* terms of the MIT License which is available at +;* https://opensource.org/licenses/MIT. +;* +;* SPDX-License-Identifier: MIT +;************************************************************************** +; Some portions generated by Gemini (Gemini 2.0 Flash). + + +;************************************************************************** -/**************************************************************************/ /**************************************************************************/ /** */ /** ThreadX Component */ @@ -69,6 +72,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB SY // Ensure memory access is complete + ISB SY // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h index d3b3bb019..d8c2b51e7 100644 --- a/ports/cortex_m7/ac6/inc/tx_port.h +++ b/ports/cortex_m7/ac6/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -539,20 +541,20 @@ unsigned int posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } -#else +#endif + __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) { __asm__ volatile ("CPSIE i": : : "memory"); } -#endif __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture) { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); - //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory"); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -578,6 +580,7 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_interrupt_posture(); @@ -589,7 +592,6 @@ unsigned int interrupt_save; __restore_interrupt(interrupt_save); } } - #define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupt(interrupt_save); diff --git a/ports/cortex_m7/ac6/src/tx_thread_system_return.S b/ports/cortex_m7/ac6/src/tx_thread_system_return.S index 831c00e4c..a092e34c8 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m7/ac6/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -73,6 +75,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m7/gnu/inc/tx_port.h b/ports/cortex_m7/gnu/inc/tx_port.h index 48a34cfa4..77355aab8 100644 --- a/ports/cortex_m7/gnu/inc/tx_port.h +++ b/ports/cortex_m7/gnu/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -539,25 +541,26 @@ unsigned int posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } -#else +#endif + __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) { __asm__ volatile ("CPSIE i": : : "memory"); } -#endif __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture) { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); - //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory"); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif } + __attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) { unsigned int int_posture; @@ -578,6 +581,7 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_interrupt_posture(); @@ -587,6 +591,7 @@ unsigned int interrupt_save; __enable_interrupts(); #endif __restore_interrupt(interrupt_save); + __asm__ volatile ("isb 0xF " : : : "memory"); } } diff --git a/ports/cortex_m7/gnu/src/tx_thread_system_return.S b/ports/cortex_m7/gnu/src/tx_thread_system_return.S index ce5a3f46f..180894b3b 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m7/gnu/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -73,6 +75,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -81,10 +85,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #endif _isr_context: BX lr // Return to caller diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h index 63d821bfc..14524c46e 100644 --- a/ports/cortex_m7/iar/inc/tx_port.h +++ b/ports/cortex_m7/iar/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -539,20 +541,20 @@ unsigned int posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } -#else +#endif + __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) { __asm__ volatile ("CPSIE i": : : "memory"); } -#endif __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture) { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); - //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory"); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -578,6 +580,7 @@ unsigned int interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (__get_ipsr_value() == 0) { interrupt_save = __get_interrupt_posture(); @@ -589,7 +592,6 @@ unsigned int interrupt_save; __restore_interrupt(interrupt_save); } } - #define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupt(interrupt_save); diff --git a/ports/cortex_m7/iar/src/tx_thread_system_return.s b/ports/cortex_m7/iar/src/tx_thread_system_return.s index 0cef80c6f..00a07ea87 100644 --- a/ports/cortex_m7/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m7/iar/src/tx_thread_system_return.s @@ -1,16 +1,19 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ +;*************************************************************************** +;* Copyright (c) 2024 Microsoft Corporation +;* Copyright (c) 2026-present Eclipse ThreadX contributors +;* +;* This program and the accompanying materials are made available under the +;* terms of the MIT License which is available at +;* https://opensource.org/licenses/MIT. +;* +;* SPDX-License-Identifier: MIT +;************************************************************************** +; Some portions generated by Gemini (Gemini 2.0 Flash). + + +;************************************************************************** -/**************************************************************************/ /**************************************************************************/ /** */ /** ThreadX Component */ @@ -70,6 +73,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB SY // Ensure memory access is complete + ISB SY // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable diff --git a/ports/cortex_m85/gnu/inc/tx_port.h b/ports/cortex_m85/gnu/inc/tx_port.h index 9057a1324..c1d2f7312 100644 --- a/ports/cortex_m85/gnu/inc/tx_port.h +++ b/ports/cortex_m85/gnu/inc/tx_port.h @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -541,7 +543,7 @@ UINT posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } #else __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) @@ -554,6 +556,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -579,6 +582,7 @@ UINT interrupt_save; /* Set PendSV to invoke ThreadX scheduler. */ *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory"); if (_tx_ipsr_get() == 0) { interrupt_save = __get_interrupt_posture(); @@ -588,6 +592,7 @@ UINT interrupt_save; __enable_interrupts(); #endif __restore_interrupt(interrupt_save); + __asm__ volatile ("isb 0xF " : : : "memory"); } } diff --git a/ports/cortex_m85/gnu/src/tx_thread_system_return.S b/ports/cortex_m85/gnu/src/tx_thread_system_return.S index bbb5a6303..356300943 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m85/gnu/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Gemini (Gemini 2.0 Flash). + /**************************************************************************/ /**************************************************************************/ @@ -74,6 +76,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -82,10 +86,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #endif _isr_context: BX lr // Return to caller diff --git a/ports/cortex_m85/iar/inc/tx_port.h b/ports/cortex_m85/iar/inc/tx_port.h index bf2450495..409aecdd3 100644 --- a/ports/cortex_m85/iar/inc/tx_port.h +++ b/ports/cortex_m85/iar/inc/tx_port.h @@ -541,7 +541,7 @@ UINT posture; #ifdef TX_PORT_USE_BASEPRI __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value) { - __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value)); + __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory"); } #else __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) @@ -554,6 +554,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i { #ifdef TX_PORT_USE_BASEPRI __set_basepri_value(int_posture); + __asm__ volatile ("" : : : "memory"); #else __asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory"); #endif @@ -623,3 +624,5 @@ extern CHAR _tx_version_id[]; #endif #endif + +#endif diff --git a/ports/cortex_m85/iar/src/tx_thread_system_return.s b/ports/cortex_m85/iar/src/tx_thread_system_return.s index 768262a2a..fcc87228c 100644 --- a/ports/cortex_m85/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m85/iar/src/tx_thread_system_return.s @@ -1,16 +1,19 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ +;*************************************************************************** +;* Copyright (c) 2024 Microsoft Corporation +;* Copyright (c) 2026-present Eclipse ThreadX contributors +;* +;* This program and the accompanying materials are made available under the +;* terms of the MIT License which is available at +;* https://opensource.org/licenses/MIT. +;* +;* SPDX-License-Identifier: MIT +;************************************************************************** +; Some portions generated by Gemini (Gemini 2.0 Flash). + + +;************************************************************************** -/**************************************************************************/ /**************************************************************************/ /** */ /** ThreadX Component */ @@ -69,6 +72,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB SY // Ensure memory access is complete + ISB SY // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable From 3c4d20285fe7aad3f04e90665b764db00a8b41ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Wed, 29 Apr 2026 13:22:15 -0400 Subject: [PATCH 12/29] Corrected typos in two test filenames (#527) --- ...r_test.c => threadx_smp_resume_suspend_ascending_order_test.c} | 0 ..._test.c => threadx_smp_resume_suspend_descending_order_test.c} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename test/smp/regression/{threadx_smp_resume_suspend_accending_order_test.c => threadx_smp_resume_suspend_ascending_order_test.c} (100%) rename test/smp/regression/{threadx_smp_resume_suspend_decending_order_test.c => threadx_smp_resume_suspend_descending_order_test.c} (100%) diff --git a/test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c b/test/smp/regression/threadx_smp_resume_suspend_ascending_order_test.c similarity index 100% rename from test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c rename to test/smp/regression/threadx_smp_resume_suspend_ascending_order_test.c diff --git a/test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c b/test/smp/regression/threadx_smp_resume_suspend_descending_order_test.c similarity index 100% rename from test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c rename to test/smp/regression/threadx_smp_resume_suspend_descending_order_test.c From 42adda44573b7c0062138818749437e6baf1044f Mon Sep 17 00:00:00 2001 From: Francisco Manuel Merino Torres Date: Wed, 13 May 2026 13:46:54 +0200 Subject: [PATCH 13/29] Added a riscv32 for the OpenHW CVA6 (#511) --- cmake/riscv32-unknown-elf.cmake | 7 +- cmake/riscv32_gnu.cmake | 8 +- .../gnu/example_build/cva6_ariane/board.c | 42 + .../cva6_ariane/build_libthreadx.sh | 6 + .../gnu/example_build/cva6_ariane/csr.h | 360 +++++++ .../example_build/cva6_ariane/demo_threadx.c | 393 +++++++ .../gnu/example_build/cva6_ariane/entry.s | 58 ++ .../gnu/example_build/cva6_ariane/hwtimer.c | 35 + .../gnu/example_build/cva6_ariane/hwtimer.h | 24 + .../gnu/example_build/cva6_ariane/link.lds | 49 + .../gnu/example_build/cva6_ariane/plic.c | 72 ++ .../gnu/example_build/cva6_ariane/plic.h | 49 + .../gnu/example_build/cva6_ariane/trap.c | 66 ++ .../cva6_ariane/tx_initialize_low_level.S | 163 +++ .../gnu/example_build/cva6_ariane/uart.c | 893 ++++++++++++++++ .../gnu/example_build/cva6_ariane/uart.h | 961 ++++++++++++++++++ 16 files changed, 3183 insertions(+), 3 deletions(-) create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/board.c create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/build_libthreadx.sh create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/csr.h create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/demo_threadx.c create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/entry.s create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/hwtimer.c create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/hwtimer.h create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/link.lds create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/plic.c create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/plic.h create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/trap.c create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/tx_initialize_low_level.S create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/uart.c create mode 100644 ports/risc-v32/gnu/example_build/cva6_ariane/uart.h diff --git a/cmake/riscv32-unknown-elf.cmake b/cmake/riscv32-unknown-elf.cmake index cfd9f7eae..d21e729ca 100644 --- a/cmake/riscv32-unknown-elf.cmake +++ b/cmake/riscv32-unknown-elf.cmake @@ -17,7 +17,12 @@ set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags") set(CMAKE_CXX_FLAGS "${CXXFLAGS}" CACHE INTERNAL "cxx compiler flags") -set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__ -D__riscv_float_abi_single" CACHE INTERNAL "asm compiler flags") +if(DEFINED SOFT_FLOAT) + set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__" CACHE INTERNAL "asm compiler flags") +else() + set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__ -D__riscv_float_abi_single" CACHE INTERNAL "asm compiler flags") +endif() + set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags") SET(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug compiler flags") diff --git a/cmake/riscv32_gnu.cmake b/cmake/riscv32_gnu.cmake index 617b12760..ec8f98576 100644 --- a/cmake/riscv32_gnu.cmake +++ b/cmake/riscv32_gnu.cmake @@ -1,10 +1,14 @@ # Name of the target set(CMAKE_SYSTEM_NAME Generic) set(CMAKE_SYSTEM_PROCESSOR risc-v32) - set(THREADX_ARCH "risc-v32") set(THREADX_TOOLCHAIN "gnu") -set(ARCH_FLAGS "-g -march=rv32gc -mabi=ilp32d -mcmodel=medany") +if(DEFINED SOFT_FLOAT) + set(ARCH_FLAGS "-g -march=rv32ima_zicsr -mabi=ilp32 -mcmodel=medany") + set(CACHE{SOFT_FLOAT} FORCE 1) +else() + set(ARCH_FLAGS "-g -march=rv32gc -mabi=ilp32d -mcmodel=medany") +endif() set(CFLAGS "${ARCH_FLAGS}") set(ASFLAGS "${ARCH_FLAGS}") set(LDFLAGS "${ARCH_FLAGS}") diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/board.c b/ports/risc-v32/gnu/example_build/cva6_ariane/board.c new file mode 100644 index 000000000..b1c7e5c5a --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/board.c @@ -0,0 +1,42 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "plic.h" +#include "hwtimer.h" +#include "uart.h" +#include +#include + +void *memset(const void *des, int c,size_t n) +{ + if((des == NULL) || n <=0) + return (void*)des; + char* t = (char*)des; + int i; + for(i=0;i + +static inline uint32_t riscv_get_core() +{ + uint32_t x; + asm volatile("csrr %0, mhartid" : "=r" (x) ); + return x; +} + +static inline uint64_t riscv_get_mstatus() +{ + uint32_t x; + uint32_t xh; + asm volatile("csrr %0, mstatus" : "=r" (x) ); + asm volatile("csrr %0, mstatush" : "=r" (xh) ); + return ((uint64_t)(x)) + ((uint64_t)(xh)) << 32; +} + +static inline void riscv_writ_mstatus(uint64_t x) +{ + asm volatile("csrw mstatus, %0" : : "r" ((uint32_t)x)); + asm volatile("csrw mstatush, %0" : : "r" ((uint32_t)(x >> 32))); +} + +// machine exception program counter, holds the +// instruction address to which a return from +// exception will go. +static inline void riscv_writ_mepc(uint32_t x) +{ + asm volatile("csrw mepc, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sstatus() +{ + uint32_t x; + asm volatile("csrr %0, sstatus" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_sstatus(uint32_t x) +{ + asm volatile("csrw sstatus, %0" : : "r" (x)); +} + +// Supervisor Interrupt Pending +static inline uint32_t riscv_get_sip() +{ + uint32_t x; + asm volatile("csrr %0, sip" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_sip(uint32_t x) +{ + asm volatile("csrw sip, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sie() +{ + uint32_t x; + asm volatile("csrr %0, sie" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_sie(uint32_t x) +{ + asm volatile("csrw sie, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_mie() +{ + uint32_t x; + asm volatile("csrr %0, mie" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mie(uint32_t x) +{ + asm volatile("csrw mie, %0" : : "r" (x)); +} + +// supervisor exception program counter, holds the +// instruction address to which a return from +// exception will go. +static inline void riscv_writ_sepc(uint32_t x) +{ + asm volatile("csrw sepc, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sepc() +{ + uint32_t x; + asm volatile("csrr %0, sepc" : "=r" (x) ); + return x; +} + +// Machine Exception Delegation +static inline uint32_t riscv_get_medeleg() +{ + uint32_t x; + asm volatile("csrr %0, medeleg" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_medeleg(uint32_t x) +{ + asm volatile("csrw medeleg, %0" : : "r" (x)); +} + +// Machine Interrupt Delegation +static inline uint32_t riscv_get_mideleg() +{ + uint32_t x; + asm volatile("csrr %0, mideleg" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mideleg(uint32_t x) +{ + asm volatile("csrw mideleg, %0" : : "r" (x)); +} + +// Supervisor Trap-Vector Base Address +// low two bits are mode. +static inline void riscv_writ_stvec(uint32_t x) +{ + asm volatile("csrw stvec, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_stvec() +{ + uint32_t x; + asm volatile("csrr %0, stvec" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_stimecmp() +{ + uint32_t x; + asm volatile("csrr %0, 0x14d" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_stimecmp(uint32_t x) +{ + asm volatile("csrw 0x14d, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_menvcfg() +{ + uint32_t x; + asm volatile("csrr %0, 0x30a" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_menvcfg(uint32_t x) +{ + asm volatile("csrw 0x30a, %0" : : "r" (x)); +} + +static inline void riscv_writ_pmpcfg0(uint32_t x) +{ + asm volatile("csrw pmpcfg0, %0" : : "r" (x)); +} + +static inline void riscv_writ_pmpaddr0(uint32_t x) +{ + asm volatile("csrw pmpaddr0, %0" : : "r" (x)); +} + +static inline void riscv_writ_satp(uint32_t x) +{ + asm volatile("csrw satp, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_satp() +{ + uint32_t x; + asm volatile("csrr %0, satp" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_scause() +{ + uint32_t x; + asm volatile("csrr %0, scause" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_stval() +{ + uint32_t x; + asm volatile("csrr %0, stval" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mcounteren(uint32_t x) +{ + asm volatile("csrw mcounteren, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_mcounteren() +{ + uint32_t x; + asm volatile("csrr %0, mcounteren" : "=r" (x) ); + return x; +} + +// machine-mode cycle counter +static inline uint64_t riscv_get_time() +{ + uint32_t x; + uint32_t xh; + asm volatile("csrr %0, time" : "=r" (x) ); + asm volatile("csrr %0, timeh" : "=r" (xh) ); + return ((uint64_t)(x)) + ((uint64_t)(xh)) << 32; +} + +static inline void riscv_sintr_on() +{ + uint32_t sstatus = riscv_get_sstatus(); + sstatus |= SSTATUS_SIE; + riscv_writ_sstatus(sstatus); +} + +static inline void riscv_sintr_off() +{ + uint32_t sstatus = riscv_get_sstatus(); + sstatus &= (~SSTATUS_SIE); + riscv_writ_sstatus(sstatus); +} + +static inline int riscv_sintr_get() +{ + uint32_t x = riscv_get_sstatus(); + return (x & SSTATUS_SIE) != 0; +} + +static inline void riscv_sintr_restore(int x) +{ + if(x) + riscv_sintr_on(); + else + riscv_sintr_off(); +} + +static inline void riscv_mintr_on() +{ + uint32_t mstatus = riscv_get_mstatus(); + mstatus |= MSTATUS_MIE; + riscv_writ_mstatus(mstatus); +} + +static inline void riscv_mintr_off() +{ + uint32_t mstatus = riscv_get_mstatus(); + mstatus &= (~MSTATUS_MIE); + riscv_writ_mstatus(mstatus); +} + +static inline int riscv_mintr_get() +{ + uint32_t x = riscv_get_mstatus(); + return (x & MSTATUS_MIE) != 0; +} + +static inline void riscv_mintr_restore(int x) +{ + if(x) + riscv_mintr_on(); + else + riscv_mintr_off(); +} + +static inline uint32_t riscv_get_sp() +{ + uint32_t x; + asm volatile("mv %0, sp" : "=r" (x) ); + return x; +} + +// read and write tp, the thread pointer, which xv6 uses to hold +// this core's hartid (core number), the index into cpus[]. +static inline uint32_t riscv_get_tp() +{ + uint32_t x; + asm volatile("mv %0, tp" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_tp(uint32_t x) +{ + asm volatile("mv tp, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_ra() +{ + uint32_t x; + asm volatile("mv %0, ra" : "=r" (x) ); + return x; +} + +// flush the TLB. +static inline void sfence_vma() +{ + // the zero, zero means flush all TLB entries. + asm volatile("sfence.vma zero, zero"); +} + +#endif // __ASSEMBLER__ + +#endif diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/demo_threadx.c b/ports/risc-v32/gnu/example_build/cva6_ariane/demo_threadx.c new file mode 100644 index 000000000..f21dbb26b --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/demo_threadx.c @@ -0,0 +1,393 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include "uart.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + +char *_to_str(ULONG val) +{ + static char buf[11]; /* 10 digits max + '\0' */ + char *p = buf + sizeof(buf) - 1; + + *p = '\0'; + do { + *--p = '0' + (val % 10); + val /= 10; + } while (val); + + return p; +} + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + CHAR *pointer = TX_NULL; + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + puts("[Thread] : thread_0_entry is here!"); + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + puts("[Thread] : thread_1_entry is here!"); + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) { + puts("[Thread 1] ERROR: Failed to send message!"); + break; + } + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + puts("[Thread] : thread_2_entry is here!"); + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)){ + puts("[Thread 2] ERROR: Failed to receive message ! Expected # "); + uart_puts(_to_str(thread_2_messages_received)); + puts(", but got # "); + uart_puts(_to_str(received_message)); + break; + } + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + puts("[Thread] : thread_3_and_4_entry is here!"); + + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + puts("[Thread] : thread_5_entry is here!"); + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + puts("[Thread] : thread_6_and_7_entry is here!"); + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/entry.s b/ports/risc-v32/gnu/example_build/cva6_ariane/entry.s new file mode 100644 index 000000000..9b202ca16 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/entry.s @@ -0,0 +1,58 @@ + +.section .text +.align 4 +.global _start +.extern main +.extern _sysstack_start +.extern _bss_start +.extern _bss_end +_start: + csrr t0, mhartid + bne t0, zero, 1f + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + la t0, _sysstack_start + li t1, 0x1000 + add sp, t0, t1 + la t0, _bss_start + la t1, _bss_end +_bss_clean_start: + bgeu t0, t1, _bss_clean_end + sb zero, 0(t0) + addi t0, t0, 1 + j _bss_clean_start +_bss_clean_end: + call main +1: + /* todo smp */ + wfi + j 1b diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/hwtimer.c b/ports/risc-v32/gnu/example_build/cva6_ariane/hwtimer.c new file mode 100644 index 000000000..b5335cf30 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/hwtimer.c @@ -0,0 +1,35 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "tx_port.h" +#include "csr.h" +#include "hwtimer.h" + +#define CLINT (0x02000000L) +#define CLINT_TIME (CLINT+0xBFF8) +#define CLINT_TIMECMP(hart_id) (CLINT+0x4000+8*(hart_id)) + + +int hwtimer_init(void) +{ + int hart = riscv_get_core(); + uint64_t time = *((uint64_t*)CLINT_TIME); + *((uint64_t*)CLINT_TIMECMP(hart)) = time + TICKNUM_PER_TIMER; + return 0; +} + +int hwtimer_handler(void) +{ + int hart = riscv_get_core(); + uint64_t time = *((uint64_t*)CLINT_TIME); + *((uint64_t*)CLINT_TIMECMP(hart)) = time + TICKNUM_PER_TIMER; + return 0; +} + diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/hwtimer.h b/ports/risc-v32/gnu/example_build/cva6_ariane/hwtimer.h new file mode 100644 index 000000000..9e4a066da --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/hwtimer.h @@ -0,0 +1,24 @@ + +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_HWTIMER_H +#define RISCV_HWTIMER_H + +#include + +#define TICKNUM_PER_SECOND 50000000 +#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 100) + +int hwtimer_init(void); + +int hwtimer_handler(void); + +#endif diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/link.lds b/ports/risc-v32/gnu/example_build/cva6_ariane/link.lds new file mode 100644 index 000000000..619080e74 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/link.lds @@ -0,0 +1,49 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY( _start ) + +SECTIONS +{ + /* + * ensure that entry.S / _entry is at 0x80000000, + * where arianes's -kernel jumps. + */ + . = 0x80000000; + + .text : { + *(.text .text.*) + . = ALIGN(0x1000); + PROVIDE(etext = .); + } + + .rodata : { + . = ALIGN(16); + *(.srodata .srodata.*) /* do not need to distinguish this from .rodata */ + . = ALIGN(16); + *(.rodata .rodata.*) + } + + .data : { + . = ALIGN(16); + *(.sdata .sdata.*) /* do not need to distinguish this from .data */ + . = ALIGN(16); + *(.data .data.*) + } + + .bss : { + . = ALIGN(16); + _bss_start = .; + *(.sbss .sbss.*) /* do not need to distinguish this from .bss */ + . = ALIGN(16); + *(.bss .bss.*) + _bss_end = .; + } + + .stack : { + . = ALIGN(4096); + _sysstack_start = .; + . += 0x1000; + _sysstack_end = .; + } + + PROVIDE(_end = .); +} diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/plic.c b/ports/risc-v32/gnu/example_build/cva6_ariane/plic.c new file mode 100644 index 000000000..01e5c71a4 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/plic.c @@ -0,0 +1,72 @@ +#include "plic.h" +#include +irq_callback callbacks[MAX_CALLBACK_NUM]; + +void plic_irq_enable(int irqno) +{ + int hart = riscv_get_core(); + *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno)); + return; +} + +void plic_irq_disable(int irqno) +{ + int hart = riscv_get_core(); + *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno))); + return; +} + +void plic_prio_set(int irqno, int prio) +{ + PLIC_SET_PRIO(irqno, prio); +} + +int plic_prio_get(int irqno) +{ + return PLIC_GET_PRIO(irqno); +} + +int plic_register_callback(int irqno, irq_callback callback) +{ + if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM)) + return -1; + callbacks[irqno] = callback; + return 0; +} + +int plic_unregister_callback(int irqno) +{ + return plic_register_callback(irqno, NULL); +} + +int plic_init(void) +{ + for(int i=0;i + +#define PLIC 0x0C000000L +#define PLIC_PRIORITY (PLIC + 0x0) +#define PLIC_PENDING (PLIC + 0x1000) +#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100) +#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100) +#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000) +#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000) +#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000) +#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000) +#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000) +#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000) + + +#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4)) +#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio)) + +#define MAX_CALLBACK_NUM 128 +typedef int (*irq_callback)(int irqno); + +void plic_irq_enable(int irqno); +void plic_irq_disable(int irqno); +int plic_prio_get(int irqno); +void plic_prio_set(int irqno, int prio); +int plic_register_callback(int irqno, irq_callback callback); +int plic_unregister_callback(int irqno); +int plic_init(void); +int plic_claim(void); +void plic_complete(int irqno); + +int plic_irq_intr(void); + +#endif + diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/trap.c b/ports/risc-v32/gnu/example_build/cva6_ariane/trap.c new file mode 100644 index 000000000..3d2467fb5 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/trap.c @@ -0,0 +1,66 @@ +#include "csr.h" +#include +#include "uart.h" +#include "hwtimer.h" +#include "plic.h" +#include +#include + +#define OS_IS_INTERUPT(mcause) (mcause & 0x80000000u) +#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT)) +#define OS_IS_TICK_INT(mcause) (mcause == 0x80000007u) +#define OS_IS_SOFT_INT(mcause) (mcause == 0x80000003u) +#define OS_IS_EXT_INT(mcause) (mcause == 0x8000000bu) +#define OS_IS_TRAP_USER(mcause) (mcause == 0x0000000bu) +extern void _tx_timer_interrupt(void); + +extern int uart_putc(int ch); + +static void print_hex(uintptr_t val) +{ + char digits[] = "0123456789ABCDEF"; + uart_putc('0'); + uart_putc('x'); + for(int i = (sizeof(uintptr_t)*2) - 1; i >= 0; i--) { + int d = (val >> (i*4)) & 0xF; + uart_putc(digits[d]); + } + uart_putc('\n'); +} + +void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) +{ + if(OS_IS_INTERUPT(mcause)) + { + if(OS_IS_TICK_INT(mcause)) + { + hwtimer_handler(); + _tx_timer_interrupt(); + } + else if(OS_IS_EXT_INT(mcause)) + { + int ret = plic_irq_intr(); + if(ret) + { + puts("[INTERRUPT]: handler irq error!"); + while(1) ; + } + } + else + { + puts("[INTERRUPT]: now can't deal with the interrupt!"); + while(1) ; + } + } + else + { + puts("[EXCEPTION] : Unkown Error!!"); + puts("mcause:"); + print_hex(mcause); + puts("mepc:"); + print_hex(mepc); + puts("mtval:"); + print_hex(mtval); + while(1) ; + } +} diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/tx_initialize_low_level.S b/ports/risc-v32/gnu/example_build/cva6_ariane/tx_initialize_low_level.S new file mode 100644 index 000000000..16910f760 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/tx_initialize_low_level.S @@ -0,0 +1,163 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "csr.h" +#include "tx_port.h" + + .section .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* trap_entry RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for riscv processor trap handle */ +/* It will do the contex save and call c trap_handler and do contex */ +/* load */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* trap_handler */ +/* */ +/* CALLED BY */ +/* */ +/* hardware exception */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .global trap_entry + .extern trap_handler + .extern _tx_thread_context_restore + trap_entry: +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -65*4 // Allocate space for all registers - with floating point enabled +#else + addi sp, sp, -32*4 // Allocate space for all registers - without floating point enabled +#endif + + sw x1, 28*4(sp) // Store RA, 28*4(because call will override ra [ra is a calle register in riscv]) + + call _tx_thread_context_save + + csrr a0, mcause + csrr a1, mepc + csrr a2, mtval + addi sp, sp, -4 + sw ra, 0(sp) + call trap_handler + lw ra, 0(sp) + addi sp, sp, 4 + call _tx_thread_context_restore + // it will nerver return +_err: + wfi + j _err + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 11-03-2026 Francisco Merino Adapted for RV32 from RV64 port */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .weak _tx_initialize_low_level + .extern _end + .extern board_init +_tx_initialize_low_level: + + .section .text + + la t0, _tx_thread_system_stack_ptr + sw sp, 0(t0) // Save system stack pointer + + la t0, _end // Pickup first free address + la t1, _tx_initialize_unused_memory + sw t0, 0(t1) // Save unused memory address + li t0, MSTATUS_MIE + csrrc zero, mstatus, t0 // clear MSTATUS_MIE bit + li t0, (MSTATUS_MPP_M | MSTATUS_MPIE ) + csrrs zero, mstatus, t0 // set MSTATUS_MPP, MPIE bit + li t0, (MIE_MTIE | MIE_MSIE | MIE_MEIE) + csrrs zero, mie, t0 // set mie +#ifdef __riscv_flen + li t0, MSTATUS_FS + csrrs zero, mstatus, t0 // set MSTATUS_FS bit to open f/d isa in riscv + fscsr x0 +#endif + addi sp, sp, -4 + sw ra, 0(sp) + call board_init + lw ra, 0(sp) + addi sp, sp, 4 + la t0, trap_entry + csrw mtvec, t0 + ret diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/uart.c b/ports/risc-v32/gnu/example_build/cva6_ariane/uart.c new file mode 100644 index 000000000..c92c67e61 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/uart.c @@ -0,0 +1,893 @@ +/******************************************************************************* + * Copyright (c) 2020 Thales. + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + */ +// Additional contributions by: +// Sebastien Jacq - sjthales on github.com +// Anjali Gedam - anjaliigedam on github.com +// +// Description: Driver for UART Ip of the CVA6 platform +// +// =========================================================================== // +// Revisions : +// Date Version Author Description +// 2020-10-06 0.1 S.Jacq modification of the Test for CVA6 softcore +// 2021-07-12 0.2 Anjali G modification for the CVA6 FPGA +// =========================================================================== // + + +#include "uart.h" + +//#include "../plic/plic.h" +//#include "../hw_platform.h" +#define FPGA_UART_0_FREQUENCY 50000000 +#define FPGA_UART_0_BASE (UART_TypeDef *)0x10000000 +#define STDIO_BAUD_RATE UART_115200_BAUD + +/******************************************************************************* + * Defines + */ +#define TX_COMPLETE 0u +#define TX_FIFO_SIZE 16u + +#define FCR_TRIG_LEVEL_MASK 0xC0u + +#define IIRF_MASK 0x0Fu + +#define INVALID_INTERRUPT 0u +#define INVALID_IRQ_HANDLER ((uart_irq_handler_t) 0) +#define NULL_HANDLER ((uart_irq_handler_t) 0) + +#define UART_DATA_READY ((uint8_t) 0x01) + + +/******************************************************************************* + * Possible values for Interrupt Identification Register Field. + */ +#define IIRF_MODEM_STATUS 0x00u +#define IIRF_THRE 0x02u +//#define IIRF_MMI 0x03u +#define IIRF_RX_DATA 0x04u +#define IIRF_RX_LINE_STATUS 0x06u +#define IIRF_DATA_TIMEOUT 0x0Cu + + +//#define PLIC_DEMO 1 +// Source/portable/GCC/RISC-V/portASM.S:290:freertos_risc_v_application_interrupt_handler (weak function : User application can add there own override) + +uart_instance_t g_uart_0 = { .hw_reg = FPGA_UART_0_BASE }; + +/******************************************************************************* + * Global initialization for all modes + */ +static void global_init +( + uart_instance_t * this_uart, + uint32_t baud_rate, + uint8_t line_config +) +{ + + /* disable interrupts */ + this_uart->hw_reg->IER = 0u; + + /* FIFO configuration */ + this_uart->hw_reg->FCR = 0u; + + /* clear receiver FIFO */ + this_uart->hw_reg->FCR = FIFO_RX_TRIGGER_LEVEL_14_MASK | CLEAR_RX_FIFO_MASK | CLEAR_TX_FIFO_MASK | RXRDY_TXRDYN_EN_MASK; + + /* clear transmitter FIFO */ + this_uart->hw_reg->FCR |= CLEAR_TX_FIFO_MASK; + + /* set default READY mode : Mode 0*/ + /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO + * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */ + this_uart->hw_reg->FCR |= RXRDY_TXRDYN_EN_MASK; + + this_uart->hw_reg->MCR = 0u; + + + + /* + * Configure baud rate divisors. This uses the fractional baud rate divisor + * where possible to provide the most accurate baud rat possible. + */ + config_baud_divisors(this_uart, baud_rate); + + /* set the line control register (bit length, stop bits, parity) */ + this_uart->hw_reg->LCR = line_config; + + /* Instance setup */ + this_uart->baudrate = baud_rate; + this_uart->lineconfig = line_config; + this_uart->tx_buff_size = TX_COMPLETE; + this_uart->tx_buffer = (const uint8_t*)0; + this_uart->tx_idx = 0u; + + /* Default handlers for MSS UART interrupts */ + this_uart->rx_handler = NULL_HANDLER; + this_uart->tx_handler = NULL_HANDLER; + this_uart->linests_handler = NULL_HANDLER; + this_uart->modemsts_handler = NULL_HANDLER; + + /* Initialize the sticky status */ + this_uart->status = 0u; +} + +/******************************************************************************* + * Public Functions + *******************************************************************************/ +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_init +( + uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config +) +{ + /* Perform generic initialization */ + global_init(this_uart, baud_rate, line_config); + + + /* set default tx handler for automated TX using interrupt in USART mode */ + this_uart->tx_handler = default_tx_handler; +} + + + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_polled_tx +( + uart_instance_t * this_uart, + const uint8_t * pbuff, + uint32_t tx_size +) +{ + uint32_t char_idx = 0u; + // uint32_t size_sent; + uint8_t status; + //uint32_t temp_tx_size = tx_size; + + //ASSERT(pbuff != ( (uint8_t*)0)); + //ASSERT(tx_size > 0u); + + if ((pbuff != ((uint8_t*)0)) && (tx_size > 0u)) + { + /* Remain in this loop until the entire input buffer + * has been transferred to the UART. + */ + do + { + /* Wait until TX FIFO is empty. */ + do + { + status = this_uart->hw_reg->LSR; + // this_uart->status |= status; + }while (0u == (status & UART_THRE)); + + + /* Check if TX FIFO is empty. */ + // if (status & UART_THRE) + //{ + // uint32_t fill_size = TX_FIFO_SIZE; + + /* Calculate the number of bytes to transmit. */ + //if (temp_tx_size < TX_FIFO_SIZE) + //{ + // fill_size = temp_tx_size; + //} + + /* Fill the TX FIFO with the calculated the number of bytes. */ + //for (size_sent = 0u; size_sent < fill_size; ++size_sent) + //{ + /* Send next character in the buffer. */ + this_uart->hw_reg->THR = pbuff[char_idx]; + char_idx++; + //} + + /* Calculate the number of bytes remaining(not transmitted yet)*/ + //temp_tx_size -= size_sent; + //} + }while (char_idx < tx_size); + } +} + + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_polled_tx_string +( + uart_instance_t * this_uart, + const uint8_t * p_sz_string +) +{ + uint32_t char_idx = 0u; + //uint32_t fill_size; + uint8_t data_byte; + volatile uint8_t status; + + //ASSERT(p_sz_string != ((uint8_t*)0)); + + if (p_sz_string != ((uint8_t*)0)) + { + /* Get the first data byte from the input buffer */ + data_byte = p_sz_string[char_idx]; + + /* First check for the NULL terminator byte. + * Then remain in this loop until the entire string in the input buffer + * has been transferred to the UART. + */ + while (0u != data_byte) + { + /* Wait until TX FIFO is empty. */ + do + { + status = this_uart->hw_reg->LSR; + // this_uart->status |= status; + }while (0u == (status & UART_THRE)); + + + /* Send bytes from the input buffer until the TX FIFO is full + * or we reach the NULL terminator byte. + */ + //fill_size = 0u; + + // while ((0u != data_byte) && (fill_size < TX_FIFO_SIZE)) + //{ + /* Send the data byte */ + this_uart->hw_reg->THR = data_byte; + //++fill_size; + char_idx++; + /* Get the next data byte from the input buffer */ + data_byte = p_sz_string[char_idx]; + //} + } + } +} + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_irq_tx +( + uart_instance_t * this_uart, + const uint8_t * pbuff, + uint32_t tx_size +) +{ + //ASSERT(pbuff != ((uint8_t*)0)); + //ASSERT(tx_size > 0u); + + if ((tx_size > 0u) && (pbuff != ((uint8_t*)0))) + { + /*Initialize the transmit info for the UART instance with the arguments*/ + this_uart->tx_buffer = pbuff; + this_uart->tx_buff_size = tx_size; + this_uart->tx_idx = 0u; + + /* assign default handler for data transfer */ + this_uart->tx_handler = default_tx_handler; + + /* enables TX interrupt */ + this_uart->hw_reg->IER |= ETBEI_MASK; + enable_irq(this_uart); + } +} + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +int8_t +UART_tx_complete +( + uart_instance_t * this_uart +) +{ + int8_t ret_value = 0; + uint8_t status = 0u; + + /* Read the Line Status Register and update the sticky record. */ + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + + if ((TX_COMPLETE == this_uart->tx_buff_size) && + ((status & UART_TEMT) != 0u)) + { + ret_value = (int8_t)1; + } + + return ret_value; +} + + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +size_t +UART_get_rx +( + uart_instance_t * this_uart, + uint8_t * rx_buff, + size_t buff_size +) +{ + size_t rx_size = 0u; + uint8_t status = 0u; + + //ASSERT(rx_buff != ((uint8_t*)0)); + //ASSERT(buff_size > 0u); + //printf("UART_get_rx() called buff_size = %d\n", buff_size); + + if ((rx_buff != (uint8_t*)0) && (buff_size > 0u)) + { + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + //printf("UART_get_rx() LSR status = %d\n", status); + + while (((status & UART_DATA_READY) != 0u) && (rx_size < buff_size)) + { + rx_buff[rx_size] = this_uart->hw_reg->RBR; + ++rx_size; + status = this_uart->hw_reg->LSR; + //printf("1 UART_get_rx() LSR status = %d\n", status); + this_uart->status |= status; + //printf("2 UART_get_rx() LSR status = %d\n", status); + + } + } + + return rx_size; +} + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_enable_irq +( + uart_instance_t * this_uart, + uart_irq_t irq_mask +) +{ + //ASSERT(UART_INVALID_IRQ > irq_mask); + + enable_irq(this_uart); + + if (UART_INVALID_IRQ > irq_mask) + { + /* irq_mask encoding: 1- enable + * bit 0 - Receive Data Available Interrupt + * bit 1 - Transmitter Holding Register Empty Interrupt + * bit 2 - Receiver Line Status Interrupt + * bit 3 - Modem Status Interrupt + */ + this_uart->hw_reg->IER |= ((uint8_t)(((uint32_t)irq_mask & + (uint32_t)IIRF_MASK))); + + } +} + + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_set_rx_handler +( + uart_instance_t * this_uart, + uart_irq_handler_t handler, + uart_rx_trig_level_t trigger_level +) +{ + //ASSERT(handler != INVALID_IRQ_HANDLER ); + //ASSERT(trigger_level < UART_FIFO_INVALID_TRIG_LEVEL); +#ifdef PLIC_DEMO + PLIC_init(); +#endif + + if ((handler != INVALID_IRQ_HANDLER) && + (trigger_level < UART_FIFO_INVALID_TRIG_LEVEL)) + { + //printf("UART DEBUG1\n"); + this_uart->rx_handler = handler; + + /* Set the receive interrupt trigger level. */ + this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR & + (uint8_t)(~((uint8_t)FCR_TRIG_LEVEL_MASK))) | + (uint8_t)trigger_level; + + /* Enable receive interrupt. */ + this_uart->hw_reg->IER |= ERBFI_MASK; + //printf("UART Enable IRQ\n"); + enable_irq(this_uart); + } +} + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_set_tx_handler +( + uart_instance_t * this_uart, + uart_irq_handler_t handler +) +{ + //ASSERT(handler != INVALID_IRQ_HANDLER); + + if (handler != INVALID_IRQ_HANDLER) + { + this_uart->tx_handler = handler; + + /* Make TX buffer info invalid */ + this_uart->tx_buffer = (const uint8_t*)0; + this_uart->tx_buff_size = 0u; + + /* Enable transmitter holding register Empty interrupt. */ + this_uart->hw_reg->IER |= ETBEI_MASK; + enable_irq(this_uart); + } +} + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_set_modemstatus_handler +( + uart_instance_t * this_uart, + uart_irq_handler_t handler +) +{ + //ASSERT(handler != INVALID_IRQ_HANDLER); + + if (handler != INVALID_IRQ_HANDLER) + { + this_uart->modemsts_handler = handler; + + /* Enable modem status interrupt. */ + this_uart->hw_reg->IER |= EDSSI_MASK; + enable_irq(this_uart); + } +} + + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +size_t +UART_fill_tx_fifo +( + uart_instance_t * this_uart, + const uint8_t * tx_buffer, + size_t tx_size +) +{ + uint8_t status = 0u; + uint32_t size_sent = 0u; + + //ASSERT(tx_buffer != ( (uint8_t*)0)); + //ASSERT(tx_size > 0); + + /* Fill the UART's Tx FIFO until the FIFO is full or the complete input + * buffer has been written. */ + if ((tx_buffer != ((uint8_t*)0)) && (tx_size > 0u)) + { + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + + if (status & UART_THRE) + { + uint32_t fill_size = TX_FIFO_SIZE; + + if (tx_size < TX_FIFO_SIZE) + { + fill_size = tx_size; + } + + /* Fill up FIFO */ + for (size_sent = 0u; size_sent < fill_size; size_sent++) + { + /* Send next character in the buffer. */ + this_uart->hw_reg->THR = tx_buffer[size_sent]; + } + } + } + + return size_sent; +} + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +uint8_t +UART_get_rx_status +( + uart_instance_t * this_uart +) +{ + uint8_t status = UART_INVALID_PARAM; + + /* + * Extract UART receive error status. + * Bit 1 - Overflow error status + * Bit 2 - Parity error status + * Bit 3 - Frame error status + * Bit 4 - Break interrupt indicator + * Bit 7 - FIFO data error status + */ + this_uart->status |= (this_uart->hw_reg->LSR); + status = (this_uart->status & STATUS_ERROR_MASK); + + //printf("UART_get_rx_status = %d", status); + //printf("UART_get_rx_LSR = %d", this_uart->hw_reg->LSR); + + + /* Clear the sticky status after reading */ + this_uart->status = 0u; + + return status; +} + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +uint8_t +UART_get_modem_status +( + const uart_instance_t * this_uart +) +{ + uint8_t status = UART_INVALID_PARAM; + + /* + * Extract UART modem status and place in lower bits of "status". + * Bit 0 - Delta Clear to Send Indicator + * Bit 1 - Delta Clear to Receive Indicator + * Bit 2 - Trailing edge of Ring Indicator detector + * Bit 3 - Delta Data Carrier Detect indicator + * Bit 4 - Clear To Send + * Bit 5 - Data Set Ready + * Bit 6 - Ring Indicator + * Bit 7 - Data Carrier Detect + */ + status = this_uart->hw_reg->MSR; + //printf("UART_get_modem_status = %d", status); + + return status; +} + + +/***************************************************************************//** + * UART_get_tx_status. + * See uart.h for details of how to use this function. + */ +uint8_t +UART_get_tx_status +( + uart_instance_t * this_uart +) +{ + uint8_t status = UART_TX_BUSY; + + /* Read the Line Status Register and update the sticky record. */ + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + + /* + * Extract the transmit status bits from the UART's Line Status Register. + * Bit 5 - Transmitter Holding Register/FIFO Empty (THRE) status. + (If = 1, TX FIFO is empty) + * Bit 6 - Transmitter Empty (TEMT) status. + (If = 1, both TX FIFO and shift register are empty) + */ + status &= (UART_THRE | UART_TEMT); + + return status; +} + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_set_break +( + uart_instance_t * this_uart +) +{ + /* set break character on Tx line */ + this_uart->hw_reg->LCR |= SB_MASK; +} + + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +void +UART_clear_break +( + uart_instance_t * this_uart +) +{ + /* remove break character from Tx line */ + this_uart->hw_reg->LCR &= ~SB_MASK; +} + +/***************************************************************************//** + * Configure baud divisors using fractional baud rate if possible. + */ +static void +config_baud_divisors +( + uart_instance_t * this_uart, + uint32_t baudrate +) +{ + uint32_t baud_value; + uint32_t baud_value_by_64; + uint32_t baud_value_by_128; +// uint32_t fractional_baud_value; + /* Note that we may need to set this as 64 bits for high frequencies */ + uint32_t pclk_freq; + + this_uart->baudrate = baudrate; + + /* Use the system clock value from hw_platform.h */ + pclk_freq = FPGA_UART_0_FREQUENCY; + + /* + * Compute baud value based on requested baud rate and PCLK frequency. + * The baud value is computed using the following equation: + * baud_value = PCLK_Frequency / (baud_rate * 16) + */ + baud_value_by_128 = (uint32_t)((8UL * pclk_freq) / baudrate); + baud_value_by_64 = baud_value_by_128 / 2u; + baud_value = baud_value_by_64 / 64u; +// fractional_baud_value = baud_value_by_64 - (baud_value * 64u); +// fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) + // - (fractional_baud_value * 2u); + + /* //ASSERT if integer baud value fits in 16-bit. */ + //ASSERT(baud_value <= UINT16_MAX); + + if (baud_value <= (uint32_t)UINT16_MAX) + { + + /* + * Use Fractional baud rate divisors + */ + /* set divisor latch */ + this_uart->hw_reg->LCR = DLAB_MASK; + + /* msb of baud value */ + this_uart->hw_reg->DLM = (uint8_t)(baud_value >> 8); + /* lsb of baud value */ + this_uart->hw_reg->DLL = (uint8_t)baud_value; + + /* reset divisor latch */ + this_uart->hw_reg->LCR = 0; + } +} + +/***************************************************************************//** + * Interrupt service routine triggered by any MSS UART interrupt. This routine + * will call the handler function appropriate to the interrupt from the + * handlers previously registered with the driver through calls to the + * UART_set_*_handler() functions, or it will call the default_tx_handler() + * function in response to transmit interrupts if UART_irq_tx() is used to + * transmit data. + */ +static void __attribute__ ((unused)) +uart_isr +( + uart_instance_t * this_uart +) +{ + //printf("uart_isr called\n"); + uint8_t iirf; + + iirf = this_uart->hw_reg->IIR & IIRF_MASK; + + switch (iirf) + { + case IIRF_MODEM_STATUS: /* Modem status interrupt */ + { + //ASSERT(NULL_HANDLER != this_uart->modemsts_handler); + if (NULL_HANDLER != this_uart->modemsts_handler) + { + (*(this_uart->modemsts_handler))(this_uart); + } + } + break; + + case IIRF_THRE: /* Transmitter Holding Register Empty */ + { + //ASSERT(NULL_HANDLER != this_uart->tx_handler); + if (NULL_HANDLER != this_uart->tx_handler) + { + (*(this_uart->tx_handler))(this_uart); + } + } + break; + + case IIRF_RX_DATA: /* Received Data Available */ + case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */ + { + //ASSERT(NULL_HANDLER != this_uart->rx_handler); + if (NULL_HANDLER != this_uart->rx_handler) + { + (*(this_uart->rx_handler))(this_uart); + } + } + break; + + case IIRF_RX_LINE_STATUS: /* Line Status Interrupt */ + { + //ASSERT(NULL_HANDLER != this_uart->linests_handler); + if (NULL_HANDLER != this_uart->linests_handler) + { + (*(this_uart->linests_handler))(this_uart); + } + } + break; + + default: + { + //ASSERT(INVALID_INTERRUPT); /*Alternative case has been considered*/ + } + break; + } +} + + + +/***************************************************************************//** + * See uart.h for details of how to use this function. + */ +static void +default_tx_handler +( + uart_instance_t * this_uart +) +{ + uint8_t status; + + //ASSERT(( (uint8_t*)0 ) != this_uart->tx_buffer); + //ASSERT(0u < this_uart->tx_buff_size); + + if ((((uint8_t*)0 ) != this_uart->tx_buffer) && + (0u < this_uart->tx_buff_size)) + { + /* Read the Line Status Register and update the sticky record. */ + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + + /* + * This function should only be called as a result of a THRE interrupt. + * Verify that this is true before proceeding to transmit data. + */ + if (status & UART_THRE) + { + uint32_t cnt; + uint32_t fill_size = TX_FIFO_SIZE; + uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx; + + /* Calculate the number of bytes to transmit. */ + if (tx_remain < TX_FIFO_SIZE) + { + fill_size = tx_remain; + } + + /* Fill the TX FIFO with the calculated the number of bytes. */ + for (cnt = 0u; cnt < fill_size; ++cnt) + { + /* Send next character in the buffer. */ + this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx]; + ++this_uart->tx_idx; + } + } + + /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */ + if (this_uart->tx_idx == this_uart->tx_buff_size) + { + this_uart->tx_buff_size = TX_COMPLETE; + + /* disables TX interrupt */ + this_uart->hw_reg->IER &= ~ETBEI_MASK; + } + } +} + + +static void __attribute__ ((unused)) +enable_irq +( + const uart_instance_t * this_uart +) +{ + +#ifdef PLIC_DEMO + PLIC_IRQn_Type plic_num = 0; +#endif + + if (&g_uart_0 == this_uart ) + { + //printf("enable_irq() UART assign plic_num = %d\n",plic_num); +#ifdef PLIC_DEMO + plic_num = UART_0_PLIC_IRQHandler; +#endif + + } + else + { + //printf("ASSERT(0) called\n"); + //ASSERT(0); /*Alternative case has been considered*/ + } + +#ifdef PLIC_DEMO + /* Enable UART instance interrupt in PLIC. */ + PLIC_EnableIRQ(plic_num); +#endif +} + +static void __attribute__ ((unused)) +disable_irq +( + const uart_instance_t * this_uart +) +{ +#ifdef PLIC_DEMO + PLIC_IRQn_Type plic_num = 0; +#endif + + if (&g_uart_0 == this_uart ) + { +#ifdef PLIC_DEMO + plic_num = UART_0_PLIC_IRQHandler; +#endif + } + else + { + //ASSERT(0); /*Alternative case has been considered*/ + } + + /* Disable UART instance interrupt in PLIC. */ +#ifdef PLIC_DEMO + PLIC_DisableIRQ(plic_num); +#endif +} + + +/////////////////////////////////////////////////////////////////////////////////// + +static uart_instance_t * const gp_my_uart = &g_uart_0; + +int uart_init(void) +{ + UART_init(gp_my_uart, STDIO_BAUD_RATE, ( UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT ) ); + + return 0; +} + +int uart_putc(int ch) +{ + UART_polled_tx(gp_my_uart, (const uint8_t *)&ch, 1); +} + +int uart_puts(const char* str) +{ + UART_polled_tx_string(gp_my_uart, str); +} \ No newline at end of file diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/uart.h b/ports/risc-v32/gnu/example_build/cva6_ariane/uart.h new file mode 100644 index 000000000..0a835727d --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/uart.h @@ -0,0 +1,961 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_UART_H +#define RISCV_UART_H + +#define UART0 0x10000000L +#define UART0_IRQ 10 + +#define puts(str) uart_puts(str"\n\r") +int uart_init(void); +int uart_putc(int ch); +int uart_puts(const char* str); +#endif + + +/******************************************************************************* + * Copyright (c) 2020 Thales. + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * + */ +// Additional contributions by: +// Sebastien Jacq - sjthales on github.com +// Anjali Gedam - anjaliigedam on github.com +// +// Description: Driver header for UART Ip of the CVA6 platform +// +// =========================================================================== // +// Revisions : +// Date Version Author Description +// 2020-10-06 0.1 S.Jacq modification of the Test for CVA6 softcore +// 2021-07-12 0.2 Anjali G modification for the CVA6 FPGA +// =========================================================================== // + +#ifndef __UART1_H_ +#define __UART1_H_ 1 + +#include +#include + + +/***************************************************************************//** + Baud rates + ========== + The following definitions are used to specify standard baud rates as a + parameter to the UART_init() function. + + | Constant | Description | + |----------------------|------------------| + | UART_110_BAUD | 110 baud rate | + | UART_300_BAUD | 300 baud rate | + | UART_600_BAUD | 600 baud rate | + | UART_1200_BAUD | 1200 baud rate | + | UART_2400_BAUD | 2400 baud rate | + | UART_4800_BAUD | 4800 baud rate | + | UART_9600_BAUD | 9600 baud rate | + | UART_19200_BAUD | 19200 baud rate | + | UART_38400_BAUD | 38400 baud rate | + | UART_57600_BAUD | 57600 baud rate | + | UART_115200_BAUD | 115200 baud rate | + | UART_230400_BAUD | 230400 baud rate | + | UART_460800_BAUD | 460800 baud rate | + | UART_921600_BAUD | 921600 baud rate | + + */ +#define UART_110_BAUD 110U +#define UART_300_BAUD 300U +#define UART_600_BAUD 600U +#define UART_1200_BAUD 1200U +#define UART_2400_BAUD 2400U +#define UART_4800_BAUD 4800U +#define UART_9600_BAUD 9600U +#define UART_19200_BAUD 19200U +#define UART_38400_BAUD 38400U +#define UART_57600_BAUD 57600U +#define UART_115200_BAUD 115200U +#define UART_230400_BAUD 230400U +#define UART_460800_BAUD 460800U +#define UART_921600_BAUD 921600U + +/***************************************************************************//** + Data Bits Length + ================ + The following defines are used to build the value of the UART_init() + function line_config parameter. + + | Constant | Description | + |----------------------|----------------------------| + | UART_DATA_5_BITS | 5 bits of data transmitted | + | UART_DATA_6_BITS | 6 bits of data transmitted | + | UART_DATA_7_BITS | 7 bits of data transmitted | + | UART_DATA_8_BITS | 8 bits of data transmitted | + + */ +#define UART_DATA_5_BITS ((uint8_t) 0x00) +#define UART_DATA_6_BITS ((uint8_t) 0x01) +#define UART_DATA_7_BITS ((uint8_t) 0x02) +#define UART_DATA_8_BITS ((uint8_t) 0x03) + +/***************************************************************************//** + Parity + ====== + The following defines are used to build the value of the UART_init() + function line_config parameter. + + | Constant | Description | + |-------------------------|--------------------------| + | UART_NO_PARITY | No parity | + | UART_ODD_PARITY | Odd Parity | + | UART_EVEN_PARITY | Even parity | + | UART_STICK_PARITY_0 | Stick parity bit to zero | + | UART_STICK_PARITY_1 | Stick parity bit to one | + */ +#define UART_NO_PARITY ((uint8_t) 0x00) +#define UART_ODD_PARITY ((uint8_t) 0x08) +#define UART_EVEN_PARITY ((uint8_t) 0x18) +#define UART_STICK_PARITY_0 ((uint8_t) 0x38) +#define UART_STICK_PARITY_1 ((uint8_t) 0x28) + +/***************************************************************************//** + Number of Stop Bits + =================== + The following defines are used to build the value of the UART_init() + function line_config parameter. + + | Constant | Description | + |---------------------------|--------------------------| + | UART_ONE_STOP_BIT | One stop bit | + | UART_ONEHALF_STOP_BIT | One and a half stop bits | + | UART_TWO_STOP_BITS | Two stop bits | + + */ +#define UART_ONE_STOP_BIT ((uint8_t) 0x00) +#define UART_ONEHALF_STOP_BIT ((uint8_t) 0x04) +#define UART_TWO_STOP_BITS ((uint8_t) 0x04) + +/***************************************************************************//** + Receiver Error Status + ===================== + The following defines are used to determine the UART receiver error type. + These bit mask constants are used with the return value of the + UART_get_rx_status() function to find out if any errors occurred while + receiving data. + + + | Constant | Description | + |------------------------|--------------------------------------------| + | UART_NO_ERROR | No error bit mask (0x00) | + | UART_OVERUN_ERROR | Overrun error bit mask (0x02) | + | UART_PARITY_ERROR | Parity error bit mask (0x04) | + | UART_FRAMING_ERROR | Framing error bit mask (0x08) | + | UART_BREAK_ERROR | Break error bit mask (0x10) | + | UART_FIFO_ERROR | FIFO error bit mask (0x80) | + | UART_INVALID_PARAM | Invalid function parameter bit mask (0xFF) | + */ +#define UART_INVALID_PARAM ((uint8_t)0xFF) +#define UART_NO_ERROR ((uint8_t)0x00 ) +#define UART_OVERUN_ERROR ((uint8_t)0x02) +#define UART_PARITY_ERROR ((uint8_t)0x04) +#define UART_FRAMING_ERROR ((uint8_t)0x08) +#define UART_BREAK_ERROR ((uint8_t)0x10) +#define UART_FIFO_ERROR ((uint8_t)0x80) + + +/******************************************************************************* + * Receiver error status mask. + */ +#define STATUS_ERROR_MASK ( UART_OVERUN_ERROR | UART_PARITY_ERROR | \ + UART_FRAMING_ERROR | UART_BREAK_ERROR | \ + UART_FIFO_ERROR) + +/***************************************************************************//** + Transmitter Status + ================== + The following definitions are used to determine the UART transmitter status. + These bit mask constants are used with the return value of the + UART_get_tx_status() function to find out the status of the transmitter. + + | Constant | Description | + |------------------|----------------------------------------------------| + | UART_TX_BUSY | Transmitter busy (0x00) | + | UART_THRE | Transmitter holding register empty bit mask (0x20) | + | UART_TEMT | Transmitter empty bit mask (0x40) | + + */ +#define UART_TX_BUSY ((uint8_t) 0x00) +#define UART_THRE ((uint8_t) 0x20) +#define UART_TEMT ((uint8_t) 0x40) + +/***************************************************************************//** + Modem Status + ============ + The following defines are used to determine the modem status. These bit + mask constants are used with the return value of the + UART_get_modem_status() function to find out the modem status of + the UART. + + | Constant | Description | + |---------------|-------------------------------------------------| + | UART_DCTS | Delta clear to send bit mask (0x01) | + | UART_DDSR | Delta data set ready bit mask (0x02) | + | UART_TERI | Trailing edge of ring indicator bit mask (0x04) | + | UART_DDCD | Delta data carrier detect bit mask (0x08) | + | UART_CTS | Clear to send bit mask (0x10) | + | UART_DSR | Data set ready bit mask (0x20) | + | UART_RI | Ring indicator bit mask (0x40) | + | UART_DCD | Data carrier detect bit mask (0x80) | + */ +#define UART_DCTS ((uint8_t) 0x01) +#define UART_DDSR ((uint8_t) 0x02) +#define UART_TERI ((uint8_t) 0x04) +#define UART_DDCD ((uint8_t) 0x08) +#define UART_CTS ((uint8_t) 0x10) +#define UART_DSR ((uint8_t) 0x20) +#define UART_RI ((uint8_t) 0x40) +#define UART_DCD ((uint8_t) 0x80) + +/***************************************************************************//** + This typedef specifies the irq_mask parameter for the UART_enable_irq() + and UART_disable_irq() functions. The driver defines a set of bit masks + that are used to build the value of the irq_mask parameter. A bitwise OR of + these bit masks is used to enable or disable multipleUART interrupts. + */ +typedef uint16_t uart_irq_t; + +/***************************************************************************//** + UART Interrupts + ===================== + The following defines specify the interrupt masks to enable and disable + UART interrupts. They are used to build the value of the irq_mask parameter + for the UART_enable_irq() and UART_disable_irq() functions. A bitwise + OR of these constants is used to enable or disable multiple interrupts. + + + | Constant | Description | + |--------------------|---------------------------------------------------------------| + | UART_RBF_IRQ | Receive Data Available Interrupt bit mask (0x001) | + | UART_TBE_IRQ | Transmitter Holding Register Empty interrupt bit mask (0x002) | + | UART_LS_IRQ | Receiver Line Status interrupt bit mask (0x004) | + | UART_MS_IRQ | Modem Status interrupt bit mask (0x008) | + + */ +#define UART_RBF_IRQ 0x001 +#define UART_TBE_IRQ 0x002 +#define UART_LS_IRQ 0x004 +#define UART_MS_IRQ 0x008 +//#define UART_RTO_IRQ 0x010 +//#define UART_NACK_IRQ 0x020 +//#define UART_PIDPE_IRQ 0x040 +//#define UART_LINB_IRQ 0x080 +//#define UART_LINS_IRQ 0x100 +#define UART_INVALID_IRQ UINT16_MAX + +/***************************************************************************//** + This enumeration specifies the receiver FIFO trigger level. This is the number + of bytes that must be received before the UART generates a receive data + available interrupt. It provides the allowed values for the + UART_set_rx_handler() function trigger_level parameter. + */ +typedef enum { + UART_FIFO_SINGLE_BYTE = 0x00, + UART_FIFO_FOUR_BYTES = 0x40, + UART_FIFO_EIGHT_BYTES = 0x80, + UART_FIFO_FOURTEEN_BYTES = 0xC0, + UART_FIFO_INVALID_TRIG_LEVEL + +} uart_rx_trig_level_t; + + + + +/***************************************************************************//** + UART instance type. + This is type definition for UART instance. You need to create and + maintain a record of this type. This holds all data regarding the UART + instance + */ +typedef struct uart_instance uart_instance_t; + +/***************************************************************************//** + Interrupt handler prototype. + This typedef specifies the function prototype for UART interrupt handlers. + All interrupt handlers registered with the UART driver must be of this type. + The interrupt handlers are registered with the driver through the + UART_set_rx_handler(), UART_set_tx_handler(), + UART_set_rxstatus_handler(), and UART_set_modemstatus_handler() + functions. + The this_uart parameter is a pointer to either g_uart0 or g_uart1 to + identify the UART to associate with the handler function. + */ +typedef void (*uart_irq_handler_t)( uart_instance_t * this_uart ); + + +/******************************************************************************* + Register Bit definitions + */ + +/* Line Control register bit definitions */ +#define SB 6u /* Set break */ +#define DLAB 7u /* Divisor latch access bit */ + +/* Line Control register bit masks */ +#define SB_MASK (0x01u << SB) /* Set break */ +#define DLAB_MASK (0x01u << DLAB) /* Divisor latch access bit */ + +/* FIFO Control register bit definitions */ +#define ENABLE_FIFO 0u /* Enable FIFO */ +#define CLEAR_RX_FIFO 1u /* Clear receiver FIFO */ +#define CLEAR_TX_FIFO 2u /* Clear transmitter FIFO */ +#define DMA_MODE 3u /* DMA mode */ +#define FIFO64_ENABLE 5u /* FIFO64 enable */ +#define RDYMODE 3u /* Mode 0 or Mode 1 for TXRDY and RXRDY */ +#define FIFO_RX_TRIGGER 6u /* FIFO RX trigger */ + +/* FIFO Control register bit MASKS */ +#define RXRDY_TXRDYN_EN_MASK (0x01u << 0u) /* Enable TXRDY and RXRDY signals */ +#define CLEAR_RX_FIFO_MASK (0x01u << 1u) /* Clear receiver FIFO */ +#define CLEAR_TX_FIFO_MASK (0x01u << 2u) /* Clear transmitter FIFO */ +#define DMA_MODE_MASK (0x01u << 3u) /* DMA mode */ +#define FIFO64_ENABLE_MASK (0x01u << 5u) /* FIFO64 enable */ +#define RDYMODE_MASK (0x01u << 3u) /* Mode 0 or Mode 1 for TXRDY and RXRDY */ + +#define FIFO_RX_TRIGGER_LEVEL_4_MASK (0x01u << 6u) +#define FIFO_RX_TRIGGER_LEVEL_8_MASK (0x02u << 6u) +#define FIFO_RX_TRIGGER_LEVEL_14_MASK (0x03u << 6u) + +#define FIFO64_RX_TRIGGER_LEVEL_16_MASK (0x01u << 6u) +#define FIFO64_RX_TRIGGER_LEVEL_32_MASK (0x02u << 6u) +#define FIFO64_RX_TRIGGER_LEVEL_56_MASK (0x03u << 6u) + +/* Modem Control register bit definitions */ +//#define LOOP 4u /* Local loopback */ +//#define RLOOP 5u /* Remote loopback */ +//#define ECHO 6u /* Automatic echo */ + +/* Modem Control register bit MASKS */ +//#define LOOP_MASK (0x01u << 4u) /* Local loopback */ +//#define RLOOP_MASK (0x01u << 5u) /* Remote loopback & Automatic echo*/ +//#define ECHO_MASK (0x01u << 6u) /* Automatic echo */ + +/* Line Status register bit definitions */ +#define DR 0u /* Data ready */ +#define THRE 5u /* Transmitter holding register empty */ +#define TEMT 6u /* Transmitter empty */ + +/* Line Status register bit MASKS */ +#define DR_MASK (0x01u << 0u) /* Data ready */ +#define THRE_MASK (0x01u << 5u) /* Transmitter holding register empty */ +#define TEMT_MASK (0x01u << 6u) /* Transmitter empty */ + +/* Interrupt Enable register bit definitions */ +#define ERBFI 0u /* Enable receiver buffer full interrupt */ +#define ETBEI 1u /* Enable transmitter buffer empty interrupt */ +#define ELSI 2u /* Enable line status interrupt */ +#define EDSSI 3u /* Enable modem status interrupt */ + +/* Interrupt Enable register bit MASKS */ +#define ERBFI_MASK (0x01u << 0u) /* Enable receiver buffer full interrupt */ +#define ETBEI_MASK (0x01u << 1u) /* Enable transmitter buffer empty interrupt */ +#define ELSI_MASK (0x01u << 2u) /* Enable line status interrupt */ +#define EDSSI_MASK (0x01u << 3u) /* Enable modem status interrupt */ + +/* Multimode register 0 bit definitions */ +#define ELIN 3u /* Enable LIN header detection */ +#define ETTG 5u /* Enable transmitter time guard */ +#define ERTO 6u /* Enable receiver time-out */ +#define EFBR 7u /* Enable fractional baud rate mode */ + +/* Multimode register 0 bit MASKS */ +#define ELIN_MASK (0x01u << 3u) /* Enable LIN header detection */ +#define ETTG_MASK (0x01u << 5u) /* Enable transmitter time guard */ +#define ERTO_MASK (0x01u << 6u) /* Enable receiver time-out */ +#define EFBR_MASK (0x01u << 7u) /* Enable fractional baud rate mode */ + +/* Multimode register 1 bit definitions */ +#define E_MSB_RX 0u /* MSB / LSB first for receiver */ +#define E_MSB_TX 1u /* MSB / LSB first for transmitter */ +#define EIRD 2u /* Enable IrDA modem */ +#define EIRX 3u /* Input polarity for IrDA modem */ +#define EITX 4u /* Output polarity for IrDA modem */ +#define EITP 5u /* Output pulse width for IrDA modem */ + +/* Multimode register 1 bit MASKS */ +#define E_MSB_RX_MASK (0x01u << 0u) /* MSB / LSB first for receiver */ +#define E_MSB_TX_MASK (0x01u << 1u) /* MSB / LSB first for transmitter */ +#define EIRD_MASK (0x01u << 2u) /* Enable IrDA modem */ +#define EIRX_MASK (0x01u << 3u) /* Input polarity for IrDA modem */ +#define EITX_MASK (0x01u << 4u) /* Output polarity for IrDA modem */ +#define EITP_MASK (0x01u << 5u) /* Output pulse width for IrDA modem */ + +/* Multimode register 2 bit definitions */ +//#define EERR 0u /* Enable ERR / NACK during stop time */ +//#define EAFM 1u /* Enable 9-bit address flag mode */ +//#define EAFC 2u /* Enable address flag clear */ +//#define ESWM 3u /* Enable single wire half-duplex mode */ + +/* Multimode register 2 bit MASKS */ +//#define EERR_MASK (0x01u << 0u) /* Enable ERR / NACK during stop time */ +//#define EAFM_MASK (0x01u << 1u) /* Enable 9-bit address flag mode */ +//#define EAFC_MASK (0x01u << 2u) /* Enable address flag clear */ +//#define ESWM_MASK (0x01u << 3u) /* Enable single wire half-duplex mode */ + +/* Multimode Interrupt Enable register and + Multimode Interrupt Identification register definitions */ +//#define ERTOI 0u /* Enable receiver timeout interrupt */ +//#define ENACKI 1u /* Enable NACK / ERR interrupt */ +//#define EPID_PEI 2u /* Enable PID parity error interrupt */ +//#define ELINBI 3u /* Enable LIN break interrupt */ +//#define ELINSI 4u /* Enable LIN sync detection interrupt */ + +/* Multimode Interrupt Enable register and + Multimode Interrupt Identification register MASKS */ +//#define ERTOI_MASK (0x01u << 0u) /* Enable receiver timeout interrupt */ +//#define ENACKI_MASK (0x01u << 1u) /* Enable NACK / ERR interrupt */ +//#define EPID_PEI_MASK (0x01u << 2u) /* Enable PID parity error interrupt */ +//#define ELINBI_MASK (0x01u << 3u) /* Enable LIN break interrupt */ +//#define ELINSI_MASK (0x01u << 4u) /* Enable LIN sync detection interrupt */ + +typedef struct +{ + union + { + volatile const uint8_t RBR; + volatile uint8_t THR; + volatile uint8_t DLL; + uint32_t RESERVED0; + }; + + union + { + volatile uint8_t DLM; + volatile uint8_t IER; + uint32_t RESERVED1; + }; + + union + { + volatile uint8_t IIR; + volatile uint8_t FCR; + uint32_t RESERVED2; + }; + + volatile uint8_t LCR; + uint8_t RESERVED3[3]; + + volatile uint8_t MCR; + uint8_t RESERVED4[3]; + + volatile const uint8_t LSR; + uint8_t RESERVED5[3]; + + volatile const uint8_t MSR; + uint8_t RESERVED6[3]; + + volatile uint8_t SR; + uint8_t RESERVED7[7]; + +} UART_TypeDef; + + +/***************************************************************************//** + uart_instance. + There is one instance of this structure for each instance of the + microprocessor subsystem's UARTs. Instances of this structure are used to + identify a specific UART. A pointer to an initialized instance of the + uart_instance_t structure is passed as the first parameter to + UART driver functions to identify which UART should perform the + requested operation. + */ +struct uart_instance{ + /* CMSIS related defines identifying the UART hardware. */ + UART_TypeDef * hw_reg; /*!< Pointer to UART registers. */ + uint32_t baudrate; /*!< Operating baud rate. */ + uint8_t lineconfig; /*!< Line configuration parameters. */ + uint8_t status; /*!< Sticky line status. */ + + /* transmit related info (used with interrupt driven transmit): */ + const uint8_t * tx_buffer; /*!< Pointer to transmit buffer. */ + uint32_t tx_buff_size; /*!< Transmit buffer size. */ + uint32_t tx_idx; /*!< Index within transmit buffer of next byte to transmit.*/ + + /* line status interrupt handler:*/ + uart_irq_handler_t linests_handler; /*!< Pointer to user registered line status handler. */ + /* receive interrupt handler:*/ + uart_irq_handler_t rx_handler; /*!< Pointer to user registered receiver handler. */ + /* transmit interrupt handler:*/ + uart_irq_handler_t tx_handler; /*!< Pointer to user registered transmit handler. */ + /* modem status interrupt handler:*/ + uart_irq_handler_t modemsts_handler; /*!< Pointer to user registered modem status handler. */ + + + +}; + +extern uart_instance_t g_uart_0; + +static void default_tx_handler(uart_instance_t * this_uart); +static void enable_irq(const uart_instance_t * this_uart); + +static void disable_irq(const uart_instance_t * this_uart); + +static void config_baud_divisors +( + uart_instance_t * this_uart, + uint32_t baudrate +); + +/***************************************************************************//** + The UART_init() function initializes and configures the + UART with the configuration passed as a parameter. The configuration + parameters are the baud_rate which is used to generate the baud value and the + line_config which is used to specify the line configuration (bit length, + stop bits and parity). + @param this_uart + The this_uart parameter is a pointer to an uart_instance_t + structure identifying the UART hardware block that will perform + the requested function. + @param baud_rate + The baud_rate parameter specifies the baud rate. It can be specified for + common baud rates using the following defines: + - UART_110_BAUD + - UART_300_BAUD + - UART_600_BAUD + - UART_1200_BAUD + - UART_2400_BAUD + - UART_4800_BAUD + - UART_9600_BAUD + - UART_19200_BAUD + - UART_38400_BAUD + - UART_57600_BAUD + - UART_115200_BAUD + - UART_230400_BAUD + - UART_460800_BAUD + - UART_921600_BAUD + + Alternatively, any nonstandard baud rate can be specified by simply passing + the actual required baud rate as the value for this parameter. + @param line_config + The line_config parameter is the line configuration specifying the bit length, + number of stop bits and parity settings. + + This is a bitwise OR of one value from each of the following groups of + allowed values: + + One of the following to specify the transmit/receive data bit length: + - UART_DATA_5_BITS + - UART_DATA_6_BITS, + - UART_DATA_7_BITS + - UART_DATA_8_BITS + + One of the following to specify the parity setting: + - UART_NO_PARITY + - UART_EVEN_PARITY + - UART_ODD_PARITY + - UART_STICK_PARITY_0 + - UART_STICK_PARITY_1 + + One of the following to specify the number of stop bits: + - UART_ONE_STOP_BIT + - UART_ONEHALF_STOP_BIT + - UART_TWO_STOP_BITS + @return + This function does not return a value. + Example: + @code + #include "uart.h" + int main(void) + { + UART_init(&g_uart0_lo, + UART_57600_BAUD, + UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT); + + return(0); + } + @endcode + */ +void +UART_init_ariane +( + uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config +); + +/***************************************************************************//** + The function UART_polled_tx() is used to transmit data. It transfers the + contents of the transmitter data buffer, passed as a function parameter, into + the UART's hardware transmitter FIFO. It returns when the full content of the + transmit data buffer has been transferred to the UART's transmit FIFO. It is + safe to release or reuse the memory used as the transmitter data buffer once + this function returns. + Note: This function reads the UART's line status register (LSR) to poll + for the active state of the transmitter holding register empty (THRE) bit + before transferring data from the data buffer to the transmitter FIFO. It + transfers data to the transmitter FIFO in blocks of 16 bytes or less and + allows the FIFO to empty before transferring the next block of data. + Note: The actual transmission over the serial connection will still be + in progress when this function returns. Use the UART_get_tx_status() + function if you need to know when the transmitter is empty. + @param this_uart + The this_uart parameter is a pointer to an uart_instance_t + structure identifying the UART hardware block that will perform + the requested function. + @param pbuff + The pbuff parameter is a pointer to a buffer containing the data to + be transmitted. + @param tx_size + The tx_size parameter specifies the size, in bytes, of the data to + be transmitted. + @return + This function does not return a value. + Example: + @code + #include "uart.h" + int main(void) + { + uint8_t message[12] = "Hello World"; + UART_init(&g_uart0_lo, + UART_57600_BAUD, + SS_UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT); + UART_polled_tx(&g_uart0_lo, message, sizeof(message)); + + return(0); + } + @endcode + */ +void +UART_polled_tx +( + uart_instance_t * this_uart, + const uint8_t * pbuff, + uint32_t tx_size +); + +/***************************************************************************//** + The function UART_polled_tx_string() is used to transmit a NULL ('\0') + terminated string. It transfers the text string, from the buffer starting at + the address pointed to by p_sz_string into the UART's hardware transmitter + FIFO. It returns when the complete string has been transferred to the UART's + transmit FIFO. It is safe to release or reuse the memory used as the string + buffer once this function returns. + Note: This function reads the UART's line status register (LSR) to poll + for the active state of the transmitter holding register empty (THRE) bit + before transferring data from the data buffer to the transmitter FIFO. It + transfers data to the transmitter FIFO in blocks of 16 bytes or less and + allows the FIFO to empty before transferring the next block of data. + Note: The actual transmission over the serial connection will still be + in progress when this function returns. Use the UART_get_tx_status() + function if you need to know when the transmitter is empty. + @param this_uart + The this_uart parameter is a pointer to an uart_instance_t + structure identifying the UART hardware block that will perform + the requested function. + @param p_sz_string + The p_sz_string parameter is a pointer to a buffer containing the NULL + ('\0') terminated string to be transmitted. + @return + This function does not return a value. + Example: + @code + #include "uart.h" + int main(void) + { + uint8_t message[12] = "Hello World"; + UART_init(&g_uart0_lo, + UART_57600_BAUD, + UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT); + + UART_polled_tx_string(&g_uart0_lo, message); + + return(0); + } + @endcode + */ +void +UART_polled_tx_string +( + uart_instance_t * this_uart, + const uint8_t * p_sz_string +); + +/***************************************************************************//** + The function UART_irq_tx() is used to initiate an interrupt-driven + transmit. It returns immediately after making a note of the transmit buffer + location and enabling transmit interrupts both at the UART and the PolarFire + SoC Core Complex PLIC level. This function takes a pointer via the pbuff + parameter to a memory buffer containing the data to transmit. The memory + buffer specified through this pointer must remain allocated and contain the + data to transmit until the transmit completion has been detected through calls + to function UART_tx_complete(). The actual transmission over the serial + connection is still in progress until calls to the UART_tx_complete() + function indicate transmit completion. + Note: The UART_irq_tx() function enables both the transmit holding + register empty (THRE) interrupt in the UART and the UART instance + interrupt in the PolarFire SoC Core Complex PLIC as part of its implementation. + Note: The UART_irq_tx() function assigns an internal default transmit + interrupt handler function to the UART's THRE interrupt. This interrupt + handler overrides any custom interrupt handler that you may have previously + registered using the UART_set_tx_handler() function. + Note: The UART_irq_tx() function's default transmit interrupt + handler disables the UART's THRE interrupt when all of the data has + been transferred to the UART's transmit FIFO. + @param this_uart + The this_uart parameter is a pointer to an uart_instance_t + structure identifying the UART hardware block that will perform + the requested function. + @param pbuff + The pbuff parameter is a pointer to a buffer containing the data + to be transmitted. + @param tx_size + The tx_size parameter specifies the size, in bytes, of the data + to be transmitted. + @return + This function does not return a value. + Example: + @code + #include "uart.h" + int main(void) + { + uint8_t tx_buff[10] = "abcdefghi"; + + UART_init(&g_uart0_lo, + UART_57600_BAUD, + UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT); + + UART_irq_tx(&g_uart0_lo, tx_buff, sizeof(tx_buff)); + + while(0 == UART_tx_complete(&g_uart0_lo)) + { + ; + } + return(0); + } + @endcode + */ +void +UART_irq_tx +( + uart_instance_t * this_uart, + const uint8_t * pbuff, + uint32_t tx_size +); + +/***************************************************************************//** + The UART_tx_complete() function is used to find out if the + interrupt-driven transmit previously initiated through a call to + UART_irq_tx() is complete. This is typically used to find out when it is + safe to reuse or release the memory buffer holding transmit data. + Note: The transfer of all of the data from the memory buffer to the UART's + transmit FIFO and the actual transmission over the serial connection are both + complete when a call to the UART_tx_complete() function indicates transmit + completion. + @param this_uart + The this_uart parameter is a pointer to an uart_instance_t + structure identifying the UART hardware block that will perform + the requested function. + @return + This function return a non-zero value if transmit has completed, otherwise + it returns zero. + Example: + See the UART_irq_tx() function for an example that uses the + UART_tx_complete() function. + */ +int8_t +UART_tx_complete +( + uart_instance_t * this_uart +); + +/***************************************************************************//** + The UART_get_rx() function reads the content of the UART receiver's FIFO + and stores it in the receive buffer that is passed via the rx_buff function + parameter. It copies either the full contents of the FIFO into the receive + buffer, or just enough data from the FIFO to fill the receive buffer, + dependent upon the size of the receive buffer passed by the buff_size + parameter. The UART_get_rx() function returns the number of bytes copied + into the receive buffer .This function is non-blocking and will return 0 + immediately if no data has been received. + Note: The UART_get_rx() function reads and accumulates the receiver + status of the UART instance before reading each byte from the receiver's + data register/FIFO. This allows the driver to maintain a sticky record of any + receiver errors that occur as the UART receives each data byte; receiver + errors would otherwise be lost after each read from the receiver's data + register. A call to the UART_get_rx_status() function returns any receiver + errors accumulated during the execution of the UART_get_rx() function. + Note: If you need to read the error status for each byte received, set + the buff_size to 1 and read the receive line error status for each byte + using the UART_get_rx_status() function. + The UART_get_rx() function can be used in polled mode, where it is called + at regular intervals to find out if any data has been received, or in + interrupt driven-mode, where it is called as part of a receive handler that is + called by the driver as a result of data being received. + Note: In interrupt driven mode you should call the UART_get_rx() + function as part of the receive handler function that you register with + the UART driver through a call to UART_set_rx_handler(). + @param this_uart + The this_uart parameter is a pointer to an uart_instance_t + structure identifying the UART hardware block that will perform + the requested function. + @param rx_buff + The rx_buff parameter is a pointer to a buffer where the received + data is copied. + @param buff_size + The buff_size parameter specifies the size of the receive buffer in bytes. + @return + This function returns the number of bytes that were copied into the + rx_buff buffer. It returns 0 if no data has been received. + Polled mode example: + @code + int main( void ) + { + uint8_t rx_buff[RX_BUFF_SIZE]; + uint32_t rx_idx = 0; + UART_init(&g_uart0_lo, + UART_57600_BAUD, + UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT); + + while(1) + { + rx_size = UART_get_rx(&g_uart0_lo, rx_buff, sizeof(rx_buff)); + if(rx_size > 0) + { + process_rx_data(rx_buff, rx_size); + } + task_a(); + task_b(); + } + return 0; + } + @endcode + Interrupt driven example: + @code + int main( void ) + { + UART_init(&g_uart1, + UART_57600_BAUD, + UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT); + + UART_set_rx_handler(&g_uart1, + uart1_rx_handler, + UART_FIFO_SINGLE_BYTE); + + while(1) + { + task_a(); + task_b(); + } + return 0; + } + void uart1_rx_handler(uart_instance_t * this_uart) + { + uint8_t rx_buff[RX_BUFF_SIZE]; + uint32_t rx_idx = 0; + rx_size = UART_get_rx(this_uart, rx_buff, sizeof(rx_buff)); + process_rx_data(rx_buff, rx_size); + } + @endcode + */ +size_t +UART_get_rx +( + uart_instance_t * this_uart, + uint8_t * rx_buff, + size_t buff_size +); + +/***************************************************************************//** + The UART_set_rx_handler() function is used to register a receive handler + function that is called by the driver when a UART receive data available (RDA) + interrupt occurs. You must create and register the receive handler function + to suit your application and it must include a call to the UART_get_rx() + function to actually read the received data. + Note: The UART_set_rx_handler() function enables both the RDA + interrupt in the UART instance. It also enables the corresponding + UART instance interrupt in the PolarFire SoC Core Complex PLIC as part + of its implementation. + Note: You can disable the RDA interrupt when required by calling the + UART_disable_irq() function. This is your choice and is dependent upon + your application. + + @param this_uart + The this_uart parameter is a pointer to an uart_instance_t + structure identifying the UART hardware block that will perform + the requested function. + @param handler + The handler parameter is a pointer to a receive interrupt handler function + provided by your application that will be called as a result of a UART RDA + interrupt. This handler function must be of type uart_irq_handler_t. + @param trigger_level + The trigger_level parameter is the receive FIFO trigger level. This + specifies the number of bytes that must be received before the UART + triggers an RDA interrupt. + @return + This function does not return a value. + Example: + @code + #include "uart.h" + #define RX_BUFF_SIZE 64 + uint8_t g_rx_buff[RX_BUFF_SIZE]; + void uart0_rx_handler(uart_instance_t * this_uart) + { + UART_get_rx(this_uart, &g_rx_buff[g_rx_idx], sizeof(g_rx_buff)); + } + int main(void) + { + UART_init(&g_uart0_lo, + UART_57600_BAUD, + UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT); + + UART_set_rx_handler(&g_uart0_lo, + uart0_rx_handler, + UART_FIFO_SINGLE_BYTE); + + while(1) + { + ; + } + return(0); + } + @endcode + */ +void +UART_set_rx_handler +( + uart_instance_t * this_uart, + uart_irq_handler_t handler, + uart_rx_trig_level_t trigger_level +); + + +#endif /*__UART_H_*/ + From 0dd6d28afb54c17eae485fa8e7c9e6a7999353ff Mon Sep 17 00:00:00 2001 From: Christos Papadopoulos Date: Wed, 13 May 2026 15:00:54 +0200 Subject: [PATCH 14/29] Fixed MPIE being cleared leading to have interrupts being disable after an mret instruction (#522) * Fixed MPIE being cleared leading to have interrupts being disable when returning from machine mode * Removed wrong register operand and replaced by immediate value --- .../gnu/src/tx_thread_context_restore.S | 27 +++++++------------ 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/ports/risc-v64/gnu/src/tx_thread_context_restore.S b/ports/risc-v64/gnu/src/tx_thread_context_restore.S index 4473a39b2..b73b485d4 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_restore.S @@ -175,18 +175,10 @@ _tx_thread_context_restore: Set MPIE and restore MPP to Machine, preserve other fields. */ csrr t1, mstatus + li t2, 0x1880 // Set MPP(0x1800) | MPIE(0x80) - /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ - - li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) - - /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, - preserve everything except the bits we will modify. */ - - li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE - and t1, t1, t4 - or t1, t1, t3 + or t1, t1, t2 // MPP and MPIE are now set. All other bits are preserved + andi t1, t1, ~0x8 // Clear MIE, Hardware will restore it from MPIE #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state @@ -352,14 +344,15 @@ _tx_thread_no_preempt_restore: ld t0, 30*8(sp) // Recover mepc csrw mepc, t0 // Setup mepc - /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */ + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. + Set MPIE and restore MPP to Machine, preserve other fields. */ csrr t1, mstatus - li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode - li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE - and t1, t1, t4 - or t1, t1, t3 + li t2, 0x1880 // Set MPP(0x1800) | MPIE(0x80) + + or t1, t1, t2 // MPP and MPIE are now set. All other bits are preserved + andi t1, t1, ~0x8 // Clear MIE, Hardware will restore it from MPIE #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) li t0, 0x2000 // Set FS bits for FP state From c1e3678797d5249268756287a33e5aca729a7631 Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Tue, 19 May 2026 20:03:23 +0500 Subject: [PATCH 15/29] Add QEMU based CI regression test infra for RV32 and RV64 (#526) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added a QEMU virt-machine BSP and CTest infrastructure to run the ThreadX regression suite on both RISC-V 32-bit and 64-bit targets in CI. New components: - BSP (entry, trap, PLIC, CLINT timer, UART, linker script) targeting QEMU virt machine for RV32 and RV64 - CMake build system with Ninja, supporting multiple build configs - CI scripts: install_riscv.sh (toolchain + QEMU), build_tx_riscv.sh, test_tx_riscv.sh - GitHub Actions workflow job for RISC-V regression gating Port fixes: - RV32 tx_thread_context_restore.S: set MPIE alongside MPP (0x1800 → 0x1880) so mret re-enables interrupts - RV32/RV64 tx_port.h: add TX_REGRESSION_TEST extension macros needed by the test harness - RV32/RV64 example_build scripts: add compile and QEMU launch steps Regression test portability fixes: - Block memory tests: increase pool sizes (320 → 340) to accommodate larger RISC-V block-header alignment - Byte memory test: replace hardcoded offsets with BYTE_POOL_OVERHEAD macro for portable pool-size computation - Event flag timeout test: make counter tolerance unconditional, removing linux-only guard Signed-off-by: Akif Ejaz --- .github/workflows/regression_test.yml | 19 +- common/src/tx_trace_object_register.c | 4 +- common/src/tx_trace_object_unregister.c | 2 +- .../qemu_virt/build_libthreadx.sh | 21 ++- ports/risc-v32/gnu/inc/tx_port.h | 98 ++++++++++ .../gnu/src/tx_thread_context_restore.S | 2 +- .../qemu_virt/build_libthreadx.sh | 18 ++ ports/risc-v64/gnu/inc/tx_port.h | 98 ++++++++++ scripts/build_tx_riscv.sh | 15 ++ scripts/install_riscv.sh | 32 ++++ scripts/test_tx_riscv.sh | 19 ++ test/tx/cmake/riscv/CMakeLists.txt | 79 ++++++++ test/tx/cmake/riscv/bsp/CMakeLists.txt | 25 +++ test/tx/cmake/riscv/bsp/board.c | 30 ++++ test/tx/cmake/riscv/bsp/csr.h | 84 +++++++++ test/tx/cmake/riscv/bsp/entry.S | 75 ++++++++ test/tx/cmake/riscv/bsp/hwtimer.c | 33 ++++ test/tx/cmake/riscv/bsp/hwtimer.h | 22 +++ test/tx/cmake/riscv/bsp/link.lds | 60 +++++++ test/tx/cmake/riscv/bsp/plic.c | 87 +++++++++ test/tx/cmake/riscv/bsp/plic.h | 46 +++++ test/tx/cmake/riscv/bsp/printf.c | 168 ++++++++++++++++++ test/tx/cmake/riscv/bsp/syscalls.c | 128 +++++++++++++ test/tx/cmake/riscv/bsp/trap.c | 84 +++++++++ .../cmake/riscv/bsp/tx_initialize_low_level.S | 100 +++++++++++ test/tx/cmake/riscv/bsp/uart.c | 79 ++++++++ test/tx/cmake/riscv/bsp/uart.h | 22 +++ test/tx/cmake/riscv/regression/CMakeLists.txt | 165 +++++++++++++++++ test/tx/cmake/riscv/run.sh | 151 ++++++++++++++++ .../threadx_block_memory_basic_test.c | 8 +- ...hreadx_block_memory_error_detection_test.c | 8 +- .../threadx_block_memory_suspension_test.c | 4 +- ...adx_block_memory_suspension_timeout_test.c | 4 +- ...readx_block_memory_thread_terminate_test.c | 4 +- .../threadx_byte_memory_basic_test.c | 23 ++- ...readx_event_flag_suspension_timeout_test.c | 17 +- 36 files changed, 1796 insertions(+), 38 deletions(-) create mode 100755 scripts/build_tx_riscv.sh create mode 100755 scripts/install_riscv.sh create mode 100755 scripts/test_tx_riscv.sh create mode 100644 test/tx/cmake/riscv/CMakeLists.txt create mode 100644 test/tx/cmake/riscv/bsp/CMakeLists.txt create mode 100644 test/tx/cmake/riscv/bsp/board.c create mode 100644 test/tx/cmake/riscv/bsp/csr.h create mode 100644 test/tx/cmake/riscv/bsp/entry.S create mode 100644 test/tx/cmake/riscv/bsp/hwtimer.c create mode 100644 test/tx/cmake/riscv/bsp/hwtimer.h create mode 100644 test/tx/cmake/riscv/bsp/link.lds create mode 100644 test/tx/cmake/riscv/bsp/plic.c create mode 100644 test/tx/cmake/riscv/bsp/plic.h create mode 100644 test/tx/cmake/riscv/bsp/printf.c create mode 100644 test/tx/cmake/riscv/bsp/syscalls.c create mode 100644 test/tx/cmake/riscv/bsp/trap.c create mode 100644 test/tx/cmake/riscv/bsp/tx_initialize_low_level.S create mode 100644 test/tx/cmake/riscv/bsp/uart.c create mode 100644 test/tx/cmake/riscv/bsp/uart.h create mode 100644 test/tx/cmake/riscv/regression/CMakeLists.txt create mode 100755 test/tx/cmake/riscv/run.sh diff --git a/.github/workflows/regression_test.yml b/.github/workflows/regression_test.yml index c55a2c56e..72e4198ba 100644 --- a/.github/workflows/regression_test.yml +++ b/.github/workflows/regression_test.yml @@ -41,6 +41,23 @@ jobs: cmake_path: ./test/smp/cmake result_affix: SMP skip_deploy: true + riscv: + permissions: + contents: read + issues: read + checks: write + pull-requests: write + pages: write + id-token: write + uses: ./.github/workflows/regression_template.yml + with: + install_script: ./scripts/install_riscv.sh + build_script: ./scripts/build_tx_riscv.sh + test_script: ./scripts/test_tx_riscv.sh + cmake_path: ./test/tx/cmake/riscv + result_affix: RISC-V + skip_deploy: true + skip_coverage: true deploy: permissions: contents: read @@ -49,7 +66,7 @@ jobs: pull-requests: write pages: write id-token: write - needs: [tx, smp] + needs: [tx, smp, riscv] uses: ./.github/workflows/regression_template.yml with: skip_test: true diff --git a/common/src/tx_trace_object_register.c b/common/src/tx_trace_object_register.c index f7cd4a4a1..741896a5a 100644 --- a/common/src/tx_trace_object_register.c +++ b/common/src/tx_trace_object_register.c @@ -85,7 +85,7 @@ TX_TRACE_OBJECT_ENTRY *entry_ptr; /* Trace buffer is enabled, proceed. */ /* Pickup the total entries. */ - entries = _tx_trace_total_registry_entries; + entries = (UINT) _tx_trace_total_registry_entries; /* Determine if there are available entries in the registry. */ if (_tx_trace_available_registry_entries != ((ULONG) 0)) @@ -98,7 +98,7 @@ TX_TRACE_OBJECT_ENTRY *entry_ptr; loop_break = TX_FALSE; /* Loop to find available entry. */ - i = _tx_trace_registry_search_start; + i = (UINT) _tx_trace_registry_search_start; do { diff --git a/common/src/tx_trace_object_unregister.c b/common/src/tx_trace_object_unregister.c index 2166c9734..5d0330a5e 100644 --- a/common/src/tx_trace_object_unregister.c +++ b/common/src/tx_trace_object_unregister.c @@ -78,7 +78,7 @@ TX_TRACE_OBJECT_ENTRY *entry_ptr; /* Registry is setup, proceed. */ /* Pickup the total entries. */ - entries = _tx_trace_total_registry_entries; + entries = (UINT) _tx_trace_total_registry_entries; /* Loop to find available entry. */ for (i = ((ULONG) 0); i < entries; i++) diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh b/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh index ba6b40222..f3d806441 100755 --- a/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh +++ b/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh @@ -1,5 +1,24 @@ #!/bin/bash +printf "y\n" | rm -rf ../../../../../build/ +rm -f kernel.elf + pushd ../../../../../ cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_gnu.cmake . cmake --build ./build/ -popd \ No newline at end of file +popd + +riscv32-unknown-elf-gcc \ + -march=rv32gc -mabi=ilp32d \ + -mcmodel=medany -O0 -g3 -Wall \ + -ffunction-sections -fdata-sections \ + -I../../../../../common/inc \ + -I../../inc \ + entry.s \ + tx_initialize_low_level.S \ + board.c uart.c hwtimer.c plic.c trap.c demo_threadx.c \ + -L../../../../../build -lthreadx \ + -T link.lds -nostartfiles \ + -o kernel.elf + + +qemu-system-riscv32 -nographic -smp 1 -bios none -m 128M -machine virt -kernel kernel.elf diff --git a/ports/risc-v32/gnu/inc/tx_port.h b/ports/risc-v32/gnu/inc/tx_port.h index ed0146751..5348a02e3 100644 --- a/ports/risc-v32/gnu/inc/tx_port.h +++ b/ports/risc-v32/gnu/inc/tx_port.h @@ -271,6 +271,104 @@ UINT _tx_thread_interrupt_control(UIN #define TX_SEMAPHORE_DISABLE TX_DISABLE +/* Define automated coverage test extensions for the ThreadX regression test. */ + +#ifndef __ASSEMBLER__ + +typedef unsigned int TEST_FLAG; +extern TEST_FLAG threadx_byte_allocate_loop_test; +extern TEST_FLAG threadx_byte_release_loop_test; +extern TEST_FLAG threadx_mutex_suspension_put_test; +extern TEST_FLAG threadx_mutex_suspension_priority_test; +#ifndef TX_TIMER_PROCESS_IN_ISR +extern TEST_FLAG threadx_delete_timer_thread; +#endif + +extern void abort_and_resume_byte_allocating_thread(void); +extern void abort_all_threads_suspended_on_mutex(void); +extern void suspend_lowest_priority(void); +#ifndef TX_TIMER_PROCESS_IN_ISR +extern void delete_timer_thread(void); +#endif +extern TEST_FLAG test_stack_analyze_flag; +extern TEST_FLAG test_initialize_flag; +extern TEST_FLAG test_forced_mutex_timeout; + + +#ifdef TX_REGRESSION_TEST + +#define TX_BYTE_ALLOCATE_EXTENSION if (threadx_byte_allocate_loop_test == ((TEST_FLAG) 1)) \ + { \ + pool_ptr -> tx_byte_pool_owner = TX_NULL; \ + threadx_byte_allocate_loop_test = ((TEST_FLAG) 0); \ + } + +#define TX_BYTE_RELEASE_EXTENSION if (threadx_byte_release_loop_test == ((TEST_FLAG) 1)) \ + { \ + threadx_byte_release_loop_test = ((TEST_FLAG) 0); \ + abort_and_resume_byte_allocating_thread(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_1 if (threadx_mutex_suspension_put_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_put_test = ((TEST_FLAG) 0); \ + abort_all_threads_suspended_on_mutex(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_2 if (test_forced_mutex_timeout == ((TEST_FLAG) 1)) \ + { \ + test_forced_mutex_timeout = ((TEST_FLAG) 0); \ + _tx_thread_wait_abort(mutex_ptr -> tx_mutex_suspension_list); \ + } + +#define TX_MUTEX_PRIORITY_CHANGE_EXTENSION if (threadx_mutex_suspension_priority_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_priority_test = ((TEST_FLAG) 0); \ + suspend_lowest_priority(); \ + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + +#define TX_TIMER_INITIALIZE_EXTENSION(a) if (threadx_delete_timer_thread == ((TEST_FLAG) 1)) \ + { \ + threadx_delete_timer_thread = ((TEST_FLAG) 0); \ + delete_timer_thread(); \ + (a) = ((UINT) 1); \ + } + +#endif + +#define TX_THREAD_STACK_ANALYZE_EXTENSION if (test_stack_analyze_flag == ((TEST_FLAG) 1)) \ + { \ + thread_ptr -> tx_thread_id = ((TEST_FLAG) 0); \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 2)) \ + { \ + stack_ptr = thread_ptr -> tx_thread_stack_start; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 3)) \ + { \ + *stack_ptr = TX_STACK_FILL; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else \ + { \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } + +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION if (test_initialize_flag == ((TEST_FLAG) 1)) \ + { \ + test_initialize_flag = ((TEST_FLAG) 0); \ + return; \ + } + +#endif /* TX_REGRESSION_TEST */ + +#endif /* __ASSEMBLER__ */ + + /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifndef __ASSEMBLER__ diff --git a/ports/risc-v32/gnu/src/tx_thread_context_restore.S b/ports/risc-v32/gnu/src/tx_thread_context_restore.S index 73a07f61d..5fa80437d 100644 --- a/ports/risc-v32/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v32/gnu/src/tx_thread_context_restore.S @@ -284,7 +284,7 @@ _tx_thread_no_preempt_restore: csrr t1, mstatus li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode + li t3, 0x1880 // Set MPP=Machine(0x1800) + MPIE(0x80) so mret re-enables MIE li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE and t1, t1, t4 or t1, t1, t3 diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh b/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh index 24a4c3ac4..35f7ac5aa 100755 --- a/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh +++ b/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh @@ -1,6 +1,24 @@ #!/bin/bash +printf "y\n" | rm -rf ../../../../../build/ +rm -f kernel.elf pushd ../../../../../ cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv64_gnu.cmake . cmake --build ./build/ popd + +riscv64-unknown-elf-gcc \ + -march=rv64gc -mabi=lp64d \ + -mcmodel=medany -O0 -g3 -Wall \ + -ffunction-sections -fdata-sections \ + -I../../../../../common/inc \ + -I../../inc \ + entry.s \ + tx_initialize_low_level.S \ + board.c uart.c hwtimer.c plic.c trap.c demo_threadx.c \ + -L../../../../../build -lthreadx \ + -T link.lds -nostartfiles \ + -o kernel.elf + + +qemu-system-riscv64 -nographic -smp 1 -bios none -m 128M -machine virt -kernel kernel.elf diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h index c8f5b3124..2f3bac1b2 100644 --- a/ports/risc-v64/gnu/inc/tx_port.h +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -280,6 +280,104 @@ UINT _tx_thread_interrupt_control(UIN #define TX_SEMAPHORE_DISABLE TX_DISABLE +/* Define automated coverage test extensions for the ThreadX regression test. */ + +#ifndef __ASSEMBLER__ + +typedef unsigned int TEST_FLAG; +extern TEST_FLAG threadx_byte_allocate_loop_test; +extern TEST_FLAG threadx_byte_release_loop_test; +extern TEST_FLAG threadx_mutex_suspension_put_test; +extern TEST_FLAG threadx_mutex_suspension_priority_test; +#ifndef TX_TIMER_PROCESS_IN_ISR +extern TEST_FLAG threadx_delete_timer_thread; +#endif + +extern void abort_and_resume_byte_allocating_thread(void); +extern void abort_all_threads_suspended_on_mutex(void); +extern void suspend_lowest_priority(void); +#ifndef TX_TIMER_PROCESS_IN_ISR +extern void delete_timer_thread(void); +#endif +extern TEST_FLAG test_stack_analyze_flag; +extern TEST_FLAG test_initialize_flag; +extern TEST_FLAG test_forced_mutex_timeout; + + +#ifdef TX_REGRESSION_TEST + +#define TX_BYTE_ALLOCATE_EXTENSION if (threadx_byte_allocate_loop_test == ((TEST_FLAG) 1)) \ + { \ + pool_ptr -> tx_byte_pool_owner = TX_NULL; \ + threadx_byte_allocate_loop_test = ((TEST_FLAG) 0); \ + } + +#define TX_BYTE_RELEASE_EXTENSION if (threadx_byte_release_loop_test == ((TEST_FLAG) 1)) \ + { \ + threadx_byte_release_loop_test = ((TEST_FLAG) 0); \ + abort_and_resume_byte_allocating_thread(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_1 if (threadx_mutex_suspension_put_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_put_test = ((TEST_FLAG) 0); \ + abort_all_threads_suspended_on_mutex(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_2 if (test_forced_mutex_timeout == ((TEST_FLAG) 1)) \ + { \ + test_forced_mutex_timeout = ((TEST_FLAG) 0); \ + _tx_thread_wait_abort(mutex_ptr -> tx_mutex_suspension_list); \ + } + +#define TX_MUTEX_PRIORITY_CHANGE_EXTENSION if (threadx_mutex_suspension_priority_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_priority_test = ((TEST_FLAG) 0); \ + suspend_lowest_priority(); \ + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + +#define TX_TIMER_INITIALIZE_EXTENSION(a) if (threadx_delete_timer_thread == ((TEST_FLAG) 1)) \ + { \ + threadx_delete_timer_thread = ((TEST_FLAG) 0); \ + delete_timer_thread(); \ + (a) = ((UINT) 1); \ + } + +#endif + +#define TX_THREAD_STACK_ANALYZE_EXTENSION if (test_stack_analyze_flag == ((TEST_FLAG) 1)) \ + { \ + thread_ptr -> tx_thread_id = ((TEST_FLAG) 0); \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 2)) \ + { \ + stack_ptr = thread_ptr -> tx_thread_stack_start; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 3)) \ + { \ + *stack_ptr = TX_STACK_FILL; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else \ + { \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } + +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION if (test_initialize_flag == ((TEST_FLAG) 1)) \ + { \ + test_initialize_flag = ((TEST_FLAG) 0); \ + return; \ + } + +#endif /* TX_REGRESSION_TEST */ + +#endif /* __ASSEMBLER__ */ + + /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifndef __ASSEMBLER__ diff --git a/scripts/build_tx_riscv.sh b/scripts/build_tx_riscv.sh new file mode 100755 index 000000000..bad952dff --- /dev/null +++ b/scripts/build_tx_riscv.sh @@ -0,0 +1,15 @@ +#!/bin/bash +# Build RISC-V regression tests for both RV32 and RV64. +# Usage: build_tx_riscv.sh [all|] + +SCRIPT_DIR="$(dirname "$(realpath "$0")")" +RUN_SH="${SCRIPT_DIR}/../test/tx/cmake/riscv/run.sh" + +ARGS="${@:-all}" + +echo "=== Building RISC-V32 ===" +"$RUN_SH" riscv32 build $ARGS + +echo "" +echo "=== Building RISC-V64 ===" +"$RUN_SH" riscv64 build $ARGS diff --git a/scripts/install_riscv.sh b/scripts/install_riscv.sh new file mode 100755 index 000000000..9c2f2cdb8 --- /dev/null +++ b/scripts/install_riscv.sh @@ -0,0 +1,32 @@ +#!/bin/bash +# Install RISC-V bare-metal cross-compiler toolchain and QEMU for CI. +set -e + +RELEASE_TAG="2026.04.26" +BASE_URL="https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/${RELEASE_TAG}" +# Use ubuntu-24.04 binaries to match ubuntu-latest runners. +RV32_TARBALL="riscv32-elf-ubuntu-24.04-gcc.tar.xz" +RV64_TARBALL="riscv64-elf-ubuntu-24.04-gcc.tar.xz" + +echo "=== Installing QEMU and build tools ===" +sudo apt-get update -qq +sudo apt-get install -y -qq qemu-system-misc ninja-build cmake + +echo "=== Downloading RISC-V GCC toolchain (${RELEASE_TAG}) ===" + +# Both tarballs extract into riscv/ with non-overlapping prefixes +# (riscv32-unknown-elf-* and riscv64-unknown-elf-*). +for tarball in "$RV32_TARBALL" "$RV64_TARBALL"; do + echo "Downloading ${tarball} ..." + wget --no-verbose "${BASE_URL}/${tarball}" -O "/tmp/${tarball}" + sudo tar xJf "/tmp/${tarball}" -C /opt + rm "/tmp/${tarball}" +done + +TOOLCHAIN_BIN=/opt/riscv/bin +echo "$TOOLCHAIN_BIN" >> "$GITHUB_PATH" + +echo "=== Verifying installation ===" +"$TOOLCHAIN_BIN/riscv32-unknown-elf-gcc" --version | head -1 +"$TOOLCHAIN_BIN/riscv64-unknown-elf-gcc" --version | head -1 +qemu-system-riscv64 --version | head -1 diff --git a/scripts/test_tx_riscv.sh b/scripts/test_tx_riscv.sh new file mode 100755 index 000000000..7d35c53fc --- /dev/null +++ b/scripts/test_tx_riscv.sh @@ -0,0 +1,19 @@ +#!/bin/bash +# Run RISC-V regression tests for both RV32 and RV64 on QEMU. +# Usage: test_tx_riscv.sh [all|] + +SCRIPT_DIR="$(dirname "$(realpath "$0")")" +RUN_SH="${SCRIPT_DIR}/../test/tx/cmake/riscv/run.sh" + +ARGS="${@:-all}" + +exit_code=0 + +echo "=== Testing RISC-V32 ===" +CTEST_PARALLEL_LEVEL=4 "$RUN_SH" riscv32 test $ARGS || exit_code=$? + +echo "" +echo "=== Testing RISC-V64 ===" +CTEST_PARALLEL_LEVEL=4 "$RUN_SH" riscv64 test $ARGS || exit_code=$? + +exit $exit_code diff --git a/test/tx/cmake/riscv/CMakeLists.txt b/test/tx/cmake/riscv/CMakeLists.txt new file mode 100644 index 000000000..0352622d0 --- /dev/null +++ b/test/tx/cmake/riscv/CMakeLists.txt @@ -0,0 +1,79 @@ +cmake_minimum_required(VERSION 3.13 FATAL_ERROR) +cmake_policy(SET CMP0054 NEW) +cmake_policy(SET CMP0057 NEW) + +project(threadx_riscv_test LANGUAGES C ASM) + +# Build configurations (same defines as Linux tests, minus coverage instrumentation) +set(BUILD_CONFIGURATIONS default_build disable_notify_callbacks_build + stack_checking_build stack_checking_rand_fill_build trace_build) +set(CMAKE_CONFIGURATION_TYPES + ${BUILD_CONFIGURATIONS} + CACHE STRING "list of supported configuration types" FORCE) +set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS + ${CMAKE_CONFIGURATION_TYPES}) +list(GET CMAKE_CONFIGURATION_TYPES 0 BUILD_TYPE) +if((NOT CMAKE_BUILD_TYPE) OR (NOT ("${CMAKE_BUILD_TYPE}" IN_LIST + CMAKE_CONFIGURATION_TYPES))) + set(CMAKE_BUILD_TYPE + "${BUILD_TYPE}" + CACHE STRING "Build Type of the project" FORCE) +endif() + +message(STATUS "Build type: ${CMAKE_BUILD_TYPE}") +message(STATUS "Using toolchain file: ${CMAKE_TOOLCHAIN_FILE}.") +message(STATUS "THREADX_ARCH: ${THREADX_ARCH}") + +# Per-configuration compile definitions +set(default_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32) +set(disable_notify_callbacks_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_DISABLE_NOTIFY_CALLBACKS) +set(stack_checking_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_ENABLE_STACK_CHECKING) +set(stack_checking_rand_fill_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_ENABLE_STACK_CHECKING -DTX_ENABLE_RANDOM_NUMBER_STACK_FILLING) +set(trace_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_ENABLE_EVENT_TRACE) + +add_compile_options( + -std=c99 + -O0 + -g3 + -fdiagnostics-color + -Werror + -ffunction-sections + -fdata-sections + -DTX_REGRESSION_TEST + -DTEST_STACK_SIZE_PRINTF=4096 + -DEXTERNAL_EXIT + ${${CMAKE_BUILD_TYPE}} +) + +enable_testing() + +# Add ThreadX library (uses the RISC-V toolchain set by CMAKE_TOOLCHAIN_FILE) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../../../.. threadx) + +# Add BSP +add_subdirectory(bsp) + +# Add regression tests +add_subdirectory(regression) + +# Strict warning flags for the ThreadX library build +target_compile_options( + threadx + PRIVATE -Werror + -Wall + -Wextra + -pedantic + -fmessage-length=0 + -fsigned-char + -ffunction-sections + -fdata-sections + -Wunused + -Wuninitialized + -Wmissing-declarations + -Wconversion + -Wpointer-arith + -Wlogical-op + -Waggregate-return + -Wfloat-equal + $<$:-include$stdlib.h> +) diff --git a/test/tx/cmake/riscv/bsp/CMakeLists.txt b/test/tx/cmake/riscv/bsp/CMakeLists.txt new file mode 100644 index 000000000..a6b8171a1 --- /dev/null +++ b/test/tx/cmake/riscv/bsp/CMakeLists.txt @@ -0,0 +1,25 @@ +cmake_minimum_required(VERSION 3.13 FATAL_ERROR) + +# BSP library for RISC-V QEMU virt regression tests. +# Provides board init, UART, CLINT timer, PLIC, trap handler, +# newlib syscall stubs, and low-level ThreadX initialization. + +project(riscv_bsp LANGUAGES C ASM) + +set(BSP_DIR ${CMAKE_CURRENT_LIST_DIR}) + +add_library(riscv_bsp + ${BSP_DIR}/entry.S + ${BSP_DIR}/tx_initialize_low_level.S + ${BSP_DIR}/board.c + ${BSP_DIR}/trap.c + ${BSP_DIR}/hwtimer.c + ${BSP_DIR}/plic.c + ${BSP_DIR}/uart.c + ${BSP_DIR}/syscalls.c + ${BSP_DIR}/printf.c +) + +target_include_directories(riscv_bsp PUBLIC ${BSP_DIR}) +target_link_libraries(riscv_bsp PUBLIC azrtos::threadx) +target_compile_definitions(riscv_bsp PUBLIC EXTERNAL_EXIT) diff --git a/test/tx/cmake/riscv/bsp/board.c b/test/tx/cmake/riscv/bsp/board.c new file mode 100644 index 000000000..0891200e0 --- /dev/null +++ b/test/tx/cmake/riscv/bsp/board.c @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "plic.h" +#include "hwtimer.h" +#include "uart.h" +#include +#include + +int board_init(void) +{ + int ret; + ret = plic_init(); + if (ret) + return ret; + ret = uart_init(); + if (ret) + return ret; + ret = hwtimer_init(); + if (ret) + return ret; + return 0; +} diff --git a/test/tx/cmake/riscv/bsp/csr.h b/test/tx/cmake/riscv/bsp/csr.h new file mode 100644 index 000000000..f3d15f824 --- /dev/null +++ b/test/tx/cmake/riscv/bsp/csr.h @@ -0,0 +1,84 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_CSR_H +#define RISCV_CSR_H + +/* Machine Status Register, mstatus */ +#define MSTATUS_MPP_MASK (3L << 11) +#define MSTATUS_MPP_M (3L << 11) +#define MSTATUS_MPP_S (1L << 11) +#define MSTATUS_MPP_U (0L << 11) +#define MSTATUS_MIE (1L << 3) +#define MSTATUS_MPIE (1L << 7) +#define MSTATUS_FS (1L << 13) + +/* Machine-mode Interrupt Enable */ +#define MIE_MTIE (1L << 7) +#define MIE_MSIE (1L << 3) +#define MIE_MEIE (1L << 11) +#define MIE_STIE (1L << 5) +#define MIE_SSIE (1L << 1) +#define MIE_SEIE (1L << 9) + +#ifndef __ASSEMBLER__ + +#include + +static inline uintptr_t riscv_get_core(void) +{ + uintptr_t x; + __asm__ volatile("csrr %0, mhartid" : "=r" (x)); + return x; +} + +static inline uintptr_t riscv_get_mstatus(void) +{ + uintptr_t x; + __asm__ volatile("csrr %0, mstatus" : "=r" (x)); + return x; +} + +static inline void riscv_writ_mstatus(uintptr_t x) +{ + __asm__ volatile("csrw mstatus, %0" : : "r" (x)); +} + +static inline void riscv_mintr_on(void) +{ + uintptr_t mstatus = riscv_get_mstatus(); + mstatus |= MSTATUS_MIE; + riscv_writ_mstatus(mstatus); +} + +static inline void riscv_mintr_off(void) +{ + uintptr_t mstatus = riscv_get_mstatus(); + mstatus &= (~MSTATUS_MIE); + riscv_writ_mstatus(mstatus); +} + +static inline int riscv_mintr_get(void) +{ + uintptr_t x = riscv_get_mstatus(); + return (x & MSTATUS_MIE) != 0; +} + +static inline void riscv_mintr_restore(int x) +{ + if (x) + riscv_mintr_on(); + else + riscv_mintr_off(); +} + +#endif /* __ASSEMBLER__ */ + +#endif /* RISCV_CSR_H */ diff --git a/test/tx/cmake/riscv/bsp/entry.S b/test/tx/cmake/riscv/bsp/entry.S new file mode 100644 index 000000000..2f16c0525 --- /dev/null +++ b/test/tx/cmake/riscv/bsp/entry.S @@ -0,0 +1,75 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* Boot code for RISC-V QEMU virt regression tests. + Works for both RV32 and RV64 (instructions are width-agnostic). */ + +.section .text.init +.align 4 +.global _start +.extern main +.extern _sysstack_end +.extern _bss_start +.extern _bss_end + +_start: + csrr t0, mhartid + bne t0, zero, _secondary_halt + + /* Zero all general-purpose registers. */ + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + /* Set up stack pointer from linker symbol. */ + la sp, _sysstack_end + + /* Clear BSS. */ + la t0, _bss_start + la t1, _bss_end +_bss_clean: + bgeu t0, t1, _bss_done + sb zero, 0(t0) + addi t0, t0, 1 + j _bss_clean +_bss_done: + call main + +_secondary_halt: + wfi + j _secondary_halt diff --git a/test/tx/cmake/riscv/bsp/hwtimer.c b/test/tx/cmake/riscv/bsp/hwtimer.c new file mode 100644 index 000000000..99821f1ee --- /dev/null +++ b/test/tx/cmake/riscv/bsp/hwtimer.c @@ -0,0 +1,33 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "csr.h" +#include "hwtimer.h" +#include + +#define CLINT (0x02000000L) +#define CLINT_TIME (CLINT + 0xBFF8) +#define CLINT_TIMECMP(id) (CLINT + 0x4000 + 8 * (id)) + +int hwtimer_init(void) +{ + uintptr_t hart = riscv_get_core(); + uint64_t time = *((volatile uint64_t *)CLINT_TIME); + *((volatile uint64_t *)CLINT_TIMECMP(hart)) = time + TICKNUM_PER_TIMER; + return 0; +} + +int hwtimer_handler(void) +{ + uintptr_t hart = riscv_get_core(); + uint64_t time = *((volatile uint64_t *)CLINT_TIME); + *((volatile uint64_t *)CLINT_TIMECMP(hart)) = time + TICKNUM_PER_TIMER; + return 0; +} diff --git a/test/tx/cmake/riscv/bsp/hwtimer.h b/test/tx/cmake/riscv/bsp/hwtimer.h new file mode 100644 index 000000000..e6b9efa4e --- /dev/null +++ b/test/tx/cmake/riscv/bsp/hwtimer.h @@ -0,0 +1,22 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_HWTIMER_H +#define RISCV_HWTIMER_H + +#include + +#define TICKNUM_PER_SECOND 10000000 +#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 10) + +int hwtimer_init(void); +int hwtimer_handler(void); + +#endif /* RISCV_HWTIMER_H */ diff --git a/test/tx/cmake/riscv/bsp/link.lds b/test/tx/cmake/riscv/bsp/link.lds new file mode 100644 index 000000000..42f08fb6e --- /dev/null +++ b/test/tx/cmake/riscv/bsp/link.lds @@ -0,0 +1,60 @@ +/*************************************************************************** + * Linker script for RISC-V QEMU virt regression tests. + * Provides 128 MB RAM starting at 0x80000000 (QEMU virt default). + * System stack is 16 KB to accommodate test framework overhead. + **************************************************************************/ + +OUTPUT_ARCH( "riscv" ) +ENTRY( _start ) + +MEMORY +{ + RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 128M +} + +SECTIONS +{ + . = 0x80000000; + + .text : { + KEEP(*(.text.init)) + *(.text .text.*) + . = ALIGN(0x1000); + PROVIDE(etext = .); + } > RAM + + .rodata : { + . = ALIGN(16); + *(.srodata .srodata.*) + . = ALIGN(16); + *(.rodata .rodata.*) + } > RAM + + .data : { + . = ALIGN(16); + *(.sdata .sdata.*) + . = ALIGN(16); + *(.data .data.*) + } > RAM + + .bss : { + . = ALIGN(16); + _bss_start = .; + *(.sbss .sbss.*) + . = ALIGN(16); + *(.bss .bss.*) + *(COMMON) + _bss_end = .; + } > RAM + + .stack : { + . = ALIGN(4096); + _sysstack_start = .; + . += 0x4000; + _sysstack_end = .; + } > RAM + + PROVIDE(_end = .); + + ASSERT(. <= ORIGIN(RAM) + LENGTH(RAM), "Image exceeds available RAM") +} diff --git a/test/tx/cmake/riscv/bsp/plic.c b/test/tx/cmake/riscv/bsp/plic.c new file mode 100644 index 000000000..a2b44feca --- /dev/null +++ b/test/tx/cmake/riscv/bsp/plic.c @@ -0,0 +1,87 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "plic.h" +#include + +irq_callback callbacks[MAX_CALLBACK_NUM]; + +void plic_irq_enable(int irqno) +{ + uintptr_t hart = riscv_get_core(); + volatile uint32_t *reg = (volatile uint32_t *)(PLIC_MENABLE(hart) + (irqno / 32) * 4); + *reg = *reg | (1U << (irqno % 32)); +} + +void plic_irq_disable(int irqno) +{ + uintptr_t hart = riscv_get_core(); + volatile uint32_t *reg = (volatile uint32_t *)(PLIC_MENABLE(hart) + (irqno / 32) * 4); + *reg = *reg & ~(1U << (irqno % 32)); +} + +void plic_prio_set(int irqno, int prio) +{ + PLIC_SET_PRIO(irqno, prio); +} + +int plic_prio_get(int irqno) +{ + return (int)PLIC_GET_PRIO(irqno); +} + +int plic_register_callback(int irqno, irq_callback callback) +{ + if (!(irqno >= 0 && irqno < MAX_CALLBACK_NUM)) + return -1; + callbacks[irqno] = callback; + return 0; +} + +int plic_unregister_callback(int irqno) +{ + return plic_register_callback(irqno, NULL); +} + +int plic_init(void) +{ + for (int i = 0; i < MAX_CALLBACK_NUM; i++) + { + callbacks[i] = NULL; + } + return 0; +} + +int plic_claim(void) +{ + uintptr_t hart = riscv_get_core(); + return (int)(*(uint32_t *)PLIC_MCLAIM(hart)); +} + +void plic_complete(int irqno) +{ + uintptr_t hart = riscv_get_core(); + *(uint32_t *)(PLIC_MCOMPLETE(hart)) = (uint32_t)irqno; +} + +int plic_irq_intr(void) +{ + int ret = -1; + int irqno = plic_claim(); + if (irqno <= 0 || irqno >= MAX_CALLBACK_NUM) { + plic_complete(irqno); + return 0; // spurious or out-of-range, not an error + } + if (callbacks[irqno] != NULL) + ret = (callbacks[irqno])(irqno); + + plic_complete(irqno); + return ret; +} diff --git a/test/tx/cmake/riscv/bsp/plic.h b/test/tx/cmake/riscv/bsp/plic.h new file mode 100644 index 000000000..e2734ea63 --- /dev/null +++ b/test/tx/cmake/riscv/bsp/plic.h @@ -0,0 +1,46 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_PLIC_H +#define RISCV_PLIC_H + +#include "csr.h" +#include + +#define PLIC 0x0c000000L +#define PLIC_PRIORITY (PLIC + 0x0) +#define PLIC_PENDING (PLIC + 0x1000) +#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart) * 0x100) +#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart) * 0x100) +#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart) * 0x2000) +#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart) * 0x2000) +#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart) * 0x2000) +#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart) * 0x2000) +#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart) * 0x2000) +#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart) * 0x2000) + +#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno) * 4)) +#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno) * 4) = (prio)) + +#define MAX_CALLBACK_NUM 128 +typedef int (*irq_callback)(int irqno); + +void plic_irq_enable(int irqno); +void plic_irq_disable(int irqno); +int plic_prio_get(int irqno); +void plic_prio_set(int irqno, int prio); +int plic_register_callback(int irqno, irq_callback callback); +int plic_unregister_callback(int irqno); +int plic_init(void); +int plic_claim(void); +void plic_complete(int irqno); +int plic_irq_intr(void); + +#endif /* RISCV_PLIC_H */ diff --git a/test/tx/cmake/riscv/bsp/printf.c b/test/tx/cmake/riscv/bsp/printf.c new file mode 100644 index 000000000..4aa185cc3 --- /dev/null +++ b/test/tx/cmake/riscv/bsp/printf.c @@ -0,0 +1,168 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* Minimal printf/puts for RISC-V QEMU virt regression tests. + Avoids linking newlib's stdio which is compiled with mcmodel=medlow + and causes relocation overflow on RV64 (DRAM at 0x80000000). + Only the format specifiers used by the test suite are supported: + %s, %d, %u, %lu, %ld, %%, and plain strings. */ + +#include +#include + +extern int _write(int fd, const char *buf, int count); + +static void print_str(const char *s) +{ + const char *p = s; + while (*p) + p++; + _write(1, s, (int)(p - s)); +} + +static void print_unsigned(unsigned long val) +{ + char buf[21]; + int i = 0; + + if (val == 0) + { + _write(1, "0", 1); + return; + } + + while (val > 0) + { + buf[i++] = (char)('0' + (int)(val % 10u)); + val /= 10u; + } + + /* Reverse. */ + for (int j = i - 1; j >= 0; j--) + _write(1, &buf[j], 1); +} + +static void print_hex(unsigned long val) +{ + static const char hex[] = "0123456789abcdef"; + char buf[17]; + int i = 0; + + if (val == 0) + { + _write(1, "0", 1); + return; + } + + while (val > 0) + { + buf[i++] = hex[val & 0xfu]; + val >>= 4; + } + + for (int j = i - 1; j >= 0; j--) + _write(1, &buf[j], 1); +} + +static void print_signed(long val) +{ + if (val < 0) + { + _write(1, "-", 1); + print_unsigned((unsigned long)(-val)); + } + else + { + print_unsigned((unsigned long)val); + } +} + +int printf(const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + + const char *p = fmt; + const char *seg = p; + + while (*p) + { + if (*p == '%') + { + /* Flush preceding literal segment. */ + if (p > seg) + _write(1, seg, (int)(p - seg)); + + p++; + /* Check for 'l' length modifier. */ + int is_long = 0; + if (*p == 'l') + { + is_long = 1; + p++; + } + + switch (*p) + { + case 's': + print_str(va_arg(ap, const char *)); + break; + case 'd': + if (is_long) + print_signed(va_arg(ap, long)); + else + print_signed((long)va_arg(ap, int)); + break; + case 'u': + if (is_long) + print_unsigned(va_arg(ap, unsigned long)); + else + print_unsigned((unsigned long)va_arg(ap, unsigned int)); + break; + case 'x': + if (is_long) + print_hex(va_arg(ap, unsigned long)); + else + print_hex((unsigned long)va_arg(ap, unsigned int)); + break; + case '%': + _write(1, "%", 1); + break; + default: + /* Unknown specifier — print as-is. */ + _write(1, "%", 1); + if (is_long) + _write(1, "l", 1); + _write(1, p, 1); + break; + } + p++; + seg = p; + } + else + { + p++; + } + } + + /* Flush remaining literal segment. */ + if (p > seg) + _write(1, seg, (int)(p - seg)); + + va_end(ap); + return 0; +} + +int puts(const char *s) +{ + print_str(s); + _write(1, "\n", 1); + return 0; +} diff --git a/test/tx/cmake/riscv/bsp/syscalls.c b/test/tx/cmake/riscv/bsp/syscalls.c new file mode 100644 index 000000000..802fe8afa --- /dev/null +++ b/test/tx/cmake/riscv/bsp/syscalls.c @@ -0,0 +1,128 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* Newlib system call stubs for RISC-V QEMU virt regression tests. + Provides _write (UART output for printf), _exit (QEMU test finisher), + and other minimal stubs needed by newlib. */ + +#include +#include +#include + +#define UART0_THR (*(volatile unsigned char *)0x10000000L) +#define UART0_LSR (*(volatile unsigned char *)0x10000005L) +#define LSR_TX_IDLE (1 << 5) + +/* QEMU virt sifive_test device for clean exit. */ +#define VIRT_TEST (*(volatile uint32_t *)0x100000L) +#define VIRT_TEST_PASS 0x5555u +#define VIRT_TEST_FAIL 0x3333u + +/* Called by testcontrol.c when EXTERNAL_EXIT is defined. */ +__attribute__((noreturn)) void external_exit(unsigned int code) +{ + if (code == 0) + VIRT_TEST = VIRT_TEST_PASS; + else + VIRT_TEST = (code << 16) | VIRT_TEST_FAIL; + + /* Should not reach here, but halt if it does. */ + while (1) + ; +} + +int _write(int fd, const char *buf, int count) +{ + (void)fd; + for (int i = 0; i < count; i++) + { + while ((UART0_LSR & LSR_TX_IDLE) == 0) + ; + UART0_THR = (unsigned char)buf[i]; + } + return count; +} + +extern char _end[]; +static char *heap_ptr = 0; + +void *_sbrk(int incr) +{ + if (heap_ptr == 0) + heap_ptr = _end; + + char *prev = heap_ptr; + heap_ptr += incr; + return prev; +} + +int _close(int fd) +{ + (void)fd; + errno = EBADF; + return -1; +} + +int _fstat(int fd, struct stat *st) +{ + (void)fd; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int fd) +{ + (void)fd; + return 1; +} + +int _lseek(int fd, int offset, int whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return -1; +} + +int _read(int fd, char *buf, int count) +{ + (void)fd; + (void)buf; + (void)count; + return 0; +} + +__attribute__((noreturn)) void _exit(int code) +{ + external_exit((unsigned int)code); +} + +/* Override newlib's exit() to avoid pulling in __call_exitprocs and + __stdio_exit_handler (compiled with mcmodel=medlow). */ +__attribute__((noreturn)) void exit(int code) +{ + external_exit((unsigned int)code); +} + +/* Minimal rand/srand to avoid pulling newlib's version which uses + _impure_ptr (compiled with mcmodel=medlow, unreachable on RV64). */ +static unsigned long rand_seed = 1; + +int rand(void) +{ + rand_seed = rand_seed * 1103515245UL + 12345UL; + return (int)((rand_seed >> 16) & 0x7fff); +} + +void srand(unsigned int seed) +{ + rand_seed = seed; +} diff --git a/test/tx/cmake/riscv/bsp/trap.c b/test/tx/cmake/riscv/bsp/trap.c new file mode 100644 index 000000000..0ac7990ac --- /dev/null +++ b/test/tx/cmake/riscv/bsp/trap.c @@ -0,0 +1,84 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* Trap handler for RISC-V QEMU virt regression tests. + Calls test_interrupt_dispatch() BEFORE _tx_timer_interrupt() to match + the Linux port's behavior (generate_test_file.sh injection order). */ + +#include "csr.h" +#include +#include +#include "uart.h" +#include "hwtimer.h" +#include "plic.h" +#include +#include +#include + +/* Interrupt bit is the MSB of mcause */ +#define MCAUSE_INT_BIT ((uintptr_t)1 << (sizeof(uintptr_t) * 8 - 1)) + +#define OS_IS_INTERUPT(mcause) ((mcause) & MCAUSE_INT_BIT) +#define OS_IS_TICK_INT(mcause) ((mcause) == (MCAUSE_INT_BIT | 7u)) +#define OS_IS_SOFT_INT(mcause) ((mcause) == (MCAUSE_INT_BIT | 3u)) +#define OS_IS_EXT_INT(mcause) ((mcause) == (MCAUSE_INT_BIT | 11u)) + +extern void _tx_timer_interrupt(void); +extern void test_interrupt_dispatch(void) __attribute__((weak)); +extern void _exit(int code) __attribute__((noreturn)); + +void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) +{ + (void)mepc; + (void)mtval; + + if (OS_IS_INTERUPT(mcause)) + { + if (OS_IS_TICK_INT(mcause)) + { + hwtimer_handler(); + + /* Trace ISR enter event (matches Linux port behavior). */ + _tx_trace_isr_enter_insert(0); + + /* Call test ISR dispatch BEFORE timer interrupt (matches Linux). */ + if (test_interrupt_dispatch) + test_interrupt_dispatch(); + + _tx_timer_interrupt(); + + /* Trace ISR exit event. */ + _tx_trace_isr_exit_insert(0); + } + else if (OS_IS_EXT_INT(mcause)) + { + int ret = plic_irq_intr(); + if (ret) + { + uart_puts("[INTERRUPT]: handler irq error!"); + while (1) + ; + } + } + else + { + uart_puts("[INTERRUPT]: unhandled interrupt!"); + while (1) + ; + } + } + else + { + uart_puts("[EXCEPTION]: unhandled exception!"); + printf(" mcause=0x%lx mepc=0x%lx mtval=0x%lx\n", + (unsigned long)mcause, (unsigned long)mepc, (unsigned long)mtval); + _exit(1); + } +} diff --git a/test/tx/cmake/riscv/bsp/tx_initialize_low_level.S b/test/tx/cmake/riscv/bsp/tx_initialize_low_level.S new file mode 100644 index 000000000..8d474d66b --- /dev/null +++ b/test/tx/cmake/riscv/bsp/tx_initialize_low_level.S @@ -0,0 +1,100 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* Trap entry and low-level init for RISC-V QEMU virt regression tests. + Supports both RV32 and RV64 via __riscv_xlen conditionals. */ + +#include "csr.h" + +#if __riscv_xlen == 64 +#define STORE sd +#define LOAD ld +#define REGBYTES 8 +#else +#define STORE sw +#define LOAD lw +#define REGBYTES 4 +#endif + + .section .text + .align 4 + +/**************************************************************************/ +/* trap_entry — saves context, calls C trap_handler, restores context. */ +/**************************************************************************/ + .global trap_entry + .extern trap_handler + .extern _tx_thread_context_restore + +trap_entry: +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -(65 * REGBYTES) +#else + addi sp, sp, -(32 * REGBYTES) +#endif + + STORE x1, (28 * REGBYTES)(sp) + + call _tx_thread_context_save + + csrr a0, mcause + csrr a1, mepc + csrr a2, mtval + addi sp, sp, -REGBYTES + STORE ra, 0(sp) + call trap_handler + LOAD ra, 0(sp) + addi sp, sp, REGBYTES + + call _tx_thread_context_restore + +_trap_err: + wfi + j _trap_err + +/**************************************************************************/ +/* _tx_initialize_low_level — hardware init for QEMU virt. */ +/**************************************************************************/ + .section .text + .global _tx_initialize_low_level + .extern _end + .extern board_init + +_tx_initialize_low_level: + + la t0, _tx_thread_system_stack_ptr + STORE sp, 0(t0) + + la t0, _end + la t1, _tx_initialize_unused_memory + STORE t0, 0(t1) + + li t0, MSTATUS_MIE + csrrc zero, mstatus, t0 + li t0, (MSTATUS_MPP_M | MSTATUS_MPIE) + csrrs zero, mstatus, t0 + li t0, (MIE_MTIE | MIE_MSIE | MIE_MEIE) + csrrs zero, mie, t0 + +#ifdef __riscv_flen + li t0, MSTATUS_FS + csrrs zero, mstatus, t0 + fscsr x0 +#endif + + addi sp, sp, -REGBYTES + STORE ra, 0(sp) + call board_init + LOAD ra, 0(sp) + addi sp, sp, REGBYTES + + la t0, trap_entry + csrw mtvec, t0 + ret diff --git a/test/tx/cmake/riscv/bsp/uart.c b/test/tx/cmake/riscv/bsp/uart.c new file mode 100644 index 000000000..c1a6b64ba --- /dev/null +++ b/test/tx/cmake/riscv/bsp/uart.c @@ -0,0 +1,79 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "uart.h" +#include "csr.h" +#include "plic.h" +#include + +#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg))) + +#define RHR 0 +#define THR 0 +#define IER 1 +#define IER_RX_ENABLE (1<<0) +#define IER_TX_ENABLE (1<<1) +#define FCR 2 +#define FCR_FIFO_ENABLE (1<<0) +#define FCR_FIFO_CLEAR (3<<1) +#define LCR 3 +#define LCR_EIGHT_BITS (3<<0) +#define LCR_BAUD_LATCH (1<<7) +#define LSR 5 +#define LSR_RX_READY (1<<0) +#define LSR_TX_IDLE (1<<5) + +#define ReadReg(reg) (*(Reg(reg))) +#define WriteReg(reg, v) (*(Reg(reg)) = (v)) + +int uart_init(void) +{ + WriteReg(IER, 0x00); + WriteReg(LCR, LCR_BAUD_LATCH); + WriteReg(0, 0x03); + WriteReg(1, 0x00); + WriteReg(LCR, LCR_EIGHT_BITS); + WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR); + + plic_irq_enable(UART0_IRQ); + plic_prio_set(UART0_IRQ, 1); + + return 0; +} + +void uart_putc_nolock(int ch) +{ + while ((ReadReg(LSR) & LSR_TX_IDLE) == 0) + ; + WriteReg(THR, ch); +} + +int uart_putc(int ch) +{ + int intr_enable = riscv_mintr_get(); + riscv_mintr_off(); + uart_putc_nolock(ch); + riscv_mintr_restore(intr_enable); + return 1; +} + +int uart_puts(const char *str) +{ + int i; + int intr_enable = riscv_mintr_get(); + riscv_mintr_off(); + for (i = 0; str[i] != 0; i++) + { + uart_putc_nolock(str[i]); + } + uart_putc_nolock('\n'); + riscv_mintr_restore(intr_enable); + return i; +} diff --git a/test/tx/cmake/riscv/bsp/uart.h b/test/tx/cmake/riscv/bsp/uart.h new file mode 100644 index 000000000..765ec38f9 --- /dev/null +++ b/test/tx/cmake/riscv/bsp/uart.h @@ -0,0 +1,22 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_UART_H +#define RISCV_UART_H + +#define UART0 0x10000000L +#define UART0_IRQ 10 + +int uart_init(void); +int uart_putc(int ch); +void uart_putc_nolock(int ch); +int uart_puts(const char *str); + +#endif /* RISCV_UART_H */ diff --git a/test/tx/cmake/riscv/regression/CMakeLists.txt b/test/tx/cmake/riscv/regression/CMakeLists.txt new file mode 100644 index 000000000..5e381b894 --- /dev/null +++ b/test/tx/cmake/riscv/regression/CMakeLists.txt @@ -0,0 +1,165 @@ +cmake_minimum_required(VERSION 3.13 FATAL_ERROR) +cmake_policy(SET CMP0057 NEW) + +project(riscv_regression_test LANGUAGES C ASM) + +set(SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/../../../regression) +set(BSP_DIR ${CMAKE_CURRENT_LIST_DIR}/../bsp) + +# Determine QEMU arch from THREADX_ARCH +if(THREADX_ARCH STREQUAL "risc-v64") + set(QEMU_SYSTEM "qemu-system-riscv64") + set(XLEN_TAG "rv64") +else() + set(QEMU_SYSTEM "qemu-system-riscv32") + set(XLEN_TAG "rv32") +endif() + +set(regression_test_cases + ${SOURCE_DIR}/threadx_block_memory_basic_test.c + ${SOURCE_DIR}/threadx_block_memory_error_detection_test.c + ${SOURCE_DIR}/threadx_block_memory_information_test.c + ${SOURCE_DIR}/threadx_block_memory_prioritize_test.c + ${SOURCE_DIR}/threadx_block_memory_suspension_test.c + ${SOURCE_DIR}/threadx_block_memory_suspension_timeout_test.c + ${SOURCE_DIR}/threadx_block_memory_thread_terminate_test.c + ${SOURCE_DIR}/threadx_byte_memory_basic_test.c + ${SOURCE_DIR}/threadx_byte_memory_information_test.c + ${SOURCE_DIR}/threadx_byte_memory_prioritize_test.c + ${SOURCE_DIR}/threadx_byte_memory_suspension_test.c + ${SOURCE_DIR}/threadx_byte_memory_suspension_timeout_test.c + ${SOURCE_DIR}/threadx_byte_memory_thread_contention_test.c + ${SOURCE_DIR}/threadx_byte_memory_thread_terminate_test.c + ${SOURCE_DIR}/threadx_event_flag_basic_test.c + ${SOURCE_DIR}/threadx_event_flag_information_test.c + ${SOURCE_DIR}/threadx_event_flag_isr_set_clear_test.c + ${SOURCE_DIR}/threadx_event_flag_isr_wait_abort_test.c + ${SOURCE_DIR}/threadx_event_flag_single_thread_terminate_test.c + ${SOURCE_DIR}/threadx_event_flag_suspension_consume_test.c + ${SOURCE_DIR}/threadx_event_flag_suspension_different_bits_consume_test.c + ${SOURCE_DIR}/threadx_event_flag_suspension_different_bits_test.c + ${SOURCE_DIR}/threadx_event_flag_suspension_test.c + ${SOURCE_DIR}/threadx_event_flag_suspension_timeout_test.c + ${SOURCE_DIR}/threadx_event_flag_thread_terminate_test.c + ${SOURCE_DIR}/threadx_interrupt_control_test.c + ${SOURCE_DIR}/threadx_mutex_basic_test.c + ${SOURCE_DIR}/threadx_mutex_delete_test.c + ${SOURCE_DIR}/threadx_mutex_information_test.c + ${SOURCE_DIR}/threadx_mutex_nested_priority_inheritance_test.c + ${SOURCE_DIR}/threadx_mutex_no_preemption_test.c + ${SOURCE_DIR}/threadx_mutex_preemption_test.c + ${SOURCE_DIR}/threadx_mutex_priority_inheritance_test.c + ${SOURCE_DIR}/threadx_mutex_proritize_test.c + ${SOURCE_DIR}/threadx_mutex_suspension_timeout_test.c + ${SOURCE_DIR}/threadx_mutex_thread_terminate_test.c + ${SOURCE_DIR}/threadx_queue_basic_eight_word_test.c + ${SOURCE_DIR}/threadx_queue_basic_four_word_test.c + ${SOURCE_DIR}/threadx_queue_basic_one_word_test.c + ${SOURCE_DIR}/threadx_queue_basic_sixteen_word_test.c + ${SOURCE_DIR}/threadx_queue_basic_two_word_test.c + ${SOURCE_DIR}/threadx_queue_basic_max_message_size_test.c + ${SOURCE_DIR}/threadx_queue_empty_suspension_test.c + ${SOURCE_DIR}/threadx_queue_flush_no_suspension_test.c + ${SOURCE_DIR}/threadx_queue_flush_test.c + ${SOURCE_DIR}/threadx_queue_front_send_test.c + ${SOURCE_DIR}/threadx_queue_full_suspension_test.c + ${SOURCE_DIR}/threadx_queue_information_test.c + ${SOURCE_DIR}/threadx_queue_prioritize.c + ${SOURCE_DIR}/threadx_queue_suspension_timeout_test.c + ${SOURCE_DIR}/threadx_queue_thread_terminate_test.c + ${SOURCE_DIR}/threadx_semaphore_basic_test.c + ${SOURCE_DIR}/threadx_semaphore_ceiling_put_test.c + ${SOURCE_DIR}/threadx_semaphore_delete_test.c + ${SOURCE_DIR}/threadx_semaphore_information_test.c + ${SOURCE_DIR}/threadx_semaphore_non_preemption_test.c + ${SOURCE_DIR}/threadx_semaphore_preemption_test.c + ${SOURCE_DIR}/threadx_semaphore_prioritize.c + ${SOURCE_DIR}/threadx_semaphore_thread_terminate_test.c + ${SOURCE_DIR}/threadx_semaphore_timeout_test.c + ${SOURCE_DIR}/threadx_thread_basic_execution_test.c + ${SOURCE_DIR}/threadx_thread_basic_time_slice_test.c + ${SOURCE_DIR}/threadx_thread_completed_test.c + ${SOURCE_DIR}/threadx_thread_create_preemption_threshold_test.c + ${SOURCE_DIR}/threadx_thread_delayed_suspension_test.c + ${SOURCE_DIR}/threadx_thread_information_test.c + ${SOURCE_DIR}/threadx_thread_multi_level_preemption_threshold_test.c + ${SOURCE_DIR}/threadx_thread_multiple_non_current_test.c + ${SOURCE_DIR}/threadx_thread_multiple_sleep_test.c + ${SOURCE_DIR}/threadx_thread_multiple_suspension_test.c + ${SOURCE_DIR}/threadx_thread_multiple_time_slice_test.c + ${SOURCE_DIR}/threadx_thread_preemptable_suspension_test.c + ${SOURCE_DIR}/threadx_thread_preemption_change_test.c + ${SOURCE_DIR}/threadx_thread_priority_change.c + ${SOURCE_DIR}/threadx_thread_relinquish_test.c + ${SOURCE_DIR}/threadx_thread_reset_test.c + ${SOURCE_DIR}/threadx_thread_simple_sleep_non_clear_test.c + ${SOURCE_DIR}/threadx_thread_simple_sleep_test.c + ${SOURCE_DIR}/threadx_thread_simple_suspend_test.c + ${SOURCE_DIR}/threadx_thread_sleep_for_100ticks_test.c + ${SOURCE_DIR}/threadx_thread_sleep_terminate_test.c + ${SOURCE_DIR}/threadx_thread_stack_checking_test.c + ${SOURCE_DIR}/threadx_thread_terminate_delete_test.c + ${SOURCE_DIR}/threadx_thread_time_slice_change_test.c + ${SOURCE_DIR}/threadx_thread_wait_abort_and_isr_test.c + ${SOURCE_DIR}/threadx_thread_wait_abort_test.c + ${SOURCE_DIR}/threadx_time_get_set_test.c + ${SOURCE_DIR}/threadx_timer_activate_deactivate_test.c + ${SOURCE_DIR}/threadx_timer_deactivate_accuracy_test.c + ${SOURCE_DIR}/threadx_timer_information_test.c + ${SOURCE_DIR}/threadx_timer_large_timer_accuracy_test.c + ${SOURCE_DIR}/threadx_timer_multiple_accuracy_test.c + ${SOURCE_DIR}/threadx_timer_multiple_test.c + ${SOURCE_DIR}/threadx_timer_simple_test.c + # threadx_trace_basic_test.c excluded: references tx_saved_posture + # (the Linux port's interrupt save variable) which is named + # interrupt_save on RISC-V. +) + +# Tests that provide their own main() and must NOT link with testcontrol. +set(standalone_test_cases + ${SOURCE_DIR}/threadx_initialize_kernel_setup_test.c +) + +# Build testcontrol.c as a static library (no patched tx_initialize_low_level +# needed — the BSP provides it directly with test_interrupt_dispatch hook). +add_library(riscv_test_utility ${SOURCE_DIR}/testcontrol.c) +target_link_libraries(riscv_test_utility PUBLIC riscv_bsp azrtos::threadx) +target_compile_definitions(riscv_test_utility PUBLIC + CTEST BATCH_TEST EXTERNAL_EXIT TEST_STACK_SIZE_PRINTF=4096) +# Bare-metal newlib needs explicit stdlib.h for rand() used in some tests. +target_compile_options(riscv_test_utility PUBLIC -include stdlib.h) + +# Helper function to register a test executable with QEMU + CTest. +function(register_riscv_test test_name) + target_link_options(${test_name} PRIVATE + -T ${BSP_DIR}/link.lds -nostartfiles + -Wl,--gc-sections) + add_test( + NAME ${CMAKE_BUILD_TYPE}::${XLEN_TAG}::${test_name} + COMMAND ${QEMU_SYSTEM} -nographic -smp 1 -bios none -m 128M + -machine virt -kernel $ + ) + set_tests_properties(${CMAKE_BUILD_TYPE}::${XLEN_TAG}::${test_name} + PROPERTIES TIMEOUT 120) +endfunction() + +# Regular tests (linked with testcontrol). +foreach(test_case ${regression_test_cases}) + get_filename_component(test_name ${test_case} NAME_WE) + add_executable(${test_name} ${test_case}) + target_link_libraries(${test_name} PRIVATE + -Wl,--whole-archive riscv_bsp -Wl,--no-whole-archive + riscv_test_utility) + register_riscv_test(${test_name}) +endforeach() + +# Standalone tests (provide their own main, no testcontrol). +foreach(test_case ${standalone_test_cases}) + get_filename_component(test_name ${test_case} NAME_WE) + add_executable(${test_name} ${test_case}) + target_link_libraries(${test_name} PRIVATE + -Wl,--whole-archive riscv_bsp -Wl,--no-whole-archive + azrtos::threadx) + target_compile_options(${test_name} PRIVATE -include stdlib.h) + register_riscv_test(${test_name}) +endforeach() diff --git a/test/tx/cmake/riscv/run.sh b/test/tx/cmake/riscv/run.sh new file mode 100755 index 000000000..890efa452 --- /dev/null +++ b/test/tx/cmake/riscv/run.sh @@ -0,0 +1,151 @@ +#!/bin/bash + +set -e + +# RISC-V regression test build/test runner. +# Usage: run.sh [all| ...] +# arch: riscv32 or riscv64 + +function help() { + echo "Usage: $0 [all| ...]" + echo "" + echo " arch: riscv32 | riscv64" + echo " command: build | test" + echo "" + echo "Available build configurations:" + for build in ${build_configurations[*]}; do + echo " $build" + done + exit 1 +} + +function validate() { + for build in ${build_configurations[*]}; do + if [ "$1" == "$build" ]; then + return + fi + done + help +} + +function generate() { + local arch=$1 + local build=$2 + local toolchain_file + local build_dir + + if [ "$arch" == "riscv32" ]; then + toolchain_file="${REPO_ROOT}/cmake/riscv32_gnu.cmake" + else + toolchain_file="${REPO_ROOT}/cmake/riscv64_gnu.cmake" + fi + + build_dir="build/${arch}_${build}" + cmake -B"$build_dir" -GNinja \ + -DCMAKE_TOOLCHAIN_FILE="$toolchain_file" \ + -DCMAKE_BUILD_TYPE="$build" \ + . +} + +function build() { + local arch=$1 + local build=$2 + cmake --build "build/${arch}_${build}" +} + +function run_test() { + local arch=$1 + local build=$2 + local parallel_jobs=$3 + + pushd "build/${arch}_${build}" + [ -z "${CTEST_PARALLEL_LEVEL}" ] && parallel="-j${parallel_jobs}" + if [ -z "${CTEST_REPEAT_FAIL}" ]; then + repeat_fail=2 + else + repeat_fail=${CTEST_REPEAT_FAIL} + fi + ctest $parallel --timeout 1000 \ + -O "${arch}_${build}.txt" \ + -T test --no-compress-output \ + --test-output-size-passed 4194304 \ + --test-output-size-failed 4194304 \ + --output-on-failure \ + --repeat until-pass:${repeat_fail} \ + --output-junit "${arch}_${build}.xml" + popd +} + +# Determine repo root and script directory +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +REPO_ROOT="$(cd "${SCRIPT_DIR}/../../../.." && pwd)" +cd "$SCRIPT_DIR" + +# Parse build configurations from CMakeLists.txt +result=$(sed -n "/(BUILD_CONFIGURATIONS/,/)/p" CMakeLists.txt | sed ':label;N;s/\n/ /;b label' | grep -Pzo "[a-zA-Z0-9_]*build[a-zA-Z0-9_]*\s*" | tr -d '\0') +IFS=' ' +read -ra build_configurations <<< "$result" + +if [ $# -lt 2 ]; then + help +fi + +arch=$1 +shift + +if [ "$arch" != "riscv32" ] && [ "$arch" != "riscv64" ]; then + echo "Error: arch must be 'riscv32' or 'riscv64'" + help +fi + +command=$1 +shift + +if [ "$#" == "0" ]; then + builds=${build_configurations[0]} +elif [ "$*" == "all" ]; then + builds=${build_configurations[@]} +else + for item in $*; do + validate "$item" + done + builds=$* +fi + +if [ "$command" == "build" ]; then + for item in $builds; do + generate "$arch" "$item" + echo "" + done + + for item in $builds; do + echo "Building ${arch} ${item}" + build "$arch" "$item" + echo "" + done +elif [ "$command" == "test" ]; then + cores=$(nproc) + if [ -z "${CTEST_PARALLEL_LEVEL}" ]; then + build_counts=$(echo $builds | wc -w) + parallel_jobs=$(($cores / $build_counts)) + parallel_jobs=$(($parallel_jobs + 2)) + pids="" + for item in $builds; do + echo "Testing ${arch} ${item}" + run_test "$arch" "$item" "$parallel_jobs" & + pids+=" $!" + done + exit_code=0 + for p in $pids; do + wait $p || exit_code=$? + done + exit $exit_code + else + for item in $builds; do + echo "Testing ${arch} ${item}" + run_test "$arch" "$item" "$parallel_jobs" + done + fi +else + help +fi diff --git a/test/tx/regression/threadx_block_memory_basic_test.c b/test/tx/regression/threadx_block_memory_basic_test.c index 12e301d1a..b2dccbff6 100644 --- a/test/tx/regression/threadx_block_memory_basic_test.c +++ b/test/tx/regression/threadx_block_memory_basic_test.c @@ -217,8 +217,8 @@ CHAR *pointer; } /* Create block pools 0 and 1. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); + pointer = pointer + 340; /* Check status. */ if (status != TX_SUCCESS) @@ -228,8 +228,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, 340); + pointer = pointer + 340; /* Check status. */ if (status != TX_SUCCESS) diff --git a/test/tx/regression/threadx_block_memory_error_detection_test.c b/test/tx/regression/threadx_block_memory_error_detection_test.c index 7b7f2f610..e06c4d174 100644 --- a/test/tx/regression/threadx_block_memory_error_detection_test.c +++ b/test/tx/regression/threadx_block_memory_error_detection_test.c @@ -49,8 +49,8 @@ INT status; pointer = pointer + TEST_STACK_SIZE_PRINTF; /* Create block pool 0. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); + pointer = pointer + 340; #ifndef TX_DISABLE_ERROR_CHECKING /* skip this test and pretend it passed */ @@ -128,8 +128,8 @@ INT i; #ifndef TX_DISABLE_ERROR_CHECKING /* skip this test and pretend it passed */ - status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, 340); + pointer = pointer + 340; /* Attempt to create a pool with an invalid size. */ status = _txe_block_pool_create(&pool_2, "pool 2", 100, pointer, 320, 777777); diff --git a/test/tx/regression/threadx_block_memory_suspension_test.c b/test/tx/regression/threadx_block_memory_suspension_test.c index da14f454e..3b49f5d9b 100644 --- a/test/tx/regression/threadx_block_memory_suspension_test.c +++ b/test/tx/regression/threadx_block_memory_suspension_test.c @@ -83,8 +83,8 @@ CHAR *pointer; } /* Create block pool. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); + pointer = pointer + 340; /* Check status. */ if (status != TX_SUCCESS) diff --git a/test/tx/regression/threadx_block_memory_suspension_timeout_test.c b/test/tx/regression/threadx_block_memory_suspension_timeout_test.c index dc460662d..a2be3c6c9 100644 --- a/test/tx/regression/threadx_block_memory_suspension_timeout_test.c +++ b/test/tx/regression/threadx_block_memory_suspension_timeout_test.c @@ -84,8 +84,8 @@ CHAR *pointer; } /* Create block pool. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); + pointer = pointer + 340; /* Check status. */ if (status != TX_SUCCESS) diff --git a/test/tx/regression/threadx_block_memory_thread_terminate_test.c b/test/tx/regression/threadx_block_memory_thread_terminate_test.c index 6064891df..c568d9a20 100644 --- a/test/tx/regression/threadx_block_memory_thread_terminate_test.c +++ b/test/tx/regression/threadx_block_memory_thread_terminate_test.c @@ -69,8 +69,8 @@ CHAR *pointer; } /* Create block pool. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); + pointer = pointer + 340; /* Check status. */ if (status != TX_SUCCESS) diff --git a/test/tx/regression/threadx_byte_memory_basic_test.c b/test/tx/regression/threadx_byte_memory_basic_test.c index 36f413317..d153ccafa 100644 --- a/test/tx/regression/threadx_byte_memory_basic_test.c +++ b/test/tx/regression/threadx_byte_memory_basic_test.c @@ -4,6 +4,15 @@ #include #include "tx_api.h" +/* Per-allocation overhead in byte pools: next pointer + ALIGN_TYPE alignment marker. */ +#define BYTE_POOL_OVERHEAD (sizeof(UCHAR *) + sizeof(ALIGN_TYPE)) + +/* Pool size for pool_0: exactly fits 3 allocations of 24 bytes with no room for a 4th. */ +#define POOL_0_SIZE (ULONG)(3u * (24u + BYTE_POOL_OVERHEAD) + BYTE_POOL_OVERHEAD) + +/* Pool size for pool_4: must accommodate 3 allocations of 84 bytes (tightest pattern). */ +#define POOL_4_SIZE (ULONG)(3u * (84u + BYTE_POOL_OVERHEAD) + BYTE_POOL_OVERHEAD + 16u) + typedef struct BYTE_MEMORY_TEST_STRUCT { ULONG first; @@ -256,8 +265,8 @@ CHAR *pointer; } /* Create byte pools 0 and 1. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, POOL_0_SIZE); + pointer = pointer + POOL_0_SIZE; /* Check status. */ if (status != TX_SUCCESS) @@ -279,9 +288,9 @@ CHAR *pointer; } /* Test for search pointer issue on wrapped seach with prior block to search pointer merged. */ - status = tx_byte_pool_create(&pool_4, "pool 4", pointer, 300); + status = tx_byte_pool_create(&pool_4, "pool 4", pointer, POOL_4_SIZE); pool_4_memory = pointer; - pointer = pointer + 300; + pointer = pointer + POOL_4_SIZE; /* Check status. */ if (status != TX_SUCCESS) @@ -865,7 +874,7 @@ UCHAR *save_search; } /* Move the search pointer to the third block to exercise that code in the byte search algorithm. */ - pool_0.tx_byte_pool_search = (UCHAR *) pointer_3-8; + pool_0.tx_byte_pool_search = (UCHAR *) pointer_3 - BYTE_POOL_OVERHEAD; /* Now allocate the block again. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_2, 24, TX_NO_WAIT); @@ -885,7 +894,7 @@ UCHAR *save_search; status += tx_byte_release(pointer_1); /* Move the search pointer to the third block to exercise that code in the byte search algorithm. */ - pool_0.tx_byte_pool_search = (UCHAR *) pointer_3-8; + pool_0.tx_byte_pool_search = (UCHAR *) pointer_3 - BYTE_POOL_OVERHEAD; /* Allocate a large block to force the search pointer update. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_3, 88, TX_NO_WAIT); @@ -961,7 +970,7 @@ UCHAR *save_search; } /* Create pool 4. */ - status = tx_byte_pool_create(&pool_4, "pool 4", pool_4_memory, 300); + status = tx_byte_pool_create(&pool_4, "pool 4", pool_4_memory, POOL_4_SIZE); /* Check status. */ if (status != TX_SUCCESS) diff --git a/test/tx/regression/threadx_event_flag_suspension_timeout_test.c b/test/tx/regression/threadx_event_flag_suspension_timeout_test.c index 149cb58fa..f4ee39955 100644 --- a/test/tx/regression/threadx_event_flag_suspension_timeout_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_timeout_test.c @@ -178,17 +178,12 @@ UINT status; /* Sleep for 63 ticks. */ tx_thread_sleep(63); - /* Check the run counters. */ - if (((thread_1_counter != 32) -#ifdef __linux__ - && (thread_1_counter != 33) /* Depending on the starting time, thread 1 can run either 32 or 33 rounds. */ -#endif - ) || - ((thread_2_counter != 13) -#ifdef __linux__ - && (thread_2_counter != 14) /* When CPU starves, the thread 2 can run 14 ronuds. */ -#endif - )) + /* Check the run counters. Depending on the starting time relative to + the tick boundary, thread 1 can run either 32 or 33 rounds and + thread 2 can run 13 or 14 rounds. This variance applies to any + platform with non-deterministic tick alignment (Linux, QEMU, etc.). */ + if (((thread_1_counter != 32) && (thread_1_counter != 33)) || + ((thread_2_counter != 13) && (thread_2_counter != 14))) { /* Event flag error. */ From 9ccdd5d82248736274a4cc5cad5e13d2ffc50de7 Mon Sep 17 00:00:00 2001 From: Ian Thompson <101299961+ianstcdns@users.noreply.github.com> Date: Tue, 19 May 2026 08:11:37 -0700 Subject: [PATCH 16/29] Updated Xtensa support (#525) * Add LX8 support for > 32 interrupts Also fix inconsistent SWPRI define in interrupt handler * ThreadX: Fix context switch logic - Disable interrupts prior to allocating a large exception frame; only reenable them after deallocating the extra memory. - Any user tasks with stacks based on TX_MINIMUM_STACK do not have sufficient space for both a context switch frame and an ISR frame; ill-timed interrupts were causing stack overruns. * ThreadX: Interrupt fixes for TX_ENABLE_EXECUTION_CHANGE_NOTIFY - Must reload register trashed by notify hook function call - Must ensure PS.WOE is set before using call8 - Remove unused XT_USE_INT_WRAPPER define and associated changes, which had a bug in XEA2 usage - Fix another case where enabling the thread notify hooks for call0 ABI corrupted a register * ThreadX: Support for __DYNAMIC_REENT__ - ThreadX change to handle dynamic reent for both newlib and xclib - Adapt ThreadX xclib interface code to handle dynamic reent pointers * ThreadX: Xtensa execution profiling support - Update upstream execution profiling for Xtensa port * ThreadX: Update xtensa port readme * ThreadX: Add Xtensa example to EPK - tx_execution_profile.h now defines an Xtensa example in addition to the existing Cortex example * ThreadX: Add xtensa.cmake * ThreadX: Update XSHAL_CLIB ifdefs in __getreent() - Prevent a fall-through with no return value when neither xclib nor newlib are used. --- cmake/xtensa.cmake | 37 ++ ports/xtensa/xcc/inc/tx_port.h | 5 +- ports/xtensa/xcc/inc/xtensa_context.h | 20 +- ports/xtensa/xcc/inc/xtensa_rtos.h | 4 + ports/xtensa/xcc/inc/xtensa_timer.h | 14 +- ports/xtensa/xcc/readme_threadx.txt | 182 +++------- ports/xtensa/xcc/src/tx_clib_lock.c | 40 +++ .../xtensa/xcc/src/tx_initialize_low_level.c | 2 + ports/xtensa/xcc/src/tx_thread_schedule.S | 27 +- .../xtensa/xcc/src/tx_thread_system_return.S | 43 ++- ports/xtensa/xcc/src/xtensa_context.S | 4 +- ports/xtensa/xcc/src/xtensa_intr.c | 12 +- ports/xtensa/xcc/src/xtensa_intr_asm.S | 5 +- ports/xtensa/xcc/src/xtensa_intr_wrapper.c | 2 +- ports/xtensa/xcc/src/xtensa_vectors.S | 321 +++++++++++++++--- .../tx_execution_profile.h | 18 + 16 files changed, 502 insertions(+), 234 deletions(-) create mode 100644 cmake/xtensa.cmake diff --git a/cmake/xtensa.cmake b/cmake/xtensa.cmake new file mode 100644 index 000000000..2f5fa6939 --- /dev/null +++ b/cmake/xtensa.cmake @@ -0,0 +1,37 @@ +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR xtensa) + +set(CMAKE_C_COMPILER xt-clang) +set(CMAKE_CXX_COMPILER xt-clang++) +set(AS xt-clang) +set(AR xt-ar) +set(OBJCOPY xt-objcopy) +set(OBJDUMP xt-objdump) +set(SIZE xt-size) + +set(THREADX_ARCH "xtensa") +set(THREADX_TOOLCHAIN "xcc") + +if (DEFINED ENV{XCC_OPTS}) + set(XCC_OPTS $ENV{XCC_OPTS}) +else() + set(XCC_OPTS "") +endif() + +set(XCC_FLAGS "${XCC_OPTS} -mlongcalls -mno-l32r-flix -mno-coproc -Wall -Wextra -Werror") + +set(CMAKE_C_FLAGS "${XCC_FLAGS} -Os -g" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${XCC_FLAGS} -Os -g -fno-rtti -fno-exceptions" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${XCC_FLAGS} -Os -g" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${XCC_FLAGS} ${LD_FLAGS} -Wl,--gc-sections" CACHE INTERNAL "exe link flags") + +SET(CMAKE_C_FLAGS_DEBUG "-O0 -g" CACHE INTERNAL "c debug compiler flags") +SET(CMAKE_CXX_FLAGS_DEBUG "-O0 -g" CACHE INTERNAL "cxx debug compiler flags") +SET(CMAKE_ASM_FLAGS_DEBUG "-O0 -g" CACHE INTERNAL "asm debug compiler flags") + +SET(CMAKE_C_FLAGS_RELEASE "-Os -g" CACHE INTERNAL "c release compiler flags") +SET(CMAKE_CXX_FLAGS_RELEASE "-Os -g" CACHE INTERNAL "cxx release compiler flags") +SET(CMAKE_ASM_FLAGS_RELEASE "-Os -g" CACHE INTERNAL "asm release compiler flags") + +# this makes the test compiles use static library option so that we don't need to pre-set linker flags and scripts +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) diff --git a/ports/xtensa/xcc/inc/tx_port.h b/ports/xtensa/xcc/inc/tx_port.h index a8897815d..d6503b4fe 100644 --- a/ports/xtensa/xcc/inc/tx_port.h +++ b/ports/xtensa/xcc/inc/tx_port.h @@ -340,7 +340,10 @@ typedef unsigned short USHORT; #define TX_THREAD_EXTENSION_2 /* Execution profile related */ -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 \ + unsigned long long tx_thread_execution_time_total; \ + unsigned long tx_thread_execution_time_last_start; + /* Define the port extensions of the remaining ThreadX objects. */ diff --git a/ports/xtensa/xcc/inc/xtensa_context.h b/ports/xtensa/xcc/inc/xtensa_context.h index 11174fff5..2d06948b9 100644 --- a/ports/xtensa/xcc/inc/xtensa_context.h +++ b/ports/xtensa/xcc/inc/xtensa_context.h @@ -373,19 +373,8 @@ XSTRUCT_END(XtExcFrame) #endif #endif - -/* -------------------------------------------------------------------------------- - This flag is meant for internal use. Have all interrupts be dispatched via a - common wrapper, which takes care of doing some OS-specific stuff common to - all interrupt handlers. Said stuff cannot safely be handled in the RTOS_ENTER - and RTOS_EXIT macros. -------------------------------------------------------------------------------- -*/ -#if (defined TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || (defined XT_INTEXC_HOOKS) -#define XT_USE_INT_WRAPPER 1 -#else -#define XT_USE_INT_WRAPPER 0 +#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS > 32) && (defined XT_USE_SWPRI) +#error "Software prioritization of interrupts (XT_USE_SWPRI) not supported for XEA2 with > 32 interrupts." #endif #if XCHAL_HAVE_XEA3 @@ -500,12 +489,15 @@ XSTRUCT_END(XtExcFrame) #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY // Call the thread entry function to indicate the thread is executing. - // SP should be pointing to a safe region at this point. + // SP should be pointing to a safe region at this point. Note that a9 + // may be trashed by this call, must be reloaded. #ifdef __XTENSA_CALL0_ABI__ call0 _tx_execution_thread_enter #else call8 _tx_execution_thread_enter #endif + movi a9, _tx_thread_current_ptr // a9 <- &_tx_thread_current_ptr + l32i a9, a9, 0 // a9 <- _tx_thread_current_ptr #endif l32i a2, a9, tx_thread_solicited // a2 = solicited flag diff --git a/ports/xtensa/xcc/inc/xtensa_rtos.h b/ports/xtensa/xcc/inc/xtensa_rtos.h index d8db73bcf..ef62035ee 100644 --- a/ports/xtensa/xcc/inc/xtensa_rtos.h +++ b/ports/xtensa/xcc/inc/xtensa_rtos.h @@ -181,7 +181,11 @@ To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. #define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI) #ifndef __ASSEMBLER__ +#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS > 32) +typedef uint32_t (*XT_INTEXC_HOOK)(uint32_t cause, uint32_t block); +#else typedef uint32_t (*XT_INTEXC_HOOK)(uint32_t cause); +#endif extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM]; #endif diff --git a/ports/xtensa/xcc/inc/xtensa_timer.h b/ports/xtensa/xcc/inc/xtensa_timer.h index 957a42ed7..fbbe48718 100644 --- a/ports/xtensa/xcc/inc/xtensa_timer.h +++ b/ports/xtensa/xcc/inc/xtensa_timer.h @@ -108,7 +108,19 @@ Otherwise select the first low or medium priority interrupt timer available. #define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) #if XCHAL_HAVE_XEA2 -#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) +/* + * Xtensa LX8 supports up to 128 interrupts whereas LX7 supports up to 32. + * + * Redefine the legacy XT_TIMER_INTEN (which limited the interrupt number to + * be in the lower 32 or lower 64 bits depending on data type) as two defines + * describing the INTEN bit within a 32-bit component and a 4-block component, + * where each block contains a group of 32 interrupt bits. + * + * Name changes are intentional such that any dependencies are caught at + * compile-time and are found regardless of timer configuration. + */ +#define XT_TIMER_INTEN_BIT (1 << (XT_TIMER_INTNUM & 31U)) +#define XT_TIMER_INTEN_BLK (XT_TIMER_INTNUM >> 5) #endif #if XT_TIMER_INDEX == 0 diff --git a/ports/xtensa/xcc/readme_threadx.txt b/ports/xtensa/xcc/readme_threadx.txt index 3ad4aec2e..3f45c95f1 100644 --- a/ports/xtensa/xcc/readme_threadx.txt +++ b/ports/xtensa/xcc/readme_threadx.txt @@ -22,7 +22,6 @@ processor configuration options: - Timer interrupt option with at least one interruptible timer for ThreadX. - Interrupt option (implied by the timer interrupt option). - Xtensa Exception Architecture 2 (XEA2) or Exception Architecture 3 (XEA3). - Please note that XEA1 is NOT supported. Minimal support for certain evaluation boards is provided via a board independent "XTBSP" API implemented by a board specific library. This @@ -35,143 +34,66 @@ this board support (a "raw" platform), but you will have to provide the clock frequency and drivers for any on-board devices you want to use. -2. Building the ThreadX run-time Library +2. Building the ThreadX Library and the Xtensa Example By default, you will build for the Xtensa instruction set simulator. If you have a supported emulation board, you can build to run on that. You -can also build to run on a raw Xtensa core with no "board support", a -good starting point for supporting your own target platform. Cadence Design Systems -recommends doing functional development on the simulator because it -is easier to debug with, then move to a board if/when you need to test -hardware drivers or real-time performance. +will have to provide the XTBSP functions for any other board you want to +run on. We recommend you start by running on the simulator, then moving +to your hardware target or emulation platform. -ThreadX/Xtensa comes with a Makefile as well as DOS .bat file, taking -advantage of xt-make, a version of GNU make that comes with Xtensa Tools -(you can just as well use generic GNU make if you have it installed). -The Makefile works on any host platform and provides for incremental builds. -The .bat file works on DOS/Windows only and always cleans before building. -The build for each target platform is placed in a sub-directory so several -platform builds can coexist even with incremental rebuilds. +ThreadX/Xtensa is built using the ThreadX Cmake infrastructure. See the +standard ThreadX documentation for details of the build process. In the +cmake/ directory there is a file named xtensa.cmake which defines the +Cmake configuration for the Xtensa target. Both Cmake and the Ninja tool +need to be installed to build ThreadX. -First, make sure you have installed Xtensa Tools and your processor -configuration, and be sure that Xtensa Tools are in your search path. +You will also need to ensure that the Xtensa SDK tools have been installed +and are on the path, and XTENSA_SYSTEM and XTENSA_CORE are set appropriately +in the environment. Refer to the SDK documentation for details. -If you wish to build for an evaluation board that is supported by an -external package, be sure the appropriate package is installed. See the -introduction (section 0) to determine if you need an external package. -If you are using an external board package, set the environment variable -XTENSA_BOARDS to the absolute path of the root of the installed support -package (or you can pass this to xt-make commands on the command line). -eg. XTENSA_BOARDS = C:\usr\xtensa\RB-2007.1-xtav60 for Avnet LX60 board. -You do not need to set XTENSA_BOARDS if using a Cadence Design Systems supported -board with Xtensa Tools RB-2007.2 and up (support is bundled with the tools). +The following commands will build the ThreadX library (some changes may be +required based on your setup) - -Next, change directories to the ThreadX installation directory, as follows: + cmake -S $(TX_SRCDIR) -B $(TX_BLDDIR) -DCMAKE_TOOLCHAIN_FILE=$(TX_SRCDIR)/cmake/xtensa.cmake -GNinja $(TX_SRCDIR) + cmake --build $(TX_BLDDIR) -> cd c:\threadx\xtensa\gnu +where TX_SRCDIR is the root of the ThreadX source tree, and TX_BLDDIR is +the location where you want the build output to go. -Now build the ThreadX library (tx.a) by executing the build_threadx.bat -batch file (or using the Makefile directly) while inside the threadx -directory, as follows: +Once the library is built, the Xtensa example can be built by going into +the directory ports/xtensa/xcc/example_build and running this command - -> build_threadx.bat +xt-clang -mlongcalls -Os -g -I../../../../common/inc -I../../../../common_smp/inc + -I../../../../ports/xtensa/xcc/inc -o demo_threadx.exe demo_threadx.c + ../../../../build/libthreadx.a -lxtutil -which always builds for the simulator (but you can edit it), or - -> xt-make - -which by default builds for the simulator (PLATFORM=sim), or either of - -> xt-make PLATFORM=board BOARD= -or -> xt-make BOARD= - -which builds for a specified supported board (note PLATFORM=board is -default when BOARD is defined). eg. BOARD=xtav60 for the Avnet LX60 -(XT-AV60) board. - -> xt-make PLATFORM=raw - -which builds for a raw Xtensa core with no "board support". - -> xt-make PLATFORM=gdbio - -Provides some very slow I/O support through the xt-gdb debugger. -For GDBIO to work, xt-gdb must remain connected to the target. - -If you are building for an Xtensa processor configuration that is not the -default you selected when you installed Xtensa Tools, you need to define the -environment variable XTENSA_CORE. If your configuration is not in the -default registry you selected when you installed Xtensa Tools, you also -need to define the environment variable XTENSA_SYSTEM. See tools manuals. -You can avoid defining these in your environment if you pass the variables -you need to redefine into xt-make as follows: - -> xt-make XTENSA_CORE= XTENSA_SYSTEM= ... - -There are more details about build options in the comment in the Makefile. - -At this point, all the ThreadX objects are located in a library file: tx.a . -This file must be linked with your application in order to use ThreadX. -This library and all the intermediate object files are placed in a platform -specific sub-directory named the same as BOARD or PLATFORM (if BOARD is not -defined), for example "sim", "xtkc705". To build ThreadX with thread-safe C library support, define TX_THREAD_SAFE_CLIB -in your build, as described in section 5 and in the Makefile. Please note -that the C library is only safe for use in threads, not in interrupt handlers. -It may also safely be used in tx_application_define (after tx_kernel_enter, -before threads are running). - +to 1 (this is set by default in tx_port.h). Note that the C library is only +safe for use in threads, not in interrupt handlers. It may also safely be used +in tx_application_define (after tx_kernel_enter, before threads are running). -3. Demonstration System -The ThreadX demonstration is designed to execute under Xtensa instruction set -simulator (ISS) or on a supported evaluation board programmed with your Xtensa -processor configuration. +3. Running the Example -Building the demonstration is easy, simply execute the build_threadx_demo.bat -batch file while inside threadx directory, as follows: +The ThreadX Xtensa example is designed to be run on the Xtensa simulator (ISS) +or a hardware target. By default the example is built for the simulator target. +To run it, -> build_threadx_demo.bat + xt-run demo_threadx.exe or -> xt-make demo + xt-gdb demo_threadx.exe (if you want to run it under the debugger) -Be sure to set or pass into xt-make the variables described in section 2 above -for building the ThreadX library, including the PLATFORM or BOARD you want to -run on. - -This compiles demo_threadx.c (which is the demonstration application) and links -it with the ThreadX objects in tx.a. The resulting file demo_threadx.out is a -ELF binary file that can be downloaded and executed on the target. - -The demo binary appears in the platform specific sub-directory described earlier. -For the following commands, change to that directory or prepend it as the path -of demo_threadx.out. - - -To execute on the simulator: - -> xt-run [--turbo] demo_threadx.out - -The option --turbo provides much faster, but non-cycle-accurate simulation. -Refer to the Xtensa simulator user manual for further simulator options. - - -To execute on the simulator using the Xplorer GUI based debugger: - -> xplorer --debug demo_threadx.out - - -To execute on a supported evaluation board, download demo_threadx.out per -instructions in the tools manuals. Be sure the board has been programmed -with the correct configuration and is set up to boot from RAM and debug -a downloaded program! Optionally you may connect a terminal or terminal -emulator to the serial port on the board with settings as described in -the board user manual, and see the output of printf on the terminal (if -the demo was compiled with DEMO_USE_PRINTF or DEMO_USE_XTUTIL). +To execute on a supported hardware target, download the example to the board +following instructions in the SDK manuals. Make sure the board has been set +up with the correct configuration (if emulation board) and is set up to boot +from RAM and debug a downloaded program. Optionally you may connect a terminal +or terminal emulator to the serial port on the board with settings as described +in the board user manual, and see the output of printf on the terminal (if +the board support package supports directing standard output to the port). To obtain I/O on a "raw" platform such as an unsupported board, you need to provide low level I/O drivers (eg. inbyte() and outbyte() for character @@ -179,13 +101,8 @@ I/O if you want to use printf etc.). You can run "raw" executables on any Xtensa platform, including simulator and any board, but you will not see any behavior specific to the platform (eg. display, printed output, stopping simulation at end of program). You can, while debugging, use a -debugger mechanism called GDBIO to obtain basic I/O. Use PLATFORM=GDBIO -on your xt-make command line - this is the same as "raw" except it links -some stubs that communicate through the debugger. It is very slow! - -WARNING: It is tempting to add printf calls to other threads in the demo. -If you modify the code in any way, you may need adjust affected threads' -stack sizes. This is especially true if you add a printf call. See 4.5. +debugger mechanism called GDBIO to obtain basic I/O. This requires linking +with the gdbio support library. See the SDK documentation for details. 4. System Initialization @@ -272,16 +189,14 @@ are provided in tx_port.h assuming no optimization (default, -O0). Threads that call C library functions may need larger stacks than those that don't. In particular, use of printf requires a very large stack and will usually cause a stack overflow if inserted in a thread without -enlarging its stack size. See DEMO_STACK_SIZE_PRINTF in demo_threadx.c -for a guideline. Use printf with care! +enlarging its stack size. 5. Assembler / Compiler Switches The following are compiler switches used in building the ThreadX library -and demonstration system. These can be supplied by editing the Makefile -or by overriding the COPT or CFLAGS variables in the make command line -(eg. make COPT="-O2 -DTX_THREAD_SAFE_CLIB"). More details in Makefile. +and demonstration system. These can be supplied by editing the xtensa.cmake +file or by overriding from the environment or command line. Compiler Switch Meaning @@ -291,7 +206,6 @@ Compiler Switch Meaning -mlongcalls Allows assembler and linker to convert call instructions to longer indirect call sequences when target is out of range. - -x assembler-with-cpp Passes .s and .S files through C preprocessor. -Dmacro Define a preprocessor macro with no value. -Dmacro=value Define a preprocessor macro with a value. @@ -306,9 +220,6 @@ Application Defines (preprocessor macros definable with the -D option): can be customized in tx_application_define. Default off. - NOTE: Thread safe support for Xtensa C library requires Xtensa Tools - version RF-2015.2 or later. - TX_ENABLE_STACK_CHECKING Enable generic ThreadX support for stack overflow checking. This can help avoid long debugging sessions or customer support calls @@ -382,7 +293,8 @@ Application Defines (preprocessor macros definable with the -D option): higher bit numbers over those with lower bit numbers at the same level. This works only for low and medium priority interrupts that can be - dispatched to C handlers. + dispatched to C handlers on either NX cores or + on LX cores with 32 or fewer interrupts. TX_SYSTEM_STACK_SIZE=n Specify the size of the interrupt stack, which is the stack that all interrupt handlers switch @@ -455,7 +367,7 @@ If multiple threads use a register, the caller must save and restore it. The saved context stack frames for context switches that occur as a result of interrupt handling (interrupt frame) or from thread-level API calls -(solicited frame) are described in human readable form in xtensa_context.h . +(solicited frame) are described in human readable form in xtensa_context.h. All suspended threads have one of these two types of stack frames. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. An Xtensa architecture port-specific diff --git a/ports/xtensa/xcc/src/tx_clib_lock.c b/ports/xtensa/xcc/src/tx_clib_lock.c index 9e3087202..43f6e2200 100644 --- a/ports/xtensa/xcc/src/tx_clib_lock.c +++ b/ports/xtensa/xcc/src/tx_clib_lock.c @@ -66,6 +66,8 @@ TX_MUTEX clib_lock_mutex; void __malloc_lock (struct _reent * ptr) { + (void) ptr; + if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) { return; } @@ -80,6 +82,8 @@ __malloc_lock (struct _reent * ptr) void __malloc_unlock (struct _reent * ptr) { + (void) ptr; + if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) { return; } @@ -99,6 +103,8 @@ __malloc_unlock (struct _reent * ptr) void __env_lock (struct _reent * ptr) { + (void) ptr; + if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) { return; } @@ -113,6 +119,8 @@ __env_lock (struct _reent * ptr) void __env_unlock (struct _reent * ptr) { + (void) ptr; + if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) { return; } @@ -128,6 +136,12 @@ __env_unlock (struct _reent * ptr) #include #include +#if defined(__DYNAMIC_REENT__) +// Helps to keep code similar between dynamic and non-dynamic. +#undef _reent_ptr +struct _reent * _reent_ptr; +#endif + #define XT_NUM_CLIB_LOCKS (_MAX_LOCK + FOPEN_MAX) typedef TX_MUTEX * _Rmtx; @@ -201,6 +215,32 @@ _Mtxunlock (_Rmtx * mtx) #endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */ +#if defined(__DYNAMIC_REENT__) +/**************************************************************************/ +/* Return libc context pointer for current thread. Overrides weak */ +/* version in libc. Until real threads are active, use the libc's */ +/* global reent struct. */ +/**************************************************************************/ +struct _reent * +__getreent(void) +{ + TX_THREAD * thread_ptr = _tx_thread_current_ptr; + + if (thread_ptr) { + return &(thread_ptr->tx_thread_clib_reent); + } + +#if XSHAL_CLIB == XTHAL_CLIB_XCLIB + extern struct _reent g_reent; /* from xclib */ + return &g_reent; +#elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB + extern struct _reent * _impure_ptr; /* from newlib */ + return _impure_ptr; +#else +#error "Unsupported C library for __DYNAMIC_REENT__" +#endif +} +#endif /**************************************************************************/ /* _sbrk_r - heap allocator. This function is called when the memory */ diff --git a/ports/xtensa/xcc/src/tx_initialize_low_level.c b/ports/xtensa/xcc/src/tx_initialize_low_level.c index de2c2b935..d52689cf4 100644 --- a/ports/xtensa/xcc/src/tx_initialize_low_level.c +++ b/ports/xtensa/xcc/src/tx_initialize_low_level.c @@ -80,6 +80,8 @@ VOID _tx_initialize_low_level(VOID) /* Disable interrupts - don't want any that interact with ThreadX yet. */ TX_DISABLE + /* Suppress compiler warning about set but not used variable. */ + (void) interrupt_save; /* Disable stack limit checking if present. Whatever was set up earlier diff --git a/ports/xtensa/xcc/src/tx_thread_schedule.S b/ports/xtensa/xcc/src/tx_thread_schedule.S index 448dc6d76..6c5951707 100644 --- a/ports/xtensa/xcc/src/tx_thread_schedule.S +++ b/ports/xtensa/xcc/src/tx_thread_schedule.S @@ -166,9 +166,18 @@ _tx_thread_schedule: #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ + /* Note a2 may be trashed by this call, must be reloaded. */ #ifdef __XTENSA_CALL0_ABI__ call0 _tx_execution_thread_enter + movi a2, _tx_thread_current_ptr + l32i a2, a2, 0 #else + /* Ensure that PS.WOE is set for windowed call */ + movi a0, PS_WOE + rsr.ps a3 + or a3, a3, a0 + wsr.ps a3 + rsync call8 _tx_execution_thread_enter #endif #endif @@ -229,14 +238,24 @@ _tx_thread_schedule: rsync /* ensure wsr.CPENABLE has completed */ #endif - wsr a3, PS /* no need to sync PS, delay is OK */ - - /* This does not return to its caller, but to the selected thread. */ + /* De-allocate the remainder of the frame before reenabling interrupts + * to avoid overrunning a task stack of TX_MINIMUM_STACK bytes, which + * can only handle one XT_STK_FRMSZ. + */ #ifdef __XTENSA_CALL0_ABI__ /* 'addi sp, sp, imm' could turn into 'addmi, addi' sequence and make */ /* the sp briefly point to an illegal stack location. Avoid that. */ - addi a2, sp, XT_STK_FRMSZ + addi a2, sp, XT_STK_FRMSZ /* fully deallocate stack frame */ mov sp, a2 + #else + addi a2, sp, XT_STK_FRMSZ - 48 /* initial SP at solicited entry; */ + movsp sp, a2 /* retw will deallocate remainder */ + #endif + + wsr a3, PS /* no need to sync PS, delay is OK */ + + /* This does not return to its caller, but to the selected thread. */ + #ifdef __XTENSA_CALL0_ABI__ ret #else retw diff --git a/ports/xtensa/xcc/src/tx_thread_system_return.S b/ports/xtensa/xcc/src/tx_thread_system_return.S index d1fc4a9ff..af0fa24bf 100644 --- a/ports/xtensa/xcc/src/tx_thread_system_return.S +++ b/ports/xtensa/xcc/src/tx_thread_system_return.S @@ -70,26 +70,25 @@ _tx_thread_system_return: Since this is solicited, no need to save regs compiler doesn't preserve. */ -#if XCHAL_HAVE_XEA3 #ifdef __XTENSA_CALL0_ABI__ - addi sp, sp, -16 + addi a2, sp, -16 /* avoid addi/addmi relaxation that */ + mov sp, a2 /* might temporarily move sp up */ #else entry sp, 48 #endif +#if XCHAL_HAVE_XEA3 s32i a0, sp, 0 /* save return address */ -#else - #ifdef __XTENSA_CALL0_ABI__ - addi a2, sp, -XT_STK_FRMSZ /* avoid addi/addmi relaxation that */ - mov sp, a2 /* might temporarily move sp up */ - #else - entry sp, XT_STK_FRMSZ - #endif #endif #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ #ifdef __XTENSA_CALL0_ABI__ + /* Preserve a0 across the call. */ +#if !XCHAL_HAVE_XEA3 + s32i a0, sp, 0 +#endif call0 _tx_execution_thread_exit + l32i a0, sp, 0 #else call8 _tx_execution_thread_exit #endif @@ -109,6 +108,7 @@ _tx_thread_system_return: interrupts enabled, but we will have to revert SP to point above the exception frame because that is what the dispatch code expects. Must disable interrupts before that. + TODO: disable interrupts prior to stack allocation as we do for XEA2 */ movi a0, .Lret @@ -185,7 +185,27 @@ _tx_thread_system_return: #else /* XEA1 or XEA2 */ + /* Disable interrupts before allocating the full stack frame. Taking + * an interrupt will allocate a second exception stack frame, which will + * overrun a task stack of TX_MINIMUM_STACK bytes. + * Read PS so it can be saved off after stack adjustment. + */ rsr a2, PS + XT_INTS_DISABLE(a3) + + /* Allocate the remainder of the frame here; we already allocated + * 16 bytes for call0 or 48 bytes for windowed upon entry. + * This memory will be deallocated in the solicited exit logic prior + * to reenabling interrupts. + */ + #ifdef __XTENSA_CALL0_ABI__ + addi a3, sp, -XT_STK_FRMSZ + 16 // avoid addi/addmi relaxation again + mov sp, a3 + #else + addi a3, sp, -XT_STK_FRMSZ + 48 + movsp sp, a3 + #endif + s32i a0, sp, XT_STK_PC s32i a2, sp, XT_STK_PS #ifdef __XTENSA_CALL0_ABI__ @@ -205,8 +225,6 @@ _tx_thread_system_return: wsr a2, PS rsync call0 xthal_window_spill_nw - l32i a0, sp, XT_STK_PS - wsr a0, PS // Restore PS value rsync #endif @@ -226,10 +244,9 @@ _tx_thread_system_return: a4 = &_tx_timer_time_slice */ - /* Lock out interrupts (except hi-pri). */ + /* Already locked out interrupts (except hi-pri). */ /* Grab thread control block of current thread. */ movi a2, _tx_thread_current_ptr /* a2 = &_tx_thread_current_ptr */ - XT_INTS_DISABLE(a0) l32i a3, a2, 0 /* a3 points to TCB */ /* Mark as having solicited entry to kernel (used on exit). */ diff --git a/ports/xtensa/xcc/src/xtensa_context.S b/ports/xtensa/xcc/src/xtensa_context.S index e4b9aa0a7..7e58ba14c 100644 --- a/ports/xtensa/xcc/src/xtensa_context.S +++ b/ports/xtensa/xcc/src/xtensa_context.S @@ -131,7 +131,7 @@ _xt_context_save: s32i a3, sp, XT_STK_ATOMCTL #endif - #if XT_USE_SWPRI + #ifdef XT_USE_SWPRI /* Save virtual priority mask */ movi a3, _xt_vpri_mask l32i a3, a3, 0 @@ -318,7 +318,7 @@ _xt_context_restore: ret -#endif /* XCHAL_HAVE_XEA3 */ +#endif /* XCHAL_HAVE_XEA2 */ /******************************************************************************* diff --git a/ports/xtensa/xcc/src/xtensa_intr.c b/ports/xtensa/xcc/src/xtensa_intr.c index c5f320cb5..2f0622cda 100644 --- a/ports/xtensa/xcc/src/xtensa_intr.c +++ b/ports/xtensa/xcc/src/xtensa_intr.c @@ -1,5 +1,5 @@ /******************************************************************************* -Copyright (c) 2006-2019 Cadence Design Systems Inc. +Copyright (c) 2006-2023 Cadence Design Systems Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -80,7 +80,7 @@ xt_exc_handler xt_set_exception_handler(uint32_t n, xt_exc_handler f) #if XCHAL_HAVE_INTERRUPTS -#if XCHAL_HAVE_XEA2 +#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32) /* Defined in xtensa_intr_asm.S */ extern uint32_t _xt_intenable; extern uint32_t _xt_vpri_mask; @@ -93,7 +93,7 @@ typedef struct xt_handler_table_entry { void * arg; } xt_handler_table_entry; -#if (XT_USE_INT_WRAPPER || XCHAL_HAVE_XEA3) +#if XCHAL_HAVE_XEA3 extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS + 1]; #else extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS]; @@ -131,7 +131,7 @@ xt_handler xt_set_interrupt_handler(uint32_t n, xt_handler f, void * arg) } #endif -#if (XT_USE_INT_WRAPPER || XCHAL_HAVE_XEA3) +#if XCHAL_HAVE_XEA3 entry = _xt_interrupt_table + n + 1; #else entry = _xt_interrupt_table + n; @@ -157,7 +157,7 @@ xt_handler xt_set_interrupt_handler(uint32_t n, xt_handler f, void * arg) */ void xt_interrupt_enable(uint32_t intnum) { -#if XCHAL_HAVE_XEA2 +#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32) uint32_t ps = XT_RSIL(15); // New INTENABLE = (_xt_intenable | mask) & _xt_vpri_mask. @@ -177,7 +177,7 @@ void xt_interrupt_enable(uint32_t intnum) */ void xt_interrupt_disable(uint32_t intnum) { -#if XCHAL_HAVE_XEA2 +#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32) uint32_t ps = XT_RSIL(15); // New INTENABLE = (_xt_intenable & ~mask) & _xt_vpri_mask. diff --git a/ports/xtensa/xcc/src/xtensa_intr_asm.S b/ports/xtensa/xcc/src/xtensa_intr_asm.S index e972378a6..c2bf15741 100644 --- a/ports/xtensa/xcc/src/xtensa_intr_asm.S +++ b/ports/xtensa/xcc/src/xtensa_intr_asm.S @@ -45,7 +45,7 @@ ------------------------------------------------------------------------------- */ -#if XCHAL_HAVE_XEA2 +#if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32) .data .global _xt_intdata @@ -112,9 +112,6 @@ _xt_interrupt_table: #if XCHAL_HAVE_XEA3 .word xt_interrupt_wrapper .word 0 -#elif XT_USE_INT_WRAPPER - .word 0 - .word 0 #endif .set i, 0 diff --git a/ports/xtensa/xcc/src/xtensa_intr_wrapper.c b/ports/xtensa/xcc/src/xtensa_intr_wrapper.c index 4ccb29f5b..76efec68c 100644 --- a/ports/xtensa/xcc/src/xtensa_intr_wrapper.c +++ b/ports/xtensa/xcc/src/xtensa_intr_wrapper.c @@ -40,7 +40,7 @@ #include "tx_thread.h" #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -#include "tx_execution_profile.h" +#include "../../utility/execution_profile_kit/tx_execution_profile.h" #endif diff --git a/ports/xtensa/xcc/src/xtensa_vectors.S b/ports/xtensa/xcc/src/xtensa_vectors.S index 7b09638e4..1dedd83d1 100644 --- a/ports/xtensa/xcc/src/xtensa_vectors.S +++ b/ports/xtensa/xcc/src/xtensa_vectors.S @@ -75,6 +75,12 @@ /* Enable stack backtrace across exception/interrupt - see below */ #define XT_DEBUG_BACKTRACE 1 +#if (XCHAL_NUM_INTERRUPTS > 32) +#define XT_EXTD_INTERRUPTS 1 +#else +#define XT_EXTD_INTERRUPTS 0 +#endif + /* -------------------------------------------------------------------------------- @@ -103,6 +109,97 @@ addi \aout, \aout, 1 /* return aout + 1 */ .endm + +/* +-------------------------------------------------------------------------------- + Macro debug_backtrace + + This bit of code provides a nice debug backtrace in the debugger. + It does take a few more instructions, so undef XT_DEBUG_BACKTRACE + if you want to save the cycles. + + Input : "ra" - Return address register (clobbered) + Input : "tmp" - Temp register (clobbered), must be a different register + Input : "level" - Numeric interrupt level + Output : "ra" - Return address modified to simulate call4 +-------------------------------------------------------------------------------- +*/ + + .macro debug_backtrace ra, tmp, level + #if XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + rsr \ra, EPC_1 + \level - 1 /* return address */ + movi \tmp, 0xC0000000 /* constant with top 2 bits set (call size) */ + or \ra, \ra, \tmp /* set top 2 bits */ + addx2 \ra, \tmp, \ra /* clear top bit -- simulating call4 size */ + #endif + #endif + .endm + + +/* +-------------------------------------------------------------------------------- + Macro call_exec_isr_entry_fn + + Call the ISR enter function to indicate an ISR is executing. + + Inputs : None + Output : Nothing +-------------------------------------------------------------------------------- +*/ + .macro call_exec_isr_entry_fn + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + #ifdef __XTENSA_CALL0_ABI__ + /* Preserve a2 across the call, a12 is callee-saved for call0 ABI. */ + mov a12, a2 + call0 _tx_execution_isr_enter + mov a2, a12 + #else + call4 _tx_execution_isr_enter + #endif + #endif + .endm + + +/* +-------------------------------------------------------------------------------- + Macro call_int_hook + + Call interrupt hook if present to (pre)handle interrupts. + NOTE: macro does not parameterize all used registers since they cannot freely + be changed, either due to ABI conventions or other assembly code in this file. + + Input : "level" - Interrupt level being processed + Input : "block" - Index of interrupt block being processed [0..3] + Input : "goto_on_done" - Label where control proceeds to if hook returns 0 + Input : a2 - bitmask of pending interrupts in block being processed [0..3] + Output : a2 - updated bitmask of pending interrupts + Clobbers : a2, a4, and: + Clobbers : for windowed ABI: a6, a7 + Clobbers : for call0 ABI: a3 +-------------------------------------------------------------------------------- +*/ + .macro call_int_hook level, block, goto_on_done + #ifdef XT_INTEXC_HOOKS + movi a4, _xt_intexc_hooks + l32i a4, a4, \level << 2 + beqz a4, 2f + #ifdef __XTENSA_CALL0_ABI__ + movi a3, \block + callx0 a4 + beqz a2, \goto_on_done + #else + mov a6, a2 + movi a7, \block + callx4 a4 + beqz a6, \goto_on_done + mov a2, a6 + #endif +2: + #endif + .endm + + /* -------------------------------------------------------------------------------- Macro dispatch_c_isr - dispatch interrupts to user ISRs. @@ -124,59 +221,134 @@ NOTE: This macro will use registers a0 and a2-a6. The arguments are: level -- interrupt level mask -- interrupt bitmask for this level + mask1 -- interrupt bitmask for this level for bits 63:32 (XT_EXTD_INTERRUPTS) + mask2 -- interrupt bitmask for this level for bits 95:64 (XT_EXTD_INTERRUPTS) + mask3 -- interrupt bitmask for this level for bits 127:96 (XT_EXTD_INTERRUPTS) -------------------------------------------------------------------------------- */ - .macro dispatch_c_isr level mask + .macro dispatch_c_isr level mask mask1 mask2 mask3 /* Get mask of pending, enabled interrupts at this level into a2. */ .L_xt_user_int_&level&: - rsr a2, INTENABLE + + #if XT_EXTD_INTERRUPTS + + /* When > 32 interrupts are configured, maintain at least 2 instructions + between RSR.INTERRUPT and branch instructions to avoid interlocks. + */ + #if (XCHAL_NUM_INTERRUPTS > 96) + rsr a6, INTERRUPT3 + #endif + #if (XCHAL_NUM_INTERRUPTS > 64) + rsr a5, INTERRUPT2 + #endif + rsr a4, INTERRUPT1 rsr a3, INTERRUPT - movi a4, \mask - and a2, a2, a3 - and a2, a2, a4 - beqz a2, 9f /* nothing to do */ + #if (XCHAL_NUM_INTERRUPTS > 96) + _bnez a6, .L_xt_user_int_&level&_chk_blk3 + #endif + #if (XCHAL_NUM_INTERRUPTS > 64) + _bnez a5, .L_xt_user_int_&level&_chk_blk2 + #endif + _bnez a4, .L_xt_user_int_&level&_chk_blk1 + _bnez a3, .L_xt_user_int_&level&_chk + j 9f /* spurious */ - /* This bit of code provides a nice debug backtrace in the debugger. - It does take a few more instructions, so undef XT_DEBUG_BACKTRACE - if you want to save the cycles. + #if (XCHAL_NUM_INTERRUPTS > 96) + /* Identify and process block 3 interrupts. If none are active, + proceed to check subsequent blocks; thus preserve a3-a5. */ - #if XT_DEBUG_BACKTRACE - #ifndef __XTENSA_CALL0_ABI__ - rsr a0, EPC_1 + \level - 1 /* return address */ - movi a4, 0xC0000000 /* constant with top 2 bits set (call size) */ - or a0, a0, a4 /* set top 2 bits */ - addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */ +.L_xt_user_int_&level&_chk_blk3: + rsr a2, INTENABLE3 + and a2, a2, a6 + movi a6, \mask3 + and a2, a2, a6 + beqz a2, .L_xt_user_int_&level&_chk_blk2 + + /* Block 3 interrupt(s) pending */ + debug_backtrace a0, a4, \level + call_exec_isr_entry_fn + call_int_hook \level, 3, 9f + extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ + wsr a4, INTCLEAR3 /* clear sw or edge-triggered interrupt */ + #ifndef TX_NO_TIMER + #if (XT_TIMER_INTEN_BLK == 3) + movi a3, XT_TIMER_INTEN_BIT /* a3 = timer interrupt bit */ + beq a3, a4, 7f /* if timer interrupt then skip table */ + #endif #endif + movi a5, _xt_interrupt_table + 8*96 /* a5 = dispatch table for block 3 */ + j .L_xt_user_int_&level&_post_clear #endif - #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the ISR enter function to indicate an ISR is executing. */ - #ifdef __XTENSA_CALL0_ABI__ - call0 _tx_execution_isr_enter - #else - call4 _tx_execution_isr_enter + #if (XCHAL_NUM_INTERRUPTS > 64) + /* Identify and process block 2 interrupts. If none are active, + proceed to check subsequent blocks; thus preserve a3-a4. + */ +.L_xt_user_int_&level&_chk_blk2: + rsr a2, INTENABLE2 + movi a6, \mask2 + and a2, a2, a5 + and a2, a2, a6 + beqz a2, .L_xt_user_int_&level&_chk_blk1 + + /* Block 2 interrupt(s) pending */ + debug_backtrace a0, a4, \level + call_exec_isr_entry_fn + call_int_hook \level, 2, 9f + extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ + wsr a4, INTCLEAR2 /* clear sw or edge-triggered interrupt */ + #ifndef TX_NO_TIMER + #if (XT_TIMER_INTEN_BLK == 2) + movi a3, XT_TIMER_INTEN_BIT /* a3 = timer interrupt bit */ + beq a3, a4, 7f /* if timer interrupt then skip table */ #endif #endif + movi a5, _xt_interrupt_table + 8*64 /* a5 = dispatch table for block 2 */ + j .L_xt_user_int_&level&_post_clear + #endif - #ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - movi a4, _xt_intexc_hooks - l32i a4, a4, \level << 2 - beqz a4, 2f - #ifdef __XTENSA_CALL0_ABI__ - callx0 a4 - beqz a2, 9f - #else - mov a6, a2 - callx4 a4 - beqz a6, 9f - mov a2, a6 + /* Identify and process block 1 interrupts. If none are active, + proceed to check subsequent blocks; thus preserve a3. + */ +.L_xt_user_int_&level&_chk_blk1: + rsr a2, INTENABLE1 + movi a6, \mask1 + and a2, a2, a4 + and a2, a2, a6 + beqz a2, .L_xt_user_int_&level&_chk + + /* Block 1 interrupt(s) pending */ + debug_backtrace a0, a4, \level + call_exec_isr_entry_fn + call_int_hook \level, 1, 9f + extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ + wsr a4, INTCLEAR1 /* clear sw or edge-triggered interrupt */ + #ifndef TX_NO_TIMER + #if (XT_TIMER_INTEN_BLK == 1) + movi a3, XT_TIMER_INTEN_BIT /* a3 = timer interrupt bit */ + beq a3, a4, 7f /* if timer interrupt then skip table */ #endif -2: #endif + movi a5, _xt_interrupt_table + 8*32 /* a5 = dispatch table for block 1 */ + j .L_xt_user_int_&level&_post_clear + + #else /* !XT_EXTD_INTERRUPTS */ + rsr a3, INTERRUPT + #endif + +.L_xt_user_int_&level&_chk: + rsr a2, INTENABLE + movi a4, \mask + and a2, a2, a3 + and a2, a2, a4 + beqz a2, 9f /* nothing to do */ + + debug_backtrace a0, a4, \level + call_exec_isr_entry_fn + call_int_hook \level, 0, 9f /* Now look up in the dispatch table and call user ISR if any. */ /* If multiple bits are set then MSB has highest priority. */ @@ -186,7 +358,7 @@ #ifdef XT_USE_SWPRI /* Enable all interrupts at this level that are numerically higher than the one we just selected, since they are treated as higher - priority. + priority. NOTE: SWPRI disabled for XT_EXTD_INTERRUPTS. */ movi a3, \mask /* a3 = all interrupts at this level */ add a2, a4, a4 /* a2 = a4 << 1 */ @@ -205,33 +377,42 @@ #endif wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */ - #ifndef TX_NO_TIMER - movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ + #if (XT_TIMER_INTEN_BLK == 0) + movi a3, XT_TIMER_INTEN_BIT /* a3 = timer interrupt bit */ beq a3, a4, 7f /* if timer interrupt then skip table */ #endif + #endif + movi a5, _xt_interrupt_table + /* Execution could arrive here from the direct, <= 32 interrupt case, or + from one of the XT_EXTD_INTERRUPTS blocks. Regardless, we have: + a4 = MSB (of 32-bit block) of pending interrupt bits, already cleared + a5 = Base of interrupt table (of 32-bit block) + */ +.L_xt_user_int_&level&_post_clear: find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */ - movi a4, _xt_interrupt_table - addx8 a3, a3, a4 /* a3 = address of interrupt table entry */ + addx8 a3, a3, a5 /* a3 = address of interrupt table entry */ l32i a4, a3, XIE_HANDLER /* a4 = handler address */ #ifdef __XTENSA_CALL0_ABI__ + #ifdef XT_USE_SWPRI mov a12, a6 /* save in callee-saved reg */ + #endif l32i a2, a3, XIE_ARG /* a2 = handler arg */ callx0 a4 /* call handler */ + #ifdef XT_USE_SWPRI mov a2, a12 - #else + #endif + #else /* !__XTENSA_CALL0_ABI__ */ + #ifdef XT_USE_SWPRI mov a2, a6 /* save in windowed reg */ + #endif l32i a6, a3, XIE_ARG /* a6 = handler arg */ callx4 a4 /* call handler */ #endif - #ifdef XT_USE_SWPRI j 8f - #else - j .L_xt_user_int_&level& /* check for more interrupts */ - #endif 7: @@ -245,24 +426,24 @@ */ #ifdef __XTENSA_CALL0_ABI__ + #ifdef XT_USE_SWPRI mov a12, a6 + #endif call0 XT_RTOS_TIMER_INT + #ifdef XT_USE_SWPRI mov a2, a12 + #endif #else + #ifdef XT_USE_SWPRI mov a2, a6 + #endif call4 XT_RTOS_TIMER_INT #endif .endif #endif - #ifdef XT_USE_SWPRI - j 8f - #else - j .L_xt_user_int_&level& /* check for more interrupts */ - #endif - - #ifdef XT_USE_SWPRI 8: + #ifdef XT_USE_SWPRI /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from virtual _xt_intenable which _could_ have changed during interrupt @@ -275,7 +456,17 @@ s32i a2, a3, 4 /* update _xt_vpri_mask */ and a4, a4, a2 /* a4 = masked intenable */ wsr a4, INTENABLE /* update INTENABLE */ - #endif + + #elif XT_EXTD_INTERRUPTS + + rsr a2, INTPBL /* INTPBL bit(n-1): pending Ln interrupt */ + bbsi.l a2, \level - 1, .L_xt_user_int_&level& + + #else + + j .L_xt_user_int_&level& /* check for more interrupts */ + + #endif /* XT_USE_SWPRI */ 9: /* done */ @@ -769,7 +960,11 @@ _xt_lowint1: /* OK to call C code at this point, dispatch user ISRs */ +#if XT_EXTD_INTERRUPTS + dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK XCHAL_INTLEVEL1_MASK1 XCHAL_INTLEVEL1_MASK2 XCHAL_INTLEVEL1_MASK3 +#else dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK +#endif /* Done handling interrupts, transfer control to OS */ call0 XT_RTOS_INT_EXIT /* does not return directly here */ @@ -849,7 +1044,11 @@ _xt_medint2: /* OK to call C code at this point, dispatch user ISRs */ +#if XT_EXTD_INTERRUPTS + dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK XCHAL_INTLEVEL2_MASK1 XCHAL_INTLEVEL2_MASK2 XCHAL_INTLEVEL2_MASK3 +#else dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK +#endif /* Done handling interrupts, transfer control to OS */ call0 XT_RTOS_INT_EXIT /* does not return directly here */ @@ -920,7 +1119,11 @@ _xt_medint3: /* OK to call C code at this point, dispatch user ISRs */ +#if XT_EXTD_INTERRUPTS + dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK XCHAL_INTLEVEL3_MASK1 XCHAL_INTLEVEL3_MASK2 XCHAL_INTLEVEL3_MASK3 +#else dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK +#endif /* Done handling interrupts, transfer control to OS */ call0 XT_RTOS_INT_EXIT /* does not return directly here */ @@ -990,7 +1193,11 @@ _xt_medint4: /* OK to call C code at this point, dispatch user ISRs */ +#if XT_EXTD_INTERRUPTS + dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK XCHAL_INTLEVEL4_MASK1 XCHAL_INTLEVEL4_MASK2 XCHAL_INTLEVEL4_MASK3 +#else dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK +#endif /* Done handling interrupts, transfer control to OS */ call0 XT_RTOS_INT_EXIT /* does not return directly here */ @@ -1060,7 +1267,11 @@ _xt_medint5: /* OK to call C code at this point, dispatch user ISRs */ +#if XT_EXTD_INTERRUPTS + dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK XCHAL_INTLEVEL5_MASK1 XCHAL_INTLEVEL5_MASK2 XCHAL_INTLEVEL5_MASK3 +#else dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK +#endif /* Done handling interrupts, transfer control to OS */ call0 XT_RTOS_INT_EXIT /* does not return directly here */ @@ -1130,7 +1341,11 @@ _xt_medint6: /* OK to call C code at this point, dispatch user ISRs */ +#if XT_EXTD_INTERRUPTS + dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK XCHAL_INTLEVEL6_MASK1 XCHAL_INTLEVEL6_MASK2 XCHAL_INTLEVEL6_MASK3 +#else dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK +#endif /* Done handling interrupts, transfer control to OS */ call0 XT_RTOS_INT_EXIT /* does not return directly here */ diff --git a/utility/execution_profile_kit/tx_execution_profile.h b/utility/execution_profile_kit/tx_execution_profile.h index fa09ac2ed..0b82082cf 100644 --- a/utility/execution_profile_kit/tx_execution_profile.h +++ b/utility/execution_profile_kit/tx_execution_profile.h @@ -56,10 +56,28 @@ typedef unsigned long EXECUTION_TIME_SOURCE_TYPE; /* Define basic constants for the execution profile kit. */ +#if defined(__XTENSA__) + +/* Example for Xtensa targets: */ +#ifndef TX_EXECUTION_TIME_SOURCE +#include +#if XCHAL_HAVE_CCOUNT +#include +#define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME_SOURCE_TYPE) XT_RSR_CCOUNT() +#else +#define TX_EXECUTION_TIME_SOURCE 0 +#endif +#endif + +#else /* __XTENSA__ */ + /* Example for Cortex-M targets: */ #ifndef TX_EXECUTION_TIME_SOURCE #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME_SOURCE_TYPE) *((volatile ULONG *) 0xE0001004) #endif + +#endif /* __XTENSA__ */ + #ifndef TX_EXECUTION_MAX_TIME_SOURCE #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFFFFFF #endif From 5513b1724adee994491b20a803d7c76a7cee9943 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Mon, 25 May 2026 11:28:55 -0400 Subject: [PATCH 17/29] Added port for the OpenHW CORE-V MCU platform (#535) Adds a complete ThreadX port for the OpenHW CORE-V MCU SoC, targeting the Digilent Nexys A7 FPGA board with an Ashling Opella-LD debug probe. New files --------- cmake/riscv64-gcc-rv32imc.cmake CMake toolchain file for riscv64-unknown-elf-gcc targeting rv32imc_zicsr/ilp32. ports/risc-v32/gnu/example_build/core_v_mcu/ -- Full BSP + demo application: Assembly crt0.S C runtime startup (BSS clear, GP/SP init, call main) vectors.S 32-entry vectored interrupt table at 0x1c000800 tx_initialize_low_level.S mtvec setup (vectored mode), stack/free-mem pointers BSP drivers (bsp/) system_core_v_mcu.c Top-level init and ISR dispatcher (isr_table[32]) irq.c PULP APB interrupt controller (enable/disable/mask) timer_irq.c PULP FC Timer -- 100 Hz tick from 10 MHz SOC clock fll.c Frequency Locked Loop -- 5 MHz to 50 MHz (FPGA) uart_driver.c UDMA UART channel 0 -- polled TX, non-blocking RX (8-bit transfer width) gpio.c PULP apb_gpiov2 driver: set/clear/toggle/direction by pin index; pad-mux via per-pad indexed registers at APB_SOC_CTRL + 0x400 + pad*4; full pinmux API (gpio_setpinmux, gpio_getpinmux, gpio_pin_set_dir, gpio_pin_read_status) i2c_master.c Polled UDMA I2C master adt7420.c ADT7420 temperature sensor driver string.c Freestanding memset/memcpy shim (no newlib) Headers (include/) Peripheral register maps, MMIO inlines, BSP API declarations, tx_user.h Application demo_threadx.c Two threads: LED[0] blink at 1 Hz (IO pad 11, GPIO pin 4, MUX=2) + UART heartbeat with startup banner ("Eclipse ThreadX for OpenHW CORE-V MCU vX.Y.Z.BBBBB") link.ld Linker script: .vectors@0x1c000800, .text@0x1c000880 CMakeLists.txt Build definition (references THREADX_ROOT) build.sh One-shot CMake+Ninja build script Tooling install_deps.sh Automates toolchain/OpenOCD dependency setup deploy.sh One-step GDB flashing via Ashling Opella-LD; gdb-multiarch fallback when riscv64-unknown-elf-gdb is absent; supports --wsl flag required by usbipd-win v5.x openocd-nexys-Ashling-Opella-LD.cfg OpenOCD config for Opella-LD over JTAG Tests (tests/) test_irq.c / test_timer.c Host-compiled unit tests (2/2 pass) mock/mmio_mock.* Software MMIO register map for host testing Documentation README.md Hardware overview, build, flash/debug, BSP API reference Architecture notes ------------------ - CV32E40P uses the PULP/PULPissimo interrupt controller (not CLINT); IRQ lines are masked via APB registers, not the mie CSR. - mtvec must be 256-byte aligned; vectors placed at 0x1c000800 (vectored mode). - Timer IRQ = line 10; dispatch via isr_table[mcause & 0x1f]. - Build: -march=rv32imc_zicsr -mabi=ilp32, -ffreestanding, -nodefaultlibs. - Verified: ELF 11 KB text, sections at correct addresses, unit tests pass. Third-party attributions ------------------------ BSP files derived from core-v-freertos (Apache-2.0): (c) 2019-2020 ETH Zurich and University of Bologna (c) 2020 GreenWaves Technologies (c) 2011-2014 Wind River Systems, Inc. (c) 2017 SiFive Inc. (crt0.S, BSD-2-Clause portions) All original copyright notices retained; see individual file headers. SPDX: Apache-2.0 AND MIT (crt0.S: (Apache-2.0 OR BSD-2-Clause) AND MIT). Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- cmake/riscv64-gcc-rv32imc.cmake | 64 +++ .../example_build/core_v_mcu/CMakeLists.txt | 65 +++ .../gnu/example_build/core_v_mcu/README.md | 501 ++++++++++++++++++ .../gnu/example_build/core_v_mcu/bsp/fll.c | 209 ++++++++ .../gnu/example_build/core_v_mcu/bsp/gpio.c | 128 +++++ .../example_build/core_v_mcu/bsp/i2c_master.c | 153 ++++++ .../gnu/example_build/core_v_mcu/bsp/irq.c | 50 ++ .../gnu/example_build/core_v_mcu/bsp/string.c | 64 +++ .../core_v_mcu/bsp/system_core_v_mcu.c | 132 +++++ .../core_v_mcu/bsp/temp_sensor.c | 46 ++ .../example_build/core_v_mcu/bsp/timer_irq.c | 58 ++ .../core_v_mcu/bsp/uart_driver.c | 169 ++++++ .../gnu/example_build/core_v_mcu/build.sh | 9 + .../gnu/example_build/core_v_mcu/crt0.S | 48 ++ .../example_build/core_v_mcu/demo_threadx.c | 134 +++++ .../gnu/example_build/core_v_mcu/deploy.sh | 142 +++++ .../gnu/example_build/core_v_mcu/gdb_init | 6 + .../example_build/core_v_mcu/include/bits.h | 59 +++ .../example_build/core_v_mcu/include/csr.h | 75 +++ .../example_build/core_v_mcu/include/fll.h | 93 ++++ .../example_build/core_v_mcu/include/gpio.h | 68 +++ .../core_v_mcu/include/i2c_master.h | 38 ++ .../gnu/example_build/core_v_mcu/include/io.h | 61 +++ .../example_build/core_v_mcu/include/irq.h | 64 +++ .../core_v_mcu/include/memory_map.h | 39 ++ .../core_v_mcu/include/properties.h | 43 ++ .../core_v_mcu/include/pulp_mem_map.h | 103 ++++ .../example_build/core_v_mcu/include/string.h | 25 + .../core_v_mcu/include/system_core_v_mcu.h | 29 + .../core_v_mcu/include/temp_sensor.h | 29 + .../example_build/core_v_mcu/include/timer.h | 120 +++++ .../core_v_mcu/include/timer_irq.h | 26 + .../core_v_mcu/include/tx_user.h | 22 + .../core_v_mcu/include/uart_driver.h | 27 + .../example_build/core_v_mcu/install_deps.sh | 53 ++ .../gnu/example_build/core_v_mcu/link.ld | 65 +++ .../openocd-nexys-Ashling-Opella-LD.cfg | 41 ++ .../core_v_mcu/tests/CMakeLists.txt | 28 + .../core_v_mcu/tests/mock/mmio_mock.c | 18 + .../core_v_mcu/tests/mock/mmio_mock.h | 45 ++ .../example_build/core_v_mcu/tests/test_irq.c | 66 +++ .../core_v_mcu/tests/test_timer.c | 53 ++ .../core_v_mcu/tx_initialize_low_level.S | 63 +++ .../gnu/example_build/core_v_mcu/vectors.S | 25 + .../gnu/src/tx_thread_context_restore.S | 4 +- 45 files changed, 3358 insertions(+), 2 deletions(-) create mode 100644 cmake/riscv64-gcc-rv32imc.cmake create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/README.md create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/fll.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/gpio.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/i2c_master.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/irq.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/string.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/system_core_v_mcu.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/temp_sensor.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/timer_irq.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/uart_driver.c create mode 100755 ports/risc-v32/gnu/example_build/core_v_mcu/build.sh create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/crt0.S create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/demo_threadx.c create mode 100755 ports/risc-v32/gnu/example_build/core_v_mcu/deploy.sh create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/gdb_init create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/bits.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/csr.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/fll.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/gpio.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/i2c_master.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/io.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/irq.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/memory_map.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/properties.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/pulp_mem_map.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/string.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/system_core_v_mcu.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/temp_sensor.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/timer.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/timer_irq.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/tx_user.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/include/uart_driver.h create mode 100755 ports/risc-v32/gnu/example_build/core_v_mcu/install_deps.sh create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/link.ld create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/openocd-nexys-Ashling-Opella-LD.cfg create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/tests/CMakeLists.txt create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/tests/mock/mmio_mock.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/tests/mock/mmio_mock.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/tests/test_irq.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/tests/test_timer.c create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/tx_initialize_low_level.S create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/vectors.S diff --git a/cmake/riscv64-gcc-rv32imc.cmake b/cmake/riscv64-gcc-rv32imc.cmake new file mode 100644 index 000000000..836ed1ce3 --- /dev/null +++ b/cmake/riscv64-gcc-rv32imc.cmake @@ -0,0 +1,64 @@ +# /*************************************************************************** +# * Copyright (C) 2026 Eclipse ThreadX contributors +# * +# * This program and the accompanying materials are made available under the +# * terms of the MIT License which is available at +# * https://opensource.org/licenses/MIT. +# * +# * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). +# * The AI-generated portions may be considered public domain (CC0-1.0) +# * and not subject to the project's licence. The human contributor has +# * reviewed and verified that the code is correct. +# * +# * SPDX-License-Identifier: MIT and CC0-1.0 +# ***************************************************************************/ + +# CMake toolchain file for CORE-V MCU (CV32E40P, RV32IMC) +# +# Uses the riscv64-unknown-elf-gcc multi-lib toolchain (Ubuntu package +# gcc-riscv64-unknown-elf) to cross-compile for a 32-bit RISC-V target. +# +# Target ISA : rv32imc_zicsr (integer, multiply, compressed, Zicsr) +# ABI : ilp32 (32-bit int/long/ptr, no hardware FP) +# Code model : medlow (addresses in [0, 2 GiB)) + +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR riscv) + +set(THREADX_ARCH "risc-v32") +set(THREADX_TOOLCHAIN "gnu") + +set(ARCH_FLAGS "-march=rv32imc_zicsr -mabi=ilp32 -mcmodel=medlow") +set(CFLAGS "${ARCH_FLAGS}") +set(ASFLAGS "${ARCH_FLAGS}") +set(LDFLAGS "${ARCH_FLAGS}") + +# Toolchain binaries (riscv64-unknown-elf can target rv32 via multilib) +set(CMAKE_C_COMPILER riscv64-unknown-elf-gcc) +set(CMAKE_CXX_COMPILER riscv64-unknown-elf-g++) +set(AS riscv64-unknown-elf-as) +set(AR riscv64-unknown-elf-ar) +set(OBJCOPY riscv64-unknown-elf-objcopy) +set(OBJDUMP riscv64-unknown-elf-objdump) +set(SIZE riscv64-unknown-elf-size) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) + +# Use static library for compiler feature probing (no linker script yet) +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${CFLAGS}" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags") + +set(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug flags") +set(CMAKE_CXX_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "cxx debug flags") +set(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug flags") + +set(CMAKE_C_FLAGS_RELEASE "-Os" CACHE INTERNAL "c release flags") +set(CMAKE_CXX_FLAGS_RELEASE "-Os" CACHE INTERNAL "cxx release flags") +set(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release flags") diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt b/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt new file mode 100644 index 000000000..eb6b4c89f --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt @@ -0,0 +1,65 @@ +cmake_minimum_required(VERSION 3.15 FATAL_ERROR) + +project(demo_threadx_core_v_mcu LANGUAGES C ASM) +set(CMAKE_C_STANDARD 99) +set(CMAKE_C_STANDARD_REQUIRED ON) + +set(CORE_V_MCU_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(THREADX_ROOT ${CMAKE_CURRENT_LIST_DIR}/../../../../..) +set(TX_USER_FILE ${CORE_V_MCU_DIR}/include/tx_user.h) + +set(THREADX_ARCH "risc-v32") +set(THREADX_TOOLCHAIN "gnu") +add_subdirectory(${THREADX_ROOT} threadx) +target_include_directories(threadx PRIVATE ${CORE_V_MCU_DIR}/include) + +set(SRCS + ${CORE_V_MCU_DIR}/crt0.S + ${CORE_V_MCU_DIR}/vectors.S + ${CORE_V_MCU_DIR}/tx_initialize_low_level.S + ${CORE_V_MCU_DIR}/bsp/irq.c + ${CORE_V_MCU_DIR}/bsp/timer_irq.c + ${CORE_V_MCU_DIR}/bsp/fll.c + ${CORE_V_MCU_DIR}/bsp/gpio.c + ${CORE_V_MCU_DIR}/bsp/uart_driver.c + ${CORE_V_MCU_DIR}/bsp/i2c_master.c + ${CORE_V_MCU_DIR}/bsp/temp_sensor.c + ${CORE_V_MCU_DIR}/bsp/system_core_v_mcu.c + ${CORE_V_MCU_DIR}/bsp/string.c + ${CORE_V_MCU_DIR}/demo_threadx.c +) + +add_executable(demo_threadx ${SRCS}) +set_target_properties(demo_threadx PROPERTIES OUTPUT_NAME "demo_threadx.elf") + +target_include_directories(demo_threadx PRIVATE + ${CORE_V_MCU_DIR}/include + ${THREADX_ROOT}/common/inc + ${THREADX_ROOT}/ports/risc-v32/gnu/inc +) + +target_link_libraries(demo_threadx PRIVATE threadx gcc) + +target_link_options(demo_threadx PRIVATE + -T${CORE_V_MCU_DIR}/link.ld + -nostartfiles + -nodefaultlibs + -Wl,--gc-sections + -Wl,-Map=${CMAKE_CURRENT_BINARY_DIR}/demo_threadx.map +) + +target_compile_options(demo_threadx PRIVATE + -Os + -g + -Wall + -Wextra + -ffreestanding + -ffunction-sections + -fdata-sections + -DTX_INCLUDE_USER_DEFINE_FILE +) + +add_custom_command(TARGET demo_threadx POST_BUILD + COMMAND ${OBJCOPY} -O binary $ ${CMAKE_CURRENT_BINARY_DIR}/demo_threadx.bin + COMMENT "Generating demo_threadx.bin" +) diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/README.md b/ports/risc-v32/gnu/example_build/core_v_mcu/README.md new file mode 100644 index 000000000..d94759d00 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/README.md @@ -0,0 +1,501 @@ +# ThreadX Port for CORE-V MCU + +This directory contains the Board Support Package (BSP) and demo application for +running Eclipse ThreadX on the +[CORE-V MCU](https://github.com/openhwgroup/core-v-mcu) — an open-source 32-bit +RISC-V SoC based on the CV32E40P core (RV32IMC). The reference hardware is a +[Digilent Nexys A7](https://digilent.com/reference/programmable-logic/nexys-a7/start) +FPGA board running the synthesised CORE-V MCU bitstream. + +--- + +## Table of Contents + +1. [Hardware overview](#1-hardware-overview) +2. [Software prerequisites](#2-software-prerequisites) +3. [Directory structure](#3-directory-structure) +4. [Architecture notes](#4-architecture-notes) +5. [Memory map](#5-memory-map) +6. [Building](#6-building) +7. [Flashing and debugging](#7-flashing-and-debugging) +8. [BSP API reference](#8-bsp-api-reference) +9. [Unit tests](#9-unit-tests) +10. [Adapting to a different board](#10-adapting-to-a-different-board) +11. [Setup and deployment scripts](#11-setup-and-deployment-scripts) + +--- + +## 1. Hardware overview + +| Item | Detail | +|------|--------| +| CPU | CV32E40P — RV32IMC, in-order, 4-stage pipeline | +| ISA | `rv32imc_zicsr` (integer, compressed, multiply/divide, CSR instructions) | +| L2 SRAM | 512 KB at `0x1c000000` (code + data + stack) | +| Interrupt controller | PULP APB interrupt controller (32 lines, **not** a standard CLINT) | +| Timer | PULP FC Timer at `0x1A10B000`, 32 kHz reference clock | +| UART | UDMA UART channel 0 at `0x1A102080` | +| GPIO | PULP GPIO controller at `0x1A101000` | +| FLL | Frequency Locked Loop — 5 MHz input (FPGA), 50 MHz output | +| Debug probe | [Ashling Opella LD](https://www.ashling.com/ashling-opella-ld/) via JTAG | + +The CV32E40P does **not** implement the standard RISC-V CLINT (`mip`/`mie` per-source +masking). Individual interrupt lines are enabled and cleared through PULP APB +registers, and `mstatus.MIE` (bit 3) acts as the single global enable. + +--- + +## 2. Software prerequisites + +Run `install_deps.sh` to install all dependencies in one step: + +```bash +bash install_deps.sh +``` + +Or install individually: + +| Tool | Minimum version | Notes | +|------|----------------|-------| +| `riscv64-unknown-elf-gcc` | 13.x | `apt install gcc-riscv64-unknown-elf binutils-riscv64-unknown-elf` | +| CMake | 3.15 | `apt install cmake` | +| Ninja | 1.10 | `apt install ninja-build` | +| OpenOCD | 0.12 | `apt install openocd` | +| GDB | any multiarch | `apt install gdb-multiarch` — Ubuntu does not ship `riscv64-unknown-elf-gdb` | + +> **Note:** There is no `riscv32-unknown-elf-gcc` package required. The +> `riscv64-unknown-elf-gcc` compiler generates RV32 code when passed +> `-march=rv32imc_zicsr -mabi=ilp32`, as configured by the toolchain file. + +--- + +## 3. Directory structure + +``` +core_v_mcu/ +├── bsp/ Board Support Package +│ ├── fll.c Frequency Locked Loop driver +│ ├── gpio.c GPIO driver +│ ├── irq.c PULP APB interrupt controller driver +│ ├── string.c Freestanding memset/memcpy shim +│ ├── system_core_v_mcu.c Top-level BSP init and ISR dispatcher +│ ├── timer_irq.c PULP FC Timer driver +│ └── uart_driver.c UDMA UART driver +├── include/ BSP headers +│ ├── bits.h Bit-manipulation macros +│ ├── csr.h CSR access macros +│ ├── fll.h +│ ├── gpio.h +│ ├── io.h MMIO read/write inlines +│ ├── irq.h +│ ├── memory_map.h Peripheral base addresses +│ ├── properties.h Clock/frequency constants +│ ├── pulp_mem_map.h PULP peripheral register offsets +│ ├── string.h Freestanding string shim header +│ ├── system_core_v_mcu.h +│ ├── timer.h +│ ├── timer_irq.h +│ ├── tx_user.h ThreadX compile-time configuration +│ └── uart_driver.h +├── tests/ Host-compiled unit tests (no cross-compiler needed) +│ ├── mock/ +│ │ ├── mmio_mock.c Replaces io.h MMIO inlines with a software map +│ │ └── mmio_mock.h +│ ├── test_irq.c Tests for irq.c +│ ├── test_timer.c Tests for timer_irq.c +│ └── CMakeLists.txt +├── crt0.S C runtime startup (clear BSS, call main) +├── vectors.S 32-entry vectored interrupt table +├── tx_initialize_low_level.S ThreadX platform init (mtvec, stack pointer) +├── link.ld Linker script +├── demo_threadx.c Demo application (blinky + UART heartbeat) +├── CMakeLists.txt Build definition +├── build.sh One-shot build script +├── gdb_init GDB startup script +└── openocd-nexys-Ashling-Opella-LD.cfg OpenOCD configuration +``` + +The ThreadX kernel sources are **not** duplicated here; they are referenced from the +repository root via `THREADX_ROOT`. + +--- + +## 4. Architecture notes + +### 4.1 Interrupt model + +The CV32E40P uses a PULP/PULPissimo-style interrupt controller rather than the +standard RISC-V CLINT. Key differences: + +- **32 direct interrupt lines** connect to the core. `mcause` for an external + interrupt is `0x80000000 | N`, where `N` (bits 4–0) is the line number. +- **Per-line masking** is done through APB registers in the PULP IRQ controller + (`IRQ_REG_MASK_SET_OFFSET` / `IRQ_REG_MASK_CLEAR_OFFSET`) — not through the `mie` + CSR. +- **Global enable** is `mstatus.MIE` (bit 3). ThreadX manages this itself: the + scheduler sets MIE just before entering the WFI idle loop in + `_tx_thread_schedule`. + +ISR dispatch flow: + +``` +CPU takes interrupt + → PC jumps to mtvec base (vectored mode, bit 0 = 1) + → vectors.S entry for line N → tx_trap_entry + → tx_trap_entry saves registers, calls _tx_thread_context_save + → tx_trap_handler(mcause, mepc, mtval) dispatches via isr_table[mcause & 0x1f] + → ThreadX timer ISR (line 10) calls _tx_timer_interrupt + → _tx_thread_context_restore (never returns to tx_trap_entry) +``` + +### 4.2 `mtvec` alignment + +The CV32E40P requires the vector table base to be **256-byte aligned**. The linker +script places `.vectors` at `0x1c000800`, which satisfies this. `mtvec` is written +as `0x1c000801` (base + vectored-mode bit). + +### 4.3 ThreadX timer tick + +- Reference clock: 32 768 Hz (ARCHI_REF_CLOCK) +- Tick rate: 100 Hz → compare value 327 (~0.1 % drift) +- The timer auto-reloads on compare match (cycle mode) +- `_tx_timer_interrupt` is registered in `isr_table[10]` during `system_init()` + +### 4.4 FLL and clock + +On the Nexys A7 FPGA, the FLL input is 5 MHz (`ARCHI_FPGA_FREQUENCY`). After +`pi_fll_init()` the system clock is 50 MHz (`DEFAULT_SYSTEM_CLOCK`). The UART baud +rate divisor is computed from this 50 MHz clock. + +### 4.5 Freestanding build + +The port builds with `-ffreestanding -nodefaultlibs` — no newlib or libc. +`bsp/string.c` provides minimal `memset` and `memcpy` for ThreadX internal use. + +--- + +## 5. Memory map + +| Region | Start | Size | Contents | +|--------|-------|------|----------| +| Vector table | `0x1c000800` | 128 B | 32 × 4-byte jump instructions to `tx_trap_entry` | +| `.text` (boot address) | `0x1c000880` | — | Code + read-only data | +| `.data` | after `.text` | — | Initialised data | +| `.bss` | after `.data` | — | Zero-initialised data | +| ThreadX free memory | after `.bss` | — | Heap pools, thread stacks | +| Stack | top of L2 | 8 KB | Initial/idle stack grows downward from `0x1c080000` | + +L2 total: 512 KB (`0x1c000000`–`0x1c07ffff`). + +Peripheral base addresses (see `include/memory_map.h`): + +| Peripheral | Address | +|------------|---------| +| PULP IRQ controller | `0x1A109800` | +| PULP FC Timer | `0x1A10B000` | +| PULP GPIO | `0x1A101000` | +| UDMA UART ch0 | `0x1A102080` | +| FLL | `0x1A100000` | + +--- + +## 6. Building + +### Quick start + +```bash +cd ports/risc-v32/gnu/example_build/core_v_mcu +bash build.sh +``` + +The script configures and builds with Ninja. The output is: + +``` +build/demo_threadx.elf — ELF with debug symbols +build/demo_threadx.bin — raw binary for flashing +build/demo_threadx.map — linker map +``` + +### Manual CMake invocation + +```bash +THREADX_ROOT=$(realpath ../../../../..) +cmake -B build -G Ninja \ + -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv64-gcc-rv32imc.cmake" \ + . +cmake --build build +``` + +### Toolchain file + +`${THREADX_ROOT}/cmake/riscv64-gcc-rv32imc.cmake` sets: + +``` +CMAKE_C_COMPILER riscv64-unknown-elf-gcc +CMAKE_ASM_COMPILER riscv64-unknown-elf-gcc +CMAKE_OBJCOPY riscv64-unknown-elf-objcopy +CMAKE_C_FLAGS -march=rv32imc_zicsr -mabi=ilp32 -mcmodel=medlow +``` + +--- + +## 7. Flashing and debugging + +### 7.1 Quick deploy (recommended) + +Use `deploy.sh` to automate the entire OpenOCD + GDB workflow in one command: + +```bash +# Flash and run (leave target running after GDB exits): +bash deploy.sh + +# Build first, then flash and run: +bash deploy.sh --build + +# Flash and stop at main for interactive debugging: +bash deploy.sh --debug + +# Override the ELF or the OpenOCD config: +bash deploy.sh --elf path/to/my.elf --openocd-cfg path/to/other.cfg +``` + +> **First time only:** run `bash ../../../../../samplex-fd/OpenHW/scripts/setup_opella.sh` +> (or the equivalent path) once to install the udev rule for the Opella LD. +> See [Section 11](#11-setup-and-deployment-scripts) for details. + +### 7.2 Manual procedure + +#### Connect hardware + +1. Connect the Ashling Opella LD to the Nexys A7 JTAG header. +2. Connect the USB-UART cable (CORE-V MCU UART0 mapped to USB micro-B on Nexys A7). +3. Power on the board. + +#### Start OpenOCD + +```bash +openocd -f openocd-nexys-Ashling-Opella-LD.cfg +``` + +Expected output ends with `Ready for Remote Connections`. OpenOCD listens on +port 3333 (GDB) and 4444 (telnet). + +#### Flash and run with GDB + +In a second terminal: + +```bash +riscv64-unknown-elf-gdb --command=gdb_init +``` + +`gdb_init` connects to OpenOCD, loads the ELF, sets a breakpoint at `main`, and +continues. You should see the LED on pin 5 blinking at 1 Hz and the UART printing +`ThreadX on CORE-V MCU` followed by periodic `.` heartbeats at 115 200 baud. + +#### UART monitor + +```bash +minicom -b 115200 -D /dev/ttyUSBx # adjust device as needed +``` + +#### Useful GDB commands + +``` +(gdb) info threads — list ThreadX threads +(gdb) thread 2 — switch to a thread +(gdb) bt — backtrace +(gdb) monitor halt — halt via OpenOCD +(gdb) monitor resume — resume via OpenOCD +``` + +--- + +## 8. BSP API reference + +### `system_core_v_mcu.h` + +```c +void system_init(void); +``` +Initialises FLL, UART, IRQ controller, and FC Timer. Must be called once from +`main()` before `tx_kernel_enter()`. + +### `uart_driver.h` + +```c +int uart_init(uint8_t uart_id, uint32_t baudrate, uint32_t periph_freq); +void uart_write_byte(uint8_t uart_id, uint8_t c); +int uart_read_byte(uint8_t uart_id); /* returns -1 if no data */ +void uart_write_str(uint8_t uart_id, const char *str); +void uart_write_buf(uint8_t uart_id, const uint8_t *buf, uint32_t len); +``` + +`uart_id` 0 is the console UART. `uart_read_byte` is non-blocking. + +### `gpio.h` + +```c +void gpio_init(void); +void gpio_set_output(uint32_t pin_mask); /* configure pins as outputs */ +void gpio_set(uint32_t pin_mask); /* drive high */ +void gpio_clear(uint32_t pin_mask); /* drive low */ +void gpio_toggle(uint32_t pin_mask); +``` + +`pin_mask` is a bitmask where bit N corresponds to GPIO pin N. + +### `irq.h` + +```c +void pulp_irq_init(void); +void irq_enable(uint32_t irq_id); +void irq_disable(uint32_t irq_id); +void irq_clint_enable(void); /* set mstatus.MIE */ +void irq_clint_disable(void); /* clear mstatus.MIE */ +``` + +`irq_id` values are defined as `IRQ_FC_EVT_*` in `irq.h`. The timer uses +`IRQ_FC_EVT_TIMER0_LO` (= 10). + +### `timer_irq.h` + +```c +void timer_irq_init(uint32_t ticks); +void timer_irq_set_timeout(uint32_t ticks, bool enable); +uint32_t timer_irq_cycle_get_32(void); +``` + +### Registering a custom ISR + +Add a function pointer to `isr_table` before calling `tx_kernel_enter()`: + +```c +extern void (*isr_table[32])(void); + +static void my_irq_handler(void) { /* ... */ } + +/* In main() or tx_application_define(), before enabling the line: */ +isr_table[MY_IRQ_LINE] = my_irq_handler; +irq_enable(MY_IRQ_LINE); +``` + +--- + +## 9. Unit tests + +The tests compile for the **host** (no cross-compiler required) using a software +MMIO mock that backs the peripheral register space with a `uint32_t` array. + +```bash +cd tests +cmake -B build -G Ninja +cmake --build build +./build/tx_core_v_mcu_tests +``` + +Expected output: + +``` +irq_tests: PASS +timer_tests: PASS +``` + +The mock is enabled by defining `CORE_V_MCU_MMIO_MOCK` before including `io.h`. +`mmio_mock.c` provides `mock_reg_read` / `mock_reg_write` helpers for assertions. + +--- + +## 10. Adapting to a different board + +To port to a different CORE-V MCU carrier board: + +1. **Clock frequencies** — update `ARCHI_REF_CLOCK`, `ARCHI_FPGA_FREQUENCY`, and + `DEFAULT_SYSTEM_CLOCK` in `include/properties.h`. + +2. **Memory layout** — adjust `ORIGIN` and `LENGTH` for `L2` in `link.ld` and + update `__boot_address` if the boot ROM routes differently. + +3. **mtvec base** — if `.vectors` moves, update the address in `link.ld`. The + 256-byte alignment requirement is a hard CV32E40P constraint. + +4. **Debug probe** — replace `openocd-nexys-Ashling-Opella-LD.cfg` with a config + matching your probe (e.g., `interface jlink` for a J-Link). + +5. **GPIO pin** — `DEMO_LED_PIN` in `demo_threadx.c` selects the LED. Change to + match your board's LED assignment. + +--- + +## 11. Setup and deployment scripts + +### 11.1 `setup_opella.sh` — one-time host setup + +Located in `samplex-fd/OpenHW/scripts/setup_opella.sh`. Run **once per machine** +to grant user-space access to the Ashling Opella LD USB device. + +```bash +# Native Linux: +sudo bash samplex-fd/OpenHW/scripts/setup_opella.sh + +# WSL (also attempts usbipd-win USB forwarding): +bash samplex-fd/OpenHW/scripts/setup_opella.sh +``` + +What it does: + +| Step | Native Linux | WSL | +|------|-------------|-----| +| Write `/etc/udev/rules.d/99-ashling-opella.rules` | ✓ | ✓ | +| Add user to `plugdev` group | ✓ | ✓ | +| Reload udev | ✓ | ✓ | +| `usbipd.exe attach --wsl` (v3: `wsl attach`) | — | automatic | + +> **WSL — one-time bind (Windows admin required):** +> Before the first attach, run this once in an **elevated (Run as Administrator) PowerShell** on the Windows host: +> ```powershell +> usbipd bind --hardware-id 0b6b:0040 +> ``` +> After binding, `setup_opella.sh` handles subsequent attaches automatically. + +> **WSL — if attach fails with "not USBIP capable" (usbipd-win v3 + Ubuntu 22.04+):** +> Ubuntu 22.04 and 24.04 enable systemd by default. usbipd-win **v3** has a +> known bug where it incorrectly reports the kernel as not USBIP capable when +> systemd is running. **Upgrade usbipd-win to v4 or later:** +> +> +> If you are on an older WSL2 kernel without USBIP support, first run: +> ```powershell +> wsl --update +> wsl --shutdown +> ``` + +After running, **re-plug the probe**. On WSL, re-run the script after each WSL restart. + +### 11.2 `deploy.sh` — flash and run + +```bash +# Flash and run (leave target running): +bash deploy.sh + +# Build first, then flash: +bash deploy.sh --build + +# Flash and stop at main for interactive debug session: +bash deploy.sh --debug +``` + +The script starts OpenOCD in the background, waits for it to become ready, +then drives `riscv64-unknown-elf-gdb` to load the ELF. OpenOCD is always +stopped on exit (including Ctrl-C). + +--- + +## Licence + +New files in this directory are © 2026 Eclipse ThreadX contributors, MIT. + +Files derived from +[core-v-freertos](https://github.com/openhwgroup/core-v-freertos) retain their +original Apache-2.0 copyright notices (ETH Zurich, GreenWaves Technologies, Wind +River Systems, SiFive Inc.) and are dual-licensed `Apache-2.0 AND MIT` (or +`(Apache-2.0 OR BSD-2-Clause) AND MIT` for `crt0.S`). See individual file headers. diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/fll.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/fll.c new file mode 100644 index 000000000..46dce8576 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/fll.c @@ -0,0 +1,209 @@ +/***************************************************************************/ +/* Copyright 2020 GreenWaves Technologies + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#include +#include + +#include "bits.h" +#include "csr.h" +#include "fll.h" +#include "irq.h" +#include "properties.h" +#include "system_core_v_mcu.h" + +#define FLL_LOG2_MAXDCO 29U +#define FLL_LOG2_REFCLK ARCHI_REF_CLOCK_LOG2 +#define FLL_LOG2_MAXM (FLL_LOG2_MAXDCO - FLL_LOG2_REFCLK) + +static volatile uint32_t flls_frequency[FLL_NUM]; + +static uint32_t fll_max_u32(uint32_t a, uint32_t b) +{ + return (a > b) ? a : b; +} + +static uint32_t fll_fl1(uint32_t value) +{ + return (uint32_t)(31U - (uint32_t)__builtin_clz(value)); +} + +static uint32_t fll_get_mult_div_from_frequency(uint32_t freq, uint32_t *mult, + uint32_t *div) +{ + uint32_t fref = FLL_REF_CLK; + uint32_t log2_m; + uint32_t d; + uint32_t m; + uint32_t fres; + + if ((freq == 0U) || (mult == NULL) || (div == NULL)) + { + if (mult != NULL) + { + *mult = 0U; + } + if (div != NULL) + { + *div = 0U; + } + return 0U; + } + + if (freq > fref) + { + log2_m = fll_fl1(freq) - fll_fl1(fref); + } + else + { + log2_m = 0U; + } + + if (FLL_LOG2_MAXM > log2_m) + { + d = fll_max_u32(1U, (FLL_LOG2_MAXM - log2_m) >> 1U); + } + else + { + d = 1U; + } + + m = (freq << d) / fref; + fres = (fref * m + (1UL << (d - 1U))) >> d; + + *mult = m; + *div = d + 1U; + return fres; +} + +static uint32_t fll_get_frequency_from_mult_div(uint32_t mult, uint32_t div) +{ + uint32_t fref = FLL_REF_CLK; + + if (div == 0U) + { + return fref * mult; + } + + return (fref * mult) >> (div - 1U); +} + +int pi_fll_set_frequency(fll_type_t which_fll, uint32_t frequency, int check) +{ + uint32_t mult; + uint32_t div; + uint32_t reg1; + uint32_t saved_irq; + + (void)check; + + if ((uint32_t)which_fll >= FLL_NUM) + { + return -1; + } + + if (frequency == 0U) + { + return -1; + } + + saved_irq = irq_clint_disable(); + (void)fll_get_mult_div_from_frequency(frequency, &mult, &div); + + reg1 = FLL_CTRL[which_fll].FLL_CONF1; + reg1 &= ~FLL_CTRL_CONF1_MULTI_FACTOR_MASK; + reg1 |= REG_SET(FLL_CTRL_CONF1_MULTI_FACTOR, mult); + reg1 &= ~FLL_CTRL_CONF1_CLK_OUT_DIV_MASK; + reg1 |= REG_SET(FLL_CTRL_CONF1_CLK_OUT_DIV, div); + FLL_CTRL[which_fll].FLL_CONF1 = reg1; + + flls_frequency[which_fll] = frequency; + if (which_fll == FLL_SOC) + { + system_core_clock = frequency; + } + + if ((saved_irq & MSTATUS_IE) != 0U) + { + (void)irq_clint_enable(); + } + + return (int)frequency; +} + +void pi_fll_init(fll_type_t which_fll, uint32_t ret_state) +{ + uint32_t reg1; + + if ((uint32_t)which_fll >= FLL_NUM) + { + return; + } + + if (ret_state != 0U) + { + (void)pi_fll_get_frequency(which_fll, 1U); + return; + } + + reg1 = FLL_CTRL[which_fll].FLL_CONF1; + if (REG_GET(FLL_CTRL_CONF1_MODE, reg1) == 0U) + { + uint32_t reg2 = FLL_CTRL[which_fll].FLL_CONF2; + uint32_t regint = FLL_CTRL[which_fll].FLL_INTEGRATOR; + + reg2 &= ~FLL_CTRL_CONF2_ASSERT_CYCLES_MASK; + reg2 |= REG_SET(FLL_CTRL_CONF2_ASSERT_CYCLES, 0x6U); + reg2 &= ~FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK; + reg2 |= REG_SET(FLL_CTRL_CONF2_LOCK_TOLERANCE, 0x50U); + FLL_CTRL[which_fll].FLL_CONF2 = reg2; + + regint &= ~FLL_CTRL_INTEGRATOR_INT_PART_MASK; + regint |= REG_SET(FLL_CTRL_INTEGRATOR_INT_PART, 332U); + FLL_CTRL[which_fll].FLL_INTEGRATOR = regint; + + reg1 &= ~FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK; + reg1 |= REG_SET(FLL_CTRL_CONF1_OUTPUT_LOCK_EN, 1U); + reg1 &= ~FLL_CTRL_CONF1_MODE_MASK; + reg1 |= REG_SET(FLL_CTRL_CONF1_MODE, 1U); + FLL_CTRL[which_fll].FLL_CONF1 = reg1; + } + + if (flls_frequency[which_fll] != 0U) + { + (void)pi_fll_set_frequency(which_fll, flls_frequency[which_fll], 0); + } + else + { + flls_frequency[which_fll] = fll_get_frequency_from_mult_div( + REG_GET(FLL_CTRL_CONF1_MULTI_FACTOR, reg1), + REG_GET(FLL_CTRL_CONF1_CLK_OUT_DIV, reg1)); + } +} + +int pi_fll_get_frequency(fll_type_t which_fll, uint8_t real) +{ + if ((uint32_t)which_fll >= FLL_NUM) + { + return -1; + } + + if (real != 0U) + { + flls_frequency[which_fll] = fll_get_frequency_from_mult_div( + FLL_CTRL[which_fll].FLL_STATUS, + REG_GET(FLL_CTRL_CONF1_CLK_OUT_DIV, FLL_CTRL[which_fll].FLL_CONF1)); + } + + return (int)flls_frequency[which_fll]; +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/gpio.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/gpio.c new file mode 100644 index 000000000..ddeba5b5d --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/gpio.c @@ -0,0 +1,128 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include + +#include "pulp_mem_map.h" +#include "io.h" +#include "gpio.h" + +/* APB SOC CTRL pad-mux interface (apb_soc_ctrl v1.0.0): + * Each IO pad has a dedicated 32-bit register at base + 0x400 + pad_index*4. + * PWDATA[1:0] = mux function (0=sys, 1=perio, 2=apbio/GPIO, 3=fpgaio) + * PWDATA[13:8] = pad config (drive/pull, optional) + * + * FUNC_C (2) routes the pad to the GPIO (apbio) controller. + * For the standard GPIO pins: io_pad = gpio_pin + GPIO_IO_PAD_OFFSET (=7). + * Verified in pad_control.sv: apbio[N] ↔ io_pad[N+7] when pad_mux[N+7]==2. */ +#define APB_SOC_PADMUX_BASE 0x400U +#define PINMUX_FUNC_C 2U +#define GPIO_IO_PAD_OFFSET 7U + +static void gpio_pinmux_set_func_c(uint32_t pin_mask) +{ + for (uint32_t gpio_pin = 0U; gpio_pin < 32U; gpio_pin++) + { + if ((pin_mask & (1UL << gpio_pin)) == 0U) + { + continue; + } + uint32_t io_pad = gpio_pin + GPIO_IO_PAD_OFFSET; + uintptr_t reg = PULP_APB_SOC_CTRL_ADDR + APB_SOC_PADMUX_BASE + + io_pad * 4U; + writew(PINMUX_FUNC_C, reg); + } +} + +/* Iterate over every set bit in pin_mask and call writew(pin_number, addr). + * The apb_gpiov2 SETGPIO/CLRGPIO/TOGGPIO/SETDIR registers are all + * pin-indexed: the written word encodes a pin number, not a bitmask. */ +static void gpio_foreach_pin(uint32_t pin_mask, uintptr_t reg_addr, uint32_t extra_bits) +{ + for (uint32_t pin = 0U; pin < 32U; pin++) + { + if ((pin_mask & (1UL << pin)) != 0U) + { + writew(pin | extra_bits, reg_addr); + } + } +} + +void gpio_init(void) +{ + /* GPIO clocking is handled by platform boot code on CORE-V MCU. */ +} + +void gpio_set_output(uint32_t pin_mask) +{ + /* Route physical pads to the GPIO controller via the pad-mux (FUNC_C). */ + gpio_pinmux_set_func_c(pin_mask); + + /* Configure each pin as push-pull output via SETDIR. */ + gpio_foreach_pin(pin_mask, + (uintptr_t)(PULP_GPIO_ADDR + GPIO_SETDIR_OFFSET), + GPIO_DIR_OUTPUT); +} + +void gpio_toggle(uint32_t pin_mask) +{ + gpio_foreach_pin(pin_mask, + (uintptr_t)(PULP_GPIO_ADDR + GPIO_TOGGPIO_OFFSET), + 0U); +} + +void gpio_set(uint32_t pin_mask) +{ + gpio_foreach_pin(pin_mask, + (uintptr_t)(PULP_GPIO_ADDR + GPIO_SETGPIO_OFFSET), + 0U); +} + +void gpio_clear(uint32_t pin_mask) +{ + gpio_foreach_pin(pin_mask, + (uintptr_t)(PULP_GPIO_ADDR + GPIO_CLRGPIO_OFFSET), + 0U); +} + +void gpio_setpinmux(uint8_t io_pad, uint8_t mux) +{ + uintptr_t reg = PULP_APB_SOC_CTRL_ADDR + APB_SOC_PADMUX_BASE + + (uintptr_t)io_pad * 4U; + writew((uint32_t)mux & 0x3U, reg); +} + +uint8_t gpio_getpinmux(uint8_t io_pad) +{ + uintptr_t reg = PULP_APB_SOC_CTRL_ADDR + APB_SOC_PADMUX_BASE + + (uintptr_t)io_pad * 4U; + return (uint8_t)(readw(reg) & 0x3U); +} + +void gpio_pin_set_dir(uint8_t pin, uint8_t dir) +{ + uint32_t val = (uint32_t)pin; + if (dir != 0U) + { + val |= GPIO_DIR_OUTPUT; + } + writew(val, (uintptr_t)(PULP_GPIO_ADDR + GPIO_SETDIR_OFFSET)); +} + +uint32_t gpio_pin_read_status(uint8_t pin) +{ + writew((uint32_t)pin, (uintptr_t)(PULP_GPIO_ADDR + GPIO_SETSEL_OFFSET)); + return readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_RDSTAT_OFFSET)); +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/i2c_master.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/i2c_master.c new file mode 100644 index 000000000..eb1461b9a --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/i2c_master.c @@ -0,0 +1,153 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include +#include + +#include "bits.h" +#include "i2c_master.h" +#include "io.h" +#include "pulp_mem_map.h" + +#define UDMA_I2C_RX_SADDR_OFFSET 0x00U +#define UDMA_I2C_RX_SIZE_OFFSET 0x04U +#define UDMA_I2C_RX_CFG_OFFSET 0x08U +#define UDMA_I2C_TX_SADDR_OFFSET 0x10U +#define UDMA_I2C_TX_SIZE_OFFSET 0x14U +#define UDMA_I2C_TX_CFG_OFFSET 0x18U +#define UDMA_I2C_STATUS_OFFSET 0x20U +#define UDMA_I2C_SETUP_OFFSET 0x24U + +#define UDMA_CTRL_CG_OFFSET 0x00U +#define UDMA_CFG_EN_BIT BIT(4) +#define UDMA_CFG_PENDING_BIT BIT(5) +#define UDMA_I2C_STATUS_AL_BIT BIT(1) +#define UDMA_I2C_SETUP_RESET_BIT BIT(0) +#define I2C_MASTER_COUNT 2U +#define I2C_TIMEOUT_ITERATIONS 1000000U + +#define I2C_CMD_CFG 0xE0U +#define I2C_CMD_START 0x00U +#define I2C_CMD_STOP 0x20U +#define I2C_CMD_RD_ACK 0x40U +#define I2C_CMD_RD_NACK 0x60U +#define I2C_CMD_WR 0x80U +#define I2C_CMD_WAIT 0xA0U +#define I2C_CMD_RPT 0xC0U + +static uint8_t s_cmd_buf[32]; +static uint8_t s_clkdiv[I2C_MASTER_COUNT]; + +static uintptr_t i2c_master_base(uint8_t id) +{ + return (id == 0U) ? (uintptr_t)UDMA_CH_ADDR_I2CM0 : (uintptr_t)UDMA_CH_ADDR_I2CM1; +} + +int i2c_master_init(uint8_t id, uint32_t i2c_freq, uint32_t periph_freq) +{ + uint32_t cg; + uint32_t clk_div; + uintptr_t base; + + if ((id >= I2C_MASTER_COUNT) || (i2c_freq == 0U) || (periph_freq == 0U)) + { + return -1; + } + + cg = readw((uintptr_t)(UDMA_CH_ADDR_CTRL + UDMA_CTRL_CG_OFFSET)); + cg |= (id == 0U) ? UDMA_CTRL_I2CM0_CLKEN : UDMA_CTRL_I2CM1_CLKEN; + writew(cg, (uintptr_t)(UDMA_CH_ADDR_CTRL + UDMA_CTRL_CG_OFFSET)); + + clk_div = periph_freq / i2c_freq; + if (clk_div == 0U) + { + clk_div = 1U; + } + else if (clk_div > 255U) + { + clk_div = 255U; + } + s_clkdiv[id] = (uint8_t)clk_div; + + base = i2c_master_base(id); + writew(UDMA_I2C_SETUP_RESET_BIT, base + UDMA_I2C_SETUP_OFFSET); + writew(0U, base + UDMA_I2C_SETUP_OFFSET); + writew(0U, base + UDMA_I2C_RX_CFG_OFFSET); + writew(0U, base + UDMA_I2C_TX_CFG_OFFSET); + + return 0; +} + +int i2c_master_read_reg(uint8_t id, uint8_t dev_addr7, uint8_t reg_addr, + uint8_t *buf, uint8_t len) +{ + uintptr_t base; + uint32_t timeout; + uint32_t cmd_len; + uint32_t status; + + if ((id >= I2C_MASTER_COUNT) || (dev_addr7 > 0x7FU) || (buf == NULL) || (len == 0U)) + { + return -1; + } + + cmd_len = 0U; + s_cmd_buf[cmd_len++] = I2C_CMD_CFG; + s_cmd_buf[cmd_len++] = 0U; + s_cmd_buf[cmd_len++] = s_clkdiv[id]; + s_cmd_buf[cmd_len++] = I2C_CMD_START; + s_cmd_buf[cmd_len++] = I2C_CMD_WR; + s_cmd_buf[cmd_len++] = (uint8_t)(dev_addr7 << 1U); + s_cmd_buf[cmd_len++] = I2C_CMD_WR; + s_cmd_buf[cmd_len++] = reg_addr; + s_cmd_buf[cmd_len++] = I2C_CMD_START; + s_cmd_buf[cmd_len++] = I2C_CMD_WR; + s_cmd_buf[cmd_len++] = (uint8_t)((dev_addr7 << 1U) | 1U); + if (len > 1U) + { + s_cmd_buf[cmd_len++] = I2C_CMD_RPT; + s_cmd_buf[cmd_len++] = (uint8_t)(len - 1U); + s_cmd_buf[cmd_len++] = I2C_CMD_RD_ACK; + } + s_cmd_buf[cmd_len++] = I2C_CMD_RD_NACK; + s_cmd_buf[cmd_len++] = I2C_CMD_STOP; + s_cmd_buf[cmd_len++] = I2C_CMD_WAIT; + s_cmd_buf[cmd_len++] = 0U; + + base = i2c_master_base(id); + writew((uint32_t)(uintptr_t)buf, base + UDMA_I2C_RX_SADDR_OFFSET); + writew((uint32_t)len, base + UDMA_I2C_RX_SIZE_OFFSET); + writew(UDMA_CFG_EN_BIT, base + UDMA_I2C_RX_CFG_OFFSET); + + writew((uint32_t)(uintptr_t)s_cmd_buf, base + UDMA_I2C_TX_SADDR_OFFSET); + writew(cmd_len, base + UDMA_I2C_TX_SIZE_OFFSET); + writew(UDMA_CFG_EN_BIT, base + UDMA_I2C_TX_CFG_OFFSET); + + for (timeout = 0U; timeout < I2C_TIMEOUT_ITERATIONS; ++timeout) + { + status = readw(base + UDMA_I2C_STATUS_OFFSET); + if ((status & UDMA_I2C_STATUS_AL_BIT) != 0U) + { + return -1; + } + if (((readw(base + UDMA_I2C_TX_CFG_OFFSET) & UDMA_CFG_PENDING_BIT) == 0U) && + ((readw(base + UDMA_I2C_RX_CFG_OFFSET) & UDMA_CFG_PENDING_BIT) == 0U)) + { + return 0; + } + } + + return -1; +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/irq.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/irq.c new file mode 100644 index 000000000..cb79cc063 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/irq.c @@ -0,0 +1,50 @@ +/***************************************************************************/ +/* Copyright (C) 2019 ETH Zurich and University of Bologna + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#include + +#include "pulp_mem_map.h" +#include "io.h" +#include "irq.h" +#include "csr.h" + +void irq_mask(uint32_t mask) +{ + writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_OFFSET)); +} + +void irq_enable(uint32_t mask) +{ + writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_SET_OFFSET)); +} + +void irq_disable(uint32_t mask) +{ + writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_CLEAR_OFFSET)); +} + +uint32_t irq_clint_disable(void) +{ + return (uint32_t)csr_read_clear(CSR_MSTATUS, MSTATUS_IE); +} + +uint32_t irq_clint_enable(void) +{ + return (uint32_t)csr_read_set(CSR_MSTATUS, MSTATUS_IE); +} + +void pulp_irq_init(void) +{ + irq_disable(0xFFFFFFFFUL); +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/string.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/string.c new file mode 100644 index 000000000..7ff699e7f --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/string.c @@ -0,0 +1,64 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include +#include + +#include "string.h" + +void *memcpy(void *dest, const void *src, size_t n) +{ + size_t index; + uint8_t *dst = (uint8_t *)dest; + const uint8_t *source = (const uint8_t *)src; + + for (index = 0U; index < n; ++index) + { + dst[index] = source[index]; + } + + return dest; +} + +void *memset(void *dest, int c, size_t n) +{ + size_t index; + uint8_t *dst = (uint8_t *)dest; + uint8_t value = (uint8_t)c; + + for (index = 0U; index < n; ++index) + { + dst[index] = value; + } + + return dest; +} + +int memcmp(const void *lhs, const void *rhs, size_t n) +{ + size_t index; + const uint8_t *left = (const uint8_t *)lhs; + const uint8_t *right = (const uint8_t *)rhs; + + for (index = 0U; index < n; ++index) + { + if (left[index] != right[index]) + { + return (left[index] < right[index]) ? -1 : 1; + } + } + + return 0; +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/system_core_v_mcu.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/system_core_v_mcu.c new file mode 100644 index 000000000..f142c95d0 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/system_core_v_mcu.c @@ -0,0 +1,132 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include +#include + +#include "csr.h" +#include "fll.h" +#include "gpio.h" +#include "irq.h" +#include "properties.h" +#include "system_core_v_mcu.h" +#include "timer_irq.h" +#include "tx_api.h" +#include "uart_driver.h" + +extern void _tx_timer_interrupt(void); + +volatile uint32_t system_core_clock = DEFAULT_SYSTEM_CLOCK; +volatile uint32_t last_trap_mcause; +void (*isr_table[32])(void); + +static uint32_t uart_console_ready; + +static void uart_write_hex32(uint32_t value) +{ + static const char hex[] = "0123456789ABCDEF"; + int shift; + + uart_write_str(0U, "0x"); + for (shift = 28; shift >= 0; shift -= 4) + { + uart_write_byte(0U, (uint8_t)hex[(value >> (uint32_t)shift) & 0xFU]); + } +} + +void tx_undefined_irq_handler(void) +{ + if (uart_console_ready != 0U) + { + uart_write_str(0U, "\r\nUndefined IRQ\r\n"); + } + + /* MISRA deviation: intentional infinite loop used as a fault sink. */ + for (;;) + { + } +} + +void tx_timer_irq_handler(void) +{ + _tx_timer_interrupt(); +} + +void system_init(void) +{ + uint32_t i; + + for (i = 0U; i < 32U; ++i) + { + isr_table[i] = tx_undefined_irq_handler; + } + + isr_table[7U] = tx_timer_irq_handler; + + for (i = 0U; i < ARCHI_NB_FLL; ++i) + { + pi_fll_init((fll_type_t)i, 0U); + } + + pulp_irq_init(); + (void)timer_irq_init(ARCHI_SOC_FREQUENCY / (uint32_t)TX_TIMER_TICKS_PER_SECOND); + /* CV32E40P routes the FC Timer LO to irq_i[7] (MTI, bit 7), which maps + * to mip[7]. IRQ_MASK in cv32e40p_cs_registers forces mie[10] to zero, + * so bit 7 is the correct enable bit. mcause will be 0x80000007. */ + (void)csr_read_set(CSR_MIE, BIT(7)); + + gpio_init(); + if (uart_init(0U, 115200U, ARCHI_FPGA_FREQUENCY) == 0) + { + uart_console_ready = 1U; + } +} + +void tx_trap_handler(uint32_t mcause, uint32_t mepc, uint32_t mtval) +{ + last_trap_mcause = mcause; + + if ((mcause & 0x80000000UL) != 0UL) + { + uint32_t irq_id = mcause & 0x1FUL; + + if (isr_table[irq_id] != NULL) + { + isr_table[irq_id](); + } + else + { + tx_undefined_irq_handler(); + } + } + else + { + if (uart_console_ready != 0U) + { + uart_write_str(0U, "\r\nTrap mcause="); + uart_write_hex32(mcause); + uart_write_str(0U, " mepc="); + uart_write_hex32(mepc); + uart_write_str(0U, " mtval="); + uart_write_hex32(mtval); + uart_write_str(0U, "\r\n"); + } + + /* MISRA deviation: intentional infinite loop used as a fault sink. */ + for (;;) + { + } + } +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/temp_sensor.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/temp_sensor.c new file mode 100644 index 000000000..6d70e9431 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/temp_sensor.c @@ -0,0 +1,46 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include + +#include "i2c_master.h" +#include "properties.h" +#include "temp_sensor.h" + +#define ADT7420_I2C_ID 1U +#define ADT7420_ADDR7 0x4BU +#define ADT7420_TEMP_REG 0x00U +#define ADT7420_I2C_FREQ_HZ 200000U + +void temp_sensor_init(void) +{ + (void)i2c_master_init(ADT7420_I2C_ID, ADT7420_I2C_FREQ_HZ, ARCHI_FPGA_FREQUENCY); +} + +int16_t temp_read_celsius_x10(void) +{ + uint8_t buf[2]; + int16_t raw; + int16_t value; + + if (i2c_master_read_reg(ADT7420_I2C_ID, ADT7420_ADDR7, ADT7420_TEMP_REG, &buf[0], 2U) != 0) + { + return INT16_MIN; + } + + raw = (int16_t)(((uint16_t)buf[0] << 8U) | (uint16_t)buf[1]); + value = (int16_t)(raw >> 3); + return (int16_t)(((int32_t)value * 5) / 8); +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/timer_irq.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/timer_irq.c new file mode 100644 index 000000000..9a085d9f4 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/timer_irq.c @@ -0,0 +1,58 @@ +/***************************************************************************/ +/* Copyright (C) 2019 ETH Zurich and University of Bologna + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#include + +#include "pulp_mem_map.h" +#include "io.h" +#include "timer.h" +#include "timer_irq.h" + +static uint32_t last_count; + +int timer_irq_init(uint32_t ticks) +{ + (void)timer_irq_set_timeout(ticks); + + writew(TIMER_CFG_LO_ENABLE_MASK | + TIMER_CFG_LO_RESET_MASK | + TIMER_CFG_LO_MODE_MASK | + TIMER_CFG_LO_IRQEN_MASK, + (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_LO_OFFSET)); + + last_count = 0U; + return 0; +} + +int timer_irq_set_timeout(uint32_t ticks) +{ + writew(1U, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_RESET_LO_OFFSET)); + writew(ticks, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CMP_LO_OFFSET)); + last_count = 0U; + return 0; +} + +uint32_t timer_irq_clock_elapsed(void) +{ + uint32_t current = timer_irq_cycle_get_32(); + uint32_t elapsed = current - last_count; + + last_count = current; + return elapsed; +} + +uint32_t timer_irq_cycle_get_32(void) +{ + return readw((uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CNT_LO_OFFSET)); +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/uart_driver.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/uart_driver.c new file mode 100644 index 000000000..33b1ff150 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/uart_driver.c @@ -0,0 +1,169 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include +#include + +#include "bits.h" +#include "io.h" +#include "pulp_mem_map.h" +#include "uart_driver.h" + +#define UDMA_CTRL_CG_OFFSET 0x00U +#define UDMA_CTRL_UART0_CLKEN BIT(0) + +#define UDMA_UART_RX_SADDR_OFFSET 0x00U +#define UDMA_UART_RX_SIZE_OFFSET 0x04U +#define UDMA_UART_RX_CFG_OFFSET 0x08U +#define UDMA_UART_TX_SADDR_OFFSET 0x10U +#define UDMA_UART_TX_SIZE_OFFSET 0x14U +#define UDMA_UART_TX_CFG_OFFSET 0x18U +#define UDMA_UART_STATUS_OFFSET 0x20U +#define UDMA_UART_SETUP_OFFSET 0x24U +#define UDMA_UART_VALID_OFFSET 0x30U +#define UDMA_UART_DATA_OFFSET 0x34U + +#define UDMA_CFG_EN_BIT BIT(4) +/* EN (bit 4) only; DATASIZE=0 for 8-bit transfers; 0x12 would set DATASIZE=1 + * (16-bit) and cause the EN bit to never clear for single-byte buffers. */ +#define UDMA_UART_TX_CFG_ENABLE 0x10U +#define UDMA_UART_WORDLEN_8_BITS 3U +#define UDMA_UART_TX_ENABLE_BIT BIT(8) +#define UDMA_UART_RX_ENABLE_BIT BIT(9) +#define UDMA_UART_RX_POLLING_BIT BIT(4) +#define UDMA_UART_RX_CLEAN_BIT BIT(5) +#define UDMA_UART_DIV_SHIFT 16U +#define UDMA_UART_VALID_DATA_BIT BIT(0) +#define UDMA_UART_STATUS_TX_BUSY BIT(0) +#define UDMA_UART_MAX_TRANSFER 0xFFFFU + +static uint8_t uart_tx_byte[N_UART]; + +static uintptr_t uart_base(uint8_t uart_id) +{ + return (uintptr_t)(UDMA_CH_ADDR_UART + ((uintptr_t)uart_id * (uintptr_t)UDMA_CH_SIZE)); +} + +int uart_init(uint8_t uart_id, uint32_t baudrate, uint32_t periph_freq) +{ + uint32_t clk_div; + uint32_t setup; + uint32_t cg; + + if ((uart_id >= N_UART) || (baudrate == 0U) || (periph_freq == 0U)) + { + return -1; + } + + cg = readw((uintptr_t)(UDMA_CH_ADDR_CTRL + UDMA_CTRL_CG_OFFSET)); + cg |= (uint32_t)(UDMA_CTRL_UART0_CLKEN << uart_id); + writew(cg, (uintptr_t)(UDMA_CH_ADDR_CTRL + UDMA_CTRL_CG_OFFSET)); + + clk_div = periph_freq / baudrate; + if (clk_div == 0U) + { + clk_div = 1U; + } + + setup = (clk_div << UDMA_UART_DIV_SHIFT) | + UDMA_UART_TX_ENABLE_BIT | + UDMA_UART_RX_ENABLE_BIT | + UDMA_UART_RX_POLLING_BIT | + UDMA_UART_RX_CLEAN_BIT | + (UDMA_UART_WORDLEN_8_BITS << 1U); + writew(setup, uart_base(uart_id) + UDMA_UART_SETUP_OFFSET); + + writew(0U, uart_base(uart_id) + UDMA_UART_RX_SADDR_OFFSET); + writew(0U, uart_base(uart_id) + UDMA_UART_RX_SIZE_OFFSET); + writew(0U, uart_base(uart_id) + UDMA_UART_RX_CFG_OFFSET); + + return 0; +} + +void uart_write_byte(uint8_t uart_id, uint8_t c) +{ + if (uart_id >= N_UART) + { + return; + } + + uart_tx_byte[uart_id] = c; + uart_write_buf(uart_id, &uart_tx_byte[uart_id], 1U); +} + +int uart_read_byte(uint8_t uart_id) +{ + if (uart_id >= N_UART) + { + return -1; + } + + if ((readw(uart_base(uart_id) + UDMA_UART_VALID_OFFSET) & UDMA_UART_VALID_DATA_BIT) == 0U) + { + return -1; + } + + return (int)(readw(uart_base(uart_id) + UDMA_UART_DATA_OFFSET) & 0xFFU); +} + +void uart_write_str(uint8_t uart_id, const char *str) +{ + if (str == NULL) + { + return; + } + + while (*str != '\0') + { + uart_write_byte(uart_id, (uint8_t)*str); + ++str; + } +} + +void uart_write_buf(uint8_t uart_id, const uint8_t *buf, uint32_t len) +{ + uintptr_t base_addr; + const uint8_t *current; + uint32_t remaining; + + if ((uart_id >= N_UART) || (buf == NULL) || (len == 0U)) + { + return; + } + + base_addr = uart_base(uart_id); + current = buf; + remaining = len; + + while (remaining > 0U) + { + uint32_t chunk = (remaining > UDMA_UART_MAX_TRANSFER) ? UDMA_UART_MAX_TRANSFER : remaining; + + while ((readw(base_addr + UDMA_UART_STATUS_OFFSET) & UDMA_UART_STATUS_TX_BUSY) != 0U) + { + } + + writew((uint32_t)(uintptr_t)current, base_addr + UDMA_UART_TX_SADDR_OFFSET); + writew(chunk, base_addr + UDMA_UART_TX_SIZE_OFFSET); + writew(UDMA_UART_TX_CFG_ENABLE, base_addr + UDMA_UART_TX_CFG_OFFSET); + + while ((readw(base_addr + UDMA_UART_TX_CFG_OFFSET) & UDMA_CFG_EN_BIT) != 0U) + { + } + + current += chunk; + remaining -= chunk; + } +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh b/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh new file mode 100755 index 000000000..fe78a8e64 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh @@ -0,0 +1,9 @@ +#!/bin/bash +set -e +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +THREADX_ROOT="${SCRIPT_DIR}/../../../../.." +cmake -B "${SCRIPT_DIR}/build" \ + -G Ninja \ + -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv64-gcc-rv32imc.cmake" \ + "${SCRIPT_DIR}" +cmake --build "${SCRIPT_DIR}/build" diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/crt0.S b/ports/risc-v32/gnu/example_build/core_v_mcu/crt0.S new file mode 100644 index 000000000..3c761bbe5 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/crt0.S @@ -0,0 +1,48 @@ +/***************************************************************************/ +/* Copyright 2020 ETH Zurich + * Copyright (c) 2017 SiFive Inc. All rights reserved. + * Copyright (c) 2019 ETH Zürich and University of Bologna + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0 (Apache-2.0) + * or the BSD 2-Clause License (BSD-2-Clause) at your option. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: (Apache-2.0 OR BSD-2-Clause) AND MIT + ***************************************************************************/ + + .section .text.start + .global _start + .type _start, @function + +_start: + .option push + .option norelax +1: auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + la sp, __stack_top + + la a0, __vector_start + ori a0, a0, 1 + csrw mtvec, a0 + + la t0, __bss_start + la t1, __bss_end +2: + bgeu t0, t1, 3f + sw zero, 0(t0) + addi t0, t0, 4 + j 2b +3: + call main +4: + wfi + j 4b + + .size _start, .-_start diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/demo_threadx.c b/ports/risc-v32/gnu/example_build/core_v_mcu/demo_threadx.c new file mode 100644 index 000000000..c7daac3c4 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/demo_threadx.c @@ -0,0 +1,134 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include + +#include "gpio.h" +#include "system_core_v_mcu.h" +#include "tx_api.h" +#include "uart_driver.h" + +#define DEMO_STACK_SIZE 1024U +#define DEMO_BYTE_POOL_SIZE 4096U +/* + * LED[0] on Nexys A7 = IO pad 11 = GPIO/apbio pin 4 (MUX=2). + * Verified in the quick-start guide and the 2022 nexys-pin-table.csv used to + * synthesise the pre-built bitfile (io_pad = gpio_pin + 7). + */ +#define DEMO_LED_PIN 4U +#define DEMO_LED_MASK (1UL << DEMO_LED_PIN) + +/* Assemble the version banner string at compile time from tx_api.h constants. */ +#define _TX_STR(x) #x +#define TX_STR(x) _TX_STR(x) +#define TX_VERSION_STRING \ + "v" TX_STR(THREADX_MAJOR_VERSION) \ + "." TX_STR(THREADX_MINOR_VERSION) \ + "." TX_STR(THREADX_PATCH_VERSION) \ + "." TX_STR(THREADX_BUILD_VERSION) + +static const char banner[] = + "\r\nEclipse ThreadX for OpenHW CORE-V MCU " TX_VERSION_STRING "\r\n" + "Copyright (c) 2026 Eclipse ThreadX Contributors\r\n\r\n"; + +static TX_THREAD blinky_thread; +static TX_THREAD uart_thread; +static TX_BYTE_POOL byte_pool; +static uint8_t memory_area[DEMO_BYTE_POOL_SIZE]; + +static void demo_error_loop(void) +{ + /* MISRA deviation: intentional infinite loop used as a fault sink. */ + for (;;) + { + } +} + +static void blinky_thread_entry(ULONG arg) +{ + TX_PARAMETER_NOT_USED(arg); + + /* Configure LED[0] as push-pull output (sets pad-mux to FUNC_C = 2). */ + gpio_set_output((uint32_t)DEMO_LED_MASK); + + for (;;) + { + gpio_set((uint32_t)DEMO_LED_MASK); + tx_thread_sleep(100U); /* 1 s on (100 ticks × 10 ms) */ + gpio_clear((uint32_t)DEMO_LED_MASK); + tx_thread_sleep(100U); /* 1 s off */ + } +} + +static void uart_thread_entry(ULONG arg) +{ + TX_PARAMETER_NOT_USED(arg); + + uart_write_str(0U, banner); + for (;;) + { + uart_write_str(0U, "."); + tx_thread_sleep(100U); + } +} + +void tx_application_define(void *first_unused_memory) +{ + CHAR *stack_ptr = TX_NULL; + UINT status; + + TX_PARAMETER_NOT_USED(first_unused_memory); + + status = tx_byte_pool_create(&byte_pool, "demo pool", memory_area, DEMO_BYTE_POOL_SIZE); + if (status != TX_SUCCESS) + { + demo_error_loop(); + } + + status = tx_byte_allocate(&byte_pool, (VOID **)&stack_ptr, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + demo_error_loop(); + } + + status = tx_thread_create(&blinky_thread, "blinky", blinky_thread_entry, 0U, + stack_ptr, DEMO_STACK_SIZE, 1U, 1U, + TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + demo_error_loop(); + } + + status = tx_byte_allocate(&byte_pool, (VOID **)&stack_ptr, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + demo_error_loop(); + } + + status = tx_thread_create(&uart_thread, "uart", uart_thread_entry, 0U, + stack_ptr, DEMO_STACK_SIZE, 2U, 2U, + TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + demo_error_loop(); + } +} + +int main(void) +{ + system_init(); + tx_kernel_enter(); + return 0; +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/deploy.sh b/ports/risc-v32/gnu/example_build/core_v_mcu/deploy.sh new file mode 100755 index 000000000..2e22ec1e9 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/deploy.sh @@ -0,0 +1,142 @@ +#!/usr/bin/env bash +# /***************************************************************************/ +# /* Copyright (C) 2026 Eclipse ThreadX contributors +# * +# * This program and the accompanying materials are made available under the +# * terms of the MIT License which is available at +# * https://opensource.org/licenses/MIT. +# * +# * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). +# * The AI-generated portions may be considered public domain (CC0-1.0) +# * and not subject to the project's licence. +# * +# * SPDX-License-Identifier: MIT AND CC0-1.0 +# ***************************************************************************/ + +# deploy.sh -- build (optionally), flash, and run/debug the CORE-V MCU target +# via the Ashling Opella LD debug probe. +# +# Usage: +# bash deploy.sh [options] +# +# Options: +# --build Run build.sh before flashing (default: skip). +# --debug After loading, stop at main and leave GDB attached +# (default: run free and exit GDB). +# --elf Override the ELF to flash +# (default: build/demo_threadx.elf). +# --openocd-cfg

Override the OpenOCD config file. +# +# Prerequisites: +# * riscv64-unknown-elf-gdb and openocd must be on PATH. +# * Run setup_opella.sh once to configure udev rules. +# * The Nexys A7 board must be powered on. + +set -euo pipefail + +SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +# Prefer a bare-metal RISC-V GDB; fall back to gdb-multiarch (Ubuntu apt default) +if command -v riscv64-unknown-elf-gdb >/dev/null 2>&1; then + GDB="riscv64-unknown-elf-gdb" +elif command -v gdb-multiarch >/dev/null 2>&1; then + GDB="gdb-multiarch" +else + GDB="riscv64-unknown-elf-gdb" # will produce a clear error below +fi +OPENOCD_LOG="/tmp/openocd_demo_threadx.log" +OPENOCD_PID="" +OPENOCD_TIMEOUT=10 + +DEFAULT_ELF="${SCRIPT_DIR}/build/demo_threadx.elf" +DEFAULT_CFG="${SCRIPT_DIR}/openocd-nexys-Ashling-Opella-LD.cfg" + +OPT_BUILD=0 +OPT_DEBUG=0 +OPT_ELF="" +OPT_CFG="" + +usage() { grep '^# ' "$0" | sed 's/^# //' | head -30; exit 0; } + +while [[ $# -gt 0 ]]; do + case "$1" in + --build) OPT_BUILD=1; shift ;; + --debug) OPT_DEBUG=1; shift ;; + --elf) OPT_ELF="$2"; shift 2 ;; + --openocd-cfg) OPT_CFG="$2"; shift 2 ;; + -h|--help) usage ;; + *) echo "[ERROR] Unknown option: $1" >&2; usage ;; + esac +done + +ELF="${OPT_ELF:-${DEFAULT_ELF}}" +CFG="${OPT_CFG:-${DEFAULT_CFG}}" + +info() { echo "[INFO] $*"; } +die() { echo "[ERROR] $*" >&2; exit 1; } + +stop_openocd() { + if [ -n "${OPENOCD_PID}" ] && kill -0 "${OPENOCD_PID}" 2>/dev/null; then + info "Stopping OpenOCD (PID ${OPENOCD_PID}) ..." + kill "${OPENOCD_PID}" 2>/dev/null || true + wait "${OPENOCD_PID}" 2>/dev/null || true + fi +} + +trap stop_openocd EXIT INT TERM + +if [ "${OPT_BUILD}" -eq 1 ]; then + info "Running build.sh ..." + bash "${SCRIPT_DIR}/build.sh" +fi + +[ -f "${ELF}" ] || die "ELF not found: ${ELF} (run with --build to build first)" +[ -f "${CFG}" ] || die "OpenOCD config not found: ${CFG}" +command -v openocd >/dev/null 2>&1 || die "openocd not found on PATH" +command -v "${GDB}" >/dev/null 2>&1 || die "${GDB} not found on PATH" + +info "Starting OpenOCD with config: ${CFG}" +info "Log: ${OPENOCD_LOG}" +openocd -f "${CFG}" >"${OPENOCD_LOG}" 2>&1 & +OPENOCD_PID=$! + +info "Waiting for OpenOCD to be ready (up to ${OPENOCD_TIMEOUT}s) ..." +ELAPSED=0 +while ! grep -q "Ready for Remote Connections" "${OPENOCD_LOG}" 2>/dev/null; do + sleep 1 + ELAPSED=$((ELAPSED + 1)) + if [ "${ELAPSED}" -ge "${OPENOCD_TIMEOUT}" ]; then + echo "--- OpenOCD log ---" && cat "${OPENOCD_LOG}" + die "OpenOCD did not become ready within ${OPENOCD_TIMEOUT}s" + fi + if ! kill -0 "${OPENOCD_PID}" 2>/dev/null; then + echo "--- OpenOCD log ---" && cat "${OPENOCD_LOG}" + die "OpenOCD exited unexpectedly" + fi +done +info "OpenOCD is ready." + +GDB_INIT_FILE="/tmp/gdb_deploy_demo_threadx.gdb" +printf 'set confirm off +set remotetimeout 60 +file %s +target extended-remote localhost:3333 +load +' "${ELF}" > "${GDB_INIT_FILE}" + +if [ "${OPT_DEBUG}" -eq 0 ]; then + info "Flashing and running (detached) ..." + printf 'monitor resume\ndisconnect\nquit\n' >> "${GDB_INIT_FILE}" + info "ELF: ${ELF}" + riscv64-unknown-elf-size "${ELF}" + "${GDB}" --batch --command="${GDB_INIT_FILE}" 2>&1 \ + | grep -v "keep_alive() was not invoked" \ + | grep -v "GDB alive packet not sent" + info "Flash complete. Application is running on the target." + info "Serial console: minicom -b 115200 -D /dev/ttyUSBx" +else + info "Flashing and stopping at main for interactive debug ..." + printf 'break main\ncontinue\n' >> "${GDB_INIT_FILE}" + info "ELF: ${ELF}" + riscv64-unknown-elf-size "${ELF}" + "${GDB}" --command="${GDB_INIT_FILE}" +fi diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/gdb_init b/ports/risc-v32/gnu/example_build/core_v_mcu/gdb_init new file mode 100644 index 000000000..718a20f19 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/gdb_init @@ -0,0 +1,6 @@ +set arch riscv:rv32 +target extended-remote localhost:3333 +file build/demo_threadx.elf +load +break main +continue diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/bits.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/bits.h new file mode 100644 index 000000000..08871387a --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/bits.h @@ -0,0 +1,59 @@ +/***************************************************************************/ +/* Copyright (c) 2011-2014, Wind River Systems, Inc. + * Copyright 2020 ETH Zurich + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#ifndef BITS_H +#define BITS_H + +#include +#include + +/* Helper to pass an integer as a pointer or vice versa. */ +#define POINTER_TO_UINT(x) ((uintptr_t)(x)) +#define UINT_TO_POINTER(x) ((void *)(uintptr_t)(x)) +#define POINTER_TO_INT(x) ((intptr_t)(x)) +#define INT_TO_POINTER(x) ((void *)(intptr_t)(x)) + +#if !(defined(__CHAR_BIT__) && defined(__SIZEOF_LONG__)) +#error Missing required predefined macros for BITS_PER_LONG calculation +#endif + +#define BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__) +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1UL) & (~0UL >> (BITS_PER_LONG - 1UL - (h)))) + +#define KB(x) ((x) << 10) +#define MB(x) (KB(x) << 10) +#define GB(x) (MB(x) << 10) + +#define KHZ(x) ((x) * 1000) +#define MHZ(x) (KHZ(x) * 1000) + +#ifndef BIT +#ifdef _ASMLANGUAGE +#define BIT(n) (1 << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif +#endif + +#define WRITE_BIT(var, bit, set) \ + ((var) = ((set) != 0) ? ((var) | BIT(bit)) : ((var) & ~BIT(bit))) + +#define BIT_MASK(n) (BIT(n) - 1UL) + +#define REG_SET(FIELD, v) (((uint32_t)(v) << FIELD##_SHIFT) & FIELD##_MASK) +#define REG_GET(FIELD, v) (((uint32_t)(v) & FIELD##_MASK) >> FIELD##_SHIFT) + +#endif /* BITS_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/csr.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/csr.h new file mode 100644 index 000000000..69c7763e9 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/csr.h @@ -0,0 +1,75 @@ +/***************************************************************************/ +/* Copyright (C) 2020 ETH Zurich and University of Bologna + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#ifndef CSR_H +#define CSR_H + +#include "bits.h" + +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3A0 +#define CSR_PMPADDR0 0x3B0 +#define CSR_MVENDORID 0xF11 +#define CSR_MARCHID 0xF12 +#define CSR_MIMPID 0xF13 +#define CSR_MHARTID 0xF14 + +#define MSTATUS_IE BIT(3) + +#define __CSR_EXPAND(x) #x + +#ifndef csr_read +#define csr_read(csr) \ + ({ \ + register unsigned long __val; \ + __asm__ volatile("csrr %0, " __CSR_EXPAND(csr) : "=r"(__val) : : "memory"); \ + __val; \ + }) +#endif + +#ifndef csr_write +#define csr_write(csr, val) \ + ({ \ + unsigned long __val = (unsigned long)(val); \ + __asm__ volatile("csrw " __CSR_EXPAND(csr) ", %0" : : "rK"(__val) : "memory"); \ + }) +#endif + +#ifndef csr_read_clear +#define csr_read_clear(csr, val) \ + ({ \ + unsigned long __val = (unsigned long)(val); \ + __asm__ volatile("csrrc %0, " __CSR_EXPAND(csr) ", %1" : "=r"(__val) : "rK"(__val) : "memory"); \ + __val; \ + }) +#endif + +#ifndef csr_read_set +#define csr_read_set(csr, val) \ + ({ \ + unsigned long __val = (unsigned long)(val); \ + __asm__ volatile("csrrs %0, " __CSR_EXPAND(csr) ", %1" : "=r"(__val) : "rK"(__val) : "memory"); \ + __val; \ + }) +#endif + +#endif /* CSR_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/fll.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/fll.h new file mode 100644 index 000000000..011268df0 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/fll.h @@ -0,0 +1,93 @@ +/***************************************************************************/ +/* Copyright 2020 GreenWaves Technologies + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#ifndef FLL_H +#define FLL_H + +#include + +#include "properties.h" +#include "pulp_mem_map.h" + +#define FLL_STATUS_OFFSET 0x000U +#define FLL_CONF1_OFFSET 0x004U +#define FLL_CONF2_OFFSET 0x008U +#define FLL_INTEGRATOR_OFFSET 0x00CU + +typedef struct +{ + volatile uint32_t FLL_STATUS; + volatile uint32_t FLL_CONF1; + volatile uint32_t FLL_CONF2; + volatile uint32_t FLL_INTEGRATOR; +} fll_ctrl_t; + +typedef enum _fll_type +{ + FLL_SOC = 0, + FLL_PERI = 1, + FLL_CLUSTER = 2 +} fll_type_t; + +typedef enum +{ + PI_FREQ_DOMAIN_FC = 0, + PI_FREQ_DOMAIN_CL = 1, + PI_FREQ_DOMAIN_PERIPH = 2 +} pi_freq_domain_e; + +#define FLL_CTRL_STATUS_MULTI_FACTOR_MASK 0xFFFFU +#define FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT 0U +#define FLL_CTRL_CONF1_MULTI_FACTOR_MASK 0xFFFFU +#define FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT 0U +#define FLL_CTRL_CONF1_DCO_INPUT_MASK 0x03FF0000U +#define FLL_CTRL_CONF1_DCO_INPUT_SHIFT 16U +#define FLL_CTRL_CONF1_CLK_OUT_DIV_MASK 0x3C000000U +#define FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT 26U +#define FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK 0x40000000U +#define FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT 30U +#define FLL_CTRL_CONF1_MODE_MASK 0x80000000U +#define FLL_CTRL_CONF1_MODE_SHIFT 31U +#define FLL_CTRL_CONF2_LOOPGAIN_MASK 0xFU +#define FLL_CTRL_CONF2_LOOPGAIN_SHIFT 0U +#define FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK 0x3F0U +#define FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT 4U +#define FLL_CTRL_CONF2_ASSERT_CYCLES_MASK 0xFC00U +#define FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT 10U +#define FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK 0x0FFF0000U +#define FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT 16U +#define FLL_CTRL_CONF2_CONF_CLK_SEL_MASK 0x20000000U +#define FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT 29U +#define FLL_CTRL_CONF2_OPEN_LOOP_MASK 0x40000000U +#define FLL_CTRL_CONF2_OPEN_LOOP_SHIFT 30U +#define FLL_CTRL_CONF2_DITHERING_MASK 0x80000000U +#define FLL_CTRL_CONF2_DITHERING_SHIFT 31U +#define FLL_CTRL_INTEGRATOR_FRACT_PART_MASK 0x0000FFC0U +#define FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT 6U +#define FLL_CTRL_INTEGRATOR_INT_PART_MASK 0x03FF0000U +#define FLL_CTRL_INTEGRATOR_INT_PART_SHIFT 16U +#define FLL_CTRL_SOC_FLL_CONV_MASK 0x1U +#define FLL_CTRL_SOC_FLL_CONV_SHIFT 0U +#define FLL_CTRL_CLUSTER_FLL_CONV_MASK 0x2U +#define FLL_CTRL_CLUSTER_FLL_CONV_SHIFT 1U + +#define FLL_NUM ARCHI_NB_FLL +#define FLL_REF_CLK ARCHI_REF_CLOCK +#define FLL_CTRL ((volatile fll_ctrl_t *)PULP_FLL_ADDR) + +void pi_fll_init(fll_type_t which_fll, uint32_t ret_state); +int pi_fll_set_frequency(fll_type_t which_fll, uint32_t frequency, int check); +int pi_fll_get_frequency(fll_type_t which_fll, uint8_t real); + +#endif /* FLL_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/gpio.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/gpio.h new file mode 100644 index 000000000..da5f60087 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/gpio.h @@ -0,0 +1,68 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef GPIO_H +#define GPIO_H + +#include + +/* apb_gpiov2 register map (pin-indexed interface) + * + * Offset Name Access Description + * 0x000 SETGPIO W PWDATA[6:0] = pin number → drive pin high + * 0x004 CLRGPIO W PWDATA[6:0] = pin number → drive pin low + * 0x008 TOGGPIO W PWDATA[6:0] = pin number → toggle pin + * 0x010 PIN0 R bits [31:0] = sampled input state of pins 0-31 + * 0x020 OUT0 R/W bits [31:0] = output state bitmask, pins 0-31 + * 0x030 SETSEL W select pin for RDSTAT + * 0x034 RDSTAT R status of selected pin + * 0x038 SETDIR W PWDATA[6:0]=pin, PWDATA[25:24]=dir + * dir[0]=1 → push-pull output; dir[1]=1 → open-drain + * 0x03C SETINT W interrupt configuration + * 0x040 INTACK W interrupt acknowledge + */ +#define GPIO_SETGPIO_OFFSET 0x000U +#define GPIO_CLRGPIO_OFFSET 0x004U +#define GPIO_TOGGPIO_OFFSET 0x008U +#define GPIO_PIN0_OFFSET 0x010U +#define GPIO_OUT0_OFFSET 0x020U +#define GPIO_SETSEL_OFFSET 0x030U +#define GPIO_RDSTAT_OFFSET 0x034U +#define GPIO_SETDIR_OFFSET 0x038U +#define GPIO_SETINT_OFFSET 0x03CU +#define GPIO_INTACK_OFFSET 0x040U + +/* Direction field in SETDIR: bits [25:24] of the written word. + * 0b01 = push-pull output enable; 0b10 = open-drain; 0b00 = input */ +#define GPIO_DIR_OUTPUT (1U << 24U) + +void gpio_init(void); +void gpio_set_output(uint32_t pin_mask); +void gpio_toggle(uint32_t pin_mask); +void gpio_set(uint32_t pin_mask); +void gpio_clear(uint32_t pin_mask); + +/* Pad-mux control (APB SOC CTRL v1.0.0). + * Each IO pad has a 32-bit register at SOC_CTRL_BASE + 0x400 + pad*4. + * bits[1:0] = mux function: 0=sys, 1=perio, 2=apbio/GPIO, 3=fpgaio. */ +void gpio_setpinmux(uint8_t io_pad, uint8_t mux); +uint8_t gpio_getpinmux(uint8_t io_pad); + +/* Single-pin direction and status (for CLI use). + * dir: 0 = input, 1 = push-pull output. */ +void gpio_pin_set_dir(uint8_t pin, uint8_t dir); +uint32_t gpio_pin_read_status(uint8_t pin); + +#endif /* GPIO_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/i2c_master.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/i2c_master.h new file mode 100644 index 000000000..4a478b302 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/i2c_master.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef I2C_MASTER_H +#define I2C_MASTER_H + +#include + +/* i2c_master_init: enable I2C channel clock gate, configure clock divider. + * id: 0 or 1 (I2CM0 or I2CM1) + * i2c_freq: desired I2C clock in Hz (e.g. 200000) + * periph_freq: UDMA peripheral clock in Hz (5000000 on CORE-V FPGA) + * Returns 0 on success, -1 on bad params. */ +int i2c_master_init(uint8_t id, uint32_t i2c_freq, uint32_t periph_freq); + +/* i2c_master_read_reg: read len bytes from register reg_addr of 7-bit addressed device. + * id: I2CM channel (0 or 1) + * dev_addr7: 7-bit I2C device address + * reg_addr: register address to read from + * buf: output buffer (must be in RAM, not stack if possible) + * len: number of bytes to read (1..255) + * Returns 0 on success, -1 on timeout or arbitration loss. */ +int i2c_master_read_reg(uint8_t id, uint8_t dev_addr7, uint8_t reg_addr, + uint8_t *buf, uint8_t len); + +#endif /* I2C_MASTER_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/io.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/io.h new file mode 100644 index 000000000..02364544f --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/io.h @@ -0,0 +1,61 @@ +/***************************************************************************/ +/* Copyright 2020 ETH Zurich + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#ifndef IO_H +#define IO_H + +#include + +#ifndef CORE_V_MCU_MMIO_MOCK +static inline void writeb(uint8_t val, uintptr_t addr) +{ + __asm__ volatile("sb %0, 0(%1)" : : "r"(val), "r"((volatile uint8_t *)addr)); +} + +static inline void writeh(uint16_t val, uintptr_t addr) +{ + __asm__ volatile("sh %0, 0(%1)" : : "r"(val), "r"((volatile uint16_t *)addr)); +} + +static inline void writew(uint32_t val, uintptr_t addr) +{ + __asm__ volatile("sw %0, 0(%1)" : : "r"(val), "r"((volatile uint32_t *)addr)); +} + +static inline uint8_t readb(const uintptr_t addr) +{ + uint8_t val; + + __asm__ volatile("lb %0, 0(%1)" : "=r"(val) : "r"((const volatile uint8_t *)addr)); + return val; +} + +static inline uint16_t readh(const uintptr_t addr) +{ + uint16_t val; + + __asm__ volatile("lh %0, 0(%1)" : "=r"(val) : "r"((const volatile uint16_t *)addr)); + return val; +} + +static inline uint32_t readw(const uintptr_t addr) +{ + uint32_t val; + + __asm__ volatile("lw %0, 0(%1)" : "=r"(val) : "r"((const volatile uint32_t *)addr)); + return val; +} +#endif /* CORE_V_MCU_MMIO_MOCK */ + +#endif /* IO_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/irq.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/irq.h new file mode 100644 index 000000000..aafe62267 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/irq.h @@ -0,0 +1,64 @@ +/***************************************************************************/ +/* Copyright (C) 2019 ETH Zurich and University of Bologna + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#ifndef IRQ_H +#define IRQ_H + +#include "pulp_mem_map.h" +#include "io.h" +#include "bits.h" + +#define IRQ_REG_MASK_OFFSET 0x000U +#define IRQ_REG_MASK_SET_OFFSET 0x004U +#define IRQ_REG_MASK_CLEAR_OFFSET 0x008U +#define IRQ_REG_INT_OFFSET 0x00CU +#define IRQ_REG_INT_SET_OFFSET 0x010U +#define IRQ_REG_INT_CLEAR_OFFSET 0x014U +#define IRQ_REG_ACK_OFFSET 0x018U +#define IRQ_REG_ACK_SET_OFFSET 0x01CU +#define IRQ_REG_ACK_CLEAR_OFFSET 0x020U +#define IRQ_REG_FIFO_OFFSET 0x024U + +#define IRQ_FC_EVT_SW0 BIT(0) +#define IRQ_FC_EVT_SW1 BIT(1) +#define IRQ_FC_EVT_SW2 BIT(2) +#define IRQ_FC_EVT_SW3 BIT(3) +#define IRQ_FC_EVT_SW4 BIT(4) +#define IRQ_FC_EVT_SW5 BIT(5) +#define IRQ_FC_EVT_SW6 BIT(6) +#define IRQ_FC_EVT_SW7 BIT(7) +#define IRQ_FC_EVT_DMA_PE_EVT BIT(8) +#define IRQ_FC_EVT_DMA_PE_IRQ BIT(9) +#define IRQ_FC_EVT_TIMER0_LO BIT(10) +#define IRQ_FC_EVT_TIMER0_HI BIT(11) +#define IRQ_FC_EVT_PF BIT(12) +#define IRQ_FC_EVT_CLK_REF BIT(14) +#define IRQ_FC_EVT_GPIO BIT(15) +#define IRQ_FC_EVT_ADV_TIMER0 BIT(17) +#define IRQ_FC_EVT_ADV_TIMER1 BIT(18) +#define IRQ_FC_EVT_ADV_TIMER2 BIT(19) +#define IRQ_FC_EVT_ADV_TIMER3 BIT(20) +#define IRQ_FC_EVT_SOC_EVT BIT(26) +#define IRQ_FC_EVT_QUIRQE_ERROR BIT(29) +#define IRQ_FC_EVT_PERIPH0 BIT(30) +#define IRQ_FC_EVT_PERIPH1 BIT(31) + +void irq_mask(uint32_t mask); +void irq_enable(uint32_t mask); +void irq_disable(uint32_t mask); +uint32_t irq_clint_disable(void); +uint32_t irq_clint_enable(void); +void pulp_irq_init(void); + +#endif /* IRQ_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/memory_map.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/memory_map.h new file mode 100644 index 000000000..f30483673 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/memory_map.h @@ -0,0 +1,39 @@ +/***************************************************************************/ +/* Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#ifndef MEMORY_MAP_H +#define MEMORY_MAP_H + +#include "pulp_mem_map.h" + +#define L2_BASE 0x1C000000UL +#define L2_SIZE 0x80000UL +#define L2_SHARED_ADDR L2_BASE +#define L2_SHARED_SIZE L2_SIZE +#define ROM_ADDR 0x1A000000UL +#define ROM_SIZE 0x00002000UL + +#define SOC_PERIPHERALS_ADDR PULP_SOC_PERIPHERALS_ADDR +#define SOC_FLL_ADDR PULP_FLL_ADDR +#define GPIO_ADDR PULP_GPIO_ADDR +#define UDMA_CTRL_ADDR PULP_UDMA_ADDR +#define APB_SOC_CTRL_ADDR PULP_APB_SOC_CTRL_ADDR +#define ADV_TIMER_ADDR PULP_ADV_TIMER_ADDR +#define SOC_EU_ADDR PULP_SOC_EU_ADDR +#define FC_IRQ_ADDR PULP_FC_IRQ_ADDR +#define FC_TIMER_ADDR PULP_FC_TIMER_ADDR +#define FC_HWPE_ADDR PULP_FC_HWPE_ADDR +#define STDOUT_ADDR PULP_STDOUT_ADDR + +#endif /* MEMORY_MAP_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/properties.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/properties.h new file mode 100644 index 000000000..98473696f --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/properties.h @@ -0,0 +1,43 @@ +/***************************************************************************/ +/* Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#ifndef PROPERTIES_H +#define PROPERTIES_H + +#define PULP + +/* Peripheral bus clock (clk_per): PER_CLK_PERIOD_NS=200 → 5 MHz */ +#define ARCHI_FPGA_FREQUENCY 5000000U +/* FC/SOC clock (clk_soc): FC_CLK_PERIOD_NS=100 → 10 MHz */ +#define ARCHI_SOC_FREQUENCY 10000000U +#define ARCHI_NUM_TIMER 1U +#define ARCHI_NUM_FLL 2U + +#define ARCHI_REF_CLOCK_LOG2 15U +#define ARCHI_REF_CLOCK (1U << ARCHI_REF_CLOCK_LOG2) + +#define ARCHI_NB_FLL 3U + +#define __RT_FLL_CL 2U +#define __RT_FLL_PERIPH 1U +#define __RT_FLL_FC 0U + +#define __RT_FREQ_DOMAIN_FC 0U +#define __RT_FREQ_DOMAIN_CL 2U +#define __RT_FREQ_DOMAIN_PERIPH 1U +#define RT_FREQ_NB_DOMAIN 3U + +#define DEFAULT_SYSTEM_CLOCK 50000000U + +#endif /* PROPERTIES_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/pulp_mem_map.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/pulp_mem_map.h new file mode 100644 index 000000000..32757d624 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/pulp_mem_map.h @@ -0,0 +1,103 @@ +/***************************************************************************/ +/* Copyright (C) 2019 ETH Zurich and University of Bologna + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#ifndef PULP_MEM_MAP_H +#define PULP_MEM_MAP_H + +#ifndef PULP_SOC_PERIPHERALS_ADDR +#define PULP_SOC_PERIPHERALS_ADDR 0x1A100000UL +#endif + +#ifndef PULP_FC_TIMER_SIZE +#define PULP_FC_TIMER_SIZE 0x00000800UL +#endif + +#ifndef PULP_FLL_OFFSET +#define PULP_FLL_OFFSET 0x00000000UL +#endif +#ifndef PULP_GPIO_OFFSET +#define PULP_GPIO_OFFSET 0x00001000UL +#endif +#ifndef PULP_UDMA_OFFSET +#define PULP_UDMA_OFFSET 0x00002000UL +#endif +#ifndef PULP_APB_SOC_CTRL_OFFSET +#define PULP_APB_SOC_CTRL_OFFSET 0x00004000UL +#endif +#ifndef PULP_ADV_TIMER_OFFSET +#define PULP_ADV_TIMER_OFFSET 0x00005000UL +#endif +#ifndef PULP_SOC_EU_OFFSET +#define PULP_SOC_EU_OFFSET 0x00006000UL +#endif +#ifndef PULP_FC_IRQ_OFFSET +#define PULP_FC_IRQ_OFFSET 0x00009800UL +#endif +#ifndef PULP_FC_TIMER_OFFSET +#define PULP_FC_TIMER_OFFSET 0x0000B000UL +#endif +#ifndef PULP_FC_HWPE_OFFSET +#define PULP_FC_HWPE_OFFSET 0x0000C000UL +#endif +#ifndef PULP_STDOUT_OFFSET +#define PULP_STDOUT_OFFSET 0x0000F000UL +#endif +#ifndef PULP_DEBUG_OFFSET +#define PULP_DEBUG_OFFSET 0x00010000UL +#endif + +#ifndef PULP_FLL_ADDR +#define PULP_FLL_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FLL_OFFSET) +#endif +#ifndef PULP_GPIO_ADDR +#define PULP_GPIO_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_GPIO_OFFSET) +#endif +#ifndef PULP_UDMA_ADDR +#define PULP_UDMA_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_UDMA_OFFSET) +#endif +#ifndef PULP_APB_SOC_CTRL_ADDR +#define PULP_APB_SOC_CTRL_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_APB_SOC_CTRL_OFFSET) +#endif +#ifndef PULP_ADV_TIMER_ADDR +#define PULP_ADV_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_ADV_TIMER_OFFSET) +#endif +#ifndef PULP_SOC_EU_ADDR +#define PULP_SOC_EU_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_SOC_EU_OFFSET) +#endif +#ifndef PULP_FC_IRQ_ADDR +#define PULP_FC_IRQ_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_IRQ_OFFSET) +#endif +#ifndef PULP_FC_TIMER_ADDR +#define PULP_FC_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_TIMER_OFFSET) +#endif +#ifndef PULP_FC_HWPE_ADDR +#define PULP_FC_HWPE_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_HWPE_OFFSET) +#endif +#ifndef PULP_STDOUT_ADDR +#define PULP_STDOUT_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_STDOUT_OFFSET) +#endif + +#define PULP_FLL_AREA_SIZE 0x00000010UL + +/* UDMA */ +#define UDMA_CH_ADDR_CTRL (PULP_UDMA_ADDR) +#define UDMA_CH_ADDR_UART (PULP_UDMA_ADDR + 0x80U) +#define UDMA_CH_ADDR_I2CM0 (PULP_UDMA_ADDR + 5U * UDMA_CH_SIZE) +#define UDMA_CH_ADDR_I2CM1 (PULP_UDMA_ADDR + 6U * UDMA_CH_SIZE) +#define UDMA_CTRL_I2CM0_CLKEN BIT(4) +#define UDMA_CTRL_I2CM1_CLKEN BIT(5) +#define UDMA_CH_SIZE (0x80U) +#define N_UART (2U) + +#endif /* PULP_MEM_MAP_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/string.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/string.h new file mode 100644 index 000000000..b56000009 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/string.h @@ -0,0 +1,25 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef STRING_H +#define STRING_H + +#include + +void *memcpy(void *dest, const void *src, size_t n); +void *memset(void *dest, int c, size_t n); +int memcmp(const void *lhs, const void *rhs, size_t n); + +#endif /* STRING_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/system_core_v_mcu.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/system_core_v_mcu.h new file mode 100644 index 000000000..4b445e31c --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/system_core_v_mcu.h @@ -0,0 +1,29 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef SYSTEM_CORE_V_MCU_H +#define SYSTEM_CORE_V_MCU_H + +#include + +extern void (*isr_table[32])(void); +extern volatile uint32_t system_core_clock; + +void system_init(void); +void tx_trap_handler(uint32_t mcause, uint32_t mepc, uint32_t mtval); +void tx_timer_irq_handler(void); +void tx_undefined_irq_handler(void); + +#endif /* SYSTEM_CORE_V_MCU_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/temp_sensor.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/temp_sensor.h new file mode 100644 index 000000000..e94c589a8 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/temp_sensor.h @@ -0,0 +1,29 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef TEMP_SENSOR_H +#define TEMP_SENSOR_H + +#include + +/* Read ADT7420 temperature sensor on I2CM1 (Nexys A7 on-board sensor). + * Returns temperature in tenths of degrees Celsius (e.g. 213 = 21.3°C). + * Returns INT16_MIN on I2C error. */ +int16_t temp_read_celsius_x10(void); + +/* Initialize the temperature sensor I2C channel. Call once at startup. */ +void temp_sensor_init(void); + +#endif /* TEMP_SENSOR_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/timer.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/timer.h new file mode 100644 index 000000000..ecfc0480b --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/timer.h @@ -0,0 +1,120 @@ +/***************************************************************************/ +/* Copyright (C) 2019 ETH Zurich and University of Bologna + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * Derived from core-v-freertos (https://github.com/openhwgroup/core-v-freertos) + * Original work licensed under the Apache License, Version 2.0. + * See https://www.apache.org/licenses/LICENSE-2.0 + * Modifications licensed under MIT (https://opensource.org/licenses/MIT). + * + * AI Disclosure: Some portions generated or modified by Copilot (Sonnet 4.6). + * + * SPDX-License-Identifier: Apache-2.0 AND MIT + ***************************************************************************/ + +#ifndef TIMER_H +#define TIMER_H + +#include "bits.h" + +#define TIMER_CFG_LO_OFFSET 0x0U +#define TIMER_CFG_HI_OFFSET 0x4U +#define TIMER_CNT_LO_OFFSET 0x8U +#define TIMER_CNT_HI_OFFSET 0xCU +#define TIMER_CMP_LO_OFFSET 0x10U +#define TIMER_CMP_HI_OFFSET 0x14U +#define TIMER_START_LO_OFFSET 0x18U +#define TIMER_START_HI_OFFSET 0x1CU +#define TIMER_RESET_LO_OFFSET 0x20U +#define TIMER_RESET_HI_OFFSET 0x24U + +#define TIMER_CFG_LO_ENABLE_BIT 0U +#define TIMER_CFG_LO_ENABLE_WIDTH 1U +#define TIMER_CFG_LO_ENABLE_MASK 0x1U +#define TIMER_CFG_LO_RESET_BIT 1U +#define TIMER_CFG_LO_RESET_WIDTH 1U +#define TIMER_CFG_LO_RESET_MASK 0x2U +#define TIMER_CFG_LO_IRQEN_BIT 2U +#define TIMER_CFG_LO_IRQEN_WIDTH 1U +#define TIMER_CFG_LO_IRQEN_MASK 0x4U +#define TIMER_CFG_LO_IEM_BIT 3U +#define TIMER_CFG_LO_IEM_WIDTH 1U +#define TIMER_CFG_LO_IEM_MASK 0x8U +#define TIMER_CFG_LO_MODE_BIT 4U +#define TIMER_CFG_LO_MODE_WIDTH 1U +#define TIMER_CFG_LO_MODE_MASK 0x10U +#define TIMER_CFG_LO_ONE_S_BIT 5U +#define TIMER_CFG_LO_ONE_S_WIDTH 1U +#define TIMER_CFG_LO_ONE_S_MASK 0x20U +#define TIMER_CFG_LO_PEN_BIT 6U +#define TIMER_CFG_LO_PEN_WIDTH 1U +#define TIMER_CFG_LO_PEN_MASK 0x40U +#define TIMER_CFG_LO_CCFG_BIT 7U +#define TIMER_CFG_LO_CCFG_WIDTH 1U +#define TIMER_CFG_LO_CCFG_MASK 0x80U +#define TIMER_CFG_LO_PVAL_BIT 8U +#define TIMER_CFG_LO_PVAL_WIDTH 8U +#define TIMER_CFG_LO_PVAL_MASK 0xFF00U +#define TIMER_CFG_LO_CASC_BIT 31U +#define TIMER_CFG_LO_CASC_WIDTH 1U +#define TIMER_CFG_LO_CASC_MASK 0x80000000UL + +#define TIMER_CFG_HI_ENABLE_BIT 0U +#define TIMER_CFG_HI_ENABLE_WIDTH 1U +#define TIMER_CFG_HI_ENABLE_MASK 0x1U +#define TIMER_CFG_HI_RESET_BIT 1U +#define TIMER_CFG_HI_RESET_WIDTH 1U +#define TIMER_CFG_HI_RESET_MASK 0x2U +#define TIMER_CFG_HI_IRQEN_BIT 2U +#define TIMER_CFG_HI_IRQEN_WIDTH 1U +#define TIMER_CFG_HI_IRQEN_MASK 0x4U +#define TIMER_CFG_HI_IEM_BIT 3U +#define TIMER_CFG_HI_IEM_WIDTH 1U +#define TIMER_CFG_HI_IEM_MASK 0x8U +#define TIMER_CFG_HI_MODE_BIT 4U +#define TIMER_CFG_HI_MODE_WIDTH 1U +#define TIMER_CFG_HI_MODE_MASK 0x10U +#define TIMER_CFG_HI_ONE_S_BIT 5U +#define TIMER_CFG_HI_ONE_S_WIDTH 1U +#define TIMER_CFG_HI_ONE_S_MASK 0x20U +#define TIMER_CFG_HI_PEN_BIT 6U +#define TIMER_CFG_HI_PEN_WIDTH 1U +#define TIMER_CFG_HI_PEN_MASK 0x40U +#define TIMER_CFG_HI_CLKCFG_BIT 7U +#define TIMER_CFG_HI_CLKCFG_WIDTH 1U +#define TIMER_CFG_HI_CLKCFG_MASK 0x80U + +#define TIMER_CNT_LO_CNT_LO_BIT 0U +#define TIMER_CNT_LO_CNT_LO_WIDTH 32U +#define TIMER_CNT_LO_CNT_LO_MASK 0xFFFFFFFFUL +#define TIMER_CNT_HI_CNT_HI_BIT 0U +#define TIMER_CNT_HI_CNT_HI_WIDTH 32U +#define TIMER_CNT_HI_CNT_HI_MASK 0xFFFFFFFFUL +#define TIMER_CMP_LO_CMP_LO_BIT 0U +#define TIMER_CMP_LO_CMP_LO_WIDTH 32U +#define TIMER_CMP_LO_CMP_LO_MASK 0xFFFFFFFFUL +#define TIMER_CMP_HI_CMP_HI_BIT 0U +#define TIMER_CMP_HI_CMP_HI_WIDTH 32U +#define TIMER_CMP_HI_CMP_HI_MASK 0xFFFFFFFFUL + +#define TIMER_START_LO_STRT_LO_BIT 0U +#define TIMER_START_LO_STRT_LO_WIDTH 1U +#define TIMER_START_LO_STRT_LO_MASK 0x1U +#define TIMER_START_HI_STRT_HI_BIT 0U +#define TIMER_START_HI_STRT_HI_WIDTH 1U +#define TIMER_START_HI_STRT_HI_MASK 0x1U +#define TIMER_RESET_LO_RST_LO_BIT 0U +#define TIMER_RESET_LO_RST_LO_WIDTH 1U +#define TIMER_RESET_LO_RST_LO_MASK 0x1U +#define TIMER_RESET_HI_RST_HI_BIT 0U +#define TIMER_RESET_HI_RST_HI_WIDTH 1U +#define TIMER_RESET_HI_RST_HI_MASK 0x1U + +struct pulp_timer +{ + unsigned int current_time; + unsigned int flags; + void *base; +}; + +#endif /* TIMER_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/timer_irq.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/timer_irq.h new file mode 100644 index 000000000..11e0d76a8 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/timer_irq.h @@ -0,0 +1,26 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef TIMER_IRQ_H +#define TIMER_IRQ_H + +#include + +int timer_irq_init(uint32_t ticks); +int timer_irq_set_timeout(uint32_t ticks); +uint32_t timer_irq_clock_elapsed(void); +uint32_t timer_irq_cycle_get_32(void); + +#endif /* TIMER_IRQ_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/tx_user.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/tx_user.h new file mode 100644 index 000000000..cc104032d --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/tx_user.h @@ -0,0 +1,22 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 100U +#define TX_INCLUDE_USER_DEFINE_FILE + +#endif /* TX_USER_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/include/uart_driver.h b/ports/risc-v32/gnu/example_build/core_v_mcu/include/uart_driver.h new file mode 100644 index 000000000..c17710932 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/include/uart_driver.h @@ -0,0 +1,27 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef UART_DRIVER_H +#define UART_DRIVER_H + +#include + +int uart_init(uint8_t uart_id, uint32_t baudrate, uint32_t periph_freq); +void uart_write_byte(uint8_t uart_id, uint8_t c); +int uart_read_byte(uint8_t uart_id); +void uart_write_str(uint8_t uart_id, const char *str); +void uart_write_buf(uint8_t uart_id, const uint8_t *buf, uint32_t len); + +#endif /* UART_DRIVER_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/install_deps.sh b/ports/risc-v32/gnu/example_build/core_v_mcu/install_deps.sh new file mode 100755 index 000000000..b4cd46a8a --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/install_deps.sh @@ -0,0 +1,53 @@ +#!/usr/bin/env bash +# /***************************************************************************/ +# /* Copyright (C) 2026 Eclipse ThreadX contributors +# * +# * This program and the accompanying materials are made available under the +# * terms of the MIT License which is available at +# * https://opensource.org/licenses/MIT. +# * +# * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). +# * The AI-generated portions may be considered public domain (CC0-1.0) +# * and not subject to the project's licence. +# * +# * SPDX-License-Identifier: MIT AND CC0-1.0 +# ***************************************************************************/ + +# install_deps.sh -- Install Linux build/debug dependencies for the CORE-V MCU ThreadX port. +# +# Supported: Ubuntu 20.04 / 22.04 / 24.04 and Debian derivatives. +# Run as a regular user; sudo is invoked internally where needed. +# +# Usage: +# bash install_deps.sh + +set -euo pipefail + +die() { echo "[ERROR] $*" >&2; exit 1; } +info() { echo "[INFO] $*"; } + +command -v apt-get >/dev/null 2>&1 || die "This script requires apt-get (Ubuntu/Debian)." + +PACKAGES=( + cmake + ninja-build + gcc-riscv64-unknown-elf + binutils-riscv64-unknown-elf + gdb-multiarch + openocd + usbutils + git +) + +info "Updating package lists ..." +sudo apt-get update -qq + +info "Installing: ${PACKAGES[*]}" +sudo apt-get install -y "${PACKAGES[@]}" + +info "" +info "All dependencies installed." +info "" +info "Next steps:" +info " 1. Run scripts/setup_opella.sh to configure udev rules for the Ashling Opella LD." +info " 2. (WSL only) Follow the usbipd-win instructions printed by setup_opella.sh." diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/link.ld b/ports/risc-v32/gnu/example_build/core_v_mcu/link.ld new file mode 100644 index 000000000..8ffb174e6 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/link.ld @@ -0,0 +1,65 @@ +OUTPUT_ARCH(riscv) +ENTRY(_start) + +MEMORY +{ + L2 (rwx) : ORIGIN = 0x1c000000, LENGTH = 0x80000 +} + +SECTIONS +{ + PROVIDE(__boot_address = 0x1c000880); + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x2000; + PROVIDE(__stack_size = __stack_size); + + .vectors 0x1c000800 : + { + __vector_start = .; + KEEP(*(.vectors)) + . = __vector_start + 0x80; + __vector_end = .; + } > L2 + + .text __boot_address : + { + *(.text.start) + *(.text .text.*) + *(.rodata .rodata.*) + . = ALIGN(4); + } > L2 + + .data : + { + __data_begin = .; + __sdata_begin = .; + *(.sdata .sdata.*) + *(.data .data.*) + . = ALIGN(4); + __data_end = .; + } > L2 + + .bss (NOLOAD) : + { + __bss_start = .; + *(.sbss .sbss.*) + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; + _end = .; + } > L2 + + PROVIDE(__tx_free_memory_start = __bss_end); + PROVIDE(__global_pointer$ = MIN(__sdata_begin + 0x800, + MAX(__data_begin + 0x800, __bss_end - 0x800))); + + __stack_top = ORIGIN(L2) + LENGTH(L2); + + ASSERT(SIZEOF(.vectors) <= 128, "Vector table exceeds reserved 128 bytes") + + /DISCARD/ : + { + *(.eh_frame) + *(.note.*) + } +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/openocd-nexys-Ashling-Opella-LD.cfg b/ports/risc-v32/gnu/example_build/core_v_mcu/openocd-nexys-Ashling-Opella-LD.cfg new file mode 100644 index 000000000..db43eae53 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/openocd-nexys-Ashling-Opella-LD.cfg @@ -0,0 +1,41 @@ +interface ftdi +ftdi_device_desc "Opella-LD Debug Probe" +ftdi_vid_pid 0x0B6B 0x0040 +ftdi_tdo_sample_edge falling +ftdi_layout_init 0x0A68 0xFF7B +ftdi_channel 0 +ftdi_layout_signal JTAGOE -ndata 0x0010 +ftdi_layout_signal nTRST -data 0x0020 +ftdi_layout_signal nSRST -data 0x0040 +ftdi_layout_signal SWD_EN -data 0x0100 +ftdi_layout_signal SWDIO_OE -data 0x0200 +ftdi_layout_signal LED -ndata 0x0800 +transport select jtag + + +reset_config none + +adapter_khz 1000 + +set _CHIPNAME riscv + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10001C05 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +riscv set_reset_timeout_sec 120 +riscv set_command_timeout_sec 120 + +# prefer to use sba for system bus access +riscv set_prefer_sba on + +# dump jtag chain +scan_chain + +init +halt +echo "Ready for Remote Connections" \ No newline at end of file diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/tests/CMakeLists.txt b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/CMakeLists.txt new file mode 100644 index 000000000..6726981f1 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/CMakeLists.txt @@ -0,0 +1,28 @@ +cmake_minimum_required(VERSION 3.15 FATAL_ERROR) +project(core_v_mcu_tests C) +set(CMAKE_C_STANDARD 99) +set(CMAKE_C_STANDARD_REQUIRED ON) + +set(CORE_V_MCU_DIR ${CMAKE_CURRENT_LIST_DIR}/..) + +add_executable(test_irq + ${CMAKE_CURRENT_LIST_DIR}/test_irq.c + ${CMAKE_CURRENT_LIST_DIR}/mock/mmio_mock.c +) +target_include_directories(test_irq PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/mock + ${CORE_V_MCU_DIR}/include +) + +add_executable(test_timer + ${CMAKE_CURRENT_LIST_DIR}/test_timer.c + ${CMAKE_CURRENT_LIST_DIR}/mock/mmio_mock.c +) +target_include_directories(test_timer PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/mock + ${CORE_V_MCU_DIR}/include +) + +enable_testing() +add_test(NAME irq_tests COMMAND test_irq) +add_test(NAME timer_tests COMMAND test_timer) diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/tests/mock/mmio_mock.c b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/mock/mmio_mock.c new file mode 100644 index 000000000..7852d5f10 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/mock/mmio_mock.c @@ -0,0 +1,18 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include "mmio_mock.h" + +uint32_t mock_mmio[MOCK_MMIO_SIZE]; diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/tests/mock/mmio_mock.h b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/mock/mmio_mock.h new file mode 100644 index 000000000..c8839e1e2 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/mock/mmio_mock.h @@ -0,0 +1,45 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef MMIO_MOCK_H +#define MMIO_MOCK_H + +#include +#include + +#define CORE_V_MCU_MMIO_MOCK 1 +#define MOCK_MMIO_SIZE 1024U + +extern uint32_t mock_mmio[MOCK_MMIO_SIZE]; + +static inline void writew(uint32_t val, uintptr_t addr) +{ + if (addr < (uintptr_t)(MOCK_MMIO_SIZE * 4U)) + { + mock_mmio[addr / 4U] = val; + } +} + +static inline uint32_t readw(const uintptr_t addr) +{ + if (addr < (uintptr_t)(MOCK_MMIO_SIZE * 4U)) + { + return mock_mmio[addr / 4U]; + } + + return 0U; +} + +#endif /* MMIO_MOCK_H */ diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/tests/test_irq.c b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/test_irq.c new file mode 100644 index 000000000..72c17f490 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/test_irq.c @@ -0,0 +1,66 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include +#include +#include +#include + +#include "mmio_mock.h" + +static uint32_t mock_mstatus = 0U; +#define csr_read(csr) (mock_mstatus) +#define csr_write(csr, val) do { mock_mstatus = (uint32_t)(val); } while (0) +#define csr_read_clear(csr, val) ({ uint32_t _v = mock_mstatus; mock_mstatus &= ~(uint32_t)(val); _v; }) +#define csr_read_set(csr, val) ({ uint32_t _v = mock_mstatus; mock_mstatus |= (uint32_t)(val); _v; }) + +#include "bits.h" +#define PULP_SOC_PERIPHERALS_ADDR 0U +#define PULP_FC_IRQ_OFFSET 0U +#include "irq.h" +#include "../../bsp/irq.c" + +static void test_irq_enable(void) +{ + memset(mock_mmio, 0, sizeof(mock_mmio)); + irq_enable(BIT(10)); + assert(mock_mmio[IRQ_REG_MASK_SET_OFFSET / 4U] == BIT(10)); + printf("test_irq_enable: PASS\n"); +} + +static void test_irq_disable(void) +{ + memset(mock_mmio, 0, sizeof(mock_mmio)); + irq_disable(BIT(10)); + assert(mock_mmio[IRQ_REG_MASK_CLEAR_OFFSET / 4U] == BIT(10)); + printf("test_irq_disable: PASS\n"); +} + +static void test_irq_clint_enable(void) +{ + mock_mstatus = 0U; + (void)irq_clint_enable(); + assert((mock_mstatus & 0x8U) != 0U); + printf("test_irq_clint_enable: PASS\n"); +} + +int main(void) +{ + test_irq_enable(); + test_irq_disable(); + test_irq_clint_enable(); + printf("All IRQ tests passed.\n"); + return 0; +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/tests/test_timer.c b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/test_timer.c new file mode 100644 index 000000000..3e1499e7d --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/tests/test_timer.c @@ -0,0 +1,53 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#include +#include +#include +#include + +#include "mmio_mock.h" +#define PULP_SOC_PERIPHERALS_ADDR 0U +#define PULP_FC_TIMER_OFFSET 0U + +#include "bits.h" +#include "timer.h" +#include "timer_irq.h" +#include "../../bsp/timer_irq.c" + +static void test_timer_irq_init(void) +{ + uint32_t cfg; + int ret; + + memset(mock_mmio, 0, sizeof(mock_mmio)); + ret = timer_irq_init(327U); + assert(ret == 0); + assert(mock_mmio[TIMER_CMP_LO_OFFSET / 4U] == 327U); + + cfg = mock_mmio[TIMER_CFG_LO_OFFSET / 4U]; + assert((cfg & TIMER_CFG_LO_ENABLE_MASK) != 0U); + assert((cfg & TIMER_CFG_LO_IRQEN_MASK) != 0U); + assert((cfg & TIMER_CFG_LO_CCFG_MASK) != 0U); + assert((cfg & TIMER_CFG_LO_MODE_MASK) != 0U); + printf("test_timer_irq_init: PASS\n"); +} + +int main(void) +{ + test_timer_irq_init(); + printf("All timer tests passed.\n"); + return 0; +} diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/tx_initialize_low_level.S b/ports/risc-v32/gnu/example_build/core_v_mcu/tx_initialize_low_level.S new file mode 100644 index 000000000..3c5a38884 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/tx_initialize_low_level.S @@ -0,0 +1,63 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + + .section .data + .global __tx_free_memory_start +__tx_free_memory_start: + + .section .text.trap_entry + .align 4 + .global tx_trap_entry + .extern _tx_thread_context_save + .extern _tx_thread_context_restore + .extern tx_trap_handler + +tx_trap_entry: + addi sp, sp, -128 + sw ra, 112(sp) + call _tx_thread_context_save + csrr a0, mcause + csrr a1, mepc + csrr a2, mtval + addi sp, sp, -4 + sw ra, 0(sp) + call tx_trap_handler + lw ra, 0(sp) + addi sp, sp, 4 + call _tx_thread_context_restore +1: + wfi + j 1b + + .section .text + .global _tx_initialize_low_level + .weak _tx_initialize_low_level + .extern _tx_thread_system_stack_ptr + .extern _tx_initialize_unused_memory + .extern __vector_start + +_tx_initialize_low_level: + la t0, _tx_thread_system_stack_ptr + sw sp, 0(t0) + + la t0, __tx_free_memory_start + la t1, _tx_initialize_unused_memory + sw t0, 0(t1) + + la t0, __vector_start + ori t0, t0, 1 + csrw mtvec, t0 + + ret diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/vectors.S b/ports/risc-v32/gnu/example_build/core_v_mcu/vectors.S new file mode 100644 index 000000000..f6a57d7ae --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/vectors.S @@ -0,0 +1,25 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + + .section .vectors, "ax" + .option norvc + .align 2 + .extern tx_trap_entry + .global __vector_start + +__vector_start: + .rept 32 + jal zero, tx_trap_entry + .endr diff --git a/ports/risc-v32/gnu/src/tx_thread_context_restore.S b/ports/risc-v32/gnu/src/tx_thread_context_restore.S index 5fa80437d..c20cbcdf5 100644 --- a/ports/risc-v32/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v32/gnu/src/tx_thread_context_restore.S @@ -149,7 +149,7 @@ _tx_thread_context_restore: /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) + li t3, 0x1880 // Set MPP=Machine (0x1800) + MPIE=1 (0x80); mret sets MIE=MPIE /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, preserve everything except the bits we will modify. */ @@ -284,7 +284,7 @@ _tx_thread_no_preempt_restore: csrr t1, mstatus li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1880 // Set MPP=Machine(0x1800) + MPIE(0x80) so mret re-enables MIE + li t3, 0x1880 // Set MPP=Machine (0x1800) + MPIE=1 (0x80); mret sets MIE=MPIE li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE and t1, t1, t4 or t1, t1, t3 From c7d4b2f22869f1f06a99599d4ccfe201b0496f82 Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Tue, 26 May 2026 00:59:17 +0500 Subject: [PATCH 18/29] Added RISC-V board Bananapi BPI-F3 (SpacemiT K1 SoC) BSP Support (#531) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Add BananaPi BPI-F3 BSP support Add RISC-V supervisor support to the rv64/gnu port and provide a complete board support package for the BananaPi BPI-F3 (SpacemiT K1 SoC, X60 cores). Port changes (risc-v64/gnu): - Guard all CSR accesses with TX_RISCV_SMODE to select S-mode registers (sstatus/sepc/sie/sret) vs M-mode (mstatus/mepc/mie/mret) in context_save, context_restore, schedule, system_return, interrupt_control, and stack_build. - Add S-mode TX_INT_ENABLE/TX_DISABLE and inline TX_RESTORE macros to tx_port.h. - Add TX_RISCV_SMODE CMake option to CMakeLists.txt. BananaPi BPI-F3 BSP (example_build/bananapi-f3): - Boot flow: FSBL → OpenSBI (M-mode) → U-Boot (S-mode) → ThreadX - S-mode trap handler with context save/restore integration - SBI legacy ecall timer at 10 Hz (24 MHz timebase) - PLIC driver with S-mode context, stale-IRQ drain, and callbacks - PXA-compatible UART0 console (115200 8N1) - Linker script at 0x200000 load address Tested on risc-v board, BananaPi BPI-F3 hardware. Signed-off-by: Akif Ejaz * Fixed S-mode context restore and PLIC spurious IRQ handling - tx_thread_context_restore.S (non-nested path): set SPIE(0x20) alongside SPP(0x100) so sret re-enables interrupts in the restored thread. - tx_thread_context_restore.S (both S-mode paths): use FS=Dirty (0x6000) instead of FS=Initial (0x2000) to match tx_thread_schedule.S and prevent FP register corruption across context switches. - plic.c (plic_irq_intr): return early when plic_claim() yields 0 (no pending interrupt) to avoid completing a spurious IRQ ID 0, which is undefined behavior per the PLIC spec. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --------- Signed-off-by: Akif Ejaz Co-authored-by: Frédéric Desbiens Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- CMakeLists.txt | 8 + .../gnu/example_build/bananapi-f3/.gitignore | 4 + .../gnu/example_build/bananapi-f3/board.c | 45 +++ .../bananapi-f3/build_libthreadx.sh | 59 +++ .../gnu/example_build/bananapi-f3/csr.h | 98 +++++ .../example_build/bananapi-f3/demo_threadx.c | 371 ++++++++++++++++++ .../gnu/example_build/bananapi-f3/entry.S | 73 ++++ .../gnu/example_build/bananapi-f3/hwtimer.c | 56 +++ .../gnu/example_build/bananapi-f3/hwtimer.h | 43 ++ .../gnu/example_build/bananapi-f3/link.lds | 87 ++++ .../gnu/example_build/bananapi-f3/plic.c | 132 +++++++ .../gnu/example_build/bananapi-f3/plic.h | 108 +++++ .../gnu/example_build/bananapi-f3/trap.c | 65 +++ .../bananapi-f3/tx_initialize_low_level.S | 139 +++++++ .../gnu/example_build/bananapi-f3/uart.c | 127 ++++++ .../gnu/example_build/bananapi-f3/uart.h | 72 ++++ ports/risc-v64/gnu/inc/tx_port.h | 23 +- .../gnu/src/tx_thread_context_restore.S | 53 ++- .../risc-v64/gnu/src/tx_thread_context_save.S | 8 + .../gnu/src/tx_thread_interrupt_control.S | 19 +- ports/risc-v64/gnu/src/tx_thread_schedule.S | 47 ++- .../risc-v64/gnu/src/tx_thread_stack_build.S | 2 +- .../gnu/src/tx_thread_system_return.S | 10 + 23 files changed, 1633 insertions(+), 16 deletions(-) create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/.gitignore create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/board.c create mode 100755 ports/risc-v64/gnu/example_build/bananapi-f3/build_libthreadx.sh create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/csr.h create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/demo_threadx.c create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/entry.S create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/hwtimer.c create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/hwtimer.h create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/link.lds create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/plic.c create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/plic.h create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/trap.c create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/tx_initialize_low_level.S create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/uart.c create mode 100644 ports/risc-v64/gnu/example_build/bananapi-f3/uart.h diff --git a/CMakeLists.txt b/CMakeLists.txt index e988d3a60..5faef86e8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -75,6 +75,14 @@ if(THREADX_SMP) target_compile_definitions(${PROJECT_NAME} PUBLIC "TX_MPCORE" ) endif() +# Optional: build for S-mode (Supervisor mode) instead of M-mode (Machine mode). +# Required when running after OpenSBI, e.g. booted from U-Boot. +option(TX_RISCV_SMODE "Use S-mode CSRs instead of M-mode for RISC-V targets" OFF) +if(TX_RISCV_SMODE) + message(STATUS "RISC-V S-mode enabled (TX_RISCV_SMODE)") + target_compile_definitions(${PROJECT_NAME} PUBLIC "TX_RISCV_SMODE") +endif() + # Enable a build target that produces a ZIP file of all sources set(CPACK_SOURCE_GENERATOR "ZIP") set(CPACK_SOURCE_IGNORE_FILES diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/.gitignore b/ports/risc-v64/gnu/example_build/bananapi-f3/.gitignore new file mode 100644 index 000000000..9cae8f843 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/.gitignore @@ -0,0 +1,4 @@ +kernel.bin +kernel.elf +kernel.uImage + diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/board.c b/ports/risc-v64/gnu/example_build/bananapi-f3/board.c new file mode 100644 index 000000000..efdbfe6dd --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/board.c @@ -0,0 +1,45 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "plic.h" +#include "hwtimer.h" +#include "uart.h" +#include +#include + +void *memset(void *des, int c, size_t n) +{ + if ((des == NULL) || n == 0) + return des; + + char *t = (char *)des; + for (size_t i = 0; i < n; i++) + t[i] = c; + return t; +} + +int board_init(void) +{ + int ret; + + ret = plic_init(); + if (ret) + return ret; + + ret = uart_init(); + if (ret) + return ret; + + ret = hwtimer_init(); + if (ret) + return ret; + + return 0; +} diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/build_libthreadx.sh b/ports/risc-v64/gnu/example_build/bananapi-f3/build_libthreadx.sh new file mode 100755 index 000000000..249ce68ce --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/build_libthreadx.sh @@ -0,0 +1,59 @@ +#!/bin/bash +# Build the bananapi-f3 (SpacemiT K1) ThreadX kernel. +# +# Boot flow: FSBL -> OpenSBI (M-mode) -> U-Boot (S-mode) -> ThreadX (S-mode). +# +# OpenSBI runs in M-mode and delegates S-mode to the next stage. +# U-Boot runs in S-mode; any code launched from U-Boot also runs in S-mode. +# +# Use the TX_RISCV_SMODE CMake option to build libthreadx.a for S-mode. +# +# This libthreadx.a (S-mode), then links the BSP objects +# to produce kernel.elf / kernel.bin. + +set -e + +# Where ThreadX is loaded by U-Boot (${loadaddr}). Must match the link.lds origin. +LOAD_ADDR=0x00200000 + +# printf "y\n" | rm -rf ../../../../../build/ +rm -f kernel.elf kernel.bin kernel.uImage + +pushd ../../../../../ +cmake -Bbuild -GNinja \ + -DCMAKE_TOOLCHAIN_FILE=cmake/riscv64_gnu.cmake \ + -DTX_USER_FILE="" \ + -DTX_RISCV_SMODE=ON \ + . +cmake --build ./build/ +popd + +riscv64-unknown-elf-gcc \ + -march=rv64gc -mabi=lp64d \ + -mcmodel=medany -O0 -g3 -Wall \ + -DTX_RISCV_SMODE \ + -ffunction-sections -fdata-sections \ + -I../../../../../common/inc \ + -I../../inc \ + entry.S \ + tx_initialize_low_level.S \ + board.c uart.c hwtimer.c plic.c trap.c demo_threadx.c \ + -L../../../../../build -lthreadx \ + -T link.lds -nostartfiles \ + -o kernel.elf + +# Strip ELF metadata down to the loadable bytes. +riscv64-unknown-elf-objcopy -O binary kernel.elf kernel.bin + +echo "== Build artifacts ==" +ls -la kernel.elf kernel.bin 2>/dev/null || true +echo +riscv64-unknown-elf-size kernel.elf || true +echo + +# Run on Bananapi BPI-F3 +# Stop the boot at U-Boot (press reset button and press "s" key continuously to stop autoboot). +# at "=>" prompt, load the kernel using the following commands: +# +# " ELF: tftpboot ${loadaddr} kernel.elf && bootelf ${loadaddr}" +# " BIN: tftpboot 0x200000 kernel.bin && go 0x200000" diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/csr.h b/ports/risc-v64/gnu/example_build/bananapi-f3/csr.h new file mode 100644 index 000000000..c5dfc6308 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/csr.h @@ -0,0 +1,98 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* RISC-V S-mode CSR helpers + * + * Privilege level: Supervisor (S-mode). + * Reference: RISC-V Privileged Specification + * + * Bit positions per the RISC-V Privileged Specification: + * + * sstatus: SIE(1) SPIE(5) SPP(8) FS(13:14) SUM(18) MXR(19) + * sie: SSIE(1) STIE(5) SEIE(9) + * scause: Interrupt bit = 63; Code 1=SSI, 5=STI, 9=SEI + */ + +#ifndef RISCV_CSR_H +#define RISCV_CSR_H + +#define SSTATUS_SIE (1L << 1) /* Supervisor Interrupt Enable */ +#define SSTATUS_SPIE (1L << 5) /* Previous SIE (saved on trap) */ +#define SSTATUS_SPP_MASK (1L << 8) +#define SSTATUS_SPP_S (1L << 8) /* SPP = Supervisor */ +#define SSTATUS_SPP_U (0L << 8) /* SPP = User */ +#define SSTATUS_FS (3L << 13) /* FP unit state (Off/Init/Clean/Dirty) */ + +#define SIE_SSIE (1L << 1) /* S-mode software interrupt */ +#define SIE_STIE (1L << 5) /* S-mode timer interrupt */ +#define SIE_SEIE (1L << 9) /* S-mode external interrupt */ + +#ifndef __ASSEMBLER__ + +#include + +/* + * Return the hart ID of the running core. + * + * mhartid is an M-mode CSR and cannot be read from S-mode. When booted + * from U-Boot only hart 0 is active (secondary harts remain parked in + * OpenSBI HSM), so we return 0. An SMP extension would need to pass + * the hart ID through a0 or shared memory at boot. + */ +static inline uint64_t riscv_get_core(void) +{ + return 0; +} + + +static inline uint64_t riscv_read_sstatus(void) +{ + uint64_t x; + asm volatile("csrr %0, sstatus" : "=r" (x)); + return x; +} + +static inline void riscv_write_sstatus(uint64_t x) +{ + asm volatile("csrw sstatus, %0" : : "r" (x)); +} + + +static inline void riscv_sintr_on(void) +{ + riscv_write_sstatus(riscv_read_sstatus() | SSTATUS_SIE); +} + +static inline void riscv_sintr_off(void) +{ + riscv_write_sstatus(riscv_read_sstatus() & ~SSTATUS_SIE); +} + +static inline int riscv_sintr_get(void) +{ + return (riscv_read_sstatus() & SSTATUS_SIE) != 0; +} + +static inline void riscv_sintr_restore(int enabled) +{ + if (enabled) + riscv_sintr_on(); + else + riscv_sintr_off(); +} + +/* Unified names used by BSP drivers (uart.c, etc.). */ +#define riscv_intr_on riscv_sintr_on +#define riscv_intr_off riscv_sintr_off +#define riscv_intr_get riscv_sintr_get +#define riscv_intr_restore riscv_sintr_restore + +#endif /* __ASSEMBLER__ */ +#endif /* RISCV_CSR_H */ diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/demo_threadx.c b/ports/risc-v64/gnu/example_build/bananapi-f3/demo_threadx.c new file mode 100644 index 000000000..93213c53a --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/demo_threadx.c @@ -0,0 +1,371 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include "uart.h" +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9180 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + puts("[Thread] : thread_0_entry is here!"); + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + puts("[Thread] : thread_1_entry is here!"); + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + puts("[Thread] : thread_2_entry is here!"); + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + puts("[Thread] : thread_3_and_4_entry is here!"); + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + puts("[Thread] : thread_5_entry is here!"); + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + puts("[Thread] : thread_6_and_7_entry is here!"); + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/entry.S b/ports/risc-v64/gnu/example_build/bananapi-f3/entry.S new file mode 100644 index 000000000..f1d0f03bf --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/entry.S @@ -0,0 +1,73 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + .global _start + .extern main + .extern _sysstack_start + .extern _bss_start + .extern _bss_end + + .section .text.entry + .align 4 +_start: + /* Zero all general-purpose registers (x1–x31). */ + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + /* Set up the initial supervisor stack (16 KiB). */ + la t0, _sysstack_start + li t1, 0x4000 + add sp, t0, t1 + + /* Zero the .bss section. */ + la t0, _bss_start + la t1, _bss_end +_bss_clean_start: + bgeu t0, t1, _bss_clean_end + sb zero, 0(t0) + addi t0, t0, 1 + j _bss_clean_start +_bss_clean_end: + + call main + + /* Halt if main() ever returns. */ +_park: + wfi + j _park diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/hwtimer.c b/ports/risc-v64/gnu/example_build/bananapi-f3/hwtimer.c new file mode 100644 index 000000000..4881ba3cc --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/hwtimer.c @@ -0,0 +1,56 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "tx_port.h" +#include "csr.h" +#include "hwtimer.h" + +/* + * SBI legacy set_timer ecall + * + * EID (a7) = 0 (SBI_SET_TIMER) + * a0 = absolute mtime compare value + * + * Programs mtimecmp for the current hart and clears sip.STIP. + */ +static inline void sbi_set_timer(uint64_t stime_value) +{ + register uint64_t a0 asm("a0") = stime_value; + register uint64_t a7 asm("a7") = 0; /* SBI_SET_TIMER */ + asm volatile("ecall" + : "+r"(a0) + : "r"(a7) + : "memory"); +} + +/* + * Read the free-running mtime counter via the rdtime pseudo-instruction. + * Accessible from S-mode per RISC-V Priv Spec §10.1 (Zicntr extension). + */ +static inline uint64_t read_time(void) +{ + uint64_t t; + asm volatile("rdtime %0" : "=r"(t)); + return t; +} + +int hwtimer_init(void) +{ + uint64_t now = read_time(); + sbi_set_timer(now + TICKNUM_PER_TIMER); + return 0; +} + +int hwtimer_handler(void) +{ + uint64_t now = read_time(); + sbi_set_timer(now + TICKNUM_PER_TIMER); + return 0; +} diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/hwtimer.h b/ports/risc-v64/gnu/example_build/bananapi-f3/hwtimer.h new file mode 100644 index 000000000..9265cee95 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/hwtimer.h @@ -0,0 +1,43 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_HWTIMER_H +#define RISCV_HWTIMER_H + +#include + +/* SpacemiT K1 TIMER (S-mode via SBI ecall) + * + * In S-mode the CLINT MMIO registers (mtime / mtimecmp) are protected + * by PMP and inaccessible. Timer operations are performed through the + * SBI legacy interface. + * + * rdtime - pseudo-instruction reading the time CSR (aliased to mtime + * by the implementation; accessible from S-mode per Priv + * Spec). + * + * SBI legacy set_timer (EID = 0, FID = 0) - programs mtimecmp on + * the current hart. Argument a0 = absolute compare value. + * Clears the pending supervisor timer interrupt (sip.STIP) + * as a side effect. + * + * + * Timebase frequency (DTS cpus { timebase-frequency = <0x16e3600>; }): + * 24,000,000 Hz (24 MHz). + * + * ThreadX tick rate: 10 Hz (100 ms period). + */ +#define TICKNUM_PER_SECOND 24000000UL +#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 10) + +int hwtimer_init(void); +int hwtimer_handler(void); + +#endif /* RISCV_HWTIMER_H */ diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/link.lds b/ports/risc-v64/gnu/example_build/bananapi-f3/link.lds new file mode 100644 index 000000000..99d9ae498 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/link.lds @@ -0,0 +1,87 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* Memory Layout of the SpacemiT K1 SoC. + * + * Memory map: + * + * Physical Address Size Usage + * ────────────────── ────────── ────────────────────────────── + * 0x0000_0000 512 KiB Reserved - M-mode / OpenSBI + * 0x0008_0000 ~2 GiB Usable DRAM Bank 0 + * 0x0020_0000 - ↠ThreadX kernel load address + * 0x7F00_0000 16 MiB Reserved - framebuffer / runtime + * 0x8000_0000–0xFFFF_FFFF PCI / MMIO hole (not DRAM) + * 0x1_0000_0000 ~14 GiB Usable DRAM Bank 1 + * + * Peripheral MMIO: + * + * 0xD401_7000 256 B UART0 (serial console) + * 0xE000_0000 64 MiB PLIC (interrupt controller) + * 0xE400_0000 64 KiB CLINT (timer / IPI) + * + * see more details on K1 Spec: + * Web : https://www.spacemit.com/community/document/?k1 + * PDF : https://cdn-resource.spacemit.com/file/chip/K1/K1_User_Manual_en.pdf + */ + + +OUTPUT_ARCH( "riscv" ) +ENTRY( _start ) + +PHDRS +{ + text PT_LOAD FLAGS(5); /* PF_R | PF_X */ + data PT_LOAD FLAGS(6); /* PF_R | PF_W */ +} + +SECTIONS +{ + . = 0x00200000; + + .text : { + KEEP(*(.text.entry)) + *(.text .text.*) + . = ALIGN(0x1000); + PROVIDE(etext = .); + } :text + + .rodata : { + . = ALIGN(16); + *(.srodata .srodata.*) + . = ALIGN(16); + *(.rodata .rodata.*) + } :text + + .data : { + . = ALIGN(16); + *(.sdata .sdata.*) + . = ALIGN(16); + *(.data .data.*) + } :data + + .bss : { + . = ALIGN(16); + _bss_start = .; + *(.sbss .sbss.*) + . = ALIGN(16); + *(.bss .bss.*) + _bss_end = .; + } :data + + .stack : { + . = ALIGN(4096); + _sysstack_start = .; + . += 0x4000; + _sysstack_end = .; + } :data + + PROVIDE(_end = .); +} diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/plic.c b/ports/risc-v64/gnu/example_build/bananapi-f3/plic.c new file mode 100644 index 000000000..6b04b65b8 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/plic.c @@ -0,0 +1,132 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "plic.h" +#include + +static irq_callback callbacks[MAX_CALLBACK_NUM]; + +#define PLIC_ENABLE(hart) PLIC_SENABLE(hart) +#define PLIC_PRIORITY_REG(hart) PLIC_SPRIORITY(hart) +#define PLIC_CLAIM_REG(hart) PLIC_SCLAIM(hart) +#define PLIC_COMPLETE_REG(hart) PLIC_SCOMPLETE(hart) + +void plic_irq_enable(int irqno) +{ + int hart = (int)riscv_get_core(); + uint32_t word = irqno / 32; + uint32_t bit = irqno % 32; + volatile uint32_t *en = (volatile uint32_t *)(PLIC_ENABLE(hart) + word * 4); + *en |= (1u << bit); +} + +void plic_irq_disable(int irqno) +{ + int hart = (int)riscv_get_core(); + uint32_t word = irqno / 32; + uint32_t bit = irqno % 32; + volatile uint32_t *en = (volatile uint32_t *)(PLIC_ENABLE(hart) + word * 4); + *en &= ~(1u << bit); +} + +void plic_prio_set(int irqno, int prio) +{ + PLIC_SET_PRIO(irqno, prio); +} + +int plic_prio_get(int irqno) +{ + return PLIC_GET_PRIO(irqno); +} + +int plic_register_callback(int irqno, irq_callback callback) +{ + if (!(irqno >= 0 && irqno < MAX_CALLBACK_NUM)) + return -1; + callbacks[irqno] = callback; + return 0; +} + +int plic_unregister_callback(int irqno) +{ + return plic_register_callback(irqno, NULL); +} + +int plic_init(void) +{ + int hart = (int)riscv_get_core(); + + for (int i = 0; i < MAX_CALLBACK_NUM; i++) + callbacks[i] = NULL; + + /* Mask everything for this hart. */ + for (int word = 0; word < (MAX_CALLBACK_NUM + 31) / 32; word++) + *(volatile uint32_t *)(PLIC_ENABLE(hart) + word * 4) = 0; + + /* Set hart threshold to 0 so any non-zero priority IRQ can fire. */ + *(volatile uint32_t *)PLIC_PRIORITY_REG(hart) = 0; + + /* + * Drain stale pending interrupts left over from a prior boot stage + * (BootROM / OpenSBI / U-Boot). We temporarily enable every source + * so claim returns the actual highest-priority pending ID, then + * complete whatever was claimed. Loop until claim returns 0 + * (no more pending). This follows the PLIC spec: claim returns 0 + * when nothing is pending for this context. + */ + for (int word = 0; word < (PLIC_NUM_SOURCES + 31) / 32; word++) + *(volatile uint32_t *)(PLIC_ENABLE(hart) + word * 4) = 0xFFFFFFFFu; + + for (;;) { + uint32_t id = *(volatile uint32_t *)PLIC_CLAIM_REG(hart); + if (id == 0) + break; + *(volatile uint32_t *)PLIC_COMPLETE_REG(hart) = id; + } + + /* Re-mask everything; individual drivers will enable their sources. */ + for (int word = 0; word < (PLIC_NUM_SOURCES + 31) / 32; word++) + *(volatile uint32_t *)(PLIC_ENABLE(hart) + word * 4) = 0; + + /* + * Set default priority for every source to PLIC_DEFAULT_PRIORITY (2), + * Priority 0 means "never pending" per the SiFive PLIC spec, so any + * source that should be active must have priority >= 1. Individual + * drivers may override this with plic_prio_set() later. + */ + for (int i = 1; i <= PLIC_NUM_SOURCES; i++) + PLIC_SET_PRIO(i, PLIC_DEFAULT_PRIORITY); + + return 0; +} + +int plic_claim(void) +{ + int hart = (int)riscv_get_core(); + return (int)*(volatile uint32_t *)PLIC_CLAIM_REG(hart); +} + +void plic_complete(int irqno) +{ + int hart = (int)riscv_get_core(); + *(volatile uint32_t *)PLIC_COMPLETE_REG(hart) = (uint32_t)irqno; +} + +int plic_irq_intr(void) +{ + int ret = -1; + int irqno = plic_claim(); + if (irqno == 0) + return ret; + if (irqno < MAX_CALLBACK_NUM && callbacks[irqno] != NULL) + ret = (callbacks[irqno])(irqno); + plic_complete(irqno); + return ret; +} diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/plic.h b/ports/risc-v64/gnu/example_build/bananapi-f3/plic.h new file mode 100644 index 000000000..fa755f896 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/plic.h @@ -0,0 +1,108 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_PLIC_H +#define RISCV_PLIC_H + +#include "csr.h" +#include + +/* + * SpacemiT K1 PLIC - SiFive-compatible Platform-Level Interrupt Controller. + * + * From bananapi-f3.dts (linux main tree): + * interrupt-controller@e0000000 { + * reg-names = "control"; + * interrupts-extended = <0x10 0x0b 0x10 0x09 0x11 0x0b 0x11 0x09 0x12 0x0b 0x12 0x09 0x13 0x0b 0x13 0x09 0x14 0x0b 0x14 0x09 0x15 0x0b 0x15 0x09 0x16 0x0b 0x16 0x09 0x17 0x0b 0x17 0x09>; + * compatible = "riscv,plic0"; + * #interrupt-cells = <0x01>; + * reg = <0x00 0xe0000000 0x00 0x4000000>; + * phandle = <0x1e>; + * riscv,ndev = <0x9f>; // (159 external interrupt sources) + * riscv,max-priority = <0x07>; // (priority levels 1..7; 0 = disabled) + * interrupt-controller; + * }; + + * The RISCV_APB block is at 0xE000_0000 with size 0x1000_0000. + * Within that block the PLIC occupies 0xE000_0000..0xE3FF_FFFF + * (64 MiB) and the CLINT lives at 0xE400_0000. + * + * The K1 main CPU has up to 8 X60 cores (harts 0..7). Each hart + * exposes both an M-mode and S-mode interrupt context to the PLIC. + * + * PLIC register layout: + * + * Offset Size Description + * ────────────── ────── ──────────────────────────────────────────── + * 0x000000 4/src Source priority (src 0 reserved, 1..159) + * 0x001000 20B Pending bits (5 × 32-bit words) + * 0x002000 0x100/h Enable bits per hart (M-mode at ctx 0) + * 0x002080 0x100/h Enable bits per hart (S-mode at ctx 1) + * 0x200000 0x2000/h Threshold + Claim/Complete (M-mode ctx 0) + * 0x201000 0x2000/h Threshold + Claim/Complete (S-mode ctx 1) + * + * Context mapping: + * EN_PER_HART = 0x100 (two contexts × 0x80 each) + * EN_PER_CONTEXT = 0x80 + * THRES_PER_HART = 0x2000 (two contexts × 0x1000 each) + * THRES_PER_CTX = 0x1000 + * THRES_CLAIM_OFF = 0x4 (claim/complete at threshold + 4) + * + */ + +#define PLIC 0xE0000000UL +#define PLIC_SIZE 0x04000000UL /* 64 MiB, from DTS reg */ + +#define PLIC_PRIORITY (PLIC + 0x0) +#define PLIC_PRIO_PER_ID 4 /* stride: 4 bytes/source */ + +#define PLIC_EN (PLIC + 0x2000) +#define PLIC_EN_PER_HART 0x100 +#define PLIC_EN_PER_CONTEXT 0x80 + + +#define PLIC_SENABLE(hart) (PLIC_EN + (hart) * PLIC_EN_PER_HART + PLIC_EN_PER_CONTEXT) + +#define PLIC_THRES (PLIC + 0x200000) +#define PLIC_THRES_PER_HART 0x2000 +#define PLIC_THRES_PER_CONTEXT 0x1000 +#define PLIC_THRES_CLAIM_OFF 0x4 + +/* + * S-mode threshold/claim = M-mode base + one context offset (0x1000). + */ +#define PLIC_SPRIORITY(hart) (PLIC_THRES + (hart) * PLIC_THRES_PER_HART + PLIC_THRES_PER_CONTEXT) +#define PLIC_SCLAIM(hart) (PLIC_SPRIORITY(hart) + PLIC_THRES_CLAIM_OFF) +#define PLIC_SCOMPLETE(hart) PLIC_SCLAIM(hart) + +#define PLIC_GET_PRIO(irqno) (*(volatile uint32_t *)(PLIC_PRIORITY + (irqno) * PLIC_PRIO_PER_ID)) +#define PLIC_SET_PRIO(irqno, prio) (*(volatile uint32_t *)(PLIC_PRIORITY + (irqno) * PLIC_PRIO_PER_ID) = (prio)) + + +#define PLIC_NUM_SOURCES 159 +#define PLIC_MAX_PRIORITY 7 +#define PLIC_DEFAULT_PRIORITY 2 +#define MAX_CALLBACK_NUM (PLIC_NUM_SOURCES + 1) + +typedef int (*irq_callback)(int irqno); + +void plic_irq_enable(int irqno); +void plic_irq_disable(int irqno); +int plic_prio_get(int irqno); +void plic_prio_set(int irqno, int prio); +int plic_register_callback(int irqno, irq_callback callback); +int plic_unregister_callback(int irqno); +int plic_init(void); +int plic_claim(void); +void plic_complete(int irqno); + +int plic_irq_intr(void); + +#endif /* RISCV_PLIC_H */ diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/trap.c b/ports/risc-v64/gnu/example_build/bananapi-f3/trap.c new file mode 100644 index 000000000..6418b02c3 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/trap.c @@ -0,0 +1,65 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* + * S-mode trap handler + */ + +#include "csr.h" +#include "uart.h" +#include "hwtimer.h" +#include "plic.h" +#include +#include +#include + +/* scause bit 63: interrupt flag. */ +#define SCAUSE_INTERRUPT 0x8000000000000000ull + +#define SCAUSE_S_TIMER_INT (SCAUSE_INTERRUPT | 5u) +#define SCAUSE_S_EXTERNAL_INT (SCAUSE_INTERRUPT | 9u) + +extern void _tx_timer_interrupt(void); + +void trap_handler(uintptr_t cause, uintptr_t epc, uintptr_t tval) +{ + (void)epc; + (void)tval; + + if (cause & SCAUSE_INTERRUPT) + { + if (cause == SCAUSE_S_TIMER_INT) + { + hwtimer_handler(); + _tx_timer_interrupt(); + } + else if (cause == SCAUSE_S_EXTERNAL_INT) + { + if (plic_irq_intr() != 0) + { + puts("[trap] PLIC dispatch failed"); + while (1) + ; + } + } + else + { + puts("[trap] unhandled S-mode interrupt"); + while (1) + ; + } + } + else + { + puts("[trap] unhandled synchronous exception"); + while (1) + ; + } +} diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/tx_initialize_low_level.S b/ports/risc-v64/gnu/example_build/bananapi-f3/tx_initialize_low_level.S new file mode 100644 index 000000000..3cfa83c39 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/tx_initialize_low_level.S @@ -0,0 +1,139 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "csr.h" + + .section .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* trap_entry RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for riscv processor trap handle */ +/* It will do the contex save and call c trap_handler and do contex */ +/* load */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* trap_handler */ +/* */ +/* CALLED BY */ +/* */ +/* hardware exception */ +/* */ +/**************************************************************************/ + + .global trap_entry + .extern trap_handler + .extern _tx_thread_context_save + .extern _tx_thread_context_restore + +trap_entry: +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -520 /* 65 * 8: integer + FP */ +#else + addi sp, sp, -256 /* 32 * 8: integer only */ +#endif + + sd x1, 224(sp) /* Save RA at offset 28*8 */ + + call _tx_thread_context_save + + csrr a0, scause + csrr a1, sepc + csrr a2, stval + addi sp, sp, -8 + sd ra, 0(sp) + call trap_handler + ld ra, 0(sp) + addi sp, sp, 8 + + call _tx_thread_context_restore + /* never returns */ +_trap_err: + wfi + j _trap_err + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V64/GNU */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/**************************************************************************/ + + .global _tx_initialize_low_level + .weak _tx_initialize_low_level + .extern _end + .extern board_init + .extern trap_entry + .extern _tx_thread_system_stack_ptr + .extern _tx_initialize_unused_memory + +_tx_initialize_low_level: + la t0, _tx_thread_system_stack_ptr + sd sp, 0(t0) /* Save system stack */ + + la t0, _end + la t1, _tx_initialize_unused_memory + sd t0, 0(t1) /* First free address */ + + /* Disable global S-mode interrupts during early init. */ + li t0, SSTATUS_SIE + csrrc zero, sstatus, t0 + + /* Set SPIE = 1 so SRET re-enables interrupts. */ + li t0, SSTATUS_SPIE + csrrs zero, sstatus, t0 + + /* Enable S-mode timer and external interrupts. */ + li t0, (SIE_STIE | SIE_SEIE) + csrrs zero, sie, t0 + +#ifdef __riscv_flen + li t0, SSTATUS_FS + csrrs zero, sstatus, t0 + fscsr x0 +#endif + + addi sp, sp, -8 + sd ra, 0(sp) + call board_init + ld ra, 0(sp) + addi sp, sp, 8 + + la t0, trap_entry + csrw stvec, t0 + ret diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/uart.c b/ports/risc-v64/gnu/example_build/bananapi-f3/uart.c new file mode 100644 index 000000000..3ef89d094 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/uart.c @@ -0,0 +1,127 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "uart.h" +#include "csr.h" +#include "plic.h" +#include + +/* + * The K1 UART Register layout + * + * Offset Name Access Description + * ────── ────── ────── ────────────────────────────── + * 0x00 RBR/THR R/W Receive Buffer / Transmit Hold + * 0x00 DLL R/W (DLAB=1) Divisor Latch Low + * 0x04 IER R/W Interrupt Enable + * 0x04 DLH R/W (DLAB=1) Divisor Latch High + * 0x08 IIR R Interrupt Identification + * 0x08 FCR W FIFO Control + * 0x0C LCR R/W Line Control + * 0x10 MCR R/W Modem Control + * 0x14 LSR R Line Status + * 0x18 MSR R Modem Status + * 0x1C SPR R/W Scratchpad + */ + +#define REG(off) (*(volatile uint32_t *)(UART0 + (off))) + +#define RHR 0x00 +#define THR 0x00 +#define DLL 0x00 +#define IER 0x04 +#define DLH 0x04 +#define IIR 0x08 +#define FCR 0x08 +#define LCR 0x0C +#define MCR 0x10 +#define LSR 0x14 + + +#define IER_RAVIE (1u << 0) /* Receiver data available IRQ enable */ +#define IER_TIE (1u << 1) /* Transmit data request IRQ enable */ +#define IER_RLSE (1u << 2) /* Receiver line status IRQ enable */ +#define IER_UUE (1u << 6) /* UART unit enable */ + +#define FCR_TRFIFOE (1u << 0) /* Transmit/Receive FIFO enable */ +#define FCR_RESETRF (1u << 1) /* Reset receive FIFO */ +#define FCR_RESETTF (1u << 2) /* Reset transmit FIFO */ +#define FCR_FIFO_CLEAR (FCR_RESETRF | FCR_RESETTF) + +#define LCR_WLS_8 (3u << 0) /* 8-bit word */ +#define LCR_DLAB (1u << 7) /* Divisor latch access bit */ + +#define LSR_DR (1u << 0) /* Data ready in receive FIFO */ +#define LSR_TDRQ (1u << 5) /* Transmit holding/FIFO ready */ +#define LSR_TEMT (1u << 6) /* Transmitter empty */ + +#define ReadReg(off) (REG(off) & 0xFF) +#define WriteReg(off, v) (REG(off) = (uint32_t)((v) & 0xFF)) + +int uart_init(void) +{ + /* + * If a prior boot stage (BootROM / OpenSBI / U-Boot) already + * configured the UART, keep its baud-rate divisor so we keep + * a working console. Just make sure interrupts are masked, + * the FIFOs are clean and the unit-enable bit is set. + */ + WriteReg(IER, 0x00); + + /* + * Program the baud-rate divisor for 115200 baud. + * The PXA UART functional clock on K1 is 14.7456 MHz: + * 14,745,600 / (16 × 8) = 115,200 baud → DLL = 8, DLH = 0. + */ + WriteReg(LCR, LCR_DLAB); + WriteReg(DLL, 0x08); + WriteReg(DLH, 0x00); + + WriteReg(LCR, LCR_WLS_8); + WriteReg(FCR, FCR_TRFIFOE | FCR_FIFO_CLEAR); + + /* Enable the UART transmit/receive engines (K1-specific). */ + WriteReg(IER, IER_UUE); + + plic_irq_enable(UART0_IRQ); + plic_prio_set(UART0_IRQ, 1); + + puts("[uart] UART0 initialized"); + return 0; +} + +static inline void uart_putc_nolock(int ch) +{ + while ((ReadReg(LSR) & LSR_TDRQ) == 0) + ; + WriteReg(THR, ch); +} + +int uart_putc(int ch) +{ + int intr_enable = riscv_intr_get(); + riscv_intr_off(); + uart_putc_nolock(ch); + riscv_intr_restore(intr_enable); + return 1; +} + +int uart_puts(const char *str) +{ + int i; + int intr_enable = riscv_intr_get(); + riscv_intr_off(); + for (i = 0; str[i] != 0; i++) + uart_putc_nolock(str[i]); + uart_putc_nolock('\r'); + uart_putc_nolock('\n'); + riscv_intr_restore(intr_enable); + return i; +} diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/uart.h b/ports/risc-v64/gnu/example_build/bananapi-f3/uart.h new file mode 100644 index 000000000..b03d0dd4a --- /dev/null +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/uart.h @@ -0,0 +1,72 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_UART_H +#define RISCV_UART_H + +/* SpacemiT K1 UART0 + * + * DTS node: /soc/serial@d4017000 + * serial@d4017000 { + * power-domains = <0x20 0x00>; + * reg-io-width = <0x04>; + * clk-fpga = <0xe11130>; + * pinctrl-names = "default"; + * interconnect-names = "dma-mem"; + * pinctrl-0 = <0x23>; + * interconnects = <0x22>; + * resets = <0x1d 0x01>; + * interrupts = <0x2a>; + * clocks = <0x03 0x3a 0x03 0xb4>; + * interrupt-parent = <0x1e>; + * dma-names = "rx", "tx"; + * cpuidle,pm-runtime,sleep; + * compatible = "spacemit,pxa-uart"; + * status = "okay"; + * reg = <0x00 0xd4017000 0x00 0x100>; + * dmas = <0x21 0x04 0x01 0x21 0x03 0x01>; + * reg-shift = <0x02>; + * }; + + + * K1 User Manual Section 16.3.4 defines the register layout. Because + * reg-shift = 2, the logical 16550A register indices (0..7) map to + * byte offsets 0x00, 0x04, 0x08, ..., 0x1C (stride of 4). + * + * Register map (at UART0 + offset): + * + * Offset Name R/W Description + * ────── ────────── ─── ──────────────────────────────────── + * 0x00 RBR/THR/DLL R/W Receive Buffer / Transmit Holding / + * Divisor Latch Low (when LCR.DLAB=1) + * 0x04 IER/DLH R/W Interrupt Enable / + * Divisor Latch High (when LCR.DLAB=1) + * 0x08 IIR/FCR R/W Interrupt Identification (R) / + * FIFO Control (W) + * 0x0C LCR R/W Line Control + * 0x10 MCR R/W Modem Control + * 0x14 LSR R Line Status + * 0x18 MSR R Modem Status + * 0x1C SPR R/W Scratchpad + * + */ + +#define UART0 0xD4017000UL +#define UART0_SIZE 0x100UL /* 256 bytes, from DTS reg */ +#define UART0_IRQ 42 /* DTS: interrupts = <0x2a> */ +#define UART0_REG_SHIFT 2 /* DTS: reg-shift = <0x02> */ + +#define puts uart_puts + +int uart_init(void); +int uart_putc(int ch); +int uart_puts(const char *str); + +#endif /* RISCV_UART_H */ diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h index 2f3bac1b2..6a70c0fe3 100644 --- a/ports/risc-v64/gnu/inc/tx_port.h +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -126,8 +126,13 @@ typedef unsigned short USHORT; /* Define various constants for the ThreadX RISC-V port. */ -#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ -#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ +#ifdef TX_RISCV_SMODE +#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ +#define TX_INT_ENABLE 0x00000002 /* Enable interrupt value (SIE bit 1 of sstatus) */ +#else +#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ +#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value (MIE bit 3 of mstatus) */ +#endif /* Define the clock source for trace event entry time stamp. The following two item are port specific. @@ -248,6 +253,19 @@ UINT _tx_thread_interrupt_control(UIN #define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; +#ifdef TX_RISCV_SMODE +#define TX_DISABLE __asm__ volatile("csrrci %0, sstatus, 2" : "=r" (interrupt_save) :: "memory"); +#define TX_RESTORE { \ + unsigned long _temp_sstatus; \ + __asm__ volatile( \ + "csrc sstatus, 2\n" \ + "andi %0, %1, 2\n" \ + "csrs sstatus, %0" \ + : "=&r" (_temp_sstatus) \ + : "r" (interrupt_save) \ + : "memory"); \ + } +#else #define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory"); #define TX_RESTORE { \ unsigned long _temp_mstatus; \ @@ -259,6 +277,7 @@ UINT _tx_thread_interrupt_control(UIN : "r" (interrupt_save) \ : "memory"); \ } +#endif /* TX_RISCV_SMODE */ #else diff --git a/ports/risc-v64/gnu/src/tx_thread_context_restore.S b/ports/risc-v64/gnu/src/tx_thread_context_restore.S index b73b485d4..9eea3df25 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_restore.S @@ -63,7 +63,11 @@ _tx_thread_context_restore: /* Lockout interrupts. */ +#ifdef TX_RISCV_SMODE + csrci sstatus, 0x02 // Disable interrupts (SIE bit 1) +#else csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) +#endif #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY call _tx_execution_isr_exit // Call the ISR execution exit function @@ -168,7 +172,25 @@ _tx_thread_context_restore: Also skip the saved registers since they have been restored by any function we called, except s0 since we use it ourselves. */ - ld t0, 30*8(sp) // Recover mepc + ld t0, 30*8(sp) // Recover exception PC +#ifdef TX_RISCV_SMODE + csrw sepc, t0 // Setup sepc + + /* Compose sstatus via read/modify/write to avoid clobbering unrelated bits. + Set SPIE and restore SPP to Supervisor, preserve other fields. */ + + csrr t1, sstatus + li t4, ~0x122 // Clear mask for SPP/SPIE/SIE + and t1, t1, t4 + li t3, 0x120 // Set SPP=Supervisor(0x100) + SPIE(0x20) so sret re-enables SIE + or t1, t1, t3 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t0, 0x6000 // Set FS=Dirty (bits 14:13) for FP state + or t1, t1, t0 +#endif + csrw sstatus, t1 // Update sstatus safely +#else csrw mepc, t0 // Setup mepc /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. @@ -189,6 +211,7 @@ _tx_thread_context_restore: or t1, t1, t0 #endif csrw mstatus, t1 // Update mstatus safely +#endif ld ra, 28*8(sp) // Recover return address ld t0, 19*8(sp) // Recover t0 @@ -228,7 +251,11 @@ _tx_thread_context_restore: ld t1, 18*8(t0) // Recover t1 ld t0, 19*8(t0) // Recover t0 #endif +#ifdef TX_RISCV_SMODE + sret // Return to point of interrupt +#else mret // Return to point of interrupt +#endif /* } */ _tx_thread_not_nested_restore: @@ -341,7 +368,24 @@ _tx_thread_no_preempt_restore: /* Restore registers, Skip global pointer because that does not change */ - ld t0, 30*8(sp) // Recover mepc + ld t0, 30*8(sp) // Recover exception PC +#ifdef TX_RISCV_SMODE + csrw sepc, t0 // Setup sepc + + /* Compose sstatus via read/modify/write to avoid clobbering unrelated bits. */ + + csrr t1, sstatus + li t4, ~0x122 // Clear mask for SPP/SPIE/SIE + and t1, t1, t4 + li t3, 0x120 // Set SPP=Supervisor(0x100) + SPIE(0x20) so sret re-enables SIE + or t1, t1, t3 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t0, 0x6000 // Set FS=Dirty (bits 14:13) for FP state + or t1, t1, t0 +#endif + csrw sstatus, t1 // Update sstatus safely +#else csrw mepc, t0 // Setup mepc @@ -363,6 +407,7 @@ _tx_thread_no_preempt_restore: or t1, t1, t0 #endif csrw mstatus, t1 // Update mstatus safely +#endif ld ra, 28*8(sp) // Recover return address ld t0, 19*8(sp) // Recover t0 @@ -402,7 +447,11 @@ _tx_thread_no_preempt_restore: ld t1, 18*8(t0) // Recover t1 ld t0, 19*8(t0) // Recover t0 #endif +#ifdef TX_RISCV_SMODE + sret // Return to point of interrupt +#else mret // Return to point of interrupt +#endif /* } else diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S index 1a6389907..3ffcb6b68 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S @@ -94,7 +94,11 @@ _tx_thread_context_save: sd t4, 15*8(sp) // Store t4 sd t5, 14*8(sp) // Store t5 sd t6, 13*8(sp) // Store t6 +#ifdef TX_RISCV_SMODE + csrr t0, sepc // Load exception program counter +#else csrr t0, mepc // Load exception program counter +#endif sd t0, 30*8(sp) // Save it on the stack /* Save floating point scratch registers if floating point is enabled. */ @@ -214,7 +218,11 @@ _tx_thread_not_nested_save: sd t5, 14*8(sp) // Store t5 sd t6, 13*8(sp) // Store t6 +#ifdef TX_RISCV_SMODE + csrr t1, sepc // Load exception program counter +#else csrr t1, mepc // Load exception program counter +#endif sd t1, 30*8(sp) // Save it on the stack /* Save floating point scratch registers if floating point is enabled. */ diff --git a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S index dfcb6b47f..b43d95589 100644 --- a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S +++ b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S @@ -59,20 +59,25 @@ .global _tx_thread_interrupt_control _tx_thread_interrupt_control: /* Pickup current interrupt lockout posture. */ - /* old_mstatus = mstatus; */ +#ifdef TX_RISCV_SMODE + csrr t0, sstatus + mv t1, t0 // Save original sstatus for return + li t2, ~0x02 // Build mask to clear SIE (bit 1) + and t0, t0, t2 // Clear SIE bit + andi a0, a0, 0x02 // Mask incoming to only SIE bit + or t0, t0, a0 // Set requested SIE state + csrw sstatus, t0 + andi a0, t1, 0x02 // Return original SIE bit +#else csrr t0, mstatus mv t1, t0 // Save original mstatus for return - - /* Apply the new interrupt posture while preserving unrelated mstatus bits. */ - /* Only modify the MIE bit (bit 3) */ - /* mstatus = (mstatus & ~MIE) | (new_posture & MIE); */ - li t2, ~0x08 // Build mask to clear MIE and t0, t0, t2 // Clear MIE bit - and a0, a0, 0x08 // Mask incoming to only MIE bit + andi a0, a0, 0x08 // Mask incoming to only MIE bit or t0, t0, a0 // Set requested MIE state csrw mstatus, t0 andi a0, t1, 0x08 // Return original MIE bit +#endif ret /* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_schedule.S b/ports/risc-v64/gnu/src/tx_thread_schedule.S index 85fc9488f..401c7b1a0 100644 --- a/ports/risc-v64/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v64/gnu/src/tx_thread_schedule.S @@ -62,7 +62,11 @@ _tx_thread_schedule: /* Enable interrupts. */ +#ifdef TX_RISCV_SMODE + csrsi sstatus, 0x02 // Enable interrupts (SIE bit 1) +#else csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) +#endif /* Wait for a thread to execute. */ /* do @@ -94,7 +98,11 @@ _tx_thread_schedule_loop: /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ +#ifdef TX_RISCV_SMODE + csrci sstatus, 0x02 // Lockout interrupts +#else csrci mstatus, 0x08 // Lockout interrupts +#endif /* Setup the current thread pointer. */ /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ @@ -236,11 +244,33 @@ _tx_thread_schedule_loop: /* Recover standard registers. */ - ld t0, 30*8(sp) // Recover mepc + ld t0, 30*8(sp) // Recover mepc/sepc +#ifdef TX_RISCV_SMODE + csrw sepc, t0 // Store sepc + + /* Read/modify/write sstatus to preserve SUM, MXR, UXL, FS, etc. + Only touch SPP, SPIE, SIE — the bits SRET consumes. */ + csrr t0, sstatus + li t1, ~0x122 // Clear mask: SIE(1) | SPIE(5) | SPP(8) + and t0, t0, t1 + li t1, 0x120 // Set SPP=Supervisor(0x100) | SPIE(0x20) + or t0, t0, t1 +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t1, 0x6000 // Set FS=Dirty (bits 14:13) + or t0, t0, t1 +#endif + csrw sstatus, t0 // Update sstatus safely +#else csrw mepc, t0 // Store mepc - li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) + + /* Read/modify/write mstatus — same principle as S-mode path. */ + csrr t0, mstatus + li t1, ~0x1888 // Clear mask: MIE(3) | MPIE(7) | MPP(11:12) + and t0, t0, t1 + li t1, 0x1880 // Set MPP=Machine(0x1800) | MPIE(0x80) + or t0, t0, t1 #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t1, 0x2000 // Set FS bits for FP state + li t1, 0x6000 // Set FS=Dirty (bits 14:13) or t0, t0, t1 #endif #if defined(__riscv_vector) @@ -248,6 +278,7 @@ _tx_thread_schedule_loop: or t0, t0, t1 #endif csrw mstatus, t0 // Set mstatus +#endif ld ra, 28*8(sp) // Recover return address ld t0, 19*8(sp) // Recover t0 @@ -297,7 +328,11 @@ _tx_thread_schedule_loop: ld t1, 18*8(t0) // Recover t1 ld t0, 19*8(t0) // Recover t0 #endif +#ifdef TX_RISCV_SMODE + sret // Return to point of interrupt +#else mret // Return to point of interrupt +#endif _tx_thread_synch_return: @@ -377,8 +412,12 @@ _tx_thread_synch_return: ld s9, 3*8(sp) // Recover s9 ld s10, 2*8(sp) // Recover s10 ld s11, 1*8(sp) // Recover s11 - ld t0, 14*8(sp) // Recover mstatus + ld t0, 14*8(sp) // Recover status register +#ifdef TX_RISCV_SMODE + csrw sstatus, t0 // Store sstatus, enables interrupt +#else csrw mstatus, t0 // Store mstatus, enables interrupt +#endif #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) addi sp, sp, 29*8 // Recover stack frame #else diff --git a/ports/risc-v64/gnu/src/tx_thread_stack_build.S b/ports/risc-v64/gnu/src/tx_thread_stack_build.S index 410f6cc84..cc1cf2a36 100644 --- a/ports/risc-v64/gnu/src/tx_thread_stack_build.S +++ b/ports/risc-v64/gnu/src/tx_thread_stack_build.S @@ -192,7 +192,7 @@ If vector extension support: sd zero, 26*8(t0) // Initial a1 sd zero, 27*8(t0) // Initial a0 sd zero, 28*8(t0) // Initial ra - sd a1, 30*8(t0) // Initial mepc (thread entry point) + sd a1, 30*8(t0) // Initial mepc/sepc (thread entry point) #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) sd zero, 31*8(t0) // Initial ft0 sd zero, 32*8(t0) // Initial ft1 diff --git a/ports/risc-v64/gnu/src/tx_thread_system_return.S b/ports/risc-v64/gnu/src/tx_thread_system_return.S index 61babae35..8becb54b0 100644 --- a/ports/risc-v64/gnu/src/tx_thread_system_return.S +++ b/ports/risc-v64/gnu/src/tx_thread_system_return.S @@ -152,6 +152,15 @@ _tx_thread_system_return: sd s9, 3*8(sp) // Save s9 sd s10, 2*8(sp) // Save s10 sd s11, 1*8(sp) // Save s11 +#ifdef TX_RISCV_SMODE + csrr t0, sstatus // Pickup sstatus + sd t0, 14*8(sp) // Save sstatus + + + /* Lockout interrupts. will be enabled in _tx_thread_schedule */ + + csrci sstatus, 0x02 // Disable interrupts (SIE bit 1) +#else csrr t0, mstatus // Pickup mstatus sd t0, 14*8(sp) // Save mstatus @@ -159,6 +168,7 @@ _tx_thread_system_return: /* Lockout interrupts. will be enabled in _tx_thread_schedule */ csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) +#endif #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY From 5b1b740a6610ae3434da9fc2cd55f390f7619429 Mon Sep 17 00:00:00 2001 From: Christos Papadopoulos Date: Mon, 25 May 2026 22:12:33 +0200 Subject: [PATCH 19/29] Reverted ULONG to be 4 bytes long, fixing missaligment issue in the current port (#534) * Reverted RISCV-64 port * Fixed wrong load/store instructions used --- ports/risc-v64/gnu/inc/tx_port.h | 7 ++++--- ports/risc-v64/gnu/src/tx_thread_context_restore.S | 14 +++++++------- ports/risc-v64/gnu/src/tx_thread_context_save.S | 2 +- ports/risc-v64/gnu/src/tx_thread_schedule.S | 10 +++++----- ports/risc-v64/gnu/src/tx_thread_stack_build.S | 4 ++-- ports/risc-v64/gnu/src/tx_thread_system_return.S | 10 +++++----- ports/risc-v64/gnu/src/tx_timer_interrupt.S | 8 ++++---- 7 files changed, 28 insertions(+), 27 deletions(-) diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h index 6a70c0fe3..9bf167043 100644 --- a/ports/risc-v64/gnu/inc/tx_port.h +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -77,15 +77,16 @@ typedef char CHAR; typedef unsigned char UCHAR; typedef int INT; typedef unsigned int UINT; -typedef long LONG; -typedef unsigned long ULONG; +typedef int LONG; +typedef unsigned int ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; #define ULONG64_DEFINED #endif /* __ASSEMBLER__ */ - +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; /* Define the priority levels for ThreadX. Legal values range diff --git a/ports/risc-v64/gnu/src/tx_thread_context_restore.S b/ports/risc-v64/gnu/src/tx_thread_context_restore.S index 9eea3df25..cebc8a062 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_restore.S @@ -78,9 +78,9 @@ _tx_thread_context_restore: { */ la t0, _tx_thread_system_state // Pickup addr of nested interrupt count - ld t1, 0(t0) // Pickup nested interrupt count + lw t1, 0(t0) // Pickup nested interrupt count addi t1, t1, -1 // Decrement the nested interrupt counter - sd t1, 0(t0) // Store new nested count + sw t1, 0(t0) // Store new nested count beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore /* Interrupts are nested. */ @@ -283,7 +283,7 @@ _tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ - ld sp, 16(t1) // Switch back to thread's stack + ld sp, 8(t1) // Switch back to thread's stack /* Recover floating point registers. */ #if defined(__riscv_float_abi_single) @@ -460,7 +460,7 @@ _tx_thread_preempt_restore: /* Instead of directly activating the thread again, ensure we save the entire stack frame by saving the remaining registers. */ - ld t0, 16(t1) // Pickup thread's stack pointer + ld t0, 8(t1) // Pickup thread's stack pointer ori t3, zero, 1 // Build interrupt stack type sd t3, 0(t0) // Store stack type @@ -543,14 +543,14 @@ _tx_thread_preempt_restore: { */ la t0, _tx_timer_time_slice // Pickup time slice variable address - ld t2, 0(t0) // Pickup time slice + lw t2, 0(t0) // Pickup time slice beqz t2, _tx_thread_dont_save_ts // If 0, skip time slice processing /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice _tx_timer_time_slice = 0; */ - sd t2, 48(t1) // Save current time slice - sd x0, 0(t0) // Clear global time slice + sw t2, 36(t1) // Save current time slice + sw x0, 0(t0) // Clear global time slice /* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S index 3ffcb6b68..7935bfee2 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S @@ -312,7 +312,7 @@ _tx_thread_not_nested_save: la t1, _tx_thread_current_ptr // Pickup current thread pointer address ld t1, 0(t1) // Pickup current thread pointer - sd sp, 16(t1) // Save stack pointer + sd sp, 8(t1) // Save stack pointer #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY /* _tx_execution_isr_enter is called with thread stack pointer */ diff --git a/ports/risc-v64/gnu/src/tx_thread_schedule.S b/ports/risc-v64/gnu/src/tx_thread_schedule.S index 401c7b1a0..860adf0b6 100644 --- a/ports/risc-v64/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v64/gnu/src/tx_thread_schedule.S @@ -113,10 +113,10 @@ _tx_thread_schedule_loop: /* Increment the run count for this thread. */ /* _tx_thread_current_ptr -> tx_thread_run_count++; */ - ld t2, 8(t1) // Pickup run count - ld t3, 48(t1) // Pickup time slice value + lw t2, 4(t1) // Pickup run count + lw t3, 36(t1) // Pickup time slice value addi t2, t2, 1 // Increment run count - sd t2, 8(t1) // Store new run count + sw t2, 4(t1) // Store new run count /* Setup time-slice, if present. */ /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ @@ -126,8 +126,8 @@ _tx_thread_schedule_loop: /* Switch to the thread's stack. */ /* SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ - ld sp, 16(t1) // Switch to thread's stack - sd t3, 0(t2) // Store new time-slice + ld sp, 8(t1) // Switch to thread's stack + sw t3, 0(t2) // Store new time-slice #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY diff --git a/ports/risc-v64/gnu/src/tx_thread_stack_build.S b/ports/risc-v64/gnu/src/tx_thread_stack_build.S index cc1cf2a36..86cab4f09 100644 --- a/ports/risc-v64/gnu/src/tx_thread_stack_build.S +++ b/ports/risc-v64/gnu/src/tx_thread_stack_build.S @@ -140,7 +140,7 @@ If vector extension support: Stack Bottom: (higher memory address) */ - ld t0, 32(a0) // Pickup end of stack area + ld t0, 24(a0) // Pickup end of stack area li t1, ~15 // Build 16-byte alignment mask and t0, t0, t1 // Make sure 16-byte alignment @@ -258,6 +258,6 @@ vector_clear_done: /* Setup stack pointer. */ /* thread_ptr -> tx_thread_stack_ptr = t0; */ - sd t0, 16(a0) // Save stack pointer in thread's + sd t0, 8(a0) // Save stack pointer in thread's ret // control block and return /* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_system_return.S b/ports/risc-v64/gnu/src/tx_thread_system_return.S index 8becb54b0..583b3f3ee 100644 --- a/ports/risc-v64/gnu/src/tx_thread_system_return.S +++ b/ports/risc-v64/gnu/src/tx_thread_system_return.S @@ -183,15 +183,15 @@ _tx_thread_system_return: /* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; SP = _tx_thread_system_stack_ptr; */ - sd sp, 16(t1) // Save stack pointer - ld sp, 0(t2) // Switch to system stack + sd sp, 8(t1) // Save stack pointer + ld sp, 0(t2) // Switch to system stack /* Determine if the time-slice is active. */ /* if (_tx_timer_time_slice) { */ la t4, _tx_timer_time_slice // Pickup time slice variable addr - ld t3, 0(t4) // Pickup time slice value + lw t3, 0(t4) // Pickup time slice value la t2, _tx_thread_schedule // Pickup address of scheduling loop beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it @@ -199,8 +199,8 @@ _tx_thread_system_return: /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; _tx_timer_time_slice = 0; */ - sd t3, 48(t1) // Save current time-slice for thread - sd zero, 0(t4) // Clear time-slice variable + sw t3, 36(t1) // Save current time-slice for thread + sw zero, 0(t4) // Clear time-slice variable /* } */ _tx_thread_dont_save_ts: diff --git a/ports/risc-v64/gnu/src/tx_timer_interrupt.S b/ports/risc-v64/gnu/src/tx_timer_interrupt.S index 02b704614..53e572f32 100644 --- a/ports/risc-v64/gnu/src/tx_timer_interrupt.S +++ b/ports/risc-v64/gnu/src/tx_timer_interrupt.S @@ -66,11 +66,11 @@ _tx_timer_interrupt: /* _tx_timer_system_clock++; */ la t0, _tx_timer_system_clock // Pickup address of system clock - ld t1, 0(t0) // Pickup system clock + lw t1, 0(t0) // Pickup system clock la t2, _tx_timer_time_slice // Pickup address of time slice - ld t3, 0(t2) // Pickup time slice + lw t3, 0(t2) // Pickup time slice addi t1, t1, 1 // Increment system clock - sd t1, 0(t0) // Store new system clock + sw t1, 0(t0) // Store new system clock li t6, 0 // Clear local expired flag /* Test for time-slice expiration. */ @@ -83,7 +83,7 @@ _tx_timer_interrupt: /* Decrement the time_slice. */ /* _tx_timer_time_slice--; */ - sd t3, 0(t2) // Store new time slice + sw t3, 0(t2) // Store new time slice /* Check for expiration. */ /* if (_tx_timer_time_slice == 0) */ From e031a3d506fdbc589fc6032eba618918e0c6719a Mon Sep 17 00:00:00 2001 From: Wei-Chen Lai <138997176+Winstonllllai@users.noreply.github.com> Date: Tue, 26 May 2026 04:43:24 +0800 Subject: [PATCH 20/29] Implemented lazy FPU, GP relaxation, and QEMU automation for GNU port in arch/risc-v32 (#513) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This PR adds three functional improvements to the RISC-V 32-bit GNU port. Lazy FPU stacking (tx_thread_context_save.S, tx_thread_context_restore.S, tx_thread_schedule.S): FP register save/restore is now skipped whenmstatus.FS is Off, reducing context switch overhead for threads that do not use floating point. GP relaxation (cmake/riscv32_gnu.cmake, entry.s, link.lds): Enables the -mrelax compiler flag and defines __global_pointer$ in the linker script.The entry stub initializes gp at startup. gp is not saved or restored during context switches. WFI in idle loop (tx_thread_schedule.S): The scheduler issues wfi when no thread is ready, replacing busy-waiting with a low-power sleep. A Python/QEMU/GDB functional test runner is added under ports/risc-v32/gnu/example_build/qemu_virt/test/. It validates context switching, FPUcontext preservation, timer interrupts, and preemption. To run: cd ports/risc-v32/gnu/example_build/qemu_virt make check-functional-riscv32 Tested on QEMU virt machine (rv32gc). Co-authored-by: Wei-Chen Lai Winstonllllai@users.noreply.github.com Co-authored-by: Frédéric Desbiens frederic.desbiens@eclipse-foundation.org Co-authored-by: Copilot 223556219+Copilot@users.noreply.github.com --- .gitignore | 1 + cmake/riscv32_gnu.cmake | 2 +- ports/risc-v32/gnu/CMakeLists.txt | 4 + .../example_build/qemu_virt/CMakeLists.txt | 45 +++ .../example_build/qemu_virt/demo_threadx.c | 5 +- .../gnu/example_build/qemu_virt/entry.s | 7 +- .../gnu/example_build/qemu_virt/link.lds | 4 + .../test/azrtos_test_tx_gnu_riscv32_qemu.py | 284 ++++++++++++++++++ .../gnu/src/tx_thread_context_restore.S | 28 +- .../risc-v32/gnu/src/tx_thread_context_save.S | 28 +- ports/risc-v32/gnu/src/tx_thread_schedule.S | 22 +- 11 files changed, 410 insertions(+), 20 deletions(-) create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/test/azrtos_test_tx_gnu_riscv32_qemu.py diff --git a/.gitignore b/.gitignore index d2216ddb4..349eaddcf 100644 --- a/.gitignore +++ b/.gitignore @@ -4,6 +4,7 @@ .tmp/ _deps/ build/ +build_qemu/ Debug/ CMakeFiles/ CMakeScripts/ diff --git a/cmake/riscv32_gnu.cmake b/cmake/riscv32_gnu.cmake index ec8f98576..6843423c5 100644 --- a/cmake/riscv32_gnu.cmake +++ b/cmake/riscv32_gnu.cmake @@ -7,7 +7,7 @@ if(DEFINED SOFT_FLOAT) set(ARCH_FLAGS "-g -march=rv32ima_zicsr -mabi=ilp32 -mcmodel=medany") set(CACHE{SOFT_FLOAT} FORCE 1) else() - set(ARCH_FLAGS "-g -march=rv32gc -mabi=ilp32d -mcmodel=medany") + set(ARCH_FLAGS "-g -march=rv32gc -mabi=ilp32d -mcmodel=medany -mrelax") endif() set(CFLAGS "${ARCH_FLAGS}") set(ASFLAGS "${ARCH_FLAGS}") diff --git a/ports/risc-v32/gnu/CMakeLists.txt b/ports/risc-v32/gnu/CMakeLists.txt index 9357c6970..7c6785bba 100644 --- a/ports/risc-v32/gnu/CMakeLists.txt +++ b/ports/risc-v32/gnu/CMakeLists.txt @@ -17,3 +17,7 @@ target_include_directories(${PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_LIST_DIR}/inc ) + +if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt/CMakeLists.txt) + add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt) +endif() diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt b/ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt new file mode 100644 index 000000000..9e9ff7223 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt @@ -0,0 +1,45 @@ +set(QEMU_DEMO_DIR ${CMAKE_CURRENT_LIST_DIR}) + +add_executable(kernel.elf EXCLUDE_FROM_ALL + ${QEMU_DEMO_DIR}/demo_threadx.c + ${QEMU_DEMO_DIR}/entry.s + ${QEMU_DEMO_DIR}/uart.c + ${QEMU_DEMO_DIR}/plic.c + ${QEMU_DEMO_DIR}/hwtimer.c + ${QEMU_DEMO_DIR}/trap.c + ${QEMU_DEMO_DIR}/board.c + ${QEMU_DEMO_DIR}/tx_initialize_low_level.S +) + +target_link_libraries(kernel.elf PRIVATE threadx) + +target_include_directories(kernel.elf PRIVATE + ${CMAKE_SOURCE_DIR}/common/inc + ${CMAKE_SOURCE_DIR}/ports/${THREADX_ARCH}/${THREADX_TOOLCHAIN}/inc + ${QEMU_DEMO_DIR} +) + +target_link_options(kernel.elf PRIVATE + -T${QEMU_DEMO_DIR}/link.lds + -nostartfiles + -Wl,-Map=kernel.map +) + +# QEMU/GDB functional test runner. Optional: skipped silently if the +# host has no Python 3 interpreter on PATH. +find_package(Python3 COMPONENTS Interpreter) +if(Python3_FOUND) + add_custom_target(check-functional-riscv32 + COMMAND ${Python3_EXECUTABLE} + ${QEMU_DEMO_DIR}/test/azrtos_test_tx_gnu_riscv32_qemu.py + --elf $ + --qemu qemu-system-riscv32 + --gdb gdb + DEPENDS kernel.elf + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + COMMENT "Running RISC-V32 QEMU/GDB functional test runner..." + ) +else() + message(STATUS + "Python3 not found; check-functional-riscv32 target unavailable.") +endif() diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c b/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c index f21dbb26b..6cf490148 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c +++ b/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c @@ -9,6 +9,7 @@ #define DEMO_BYTE_POOL_SIZE 9120 #define DEMO_BLOCK_POOL_SIZE 100 #define DEMO_QUEUE_SIZE 100 +float fpu_test_val = 0.0f; char *_to_str(ULONG val) { @@ -201,7 +202,7 @@ UINT status; thread_0_counter++; /* Sleep for 10 ticks. */ - tx_thread_sleep(10); + tx_thread_sleep(1); /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); @@ -363,6 +364,8 @@ UINT status; if (status != TX_SUCCESS) break; + /* FPU Test */ + fpu_test_val += 1.1f; /* Get the mutex again with suspension. This shows that an owning thread may retrieve the mutex it owns multiple times. */ diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/entry.s b/ports/risc-v32/gnu/example_build/qemu_virt/entry.s index 9b202ca16..06cc2a2c3 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/entry.s +++ b/ports/risc-v32/gnu/example_build/qemu_virt/entry.s @@ -1,5 +1,5 @@ -.section .text +.section .text.boot, "ax" .align 4 .global _start .extern main @@ -11,7 +11,10 @@ _start: bne t0, zero, 1f li x1, 0 li x2, 0 - li x3, 0 +.option push +.option norelax + la gp, __global_pointer$ /* x3 = gp; norelax keeps this load absolute */ +.option pop li x4, 0 li x5, 0 li x6, 0 diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/link.lds b/ports/risc-v32/gnu/example_build/qemu_virt/link.lds index 522f90d96..d2ef5f289 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/link.lds +++ b/ports/risc-v32/gnu/example_build/qemu_virt/link.lds @@ -10,6 +10,7 @@ SECTIONS . = 0x80000000; .text : { + KEEP(*(.text.boot)) /* entry.s _start — must be first at 0x80000000 */ *(.text .text.*) . = ALIGN(0x1000); PROVIDE(etext = .); @@ -24,6 +25,9 @@ SECTIONS .data : { . = ALIGN(16); + /* Centre __global_pointer$ in the small-data window so the +/-2 KiB + reach of GP-relative addressing covers the .sdata/.sbss area. */ + PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) /* do not need to distinguish this from .data */ . = ALIGN(16); *(.data .data.*) diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/test/azrtos_test_tx_gnu_riscv32_qemu.py b/ports/risc-v32/gnu/example_build/qemu_virt/test/azrtos_test_tx_gnu_riscv32_qemu.py new file mode 100644 index 000000000..858b96e6a --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/test/azrtos_test_tx_gnu_riscv32_qemu.py @@ -0,0 +1,284 @@ +import subprocess +import sys +import os +import argparse +import socket +import select + +def print_content(content): + """Prints content using os.write to handle non-blocking stdout robustly.""" + try: + msg = f"{content}\n".encode('utf-8') + total_len = len(msg) + written = 0 + fd = sys.stdout.fileno() + while written < total_len: + try: + n = os.write(fd, msg[written:]) + written += n + except BlockingIOError: + select.select([], [fd], []) + except Exception: + pass + +def get_free_port(): + """Finds a free TCP port.""" + with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s: + s.bind(('', 0)) + return s.getsockname()[1] + +def run_qemu_test(elf_path, qemu_bin, gdb_bin): + """ + Runs a test cycle using QEMU and GDB. + """ + print(f"Testing ELF: {elf_path}") + print(f"QEMU: {qemu_bin}") + print(f"GDB: {gdb_bin}") + + # Find a free port for GDB connection + gdb_port = get_free_port() + print(f"Using GDB port: {gdb_port}") + + # 1. Start QEMU in the background + qemu_cmd = [ + qemu_bin, + "-M", "virt", + "-nographic", + "-bios", "none", # Disable default OpenSBI to avoid overlap at 0x80000000 + "-kernel", elf_path, + "-gdb", f"tcp::{gdb_port}", "-S", + "-monitor", "none", # Disable monitor to avoid clutter + "-serial", "stdio" # Redirect serial output to stdio so we can see it + ] + + print(f"Starting QEMU: {' '.join(qemu_cmd)}") + qemu_process = subprocess.Popen( + qemu_cmd, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + text=True + ) + + if qemu_process.poll() is not None: + print("QEMU failed to start.") + print(qemu_process.stderr.read()) + return False + + # 2. Create a GDB command file + # We use a defined command for the timer interrupt to perform the check automatically + gdb_cmds = """ +file {elf} +target remote :{port} +set pagination off +set confirm off + +# Setup Breakpoints +break tx_application_define +break thread_0_entry +break thread_6_and_7_entry +break _tx_timer_interrupt + +# Execute to Application Definition +continue + +# Inspect mstatus once thread_0 has started (FS bits should be observable; +# kept as a smoke check, the lazy-save logic itself is targeted by a +# follow-up PR). +continue +print/x $mstatus + +# Verify FPU Logic and Register State exercised by thread_6/7 +continue +finish +step +step +step +print/x $mstatus +info registers float +print fpu_test_val + +# Await Timer Interrupt +continue +print "Hit Timer Interrupt" + +# Verify MEPC Integrity - Save State +print/x $mepc +set $saved_pc = $mepc + +# Verify System Timer Before ISR +set $clock_before = _tx_timer_system_clock +print $clock_before + +# Configure Time-Slice Test Conditions +set _tx_timer_time_slice = 1 +set _tx_timer_expired_time_slice = 0 +set $ts_handler_called = 0 + +# Set Breakpoint at Time-Slice Handler with Auto-Continue +tbreak _tx_thread_time_slice +commands + set $ts_handler_called = 1 + continue +end + +# Set Breakpoint at ISR Return Address +set $ret_addr = $ra +tbreak *$ret_addr +continue + +# Verify Time-Slice Handler Was Called +if $ts_handler_called == 1 + print "SUCCESS: Time-slice handler called." +else + print "FAILURE: Time-slice handler NOT called." +end + +# Verify System Timer Increment (Monotonicity) +set $clock_after = _tx_timer_system_clock +print $clock_after + +if $clock_after > $clock_before + print "SUCCESS: System timer incremented." +else + print "FAILURE: System timer did not increment." +end + +# Verify Preemption Logic (Thread Priority) +# +# We are now stopped at the return address from _tx_timer_interrupt, +# after _tx_thread_time_slice has had a chance to update +# _tx_thread_execute_ptr but before trap_handler returns into +# _tx_thread_context_restore. At this point, a pending preemption is +# observable directly by comparing current_ptr (interrupted thread) +# and execute_ptr (thread chosen by the scheduler). +set $curr_ptr = _tx_thread_current_ptr +set $exec_ptr = _tx_thread_execute_ptr +if $curr_ptr != 0 && $exec_ptr != 0 + set $curr_prio = $curr_ptr->tx_thread_priority + set $exec_prio = $exec_ptr->tx_thread_priority + printf "PREEMPT_CHECK current_prio=%d execute_prio=%d\\n", $curr_prio, $exec_prio + if $exec_prio < $curr_prio + printf "PREEMPT_VERIFIED_OK\\n" + else + printf "PREEMPT_VERIFIED_FAIL_NOT_OBSERVED\\n" + end +else + printf "PREEMPT_VERIFIED_FAIL_NULL\\n" +end + +quit +""".format(port=gdb_port, elf=elf_path) + + gdb_cmd_file = "test_cmds.gdb" + with open(gdb_cmd_file, "w") as f: + f.write(gdb_cmds) + + # 3. Run GDB + gdb_cmd = [ + gdb_bin, + "--batch", + "-x", gdb_cmd_file + ] + + print_content(f"Starting GDB: {' '.join(gdb_cmd)}") + + # Cap the GDB session to 30 s so a wedged batch script (e.g. a + # `continue` that never hits its breakpoint) cannot hang CI. + GDB_TIMEOUT_S = 30 + + try: + gdb_process = subprocess.run( + gdb_cmd, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + text=True, + timeout=GDB_TIMEOUT_S, + ) + + print_content("GDB Output:") + print_content(gdb_process.stdout) + if gdb_process.stderr: + print_content("GDB Error Output:") + print_content(gdb_process.stderr) + + except subprocess.TimeoutExpired as e: + print_content( + f"FAILURE: GDB session exceeded {GDB_TIMEOUT_S}s timeout; " + "likely stuck on a `continue` that never matched a breakpoint." + ) + if e.stdout: + print_content("GDB Output (partial):") + print_content(e.stdout if isinstance(e.stdout, str) + else e.stdout.decode(errors='replace')) + if e.stderr: + print_content("GDB Error Output (partial):") + print_content(e.stderr if isinstance(e.stderr, str) + else e.stderr.decode(errors='replace')) + return False + + except Exception as e: + print_content(f"An error occurred during test execution: {e}") + return False + + finally: + # 4. Clean up + print_content("Stopping QEMU...") + qemu_process.terminate() + try: + qemu_process.wait(timeout=2) + except subprocess.TimeoutExpired: + print_content("QEMU did not terminate gracefully, killing it forcefullly.") + qemu_process.kill() + + # Verify results + stdout = gdb_process.stdout + timer_hit = "Breakpoint 4, _tx_timer_interrupt" in stdout + fpu_verified = False + preemption_verified = "PREEMPT_VERIFIED_OK" in stdout + + if "Breakpoint 3, thread_6_and_7_entry" in stdout: + if "1.10" in stdout or "fpu_test_val" in stdout: + print_content("SUCCESS: FPU instructions executed and registers inspected.") + fpu_verified = True + else: + print_content("FAILURE: Hit thread, but failed to inspect FPU. Output does not contain expected value.") + + if timer_hit: + print_content("SUCCESS: Timer Interrupt verified! Hit _tx_timer_interrupt.") + else: + print_content("FAILURE: Did not hit timer interrupt.") + + if preemption_verified: + print_content("SUCCESS: Preemption verified (higher-priority thread " + "preempted a lower-priority one).") + else: + if "PREEMPT_VERIFIED_FAIL_INVERTED" in stdout: + print_content("FAILURE: Preemption inverted -- lower priority " + "thread scheduled over higher priority one.") + elif "PREEMPT_VERIFIED_FAIL_NULL" in stdout: + print_content("FAILURE: Preemption check saw NULL thread pointers.") + elif "PREEMPT_VERIFIED_FAIL_NOT_OBSERVED" in stdout: + print_content("FAILURE: Preemption was not observed within the " + "loop budget.") + else: + print_content("FAILURE: Preemption check did not run to completion.") + + if timer_hit and fpu_verified and preemption_verified: + return True + else: + return False + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Run ThreadX QEMU/GDB Test") + parser.add_argument("--elf", required=True, help="Path to the kernel ELF file") + parser.add_argument("--qemu", default="qemu-system-riscv32", help="Path to QEMU binary") + parser.add_argument("--gdb", default="riscv-none-elf-gdb", help="Path to GDB binary") + + args = parser.parse_args() + + success = run_qemu_test(args.elf, args.qemu, args.gdb) + + if success: + sys.exit(0) + else: + sys.exit(1) diff --git a/ports/risc-v32/gnu/src/tx_thread_context_restore.S b/ports/risc-v32/gnu/src/tx_thread_context_restore.S index c20cbcdf5..d3d449e47 100644 --- a/ports/risc-v32/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v32/gnu/src/tx_thread_context_restore.S @@ -29,6 +29,7 @@ /* AUTHOR */ /* */ /* Akif Ejaz, 10xEngineers */ +/* Wei-Chen Lai, National Cheng Kung University */ /* */ /* DESCRIPTION */ /* */ @@ -82,7 +83,13 @@ _tx_thread_context_restore: /* Just recover the saved registers and return to the point of interrupt. */ - /* Recover floating point registers. */ + /* Recover floating point registers only if saved mstatus.FS was not Off. */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + lw t1, 29*4(sp) // Pickup saved mstatus + srli t1, t1, 13 + andi t1, t1, 0x3 + beqz t1, _tx_thread_skip_fp_restore // Skip if FS was Off +#endif #if defined(__riscv_float_abi_single) flw f0, 31*4(sp) // Recover ft0 flw f1, 32*4(sp) // Recover ft1 @@ -130,6 +137,7 @@ _tx_thread_context_restore: lw t0, 63*4(sp) // Recover fcsr csrw fcsr, t0 // Restore fcsr #endif +_tx_thread_skip_fp_restore: /* Recover standard registers. */ @@ -222,7 +230,13 @@ _tx_thread_no_preempt_restore: lw sp, 8(t1) // Switch back to thread's stack - /* Recover floating point registers. */ + /* Recover floating point registers only if saved mstatus.FS was not Off. */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + lw t3, 29*4(sp) // Pickup saved mstatus + srli t3, t3, 13 + andi t3, t3, 0x3 + beqz t3, _tx_thread_no_preempt_skip_fp_restore // Skip if FS was Off +#endif #if defined(__riscv_float_abi_single) flw f0, 31*4(sp) // Recover ft0 flw f1, 32*4(sp) // Recover ft1 @@ -270,6 +284,7 @@ _tx_thread_no_preempt_restore: lw t0, 63*4(sp) // Recover fcsr csrw fcsr, t0 // Restore fcsr #endif +_tx_thread_no_preempt_skip_fp_restore: /* Recover the saved context and return to the point of interrupt. */ @@ -331,7 +346,13 @@ _tx_thread_preempt_restore: ori t3, zero, 1 // Build interrupt stack type sw t3, 0(t0) // Store stack type - /* Store floating point preserved registers. */ + /* Store floating point preserved registers only if saved mstatus.FS was not Off. */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + lw t3, 29*4(t0) // Pickup saved mstatus + srli t3, t3, 13 + andi t3, t3, 0x3 + beqz t3, _tx_thread_preempt_skip_fp_restore // Skip if FS was Off +#endif #ifdef __riscv_float_abi_single fsw f8, 39*4(t0) // Store fs0 fsw f9, 40*4(t0) // Store fs1 @@ -359,6 +380,7 @@ _tx_thread_preempt_restore: fsd f26, 57*4(t0) // Store fs10 fsd f27, 58*4(t0) // Store fs11 #endif +_tx_thread_preempt_skip_fp_restore: /* Store standard preserved registers. */ diff --git a/ports/risc-v32/gnu/src/tx_thread_context_save.S b/ports/risc-v32/gnu/src/tx_thread_context_save.S index 664029340..0a0c0c156 100644 --- a/ports/risc-v32/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v32/gnu/src/tx_thread_context_save.S @@ -29,6 +29,7 @@ /* AUTHOR */ /* */ /* Akif Ejaz, 10xEngineers */ +/* Wei-Chen Lai, National Cheng Kung University */ /* */ /* DESCRIPTION */ /* */ @@ -96,6 +97,15 @@ _tx_thread_context_save: sw t5, 14*4(sp) // Store t5 sw t6, 13*4(sp) // Store t6 + /* Save mstatus and skip FP state if FS is Off. */ + csrr t0, mstatus + sw t0, 29*4(sp) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + srli t1, t0, 13 + andi t1, t1, 0x3 + beqz t1, _tx_thread_skip_fpu_save +#endif + /* Save floating point registers. */ #if defined(__riscv_float_abi_single) fsw f0, 31*4(sp) // Store ft0 @@ -144,14 +154,11 @@ _tx_thread_context_save: csrr t0, fcsr sw t0, 63*4(sp) // Store fcsr #endif +_tx_thread_skip_fpu_save: csrr t0, mepc sw t0, 30*4(sp) // Save it on the stack - /* Save mstatus. */ - csrr t0, mstatus - sw t0, 29*4(sp) - la t1, _tx_thread_current_ptr // Pickup address of current thread ptr lw t2, 0(t1) // Pickup current thread pointer beqz t2, _tx_thread_idle_system_save // If NULL, idle system was interrupted @@ -190,6 +197,15 @@ _tx_thread_nested_save: sw t5, 14*4(sp) // Store t5 sw t6, 13*4(sp) // Store t6 + /* Save mstatus and skip FP state if FS is Off. */ + csrr t0, mstatus + sw t0, 29*4(sp) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + srli t1, t0, 13 + andi t1, t1, 0x3 + beqz t1, _tx_thread_skip_nested_fpu_save +#endif + /* Save floating point registers. */ #if defined(__riscv_float_abi_single) fsw f0, 31*4(sp) // Store ft0 @@ -238,13 +254,11 @@ _tx_thread_nested_save: csrr t0, fcsr sw t0, 63*4(sp) // Store fcsr #endif +_tx_thread_skip_nested_fpu_save: csrr t0, mepc sw t0, 30*4(sp) // Save it on stack - csrr t0, mstatus - sw t0, 29*4(sp) - /* Call the ISR execution exit function if enabled. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY call _tx_execution_isr_enter // Call the ISR execution enter function diff --git a/ports/risc-v32/gnu/src/tx_thread_schedule.S b/ports/risc-v32/gnu/src/tx_thread_schedule.S index 1c235a2d2..213aa9769 100644 --- a/ports/risc-v32/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v32/gnu/src/tx_thread_schedule.S @@ -133,7 +133,12 @@ _tx_thread_ready_to_run: lw t0, 0(sp) // Pickup stack type beqz t0, _tx_thread_solicited_return // If 0, solicited return - /* Recover floating point registers. */ + /* Recover floating point registers only if saved mstatus.FS was not Off. */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + lw t1, 29*4(sp) // Pickup saved mstatus + srli t1, t1, 13 + andi t1, t1, 0x3 + beqz t1, _tx_thread_schedule_skip_fp_restore // Skip if FS was Off #if defined(__riscv_float_abi_single) flw f0, 31*4(sp) // Recover ft0 flw f1, 32*4(sp) // Recover ft1 @@ -204,11 +209,11 @@ _tx_thread_ready_to_run: fld f31, 62*4(sp) // Recover ft11 lw t0, 63*4(sp) // Recover fcsr csrw fcsr, t0 // Restore fcsr +#endif +_tx_thread_schedule_skip_fp_restore: #endif /* Recover standard registers. */ - - lw t0, 30*4(sp) // Recover mepc csrw mepc, t0 // Setup mepc li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) @@ -256,7 +261,12 @@ _tx_thread_ready_to_run: _tx_thread_solicited_return: - /* Recover floating point registers. */ + /* Recover floating point registers only if saved mstatus.FS was not Off. */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + lw t1, 14*4(sp) // Pickup saved mstatus + srli t1, t1, 13 + andi t1, t1, 0x3 + beqz t1, _tx_thread_schedule_solicited_skip_fp_restore // Skip if FS was Off #if defined(__riscv_float_abi_single) flw f8, 15*4(sp) // Recover fs0 flw f9, 16*4(sp) // Recover fs1 @@ -287,11 +297,11 @@ _tx_thread_solicited_return: fld f27, 26*4(sp) // Recover fs11 lw t0, 27*4(sp) // Recover fcsr csrw fcsr, t0 // Restore fcsr +#endif +_tx_thread_schedule_solicited_skip_fp_restore: #endif /* Recover standard registers. */ - - lw t0, 14*4(sp) // Recover mstatus csrw mstatus, t0 // Restore mstatus lw ra, 13*4(sp) // Recover return address From 2c16114a450056103bacee0a3254a57dad7e1abd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Tue, 26 May 2026 17:17:40 -0400 Subject: [PATCH 21/29] Added win64 ports of ThreadX and ThreadX SMP (#529) Windows x64 port and regression suite This PR adds the Windows x64 (Win64) simulation port for both the standalone and SMP variants of ThreadX, along with the full CMake build and test infrastructure needed to run the regression suite on Windows. New ports Win64 standalone (ports/win64/vs_2022): self-contained Windows simulation port using Win32 threading primitives as virtual cores. Includes CMake integration, build/test scripts, and MSVC project files. Win64 SMP (ports/win64_smp/vs_2022): multi-core Windows simulation port. Supports up to 4 virtual cores backed by Windows host threads. Scheduler and timer improvements The initial port used coarse polling and synchronous SuspendThread/ResumeThread pairs throughout the scheduler hot path. Several rounds of optimization reduced the SMP regression suite runtime from ~150 s to ~78 s (-48%), with no regressions: - Replaced scheduler polling with an event-driven wake path; switched the simulated timer to one-shot rearming to eliminate catch-up ticks. - Skip SuspendThread when _tx_thread_preempt_disable != 0 (new suspension type 3) -- the primary optimization, yielding up to 7.9x speedup on preemption-heavy tests. - Skip SuspendThread when a thread is spinning on the Win32 critical section (suspension type 4), and fix a stale-TLS bug in _tx_win32_critical_section_obtain that could stamp mutex_access on the wrong virtual core. - Added a 2 ms scheduler event timeout (matching the Linux SMP port) to prevent stalls on any missed SetEvent. - Enabled high-resolution waitable timers (SetWaitableTimerEx) for accurate 100 Hz tick cadence. - Increased TX_WIN32_CONTENTION_PAUSE_COUNT from 64 to 256 to reduce SwitchToThread overhead under heavy CS contention. Build and test infrastructure - Hardened the Windows build wrapper (scripts/build_tx.ps1): invoke Ninja directly for Ninja build trees, fix timeout detection, add a default build timeout, and limit fallback replay to real timeout cases. - Added -Clean support to Windows test scripts to remove stale CTest state before each run. - Skip Visual Studio DevShell re-entry when the active MSVC environment already matches the requested architecture. - Fixed scripts/build_tx.sh (Linux) regression source generation: replaced brittle exact-string insertion with line-based matching so the interrupt dispatcher hook is inserted reliably for both simulator ports. Test suite updates - Introduced test/tx/regression/threadx_test_port.h with portable macros (TX_TEST_POINTER_WORD, TX_TEST_STORE_POINTER) for storing pointers in test arrays on 64-bit targets where ULONG remains 32-bit. - Adjusted pool-capacity and pointer-storage patterns in regression tests to use ALIGN_TYPE-sized slots, making the suite correct on 64-bit hosts. - Restored stricter event flag, sleep, and timer expectations now that port-level fixes make prior Windows accommodations unnecessary. - Tightened SMP watchdog and clean-build timeout defaults. Version metadata Updated Win32, Win64, and Win64 SMP port version strings to 6.5.1.202602. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Co-authored-by: Codex (gpt 5.5) --- CMakeLists.txt | 25 +- cmake/win32.cmake | 12 +- cmake/win64.cmake | 9 + common/src/tx_initialize_high_level.c | 7 +- common/src/tx_initialize_kernel_enter.c | 4 +- common/src/tx_timer_initialize.c | 3 +- common_smp/src/tx_thread_system_resume.c | 1 - common_smp/src/tx_thread_system_suspend.c | 1 - ports/win32/vs_2019/inc/tx_port.h | 105 +- .../vs_2019/src/tx_initialize_low_level.c | 3 +- ports/win64/vs_2022/CMakeLists.txt | 19 + ports/win64/vs_2022/inc/tx_port.h | 630 +++++++++ .../vs_2022/src/tx_initialize_low_level.c | 417 ++++++ .../vs_2022/src/tx_thread_context_restore.c | 180 +++ .../vs_2022/src/tx_thread_context_save.c | 111 ++ .../vs_2022/src/tx_thread_interrupt_control.c | 211 +++ ports/win64/vs_2022/src/tx_thread_schedule.c | 331 +++++ .../win64/vs_2022/src/tx_thread_stack_build.c | 211 +++ .../vs_2022/src/tx_thread_system_return.c | 216 ++++ ports/win64/vs_2022/src/tx_timer_interrupt.c | 151 +++ ports_smp/win64/vs_2022/CMakeLists.txt | 28 + ports_smp/win64/vs_2022/inc/tx_port.h | 532 ++++++++ ports_smp/win64/vs_2022/readme_threadx.txt | 13 + .../vs_2022/src/tx_initialize_low_level.c | 1150 +++++++++++++++++ .../vs_2022/src/tx_thread_context_restore.c | 139 ++ .../vs_2022/src/tx_thread_context_save.c | 83 ++ .../vs_2022/src/tx_thread_interrupt_control.c | 104 ++ .../win64/vs_2022/src/tx_thread_schedule.c | 261 ++++ .../vs_2022/src/tx_thread_smp_core_get.c | 26 + .../vs_2022/src/tx_thread_smp_core_preempt.c | 52 + .../src/tx_thread_smp_current_state_get.c | 49 + .../src/tx_thread_smp_current_thread_get.c | 54 + .../src/tx_thread_smp_initialize_wait.c | 25 + .../src/tx_thread_smp_low_level_initialize.c | 26 + .../win64/vs_2022/src/tx_thread_smp_protect.c | 128 ++ .../vs_2022/src/tx_thread_smp_time_get.c | 27 + .../vs_2022/src/tx_thread_smp_unprotect.c | 73 ++ .../win64/vs_2022/src/tx_thread_stack_build.c | 122 ++ .../vs_2022/src/tx_thread_system_return.c | 117 ++ .../win64/vs_2022/src/tx_timer_interrupt.c | 56 + scripts/build_smp.ps1 | 54 + scripts/build_tx.ps1 | 58 + scripts/test_smp.ps1 | 120 ++ scripts/test_tx.ps1 | 121 ++ scripts/tx_windows_common.ps1 | 941 ++++++++++++++ .../regression/testcontrol_weak_defaults.c | 49 + test/smp/cmake/CMakeLists.txt | 100 +- test/smp/cmake/regression/CMakeLists.txt | 40 +- .../cmake/regression/generate_test_file.cmake | 44 + test/smp/cmake/threadx_smp/CMakeLists.txt | 19 +- .../ports_smp/win64/vs_2022/CMakeLists.txt | 29 + test/smp/regression/testcontrol.c | 109 +- .../threadx_block_memory_basic_test.c | 21 +- ...hreadx_block_memory_error_detection_test.c | 18 +- .../threadx_block_memory_suspension_test.c | 6 +- ...adx_block_memory_suspension_timeout_test.c | 14 +- ...readx_block_memory_thread_terminate_test.c | 6 +- .../threadx_byte_memory_basic_test.c | 36 +- .../threadx_byte_memory_information_test.c | 3 +- .../threadx_byte_memory_prioritize_test.c | 4 +- .../threadx_byte_memory_suspension_test.c | 5 +- ...eadx_byte_memory_suspension_timeout_test.c | 13 +- ...readx_byte_memory_thread_contention_test.c | 10 +- ...hreadx_byte_memory_thread_terminate_test.c | 6 +- .../threadx_event_flag_isr_set_clear_test.c | 4 - .../threadx_event_flag_isr_wait_abort_test.c | 1 - .../threadx_initialize_kernel_setup_test.c | 14 +- ..._random_resume_suspend_exclusion_pt_test.c | 2 + ...smp_random_resume_suspend_exclusion_test.c | 1 - .../threadx_smp_random_resume_suspend_test.c | 2 - .../regression/threadx_smp_relinquish_test.c | 1 - .../regression/threadx_smp_time_slice_test.c | 5 +- .../threadx_thread_basic_execution_test.c | 17 + .../threadx_thread_delayed_suspension_test.c | 2 - .../threadx_thread_multiple_sleep_test.c | 7 +- .../threadx_thread_relinquish_test.c | 5 - .../threadx_thread_sleep_for_100ticks_test.c | 2 - .../threadx_thread_wait_abort_and_isr_test.c | 1 - .../threadx_timer_multiple_accuracy_test.c | 1 - .../regression/threadx_timer_simple_test.c | 1 - test/tx/cmake/CMakeLists.txt | 94 +- test/tx/cmake/regression/CMakeLists.txt | 39 +- .../cmake/regression/generate_test_file.cmake | 42 + test/tx/regression/testcontrol.c | 18 +- .../threadx_block_memory_basic_test.c | 17 +- ...hreadx_block_memory_error_detection_test.c | 18 +- .../threadx_block_memory_suspension_test.c | 6 +- ...adx_block_memory_suspension_timeout_test.c | 6 +- ...readx_block_memory_thread_terminate_test.c | 6 +- .../threadx_byte_memory_basic_test.c | 36 +- .../threadx_byte_memory_information_test.c | 3 +- .../threadx_byte_memory_prioritize_test.c | 4 +- .../threadx_byte_memory_suspension_test.c | 5 +- ...eadx_byte_memory_suspension_timeout_test.c | 5 +- ...readx_byte_memory_thread_contention_test.c | 5 +- ...hreadx_byte_memory_thread_terminate_test.c | 6 +- .../threadx_event_flag_isr_set_clear_test.c | 2 - ...readx_event_flag_suspension_timeout_test.c | 6 +- .../threadx_initialize_kernel_setup_test.c | 21 +- .../threadx_semaphore_timeout_test.c | 2 - test/tx/regression/threadx_test_port.h | 37 + .../threadx_thread_basic_execution_test.c | 21 +- ...readx_thread_simple_sleep_non_clear_test.c | 1 - .../threadx_thread_simple_sleep_test.c | 1 - .../threadx_thread_sleep_for_100ticks_test.c | 1 - .../tx/regression/threadx_time_get_set_test.c | 1 - .../threadx_timer_multiple_accuracy_test.c | 1 - .../regression/threadx_timer_multiple_test.c | 1 - 108 files changed, 7614 insertions(+), 395 deletions(-) create mode 100644 cmake/win64.cmake create mode 100644 ports/win64/vs_2022/CMakeLists.txt create mode 100644 ports/win64/vs_2022/inc/tx_port.h create mode 100644 ports/win64/vs_2022/src/tx_initialize_low_level.c create mode 100644 ports/win64/vs_2022/src/tx_thread_context_restore.c create mode 100644 ports/win64/vs_2022/src/tx_thread_context_save.c create mode 100644 ports/win64/vs_2022/src/tx_thread_interrupt_control.c create mode 100644 ports/win64/vs_2022/src/tx_thread_schedule.c create mode 100644 ports/win64/vs_2022/src/tx_thread_stack_build.c create mode 100644 ports/win64/vs_2022/src/tx_thread_system_return.c create mode 100644 ports/win64/vs_2022/src/tx_timer_interrupt.c create mode 100644 ports_smp/win64/vs_2022/CMakeLists.txt create mode 100644 ports_smp/win64/vs_2022/inc/tx_port.h create mode 100644 ports_smp/win64/vs_2022/readme_threadx.txt create mode 100644 ports_smp/win64/vs_2022/src/tx_initialize_low_level.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_context_restore.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_context_save.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_interrupt_control.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_schedule.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_smp_core_get.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_smp_core_preempt.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_smp_current_state_get.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_smp_current_thread_get.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_smp_initialize_wait.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_smp_low_level_initialize.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_smp_protect.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_smp_time_get.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_smp_unprotect.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_stack_build.c create mode 100644 ports_smp/win64/vs_2022/src/tx_thread_system_return.c create mode 100644 ports_smp/win64/vs_2022/src/tx_timer_interrupt.c create mode 100644 scripts/build_smp.ps1 create mode 100644 scripts/build_tx.ps1 create mode 100644 scripts/test_smp.ps1 create mode 100644 scripts/test_tx.ps1 create mode 100644 scripts/tx_windows_common.ps1 create mode 100644 test/shared/regression/testcontrol_weak_defaults.c create mode 100644 test/smp/cmake/regression/generate_test_file.cmake create mode 100644 test/smp/cmake/threadx_smp/ports_smp/win64/vs_2022/CMakeLists.txt create mode 100644 test/tx/cmake/regression/generate_test_file.cmake create mode 100644 test/tx/regression/threadx_test_port.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 5faef86e8..fc9ffb291 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,10 +1,5 @@ cmake_minimum_required(VERSION 3.13 FATAL_ERROR) -# Set up the project -project(threadx - LANGUAGES C ASM -) - if(NOT DEFINED THREADX_ARCH) message(FATAL_ERROR "Error: THREADX_ARCH not defined") endif() @@ -12,6 +7,24 @@ if(NOT DEFINED THREADX_TOOLCHAIN) message(FATAL_ERROR "Error: THREADX_TOOLCHAIN not defined") endif() +# The Windows simulation ports build cleanly without executable try-compiles. +if((THREADX_ARCH STREQUAL "win32") OR (THREADX_ARCH STREQUAL "win64")) + set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) +endif() + +# Set up the project. The Windows simulation ports do not use assembly and +# avoiding ASM language enablement keeps MSVC configuration on the CLI path +# deterministic. +if((THREADX_ARCH STREQUAL "win32") OR (THREADX_ARCH STREQUAL "win64")) + project(threadx + LANGUAGES C + ) +else() + project(threadx + LANGUAGES C ASM + ) +endif() + option(THREADX_SMP "Build ThreadX SMP version" OFF) if(THREADX_SMP) @@ -95,4 +108,4 @@ set(CPACK_SOURCE_IGNORE_FILES ".*~$" ) set(CPACK_VERBATIM_VARIABLES YES) -include(CPack) \ No newline at end of file +include(CPack) diff --git a/cmake/win32.cmake b/cmake/win32.cmake index 974107ad8..fb9d5086a 100644 --- a/cmake/win32.cmake +++ b/cmake/win32.cmake @@ -1,15 +1,9 @@ set(CMAKE_SYSTEM_NAME Windows) -set(CMAKE_SYSTEM_PROCESSOR x86_64) +set(CMAKE_SYSTEM_PROCESSOR x86) set(THREADX_ARCH "win32") set(THREADX_TOOLCHAIN "vs_2019") -set(WIN32_FLAGS "") - -set(CMAKE_C_FLAGS "${WIN32_FLAGS} " CACHE INTERNAL "c compiler flags") -set(CMAKE_CXX_FLAGS "${WIN32_FLAGS} -fno-rtti -fno-exceptions" CACHE INTERNAL "cxx compiler flags") -set(CMAKE_ASM_FLAGS "${WIN32_FLAGS} -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") -set(CMAKE_EXE_LINKER_FLAGS "${WIN32_FLAGS} ${LD_FLAGS}" CACHE INTERNAL "exe link flags") - -# this makes the test compiles use static library option so that we don't need to pre-set linker flags and scripts +# This makes the test compiles use the static library option so that the +# compiler environment can be discovered from the active MSVC shell. set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) diff --git a/cmake/win64.cmake b/cmake/win64.cmake new file mode 100644 index 000000000..5ba9988c5 --- /dev/null +++ b/cmake/win64.cmake @@ -0,0 +1,9 @@ +set(CMAKE_SYSTEM_NAME Windows) +set(CMAKE_SYSTEM_PROCESSOR AMD64) + +set(THREADX_ARCH "win64") +set(THREADX_TOOLCHAIN "vs_2022") + +# This makes the test compiles use the static library option so that the +# compiler environment can be discovered from the active MSVC shell. +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) diff --git a/common/src/tx_initialize_high_level.c b/common/src/tx_initialize_high_level.c index 77bc3ed78..6de5eed52 100644 --- a/common/src/tx_initialize_high_level.c +++ b/common/src/tx_initialize_high_level.c @@ -111,17 +111,22 @@ VOID _tx_initialize_high_level(VOID) /* Initialize the event log, if enabled. */ TX_EL_INITIALIZE + /* Call the thread control initialization function. */ _tx_thread_initialize(); + #ifndef TX_NO_TIMER + /* Call the timer control initialization function. */ _tx_timer_initialize(); + #endif #ifndef TX_DISABLE_REDUNDANT_CLEARING + /* Call the semaphore initialization function. */ _tx_semaphore_initialize(); @@ -139,6 +144,6 @@ VOID _tx_initialize_high_level(VOID) /* Call the mutex initialization function. */ _tx_mutex_initialize(); + #endif } - diff --git a/common/src/tx_initialize_kernel_enter.c b/common/src/tx_initialize_kernel_enter.c index 20dc3017a..bbb073326 100644 --- a/common/src/tx_initialize_kernel_enter.c +++ b/common/src/tx_initialize_kernel_enter.c @@ -101,15 +101,18 @@ VOID _tx_initialize_kernel_enter(VOID) /* Call any port specific preprocessing. */ TX_PORT_SPECIFIC_PRE_INITIALIZATION + /* Invoke the low-level initialization to handle all processor specific initialization issues. */ _tx_initialize_low_level(); + /* Invoke the high-level initialization to exercise all of the ThreadX components and the application's initialization function. */ _tx_initialize_high_level(); + /* Call any port specific post-processing. */ TX_PORT_SPECIFIC_POST_INITIALIZATION } @@ -150,4 +153,3 @@ VOID _tx_initialize_kernel_enter(VOID) TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/common/src/tx_timer_initialize.c b/common/src/tx_timer_initialize.c index 2172b4a64..210888a1e 100644 --- a/common/src/tx_timer_initialize.c +++ b/common/src/tx_timer_initialize.c @@ -245,6 +245,7 @@ UINT status; do { + /* Create the system timer thread. */ status = _tx_thread_create(&_tx_timer_thread, TX_CONST_CHAR_TO_CHAR_POINTER_CONVERT("System Timer Thread"), @@ -253,6 +254,7 @@ UINT status; _tx_timer_stack_start, _tx_timer_stack_size, _tx_timer_priority, _tx_timer_priority, TX_NO_TIME_SLICE, TX_DONT_START); + #ifdef TX_SAFETY_CRITICAL /* Check return from thread create - if an error is detected throw an exception. */ @@ -295,4 +297,3 @@ UINT status; #endif #endif } - diff --git a/common_smp/src/tx_thread_system_resume.c b/common_smp/src/tx_thread_system_resume.c index 256c06f2a..476af380a 100644 --- a/common_smp/src/tx_thread_system_resume.c +++ b/common_smp/src/tx_thread_system_resume.c @@ -960,4 +960,3 @@ VOID _tx_thread_system_ni_resume(TX_THREAD *thread_ptr) _tx_thread_system_resume(thread_ptr); } #endif - diff --git a/common_smp/src/tx_thread_system_suspend.c b/common_smp/src/tx_thread_system_suspend.c index d5bf5cc76..a64b4efa7 100644 --- a/common_smp/src/tx_thread_system_suspend.c +++ b/common_smp/src/tx_thread_system_suspend.c @@ -984,4 +984,3 @@ VOID _tx_thread_system_ni_suspend(TX_THREAD *thread_ptr, ULONG timeout) _tx_thread_system_suspend(thread_ptr); } #endif - diff --git a/ports/win32/vs_2019/inc/tx_port.h b/ports/win32/vs_2019/inc/tx_port.h index 2cd61b434..167da692b 100644 --- a/ports/win32/vs_2019/inc/tx_port.h +++ b/ports/win32/vs_2019/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Win32/Visual */ -/* 6.1 */ +/* 6.5.1.202602 */ /* */ /* AUTHOR */ /* */ @@ -66,6 +66,95 @@ #include #include +/* Define automated coverage test extensions required by the regression tests. */ + +typedef unsigned int TEST_FLAG; +extern TEST_FLAG threadx_byte_allocate_loop_test; +extern TEST_FLAG threadx_byte_release_loop_test; +extern TEST_FLAG threadx_mutex_suspension_put_test; +extern TEST_FLAG threadx_mutex_suspension_priority_test; +#ifndef TX_TIMER_PROCESS_IN_ISR +extern TEST_FLAG threadx_delete_timer_thread; +#endif +extern void abort_and_resume_byte_allocating_thread(void); +extern void abort_all_threads_suspended_on_mutex(void); +extern void suspend_lowest_priority(void); +#ifndef TX_TIMER_PROCESS_IN_ISR +extern void delete_timer_thread(void); +#endif +extern TEST_FLAG test_stack_analyze_flag; +extern TEST_FLAG test_initialize_flag; +extern TEST_FLAG test_forced_mutex_timeout; + +#ifdef TX_REGRESSION_TEST + +#define TX_BYTE_ALLOCATE_EXTENSION if (threadx_byte_allocate_loop_test == ((TEST_FLAG) 1)) \ + { \ + pool_ptr -> tx_byte_pool_owner = TX_NULL; \ + threadx_byte_allocate_loop_test = ((TEST_FLAG) 0); \ + } + +#define TX_BYTE_RELEASE_EXTENSION if (threadx_byte_release_loop_test == ((TEST_FLAG) 1)) \ + { \ + threadx_byte_release_loop_test = ((TEST_FLAG) 0); \ + abort_and_resume_byte_allocating_thread(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_1 if (threadx_mutex_suspension_put_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_put_test = ((TEST_FLAG) 0); \ + abort_all_threads_suspended_on_mutex(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_2 if (test_forced_mutex_timeout == ((TEST_FLAG) 1)) \ + { \ + test_forced_mutex_timeout = ((TEST_FLAG) 0); \ + _tx_thread_wait_abort(mutex_ptr -> tx_mutex_suspension_list); \ + } + +#define TX_MUTEX_PRIORITY_CHANGE_EXTENSION if (threadx_mutex_suspension_priority_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_priority_test = ((TEST_FLAG) 0); \ + suspend_lowest_priority(); \ + } + +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_INITIALIZE_EXTENSION(a) if (threadx_delete_timer_thread == ((TEST_FLAG) 1)) \ + { \ + threadx_delete_timer_thread = ((TEST_FLAG) 0); \ + delete_timer_thread(); \ + (a) = ((UINT) 1); \ + } +#endif + +#define TX_THREAD_STACK_ANALYZE_EXTENSION if (test_stack_analyze_flag == ((TEST_FLAG) 1)) \ + { \ + thread_ptr -> tx_thread_id = ((TEST_FLAG) 0); \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 2)) \ + { \ + stack_ptr = thread_ptr -> tx_thread_stack_start; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 3)) \ + { \ + *stack_ptr = TX_STACK_FILL; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else \ + { \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } + +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION if (test_initialize_flag == ((TEST_FLAG) 1)) \ + { \ + test_initialize_flag = ((TEST_FLAG) 0); \ + return; \ + } + +#endif + /* Define performance metric symbols. */ @@ -101,7 +190,6 @@ #define TX_TIMER_ENABLE_PERFORMANCE_INFO #endif - /* Enable trace info. */ #ifndef TX_ENABLE_EVENT_TRACE @@ -198,7 +286,7 @@ void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long lin #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) #define TX_TRACE_TIME_MASK 0x0000FFFFUL -*/ + */ #ifndef TX_TRACE_TIME_SOURCE #define TX_TRACE_TIME_SOURCE ((ULONG) (_tx_win32_time_stamp.LowPart)); @@ -232,7 +320,6 @@ void _tx_initialize_start_interrupts(void); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION _tx_initialize_start_interrupts(); - /* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING @@ -413,7 +500,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Win32/Visual Studio Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Win32/Visual Studio Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif @@ -437,11 +524,11 @@ extern LARGE_INTEGER _tx_win32_time_stamp; #endif #ifndef TX_TIMER_PERIODIC +#ifdef TX_WIN32_SLOW_TIMER +#define TX_TIMER_PERIODIC TX_WIN32_SLOW_TIMER +#else #define TX_TIMER_PERIODIC 10 #endif - #endif - - - +#endif diff --git a/ports/win32/vs_2019/src/tx_initialize_low_level.c b/ports/win32/vs_2019/src/tx_initialize_low_level.c index dd364d06d..c362b3e73 100644 --- a/ports/win32/vs_2019/src/tx_initialize_low_level.c +++ b/ports/win32/vs_2019/src/tx_initialize_low_level.c @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Codex (gpt 5.4). /**************************************************************************/ /**************************************************************************/ @@ -280,4 +281,4 @@ VOID CALLBACK _tx_win32_timer_interrupt(UINT wTimerID, UINT msg, DWORD dwUser, D /* Call ThreadX context restore for interrupt completion. */ _tx_thread_context_restore(); -} \ No newline at end of file +} diff --git a/ports/win64/vs_2022/CMakeLists.txt b/ports/win64/vs_2022/CMakeLists.txt new file mode 100644 index 000000000..328b89d19 --- /dev/null +++ b/ports/win64/vs_2022/CMakeLists.txt @@ -0,0 +1,19 @@ +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.c + + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/win64/vs_2022/inc/tx_port.h b/ports/win64/vs_2022/inc/tx_port.h new file mode 100644 index 000000000..4cc4e8e07 --- /dev/null +++ b/ports/win64/vs_2022/inc/tx_port.h @@ -0,0 +1,630 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Win64/Visual */ +/* 6.5.1.202602 */ +/* */ +/* AUTHOR */ +/* */ +/* Eclipse ThreadX contributors */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include + +/* Define automated coverage test extensions required by the regression tests. */ + +typedef unsigned int TEST_FLAG; +extern TEST_FLAG threadx_byte_allocate_loop_test; +extern TEST_FLAG threadx_byte_release_loop_test; +extern TEST_FLAG threadx_mutex_suspension_put_test; +extern TEST_FLAG threadx_mutex_suspension_priority_test; +#ifndef TX_TIMER_PROCESS_IN_ISR +extern TEST_FLAG threadx_delete_timer_thread; +#endif +extern void abort_and_resume_byte_allocating_thread(void); +extern void abort_all_threads_suspended_on_mutex(void); +extern void suspend_lowest_priority(void); +#ifndef TX_TIMER_PROCESS_IN_ISR +extern void delete_timer_thread(void); +#endif +extern TEST_FLAG test_stack_analyze_flag; +extern TEST_FLAG test_initialize_flag; +extern TEST_FLAG test_forced_mutex_timeout; + +#ifdef TX_REGRESSION_TEST + +#define TX_BYTE_ALLOCATE_EXTENSION if (threadx_byte_allocate_loop_test == ((TEST_FLAG) 1)) \ + { \ + pool_ptr -> tx_byte_pool_owner = TX_NULL; \ + threadx_byte_allocate_loop_test = ((TEST_FLAG) 0); \ + } + +#define TX_BYTE_RELEASE_EXTENSION if (threadx_byte_release_loop_test == ((TEST_FLAG) 1)) \ + { \ + threadx_byte_release_loop_test = ((TEST_FLAG) 0); \ + abort_and_resume_byte_allocating_thread(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_1 if (threadx_mutex_suspension_put_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_put_test = ((TEST_FLAG) 0); \ + abort_all_threads_suspended_on_mutex(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_2 if (test_forced_mutex_timeout == ((TEST_FLAG) 1)) \ + { \ + test_forced_mutex_timeout = ((TEST_FLAG) 0); \ + _tx_thread_wait_abort(mutex_ptr -> tx_mutex_suspension_list); \ + } + +#define TX_MUTEX_PRIORITY_CHANGE_EXTENSION if (threadx_mutex_suspension_priority_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_priority_test = ((TEST_FLAG) 0); \ + suspend_lowest_priority(); \ + } + +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_INITIALIZE_EXTENSION(a) if (threadx_delete_timer_thread == ((TEST_FLAG) 1)) \ + { \ + threadx_delete_timer_thread = ((TEST_FLAG) 0); \ + delete_timer_thread(); \ + (a) = ((UINT) 1); \ + } +#endif + +#define TX_THREAD_STACK_ANALYZE_EXTENSION if (test_stack_analyze_flag == ((TEST_FLAG) 1)) \ + { \ + thread_ptr -> tx_thread_id = ((TEST_FLAG) 0); \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 2)) \ + { \ + stack_ptr = thread_ptr -> tx_thread_stack_start; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 3)) \ + { \ + *stack_ptr = TX_STACK_FILL; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else \ + { \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } + +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION if (test_initialize_flag == ((TEST_FLAG) 1)) \ + { \ + test_initialize_flag = ((TEST_FLAG) 0); \ + return; \ + } + +#endif + + +/* Define performance metric symbols. */ + +#ifndef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#endif + +#ifndef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +#endif + +#ifndef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +#endif + +#ifndef TX_MUTEX_ENABLE_PERFORMANCE_INFO +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +#endif + +#ifndef TX_QUEUE_ENABLE_PERFORMANCE_INFO +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +#endif + +#ifndef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +#endif + +#ifndef TX_THREAD_ENABLE_PERFORMANCE_INFO +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +#endif + +#ifndef TX_TIMER_ENABLE_PERFORMANCE_INFO +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +#endif + + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; +typedef uint64_t ULONG64; +#define ULONG64_DEFINED + + +/* Override the alignment type to preserve pointer-sized alignment on LLP64. */ + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + + +/* Override the free block marker for byte pools to be a 64-bit constant. */ + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEEULL) + + +/* Add Win32 debug insert prototype. */ + +void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long line); + +#ifndef TX_WIN32_DEBUG_ENABLE + +/* If Win32 debug is not enabled, turn logging into white-space. */ + +#define _tx_win32_debug_entry_insert(a, b, c) + +#endif + + +/* Define the TX_MEMSET macro to remove library reference. */ + +#define TX_MEMSET(a,b,c) { \ + UCHAR *ptr; \ + UCHAR value; \ + UINT i, size; \ + ptr = (UCHAR *) ((VOID *) a); \ + value = (UCHAR) b; \ + size = (UINT) c; \ + for (i = 0; i < size; i++) \ + { \ + *ptr++ = value; \ + } \ + } + + +/* Include windows include file. */ + +#include + +#ifndef TX_WIN32_USE_HIGH_RESOLUTION_TIMER +#define TX_WIN32_USE_HIGH_RESOLUTION_TIMER 1 +#endif + +#ifndef CREATE_WAITABLE_TIMER_HIGH_RESOLUTION +#define CREATE_WAITABLE_TIMER_HIGH_RESOLUTION 0x00000002UL +#endif + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 400 /* Default timer thread stack size - Not used in Win64 port! */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + + */ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ((ULONG) (_tx_win32_time_stamp.LowPart)) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port-specific trace extension to pickup the Windows timer. */ + +#define TX_TRACE_PORT_EXTENSION QueryPerformanceCounter((LARGE_INTEGER *)&_tx_win32_time_stamp); + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Define the Win32-specific initialization code that is expanded in the generic source. */ + +void _tx_initialize_start_interrupts(void); + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION _tx_initialize_start_interrupts(); + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 HANDLE tx_thread_win32_thread_handle; \ + DWORD tx_thread_win32_thread_id; \ + HANDLE tx_thread_win32_thread_run_semaphore; \ + HANDLE tx_thread_win32_thread_start_semaphore; \ + UINT tx_thread_win32_suspension_type; \ + UINT tx_thread_win32_int_disabled_flag; +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Preserve the thread timeout pointer on LLP64 targets. */ + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr; + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_extension_ptr = (VOID *) (t); + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr; + + +struct TX_THREAD_STRUCT; + + +/* Define the Win32 critical section data structure. */ + +typedef struct TX_WIN32_CRITICAL_SECTION_STRUCT +{ + HANDLE tx_win32_critical_section_mutex_handle; + DWORD tx_win32_critical_section_owner; + ULONG tx_win32_critical_section_nested_count; +} TX_WIN32_CRITICAL_SECTION; + + +/* Define Win32-specific critical section APIs. */ + +void _tx_win32_critical_section_obtain(TX_WIN32_CRITICAL_SECTION *critical_section); +void _tx_win32_critical_section_release(TX_WIN32_CRITICAL_SECTION *critical_section); +void _tx_win32_critical_section_release_all(TX_WIN32_CRITICAL_SECTION *critical_section); + + +/* Define post completion processing for tx_thread_delete, so that the Win32 thread resources are properly removed. */ + +#define TX_THREAD_DELETE_PORT_COMPLETION(thread_ptr) \ +{ \ +BOOL win32_status; \ +DWORD exitcode; \ +HANDLE threadrunsemaphore; \ +HANDLE threadhandle; \ +ULONG wait_count; \ + threadhandle = thread_ptr -> tx_thread_win32_thread_handle; \ + threadrunsemaphore = thread_ptr -> tx_thread_win32_thread_run_semaphore; \ + if ((threadhandle != ((HANDLE) 0)) || (threadrunsemaphore != ((HANDLE) 0)))\ + { \ + _tx_thread_interrupt_restore(tx_saved_posture); \ + if (threadhandle != ((HANDLE) 0)) \ + { \ + wait_count = ((ULONG) 0); \ + do \ + { \ + win32_status = GetExitCodeThread(threadhandle, &exitcode); \ + if ((win32_status) && (exitcode != STILL_ACTIVE)) \ + { \ + break; \ + } \ + ResumeThread(threadhandle); \ + if (threadrunsemaphore != ((HANDLE) 0)) \ + { \ + ReleaseSemaphore(threadrunsemaphore, 1, NULL); \ + } \ + Sleep(1); \ + wait_count++; \ + } while (wait_count < ((ULONG) 100)); \ + win32_status = GetExitCodeThread(threadhandle, &exitcode); \ + if ((win32_status) && (exitcode == STILL_ACTIVE)) \ + { \ + (void) TerminateThread(threadhandle, 0U); \ + (void) WaitForSingleObject(threadhandle, INFINITE); \ + } \ + CloseHandle(threadhandle); \ + } \ + if (threadrunsemaphore != ((HANDLE) 0)) \ + { \ + CloseHandle(threadrunsemaphore); \ + } \ + tx_saved_posture = _tx_thread_interrupt_disable(); \ + } \ +} + + +/* Define post completion processing for tx_thread_reset, so that the Win32 thread resources are properly removed. */ + +#define TX_THREAD_RESET_PORT_COMPLETION(thread_ptr) \ +{ \ +BOOL win32_status; \ +DWORD exitcode; \ +HANDLE threadrunsemaphore; \ +HANDLE threadhandle; \ +ULONG wait_count; \ + threadhandle = thread_ptr -> tx_thread_win32_thread_handle; \ + threadrunsemaphore = thread_ptr -> tx_thread_win32_thread_run_semaphore; \ + if ((threadhandle != ((HANDLE) 0)) || (threadrunsemaphore != ((HANDLE) 0)))\ + { \ + _tx_thread_interrupt_restore(tx_saved_posture); \ + if (threadhandle != ((HANDLE) 0)) \ + { \ + wait_count = ((ULONG) 0); \ + do \ + { \ + win32_status = GetExitCodeThread(threadhandle, &exitcode); \ + if ((win32_status) && (exitcode != STILL_ACTIVE)) \ + { \ + break; \ + } \ + ResumeThread(threadhandle); \ + if (threadrunsemaphore != ((HANDLE) 0)) \ + { \ + ReleaseSemaphore(threadrunsemaphore, 1, NULL); \ + } \ + Sleep(1); \ + wait_count++; \ + } while (wait_count < ((ULONG) 100)); \ + win32_status = GetExitCodeThread(threadhandle, &exitcode); \ + if ((win32_status) && (exitcode == STILL_ACTIVE)) \ + { \ + (void) TerminateThread(threadhandle, 0U); \ + (void) WaitForSingleObject(threadhandle, INFINITE); \ + } \ + CloseHandle(threadhandle); \ + } \ + if (threadrunsemaphore != ((HANDLE) 0)) \ + { \ + CloseHandle(threadrunsemaphore); \ + } \ + tx_saved_posture = _tx_thread_interrupt_disable(); \ + } \ +} + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +UINT _tx_thread_interrupt_disable(void); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA UINT tx_saved_posture; + +#define TX_DISABLE tx_saved_posture = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(tx_saved_posture); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "(c) 2026 Eclipse ThreadX contributors. * ThreadX Win64/MSVC Version 6.5.1.202602 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +/* Define externals for the Win32 port of ThreadX. */ + +extern TX_WIN32_CRITICAL_SECTION _tx_win32_critical_section; +extern HANDLE _tx_win32_scheduler_semaphore; +extern HANDLE _tx_win32_scheduler_wake_event; +extern DWORD _tx_win32_scheduler_id; +extern ULONG _tx_win32_global_int_disabled_flag; +extern LARGE_INTEGER _tx_win32_time_stamp; +extern ULONG _tx_win32_system_error; +extern HANDLE _tx_win32_timer_handle; +extern HANDLE _tx_win32_timer_thread_handle; +extern HANDLE _tx_win32_isr_semaphore; +extern UINT _tx_win32_timer_waiting; +extern UINT _tx_win32_timer_id; +extern LARGE_INTEGER _tx_win32_time_stamp; + + +#ifndef TX_WIN32_MEMORY_SIZE +#define TX_WIN32_MEMORY_SIZE 64000 +#endif + +VOID _tx_win32_scheduler_wake(VOID); + +#ifndef TX_TIMER_PERIODIC +#ifdef TX_WIN32_SLOW_TIMER +#define TX_TIMER_PERIODIC TX_WIN32_SLOW_TIMER +#else +#define TX_TIMER_PERIODIC 10 +#endif +#endif + +#endif + + + + + + + + + + + + + + diff --git a/ports/win64/vs_2022/src/tx_initialize_low_level.c b/ports/win64/vs_2022/src/tx_initialize_low_level.c new file mode 100644 index 000000000..b7e965758 --- /dev/null +++ b/ports/win64/vs_2022/src/tx_initialize_low_level.c @@ -0,0 +1,417 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include +#include +#include +#pragma comment (lib, "Winmm.lib") + +/* Define various Win32 objects used by the ThreadX port. */ + +TX_WIN32_CRITICAL_SECTION _tx_win32_critical_section; +HANDLE _tx_win32_scheduler_semaphore; +HANDLE _tx_win32_scheduler_wake_event; +DWORD _tx_win32_scheduler_id; +ULONG _tx_win32_global_int_disabled_flag; +LARGE_INTEGER _tx_win32_time_stamp; +ULONG _tx_win32_system_error; +HANDLE _tx_win32_timer_handle; +HANDLE _tx_win32_timer_thread_handle; +HANDLE _tx_win32_isr_semaphore; +UINT _tx_win32_timer_waiting; +extern TX_THREAD *_tx_thread_current_ptr; + + +/* Define simulated timer interrupt. This is done inside a thread, which is + how other interrupts may be defined as well. See code below for an + example. */ + +UINT _tx_win32_timer_id; +VOID CALLBACK _tx_win32_timer_interrupt(UINT wTimerID, UINT msg, DWORD_PTR dwUser, DWORD_PTR dw1, DWORD_PTR dw2); +static VOID _tx_win32_timer_start(VOID); +static DWORD WINAPI _tx_win32_timer_thread_entry(LPVOID thread_input); + + +#ifdef TX_WIN32_DEBUG_ENABLE + +extern ULONG _tx_thread_system_state; +extern UINT _tx_thread_preempt_disable; +extern TX_THREAD *_tx_thread_current_ptr; +extern TX_THREAD *_tx_thread_execute_ptr; + + +/* Define the maximum size of the Win32 debug array. */ + +#ifndef TX_WIN32_DEBUG_EVENT_SIZE +#define TX_WIN32_DEBUG_EVENT_SIZE 400 +#endif + + +/* Define debug log in order to debug Win32 issues with this port. */ + +typedef struct TX_WIN32_DEBUG_ENTRY_STRUCT +{ + char *tx_win32_debug_entry_action; + LARGE_INTEGER tx_win32_debug_entry_timestamp; + char *tx_win32_debug_entry_file; + unsigned long tx_win32_debug_entry_line; + TX_WIN32_CRITICAL_SECTION tx_win32_debug_entry_critical_section; + unsigned long tx_win32_debug_entry_int_disabled_flag; + ULONG tx_win32_debug_entry_system_state; + UINT tx_win32_debug_entry_preempt_disable; + TX_THREAD *tx_win32_debug_entry_current_thread; + DWORD tx_win32_debug_entry_current_thread_id; + TX_THREAD *tx_win32_debug_entry_execute_thread; + DWORD tx_win32_debug_entry_execute_thread_id; + DWORD tx_win32_debug_entry_running_id; +} TX_WIN32_DEBUG_ENTRY; + + +/* Define the circular array of Win32 debug entries. */ + +TX_WIN32_DEBUG_ENTRY _tx_win32_debug_entry_array[TX_WIN32_DEBUG_EVENT_SIZE]; + + +/* Define the Win32 debug index. */ + +unsigned long _tx_win32_debug_entry_index = 0; + + +/* Now define the debug entry function. */ +void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long line) +{ + + + /* Get the time stamp. */ + QueryPerformanceCounter((LARGE_INTEGER *)&_tx_win32_time_stamp); + + /* Setup the debug entry. */ + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_action = action; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_timestamp = _tx_win32_time_stamp; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_file = file; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_line = line; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_critical_section = _tx_win32_critical_section; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_int_disabled_flag = _tx_win32_global_int_disabled_flag; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_system_state = _tx_thread_system_state; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_preempt_disable = _tx_thread_preempt_disable; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread = _tx_thread_current_ptr; + if (_tx_thread_current_ptr) + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread_id = _tx_thread_current_ptr -> tx_thread_win32_thread_id; + else + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread_id = 0; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread = _tx_thread_execute_ptr; + if (_tx_thread_execute_ptr) + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread_id = _tx_thread_execute_ptr -> tx_thread_win32_thread_id; + else + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread_id = 0; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_running_id = GetCurrentThreadId(); + + /* Now move to the next entry. */ + _tx_win32_debug_entry_index++; + + /* Determine if we need to wrap the list. */ + if (_tx_win32_debug_entry_index >= TX_WIN32_DEBUG_EVENT_SIZE) + { + + /* Yes, wrap the list! */ + _tx_win32_debug_entry_index = 0; + } +} + +#endif + + +/* Define the ThreadX timer interrupt handler. */ + +void _tx_timer_interrupt(void); + + +/* Define other external function references. */ + +VOID _tx_initialize_low_level(VOID); +VOID _tx_thread_context_save(VOID); +VOID _tx_thread_context_restore(VOID); +VOID _tx_win32_scheduler_wake(VOID); + + +/* Define other external variable references. */ + +extern VOID *_tx_initialize_unused_memory; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Win64/MSVC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* CreateMutex Win32 create mutex */ +/* CreateThread Win32 create thread */ +/* CreateSemaphore Win32 create semaphore */ +/* GetCurrentThreadId Win32 get current thread ID */ +/* SetProcessAffinityMask Win32 process affinity set */ +/* SetThreadPriority Win32 set thread priority */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/**************************************************************************/ +VOID _tx_initialize_low_level(VOID) +{ + +/* Deprecate TX_WIN32_MULTI_CORE build option and default to restricting + execution to one core. */ + +#ifndef TX_WIN32_BYPASS_AFFINITY_SETUP + + /* Limit this ThreadX simulation on Win64 to a single core. */ + if (SetProcessAffinityMask(GetCurrentProcess(), ((DWORD_PTR) 1)) == 0) + { + + /* Error restricting the process to one core. */ + printf("ThreadX Win64 error restricting the process to one core!\n"); + while(1) + { + } + } +#endif + + /* Pickup the first available memory address. */ + + /* Save the first available memory address. */ + _tx_initialize_unused_memory = malloc(TX_WIN32_MEMORY_SIZE); + + /* Pickup the unique Id of the current thread, which will also be the Id of the scheduler. */ + _tx_win32_scheduler_id = GetCurrentThreadId(); + + /* Create the system critical section mutex. This is used by the system to block all other access, + analogous to an interrupt lockout on an embedded target. */ + _tx_win32_critical_section.tx_win32_critical_section_mutex_handle = CreateMutex(NULL, FALSE, NULL); + _tx_win32_critical_section.tx_win32_critical_section_nested_count = 0; + _tx_win32_critical_section.tx_win32_critical_section_owner = 0; + if (_tx_win32_critical_section.tx_win32_critical_section_mutex_handle == NULL) + { + printf("ThreadX Win64 error creating critical section mutex!\n"); + while(1) + { + } + } + + /* Create the semaphore that regulates when the scheduler executes. */ + _tx_win32_scheduler_semaphore = CreateSemaphore(NULL, 0, 1, NULL); + _tx_win32_isr_semaphore = CreateSemaphore(NULL, 0, 1, NULL); + if ((_tx_win32_scheduler_semaphore == NULL) || (_tx_win32_isr_semaphore == NULL)) + { + printf("ThreadX Win64 error creating semaphores!\n"); + while(1) + { + } + } + + /* Create the event that wakes the scheduler whenever the ready state changes. */ + _tx_win32_scheduler_wake_event = CreateEvent(NULL, FALSE, FALSE, NULL); + if (_tx_win32_scheduler_wake_event == NULL) + { + printf("ThreadX Win64 error creating scheduler wake event!\n"); + while(1) + { + } + } + + /* Initialize the global interrupt disabled flag. */ + _tx_win32_global_int_disabled_flag = TX_FALSE; + _tx_win32_timer_waiting = TX_FALSE; + + /* Done, return to caller. */ +} + + +/* This routine is called after initialization is complete in order to start + all interrupt threads. Interrupt threads in addition to the timer may + be added to this routine as well. */ + +void _tx_initialize_start_interrupts(void) +{ + TIMECAPS tc; + UINT wTimerRes; + + /* Queries the timer device to determine its resolution. */ + if (timeGetDevCaps(&tc, sizeof(TIMECAPS)) != TIMERR_NOERROR) + { + /* Error; application can't continue. */ + printf("Query timer device error."); + while (1) + { + } + } + + wTimerRes = min(max(tc.wPeriodMin, TX_TIMER_PERIODIC), tc.wPeriodMax); + + /* Request the best available timer resolution for the simulation. */ + if (timeBeginPeriod(wTimerRes) != TIMERR_NOERROR) + { + printf("ThreadX Win64 error configuring timer resolution!\n"); + while (1) + { + } + } + + /* Create the periodic waitable timer used to drive simulated interrupts. */ +#if (TX_WIN32_USE_HIGH_RESOLUTION_TIMER != 0) + _tx_win32_timer_handle = CreateWaitableTimerEx(NULL, NULL, CREATE_WAITABLE_TIMER_HIGH_RESOLUTION, TIMER_ALL_ACCESS); + if (_tx_win32_timer_handle == NULL) +#endif + { + _tx_win32_timer_handle = CreateWaitableTimer(NULL, FALSE, NULL); + } + + if (_tx_win32_timer_handle == NULL) + { + printf("ThreadX Win64 error creating timer handle!\n"); + while (1) + { + } + } + + /* Create the timer thread so interrupts are serialized through one execution context. */ + _tx_win32_timer_thread_handle = CreateThread(NULL, 0, _tx_win32_timer_thread_entry, NULL, 0, NULL); + if (_tx_win32_timer_thread_handle == NULL) + { + printf("ThreadX Win64 error creating timer thread!\n"); + while (1) + { + } + } + + SetThreadPriority(_tx_win32_timer_thread_handle, THREAD_PRIORITY_HIGHEST); + + _tx_win32_timer_id = 1; + + /* Start the first simulated tick. */ + _tx_win32_timer_start(); +} + +/* Define the ThreadX system timer interrupt. Other interrupts may be simulated + in a similar way. */ + +VOID CALLBACK _tx_win32_timer_interrupt(UINT wTimerID, UINT msg, DWORD_PTR dwUser, DWORD_PTR dw1, DWORD_PTR dw2) +{ + TX_PARAMETER_NOT_USED(wTimerID); + TX_PARAMETER_NOT_USED(msg); + TX_PARAMETER_NOT_USED(dwUser); + TX_PARAMETER_NOT_USED(dw1); + TX_PARAMETER_NOT_USED(dw2); + + /* Call ThreadX context save for interrupt preparation. */ + _tx_thread_context_save(); + + /* Call the ThreadX system timer interrupt processing. */ + _tx_timer_interrupt(); + + /* Call ThreadX context restore for interrupt completion. */ + _tx_thread_context_restore(); + + /* Wake the scheduler so it can promptly observe timer-driven work. */ + _tx_win32_scheduler_wake(); +} + + +static DWORD WINAPI _tx_win32_timer_thread_entry(LPVOID thread_input) +{ + TX_PARAMETER_NOT_USED(thread_input); + + /* Drive periodic simulated interrupts from a single thread. */ + while (1) + { + WaitForSingleObject(_tx_win32_timer_handle, INFINITE); + _tx_win32_timer_interrupt(0, 0, 0, 0, 0); + _tx_win32_timer_start(); + } +} + + +VOID _tx_win32_scheduler_wake(VOID) +{ + + /* Wake the scheduler if it is waiting for a state change. */ + if (_tx_win32_scheduler_wake_event != NULL) + { + SetEvent(_tx_win32_scheduler_wake_event); + } +} + + +static VOID _tx_win32_timer_start(VOID) +{ + +LARGE_INTEGER due_time; + + + /* Rearm the host timer relative to "now" to avoid burst catch-up ticks. */ + due_time.QuadPart = -(((LONGLONG) TX_TIMER_PERIODIC) * 10000LL); +#if (TX_WIN32_USE_HIGH_RESOLUTION_TIMER != 0) + if (SetWaitableTimerEx(_tx_win32_timer_handle, &due_time, 0, NULL, NULL, NULL, 0) == 0) +#else + if (SetWaitableTimer(_tx_win32_timer_handle, &due_time, 0, NULL, NULL, FALSE) == 0) +#endif + { + printf("ThreadX Win64 error starting timer!\n"); + while (1) + { + } + } +} + diff --git a/ports/win64/vs_2022/src/tx_thread_context_restore.c b/ports/win64/vs_2022/src/tx_thread_context_restore.c new file mode 100644 index 000000000..9786e7cbe --- /dev/null +++ b/ports/win64/vs_2022/src/tx_thread_context_restore.c @@ -0,0 +1,180 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Win64/MSVC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* ReleaseSemaphore Win32 release semaphore */ +/* ResumeThread Win32 resume thread */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/**************************************************************************/ +VOID _tx_thread_context_restore(VOID) +{ +TX_THREAD *execute_thread; + + /* Enter critical section to ensure other threads are not playing with + the core ThreadX data structures. */ + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + /* Debug entry. */ + _tx_win32_debug_entry_insert("CONTEXT_RESTORE", __FILE__, __LINE__); + + /* Decrement the nested interrupt count. */ + _tx_thread_system_state--; + + /* Pickup the execute thread pointer. */ + execute_thread = _tx_thread_execute_ptr; + + /* Determine if this is the first nested interrupt and if a ThreadX + application thread was running at the time. */ + if ((!_tx_thread_system_state) && (_tx_thread_current_ptr)) + { + + /* Yes, this is the first and last interrupt processed. */ + + /* Check to see if preemption is required. */ + if ((_tx_thread_preempt_disable == 0) && (_tx_thread_current_ptr != _tx_thread_execute_ptr)) + { + + /* Preempt the running application thread. We don't need to suspend the + application thread since that is done in the context save processing. */ + + /* Indicate that this thread was suspended asynchronously. */ + _tx_thread_current_ptr -> tx_thread_win32_suspension_type = 1; + + /* Save the remaining time-slice and disable it. */ + if (_tx_timer_time_slice) + { + + _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; + } + + /* Clear the current thread pointer. */ + _tx_thread_current_ptr = TX_NULL; + + /* Block the timer ISR until the resumed thread has observed the wakeup. */ + _tx_win32_timer_waiting = TX_TRUE; + + /* Wakeup the system thread by setting the system semaphore. */ + ReleaseSemaphore(_tx_win32_scheduler_semaphore, 1, NULL); + _tx_win32_scheduler_wake(); + + /* If the timer made a solicited wakeup ready, let that thread run before + the host timer ISR continues. */ + if ((execute_thread != TX_NULL) && + (execute_thread -> tx_thread_win32_suspension_type == 0)) + { + + /* Release the critical section while the scheduler runs. */ + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + WaitForSingleObject(_tx_win32_isr_semaphore, INFINITE); + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + while (WaitForSingleObject(_tx_win32_isr_semaphore, 0) == WAIT_OBJECT_0) + { + } + } + + /* The timer ISR no longer needs to hold off future ticks. */ + _tx_win32_timer_waiting = TX_FALSE; + } + else + { + + /* Since preemption is not required, resume the interrupted thread. */ + ResumeThread(_tx_thread_current_ptr -> tx_thread_win32_thread_handle); + } + } + else if ((!_tx_thread_system_state) && (execute_thread != TX_NULL)) + { + + /* The timer made a thread ready while the scheduler was idle. Keep the + timer ISR blocked until the solicited wakeup has started running. */ + _tx_win32_timer_waiting = TX_TRUE; + _tx_win32_scheduler_wake(); + + if (execute_thread -> tx_thread_win32_suspension_type == 0) + { + + /* Release the critical section while the scheduler runs. */ + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + WaitForSingleObject(_tx_win32_isr_semaphore, INFINITE); + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + while (WaitForSingleObject(_tx_win32_isr_semaphore, 0) == WAIT_OBJECT_0) + { + } + } + + _tx_win32_timer_waiting = TX_FALSE; + } + + /* Leave Win32 critical section. */ + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); +} + + diff --git a/ports/win64/vs_2022/src/tx_thread_context_save.c b/ports/win64/vs_2022/src/tx_thread_context_save.c new file mode 100644 index 000000000..84f2d2902 --- /dev/null +++ b/ports/win64/vs_2022/src/tx_thread_context_save.c @@ -0,0 +1,111 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Win64/MSVC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* SuspendThread Win32 thread suspend */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/**************************************************************************/ +VOID _tx_thread_context_save(VOID) +{ + +TX_THREAD *thread_ptr; + + + /* Enter critical section to ensure other threads are not playing with + the core ThreadX data structures. */ + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + /* Debug entry. */ + _tx_win32_debug_entry_insert("CONTEXT_SAVE", __FILE__, __LINE__); + + /* Pickup the current thread pointer. */ + thread_ptr = _tx_thread_current_ptr; + + /* If an application thread is running, suspend it to simulate preemption. */ + if ((thread_ptr) && (_tx_thread_system_state == 0)) + { + + /* Yes, this is the first interrupt and an application thread is running... + suspend it! */ + + /* Suspend the thread to simulate preemption. Note that the thread is suspended BEFORE the protection get + flag is checked to ensure there is not a race condition between this thread and the update of that flag. */ + SuspendThread(thread_ptr -> tx_thread_win32_thread_handle); + + /* Debug entry. */ + _tx_win32_debug_entry_insert("CONTEXT_SAVE-suspend_thread", __FILE__, __LINE__); + + } + + /* Increment the nested interrupt condition. */ + _tx_thread_system_state++; + + /* Exit Win32 critical section. */ + _tx_win32_critical_section_release(&_tx_win32_critical_section); +} + + diff --git a/ports/win64/vs_2022/src/tx_thread_interrupt_control.c b/ports/win64/vs_2022/src/tx_thread_interrupt_control.c new file mode 100644 index 000000000..ab50a3c9e --- /dev/null +++ b/ports/win64/vs_2022/src/tx_thread_interrupt_control.c @@ -0,0 +1,211 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +#include + +/* Define small routines used for the TX_DISABLE/TX_RESTORE macros. */ + +UINT _tx_thread_interrupt_disable(void) +{ + +UINT previous_value; + + + previous_value = _tx_thread_interrupt_control(TX_INT_DISABLE); + return(previous_value); +} + + +VOID _tx_thread_interrupt_restore(UINT previous_posture) +{ + + previous_posture = _tx_thread_interrupt_control(previous_posture); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Win64/MSVC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* ExitThread Win32 thread exit */ +/* GetCurrentThread Win32 get current thread */ +/* GetCurrentThreadId Win32 get current thread ID */ +/* GetThreadPriority Win32 get thread priority */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* _tx_win32_critical_section_release_all */ +/* Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/**************************************************************************/ +UINT _tx_thread_interrupt_control(UINT new_posture) +{ + +UINT old_posture; +HANDLE threadhandle; +int threadpriority; +DWORD threadid; +TX_THREAD *thread_ptr; + + + /* Enter Win32 critical section. */ + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + +#ifdef TX_WIN32_DEBUG_ENABLE + + /* Determine if this is a disable or enable request. */ + if (new_posture == TX_INT_ENABLE) + { + /* Enable. */ + _tx_win32_debug_entry_insert("RESTORE", __FILE__, __LINE__); + } + else + { + /* Disable. */ + _tx_win32_debug_entry_insert("DISABLE", __FILE__, __LINE__); + } +#endif + + /* Determine if the thread was terminated. */ + + /* Pickup the handle of the current thread. */ + threadhandle = GetCurrentThread(); + + /* Pickup the current thread pointer. */ + thread_ptr = _tx_thread_current_ptr; + + /* Pickup the priority of the current thread. */ + threadpriority = GetThreadPriority(threadhandle); + + /* Pickup the ID of the current thread. */ + threadid = GetCurrentThreadId(); + + /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not + match the current thread pointer. */ + if ((threadpriority == THREAD_PRIORITY_LOWEST) && + ((!thread_ptr) || (thread_ptr -> tx_thread_win32_thread_id != threadid))) + { + + /* This indicates the Win32 thread was actually terminated by ThreadX is only + being allowed to run in order to cleanup its resources. */ + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + + /* Exit this thread. */ + ExitThread(0); + } + + /* Determine the current interrupt lockout condition. */ + if (_tx_win32_critical_section.tx_win32_critical_section_nested_count == 1) + { + + /* First pass through, interrupts are enabled. */ + old_posture = TX_INT_ENABLE; + } + else + { + + /* Interrupts are disabled. */ + old_posture = TX_INT_DISABLE; + } + + /* First, determine if this call is from a non-thread. */ + if (_tx_thread_system_state) + { + + /* Determine how to apply the new posture. */ + if (new_posture == TX_INT_ENABLE) + { + + /* Clear the disabled flag. */ + _tx_win32_global_int_disabled_flag = TX_FALSE; + + /* Determine if the critical section is locked. */ + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + } + else if (new_posture == TX_INT_DISABLE) + { + + /* Set the disabled flag. */ + _tx_win32_global_int_disabled_flag = TX_TRUE; + } + } + else if (thread_ptr) + { + + /* Determine how to apply the new posture. */ + if (new_posture == TX_INT_ENABLE) + { + + /* Clear the disabled flag. */ + _tx_thread_current_ptr -> tx_thread_win32_int_disabled_flag = TX_FALSE; + + /* Determine if the critical section is locked. */ + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + } + else if (new_posture == TX_INT_DISABLE) + { + + /* Set the disabled flag. */ + _tx_thread_current_ptr -> tx_thread_win32_int_disabled_flag = TX_TRUE; + } + } + + /* Return the previous interrupt disable posture. */ + return(old_posture); +} + + diff --git a/ports/win64/vs_2022/src/tx_thread_schedule.c b/ports/win64/vs_2022/src/tx_thread_schedule.c new file mode 100644 index 000000000..d08305ee8 --- /dev/null +++ b/ports/win64/vs_2022/src/tx_thread_schedule.c @@ -0,0 +1,331 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +static VOID _tx_win32_semaphore_reset(HANDLE semaphore_handle); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Win64/MSVC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* ReleaseSemaphore Win32 release semaphore */ +/* ResumeThread Win32 resume thread */ +/* _tx_win32_scheduler_wake Wake scheduler waiters */ +/* WaitForSingleObject Win32 wait on a semaphore */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/**************************************************************************/ +VOID _tx_thread_schedule(VOID) +{ +DWORD wait_status; + + + /* Loop forever. */ + while(1) + { + + /* Wait for a thread to execute and all ISRs to complete. */ + while(1) + { + + + /* Enter Win32 critical section. */ + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + /* Debug entry. */ + _tx_win32_debug_entry_insert("SCHEDULE-wake_up", __FILE__, __LINE__); + + /* Determine if there is a thread ready to execute AND all ISRs + are complete. */ + if ((_tx_thread_execute_ptr != TX_NULL) && (_tx_thread_system_state == 0)) + { + + /* Get out of this loop and schedule the thread! */ + break; + } + else + { + + /* Leave the critical section. */ + _tx_win32_critical_section_release(&_tx_win32_critical_section); + + /* Wait for the next scheduling state change. */ + WaitForSingleObject(_tx_win32_scheduler_wake_event, INFINITE); + } + } + + /* Yes! We have a thread to execute. Note that the critical section is already + active from the scheduling loop above. */ + + /* Setup the current thread pointer. */ + _tx_thread_current_ptr = _tx_thread_execute_ptr; + + /* Increment the run count for this thread. */ + _tx_thread_current_ptr -> tx_thread_run_count++; + + /* Setup time-slice, if present. */ + _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; + + /* Determine how the thread was suspended. */ + if (_tx_thread_current_ptr -> tx_thread_win32_suspension_type) + { + + /* Debug entry. */ + _tx_win32_debug_entry_insert("SCHEDULE-resume_thread", __FILE__, __LINE__); + + /* Pseudo interrupt suspension. The thread is not waiting on + its run semaphore. */ + ResumeThread(_tx_thread_current_ptr -> tx_thread_win32_thread_handle); + } + else + { + + /* Debug entry. */ + _tx_win32_debug_entry_insert("SCHEDULE-release_sem", __FILE__, __LINE__); + + /* Clear any stale wakeup acknowledgements before this solicited resume. */ + _tx_win32_semaphore_reset(_tx_thread_current_ptr -> tx_thread_win32_thread_start_semaphore); + _tx_win32_semaphore_reset(_tx_thread_current_ptr -> tx_thread_win32_thread_run_semaphore); + + /* Let the thread run again by releasing its run semaphore. */ + if (ReleaseSemaphore(_tx_thread_current_ptr -> tx_thread_win32_thread_run_semaphore, 1, NULL) == 0) + { + + /* Increment the system error counter. */ + _tx_win32_system_error++; + } + + /* Let the solicited wakeup reach ThreadX before the timer ISR advances again. */ + if (_tx_win32_timer_waiting) + { + + /* Wait for the thread to acknowledge the wakeup and then release the ISR. */ + wait_status = WaitForSingleObject(_tx_thread_current_ptr -> tx_thread_win32_thread_start_semaphore, INFINITE); + if (ReleaseSemaphore(_tx_win32_isr_semaphore, 1, NULL) == 0) + { + + /* Increment the system error counter. */ + _tx_win32_system_error++; + } + + if (wait_status != WAIT_OBJECT_0) + { + + /* Increment the system error counter. */ + _tx_win32_system_error++; + } + } + } + + /* Debug entry. */ + _tx_win32_debug_entry_insert("SCHEDULE-self_suspend_sem", __FILE__, __LINE__); + + /* Exit Win32 critical section. */ + _tx_win32_critical_section_release(&_tx_win32_critical_section); + + /* Now suspend the main thread so the application thread can run. */ + WaitForSingleObject(_tx_win32_scheduler_semaphore, INFINITE); + } +} + + +static VOID _tx_win32_semaphore_reset(HANDLE semaphore_handle) +{ + + /* Drain any stale semaphore count from a previous host-side wakeup. */ + while (WaitForSingleObject(semaphore_handle, 0) == WAIT_OBJECT_0) + { + } +} + + +/* Define the ThreadX Win32 critical section get, release, and release all functions. */ + +void _tx_win32_critical_section_obtain(TX_WIN32_CRITICAL_SECTION *critical_section) +{ + /* Is the protection owned? */ + if (critical_section -> tx_win32_critical_section_owner == GetCurrentThreadId()) + { + + /* Simply increment the nested counter. */ + critical_section -> tx_win32_critical_section_nested_count++; + } + else + { + + /* Get the Win32 critical section. */ + if (WaitForSingleObject(critical_section -> tx_win32_critical_section_mutex_handle, INFINITE) != WAIT_OBJECT_0) + { + + /* Increment the system error counter and stop when the mutex cannot be acquired. */ + _tx_win32_system_error++; + while(1) + { + } + } + + /* At this point we have the mutex. */ + + /* Increment the nesting counter. */ + critical_section -> tx_win32_critical_section_nested_count = 1; + + /* Remember the owner. */ + critical_section -> tx_win32_critical_section_owner = GetCurrentThreadId(); + } +} + + +void _tx_win32_critical_section_release(TX_WIN32_CRITICAL_SECTION *critical_section) +{ + + + /* Ensure the caller is the mutex owner. */ + if (critical_section -> tx_win32_critical_section_owner == GetCurrentThreadId()) + { + + /* Determine if there is protection. */ + if (critical_section -> tx_win32_critical_section_nested_count) + { + + /* Decrement the nesting counter. */ + critical_section -> tx_win32_critical_section_nested_count--; + + /* Determine if the critical section is now being released. */ + if (critical_section -> tx_win32_critical_section_nested_count == 0) + { + + /* Yes, it is being released clear the owner. */ + critical_section -> tx_win32_critical_section_owner = 0; + + /* Finally, release the mutex. */ + if (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) != TX_TRUE) + { + + /* Increment the system error counter. */ + _tx_win32_system_error++; + } + + /* Just in case, make sure there the mutex is not owned. */ + while (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) == TX_TRUE) + { + + /* Increment the system error counter. */ + _tx_win32_system_error++; + } + } + } + } + else + { + + /* Increment the system error counter. */ + _tx_win32_system_error++; + } +} + + +void _tx_win32_critical_section_release_all(TX_WIN32_CRITICAL_SECTION *critical_section) +{ + + /* Ensure the caller is the mutex owner. */ + if (critical_section -> tx_win32_critical_section_owner == GetCurrentThreadId()) + { + + /* Determine if there is protection. */ + if (critical_section -> tx_win32_critical_section_nested_count) + { + + /* Clear the nesting counter. */ + critical_section -> tx_win32_critical_section_nested_count = 0; + + /* Yes, it is being release clear the owner. */ + critical_section -> tx_win32_critical_section_owner = 0; + + /* Finally, release the mutex. */ + if (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) != TX_TRUE) + { + + /* Increment the system error counter. */ + _tx_win32_system_error++; + } + + /* Just in case, make sure there the mutex is not owned. */ + while (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) == TX_TRUE) + { + + /* Increment the system error counter. */ + _tx_win32_system_error++; + } + } + } + else + { + + /* Increment the system error counter. */ + _tx_win32_system_error++; + } +} + + diff --git a/ports/win64/vs_2022/src/tx_thread_stack_build.c b/ports/win64/vs_2022/src/tx_thread_stack_build.c new file mode 100644 index 000000000..c50f7754d --- /dev/null +++ b/ports/win64/vs_2022/src/tx_thread_stack_build.c @@ -0,0 +1,211 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include + + +/* Prototype for new thread entry function. */ + +DWORD WINAPI _tx_win32_thread_entry(LPVOID p); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Win64/MSVC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* CreateThread Win32 create thread */ +/* ResumeThread Win32 resume thread */ +/* SetThreadPriority Win32 set thread priority */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* _tx_thread_reset Reset thread service */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ + + /* Create a Win32 thread for the application thread. */ + thread_ptr -> tx_thread_win32_thread_handle = + CreateThread(NULL, 0, _tx_win32_thread_entry, (LPVOID) thread_ptr, CREATE_SUSPENDED, + &(thread_ptr -> tx_thread_win32_thread_id)); + + /* Check for a good thread create. */ + if (!thread_ptr -> tx_thread_win32_thread_handle) + { + + /* Display an error message. */ + printf("ThreadX Win32 error creating thread!\n"); + while(1) + { + } + } + + /* Otherwise, we have a good thread create. Now set the priority to + a lower level. */ + SetThreadPriority(thread_ptr -> tx_thread_win32_thread_handle, THREAD_PRIORITY_LOWEST); + + /* Create the run semaphore for the thread. This will allow the scheduler + control over when the thread actually runs. */ + thread_ptr -> tx_thread_win32_thread_run_semaphore = CreateSemaphore(NULL, 0, 1, NULL); + + /* Determine if the run semaphore was created successfully. */ + if (!thread_ptr -> tx_thread_win32_thread_run_semaphore) + { + + /* Display an error message. */ + printf("ThreadX Win32 error creating thread running semaphore!\n"); + while(1) + { + } + } + + /* Create the scheduler acknowledgement semaphore for this thread. */ + thread_ptr -> tx_thread_win32_thread_start_semaphore = CreateSemaphore(NULL, 0, 1, NULL); + + /* Determine if the start semaphore was created successfully. */ + if (!thread_ptr -> tx_thread_win32_thread_start_semaphore) + { + + /* Display an error message. */ + printf("ThreadX Win32 error creating thread start semaphore!\n"); + while(1) + { + } + } + + /* Setup the thread suspension type to solicited thread suspension. + Pseudo interrupt handlers will suspend with this field set to 1. */ + thread_ptr -> tx_thread_win32_suspension_type = 0; + + /* Clear the disabled count that will keep track of the + tx_interrupt_control nesting. */ + thread_ptr -> tx_thread_win32_int_disabled_flag = 0; + + /* Setup a fake thread stack pointer. */ + thread_ptr -> tx_thread_stack_ptr = (VOID *) (((CHAR *) thread_ptr -> tx_thread_stack_end) - 8); + + /* Clear the first word of the stack. */ + *(((ULONG *) thread_ptr -> tx_thread_stack_ptr) - 1) = 0; + + /* Make the thread initially ready so it will run to the initial wait on + its run semaphore. */ + ResumeThread(thread_ptr -> tx_thread_win32_thread_handle); + + /* Wait until the host thread is parked at the controlled handoff point + before ThreadX can schedule it. */ + if (WaitForSingleObject(thread_ptr -> tx_thread_win32_thread_start_semaphore, INFINITE) != WAIT_OBJECT_0) + { + + /* Display an error message. */ + printf("ThreadX Win32 error synchronizing thread startup!\n"); + while(1) + { + } + } +} + + +DWORD WINAPI _tx_win32_thread_entry(LPVOID ptr) +{ + +TX_THREAD *thread_ptr; +TX_THREAD *current_thread_ptr; +HANDLE threadhandle; +int threadpriority; +DWORD threadid; + + /* Pickup the current thread pointer. */ + thread_ptr = (TX_THREAD *) ptr; + + /* Tell the creator that this host thread has reached the controlled + handoff point and is ready to be scheduled. */ + ReleaseSemaphore(thread_ptr -> tx_thread_win32_thread_start_semaphore, 1, NULL); + + /* Now suspend the thread initially. If the thread has already + been scheduled, this will return immediately. */ + WaitForSingleObject(thread_ptr -> tx_thread_win32_thread_run_semaphore, INFINITE); + + /* Acknowledge that the host thread is now able to execute ThreadX code. */ + ReleaseSemaphore(thread_ptr -> tx_thread_win32_thread_start_semaphore, 1, NULL); + + /* A deleted host thread can be released only to let it exit. In notify-enabled + builds, the first TX_DISABLE in _tx_thread_shell_entry catches this path. + When callbacks are disabled, perform the same check before the shell calls + the stale ThreadX entry function. */ + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + threadhandle = GetCurrentThread(); + threadpriority = GetThreadPriority(threadhandle); + threadid = GetCurrentThreadId(); + current_thread_ptr = _tx_thread_current_ptr; + if ((threadpriority == THREAD_PRIORITY_LOWEST) && + ((current_thread_ptr == TX_NULL) || (current_thread_ptr -> tx_thread_win32_thread_id != threadid))) + { + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + ExitThread(0); + } + _tx_win32_critical_section_release(&_tx_win32_critical_section); + + /* Call ThreadX thread entry point. */ + _tx_thread_shell_entry(); + + return EXIT_SUCCESS; +} + + diff --git a/ports/win64/vs_2022/src/tx_thread_system_return.c b/ports/win64/vs_2022/src/tx_thread_system_return.c new file mode 100644 index 000000000..7a8fc89c0 --- /dev/null +++ b/ports/win64/vs_2022/src/tx_thread_system_return.c @@ -0,0 +1,216 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Win64/MSVC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* _tx_win32_critical_section_release_all */ +/* Release critical section */ +/* ExitThread Win32 thread exit */ +/* GetCurrentThread Win32 get current thread */ +/* GetCurrentThreadId Win32 get current thread ID */ +/* GetThreadPriority Win32 get thread priority */ +/* ReleaseSemaphore Win32 release semaphore */ +/* WaitForSingleObject Win32 wait on semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/**************************************************************************/ +VOID _tx_thread_system_return(VOID) +{ + +TX_THREAD *temp_thread_ptr; +HANDLE temp_run_semaphore; +UINT temp_thread_state; +HANDLE threadhandle; +int threadpriority; +DWORD threadid; + + + /* Enter Win32 critical section. */ + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + /* Pickup the handle of the current thread. */ + threadhandle = GetCurrentThread(); + + /* Debug entry. */ + _tx_win32_debug_entry_insert("SYSTEM_RETURN", __FILE__, __LINE__); + + /* First, determine if the thread was terminated. */ + + /* Pickup the priority of the current thread. */ + threadpriority = GetThreadPriority(threadhandle); + + /* Pickup the ID of the current thread. */ + threadid = GetCurrentThreadId(); + + /* Pickup the current thread pointer. */ + temp_thread_ptr = _tx_thread_current_ptr; + + /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not + match the current thread pointer. */ + if ((threadpriority == THREAD_PRIORITY_LOWEST) && + ((!temp_thread_ptr) || (temp_thread_ptr -> tx_thread_win32_thread_id != threadid))) + { + + /* This indicates the Win32 thread was actually terminated by ThreadX and is only + being allowed to run in order to cleanup its resources. */ + + /* Release critical section. */ + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + + /* Exit thread. */ + ExitThread(0); + } + + /* Determine if the time-slice is active. */ + if (_tx_timer_time_slice) + { + + /* Preserve current remaining time-slice for the thread and clear the current time-slice. */ + temp_thread_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; + } + + /* Save the run semaphore into a temporary variable as well. */ + temp_run_semaphore = temp_thread_ptr -> tx_thread_win32_thread_run_semaphore; + + /* Pickup the current thread state. */ + temp_thread_state = temp_thread_ptr -> tx_thread_state; + + /* Setup the suspension type for this thread. */ + temp_thread_ptr -> tx_thread_win32_suspension_type = 0; + + /* Set the current thread pointer to NULL. */ + _tx_thread_current_ptr = TX_NULL; + + /* Debug entry. */ + _tx_win32_debug_entry_insert("SYSTEM_RETURN-release_sem", __FILE__, __LINE__); + + /* Release the semaphore that the main scheduling thread is waiting + on. Note that the main scheduling algorithm will take care of + setting the current thread pointer to NULL. */ + ReleaseSemaphore(_tx_win32_scheduler_semaphore, 1, NULL); + _tx_win32_scheduler_wake(); + + /* Leave Win32 critical section. */ + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + + /* Determine if the thread was self-terminating. */ + if (temp_thread_state == TX_TERMINATED) + { + + /* Exit the thread instead of waiting on the semaphore! */ + ExitThread(0); + } + + /* Wait on the run semaphore for this thread. This won't get set again + until the thread is scheduled. */ + WaitForSingleObject(temp_run_semaphore, INFINITE); + + /* Acknowledge that the thread is once again executing ThreadX code. */ + ReleaseSemaphore(temp_thread_ptr -> tx_thread_win32_thread_start_semaphore, 1, NULL); + + /* Enter Win32 critical section. */ + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + /* Debug entry. */ + _tx_win32_debug_entry_insert("SYSTEM_RETURN-wake_up", __FILE__, __LINE__); + + /* Determine if the thread was terminated. */ + + /* Pickup the current thread pointer. */ + temp_thread_ptr = _tx_thread_current_ptr; + + /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not + match the current thread pointer. */ + if ((threadpriority == THREAD_PRIORITY_LOWEST) && + ((!temp_thread_ptr) || (temp_thread_ptr -> tx_thread_win32_thread_id != threadid))) + { + + /* Leave Win32 critical section. */ + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + + /* This indicates the Win32 thread was actually terminated by ThreadX and is only + being allowed to run in order to cleanup its resources. */ + ExitThread(0); + } + + /* Now determine if the application thread last had interrupts disabled. */ + + /* Debug entry. */ + _tx_win32_debug_entry_insert("SYSTEM_RETURN-finish", __FILE__, __LINE__); + + /* Determine if this thread had interrupts disabled. */ + if (!_tx_thread_current_ptr -> tx_thread_win32_int_disabled_flag) + { + + /* Leave Win32 critical section. */ + _tx_win32_critical_section_release(&_tx_win32_critical_section); + } +} + + diff --git a/ports/win64/vs_2022/src/tx_timer_interrupt.c b/ports/win64/vs_2022/src/tx_timer_interrupt.c new file mode 100644 index 000000000..6814334b5 --- /dev/null +++ b/ports/win64/vs_2022/src/tx_timer_interrupt.c @@ -0,0 +1,151 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Win64/MSVC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/**************************************************************************/ +VOID _tx_timer_interrupt(VOID) +{ + + + /* Enter critical section to ensure other threads are not playing with + the core ThreadX data structures. */ + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + /* Debug entry. */ + _tx_win32_debug_entry_insert("TIMER INTERRUPT", __FILE__, __LINE__); + + /* Increment the system clock. */ + _tx_timer_system_clock++; + + /* Test for time-slice expiration. */ + if (_tx_timer_time_slice) + { + + /* Decrement the time_slice. */ + _tx_timer_time_slice--; + + /* Check for expiration. */ + if (_tx_timer_time_slice == 0) + { + + /* Set the time-slice expired flag. */ + _tx_timer_expired_time_slice = TX_TRUE; + } + } + + /* Test for timer expiration. */ + if (*_tx_timer_current_ptr) + { + + /* Set expiration flag. */ + _tx_timer_expired = TX_TRUE; + } + else + { + + /* No timer expired, increment the timer pointer. */ + _tx_timer_current_ptr++; + + /* Check for wrap-around. */ + if (_tx_timer_current_ptr == _tx_timer_list_end) + { + + /* Wrap to beginning of list. */ + _tx_timer_current_ptr = _tx_timer_list_start; + } + } + + /* See if anything has expired. */ + if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { + + /* Did a timer expire? */ + if (_tx_timer_expired) + { + + /* Process timer expiration. */ + _tx_timer_expiration_process(); + } + + /* Did time slice expire? */ + if (_tx_timer_expired_time_slice) + { + + /* Time slice interrupted thread. */ + _tx_thread_time_slice(); + } + } + + /* Exit Win32 critical section. */ + _tx_win32_critical_section_release(&_tx_win32_critical_section); +} + + diff --git a/ports_smp/win64/vs_2022/CMakeLists.txt b/ports_smp/win64/vs_2022/CMakeLists.txt new file mode 100644 index 000000000..982f9684f --- /dev/null +++ b/ports_smp/win64/vs_2022/CMakeLists.txt @@ -0,0 +1,28 @@ +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_core_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_core_preempt.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_current_state_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_current_thread_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_initialize_wait.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_low_level_initialize.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_protect.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_time_get.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_smp_unprotect.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.c + + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports_smp/win64/vs_2022/inc/tx_port.h b/ports_smp/win64/vs_2022/inc/tx_port.h new file mode 100644 index 000000000..d9790f35e --- /dev/null +++ b/ports_smp/win64/vs_2022/inc/tx_port.h @@ -0,0 +1,532 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/************* Define ThreadX SMP constants. *************/ + +#define TX_DISABLE_INLINE + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xFU +#endif + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT +#define TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC +#include "tx_thread_smp_core_wakeup.h" +#else +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + +#define INLINE_DECLARE __inline + +/************* End ThreadX SMP constants. *************/ + + +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned long long ULONG64; +#define ULONG64_DEFINED + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEEULL) + + +#include +#include +#include + +#ifndef __GNUC__ +#ifndef __attribute__ +#define __attribute__(a) +#endif +#endif + +typedef unsigned int TEST_FLAG; +extern TEST_FLAG threadx_byte_allocate_loop_test; +extern TEST_FLAG threadx_byte_release_loop_test; +extern TEST_FLAG threadx_mutex_suspension_put_test; +extern TEST_FLAG threadx_mutex_suspension_priority_test; +#ifndef TX_TIMER_PROCESS_IN_ISR +extern TEST_FLAG threadx_delete_timer_thread; +#endif +extern void abort_and_resume_byte_allocating_thread(void); +extern void abort_all_threads_suspended_on_mutex(void); +extern void suspend_lowest_priority(void); +#ifndef TX_TIMER_PROCESS_IN_ISR +extern void delete_timer_thread(void); +#endif +extern TEST_FLAG test_stack_analyze_flag; +extern TEST_FLAG test_initialize_flag; +extern TEST_FLAG test_forced_mutex_timeout; +extern UINT mutex_priority_change_extension_selection; +extern UINT priority_change_extension_selection; + +#ifdef TX_REGRESSION_TEST + +#define TX_PORT_SPECIFIC_MEMORY_SYNCHRONIZATION other_core_status = other_core_status + _tx_thread_system_state[0]; \ + _tx_thread_system_state[0] = 0; + +#define TX_BYTE_ALLOCATE_EXTENSION if (threadx_byte_allocate_loop_test == ((TEST_FLAG) 1)) \ + { \ + pool_ptr -> tx_byte_pool_owner = TX_NULL; \ + threadx_byte_allocate_loop_test = ((TEST_FLAG) 0); \ + } + +#define TX_BYTE_RELEASE_EXTENSION if (threadx_byte_release_loop_test == ((TEST_FLAG) 1)) \ + { \ + threadx_byte_release_loop_test = ((TEST_FLAG) 0); \ + abort_and_resume_byte_allocating_thread(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_1 if (threadx_mutex_suspension_put_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_put_test = ((TEST_FLAG) 0); \ + abort_all_threads_suspended_on_mutex(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_2 if (test_forced_mutex_timeout == ((TEST_FLAG) 1)) \ + { \ + test_forced_mutex_timeout = ((TEST_FLAG) 0); \ + _tx_thread_wait_abort(mutex_ptr -> tx_mutex_suspension_list); \ + } + +#define TX_MUTEX_PRIORITY_CHANGE_EXTENSION if (threadx_mutex_suspension_priority_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_priority_test = ((TEST_FLAG) 0); \ + if (mutex_priority_change_extension_selection == 2U) \ + original_priority = new_priority; \ + if (mutex_priority_change_extension_selection == 3U) \ + original_pt_thread = thread_ptr; \ + if (mutex_priority_change_extension_selection == 4U) \ + { \ + execute_ptr = thread_ptr; \ + _tx_thread_preemption__threshold_scheduled = TX_NULL; \ + } \ + suspend_lowest_priority(); \ + } + +#define TX_THREAD_PRIORITY_CHANGE_EXTENSION if (priority_change_extension_selection != ((TEST_FLAG) 0)) \ + { \ + if (priority_change_extension_selection == 1U) \ + thread_ptr -> tx_thread_smp_core_mapped = TX_THREAD_SMP_MAX_CORES; \ + else if (priority_change_extension_selection == 2U) \ + { \ + original_priority = new_priority; \ + _tx_thread_execute_ptr[0] = TX_NULL; \ + } \ + else if (priority_change_extension_selection == 3U) \ + { \ + original_pt_thread = thread_ptr; \ + } \ + else \ + { \ + _tx_thread_preemption__threshold_scheduled = TX_NULL; \ + } \ + priority_change_extension_selection = 0; \ + } + +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_INITIALIZE_EXTENSION(a) if (threadx_delete_timer_thread == ((TEST_FLAG) 1)) \ + { \ + threadx_delete_timer_thread = ((TEST_FLAG) 0); \ + delete_timer_thread(); \ + (a) = ((UINT) 1); \ + } +#endif + +#define TX_THREAD_STACK_ANALYZE_EXTENSION if (test_stack_analyze_flag == ((TEST_FLAG) 1)) \ + { \ + thread_ptr -> tx_thread_id = ((TEST_FLAG) 0); \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 2)) \ + { \ + stack_ptr = thread_ptr -> tx_thread_stack_start; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 3)) \ + { \ + *stack_ptr = TX_STACK_FILL; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else \ + { \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } + +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION if (test_initialize_flag == ((TEST_FLAG) 1)) \ + { \ + test_initialize_flag = ((TEST_FLAG) 0); \ + return; \ + } + +#endif + + +void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long line); + +#ifndef TX_WIN32_DEBUG_ENABLE +#define _tx_win32_debug_entry_insert(a, b, c) +#endif + + +#ifndef TX_MISRA_ENABLE +#define TX_MEMSET(a,b,c) { \ + UCHAR *ptr; \ + UCHAR value; \ + UINT i, size; \ + ptr = (UCHAR *) ((VOID *) a); \ + value = (UCHAR) b; \ + size = (UINT) c; \ + for (i = 0; i < size; i++) \ + { \ + *ptr++ = value; \ + } \ + } +#endif + + +#include + +#ifndef TX_WIN32_USE_ADDRESS_WAIT +#define TX_WIN32_USE_ADDRESS_WAIT 1 +#endif + +#ifndef TX_WIN32_USE_HIGH_RESOLUTION_TIMER +#define TX_WIN32_USE_HIGH_RESOLUTION_TIMER 1 +#endif + +#ifndef CREATE_WAITABLE_TIMER_HIGH_RESOLUTION +#define CREATE_WAITABLE_TIMER_HIGH_RESOLUTION 0x00000002UL +#endif + + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 +#endif + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 400 +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 +#endif + +#define TX_INT_DISABLE 1 +#define TX_INT_ENABLE 0 + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ((ULONG) (_tx_win32_time_stamp.LowPart)) +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + +#define TX_TRACE_PORT_EXTENSION QueryPerformanceCounter((LARGE_INTEGER *)&_tx_win32_time_stamp); +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + +void _tx_initialize_start_interrupts(void); + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION _tx_initialize_start_interrupts(); \ + { \ + UINT k; \ + for (k = 1U; k < TX_THREAD_SMP_MAX_CORES; k++) \ + { \ + _tx_thread_system_state[k] = 0; \ + } \ + } + +#ifdef TX_WIN32_PROFILE_ENABLE +#define TX_WIN32_PROFILE_THREAD_EXTENSION ULONG64 tx_thread_win32_profile_run_signal_ticks; \ + ULONG64 tx_thread_win32_profile_run_wake_ticks; +#else +#define TX_WIN32_PROFILE_THREAD_EXTENSION +#endif + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +#define TX_THREAD_EXTENSION_0 HANDLE tx_thread_win32_thread_handle; \ + DWORD tx_thread_win32_thread_id; \ + HANDLE tx_thread_win32_thread_run_semaphore; \ + HANDLE tx_thread_win32_thread_start_semaphore; \ + LONG tx_thread_win32_run_sequence; \ + LONG tx_thread_win32_run_sequence_seen; \ + LONG tx_thread_win32_start_sequence; \ + UINT tx_thread_win32_suspension_type; \ + UINT tx_thread_win32_mutex_access; \ + UINT tx_thread_win32_int_disabled_flag; \ + UINT tx_thread_win32_deferred_preempt; \ + UINT tx_thread_win32_virtual_core; \ + TX_WIN32_PROFILE_THREAD_EXTENSION +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr; + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_extension_ptr = (VOID *) (t); + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr; + + +struct TX_THREAD_STRUCT; + +typedef struct TX_WIN32_CRITICAL_SECTION_STRUCT +{ + HANDLE tx_win32_critical_section_mutex_handle; + DWORD tx_win32_critical_section_owner; + ULONG tx_win32_critical_section_nested_count; +} TX_WIN32_CRITICAL_SECTION; + +void _tx_win32_critical_section_obtain(TX_WIN32_CRITICAL_SECTION *critical_section); +void _tx_win32_critical_section_release(TX_WIN32_CRITICAL_SECTION *critical_section); +void _tx_win32_critical_section_release_all(TX_WIN32_CRITICAL_SECTION *critical_section); + +typedef struct TX_THREAD_STRUCT TX_THREAD; + +void _tx_thread_delete_port_completion(TX_THREAD *thread_ptr, UINT tx_interrupt_save); +#define TX_THREAD_DELETE_PORT_COMPLETION(thread_ptr) _tx_thread_delete_port_completion(thread_ptr, tx_interrupt_save); + +void _tx_thread_reset_port_completion(TX_THREAD *thread_ptr, UINT tx_interrupt_save); +#define TX_THREAD_RESET_PORT_COMPLETION(thread_ptr) _tx_thread_reset_port_completion(thread_ptr, tx_interrupt_save); + + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT *tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + DWORD tx_thread_smp_protect_thread_id; +} TX_THREAD_SMP_PROTECT; + +typedef struct TX_THREAD_SMP_CORE_MAPPING_STRUCT +{ + HANDLE tx_thread_smp_core_mapping_thread_handle; + DWORD tx_thread_smp_core_mapping_thread_id; + struct TX_THREAD_STRUCT *tx_thread_smp_core_mapping_thread; +} TX_THREAD_SMP_CORE_MAPPING; + +struct TX_THREAD_STRUCT * _tx_thread_smp_current_thread_get(void); +UINT _tx_thread_smp_core_get(void); +void _tx_thread_smp_core_preempt(UINT core); +UINT _tx_thread_smp_protect(void); +void _tx_thread_smp_unprotect(UINT interrupt_save); +ULONG _tx_thread_smp_current_state_get(void); +ULONG _tx_thread_smp_time_get(void); +void _tx_thread_smp_low_level_initialize(UINT number_of_cores); +void _tx_thread_smp_initialize_wait(void); + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE +void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG suspend, VOID *thread_ptr); +#else +#define _tx_thread_smp_debug_entry_insert(a, b, c) +#endif + +#define TX_SMP_CORE_ID _tx_thread_smp_core_get() + + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +UINT _tx_thread_interrupt_disable(void); +VOID _tx_thread_interrupt_restore(UINT previous_posture); +UINT _tx_thread_interrupt_control(UINT new_posture); + +#define TX_INTERRUPT_SAVE_AREA UINT tx_interrupt_save; +#define TX_DISABLE tx_interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(tx_interrupt_save); + + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "(c) 2026 Eclipse ThreadX contributors. * ThreadX SMP/Win64/MSVC Version 6.5.1.202602 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +extern TX_WIN32_CRITICAL_SECTION _tx_win32_critical_section; +extern HANDLE _tx_win32_scheduler_event; +extern DWORD _tx_win32_scheduler_id; +extern ULONG _tx_win32_global_int_disabled_flag; +extern LARGE_INTEGER _tx_win32_time_stamp; +extern ULONG _tx_win32_system_error; +extern HANDLE _tx_win32_timer_handle; +extern HANDLE _tx_win32_timer_thread_handle; +extern DWORD _tx_win32_timer_thread_id; +extern HANDLE _tx_win32_isr_semaphore; +extern UINT _tx_win32_timer_waiting; +extern TX_THREAD_SMP_CORE_MAPPING _tx_win32_virtual_cores[TX_THREAD_SMP_MAX_CORES]; +extern __declspec(thread) int _tx_win32_threadx_thread; +extern __declspec(thread) UINT _tx_win32_current_virtual_core; + +UINT _tx_win32_smp_current_core_get(void); +void _tx_win32_thread_suspend(HANDLE thread_handle); +void _tx_win32_thread_resume(HANDLE thread_handle); +void _tx_win32_thread_sleep(ULONG milliseconds); +void _tx_win32_thread_yield(void); +void _tx_win32_semaphore_reset(HANDLE semaphore_handle); +LONG _tx_win32_thread_start_sequence_get(TX_THREAD *thread_ptr); +void _tx_win32_thread_run_signal(TX_THREAD *thread_ptr); +DWORD _tx_win32_wait_for_thread_run(TX_THREAD *thread_ptr); +void _tx_win32_thread_start_ack_signal(TX_THREAD *thread_ptr); +DWORD _tx_win32_wait_for_scheduler_event(void); +DWORD _tx_win32_wait_for_thread_run_semaphore(HANDLE semaphore_handle); +DWORD _tx_win32_wait_for_thread_start_semaphore(HANDLE semaphore_handle); +DWORD _tx_win32_wait_for_thread_start_ack(TX_THREAD *thread_ptr, LONG start_sequence); +DWORD _tx_win32_wait_for_isr_semaphore(void); +DWORD _tx_win32_wait_for_isr_rendezvous(void); +DWORD _tx_win32_wait_for_timer_object(void); +#ifdef TX_WIN32_PROFILE_ENABLE +void _tx_win32_profile_reset(void); +void _tx_win32_profile_report(CHAR *label); +void _tx_win32_profile_mark_run_signal(TX_THREAD *thread_ptr); +void _tx_win32_profile_mark_run_wake(TX_THREAD *thread_ptr); +void _tx_win32_profile_mark_start_ack(TX_THREAD *thread_ptr); +#endif + +#ifndef TX_WIN32_MEMORY_SIZE +#define TX_WIN32_MEMORY_SIZE 100000 +#endif + +#ifndef TX_TIMER_TICKS_PER_SECOND +#define TX_TIMER_TICKS_PER_SECOND 100UL +#endif + +#ifndef TX_WIN32_THREAD_STACK_SIZE +#define TX_WIN32_THREAD_STACK_SIZE 65536 +#endif + +#ifndef TX_TIMER_PERIODIC +#ifdef TX_WIN32_SLOW_TIMER +#define TX_TIMER_PERIODIC TX_WIN32_SLOW_TIMER +#else +#define TX_TIMER_PERIODIC 10 +#endif +#endif + +#ifndef TX_WIN32_ISR_PERIODIC +#if defined(CTEST) || defined(BATCH_TEST) +#define TX_WIN32_ISR_PERIODIC 1 +#else +#define TX_WIN32_ISR_PERIODIC TX_TIMER_PERIODIC +#endif +#endif + +#if (TX_WIN32_ISR_PERIODIC > TX_TIMER_PERIODIC) +#error "TX_WIN32_ISR_PERIODIC must not exceed TX_TIMER_PERIODIC" +#endif + +#if ((TX_TIMER_PERIODIC % TX_WIN32_ISR_PERIODIC) != 0) +#error "TX_TIMER_PERIODIC must be an integer multiple of TX_WIN32_ISR_PERIODIC" +#endif + +#define TX_WIN32_TIMER_INTERRUPTS_PER_TICK (TX_TIMER_PERIODIC / TX_WIN32_ISR_PERIODIC) + +#define TX_WIN32_PRIORITY_SCHEDULE THREAD_PRIORITY_NORMAL +#define TX_WIN32_PRIORITY_ISR THREAD_PRIORITY_HIGHEST +#define TX_WIN32_PRIORITY_USER_THREAD THREAD_PRIORITY_LOWEST + +#endif diff --git a/ports_smp/win64/vs_2022/readme_threadx.txt b/ports_smp/win64/vs_2022/readme_threadx.txt new file mode 100644 index 000000000..f37fc0567 --- /dev/null +++ b/ports_smp/win64/vs_2022/readme_threadx.txt @@ -0,0 +1,13 @@ +This port provides a Windows-hosted SMP simulation environment for ThreadX. + +The implementation models virtual ThreadX cores on top of Win64 host threads. +It is intended for validation and regression testing only. It is not a +production runtime port for deploying ThreadX applications on Windows. + +Key characteristics: +- ThreadX cores are virtual scheduler-owned mappings, not Windows CPU numbers. +- One Windows host thread is created for each ThreadX thread. +- A dedicated scheduler thread and a dedicated timer/ISR thread coordinate the + simulation. +- SuspendThread and ResumeThread are used only to emulate asynchronous + preemption in the simulator. diff --git a/ports_smp/win64/vs_2022/src/tx_initialize_low_level.c b/ports_smp/win64/vs_2022/src/tx_initialize_low_level.c new file mode 100644 index 000000000..f517fd6ba --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_initialize_low_level.c @@ -0,0 +1,1150 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.5). +// Some portions generated by GitHub Copilot (claude-sonnet-4.6). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +#include +#include + +#pragma comment (lib, "Winmm.lib") +#if (TX_WIN32_USE_ADDRESS_WAIT != 0) +#pragma comment (lib, "Synchronization.lib") +#endif + +TX_WIN32_CRITICAL_SECTION _tx_win32_critical_section; +HANDLE _tx_win32_scheduler_event; +DWORD _tx_win32_scheduler_id; +ULONG _tx_win32_global_int_disabled_flag; +LARGE_INTEGER _tx_win32_time_stamp; +ULONG _tx_win32_system_error; +HANDLE _tx_win32_timer_handle; +HANDLE _tx_win32_timer_thread_handle; +DWORD _tx_win32_timer_thread_id; +HANDLE _tx_win32_isr_semaphore; +UINT _tx_win32_timer_waiting; +TX_THREAD_SMP_CORE_MAPPING _tx_win32_virtual_cores[TX_THREAD_SMP_MAX_CORES]; +__declspec(thread) int _tx_win32_threadx_thread = 0; +__declspec(thread) UINT _tx_win32_current_virtual_core = 0U; + +static VOID _tx_win32_timer_start(VOID); +static DWORD WINAPI _tx_win32_timer_thread_entry(LPVOID thread_input); +static UINT _tx_win32_smp_current_core_get_internal(DWORD thread_id); +static UINT _tx_win32_smp_thread_core_get(DWORD thread_id); + +#ifndef TX_WIN32_CONTENTION_PAUSE_COUNT +#define TX_WIN32_CONTENTION_PAUSE_COUNT 256U +#endif + +#ifdef TX_WIN32_PROFILE_ENABLE +typedef struct TX_WIN32_PROFILE_STRUCT +{ + ULONG64 tx_win32_profile_start_ticks; + ULONG64 tx_win32_profile_scheduler_wait_ticks; + ULONG64 tx_win32_profile_thread_run_wait_ticks; + ULONG64 tx_win32_profile_thread_start_wait_ticks; + ULONG64 tx_win32_profile_thread_start_ack_wait_ticks; + ULONG64 tx_win32_profile_run_signal_to_wake_ticks; + ULONG64 tx_win32_profile_run_wake_to_ack_ticks; + ULONG64 tx_win32_profile_isr_wait_ticks; + ULONG64 tx_win32_profile_isr_rendezvous_wait_ticks; + ULONG64 tx_win32_profile_timer_wait_ticks; + ULONG64 tx_win32_profile_suspend_ticks; + ULONG64 tx_win32_profile_resume_ticks; + ULONG64 tx_win32_profile_semaphore_reset_ticks; + ULONG64 tx_win32_profile_critical_section_spin_ticks; + ULONG64 tx_win32_profile_yield_ticks; + ULONG tx_win32_profile_scheduler_wait_count; + ULONG tx_win32_profile_thread_run_wait_count; + ULONG tx_win32_profile_thread_start_wait_count; + ULONG tx_win32_profile_thread_start_ack_wait_count; + ULONG tx_win32_profile_run_signal_to_wake_count; + ULONG tx_win32_profile_run_wake_to_ack_count; + ULONG tx_win32_profile_isr_wait_count; + ULONG tx_win32_profile_isr_rendezvous_wait_count; + ULONG tx_win32_profile_timer_wait_count; + ULONG tx_win32_profile_suspend_count; + ULONG tx_win32_profile_resume_count; + ULONG tx_win32_profile_semaphore_reset_count; + ULONG tx_win32_profile_semaphore_reset_loops; + ULONG tx_win32_profile_critical_section_spin_count; + ULONG tx_win32_profile_yield_count; +} TX_WIN32_PROFILE; + +static TX_WIN32_PROFILE _tx_win32_profile; +static LARGE_INTEGER _tx_win32_profile_frequency; + +static ULONG64 _tx_win32_profile_time_get(VOID); +static VOID _tx_win32_profile_accumulate(ULONG64 *ticks_total, ULONG *count_total, ULONG64 start_ticks); +static double _tx_win32_profile_ticks_to_ms(ULONG64 ticks); +#endif + +#ifdef TX_WIN32_DEBUG_ENABLE + +#ifndef TX_WIN32_DEBUG_EVENT_SIZE +#define TX_WIN32_DEBUG_EVENT_SIZE 400 +#endif + +typedef struct TX_WIN32_DEBUG_ENTRY_STRUCT +{ + char *tx_win32_debug_entry_action; + DWORD tx_win32_debug_entry_running_id; + UINT tx_win32_debug_entry_core; + LARGE_INTEGER tx_win32_debug_entry_timestamp; + char *tx_win32_debug_entry_file; + unsigned long tx_win32_debug_entry_line; + TX_WIN32_CRITICAL_SECTION tx_win32_debug_entry_critical_section; + TX_THREAD_SMP_PROTECT tx_win32_debug_protection; + unsigned long tx_win32_debug_entry_int_disabled_flag; + UINT tx_win32_debug_entry_preempt_disable; + ULONG tx_win32_debug_entry_system_state[TX_THREAD_SMP_MAX_CORES]; + TX_THREAD *tx_win32_debug_entry_current_thread[TX_THREAD_SMP_MAX_CORES]; + DWORD tx_win32_debug_entry_current_thread_id[TX_THREAD_SMP_MAX_CORES]; + TX_THREAD *tx_win32_debug_entry_execute_thread[TX_THREAD_SMP_MAX_CORES]; + DWORD tx_win32_debug_entry_execute_thread_id[TX_THREAD_SMP_MAX_CORES]; +} TX_WIN32_DEBUG_ENTRY; + +TX_WIN32_DEBUG_ENTRY _tx_win32_debug_entry_array[TX_WIN32_DEBUG_EVENT_SIZE]; +unsigned long _tx_win32_debug_entry_index = 0; + +void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long line) +{ +UINT i; +DWORD thread_id; + + QueryPerformanceCounter((LARGE_INTEGER *) &_tx_win32_time_stamp); + thread_id = GetCurrentThreadId(); + + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_action = action; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_core = _tx_win32_smp_current_core_get_internal(thread_id); + if (_tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_core == TX_THREAD_SMP_MAX_CORES) + { + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_core = 0U; + } + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_timestamp = _tx_win32_time_stamp; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_file = file; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_line = line; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_protection = _tx_thread_smp_protection; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_preempt_disable = _tx_thread_preempt_disable; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_critical_section = _tx_win32_critical_section; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_int_disabled_flag = _tx_win32_global_int_disabled_flag; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_running_id = thread_id; + + for (i = 0U; i < TX_THREAD_SMP_MAX_CORES; i++) + { + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_system_state[i] = _tx_thread_system_state[i]; + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread[i] = _tx_thread_current_ptr[i]; + if (_tx_thread_current_ptr[i] != TX_NULL) + { + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread_id[i] = + _tx_thread_current_ptr[i] -> tx_thread_win32_thread_id; + } + else + { + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread_id[i] = 0U; + } + + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread[i] = _tx_thread_execute_ptr[i]; + if (_tx_thread_execute_ptr[i] != TX_NULL) + { + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread_id[i] = + _tx_thread_execute_ptr[i] -> tx_thread_win32_thread_id; + } + else + { + _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread_id[i] = 0U; + } + } + + _tx_win32_debug_entry_index++; + if (_tx_win32_debug_entry_index >= TX_WIN32_DEBUG_EVENT_SIZE) + { + _tx_win32_debug_entry_index = 0U; + } +} + +#endif + + +void _tx_timer_interrupt(void); +VOID _tx_thread_context_save(VOID); +VOID _tx_thread_context_restore(VOID); +VOID _tx_win32_timer_interrupt(VOID); +#if defined(CTEST) || defined(BATCH_TEST) +VOID test_interrupt_dispatch(VOID); +extern VOID (*test_isr_dispatch)(void); +#if (TX_WIN32_ISR_PERIODIC < TX_TIMER_PERIODIC) +static VOID _tx_win32_timer_tick_process(VOID); +static UINT _tx_win32_timer_fast_active; +static UINT _tx_win32_timer_fast_count; +#endif +#endif + + +VOID _tx_initialize_low_level(VOID) +{ +UINT i; +TIMECAPS tc; +UINT timer_resolution; + + _tx_initialize_unused_memory = malloc(TX_WIN32_MEMORY_SIZE); + _tx_win32_scheduler_id = GetCurrentThreadId(); + + _tx_win32_critical_section.tx_win32_critical_section_mutex_handle = CreateMutex(NULL, FALSE, NULL); + _tx_win32_critical_section.tx_win32_critical_section_nested_count = 0U; + _tx_win32_critical_section.tx_win32_critical_section_owner = 0U; + if (_tx_win32_critical_section.tx_win32_critical_section_mutex_handle == NULL) + { + printf("ThreadX SMP Win64 error creating critical section mutex!\n"); + while (1) + { + } + } + + _tx_win32_scheduler_event = CreateEvent(NULL, FALSE, FALSE, NULL); + _tx_win32_isr_semaphore = CreateSemaphore(NULL, 0, 0x7FFFFFFF, NULL); + if ((_tx_win32_scheduler_event == NULL) || + (_tx_win32_isr_semaphore == NULL)) + { + printf("ThreadX SMP Win64 error creating semaphores!\n"); + while (1) + { + } + } + + for (i = 0U; i < TX_THREAD_SMP_MAX_CORES; i++) + { + _tx_win32_virtual_cores[i].tx_thread_smp_core_mapping_thread_handle = NULL; + _tx_win32_virtual_cores[i].tx_thread_smp_core_mapping_thread_id = 0U; + _tx_win32_virtual_cores[i].tx_thread_smp_core_mapping_thread = TX_NULL; + } + + _tx_win32_global_int_disabled_flag = TX_FALSE; + _tx_win32_timer_waiting = 0U; +#if (defined(CTEST) || defined(BATCH_TEST)) && (TX_WIN32_ISR_PERIODIC < TX_TIMER_PERIODIC) + _tx_win32_timer_fast_active = TX_FALSE; + _tx_win32_timer_fast_count = 0U; +#endif + +#ifdef TX_WIN32_PROFILE_ENABLE + if (_tx_win32_profile_frequency.QuadPart == 0) + { + QueryPerformanceFrequency(&_tx_win32_profile_frequency); + } + _tx_win32_profile_reset(); +#endif + + if (timeGetDevCaps(&tc, sizeof(TIMECAPS)) != TIMERR_NOERROR) + { + printf("ThreadX SMP Win64 error querying timer resolution!\n"); + while (1) + { + } + } + + timer_resolution = (UINT) min(max(tc.wPeriodMin, TX_WIN32_ISR_PERIODIC), tc.wPeriodMax); + if (timeBeginPeriod(timer_resolution) != TIMERR_NOERROR) + { + printf("ThreadX SMP Win64 error configuring timer resolution!\n"); + while (1) + { + } + } + +#if (TX_WIN32_USE_HIGH_RESOLUTION_TIMER != 0) + _tx_win32_timer_handle = CreateWaitableTimerEx(NULL, NULL, CREATE_WAITABLE_TIMER_HIGH_RESOLUTION, TIMER_ALL_ACCESS); + if (_tx_win32_timer_handle == NULL) +#endif + { + _tx_win32_timer_handle = CreateWaitableTimer(NULL, FALSE, NULL); + } + + if (_tx_win32_timer_handle == NULL) + { + printf("ThreadX SMP Win64 error creating timer handle!\n"); + while (1) + { + } + } + + _tx_win32_timer_thread_handle = CreateThread(NULL, 0, _tx_win32_timer_thread_entry, NULL, 0, &_tx_win32_timer_thread_id); + if (_tx_win32_timer_thread_handle == NULL) + { + printf("ThreadX SMP Win64 error creating timer thread!\n"); + while (1) + { + } + } + + SetThreadPriority(GetCurrentThread(), TX_WIN32_PRIORITY_SCHEDULE); + SetThreadPriority(_tx_win32_timer_thread_handle, TX_WIN32_PRIORITY_ISR); +} + +#ifdef TX_WIN32_PROFILE_ENABLE +static ULONG64 _tx_win32_profile_time_get(VOID) +{ +LARGE_INTEGER current_time; + + QueryPerformanceCounter(¤t_time); + return((ULONG64) current_time.QuadPart); +} + + +static VOID _tx_win32_profile_accumulate(ULONG64 *ticks_total, ULONG *count_total, ULONG64 start_ticks) +{ +ULONG64 end_ticks; + + end_ticks = _tx_win32_profile_time_get(); + *ticks_total = *ticks_total + (end_ticks - start_ticks); + *count_total = *count_total + 1UL; +} + + +static double _tx_win32_profile_ticks_to_ms(ULONG64 ticks) +{ +double frequency; + + frequency = (double) _tx_win32_profile_frequency.QuadPart; + if (frequency == 0.0) + { + return(0.0); + } + + return((((double) ticks) * 1000.0) / frequency); +} + + +void _tx_win32_profile_reset(VOID) +{ + TX_MEMSET(&_tx_win32_profile, 0, sizeof(TX_WIN32_PROFILE)); + _tx_win32_profile.tx_win32_profile_start_ticks = _tx_win32_profile_time_get(); +} + + +void _tx_win32_profile_report(CHAR *label) +{ +ULONG64 elapsed_ticks; + + elapsed_ticks = _tx_win32_profile_time_get() - _tx_win32_profile.tx_win32_profile_start_ticks; + + printf("**** Win64 SMP Profile (%s) elapsed_ms=%.3f\n", + label, + _tx_win32_profile_ticks_to_ms(elapsed_ticks)); + printf("**** waits: scheduler=%lu/%.3fms run=%lu/%.3fms start=%lu/%.3fms start_ack=%lu/%.3fms sig_wake=%lu/%.3fms wake_ack=%lu/%.3fms isr=%lu/%.3fms isr_rdv=%lu/%.3fms timer=%lu/%.3fms\n", + _tx_win32_profile.tx_win32_profile_scheduler_wait_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_scheduler_wait_ticks), + _tx_win32_profile.tx_win32_profile_thread_run_wait_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_thread_run_wait_ticks), + _tx_win32_profile.tx_win32_profile_thread_start_wait_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_thread_start_wait_ticks), + _tx_win32_profile.tx_win32_profile_thread_start_ack_wait_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_thread_start_ack_wait_ticks), + _tx_win32_profile.tx_win32_profile_run_signal_to_wake_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_run_signal_to_wake_ticks), + _tx_win32_profile.tx_win32_profile_run_wake_to_ack_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_run_wake_to_ack_ticks), + _tx_win32_profile.tx_win32_profile_isr_wait_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_isr_wait_ticks), + _tx_win32_profile.tx_win32_profile_isr_rendezvous_wait_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_isr_rendezvous_wait_ticks), + _tx_win32_profile.tx_win32_profile_timer_wait_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_timer_wait_ticks)); + printf("**** host ops: suspend=%lu/%.3fms resume=%lu/%.3fms reset=%lu/%.3fms reset_loops=%lu cs_spin=%lu/%.3fms yield=%lu/%.3fms\n", + _tx_win32_profile.tx_win32_profile_suspend_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_suspend_ticks), + _tx_win32_profile.tx_win32_profile_resume_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_resume_ticks), + _tx_win32_profile.tx_win32_profile_semaphore_reset_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_semaphore_reset_ticks), + _tx_win32_profile.tx_win32_profile_semaphore_reset_loops, + _tx_win32_profile.tx_win32_profile_critical_section_spin_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_critical_section_spin_ticks), + _tx_win32_profile.tx_win32_profile_yield_count, + _tx_win32_profile_ticks_to_ms(_tx_win32_profile.tx_win32_profile_yield_ticks)); +} + + +void _tx_win32_profile_mark_run_signal(TX_THREAD *thread_ptr) +{ + thread_ptr -> tx_thread_win32_profile_run_signal_ticks = _tx_win32_profile_time_get(); + thread_ptr -> tx_thread_win32_profile_run_wake_ticks = 0ULL; +} + + +void _tx_win32_profile_mark_run_wake(TX_THREAD *thread_ptr) +{ +ULONG64 current_ticks; +ULONG64 signal_ticks; + + current_ticks = _tx_win32_profile_time_get(); + signal_ticks = thread_ptr -> tx_thread_win32_profile_run_signal_ticks; + + if (signal_ticks != 0ULL) + { + _tx_win32_profile.tx_win32_profile_run_signal_to_wake_ticks = + _tx_win32_profile.tx_win32_profile_run_signal_to_wake_ticks + (current_ticks - signal_ticks); + _tx_win32_profile.tx_win32_profile_run_signal_to_wake_count++; + } + + thread_ptr -> tx_thread_win32_profile_run_signal_ticks = 0ULL; + thread_ptr -> tx_thread_win32_profile_run_wake_ticks = current_ticks; +} + + +void _tx_win32_profile_mark_start_ack(TX_THREAD *thread_ptr) +{ +ULONG64 current_ticks; +ULONG64 wake_ticks; + + current_ticks = _tx_win32_profile_time_get(); + wake_ticks = thread_ptr -> tx_thread_win32_profile_run_wake_ticks; + + if (wake_ticks != 0ULL) + { + _tx_win32_profile.tx_win32_profile_run_wake_to_ack_ticks = + _tx_win32_profile.tx_win32_profile_run_wake_to_ack_ticks + (current_ticks - wake_ticks); + _tx_win32_profile.tx_win32_profile_run_wake_to_ack_count++; + } + + thread_ptr -> tx_thread_win32_profile_run_wake_ticks = 0ULL; +} +#endif + + +void _tx_initialize_start_interrupts(void) +{ + _tx_win32_timer_start(); +} + + +void _tx_win32_critical_section_obtain(TX_WIN32_CRITICAL_SECTION *critical_section) +{ +DWORD thread_id; +LONG previous_owner; +UINT contention_count; +TX_THREAD *current_thread; +UINT core_scan; +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; +#endif + + thread_id = GetCurrentThreadId(); + + if (critical_section -> tx_win32_critical_section_owner == thread_id) + { + critical_section -> tx_win32_critical_section_nested_count++; + } + else + { + /* If this is a ThreadX application thread, signal that it is about to + * spin waiting for the critical section. context_save checks this flag + * before calling SuspendThread(): a thread that is merely blocked on the + * spinlock does not need to be OS-suspended — it cannot execute protected + * code anyway, and will proceed automatically once the CS is released. + * The flag is cleared below once the CS has been acquired. + * + * Identify the calling thread by scanning _tx_win32_virtual_cores for a + * matching OS thread ID. As a fast path, check the TLS-cached virtual core + * index first; fall back to a full scan only when the TLS value is stale + * (e.g., after a type-1 scheduler hand-off moves the thread to a new core). + * Worst case: the entry is momentarily absent and current_thread stays + * TX_NULL, which simply skips the mutex_access optimisation this cycle. */ + current_thread = TX_NULL; + if (_tx_win32_threadx_thread != 0) + { + core_scan = _tx_win32_current_virtual_core; + if ((core_scan < TX_THREAD_SMP_MAX_CORES) && + (_tx_win32_virtual_cores[core_scan].tx_thread_smp_core_mapping_thread_id == thread_id)) + { + current_thread = _tx_win32_virtual_cores[core_scan].tx_thread_smp_core_mapping_thread; + } + else + { + for (core_scan = 0U; core_scan < TX_THREAD_SMP_MAX_CORES; core_scan++) + { + if (_tx_win32_virtual_cores[core_scan].tx_thread_smp_core_mapping_thread_id == thread_id) + { + current_thread = _tx_win32_virtual_cores[core_scan].tx_thread_smp_core_mapping_thread; + break; + } + } + } + if (current_thread != TX_NULL) + { + current_thread -> tx_thread_win32_mutex_access = TX_TRUE; + } + } + + contention_count = 0U; +#ifdef TX_WIN32_PROFILE_ENABLE + start_ticks = _tx_win32_profile_time_get(); +#endif + do + { + previous_owner = InterlockedCompareExchange((LONG *) &(critical_section -> tx_win32_critical_section_owner), (LONG) thread_id, 0L); + + if (previous_owner != 0L) + { +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile.tx_win32_profile_critical_section_spin_count++; +#endif + contention_count++; + if (contention_count < TX_WIN32_CONTENTION_PAUSE_COUNT) + { + YieldProcessor(); + } + else + { + contention_count = 0U; + _tx_win32_thread_yield(); + } + } + } while (previous_owner != 0L); + +#ifdef TX_WIN32_PROFILE_ENABLE + if (critical_section -> tx_win32_critical_section_owner == thread_id) + { + _tx_win32_profile.tx_win32_profile_critical_section_spin_ticks = + _tx_win32_profile.tx_win32_profile_critical_section_spin_ticks + + (_tx_win32_profile_time_get() - start_ticks); + } +#endif + /* CS acquired; clear the spinning flag so the next timer ISR will see + * the thread as normally running. The thread is now inside the CS body + * and the ISR cannot reach context_save until we release the CS. */ + if (current_thread != TX_NULL) + { + current_thread -> tx_thread_win32_mutex_access = TX_FALSE; + } + + critical_section -> tx_win32_critical_section_nested_count = 1U; + } +} + + +void _tx_win32_critical_section_release(TX_WIN32_CRITICAL_SECTION *critical_section) +{ +DWORD thread_id; + + thread_id = GetCurrentThreadId(); + + if (critical_section -> tx_win32_critical_section_owner == thread_id) + { + if (critical_section -> tx_win32_critical_section_nested_count != 0U) + { + critical_section -> tx_win32_critical_section_nested_count--; + + if (critical_section -> tx_win32_critical_section_nested_count == 0U) + { + InterlockedExchange((LONG *) &(critical_section -> tx_win32_critical_section_owner), 0L); + } + } + } + else + { + _tx_win32_system_error++; + } +} + + +void _tx_win32_critical_section_release_all(TX_WIN32_CRITICAL_SECTION *critical_section) +{ +DWORD thread_id; + + thread_id = GetCurrentThreadId(); + + if (critical_section -> tx_win32_critical_section_owner == thread_id) + { + if (critical_section -> tx_win32_critical_section_nested_count != 0U) + { + critical_section -> tx_win32_critical_section_nested_count = 0U; + InterlockedExchange((LONG *) &(critical_section -> tx_win32_critical_section_owner), 0L); + } + } + else + { + _tx_win32_system_error++; + } +} + + +UINT _tx_win32_smp_current_core_get(void) +{ +UINT core; +DWORD thread_id; +UINT critical_section_owned; + + thread_id = GetCurrentThreadId(); + critical_section_owned = (UINT) (_tx_win32_critical_section.tx_win32_critical_section_owner == thread_id); + + if (critical_section_owned == TX_FALSE) + { + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + } + + if (_tx_win32_threadx_thread != 0) + { + core = _tx_win32_smp_thread_core_get(thread_id); + + if (core == TX_THREAD_SMP_MAX_CORES) + { + core = _tx_win32_current_virtual_core; + } + else + { + _tx_win32_current_virtual_core = core; + } + } + else + { + core = _tx_win32_smp_current_core_get_internal(thread_id); + if (core == TX_THREAD_SMP_MAX_CORES) + { + core = 0U; + } + } + + if (critical_section_owned == TX_FALSE) + { + _tx_win32_critical_section_release(&_tx_win32_critical_section); + } + + return(core); +} + + +static UINT _tx_win32_smp_thread_core_get(DWORD thread_id) +{ +UINT core; +UINT i; +TX_THREAD *thread_ptr; + + core = TX_THREAD_SMP_MAX_CORES; + + for (i = 0U; i < TX_THREAD_SMP_MAX_CORES; i++) + { + if (_tx_win32_virtual_cores[i].tx_thread_smp_core_mapping_thread_id == thread_id) + { + core = i; + break; + } + } + + if (core == TX_THREAD_SMP_MAX_CORES) + { + for (i = 0U; i < TX_THREAD_SMP_MAX_CORES; i++) + { + thread_ptr = _tx_thread_current_ptr[i]; + if ((thread_ptr != TX_NULL) && (thread_ptr -> tx_thread_win32_thread_id == thread_id)) + { + core = i; + break; + } + } + } + + return(core); +} + + +static UINT _tx_win32_smp_current_core_get_internal(DWORD thread_id) +{ +UINT core; +UINT i; +TX_THREAD *thread_ptr; + + core = _tx_win32_smp_thread_core_get(thread_id); + + if (core == TX_THREAD_SMP_MAX_CORES) + { + for (i = 0U; i < TX_THREAD_SMP_MAX_CORES; i++) + { + thread_ptr = _tx_thread_execute_ptr[i]; + if ((thread_ptr != TX_NULL) && (thread_ptr -> tx_thread_win32_thread_id == thread_id)) + { + core = i; + break; + } + } + } + + return(core); +} + + +void _tx_win32_thread_suspend(HANDLE thread_handle) +{ +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + if (SuspendThread(thread_handle) == (DWORD) -1) + { + _tx_win32_system_error++; + while (1) + { + } + } +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_suspend_ticks, + &_tx_win32_profile.tx_win32_profile_suspend_count, + start_ticks); +#endif +} + + +void _tx_win32_thread_resume(HANDLE thread_handle) +{ + DWORD suspend_count; +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + + do + { + suspend_count = ResumeThread(thread_handle); + if (suspend_count == (DWORD) -1) + { + _tx_win32_system_error++; + while (1) + { + } + } + } while (suspend_count > 1U); +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_resume_ticks, + &_tx_win32_profile.tx_win32_profile_resume_count, + start_ticks); +#endif +} + + +void _tx_win32_thread_sleep(ULONG milliseconds) +{ + if (milliseconds == 0U) + { + milliseconds = 1U; + } + + Sleep((DWORD) milliseconds); +} + + +void _tx_win32_thread_yield(VOID) +{ +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + + if (SwitchToThread() == 0) + { + Sleep(0); + } + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_yield_ticks, + &_tx_win32_profile.tx_win32_profile_yield_count, + start_ticks); +#endif +} + + +void _tx_win32_semaphore_reset(HANDLE semaphore_handle) +{ +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + + while (WaitForSingleObject(semaphore_handle, 0) == WAIT_OBJECT_0) + { +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile.tx_win32_profile_semaphore_reset_loops++; +#endif + } + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_semaphore_reset_ticks, + &_tx_win32_profile.tx_win32_profile_semaphore_reset_count, + start_ticks); +#endif +} + + +LONG _tx_win32_thread_start_sequence_get(TX_THREAD *thread_ptr) +{ +#if (TX_WIN32_USE_ADDRESS_WAIT != 0) + return(thread_ptr -> tx_thread_win32_start_sequence); +#else + TX_PARAMETER_NOT_USED(thread_ptr); + return(0L); +#endif +} + + +void _tx_win32_thread_run_signal(TX_THREAD *thread_ptr) +{ +#if (TX_WIN32_USE_ADDRESS_WAIT != 0) + (void) InterlockedIncrement(&(thread_ptr -> tx_thread_win32_run_sequence)); + WakeByAddressSingle(&(thread_ptr -> tx_thread_win32_run_sequence)); +#else + ReleaseSemaphore(thread_ptr -> tx_thread_win32_thread_run_semaphore, 1, NULL); +#endif +} + + +DWORD _tx_win32_wait_for_thread_run(TX_THREAD *thread_ptr) +{ +DWORD wait_status; +#if (TX_WIN32_USE_ADDRESS_WAIT != 0) +LONG observed_sequence; +LONG current_sequence; +#endif +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + +#if (TX_WIN32_USE_ADDRESS_WAIT != 0) + wait_status = WAIT_OBJECT_0; + observed_sequence = thread_ptr -> tx_thread_win32_run_sequence_seen; + current_sequence = thread_ptr -> tx_thread_win32_run_sequence; + + while (current_sequence == observed_sequence) + { + if (WaitOnAddress(&(thread_ptr -> tx_thread_win32_run_sequence), + &observed_sequence, + sizeof(thread_ptr -> tx_thread_win32_run_sequence), + INFINITE) == 0) + { + _tx_win32_system_error++; + wait_status = WAIT_FAILED; + break; + } + + current_sequence = thread_ptr -> tx_thread_win32_run_sequence; + } + + if (wait_status == WAIT_OBJECT_0) + { + thread_ptr -> tx_thread_win32_run_sequence_seen = current_sequence; + } +#else + wait_status = WaitForSingleObject(thread_ptr -> tx_thread_win32_thread_run_semaphore, INFINITE); +#endif + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_thread_run_wait_ticks, + &_tx_win32_profile.tx_win32_profile_thread_run_wait_count, + start_ticks); +#endif + + return(wait_status); +} + + +void _tx_win32_thread_start_ack_signal(TX_THREAD *thread_ptr) +{ +#if (TX_WIN32_USE_ADDRESS_WAIT != 0) + (void) InterlockedIncrement(&(thread_ptr -> tx_thread_win32_start_sequence)); + WakeByAddressSingle(&(thread_ptr -> tx_thread_win32_start_sequence)); +#else + ReleaseSemaphore(thread_ptr -> tx_thread_win32_thread_start_semaphore, 1, NULL); +#endif +} + + +DWORD _tx_win32_wait_for_scheduler_event(VOID) +{ +DWORD wait_status; +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + + /* Use a 2 ms timeout (matching the Linux SMP port's sem_timedwait interval) so that + * a missed SetEvent() does not stall the scheduler indefinitely and so that the + * timer-tick phase varies slightly between iterations, preventing a systematic + * resonance where the ISR always fires outside the _tx_thread_preempt_disable + * window (which would make tests like threadx_thread_wait_abort_and_isr_test + * take an unreasonably long time to complete). */ + wait_status = WaitForSingleObject(_tx_win32_scheduler_event, 2U); + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_scheduler_wait_ticks, + &_tx_win32_profile.tx_win32_profile_scheduler_wait_count, + start_ticks); +#endif + + return(wait_status); +} + + +DWORD _tx_win32_wait_for_thread_run_semaphore(HANDLE semaphore_handle) +{ +DWORD wait_status; +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + + wait_status = WaitForSingleObject(semaphore_handle, INFINITE); + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_thread_run_wait_ticks, + &_tx_win32_profile.tx_win32_profile_thread_run_wait_count, + start_ticks); +#endif + + return(wait_status); +} + + +DWORD _tx_win32_wait_for_thread_start_semaphore(HANDLE semaphore_handle) +{ +DWORD wait_status; +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + + wait_status = WaitForSingleObject(semaphore_handle, INFINITE); + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_thread_start_wait_ticks, + &_tx_win32_profile.tx_win32_profile_thread_start_wait_count, + start_ticks); +#endif + + return(wait_status); +} + + +DWORD _tx_win32_wait_for_thread_start_ack(TX_THREAD *thread_ptr, LONG start_sequence) +{ +DWORD wait_status; +#if (TX_WIN32_USE_ADDRESS_WAIT != 0) +LONG current_sequence; +#endif +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + +#if (TX_WIN32_USE_ADDRESS_WAIT != 0) + wait_status = WAIT_OBJECT_0; + current_sequence = thread_ptr -> tx_thread_win32_start_sequence; + + while (current_sequence == start_sequence) + { + if (WaitOnAddress(&(thread_ptr -> tx_thread_win32_start_sequence), + &start_sequence, + sizeof(thread_ptr -> tx_thread_win32_start_sequence), + INFINITE) == 0) + { + _tx_win32_system_error++; + wait_status = WAIT_FAILED; + break; + } + + current_sequence = thread_ptr -> tx_thread_win32_start_sequence; + } +#else + TX_PARAMETER_NOT_USED(start_sequence); + wait_status = WaitForSingleObject(thread_ptr -> tx_thread_win32_thread_start_semaphore, INFINITE); +#endif + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_thread_start_ack_wait_ticks, + &_tx_win32_profile.tx_win32_profile_thread_start_ack_wait_count, + start_ticks); +#endif + + return(wait_status); +} + + +DWORD _tx_win32_wait_for_isr_semaphore(VOID) +{ +DWORD wait_status; +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + + wait_status = WaitForSingleObject(_tx_win32_isr_semaphore, INFINITE); + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_isr_wait_ticks, + &_tx_win32_profile.tx_win32_profile_isr_wait_count, + start_ticks); +#endif + + return(wait_status); +} + + +DWORD _tx_win32_wait_for_isr_rendezvous(VOID) +{ +DWORD wait_status; +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + + wait_status = WaitForSingleObject(_tx_win32_isr_semaphore, INFINITE); + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_isr_rendezvous_wait_ticks, + &_tx_win32_profile.tx_win32_profile_isr_rendezvous_wait_count, + start_ticks); +#endif + + return(wait_status); +} + + +DWORD _tx_win32_wait_for_timer_object(VOID) +{ +DWORD wait_status; +#ifdef TX_WIN32_PROFILE_ENABLE +ULONG64 start_ticks; + + start_ticks = _tx_win32_profile_time_get(); +#endif + + wait_status = WaitForSingleObject(_tx_win32_timer_handle, INFINITE); + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_accumulate(&_tx_win32_profile.tx_win32_profile_timer_wait_ticks, + &_tx_win32_profile.tx_win32_profile_timer_wait_count, + start_ticks); +#endif + + return(wait_status); +} + + +static DWORD WINAPI _tx_win32_timer_thread_entry(LPVOID thread_input) +{ + TX_PARAMETER_NOT_USED(thread_input); + + while (1) + { + _tx_win32_wait_for_timer_object(); + _tx_win32_timer_interrupt(); + _tx_win32_timer_start(); + } +} + + +VOID _tx_win32_timer_interrupt(VOID) +{ + _tx_thread_context_save(); +#if defined(CTEST) || defined(BATCH_TEST) + test_interrupt_dispatch(); +#if (TX_WIN32_ISR_PERIODIC < TX_TIMER_PERIODIC) + _tx_win32_timer_tick_process(); +#else + _tx_timer_interrupt(); +#endif +#else + _tx_timer_interrupt(); +#endif + _tx_thread_context_restore(); +} + + +#if (defined(CTEST) || defined(BATCH_TEST)) && (TX_WIN32_ISR_PERIODIC < TX_TIMER_PERIODIC) +static VOID _tx_win32_timer_tick_process(VOID) +{ + if (test_isr_dispatch != TX_NULL) + { + if (_tx_win32_timer_fast_active == TX_FALSE) + { + _tx_win32_timer_fast_active = TX_TRUE; + _tx_win32_timer_fast_count = 0U; + } + else + { + _tx_win32_timer_fast_count++; + if (_tx_win32_timer_fast_count < TX_WIN32_TIMER_INTERRUPTS_PER_TICK) + { + return; + } + + _tx_win32_timer_fast_count = 0U; + } + } + else + { + _tx_win32_timer_fast_active = TX_FALSE; + _tx_win32_timer_fast_count = 0U; + } + + _tx_timer_interrupt(); +} +#endif + + +static VOID _tx_win32_timer_start(VOID) +{ +LARGE_INTEGER due_time; +LONGLONG timer_period; + +#if (defined(CTEST) || defined(BATCH_TEST)) && (TX_WIN32_ISR_PERIODIC < TX_TIMER_PERIODIC) + if (test_isr_dispatch != TX_NULL) + { + timer_period = (LONGLONG) TX_WIN32_ISR_PERIODIC; + } + else +#endif + { + timer_period = (LONGLONG) TX_TIMER_PERIODIC; + } + + due_time.QuadPart = -(timer_period * 10000LL); +#if (TX_WIN32_USE_HIGH_RESOLUTION_TIMER != 0) + if (SetWaitableTimerEx(_tx_win32_timer_handle, &due_time, 0, NULL, NULL, NULL, 0) == 0) +#else + if (SetWaitableTimer(_tx_win32_timer_handle, &due_time, 0, NULL, NULL, FALSE) == 0) +#endif + { + printf("ThreadX SMP Win64 error starting timer!\n"); + while (1) + { + } + } +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_context_restore.c b/ports_smp/win64/vs_2022/src/tx_thread_context_restore.c new file mode 100644 index 000000000..d1b74c383 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_context_restore.c @@ -0,0 +1,139 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.5). +// Some portions generated by GitHub Copilot (claude-sonnet-4.6). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +VOID _tx_thread_context_restore(VOID) +{ +TX_THREAD *current_thread; +TX_THREAD *execute_thread; + + _tx_win32_debug_entry_insert("CONTEXT_RESTORE", __FILE__, __LINE__); + + _tx_thread_system_state[0]--; + current_thread = _tx_thread_current_ptr[0]; + execute_thread = _tx_thread_execute_ptr[0]; + + if (_tx_thread_system_state[0] == 0UL) + { + if (current_thread != TX_NULL) + { + if ((_tx_thread_preempt_disable == 0U) && (current_thread != execute_thread)) + { + /* If context_save skipped SuspendThread because the thread was spinning + * on the Win32 CS (suspension_type == 4), suspend it now. The ISR still + * holds the CS so the spinning thread cannot make forward progress, making + * SuspendThread safe to call here. mutex_access remains TRUE; the thread + * will clear it naturally when it acquires the CS after being resumed. */ + if (current_thread -> tx_thread_win32_suspension_type == 4U) + { + _tx_win32_thread_suspend(current_thread -> tx_thread_win32_thread_handle); + } + + current_thread -> tx_thread_win32_suspension_type = 1U; + + if (_tx_timer_time_slice[0] != 0U) + { + current_thread -> tx_thread_time_slice = _tx_timer_time_slice[0]; + _tx_timer_time_slice[0] = 0U; + } + + _tx_thread_current_ptr[0] = TX_NULL; + _tx_win32_virtual_cores[0].tx_thread_smp_core_mapping_thread_handle = NULL; + _tx_win32_virtual_cores[0].tx_thread_smp_core_mapping_thread_id = 0U; + _tx_win32_virtual_cores[0].tx_thread_smp_core_mapping_thread = TX_NULL; + current_thread -> tx_thread_smp_core_control = 1U; + + /* Signal the scheduler to assign the next execute_thread. Wait for the + * scheduler to signal isr_semaphore before returning: the scheduler holds + * the CS while waiting for start_ack from the execute_thread, which forces + * any thread calling TX_DISABLE to spin with mutex_access=TRUE while + * preempt_disable may be non-zero — exactly the window needed to satisfy + * the condition in tests such as wait_abort_and_isr. */ + _tx_win32_timer_waiting = 1U; + MemoryBarrier(); + if (SetEvent(_tx_win32_scheduler_event) == 0) + { + _tx_win32_system_error++; + } + + if ((execute_thread != TX_NULL) && + (execute_thread -> tx_thread_win32_suspension_type == 2U)) + { + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + _tx_win32_wait_for_isr_rendezvous(); + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + _tx_win32_semaphore_reset(_tx_win32_isr_semaphore); + } + + _tx_win32_timer_waiting = 0U; + } + else + { + if ((current_thread -> tx_thread_win32_suspension_type == 3U) || + (current_thread -> tx_thread_win32_suspension_type == 4U)) + { + /* context_save did not call SuspendThread (type 3: preempt_disable≠0; + * type 4: thread was spinning on Win32 CS). Clear the flag; do not + * issue a matching ResumeThread. The thread will continue + * automatically once the ISR releases the Win32 critical section. */ + current_thread -> tx_thread_win32_suspension_type = 0U; + } + else + { + /* suspension_type 0: context_save called SuspendThread. Always issue + * the matching ResumeThread here, regardless of mutex_access. + * + * Do NOT gate this on mutex_access: a thread on a different virtual core + * that happens to share the same stale TLS slot can momentarily stamp + * mutex_access = TRUE on this thread's struct while it is OS-suspended, + * which would otherwise cause context_restore to skip ResumeThread and + * leave the thread permanently suspended (deadlock). */ + _tx_win32_thread_resume(current_thread -> tx_thread_win32_thread_handle); + } + } + } + else if (execute_thread != TX_NULL) + { + _tx_win32_timer_waiting = 1U; + MemoryBarrier(); + if (SetEvent(_tx_win32_scheduler_event) == 0) + { + _tx_win32_system_error++; + } + + if (execute_thread -> tx_thread_win32_suspension_type == 2U) + { + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + _tx_win32_wait_for_isr_rendezvous(); + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + _tx_win32_semaphore_reset(_tx_win32_isr_semaphore); + } + + _tx_win32_timer_waiting = 0U; + } + } + + _tx_thread_smp_unprotect(TX_INT_ENABLE); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_context_save.c b/ports_smp/win64/vs_2022/src/tx_thread_context_save.c new file mode 100644 index 000000000..89d6cd75c --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_context_save.c @@ -0,0 +1,83 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). +// Some portions generated by GitHub Copilot (claude-sonnet-4.6). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +VOID _tx_thread_context_save(VOID) +{ +TX_THREAD *thread_ptr; +UINT interrupt_posture; + + interrupt_posture = _tx_thread_smp_protect(); + if (interrupt_posture != TX_FALSE) + { + _tx_win32_system_error++; + } + + _tx_win32_debug_entry_insert("CONTEXT_SAVE", __FILE__, __LINE__); + + thread_ptr = _tx_thread_current_ptr[0]; + + if ((thread_ptr != TX_NULL) && (_tx_thread_system_state[0] == 0UL)) + { + if (thread_ptr -> tx_thread_win32_mutex_access == TX_FALSE) + { + if (_tx_thread_preempt_disable == 0U) + { + /* Thread is not in a preempt-disabled section; suspend it normally so + * context_restore can preempt it if a higher-priority thread is ready. */ + _tx_win32_thread_suspend(thread_ptr -> tx_thread_win32_thread_handle); + _tx_win32_debug_entry_insert("CONTEXT_SAVE-suspend_thread", __FILE__, __LINE__); + } + else + { + /* Thread holds the SMP preemption lock (_tx_thread_preempt_disable != 0). + * Issuing SuspendThread/ResumeThread here would cost ~100 µs for zero + * benefit: context_restore will skip preemption anyway because + * _tx_thread_preempt_disable is still non-zero when it runs (the ISR + * cannot lower the count below its value at ISR entry while it holds the + * Win32 critical section). Flag the thread so context_restore knows not + * to issue a matching ResumeThread. + * + * MISRA C 2012 Rule 10.3 deviation: suspension_type is a UINT field used + * as a small state tag; value 3 is a port-local extension of the existing + * 0/1/2 enumeration. */ + thread_ptr -> tx_thread_win32_suspension_type = 3U; + } + } + else + { + /* Thread is spinning on the Win32 critical section (mutex_access TRUE). + * It is blocked waiting to acquire the CS and cannot execute any protected + * ThreadX code, so SuspendThread is unnecessary. Tag the thread with + * suspension_type 4 so context_restore handles it correctly: + * - no-preemption path: just clear the flag (no ResumeThread). + * - preemption path: call SuspendThread retrospectively and proceed. + * + * MISRA C 2012 Rule 10.3 deviation: value 4 is a port-local extension. */ + thread_ptr -> tx_thread_win32_suspension_type = 4U; + } + } + + _tx_thread_system_state[0]++; +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_interrupt_control.c b/ports_smp/win64/vs_2022/src/tx_thread_interrupt_control.c new file mode 100644 index 000000000..b596baeb4 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_interrupt_control.c @@ -0,0 +1,104 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" + +UINT _tx_thread_interrupt_disable(void) +{ +UINT previous_value; + + previous_value = _tx_thread_interrupt_control(TX_INT_DISABLE); + return(previous_value); +} + + +VOID _tx_thread_interrupt_restore(UINT previous_posture) +{ + previous_posture = _tx_thread_interrupt_control(previous_posture); + TX_PARAMETER_NOT_USED(previous_posture); +} + + +UINT _tx_thread_interrupt_control(UINT new_posture) +{ +UINT old_posture; +TX_THREAD *thread_ptr; +DWORD thread_id; +UINT core; + + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + +#ifdef TX_WIN32_DEBUG_ENABLE + if (new_posture == TX_INT_ENABLE) + { + _tx_win32_debug_entry_insert("RESTORE", __FILE__, __LINE__); + } + else + { + _tx_win32_debug_entry_insert("DISABLE", __FILE__, __LINE__); + } +#endif + + thread_id = GetCurrentThreadId(); + core = _tx_thread_smp_core_get(); + thread_ptr = _tx_thread_current_ptr[core]; + + if ((_tx_win32_threadx_thread != 0) && + ((thread_ptr == TX_NULL) || (thread_ptr -> tx_thread_win32_thread_id != thread_id))) + { + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + ExitThread(0); + } + + if (_tx_win32_critical_section.tx_win32_critical_section_nested_count == 1U) + { + old_posture = TX_INT_ENABLE; + } + else + { + old_posture = TX_INT_DISABLE; + } + + if (_tx_thread_system_state[core] != 0UL) + { + if (new_posture == TX_INT_ENABLE) + { + _tx_win32_global_int_disabled_flag = TX_FALSE; + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + } + else if (new_posture == TX_INT_DISABLE) + { + _tx_win32_global_int_disabled_flag = TX_TRUE; + } + } + else if (thread_ptr != TX_NULL) + { + if (new_posture == TX_INT_ENABLE) + { + thread_ptr -> tx_thread_win32_int_disabled_flag = TX_FALSE; + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + } + else if (new_posture == TX_INT_DISABLE) + { + thread_ptr -> tx_thread_win32_int_disabled_flag = TX_TRUE; + } + } + + return(old_posture); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_schedule.c b/ports_smp/win64/vs_2022/src/tx_thread_schedule.c new file mode 100644 index 000000000..f33eb7b07 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_schedule.c @@ -0,0 +1,261 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.5). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +static VOID _tx_win32_thread_cleanup(TX_THREAD *thread_ptr); + +VOID _tx_thread_schedule(VOID) +{ +UINT core; +UINT pending_work; +TX_THREAD *current_thread; +TX_THREAD *execute_thread; +UCHAR preempt_retry; +DWORD wait_status; +LONG start_sequence; + + preempt_retry = TX_FALSE; + + while (1) + { + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + if (_tx_win32_global_int_disabled_flag != TX_FALSE) + { + _tx_win32_system_error++; + } + + _tx_win32_debug_entry_insert("SCHEDULE-wake_up", __FILE__, __LINE__); + + for (core = 0U; core < TX_THREAD_SMP_MAX_CORES; core++) + { + current_thread = _tx_thread_current_ptr[core]; + + if ((current_thread != TX_NULL) && (current_thread -> tx_thread_win32_deferred_preempt != TX_FALSE)) + { + if (_tx_thread_preempt_disable != 0U) + { + preempt_retry = TX_TRUE; + continue; + } + + if (current_thread -> tx_thread_win32_mutex_access != TX_FALSE) + { + preempt_retry = TX_TRUE; + continue; + } + + if (current_thread -> tx_thread_state != TX_TERMINATED) + { + _tx_win32_thread_suspend(current_thread -> tx_thread_win32_thread_handle); + current_thread -> tx_thread_win32_deferred_preempt = TX_FALSE; + current_thread -> tx_thread_win32_suspension_type = 1U; + + if (_tx_timer_time_slice[core] != 0U) + { + current_thread -> tx_thread_time_slice = _tx_timer_time_slice[core]; + _tx_timer_time_slice[core] = 0U; + } + } + + _tx_thread_current_ptr[core] = TX_NULL; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread = TX_NULL; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread_handle = NULL; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread_id = 0U; + current_thread -> tx_thread_smp_core_control = 1U; + + _tx_win32_debug_entry_insert("SCHEDULE-core_preempt_complete", __FILE__, __LINE__); + } + + if (_tx_thread_current_ptr[core] == TX_NULL) + { + execute_thread = _tx_thread_execute_ptr[core]; + + if ((execute_thread != TX_NULL) && (execute_thread -> tx_thread_smp_core_control != 0U)) + { + _tx_thread_current_ptr[core] = execute_thread; + execute_thread -> tx_thread_win32_virtual_core = core; + execute_thread -> tx_thread_smp_core_mapped = core; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread = execute_thread; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread_handle = execute_thread -> tx_thread_win32_thread_handle; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread_id = execute_thread -> tx_thread_win32_thread_id; + execute_thread -> tx_thread_smp_core_control = 0U; + execute_thread -> tx_thread_run_count++; + _tx_timer_time_slice[core] = execute_thread -> tx_thread_time_slice; + MemoryBarrier(); + if (execute_thread -> tx_thread_win32_suspension_type == 1U) + { + execute_thread -> tx_thread_win32_suspension_type = 0U; + _tx_win32_debug_entry_insert("SCHEDULE-resume_thread", __FILE__, __LINE__); + _tx_win32_thread_resume(execute_thread -> tx_thread_win32_thread_handle); + } + else if (execute_thread -> tx_thread_win32_suspension_type == 2U) + { + execute_thread -> tx_thread_win32_suspension_type = 0U; + _tx_win32_debug_entry_insert("SCHEDULE-release_sem", __FILE__, __LINE__); + +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_mark_run_signal(execute_thread); +#endif +#if (TX_WIN32_USE_ADDRESS_WAIT == 0) + _tx_win32_semaphore_reset(execute_thread -> tx_thread_win32_thread_start_semaphore); + _tx_win32_semaphore_reset(execute_thread -> tx_thread_win32_thread_run_semaphore); +#endif + start_sequence = _tx_win32_thread_start_sequence_get(execute_thread); + _tx_win32_thread_run_signal(execute_thread); + /* Wait for the execute_thread to signal start_ack before proceeding. + * Holding the CS here means any thread that calls TX_DISABLE will + * spin with mutex_access=TRUE and preempt_disable≠0, creating the + * window the ISR needs to observe preempt_disable!=0 for resonance + * tests such as wait_abort_and_isr. */ + wait_status = _tx_win32_wait_for_thread_start_ack(execute_thread, start_sequence); + if (wait_status != WAIT_OBJECT_0) + { + _tx_win32_system_error++; + } + } + else + { + _tx_win32_system_error++; + } + } + } + } + + /* Signal context_restore's rendezvous wait now that all execute_threads have + * been resumed and their start_ack received. */ + if (_tx_win32_timer_waiting != 0U) + { + ReleaseSemaphore(_tx_win32_isr_semaphore, 1, NULL); + } + + if (preempt_retry != TX_FALSE) + { + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + _tx_win32_thread_yield(); + preempt_retry = TX_FALSE; + continue; + } + + _tx_win32_debug_entry_insert("SCHEDULE-self_suspend_sem", __FILE__, __LINE__); + + pending_work = TX_FALSE; + for (core = 0U; core < TX_THREAD_SMP_MAX_CORES; core++) + { + current_thread = _tx_thread_current_ptr[core]; + execute_thread = _tx_thread_execute_ptr[core]; + + if ((current_thread != TX_NULL) && (current_thread -> tx_thread_win32_deferred_preempt != TX_FALSE)) + { + pending_work = TX_TRUE; + break; + } + + if ((_tx_thread_current_ptr[core] == TX_NULL) && + (execute_thread != TX_NULL) && + (execute_thread -> tx_thread_smp_core_control != 0U)) + { + pending_work = TX_TRUE; + break; + } + } + + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + + if (pending_work != TX_FALSE) + { + continue; + } + + /* Coalesce stale wakeups so the scheduler yields to worker threads + until there is a new ready-state transition to process. */ + (void) _tx_win32_wait_for_scheduler_event(); + } +} + + +static VOID _tx_win32_thread_cleanup(TX_THREAD *thread_ptr) +{ +DWORD exit_code; +ULONG wait_count; + + if (thread_ptr -> tx_thread_win32_thread_handle != NULL) + { + wait_count = 0U; + + do + { + if ((GetExitCodeThread(thread_ptr -> tx_thread_win32_thread_handle, &exit_code) != 0) && + (exit_code != STILL_ACTIVE)) + { + break; + } + + _tx_win32_thread_resume(thread_ptr -> tx_thread_win32_thread_handle); + + _tx_win32_thread_run_signal(thread_ptr); + + _tx_win32_thread_sleep(1U); + wait_count++; + } while (wait_count < 100U); + + if ((GetExitCodeThread(thread_ptr -> tx_thread_win32_thread_handle, &exit_code) != 0) && + (exit_code == STILL_ACTIVE)) + { + (void) TerminateThread(thread_ptr -> tx_thread_win32_thread_handle, 0U); + (void) WaitForSingleObject(thread_ptr -> tx_thread_win32_thread_handle, INFINITE); + } + + CloseHandle(thread_ptr -> tx_thread_win32_thread_handle); + thread_ptr -> tx_thread_win32_thread_handle = NULL; + } + + if (thread_ptr -> tx_thread_win32_thread_run_semaphore != NULL) + { + CloseHandle(thread_ptr -> tx_thread_win32_thread_run_semaphore); + thread_ptr -> tx_thread_win32_thread_run_semaphore = NULL; + } + + if (thread_ptr -> tx_thread_win32_thread_start_semaphore != NULL) + { + CloseHandle(thread_ptr -> tx_thread_win32_thread_start_semaphore); + thread_ptr -> tx_thread_win32_thread_start_semaphore = NULL; + } +} + + +void _tx_thread_delete_port_completion(TX_THREAD *thread_ptr, UINT tx_interrupt_save) +{ + _tx_thread_smp_unprotect(tx_interrupt_save); + + _tx_win32_thread_cleanup(thread_ptr); + + tx_interrupt_save = _tx_thread_smp_protect(); + TX_PARAMETER_NOT_USED(tx_interrupt_save); +} + + +void _tx_thread_reset_port_completion(TX_THREAD *thread_ptr, UINT tx_interrupt_save) +{ + _tx_thread_delete_port_completion(thread_ptr, tx_interrupt_save); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_smp_core_get.c b/ports_smp/win64/vs_2022/src/tx_thread_smp_core_get.c new file mode 100644 index 000000000..5a1698a46 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_smp_core_get.c @@ -0,0 +1,26 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +UINT _tx_thread_smp_core_get(void) +{ + return(_tx_win32_smp_current_core_get()); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_smp_core_preempt.c b/ports_smp/win64/vs_2022/src/tx_thread_smp_core_preempt.c new file mode 100644 index 000000000..2da24fda3 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_smp_core_preempt.c @@ -0,0 +1,52 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +void _tx_thread_smp_core_preempt(UINT core) +{ +TX_THREAD *preempt_thread; + + preempt_thread = _tx_thread_current_ptr[core]; + + if (preempt_thread != TX_NULL) + { + preempt_thread -> tx_thread_win32_deferred_preempt = TX_TRUE; + _tx_win32_debug_entry_insert("CORE_PREEMPT_deferred", __FILE__, __LINE__); + + MemoryBarrier(); + if (SetEvent(_tx_win32_scheduler_event) == 0) + { + _tx_win32_system_error++; + } + } + else if (_tx_thread_execute_ptr[core] != TX_NULL) + { + _tx_win32_debug_entry_insert("CORE_PREEMPT_wake_idle", __FILE__, __LINE__); + + MemoryBarrier(); + if (SetEvent(_tx_win32_scheduler_event) == 0) + { + _tx_win32_system_error++; + } + } +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_smp_current_state_get.c b/ports_smp/win64/vs_2022/src/tx_thread_smp_current_state_get.c new file mode 100644 index 000000000..bf1726dfb --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_smp_current_state_get.c @@ -0,0 +1,49 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +ULONG _tx_thread_smp_current_state_get(void) +{ +UINT core; +DWORD thread_id; +UINT critical_section_owned; +ULONG current_state; + + thread_id = GetCurrentThreadId(); + critical_section_owned = (UINT) (_tx_win32_critical_section.tx_win32_critical_section_owner == thread_id); + + if (critical_section_owned == TX_FALSE) + { + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + } + + core = _tx_win32_smp_current_core_get(); + current_state = _tx_thread_system_state[core]; + + if (critical_section_owned == TX_FALSE) + { + _tx_win32_critical_section_release(&_tx_win32_critical_section); + } + + return(current_state); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_smp_current_thread_get.c b/ports_smp/win64/vs_2022/src/tx_thread_smp_current_thread_get.c new file mode 100644 index 000000000..ade6774f9 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_smp_current_thread_get.c @@ -0,0 +1,54 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +TX_THREAD *_tx_thread_smp_current_thread_get(void) +{ +UINT core; +DWORD thread_id; +UINT critical_section_owned; +TX_THREAD *current_thread; + + thread_id = GetCurrentThreadId(); + critical_section_owned = (UINT) (_tx_win32_critical_section.tx_win32_critical_section_owner == thread_id); + + if (critical_section_owned == TX_FALSE) + { + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + } + + core = _tx_win32_smp_current_core_get(); + current_thread = _tx_thread_current_ptr[core]; + + if ((_tx_win32_threadx_thread != 0) && (current_thread == TX_NULL)) + { + _tx_win32_debug_entry_insert("CURRENT_THREAD_GET_NULL", __FILE__, __LINE__); + } + + if (critical_section_owned == TX_FALSE) + { + _tx_win32_critical_section_release(&_tx_win32_critical_section); + } + + return(current_thread); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_smp_initialize_wait.c b/ports_smp/win64/vs_2022/src/tx_thread_smp_initialize_wait.c new file mode 100644 index 000000000..06af9a932 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_smp_initialize_wait.c @@ -0,0 +1,25 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +void _tx_thread_smp_initialize_wait(void) +{ +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_smp_low_level_initialize.c b/ports_smp/win64/vs_2022/src/tx_thread_smp_low_level_initialize.c new file mode 100644 index 000000000..a2c2e25d5 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_smp_low_level_initialize.c @@ -0,0 +1,26 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +void _tx_thread_smp_low_level_initialize(UINT number_of_cores) +{ + TX_PARAMETER_NOT_USED(number_of_cores); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_smp_protect.c b/ports_smp/win64/vs_2022/src/tx_thread_smp_protect.c new file mode 100644 index 000000000..e59caffc5 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_smp_protect.c @@ -0,0 +1,128 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.5). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +UINT _tx_thread_smp_protect(void) +{ +DWORD current_thread_id; +UINT core; +UINT interrupt_posture; +TX_THREAD *current_thread; +UINT current_state; + + do + { + do + { + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + current_thread_id = GetCurrentThreadId(); + core = _tx_thread_smp_core_get(); + current_thread = _tx_thread_current_ptr[core]; + + if ((_tx_win32_threadx_thread != 0) && + ((current_thread == TX_NULL) || (current_thread -> tx_thread_win32_thread_id != current_thread_id))) + { + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + ExitThread(0); + } + + if (_tx_win32_threadx_thread == 0) + { + break; + } + + if ((current_thread != TX_NULL) && (_tx_thread_preempt_disable == 0U)) + { + current_state = current_thread -> tx_thread_state; + if ((current_state == TX_TERMINATED) || (current_state == TX_COMPLETED)) + { + current_thread -> tx_thread_win32_deferred_preempt = TX_FALSE; + current_thread -> tx_thread_win32_suspension_type = 1U; + + if (_tx_timer_time_slice[core] != 0U) + { + current_thread -> tx_thread_time_slice = _tx_timer_time_slice[core]; + _tx_timer_time_slice[core] = 0U; + } + + _tx_thread_current_ptr[core] = TX_NULL; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread = TX_NULL; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread_handle = NULL; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread_id = 0U; + current_thread -> tx_thread_smp_core_control = 1U; + + _tx_win32_debug_entry_insert("SCHEDULE-thread_terminate_preempt_complete", __FILE__, __LINE__); + if (SetEvent(_tx_win32_scheduler_event) == 0) + { + _tx_win32_system_error++; + } + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + ExitThread(0); + } + } + + if ((current_thread != TX_NULL) && (current_thread -> tx_thread_win32_deferred_preempt != TX_FALSE)) + { + if (SetEvent(_tx_win32_scheduler_event) == 0) + { + _tx_win32_system_error++; + } + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + _tx_win32_thread_yield(); + } + else + { + break; + } + } while (1); + + interrupt_posture = (UINT) _tx_win32_global_int_disabled_flag; + + if (_tx_thread_smp_protection.tx_thread_smp_protect_core == core) + { + _tx_thread_smp_protection.tx_thread_smp_protect_count++; + _tx_win32_global_int_disabled_flag = TX_TRUE; + _tx_win32_debug_entry_insert("PROTECT-obtained-nested", __FILE__, __LINE__); + break; + } + else if (_tx_thread_smp_protection.tx_thread_smp_protect_core == 0xFFFFFFFFUL) + { + _tx_thread_smp_protection.tx_thread_smp_protect_in_force = TX_TRUE; + _tx_thread_smp_protection.tx_thread_smp_protect_thread = current_thread; + _tx_thread_smp_protection.tx_thread_smp_protect_core = core; + _tx_thread_smp_protection.tx_thread_smp_protect_count = 1U; + _tx_thread_smp_protection.tx_thread_smp_protect_thread_id = current_thread_id; + _tx_win32_global_int_disabled_flag = TX_TRUE; + _tx_win32_debug_entry_insert("PROTECT-obtained", __FILE__, __LINE__); + break; + } + else + { + _tx_win32_critical_section_release(&_tx_win32_critical_section); + } + } while (1); + + _tx_win32_global_int_disabled_flag = TX_TRUE; + return(interrupt_posture); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_smp_time_get.c b/ports_smp/win64/vs_2022/src/tx_thread_smp_time_get.c new file mode 100644 index 000000000..adf4a82e3 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_smp_time_get.c @@ -0,0 +1,27 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +ULONG _tx_thread_smp_time_get(void) +{ + QueryPerformanceCounter((LARGE_INTEGER *) &_tx_win32_time_stamp); + return((ULONG) _tx_win32_time_stamp.LowPart); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_smp_unprotect.c b/ports_smp/win64/vs_2022/src/tx_thread_smp_unprotect.c new file mode 100644 index 000000000..b845767d9 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_smp_unprotect.c @@ -0,0 +1,73 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.4). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +void _tx_thread_smp_unprotect(UINT new_interrupt_posture) +{ +UINT core; +DWORD current_thread_id; +UINT critical_section_owned; + + current_thread_id = GetCurrentThreadId(); + critical_section_owned = (UINT) (_tx_win32_critical_section.tx_win32_critical_section_owner == current_thread_id); + + if (critical_section_owned == TX_FALSE) + { + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + } + + core = _tx_thread_smp_core_get(); + + if (_tx_thread_smp_protection.tx_thread_smp_protect_core == core) + { + _tx_thread_smp_protection.tx_thread_smp_protect_count--; + + if (_tx_thread_smp_protection.tx_thread_smp_protect_count == 0U) + { + _tx_win32_global_int_disabled_flag = new_interrupt_posture; + + if (_tx_thread_preempt_disable == 0U) + { + _tx_thread_smp_protection.tx_thread_smp_protect_in_force = TX_FALSE; + _tx_thread_smp_protection.tx_thread_smp_protect_thread = TX_NULL; + _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFFUL; + _tx_thread_smp_protection.tx_thread_smp_protect_thread_id = 0U; + _tx_win32_debug_entry_insert("UNPROTECT-keep", __FILE__, __LINE__); + } + else + { + _tx_win32_debug_entry_insert("UNPROTECT-released", __FILE__, __LINE__); + } + } + else + { + _tx_win32_debug_entry_insert("UNPROTECT-nested", __FILE__, __LINE__); + } + + _tx_win32_critical_section_release(&_tx_win32_critical_section); + } + else + { + _tx_win32_critical_section_release(&_tx_win32_critical_section); + } +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_stack_build.c b/ports_smp/win64/vs_2022/src/tx_thread_stack_build.c new file mode 100644 index 000000000..0531fb3b6 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_stack_build.c @@ -0,0 +1,122 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.5). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" + +#include + +static DWORD WINAPI _tx_win32_thread_entry(LPVOID ptr); + +VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ + TX_PARAMETER_NOT_USED(function_ptr); + +#if (TX_WIN32_USE_ADDRESS_WAIT != 0) + thread_ptr -> tx_thread_win32_thread_run_semaphore = NULL; + thread_ptr -> tx_thread_win32_thread_start_semaphore = NULL; +#else + thread_ptr -> tx_thread_win32_thread_run_semaphore = CreateSemaphore(NULL, 0, 0x7FFFFFFF, NULL); + if (thread_ptr -> tx_thread_win32_thread_run_semaphore == NULL) + { + printf("ThreadX SMP Win64 error creating thread run semaphore!\n"); + while (1) + { + } + } + + thread_ptr -> tx_thread_win32_thread_start_semaphore = CreateSemaphore(NULL, 0, 1, NULL); + if (thread_ptr -> tx_thread_win32_thread_start_semaphore == NULL) + { + printf("ThreadX SMP Win64 error creating thread start semaphore!\n"); + while (1) + { + } + } +#endif + + thread_ptr -> tx_thread_win32_thread_handle = CreateThread(NULL, + TX_WIN32_THREAD_STACK_SIZE, + _tx_win32_thread_entry, + (LPVOID) thread_ptr, + CREATE_SUSPENDED, + &thread_ptr -> tx_thread_win32_thread_id); + if (thread_ptr -> tx_thread_win32_thread_handle == NULL) + { + printf("ThreadX SMP Win64 error creating thread!\n"); + while (1) + { + } + } + + SetThreadPriority(thread_ptr -> tx_thread_win32_thread_handle, TX_WIN32_PRIORITY_USER_THREAD); + + thread_ptr -> tx_thread_win32_suspension_type = 2U; + thread_ptr -> tx_thread_win32_mutex_access = TX_FALSE; + thread_ptr -> tx_thread_win32_int_disabled_flag = TX_FALSE; + thread_ptr -> tx_thread_win32_deferred_preempt = TX_FALSE; + thread_ptr -> tx_thread_win32_virtual_core = 0U; + thread_ptr -> tx_thread_win32_run_sequence = 0L; + thread_ptr -> tx_thread_win32_run_sequence_seen = 0L; + thread_ptr -> tx_thread_win32_start_sequence = 0L; + + thread_ptr -> tx_thread_stack_ptr = (VOID *) (((CHAR *) thread_ptr -> tx_thread_stack_end) - 8); + *(((ULONG *) thread_ptr -> tx_thread_stack_ptr) - 1) = 0UL; + thread_ptr -> tx_thread_smp_core_control = 1U; + + ResumeThread(thread_ptr -> tx_thread_win32_thread_handle); +} + + +static DWORD WINAPI _tx_win32_thread_entry(LPVOID ptr) +{ +TX_THREAD *thread_ptr; + + thread_ptr = (TX_THREAD *) ptr; + _tx_win32_threadx_thread = 1; + + _tx_win32_debug_entry_insert("THREAD_ENTRY_wait", __FILE__, __LINE__); + _tx_win32_wait_for_thread_run(thread_ptr); +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_mark_run_wake(thread_ptr); +#endif + _tx_win32_debug_entry_insert("THREAD_ENTRY_wake", __FILE__, __LINE__); + + /* A delete/reset cleanup may wake a host thread that was never scheduled. + Only treat the wakeup as terminal if the ThreadX thread is already in a + terminal state; otherwise allow the normal startup race to complete. */ + if ((thread_ptr -> tx_thread_smp_core_control != 0U) && + ((thread_ptr -> tx_thread_state == TX_TERMINATED) || + (thread_ptr -> tx_thread_state == TX_COMPLETED))) + { + ExitThread(0U); + } + + _tx_win32_current_virtual_core = thread_ptr -> tx_thread_win32_virtual_core; +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_mark_start_ack(thread_ptr); +#endif + _tx_win32_thread_start_ack_signal(thread_ptr); + _tx_win32_debug_entry_insert("THREAD_ENTRY_ack", __FILE__, __LINE__); + + _tx_thread_shell_entry(); + + return(0U); +} diff --git a/ports_smp/win64/vs_2022/src/tx_thread_system_return.c b/ports_smp/win64/vs_2022/src/tx_thread_system_return.c new file mode 100644 index 000000000..8207f3450 --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_thread_system_return.c @@ -0,0 +1,117 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +// Some portions generated by Codex (gpt 5.5). + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +VOID _tx_thread_system_return(VOID) +{ +TX_THREAD *temp_thread_ptr; +UINT temp_thread_state; +UINT core; +DWORD thread_id; + + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + core = _tx_thread_smp_core_get(); + thread_id = GetCurrentThreadId(); + + _tx_win32_debug_entry_insert("SYSTEM_RETURN", __FILE__, __LINE__); + + temp_thread_ptr = _tx_thread_current_ptr[core]; + + if ((_tx_win32_threadx_thread != 0) && + ((temp_thread_ptr == TX_NULL) || (temp_thread_ptr -> tx_thread_win32_thread_id != thread_id))) + { + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + ExitThread(0); + } + + if (_tx_timer_time_slice[core] != 0U) + { + temp_thread_ptr -> tx_thread_time_slice = _tx_timer_time_slice[core]; + _tx_timer_time_slice[core] = 0U; + } + + temp_thread_state = temp_thread_ptr -> tx_thread_state; + temp_thread_ptr -> tx_thread_win32_suspension_type = 2U; + _tx_thread_current_ptr[core] = TX_NULL; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread_handle = NULL; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread_id = 0U; + _tx_win32_virtual_cores[core].tx_thread_smp_core_mapping_thread = TX_NULL; + + _tx_win32_debug_entry_insert("SYSTEM_RETURN-release_sem", __FILE__, __LINE__); + + if (temp_thread_ptr != _tx_thread_smp_protection.tx_thread_smp_protect_thread) + { + _tx_win32_system_error++; + } + + _tx_thread_smp_protection.tx_thread_smp_protect_count = 0U; + _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFFUL; + _tx_thread_smp_protection.tx_thread_smp_protect_thread = TX_NULL; + _tx_thread_smp_protection.tx_thread_smp_protect_in_force = TX_FALSE; + _tx_thread_smp_protection.tx_thread_smp_protect_thread_id = 0U; + + temp_thread_ptr -> tx_thread_smp_core_control = 1U; + _tx_win32_global_int_disabled_flag = TX_FALSE; + _tx_thread_preempt_disable = 0U; + + MemoryBarrier(); + if (SetEvent(_tx_win32_scheduler_event) == 0) + { + _tx_win32_system_error++; + } + + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + + if (temp_thread_state == TX_TERMINATED) + { + ExitThread(0); + } + + _tx_win32_wait_for_thread_run(temp_thread_ptr); +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_mark_run_wake(temp_thread_ptr); +#endif + _tx_win32_current_virtual_core = temp_thread_ptr -> tx_thread_win32_virtual_core; +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_mark_start_ack(temp_thread_ptr); +#endif + _tx_win32_thread_start_ack_signal(temp_thread_ptr); + + _tx_win32_critical_section_obtain(&_tx_win32_critical_section); + + _tx_win32_debug_entry_insert("SYSTEM_RETURN-wake_up", __FILE__, __LINE__); + + core = _tx_thread_smp_core_get(); + temp_thread_ptr = _tx_thread_current_ptr[core]; + + if ((_tx_win32_threadx_thread != 0) && + ((temp_thread_ptr == TX_NULL) || (temp_thread_ptr -> tx_thread_win32_thread_id != thread_id))) + { + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); + ExitThread(0); + } + + _tx_win32_debug_entry_insert("SYSTEM_RETURN-finish", __FILE__, __LINE__); + _tx_win32_critical_section_release_all(&_tx_win32_critical_section); +} diff --git a/ports_smp/win64/vs_2022/src/tx_timer_interrupt.c b/ports_smp/win64/vs_2022/src/tx_timer_interrupt.c new file mode 100644 index 000000000..0a19d394e --- /dev/null +++ b/ports_smp/win64/vs_2022/src/tx_timer_interrupt.c @@ -0,0 +1,56 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" + +VOID _tx_timer_interrupt(VOID) +{ +UINT saved_posture; + + saved_posture = _tx_thread_smp_protect(); + + _tx_timer_interrupt_active++; + _tx_win32_debug_entry_insert("TIMER INTERRUPT", __FILE__, __LINE__); + + _tx_timer_system_clock++; + + if (*_tx_timer_current_ptr) + { + _tx_timer_expired = TX_TRUE; + } + else + { + _tx_timer_current_ptr++; + if (_tx_timer_current_ptr == _tx_timer_list_end) + { + _tx_timer_current_ptr = _tx_timer_list_start; + } + } + + if (_tx_timer_expired != TX_FALSE) + { + _tx_timer_expiration_process(); + } + + _tx_thread_time_slice(); + + _tx_timer_interrupt_active++; + _tx_thread_smp_unprotect(saved_posture); +} diff --git a/scripts/build_smp.ps1 b/scripts/build_smp.ps1 new file mode 100644 index 000000000..c66a2beb7 --- /dev/null +++ b/scripts/build_smp.ps1 @@ -0,0 +1,54 @@ +[CmdletBinding()] +param( + [AllowNull()] + [object]$Configuration = 'all', + + [int]$Parallel = [Math]::Max(1, [Environment]::ProcessorCount), + + [int]$BuildTimeoutSeconds = 180, + + [string]$BuildDir, + + [switch]$Clean +) + +$ErrorActionPreference = 'Stop' +. (Join-Path $PSScriptRoot 'tx_windows_common.ps1') + +$repoRoot = Split-Path -Parent $PSScriptRoot + +if (-not $BuildDir) { + $BuildDir = Join-Path $repoRoot 'build\tests\win64_smp' +} + +$selectedConfigurations = Resolve-RegressionConfigurations -RequestedConfigurations $Configuration +Write-Host "Selected configurations: $($selectedConfigurations -join ', ')" + +Enter-VisualStudioDevShell -VsArch 'amd64' + +foreach ($currentConfiguration in $selectedConfigurations) { + $currentBuildDirName = Get-RegressionBuildDirectoryName -ConfigurationName $currentConfiguration + $currentBuildDir = Join-Path $BuildDir $currentBuildDirName + + if ($Clean) { + Remove-BuildDirectory -Path $currentBuildDir -RepoRoot $repoRoot + } + + Remove-NinjaLock -Path $currentBuildDir + + Write-Host "Configuring win64_smp / $currentConfiguration" + Invoke-NativeCommand -FilePath 'cmake' -Arguments @( + '-S', (Join-Path $repoRoot 'test\smp\cmake'), + '-B', $currentBuildDir, + '-G', 'Ninja', + '-DCMAKE_C_COMPILER_FORCED=TRUE', + '-DCMAKE_C_COMPILER_WORKS=TRUE', + '-DCMAKE_C_ABI_COMPILED=TRUE', + "-DCMAKE_BUILD_TYPE=$currentConfiguration", + '-DTHREADX_ARCH=win64', + '-DTHREADX_TOOLCHAIN=vs_2022' + ) + + Write-Host "Building win64_smp / $currentConfiguration" + Invoke-CMakeBuild -BuildDir $currentBuildDir -Parallel $Parallel -TimeoutSeconds $BuildTimeoutSeconds +} diff --git a/scripts/build_tx.ps1 b/scripts/build_tx.ps1 new file mode 100644 index 000000000..eeaa2222a --- /dev/null +++ b/scripts/build_tx.ps1 @@ -0,0 +1,58 @@ +[CmdletBinding()] +param( + [ValidateSet('win64', 'win32')] + [string]$Arch = 'win64', + + [AllowNull()] + [object]$Configuration = 'all', + + [int]$Parallel = [Math]::Max(1, [Environment]::ProcessorCount), + + [int]$BuildTimeoutSeconds = 60, + + [string]$BuildDir, + + [switch]$Clean +) + +$ErrorActionPreference = 'Stop' +. (Join-Path $PSScriptRoot 'tx_windows_common.ps1') + +$repoRoot = Split-Path -Parent $PSScriptRoot +$settings = Get-PortSettings -SelectedArch $Arch + +if (-not $BuildDir) { + $BuildDir = Join-Path $repoRoot "build\tests\$Arch" +} + +$selectedConfigurations = Resolve-RegressionConfigurations -RequestedConfigurations $Configuration +Write-Host "Selected configurations: $($selectedConfigurations -join ', ')" + +Enter-VisualStudioDevShell -VsArch $settings.VsArch + +foreach ($currentConfiguration in $selectedConfigurations) { + $currentBuildDirName = Get-RegressionBuildDirectoryName -ConfigurationName $currentConfiguration + $currentBuildDir = Join-Path $BuildDir $currentBuildDirName + + if ($Clean) { + Remove-BuildDirectory -Path $currentBuildDir -RepoRoot $repoRoot + } + + Remove-NinjaLock -Path $currentBuildDir + + Write-Host "Configuring $Arch / $currentConfiguration" + Invoke-NativeCommand -FilePath 'cmake' -Arguments @( + '-S', (Join-Path $repoRoot 'test\tx\cmake'), + '-B', $currentBuildDir, + '-G', 'Ninja', + '-DCMAKE_C_COMPILER_FORCED=TRUE', + '-DCMAKE_C_COMPILER_WORKS=TRUE', + '-DCMAKE_C_ABI_COMPILED=TRUE', + "-DCMAKE_BUILD_TYPE=$currentConfiguration", + "-DTHREADX_ARCH=$($settings.ThreadXArch)", + "-DTHREADX_TOOLCHAIN=$($settings.ThreadXToolchain)" + ) + + Write-Host "Building $Arch / $currentConfiguration" + Invoke-CMakeBuild -BuildDir $currentBuildDir -Parallel $Parallel -TimeoutSeconds $BuildTimeoutSeconds +} diff --git a/scripts/test_smp.ps1 b/scripts/test_smp.ps1 new file mode 100644 index 000000000..e71b10815 --- /dev/null +++ b/scripts/test_smp.ps1 @@ -0,0 +1,120 @@ +[CmdletBinding()] +param( + [AllowNull()] + [object]$Configuration = 'all', + + [int]$Parallel = 1, + + [int]$RepeatFailCount = 2, + + [int]$TestTimeoutSeconds = 45, + + [switch]$CollectFailureDiagnostics = $true, + + [string]$TestRegex, + + [switch]$RerunFailedOnly, + + [string]$BuildDir, + + [switch]$Clean +) + +$ErrorActionPreference = 'Stop' +. (Join-Path $PSScriptRoot 'tx_windows_common.ps1') + +$repoRoot = Split-Path -Parent $PSScriptRoot + +if (-not $BuildDir) { + $BuildDir = Join-Path $repoRoot 'build\tests\win64_smp' +} + +$selectedConfigurations = Resolve-RegressionConfigurations -RequestedConfigurations $Configuration +Write-Host "Selected configurations: $($selectedConfigurations -join ', ')" + +Enter-VisualStudioDevShell -VsArch 'amd64' + +if ($Parallel -ne 1) { + Write-Warning 'Windows SMP simulator regression tests are timing-sensitive. Forcing -Parallel 1.' + $Parallel = 1 +} + +if ($TestRegex -and -not $PSBoundParameters.ContainsKey('TestTimeoutSeconds')) { + $TestTimeoutSeconds = 60 + Write-Host "Targeted run detected; using per-test timeout of $TestTimeoutSeconds seconds." +} + +$failedConfigurations = @() + +foreach ($currentConfiguration in $selectedConfigurations) { + $currentBuildDirName = Get-RegressionBuildDirectoryName -ConfigurationName $currentConfiguration + $currentBuildDir = Join-Path $BuildDir $currentBuildDirName + $currentTestingTemporaryDir = Join-Path $currentBuildDir 'Testing\Temporary' + + try { + if ($Clean) { + $currentTestingDir = Join-Path $currentBuildDir 'Testing' + Remove-CtestTestingDirectory -Path $currentTestingDir + } + + if (-not (Test-Path -LiteralPath $currentBuildDir)) { + throw "Build directory does not exist for win64_smp / ${currentConfiguration}: $currentBuildDir" + } + + Remove-NinjaLock -Path $currentBuildDir + if (Test-Path -LiteralPath $currentTestingTemporaryDir) { + Remove-Item -LiteralPath (Join-Path $currentTestingTemporaryDir 'LastTest.log') -Force -ErrorAction SilentlyContinue + Remove-Item -LiteralPath (Join-Path $currentTestingTemporaryDir 'LastTestsFailed.log') -Force -ErrorAction SilentlyContinue + } + + Write-Host "Testing win64_smp / $currentConfiguration" + $ctestArguments = @( + '--test-dir', $currentBuildDir, + '--output-on-failure', + '--timeout', $TestTimeoutSeconds.ToString(), + '-j', $Parallel.ToString() + ) + + if ($RepeatFailCount -gt 1) { + $ctestArguments += @('--repeat', "until-pass:$RepeatFailCount") + } + + if ($TestRegex) { + $ctestArguments += @('-R', $TestRegex) + } + + if ($RerunFailedOnly) { + $ctestArguments += '--rerun-failed' + } + + Invoke-NativeCommand -FilePath 'ctest' -Arguments $ctestArguments + } + catch { + if ($CollectFailureDiagnostics -and (Test-Path -LiteralPath $currentBuildDir)) { + try { + Invoke-CtestFailureDiagnostics -BuildDir $currentBuildDir -TestingTemporaryDir $currentTestingTemporaryDir ` + -TimeoutSeconds $TestTimeoutSeconds + } + catch { + Write-Warning "Failure diagnostics collection failed for ${currentConfiguration}: $($_.Exception.Message)" + } + } + + $failedConfigurations += @{ + Configuration = $currentConfiguration + Message = $_.Exception.Message + } + + Write-Warning "Configuration failed: $currentConfiguration" + } +} + +if ($failedConfigurations.Count -gt 0) { + Write-Host '' + Write-Host 'Configuration failure summary:' + foreach ($failedConfiguration in $failedConfigurations) { + Write-Host "- $($failedConfiguration.Configuration): $($failedConfiguration.Message)" + } + + throw "One or more configurations failed: $($failedConfigurations.Configuration -join ', ')" +} diff --git a/scripts/test_tx.ps1 b/scripts/test_tx.ps1 new file mode 100644 index 000000000..a5607ed7f --- /dev/null +++ b/scripts/test_tx.ps1 @@ -0,0 +1,121 @@ +[CmdletBinding()] +param( + [ValidateSet('win64', 'win32')] + [string]$Arch = 'win64', + + [AllowNull()] + [object]$Configuration = 'all', + + [int]$Parallel = [Math]::Max(1, [Environment]::ProcessorCount), + + [int]$RepeatFailCount = 1, + + [int]$TestTimeoutSeconds = 20, + + [switch]$CollectFailureDiagnostics = $true, + + [string]$TestRegex, + + [switch]$RerunFailedOnly, + + [string]$BuildDir, + + [switch]$Clean +) + +$ErrorActionPreference = 'Stop' +. (Join-Path $PSScriptRoot 'tx_windows_common.ps1') + +$repoRoot = Split-Path -Parent $PSScriptRoot +$settings = Get-PortSettings -SelectedArch $Arch + +if (-not $BuildDir) { + $BuildDir = Join-Path $repoRoot "build\tests\$Arch" +} + +$selectedConfigurations = Resolve-RegressionConfigurations -RequestedConfigurations $Configuration +Write-Host "Selected configurations: $($selectedConfigurations -join ', ')" + +Enter-VisualStudioDevShell -VsArch $settings.VsArch + +if (($settings.ThreadXArch -eq 'win32') -or ($settings.ThreadXArch -eq 'win64')) { + if ($Parallel -ne 1) { + Write-Warning "Windows simulator regression tests are timing-sensitive under concurrent ctest execution. Forcing -Parallel 1." + $Parallel = 1 + } +} + +$failedConfigurations = @() + +foreach ($currentConfiguration in $selectedConfigurations) { + $currentBuildDirName = Get-RegressionBuildDirectoryName -ConfigurationName $currentConfiguration + $currentBuildDir = Join-Path $BuildDir $currentBuildDirName + $currentTestingTemporaryDir = Join-Path $currentBuildDir 'Testing\Temporary' + + try { + if ($Clean) { + $currentTestingDir = Join-Path $currentBuildDir 'Testing' + Remove-CtestTestingDirectory -Path $currentTestingDir + } + + if (-not (Test-Path -LiteralPath $currentBuildDir)) { + throw "Build directory does not exist for $Arch / ${currentConfiguration}: $currentBuildDir" + } + + Remove-NinjaLock -Path $currentBuildDir + if (Test-Path -LiteralPath $currentTestingTemporaryDir) { + Remove-Item -LiteralPath (Join-Path $currentTestingTemporaryDir 'LastTest.log') -Force -ErrorAction SilentlyContinue + Remove-Item -LiteralPath (Join-Path $currentTestingTemporaryDir 'LastTestsFailed.log') -Force -ErrorAction SilentlyContinue + } + + Write-Host "Testing $Arch / $currentConfiguration" + $ctestArguments = @( + '--test-dir', $currentBuildDir, + '--output-on-failure', + '--timeout', $TestTimeoutSeconds.ToString(), + '-j', $Parallel.ToString() + ) + + if ($RepeatFailCount -gt 1) { + $ctestArguments += @('--repeat', "until-pass:$RepeatFailCount") + } + + if ($TestRegex) { + $ctestArguments += @('-R', $TestRegex) + } + + if ($RerunFailedOnly) { + $ctestArguments += '--rerun-failed' + } + + Invoke-NativeCommand -FilePath 'ctest' -Arguments $ctestArguments + } + catch { + if ($CollectFailureDiagnostics -and (Test-Path -LiteralPath $currentBuildDir)) { + try { + Invoke-CtestFailureDiagnostics -BuildDir $currentBuildDir -TestingTemporaryDir $currentTestingTemporaryDir ` + -TimeoutSeconds $TestTimeoutSeconds + } + catch { + Write-Warning "Failure diagnostics collection failed for ${currentConfiguration}: $($_.Exception.Message)" + } + } + + $failedConfigurations += @{ + Configuration = $currentConfiguration + Message = $_.Exception.Message + } + + Write-Warning "Configuration failed: $currentConfiguration" + } +} + +if ($failedConfigurations.Count -gt 0) { + Write-Host '' + Write-Host 'Configuration failure summary:' + foreach ($failedConfiguration in $failedConfigurations) { + Write-Host "- $($failedConfiguration.Configuration): $($failedConfiguration.Message)" + } + + throw "One or more configurations failed: $($failedConfigurations.Configuration -join ', ')" +} diff --git a/scripts/tx_windows_common.ps1 b/scripts/tx_windows_common.ps1 new file mode 100644 index 000000000..7b712d4ad --- /dev/null +++ b/scripts/tx_windows_common.ps1 @@ -0,0 +1,941 @@ +[CmdletBinding()] +param() + +$ErrorActionPreference = 'Stop' + +function Invoke-NativeCommand { + param( + [Parameter(Mandatory = $true)] + [string]$FilePath, + + [Parameter()] + [string[]]$Arguments = @() + ) + + & $FilePath @Arguments + if ($LASTEXITCODE -ne 0) { + throw "Command failed with exit code ${LASTEXITCODE}: $FilePath $($Arguments -join ' ')" + } +} + +function Get-CommandPathIfAvailable { + param( + [Parameter(Mandatory = $true)] + [string]$CommandName + ) + + $command = Get-Command $CommandName -ErrorAction SilentlyContinue + if ($null -eq $command) { + return $null + } + + return $command.Source +} + +function Get-PortSettings { + param( + [Parameter(Mandatory = $true)] + [string]$SelectedArch + ) + + switch ($SelectedArch) { + 'win32' { + return @{ + ThreadXArch = 'win32' + ThreadXToolchain = 'vs_2019' + VsArch = 'x86' + } + } + 'win64' { + return @{ + ThreadXArch = 'win64' + ThreadXToolchain = 'vs_2022' + VsArch = 'amd64' + } + } + default { + throw "Unsupported architecture: $SelectedArch" + } + } +} + +function Get-RegressionConfigurations { + return @( + 'default_build_coverage', + 'disable_notify_callbacks_build', + 'stack_checking_build', + 'stack_checking_rand_fill_build', + 'trace_build' + ) +} + +function Resolve-RegressionConfigurations { + param( + [Parameter(Mandatory = $false)] + [AllowNull()] + [AllowEmptyCollection()] + [object]$RequestedConfigurations = 'all' + ) + + $allConfigurations = Get-RegressionConfigurations + $resolvedConfigurations = @() + + if ($null -eq $RequestedConfigurations) { + $resolvedConfigurations = @('all') + } + elseif ($RequestedConfigurations -is [System.Array]) { + foreach ($requestedConfiguration in $RequestedConfigurations) { + if ($null -ne $requestedConfiguration) { + $resolvedConfigurations += [string]$requestedConfiguration + } + } + } + else { + $resolvedConfigurations = @([string]$RequestedConfigurations) + } + + $normalizedConfigurations = @() + foreach ($requestedConfiguration in $resolvedConfigurations) { + foreach ($configurationPart in ($requestedConfiguration -split ',')) { + $trimmedConfiguration = $configurationPart.Trim() + if ($trimmedConfiguration.Length -gt 0) { + $normalizedConfigurations += $trimmedConfiguration + } + } + } + + if (($normalizedConfigurations.Count -eq 0) -or ($normalizedConfigurations -contains 'all')) { + return $allConfigurations + } + + foreach ($normalizedConfiguration in $normalizedConfigurations) { + if ($allConfigurations -notcontains $normalizedConfiguration) { + throw "Unsupported configuration: $normalizedConfiguration" + } + } + + return $normalizedConfigurations +} + +function Get-RegressionBuildDirectoryName { + param( + [Parameter(Mandatory = $true)] + [string]$ConfigurationName + ) + + switch ($ConfigurationName) { + 'default_build_coverage' { + return 'dbc' + } + 'disable_notify_callbacks_build' { + return 'dnc' + } + 'stack_checking_build' { + return 'sc' + } + 'stack_checking_rand_fill_build' { + return 'scrf' + } + 'trace_build' { + return 'tr' + } + default { + throw "Unsupported configuration: $ConfigurationName" + } + } +} + +function Enter-VisualStudioDevShell { + param( + [Parameter(Mandatory = $true)] + [string]$VsArch + ) + + $targetArch = switch ($VsArch) { + 'amd64' { 'x64' } + 'x86' { 'x86' } + default { $VsArch } + } + + if ((Get-Command cl -ErrorAction SilentlyContinue) -and ($env:VSCMD_ARG_TGT_ARCH -eq $targetArch)) { + return + } + + $vsWherePath = Join-Path ${env:ProgramFiles(x86)} 'Microsoft Visual Studio\Installer\vswhere.exe' + if (-not (Test-Path -LiteralPath $vsWherePath)) { + throw "Unable to locate vswhere.exe at $vsWherePath" + } + + $installationPath = & $vsWherePath -latest -products * -requires Microsoft.VisualStudio.Component.VC.Tools.x86.x64 -property installationPath + if (-not $installationPath) { + throw 'Unable to locate a Visual Studio 2022 installation with MSVC build tools.' + } + + $launchScript = Join-Path $installationPath 'Common7\Tools\Launch-VsDevShell.ps1' + if (-not (Test-Path -LiteralPath $launchScript)) { + throw "Unable to locate Launch-VsDevShell.ps1 at $launchScript" + } + + $env:VSCMD_SKIP_SENDTELEMETRY = '1' + & $launchScript -VsInstallationPath $installationPath -Arch $VsArch -HostArch amd64 -SkipAutomaticLocation | Out-Null + + if (-not (Get-Command cl -ErrorAction SilentlyContinue)) { + throw 'MSVC compiler environment was not activated successfully.' + } +} + +function Remove-BuildDirectory { + param( + [Parameter(Mandatory = $true)] + [string]$Path, + + [Parameter(Mandatory = $true)] + [string]$RepoRoot + ) + + $fullRepoRoot = [System.IO.Path]::GetFullPath($RepoRoot) + $fullPath = [System.IO.Path]::GetFullPath($Path) + + if (-not $fullPath.StartsWith($fullRepoRoot, [System.StringComparison]::OrdinalIgnoreCase)) { + throw "Refusing to remove a directory outside the repository: $fullPath" + } + + if (Test-Path -LiteralPath $fullPath) { + try { + Remove-Item -LiteralPath $fullPath -Recurse -Force -ErrorAction Stop + return + } catch { + Write-Warning "Failed to remove build directory '$fullPath': $($_.Exception.Message)" + } + + Get-ChildItem -LiteralPath $fullPath -Force -Recurse -ErrorAction SilentlyContinue | ForEach-Object { + try { + if (($_.Attributes -band [System.IO.FileAttributes]::ReadOnly) -ne 0) { + $_.Attributes = ($_.Attributes -band (-bnot [System.IO.FileAttributes]::ReadOnly)) + } + } catch { + } + } + + try { + Remove-Item -LiteralPath $fullPath -Recurse -Force -ErrorAction Stop + } catch { + Write-Warning "Proceeding with partially cleaned build directory '$fullPath': $($_.Exception.Message)" + } + } +} + +function Remove-CtestTestingDirectory { + param( + [Parameter(Mandatory = $true)] + [string]$Path + ) + + if (-not (Test-Path -LiteralPath $Path)) { + return + } + + try { + Remove-Item -LiteralPath $Path -Recurse -Force -ErrorAction Stop + return + } catch { + Write-Warning "Failed to remove CTest directory '$Path': $($_.Exception.Message)" + } + + Get-ChildItem -LiteralPath $Path -Force -Recurse -ErrorAction SilentlyContinue | ForEach-Object { + try { + if (($_.Attributes -band [System.IO.FileAttributes]::ReadOnly) -ne 0) { + $_.Attributes = ($_.Attributes -band (-bnot [System.IO.FileAttributes]::ReadOnly)) + } + } catch { + } + } + + try { + Remove-Item -LiteralPath $Path -Recurse -Force -ErrorAction Stop + } catch { + Write-Warning "Proceeding with partially cleaned CTest directory '$Path': $($_.Exception.Message)" + } +} + +function Remove-NinjaLock { + param( + [Parameter(Mandatory = $true)] + [string]$Path + ) + + $ninjaLockPath = Join-Path $Path '.ninja_lock' + if (Test-Path -LiteralPath $ninjaLockPath) { + Remove-Item -LiteralPath $ninjaLockPath -Force + } +} + +function Get-WindowsDebuggerPath { + $debuggerPath = Get-CommandPathIfAvailable -CommandName 'cdb.exe' + if ($debuggerPath) { + return $debuggerPath + } + + $candidatePaths = @( + (Join-Path ${env:ProgramFiles(x86)} 'Windows Kits\10\Debuggers\x64\cdb.exe'), + (Join-Path ${env:ProgramFiles(x86)} 'Windows Kits\10\Debuggers\x86\cdb.exe') + ) + + foreach ($candidatePath in $candidatePaths) { + if (Test-Path -LiteralPath $candidatePath) { + return $candidatePath + } + } + + return $null +} + +function Get-SanitizedFileName { + param( + [Parameter(Mandatory = $true)] + [string]$Name + ) + + $safeName = [regex]::Replace($Name, '[<>:"/\\|?*]', '_') + $safeName = $safeName -replace '\s+', '_' + return $safeName +} + +function Initialize-MinidumpSupport { + if ($null -ne ('ThreadX.WindowsMiniDump' -as [type])) { + return + } + + Add-Type -TypeDefinition @' +using System; +using System.IO; +using System.Runtime.InteropServices; + +namespace ThreadX +{ + public static class WindowsMiniDump + { + [DllImport("Dbghelp.dll", SetLastError = true)] + private static extern bool MiniDumpWriteDump( + IntPtr hProcess, + uint processId, + IntPtr hFile, + uint dumpType, + IntPtr exceptionParam, + IntPtr userStreamParam, + IntPtr callbackParam); + + [DllImport("kernel32.dll", SetLastError = true)] + private static extern IntPtr OpenProcess(uint desiredAccess, bool inheritHandle, int processId); + + [DllImport("kernel32.dll", SetLastError = true)] + private static extern bool CloseHandle(IntPtr handle); + + private const uint ProcessQueryInformation = 0x0400U; + private const uint ProcessVmRead = 0x0010U; + private const uint ProcessDupHandle = 0x0040U; + + public static bool WriteDump(int processId, string dumpPath, uint dumpType, out int errorCode) + { + IntPtr processHandle = OpenProcess(ProcessQueryInformation | ProcessVmRead | ProcessDupHandle, false, processId); + if (processHandle == IntPtr.Zero) + { + errorCode = Marshal.GetLastWin32Error(); + return false; + } + + try + { + using (FileStream dumpStream = new FileStream(dumpPath, FileMode.Create, FileAccess.ReadWrite, FileShare.Read)) + { + bool success = MiniDumpWriteDump( + processHandle, + unchecked((uint)processId), + dumpStream.SafeFileHandle.DangerousGetHandle(), + dumpType, + IntPtr.Zero, + IntPtr.Zero, + IntPtr.Zero); + + errorCode = success ? 0 : Marshal.GetLastWin32Error(); + return success; + } + } + finally + { + CloseHandle(processHandle); + } + } + } +} +'@ +} + +function Wait-FileReadable { + param( + [Parameter(Mandatory = $true)] + [string]$Path, + + [Parameter()] + [int]$TimeoutSeconds = 10 + ) + + $deadline = (Get-Date).AddSeconds($TimeoutSeconds) + while ((Get-Date) -lt $deadline) { + if (-not (Test-Path -LiteralPath $Path)) { + Start-Sleep -Milliseconds 200 + continue + } + + try { + $fileStream = [System.IO.File]::Open($Path, [System.IO.FileMode]::Open, [System.IO.FileAccess]::Read, [System.IO.FileShare]::ReadWrite) + $fileStream.Dispose() + return $true + } + catch { + Start-Sleep -Milliseconds 200 + } + } + + return $false +} + +function Get-CtestTestMetadata { + param( + [Parameter(Mandatory = $true)] + [string]$BuildDir + ) + + $ctestOutput = & ctest --test-dir $BuildDir --show-only=json-v1 + if ($LASTEXITCODE -ne 0) { + throw "Unable to enumerate ctest metadata in $BuildDir" + } + + return (($ctestOutput -join [Environment]::NewLine) | ConvertFrom-Json).tests +} + +function Get-CtestFailedTestNames { + param( + [Parameter(Mandatory = $true)] + [string]$TestingTemporaryDir + ) + + $lastFailedPath = Join-Path $TestingTemporaryDir 'LastTestsFailed.log' + if (-not (Test-Path -LiteralPath $lastFailedPath)) { + return @() + } + + $failedTestNames = @() + foreach ($logLine in (Get-Content -LiteralPath $lastFailedPath)) { + if ([string]::IsNullOrWhiteSpace($logLine)) { + continue + } + + if ($logLine -match '^\s*\d+:(?.+)\s*$') { + $failedTestNames += $Matches['name'].Trim() + } + else { + $failedTestNames += $logLine.Trim() + } + } + + return $failedTestNames +} + +function Invoke-ProcessDumpCapture { + param( + [Parameter(Mandatory = $true)] + [int]$ProcessId, + + [Parameter(Mandatory = $true)] + [string]$DumpPath, + + [Parameter()] + [int]$TimeoutSeconds = 15 + ) + + $outputDirectory = Split-Path -Parent $DumpPath + if (-not (Test-Path -LiteralPath $outputDirectory)) { + New-Item -ItemType Directory -Path $outputDirectory | Out-Null + } + + Remove-Item -LiteralPath $DumpPath -Force -ErrorAction SilentlyContinue + + Initialize-MinidumpSupport + $dumpType = [uint32]0x00001006 + $errorCode = 0 + $dumpCaptured = [ThreadX.WindowsMiniDump]::WriteDump($ProcessId, $DumpPath, $dumpType, [ref]$errorCode) + + if (-not $dumpCaptured) { + Write-Warning "MiniDumpWriteDump failed for PID ${ProcessId} with Win32 error $errorCode" + return $false + } + + return (Test-Path -LiteralPath $DumpPath) +} + +function Invoke-DumpStackAnalysis { + param( + [Parameter(Mandatory = $true)] + [string]$DumpPath, + + [Parameter(Mandatory = $true)] + [string]$OutputBasePath, + + [Parameter()] + [string]$SymbolPath, + + [Parameter()] + [int]$TimeoutSeconds = 15 + ) + + if (-not (Test-Path -LiteralPath $DumpPath)) { + Write-Warning "Skipping dump analysis because the dump file was not created: $DumpPath" + return $false + } + + if (-not (Wait-FileReadable -Path $DumpPath)) { + Write-Warning "Skipping dump analysis because the dump file is not readable yet: $DumpPath" + return $false + } + + $debuggerPath = Get-WindowsDebuggerPath + if (-not $debuggerPath) { + Write-Warning 'Skipping dump analysis because cdb.exe is not available.' + return $false + } + + $outputDirectory = Split-Path -Parent $OutputBasePath + if (-not (Test-Path -LiteralPath $outputDirectory)) { + New-Item -ItemType Directory -Path $outputDirectory | Out-Null + } + + $stdoutPath = "${OutputBasePath}.stdout.txt" + $stderrPath = "${OutputBasePath}.stderr.txt" + $commandFilePath = "${OutputBasePath}.commands.txt" + Set-Content -LiteralPath $commandFilePath -Value @( + '!runaway 7' + '~* kb 200' + 'q' + ) -Encoding Ascii + $cdbArguments = @( + '-lines', + '-z', $DumpPath + ) + + if ($SymbolPath) { + $cdbArguments += @('-y', $SymbolPath) + } + + $cdbArguments += @('-cf', $commandFilePath) + $cdbProcess = Start-Process -FilePath $debuggerPath -ArgumentList $cdbArguments -PassThru -NoNewWindow ` + -RedirectStandardOutput $stdoutPath -RedirectStandardError $stderrPath + + try { + $cdbProcess | Wait-Process -Timeout $TimeoutSeconds -ErrorAction Stop + } + catch { + if (-not $cdbProcess.HasExited) { + $null = Start-Process -FilePath 'taskkill.exe' -ArgumentList @('/PID', $cdbProcess.Id.ToString(), '/T', '/F') ` + -WindowStyle Hidden -Wait -PassThru + } + } + + return $true +} + +function Invoke-ProcessWithTimeout { + param( + [Parameter(Mandatory = $true)] + [string]$FilePath, + + [Parameter()] + [string[]]$Arguments = @(), + + [Parameter()] + [int]$TimeoutSeconds = 0, + + [Parameter()] + [string]$WorkingDirectory, + + [Parameter()] + [string]$RedirectStandardOutputPath, + + [Parameter()] + [string]$RedirectStandardErrorPath, + + [Parameter()] + [scriptblock]$OnTimeout, + + [Parameter()] + [scriptblock]$PostTimeout + ) + + $argumentList = @() + foreach ($argument in $Arguments) { + if ($argument -match '\s|"') { + $argumentList += '"' + ($argument -replace '"', '\"') + '"' + } + else { + $argumentList += $argument + } + } + + $startProcessParameters = @{ + FilePath = $FilePath + NoNewWindow = $true + PassThru = $true + } + + if ($argumentList.Count -gt 0) { + $startProcessParameters['ArgumentList'] = $argumentList + } + + if ($WorkingDirectory) { + $startProcessParameters['WorkingDirectory'] = $WorkingDirectory + } + + if ($RedirectStandardOutputPath) { + $startProcessParameters['RedirectStandardOutput'] = $RedirectStandardOutputPath + } + + if ($RedirectStandardErrorPath) { + $startProcessParameters['RedirectStandardError'] = $RedirectStandardErrorPath + } + + $process = Start-Process @startProcessParameters + if ($TimeoutSeconds -le 0) { + $process | Wait-Process + $completed = $true + } + else { + try { + $process | Wait-Process -Timeout $TimeoutSeconds -ErrorAction Stop + $completed = $true + } + catch { + $completed = $false + } + } + + if (-not $completed) { + if ($null -ne $OnTimeout) { + & $OnTimeout $process + } + + $null = Start-Process -FilePath 'taskkill.exe' -ArgumentList @('/PID', $process.Id.ToString(), '/T', '/F') -WindowStyle Hidden -Wait -PassThru + + if ($null -ne $PostTimeout) { + & $PostTimeout $process + } + + return @{ + Completed = $false + ExitCode = $null + ProcessId = $process.Id + } + } + + $process.Refresh() + return @{ + Completed = $true + ExitCode = $process.ExitCode + ProcessId = $process.Id + } +} + +function Invoke-CtestFailureDiagnostics { + param( + [Parameter(Mandatory = $true)] + [string]$BuildDir, + + [Parameter(Mandatory = $true)] + [string]$TestingTemporaryDir, + + [Parameter(Mandatory = $true)] + [int]$TimeoutSeconds + ) + + $failedTestNames = Get-CtestFailedTestNames -TestingTemporaryDir $TestingTemporaryDir + if ($failedTestNames.Count -eq 0) { + Write-Warning "No failed tests were recorded in $TestingTemporaryDir" + return + } + + $testMetadataList = Get-CtestTestMetadata -BuildDir $BuildDir + $testMetadataMap = @{} + foreach ($testMetadata in $testMetadataList) { + $testMetadataMap[$testMetadata.name] = $testMetadata + } + + $diagnosticsRoot = Join-Path $TestingTemporaryDir 'FailureDiagnostics' + if (-not (Test-Path -LiteralPath $diagnosticsRoot)) { + New-Item -ItemType Directory -Path $diagnosticsRoot | Out-Null + } + + foreach ($failedTestName in $failedTestNames) { + if (-not $testMetadataMap.ContainsKey($failedTestName)) { + Write-Warning "Unable to locate ctest metadata for failed test: $failedTestName" + continue + } + + $testMetadata = $testMetadataMap[$failedTestName] + if (($null -eq $testMetadata.command) -or ($testMetadata.command.Count -eq 0)) { + Write-Warning "No executable command was recorded for failed test: $failedTestName" + continue + } + + $testArguments = @() + if ($testMetadata.command.Count -gt 1) { + $testArguments = @($testMetadata.command[1..($testMetadata.command.Count - 1)]) + } + + $safeTestName = Get-SanitizedFileName -Name $failedTestName + $stdoutPath = Join-Path $diagnosticsRoot "${safeTestName}.stdout.txt" + $stderrPath = Join-Path $diagnosticsRoot "${safeTestName}.stderr.txt" + $debugOutputBasePath = Join-Path $diagnosticsRoot "${safeTestName}.cdb" + $workingDirectory = $null + $symbolDirectory = Split-Path -Parent $testMetadata.command[0] + + if ($null -ne $testMetadata.properties) { + foreach ($testProperty in $testMetadata.properties) { + if ($testProperty.name -eq 'WORKING_DIRECTORY') { + $workingDirectory = $testProperty.value + break + } + } + } + + Write-Warning "Collecting failure diagnostics for $failedTestName" + $dumpPath = '{0}.{1}.dmp' -f $debugOutputBasePath, ([DateTime]::UtcNow.ToString('yyyyMMddHHmmssfff')) + $testResult = Invoke-ProcessWithTimeout -FilePath $testMetadata.command[0] -Arguments $testArguments ` + -TimeoutSeconds $TimeoutSeconds -WorkingDirectory $workingDirectory -RedirectStandardOutputPath $stdoutPath ` + -RedirectStandardErrorPath $stderrPath -OnTimeout { + param($timedOutProcess) + Invoke-ProcessDumpCapture -ProcessId $timedOutProcess.Id -DumpPath $dumpPath | Out-Null + } -PostTimeout { + param($timedOutProcess) + if (Test-Path -LiteralPath $dumpPath) { + Invoke-DumpStackAnalysis -DumpPath $dumpPath -OutputBasePath $debugOutputBasePath -SymbolPath $symbolDirectory | Out-Null + } + } + + if (-not $testResult.Completed) { + Write-Warning "Timeout diagnostics were captured for $failedTestName under $diagnosticsRoot" + continue + } + + Write-Warning "Replay finished for $failedTestName with exit code $($testResult.ExitCode). Output was saved under $diagnosticsRoot" + } +} + +function Test-IsNinjaBuildDirectory { + param( + [Parameter(Mandatory = $true)] + [string]$BuildDir + ) + + return (Test-Path -LiteralPath (Join-Path $BuildDir 'build.ninja')) +} + +function Get-NinjaBuildStatements { + param( + [Parameter(Mandatory = $true)] + [string]$BuildDir + ) + + $buildNinjaPath = Join-Path $BuildDir 'build.ninja' + if (-not (Test-Path -LiteralPath $buildNinjaPath)) { + throw "Unable to locate build.ninja in $BuildDir" + } + + return Get-Content -LiteralPath $buildNinjaPath +} + +function New-NinjaRspFile { + param( + [Parameter(Mandatory = $true)] + [string]$BuildDir, + + [Parameter(Mandatory = $true)] + [string]$RspRelativePath + ) + + $buildStatements = Get-NinjaBuildStatements -BuildDir $BuildDir + $rspLine = ' RSP_FILE = ' + $RspRelativePath + $rspIndex = -1 + + for ($index = 0; $index -lt $buildStatements.Count; $index++) { + if ($buildStatements[$index] -eq $rspLine) { + $rspIndex = $index + break + } + } + + if ($rspIndex -lt 0) { + throw "Unable to locate RSP_FILE entry for $RspRelativePath in build.ninja." + } + + $buildIndex = -1 + for ($index = $rspIndex; $index -ge 0; $index--) { + if ($buildStatements[$index].StartsWith('build ')) { + $buildIndex = $index + break + } + } + + if ($buildIndex -lt 0) { + throw "Unable to locate the build statement that owns $RspRelativePath." + } + + $buildLine = $buildStatements[$buildIndex] + if ($buildLine -notmatch '^build\s+\S+:\s+\S+\s+(.+)$') { + throw "Unable to parse build statement for $RspRelativePath." + } + + $rspContents = ($Matches[1] -split '\s+') -join [Environment]::NewLine + $rspPath = Join-Path $BuildDir $RspRelativePath + $rspParent = Split-Path -Parent $rspPath + + if (-not (Test-Path -LiteralPath $rspParent)) { + New-Item -ItemType Directory -Path $rspParent | Out-Null + } + + Set-Content -LiteralPath $rspPath -Value $rspContents +} + +function Ensure-NinjaRspFiles { + param( + [Parameter(Mandatory = $true)] + [string]$BuildDir, + + [Parameter(Mandatory = $true)] + [string]$CommandLine + ) + + $rspMatches = [regex]::Matches($CommandLine, '@(?[^\s"]+\.rsp)') + foreach ($rspMatch in $rspMatches) { + $rspRelativePath = $rspMatch.Groups['path'].Value + $rspPath = Join-Path $BuildDir $rspRelativePath + if (-not (Test-Path -LiteralPath $rspPath)) { + New-NinjaRspFile -BuildDir $BuildDir -RspRelativePath $rspRelativePath + } + } +} + +function Get-PendingNinjaCommands { + param( + [Parameter(Mandatory = $true)] + [string]$BuildDir + ) + + $commandLines = & ninja -C $BuildDir -t commands + if ($LASTEXITCODE -ne 0) { + throw "Unable to enumerate pending Ninja commands in $BuildDir" + } + + return $commandLines | Where-Object { -not [string]::IsNullOrWhiteSpace($_) } +} + +function Invoke-NinjaFallbackBuild { + param( + [Parameter(Mandatory = $true)] + [string]$BuildDir + ) + + $pendingCommands = Get-PendingNinjaCommands -BuildDir $BuildDir + if ($pendingCommands.Count -eq 0) { + return + } + + Push-Location $BuildDir + try { + foreach ($pendingCommand in $pendingCommands) { + Ensure-NinjaRspFiles -BuildDir $BuildDir -CommandLine $pendingCommand + + $commandToRun = $pendingCommand -replace '\s/showIncludes(?=\s|$)', '' + + if ($commandToRun -match '^[^ ]*cmd(?:\.exe)?\s+/C\s+"(?.*)"\s*$') { + & cmd.exe /C $Matches['inner'] + } + else { + & cmd.exe /C $commandToRun + } + + if ($LASTEXITCODE -ne 0) { + throw "Fallback Ninja command failed with exit code ${LASTEXITCODE}: $pendingCommand" + } + } + } + finally { + Pop-Location + } +} + +function Invoke-CMakeBuild { + param( + [Parameter(Mandatory = $true)] + [string]$BuildDir, + + [Parameter(Mandatory = $true)] + [int]$Parallel, + + [Parameter()] + [int]$TimeoutSeconds = 0 + ) + + Remove-NinjaLock -Path $BuildDir + $isNinjaBuild = Test-IsNinjaBuildDirectory -BuildDir $BuildDir + + if ($TimeoutSeconds -le 0) { + if ($isNinjaBuild) { + Invoke-NativeCommand -FilePath 'ninja' -Arguments @( + '-C', $BuildDir, + '-j', $Parallel.ToString() + ) + } + else { + Invoke-NativeCommand -FilePath 'cmake' -Arguments @( + '--build', $BuildDir, + '--parallel', $Parallel.ToString() + ) + } + return + } + + if ($isNinjaBuild) { + $buildToolName = 'Ninja' + $buildResult = Invoke-ProcessWithTimeout -FilePath 'ninja' -Arguments @( + '-C', $BuildDir, + '-j', $Parallel.ToString() + ) -TimeoutSeconds $TimeoutSeconds + } + else { + $buildToolName = 'CMake' + $buildResult = Invoke-ProcessWithTimeout -FilePath 'cmake' -Arguments @( + '--build', $BuildDir, + '--parallel', $Parallel.ToString() + ) -TimeoutSeconds $TimeoutSeconds + } + + if ($buildResult.Completed -and ($buildResult.ExitCode -eq 0)) { + return + } + + if (-not $isNinjaBuild) { + if (-not $buildResult.Completed) { + throw "$buildToolName build timed out after $TimeoutSeconds seconds in $BuildDir" + } + + throw "$buildToolName build failed with exit code $($buildResult.ExitCode) in $BuildDir" + } + + if ($buildResult.Completed) { + throw "$buildToolName build failed with exit code $($buildResult.ExitCode) in $BuildDir" + } + + Write-Warning "$buildToolName build timed out after $TimeoutSeconds seconds in $BuildDir. Replaying pending Ninja commands from PowerShell." + + Remove-NinjaLock -Path $BuildDir + Invoke-NinjaFallbackBuild -BuildDir $BuildDir +} diff --git a/test/shared/regression/testcontrol_weak_defaults.c b/test/shared/regression/testcontrol_weak_defaults.c new file mode 100644 index 000000000..b93a28e5f --- /dev/null +++ b/test/shared/regression/testcontrol_weak_defaults.c @@ -0,0 +1,49 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifdef _MSC_VER +#if defined(_M_IX86) +#define TX_TEST_LINKER_ALIAS(symbol, default_symbol) __pragma(comment(linker, "/alternatename:_" #symbol "=_" #default_symbol)) +#else +#define TX_TEST_LINKER_ALIAS(symbol, default_symbol) __pragma(comment(linker, "/alternatename:" #symbol "=" #default_symbol)) +#endif + +void tx_test_default_abort_all_threads_suspended_on_mutex(void) +{ +} +TX_TEST_LINKER_ALIAS(abort_all_threads_suspended_on_mutex, tx_test_default_abort_all_threads_suspended_on_mutex) + +void tx_test_default_suspend_lowest_priority(void) +{ +} +TX_TEST_LINKER_ALIAS(suspend_lowest_priority, tx_test_default_suspend_lowest_priority) + +void tx_test_default_abort_and_resume_byte_allocating_thread(void) +{ +} +TX_TEST_LINKER_ALIAS(abort_and_resume_byte_allocating_thread, tx_test_default_abort_and_resume_byte_allocating_thread) +#else +__attribute__((weak)) void abort_all_threads_suspended_on_mutex(void) +{ +} + +__attribute__((weak)) void suspend_lowest_priority(void) +{ +} + +__attribute__((weak)) void abort_and_resume_byte_allocating_thread(void) +{ +} +#endif diff --git a/test/smp/cmake/CMakeLists.txt b/test/smp/cmake/CMakeLists.txt index f57d253ce..e2ca8627c 100644 --- a/test/smp/cmake/CMakeLists.txt +++ b/test/smp/cmake/CMakeLists.txt @@ -2,11 +2,19 @@ cmake_minimum_required(VERSION 3.13 FATAL_ERROR) cmake_policy(SET CMP0054 NEW) cmake_policy(SET CMP0057 NEW) +if((DEFINED THREADX_ARCH) AND (THREADX_ARCH STREQUAL "win64")) + set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) +endif() + project(threadx_smp_test LANGUAGES C) +set(CMAKE_C_STANDARD 99) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS OFF) + # Set build configurations -set(BUILD_CONFIGURATIONS default_build_coverage - disable_notify_callbacks_build stack_checking_build stack_checking_rand_fill_build +set(BUILD_CONFIGURATIONS default_build_coverage disable_notify_callbacks_build + stack_checking_build stack_checking_rand_fill_build trace_build) set(CMAKE_CONFIGURATION_TYPES ${BUILD_CONFIGURATIONS} @@ -23,26 +31,31 @@ endif() message(STATUS "Build type: ${CMAKE_BUILD_TYPE}") message(STATUS "Using toolchain file: ${CMAKE_TOOLCHAIN_FILE}.") -set(default_build_coverage -DTX_QUEUE_MESSAGE_MAX_SIZE=32) -set(disable_notify_callbacks_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_DISABLE_NOTIFY_CALLBACKS) -set(stack_checking_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_ENABLE_STACK_CHECKING) -set(stack_checking_rand_fill_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_ENABLE_STACK_CHECKING -DTX_ENABLE_RANDOM_NUMBER_STACK_FILLING) -set(trace_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_ENABLE_EVENT_TRACE) +set(default_build_coverage TX_QUEUE_MESSAGE_MAX_SIZE=32) +set(disable_notify_callbacks_build TX_QUEUE_MESSAGE_MAX_SIZE=32 TX_DISABLE_NOTIFY_CALLBACKS) +set(stack_checking_build TX_QUEUE_MESSAGE_MAX_SIZE=32 TX_ENABLE_STACK_CHECKING) +set(stack_checking_rand_fill_build TX_QUEUE_MESSAGE_MAX_SIZE=32 TX_ENABLE_STACK_CHECKING TX_ENABLE_RANDOM_NUMBER_STACK_FILLING) +set(trace_build TX_QUEUE_MESSAGE_MAX_SIZE=32 TX_ENABLE_EVENT_TRACE) -add_compile_options( - -m32 - -std=c99 - -ggdb - -g3 - -gdwarf-2 - -fdiagnostics-color - # -Werror - -DTX_THREAD_SMP_ONLY_CORE_0_DEFAULT - -DTX_SMP_NOT_POSSIBLE - -DTX_REGRESSION_TEST - -DTEST_STACK_SIZE_PRINTF=4096 +add_compile_definitions( + TX_THREAD_SMP_ONLY_CORE_0_DEFAULT + TX_SMP_NOT_POSSIBLE + TX_REGRESSION_TEST + TEST_STACK_SIZE_PRINTF=4096 ${${CMAKE_BUILD_TYPE}}) -add_link_options(-m32) + +if(MSVC) + add_compile_options(/W3 /Zi) + add_link_options(/DEBUG /INCREMENTAL:NO) +else() + add_compile_options( + -m32 + -ggdb + -g3 + -gdwarf-2 + -fdiagnostics-color) + add_link_options(-m32) +endif() enable_testing() @@ -52,26 +65,31 @@ add_subdirectory(samples) # Coverage if(CMAKE_BUILD_TYPE MATCHES ".*_coverage") - target_compile_options(threadx_smp PRIVATE -fprofile-arcs -ftest-coverage) - target_link_options(threadx_smp PRIVATE -fprofile-arcs -ftest-coverage) + if(NOT MSVC) + target_compile_options(threadx_smp PRIVATE -fprofile-arcs -ftest-coverage) + target_link_options(threadx_smp PRIVATE -fprofile-arcs -ftest-coverage) + endif() endif() -target_compile_options( - threadx_smp - PRIVATE # -Werror - -Wall - -Wextra - -pedantic - -fmessage-length=0 - -fsigned-char - -ffunction-sections - -fdata-sections - -Wunused - -Wuninitialized - -Wmissing-declarations - -Wconversion - -Wpointer-arith - # -Wshadow - -Wlogical-op - -Waggregate-return - -Wfloat-equal) +if(MSVC) + target_compile_options(threadx_smp PRIVATE /W3) +else() + target_compile_options( + threadx_smp + PRIVATE + -Wall + -Wextra + -pedantic + -fmessage-length=0 + -fsigned-char + -ffunction-sections + -fdata-sections + -Wunused + -Wuninitialized + -Wmissing-declarations + -Wconversion + -Wpointer-arith + -Wlogical-op + -Waggregate-return + -Wfloat-equal) +endif() diff --git a/test/smp/cmake/regression/CMakeLists.txt b/test/smp/cmake/regression/CMakeLists.txt index f7226c216..7d258e50e 100644 --- a/test/smp/cmake/regression/CMakeLists.txt +++ b/test/smp/cmake/regression/CMakeLists.txt @@ -4,6 +4,16 @@ cmake_policy(SET CMP0057 NEW) project(regression_test LANGUAGES C) set(SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/../../regression) +set(REPO_ROOT ${CMAKE_CURRENT_LIST_DIR}/../../../..) +set(PORT_LOW_LEVEL_SOURCE ${REPO_ROOT}/ports_smp/${THREADX_ARCH}/${THREADX_TOOLCHAIN}/src/tx_initialize_low_level.c) +set(GENERATED_LOW_LEVEL_SOURCE ${CMAKE_CURRENT_BINARY_DIR}/tx_initialize_low_level.c) +set(TESTCONTROL_WEAK_DEFAULTS_SOURCE ${REPO_ROOT}/test/shared/regression/testcontrol_weak_defaults.c) + +include_directories(${REPO_ROOT}/test/tx/regression) + +if(NOT EXISTS ${PORT_LOW_LEVEL_SOURCE}) + message(FATAL_ERROR "Unable to locate tx_initialize_low_level.c for ${THREADX_ARCH}/${THREADX_TOOLCHAIN}") +endif() set(regression_test_cases ${SOURCE_DIR}/threadx_block_memory_basic_test.c @@ -117,18 +127,32 @@ set(regression_test_cases ${SOURCE_DIR}/threadx_initialize_kernel_setup_test.c) add_custom_command( - OUTPUT ${SOURCE_DIR}/tx_initialize_low_level.c - COMMAND bash ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.sh + OUTPUT ${GENERATED_LOW_LEVEL_SOURCE} + COMMAND ${CMAKE_COMMAND} + -DSOURCE_FILE=${PORT_LOW_LEVEL_SOURCE} + -DOUTPUT_FILE=${GENERATED_LOW_LEVEL_SOURCE} + -P ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.cmake + DEPENDS ${PORT_LOW_LEVEL_SOURCE} ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.cmake COMMENT "Generating tx_initialize_low_level.c for test") -add_library(test_utility ${SOURCE_DIR}/tx_initialize_low_level.c - ${SOURCE_DIR}/testcontrol.c) -target_link_libraries(test_utility PUBLIC azrtos::threadx_smp) -target_compile_definitions(test_utility PUBLIC CTEST BATCH_TEST) +add_library(test_utility OBJECT ${GENERATED_LOW_LEVEL_SOURCE} + ${SOURCE_DIR}/testcontrol.c + ${TESTCONTROL_WEAK_DEFAULTS_SOURCE}) +target_link_libraries(test_utility PRIVATE azrtos::threadx_smp) +target_compile_definitions(test_utility PRIVATE CTEST BATCH_TEST + TEST_STACK_SIZE_PRINTF=4096) foreach(test_case ${regression_test_cases}) get_filename_component(test_name ${test_case} NAME_WE) - add_executable(${test_name} ${test_case}) - target_link_libraries(${test_name} PRIVATE test_utility) + + if(test_name STREQUAL "threadx_initialize_kernel_setup_test") + add_executable(${test_name} ${test_case}) + else() + add_executable(${test_name} ${test_case} $) + target_compile_definitions(${test_name} PRIVATE CTEST BATCH_TEST + TEST_STACK_SIZE_PRINTF=4096) + endif() + + target_link_libraries(${test_name} PRIVATE azrtos::threadx_smp) add_test(${CMAKE_BUILD_TYPE}::${test_name} ${test_name}) endforeach() diff --git a/test/smp/cmake/regression/generate_test_file.cmake b/test/smp/cmake/regression/generate_test_file.cmake new file mode 100644 index 000000000..77cccaa59 --- /dev/null +++ b/test/smp/cmake/regression/generate_test_file.cmake @@ -0,0 +1,44 @@ +if(NOT DEFINED SOURCE_FILE) + message(FATAL_ERROR "SOURCE_FILE is required") +endif() + +if(NOT DEFINED OUTPUT_FILE) + message(FATAL_ERROR "OUTPUT_FILE is required") +endif() + +file(STRINGS "${SOURCE_FILE}" FILE_LINES) + +set(UPDATED_FILE_CONTENTS "") +set(DISPATCH_DECLARATION "VOID test_interrupt_dispatch(VOID);") +set(DISPATCH_CALL "test_interrupt_dispatch();") +set(DECLARATION_INSERTED FALSE) +set(CALL_INSERTED FALSE) + +foreach(FILE_LINE IN LISTS FILE_LINES) + if((NOT DECLARATION_INSERTED) AND + ((FILE_LINE MATCHES "^void[ \t]+\\*_tx_linux_timer_interrupt\\(void \\*p\\);[ \t]*$") + OR + (FILE_LINE MATCHES "^VOID[ \t]+_tx_win32_timer_interrupt\\(VOID\\);[ \t]*$") + OR + (FILE_LINE MATCHES "^VOID CALLBACK[ \t]+_tx_win32_timer_interrupt\\(UINT wTimerID, UINT msg, DWORD_PTR dwUser, DWORD_PTR dw1, DWORD_PTR dw2\\);[ \t]*$"))) + string(APPEND UPDATED_FILE_CONTENTS "${FILE_LINE}\n${DISPATCH_DECLARATION}\n") + set(DECLARATION_INSERTED TRUE) + elseif((NOT CALL_INSERTED) AND (FILE_LINE MATCHES "^([ \t]*)_tx_timer_interrupt\\(\\);[ \t]*$")) + string(APPEND UPDATED_FILE_CONTENTS "${CMAKE_MATCH_1}${DISPATCH_CALL}\n${FILE_LINE}\n") + set(CALL_INSERTED TRUE) + else() + string(APPEND UPDATED_FILE_CONTENTS "${FILE_LINE}\n") + endif() +endforeach() + +if(NOT CALL_INSERTED) + message(FATAL_ERROR "Unable to insert test interrupt dispatcher call into ${SOURCE_FILE}") +endif() + +if(NOT DECLARATION_INSERTED) + message(FATAL_ERROR "Unable to insert test interrupt dispatcher declaration into ${SOURCE_FILE}") +endif() + +get_filename_component(OUTPUT_DIRECTORY "${OUTPUT_FILE}" DIRECTORY) +file(MAKE_DIRECTORY "${OUTPUT_DIRECTORY}") +file(WRITE "${OUTPUT_FILE}" "${UPDATED_FILE_CONTENTS}") diff --git a/test/smp/cmake/threadx_smp/CMakeLists.txt b/test/smp/cmake/threadx_smp/CMakeLists.txt index f65962537..568fece41 100644 --- a/test/smp/cmake/threadx_smp/CMakeLists.txt +++ b/test/smp/cmake/threadx_smp/CMakeLists.txt @@ -1,11 +1,5 @@ cmake_minimum_required(VERSION 3.13 FATAL_ERROR) -# Set up the project -project(threadx_smp - VERSION 6.0.0 - LANGUAGES C ASM -) - if(NOT DEFINED THREADX_ARCH) message(FATAL_ERROR "Error: THREADX_ARCH not defined") endif() @@ -13,6 +7,17 @@ if(NOT DEFINED THREADX_TOOLCHAIN) message(FATAL_ERROR "Error: THREADX_TOOLCHAIN not defined") endif() +set(THREADX_SMP_PROJECT_LANGUAGES C) +if(NOT ((THREADX_ARCH STREQUAL "win64") AND (THREADX_TOOLCHAIN STREQUAL "vs_2022"))) + list(APPEND THREADX_SMP_PROJECT_LANGUAGES ASM) +endif() + +# Set up the project +project(threadx_smp + VERSION 6.0.0 + LANGUAGES ${THREADX_SMP_PROJECT_LANGUAGES} +) + set(PROJECT_DIR ${CMAKE_CURRENT_LIST_DIR}/../../../..) # Define our target library and an alias for consumers @@ -57,4 +62,4 @@ set(CPACK_SOURCE_IGNORE_FILES ".*~$" ) set(CPACK_VERBATIM_VARIABLES YES) -include(CPack) \ No newline at end of file +include(CPack) diff --git a/test/smp/cmake/threadx_smp/ports_smp/win64/vs_2022/CMakeLists.txt b/test/smp/cmake/threadx_smp/ports_smp/win64/vs_2022/CMakeLists.txt new file mode 100644 index 000000000..6b219bb21 --- /dev/null +++ b/test/smp/cmake/threadx_smp/ports_smp/win64/vs_2022/CMakeLists.txt @@ -0,0 +1,29 @@ +set(CURRENT_DIR ${PROJECT_DIR}/ports_smp/win64/vs_2022) +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CURRENT_DIR}/src/tx_initialize_low_level.c + ${CURRENT_DIR}/src/tx_thread_context_restore.c + ${CURRENT_DIR}/src/tx_thread_context_save.c + ${CURRENT_DIR}/src/tx_thread_interrupt_control.c + ${CURRENT_DIR}/src/tx_thread_schedule.c + ${CURRENT_DIR}/src/tx_thread_smp_core_get.c + ${CURRENT_DIR}/src/tx_thread_smp_core_preempt.c + ${CURRENT_DIR}/src/tx_thread_smp_current_state_get.c + ${CURRENT_DIR}/src/tx_thread_smp_current_thread_get.c + ${CURRENT_DIR}/src/tx_thread_smp_initialize_wait.c + ${CURRENT_DIR}/src/tx_thread_smp_low_level_initialize.c + ${CURRENT_DIR}/src/tx_thread_smp_protect.c + ${CURRENT_DIR}/src/tx_thread_smp_time_get.c + ${CURRENT_DIR}/src/tx_thread_smp_unprotect.c + ${CURRENT_DIR}/src/tx_thread_stack_build.c + ${CURRENT_DIR}/src/tx_thread_system_return.c + ${CURRENT_DIR}/src/tx_timer_interrupt.c + + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CURRENT_DIR}/inc +) diff --git a/test/smp/regression/testcontrol.c b/test/smp/regression/testcontrol.c index dacaf70e8..07aa9a3f0 100644 --- a/test/smp/regression/testcontrol.c +++ b/test/smp/regression/testcontrol.c @@ -1,4 +1,5 @@ /* This is the test control routine of the ThreadX kernel. All tests are dispatched from this routine. */ +// Some portions generated by Codex (gpt 5.5). #define TX_THREAD_SMP_SOURCE_CODE @@ -1355,6 +1356,10 @@ UINT i; /* Clear the ISR dispatch. */ test_isr_dispatch = TX_NULL; +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_reset(); +#endif + /* Dispatch the test. */ (test_control_tests[i++].test_entry)(test_free_memory_ptr); @@ -1435,6 +1440,10 @@ UINT old_posture = TX_INT_ENABLE; test_control_system_errors++; } +#ifdef TX_WIN32_PROFILE_ENABLE + _tx_win32_profile_report("smp_test"); +#endif + /* Resume the control thread to fully exit the test. */ tx_thread_resume(&test_control_thread); } @@ -1447,6 +1456,51 @@ TX_MUTEX *mutex_ptr; TX_THREAD *thread_ptr; + /* Delete all threads, except for timer thread, and test control thread. + This ensures application-owned objects are no longer referenced before + the object cleanup loops below attempt to delete them. */ + while (_tx_thread_created_ptr) + { + + /* Setup working pointer. */ + thread_ptr = _tx_thread_created_ptr; + + +#ifdef TX_TIMER_PROCESS_IN_ISR + + /* Determine if there are more threads to delete. */ + if (_tx_thread_created_count == 1) + break; + + /* Determine if this thread is the test control thread. */ + if (thread_ptr == &test_control_thread) + { + + /* Move to the next thread pointer. */ + thread_ptr = thread_ptr -> tx_thread_created_next; + } +#else + + /* Determine if there are more threads to delete. */ + if (_tx_thread_created_count == 2) + break; + + /* Move to the thread not protected. */ + while ((thread_ptr == &_tx_timer_thread) || (thread_ptr == &test_control_thread)) + { + + /* Yes, move to the next thread. */ + thread_ptr = thread_ptr -> tx_thread_created_next; + } +#endif + + /* First terminate the thread to ensure it is ready for deletion. */ + tx_thread_terminate(thread_ptr); + + /* Delete the thread. */ + tx_thread_delete(thread_ptr); + } + /* Delete all queues. */ while(_tx_queue_created_ptr) { @@ -1524,49 +1578,6 @@ TX_THREAD *thread_ptr; tx_mutex_delete(mutex_ptr); } - /* Delete all threads, except for timer thread, and test control thread. */ - while (_tx_thread_created_ptr) - { - - /* Setup working pointer. */ - thread_ptr = _tx_thread_created_ptr; - - -#ifdef TX_TIMER_PROCESS_IN_ISR - - /* Determine if there are more threads to delete. */ - if (_tx_thread_created_count == 1) - break; - - /* Determine if this thread is the test control thread. */ - if (thread_ptr == &test_control_thread) - { - - /* Move to the next thread pointer. */ - thread_ptr = thread_ptr -> tx_thread_created_next; - } -#else - - /* Determine if there are more threads to delete. */ - if (_tx_thread_created_count == 2) - break; - - /* Move to the thread not protected. */ - while ((thread_ptr == &_tx_timer_thread) || (thread_ptr == &test_control_thread)) - { - - /* Yes, move to the next thread. */ - thread_ptr = thread_ptr -> tx_thread_created_next; - } -#endif - - /* First terminate the thread to ensure it is ready for deletion. */ - tx_thread_terminate(thread_ptr); - - /* Delete the thread. */ - tx_thread_delete(thread_ptr); - } - /* At this point, only the test control thread and the system timer thread and/or mutex should still be in the system. */ } @@ -1609,15 +1620,3 @@ void test_exit_notify(TX_THREAD *thread_ptr, UINT type) /* Clear the suspending flag to short-circuit the suspension. */ thread_ptr -> tx_thread_suspending = TX_FALSE; } - -__attribute__((weak)) void abort_all_threads_suspended_on_mutex(void) -{ -} - -__attribute__((weak)) void suspend_lowest_priority(void) -{ -} - -__attribute__((weak)) void abort_and_resume_byte_allocating_thread(void) -{ -} diff --git a/test/smp/regression/threadx_block_memory_basic_test.c b/test/smp/regression/threadx_block_memory_basic_test.c index 12e301d1a..117872c3f 100644 --- a/test/smp/regression/threadx_block_memory_basic_test.c +++ b/test/smp/regression/threadx_block_memory_basic_test.c @@ -3,6 +3,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" typedef struct BLOCK_MEMORY_TEST_STRUCT { @@ -86,7 +87,7 @@ CHAR *pointer; /* Attempt to create a block pool from a timer. */ pointer = (CHAR *) 0x30000; - status = tx_block_pool_create(&pool_3, "pool 3", 100, pointer, 320); + status = tx_block_pool_create(&pool_3, "pool 3", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); /* Check status. */ if (status != TX_CALLER_ERROR) @@ -146,7 +147,7 @@ UINT status; } /* Attempt to create a block pool from an ISR. */ - status = tx_block_pool_create(&pool_3, "pool 3", 100, (void *) 0x100000, 320); + status = tx_block_pool_create(&pool_3, "pool 3", 100, (void *) 0x100000, TX_TEST_BLOCK_POOL_BYTES(100, 3)); /* Check status. */ if (status != TX_CALLER_ERROR) @@ -217,8 +218,8 @@ CHAR *pointer; } /* Create block pools 0 and 1. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -228,8 +229,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -241,7 +242,7 @@ CHAR *pointer; /* Check the no-blocks path. */ status = _tx_block_pool_create(&pool_2, "pool 2", 100, pointer, 50); - pointer = pointer + 320; + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SIZE_ERROR) @@ -265,7 +266,7 @@ CHAR *pointer_2; CHAR *pointer_3; CHAR *pointer_4; INT i; -unsigned long fake_block[20]; +TX_TEST_POINTER_WORD fake_block[20]; /* Inform user. */ @@ -316,7 +317,7 @@ unsigned long fake_block[20]; /* Try to release a block that points to a non-pool. */ fake_block[0] = 0; - fake_block[1] = (unsigned long) &fake_block[0]; + TX_TEST_STORE_POINTER(fake_block[1], &fake_block[0]); status = tx_block_release(&fake_block[2]); /* Check status. */ @@ -519,7 +520,7 @@ unsigned long fake_block[20]; { /* Block memory error. */ - printf("ERROR #20\n"); + printf("ERROR #20 (%lu %lu %lu)\n", error, timer_executed, isr_executed); test_control_return(1); } diff --git a/test/smp/regression/threadx_block_memory_error_detection_test.c b/test/smp/regression/threadx_block_memory_error_detection_test.c index 7b7f2f610..e9869b1eb 100644 --- a/test/smp/regression/threadx_block_memory_error_detection_test.c +++ b/test/smp/regression/threadx_block_memory_error_detection_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -49,18 +50,18 @@ INT status; pointer = pointer + TEST_STACK_SIZE_PRINTF; /* Create block pool 0. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); #ifndef TX_DISABLE_ERROR_CHECKING /* skip this test and pretend it passed */ /* Create block pool again to get pool_ptr error. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); if (status != TX_POOL_ERROR) return; /* Create block pool with NULL pointer. */ - status = tx_block_pool_create(TX_NULL, "pool 0", 100, pointer, 320); + status = tx_block_pool_create(TX_NULL, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); if (status != TX_POOL_ERROR) { @@ -69,7 +70,7 @@ INT status; } /* Create block pool pointer if NULL start. */ - status = tx_block_pool_create(&pool_1, "pool 0", 100, NULL, 320); + status = tx_block_pool_create(&pool_1, "pool 0", 100, NULL, TX_TEST_BLOCK_POOL_BYTES(100, 3)); if (status != TX_PTR_ERROR) { @@ -128,11 +129,11 @@ INT i; #ifndef TX_DISABLE_ERROR_CHECKING /* skip this test and pretend it passed */ - status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Attempt to create a pool with an invalid size. */ - status = _txe_block_pool_create(&pool_2, "pool 2", 100, pointer, 320, 777777); + status = _txe_block_pool_create(&pool_2, "pool 2", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3), 777777); if (status != TX_POOL_ERROR) { @@ -384,4 +385,3 @@ INT i; printf("SUCCESS!\n"); test_control_return(0); } - diff --git a/test/smp/regression/threadx_block_memory_suspension_test.c b/test/smp/regression/threadx_block_memory_suspension_test.c index da14f454e..9ce8939c5 100644 --- a/test/smp/regression/threadx_block_memory_suspension_test.c +++ b/test/smp/regression/threadx_block_memory_suspension_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -83,8 +84,8 @@ CHAR *pointer; } /* Create block pool. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -308,4 +309,3 @@ CHAR *pointer_1; } } - diff --git a/test/smp/regression/threadx_block_memory_suspension_timeout_test.c b/test/smp/regression/threadx_block_memory_suspension_timeout_test.c index dc460662d..57be8aaa3 100644 --- a/test/smp/regression/threadx_block_memory_suspension_timeout_test.c +++ b/test/smp/regression/threadx_block_memory_suspension_timeout_test.c @@ -1,7 +1,10 @@ /* This test is designed to test timeouts on suspension on memory block pools. */ +// Some portions generated by Codex (gpt 5.4). + #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -84,8 +87,8 @@ CHAR *pointer; } /* Create block pool. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -135,15 +138,15 @@ CHAR *pointer_3; /* Set all the memory of the blocks. */ TX_MEMSET(pointer_3, (CHAR) 0xEF, 100); - /* Sleep for 64 ticks to allow the other thread 6 timeouts on the block - pool. */ + /* Sleep long enough to allow the other threads to complete their expected + timeout cycles on the block pool. */ tx_thread_sleep(64); /* Incrment the run counter. */ thread_0_counter++; /* Check the counter of the other thread. */ - if ((thread_1_counter != 6) || (thread_2_counter != 3)) + if ((thread_1_counter != 6UL) || (thread_2_counter != 3UL)) { /* Block memory error. */ @@ -209,4 +212,3 @@ CHAR *pointer_1; thread_2_counter++; } } - diff --git a/test/smp/regression/threadx_block_memory_thread_terminate_test.c b/test/smp/regression/threadx_block_memory_thread_terminate_test.c index 6064891df..291ab0187 100644 --- a/test/smp/regression/threadx_block_memory_thread_terminate_test.c +++ b/test/smp/regression/threadx_block_memory_thread_terminate_test.c @@ -3,6 +3,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -69,8 +70,8 @@ CHAR *pointer; } /* Create block pool. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); - pointer = pointer + 320; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -182,4 +183,3 @@ CHAR *pointer_1; thread_1_counter++; } } - diff --git a/test/smp/regression/threadx_byte_memory_basic_test.c b/test/smp/regression/threadx_byte_memory_basic_test.c index 36f413317..d609712c1 100644 --- a/test/smp/regression/threadx_byte_memory_basic_test.c +++ b/test/smp/regression/threadx_byte_memory_basic_test.c @@ -3,6 +3,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" typedef struct BYTE_MEMORY_TEST_STRUCT { @@ -91,7 +92,7 @@ CHAR *pointer; /* Attempt to create a byte pool from a timer. */ pointer = (CHAR *) 0x30000; - status = tx_byte_pool_create(&pool_2, "pool 2", pointer, 108); + status = tx_byte_pool_create(&pool_2, "pool 2", pointer, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_CALLER_ERROR) @@ -103,7 +104,7 @@ CHAR *pointer; /* Attempt to create a byte pool with an invalid size. */ status = _txe_byte_pool_create(&pool_3, "pool 3", pointer, - 108, (sizeof(TX_BYTE_POOL)+1)); + TX_TEST_BYTE_POOL_BYTES(108), (sizeof(TX_BYTE_POOL)+1)); /* Check status. */ if (status != TX_POOL_ERROR) @@ -186,7 +187,7 @@ UINT status; /* Attempt to create a byte pool from an ISR. */ - status = tx_byte_pool_create(&pool_2, "pool 0", (void *) 0x100000, 108); + status = tx_byte_pool_create(&pool_2, "pool 0", (void *) 0x100000, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_CALLER_ERROR) @@ -256,8 +257,8 @@ CHAR *pointer; } /* Create byte pools 0 and 1. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_CAPACITY_BYTES(24, 3)); + pointer = pointer + TX_TEST_BYTE_POOL_CAPACITY_BYTES(24, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -267,8 +268,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_byte_pool_create(&pool_1, "pool 1", pointer, 200); - pointer = pointer + 200; + status = tx_byte_pool_create(&pool_1, "pool 1", pointer, TX_TEST_BYTE_POOL_BYTES(200)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(200); /* Check status. */ if (status != TX_SUCCESS) @@ -279,9 +280,9 @@ CHAR *pointer; } /* Test for search pointer issue on wrapped seach with prior block to search pointer merged. */ - status = tx_byte_pool_create(&pool_4, "pool 4", pointer, 300); + status = tx_byte_pool_create(&pool_4, "pool 4", pointer, TX_TEST_BYTE_POOL_CAPACITY_BYTES(84, 3)); pool_4_memory = pointer; - pointer = pointer + 300; + pointer = pointer + TX_TEST_BYTE_POOL_CAPACITY_BYTES(84, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -353,7 +354,7 @@ CHAR *pointer_2; CHAR *pointer_3; CHAR *pointer_4; INT i; -ULONG array[20]; +TX_TEST_POINTER_WORD array[20]; UCHAR *save_search; @@ -394,7 +395,7 @@ UCHAR *save_search; /* Try to create a NULL pool. */ pointer_1 = (CHAR *) 0x30000; - status = tx_byte_pool_create(TX_NULL, "pool 0", pointer_1, 108); + status = tx_byte_pool_create(TX_NULL, "pool 0", pointer_1, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_POOL_ERROR) @@ -406,7 +407,7 @@ UCHAR *save_search; } /* Try to create the same pool. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer_1, 108); + status = tx_byte_pool_create(&pool_0, "pool 0", pointer_1, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_POOL_ERROR) @@ -418,7 +419,7 @@ UCHAR *save_search; } /* Try to create a pool with a NULL start address. */ - status = tx_byte_pool_create(&pool_2, "pool 2", TX_NULL, 108); + status = tx_byte_pool_create(&pool_2, "pool 2", TX_NULL, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_PTR_ERROR) @@ -626,7 +627,7 @@ UCHAR *save_search; /* Test another bad block release.... pool pointer is not a valid pool! */ array[0] = 0; - array[1] = (ULONG) &array[3]; + TX_TEST_STORE_POINTER(array[1], &array[3]); array[2] = 0; array[3] = 0; status = _tx_byte_release(&array[2]); @@ -865,7 +866,7 @@ UCHAR *save_search; } /* Move the search pointer to the third block to exercise that code in the byte search algorithm. */ - pool_0.tx_byte_pool_search = (UCHAR *) pointer_3-8; + pool_0.tx_byte_pool_search = (UCHAR *) pointer_3 - TX_TEST_BYTE_POOL_SEARCH_OFFSET; /* Now allocate the block again. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_2, 24, TX_NO_WAIT); @@ -885,7 +886,7 @@ UCHAR *save_search; status += tx_byte_release(pointer_1); /* Move the search pointer to the third block to exercise that code in the byte search algorithm. */ - pool_0.tx_byte_pool_search = (UCHAR *) pointer_3-8; + pool_0.tx_byte_pool_search = (UCHAR *) pointer_3 - TX_TEST_BYTE_POOL_SEARCH_OFFSET; /* Allocate a large block to force the search pointer update. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_3, 88, TX_NO_WAIT); @@ -961,7 +962,7 @@ UCHAR *save_search; } /* Create pool 4. */ - status = tx_byte_pool_create(&pool_4, "pool 4", pool_4_memory, 300); + status = tx_byte_pool_create(&pool_4, "pool 4", pool_4_memory, TX_TEST_BYTE_POOL_CAPACITY_BYTES(84, 3)); /* Check status. */ if (status != TX_SUCCESS) @@ -1061,4 +1062,3 @@ UCHAR *save_search; printf("SUCCESS!\n"); test_control_return(0); } - diff --git a/test/smp/regression/threadx_byte_memory_information_test.c b/test/smp/regression/threadx_byte_memory_information_test.c index 8a6192694..df607acb4 100644 --- a/test/smp/regression/threadx_byte_memory_information_test.c +++ b/test/smp/regression/threadx_byte_memory_information_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" #include "tx_byte_pool.h" @@ -193,7 +194,7 @@ CHAR *pointer; } /* Create the byte_pool with one byte. */ - status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, 100); + status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(100)); pointer = pointer + 100; /* Check for status. */ diff --git a/test/smp/regression/threadx_byte_memory_prioritize_test.c b/test/smp/regression/threadx_byte_memory_prioritize_test.c index 294071350..9160db91a 100644 --- a/test/smp/regression/threadx_byte_memory_prioritize_test.c +++ b/test/smp/regression/threadx_byte_memory_prioritize_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" /* Define the ISR dispatch. */ @@ -197,7 +198,7 @@ CHAR *pointer; } /* Create the byte_pool with one byte. */ - status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, 100); + status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(100)); pointer = pointer + 100; /* Check for status. */ @@ -495,4 +496,3 @@ VOID *pointer; thread_6_counter++; } } - diff --git a/test/smp/regression/threadx_byte_memory_suspension_test.c b/test/smp/regression/threadx_byte_memory_suspension_test.c index ba159894b..2736195dc 100644 --- a/test/smp/regression/threadx_byte_memory_suspension_test.c +++ b/test/smp/regression/threadx_byte_memory_suspension_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -121,8 +122,8 @@ CHAR *pointer; } /* Create byte pool 0. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(108)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(108); /* Check status. */ if (status != TX_SUCCESS) diff --git a/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c b/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c index 5e94df97a..68f18c74d 100644 --- a/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c +++ b/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c @@ -1,7 +1,10 @@ /* This test is designed to test suspension timeout on a memory byte pool. */ +// Some portions generated by Codex (gpt 5.4). + #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -85,8 +88,8 @@ CHAR *pointer; } /* Create byte pool 0. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(108)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(108); /* Check status. */ if (status != TX_SUCCESS) @@ -126,12 +129,12 @@ CHAR *pointer; test_control_return(1); } - /* Sleep to allow the other thread to suspend and timeout on the memory - pool once. */ + /* Sleep long enough to allow the other threads to complete their expected + timeout cycles on the byte pool. */ tx_thread_sleep(64); /* Check the counter of the other thread. */ - if ((thread_1_counter != 6) || (thread_2_counter != 3)) + if ((thread_1_counter != 6UL) || (thread_2_counter != 3UL)) { /* Block memory error. */ diff --git a/test/smp/regression/threadx_byte_memory_thread_contention_test.c b/test/smp/regression/threadx_byte_memory_thread_contention_test.c index 899ed2691..cd379e54c 100644 --- a/test/smp/regression/threadx_byte_memory_thread_contention_test.c +++ b/test/smp/regression/threadx_byte_memory_thread_contention_test.c @@ -3,6 +3,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -89,8 +90,8 @@ CHAR *pointer; } /* Create byte pool 0. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(108)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(108); /* Save off the intial pool size. */ initial_pool_size = pool_0.tx_byte_pool_available; @@ -126,7 +127,6 @@ CHAR *pointer; while(1) { - /* Allocate memory from the pool. This size will cause merge activity because the search pointer will sit in this large block about half the time. */ @@ -195,10 +195,8 @@ static void thread_1_entry(ULONG thread_input) UINT status; CHAR *pointer; - while(test_done == TX_FALSE) { - /* Allocate memory from the pool. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 30, TX_WAIT_FOREVER); @@ -228,10 +226,8 @@ static void thread_2_entry(ULONG thread_input) UINT status; CHAR *pointer; - while(test_done == TX_FALSE) { - /* Allocate memory from the pool. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 12, TX_WAIT_FOREVER); diff --git a/test/smp/regression/threadx_byte_memory_thread_terminate_test.c b/test/smp/regression/threadx_byte_memory_thread_terminate_test.c index 4805ba571..35a4615aa 100644 --- a/test/smp/regression/threadx_byte_memory_thread_terminate_test.c +++ b/test/smp/regression/threadx_byte_memory_thread_terminate_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -68,8 +69,8 @@ CHAR *pointer; } /* Create byte pools 0 and 1. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(108)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(108); /* Check status. */ if (status != TX_SUCCESS) @@ -174,4 +175,3 @@ CHAR *pointer; thread_1_counter++; } } - diff --git a/test/smp/regression/threadx_event_flag_isr_set_clear_test.c b/test/smp/regression/threadx_event_flag_isr_set_clear_test.c index b1420d767..54b18a2e6 100644 --- a/test/smp/regression/threadx_event_flag_isr_set_clear_test.c +++ b/test/smp/regression/threadx_event_flag_isr_set_clear_test.c @@ -240,14 +240,12 @@ ULONG actual; /* Inform user. */ printf("Running Event Flag Set/Clear from ISR Test.......................... "); - /* Setup the test ISR. */ test_isr_dispatch = test_isr; /* Loop to exploit the probability window inside tx_event_flags_set call. */ while (condition_count < 40) { - /* Suspend on the event_flags that is going to be set via the ISR. */ status = tx_event_flags_get(&event_flags_0, 2, TX_OR_CLEAR, &actual, 4); @@ -354,5 +352,3 @@ static void timer_0_entry(ULONG input) { timer_0_counter++; } - - diff --git a/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c b/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c index 95d3b5ab9..8706b8bc4 100644 --- a/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c +++ b/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c @@ -32,7 +32,6 @@ static unsigned long condition_count = 0; static TX_EVENT_FLAGS_GROUP event_flags_0; - /* Define thread prototypes. */ static void thread_0_entry(ULONG thread_input); diff --git a/test/smp/regression/threadx_initialize_kernel_setup_test.c b/test/smp/regression/threadx_initialize_kernel_setup_test.c index a1172ded9..8c2b11596 100644 --- a/test/smp/regression/threadx_initialize_kernel_setup_test.c +++ b/test/smp/regression/threadx_initialize_kernel_setup_test.c @@ -33,18 +33,6 @@ UINT mutex_priority_change_extension_selection; UINT priority_change_extension_selection; -__attribute__((weak)) void abort_all_threads_suspended_on_mutex(void) -{ -} - -__attribute__((weak)) void suspend_lowest_priority(void) -{ -} - -__attribute__((weak)) void abort_and_resume_byte_allocating_thread(void) -{ -} - void main() { @@ -80,4 +68,4 @@ void delete_timer_thread(void) _tx_thread_delete(&_tx_timer_thread); } -#endif \ No newline at end of file +#endif diff --git a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c index db174ef2c..ce2315f8a 100644 --- a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c +++ b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c @@ -1,7 +1,9 @@ /* Define the ThreadX SMP random resume/suspend/exclude/pt test. */ +// Some portions generated by Codex (gpt 5.4). #include #include "tx_api.h" +#include "tx_thread.h" //#define MAX_PASSES 50000000 //#define MAX_PASSES 50000 diff --git a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c index 1a02cf190..379e1fdfe 100644 --- a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c +++ b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c @@ -2370,4 +2370,3 @@ TX_THREAD *thread_ptr; tx_thread_suspend(thread_ptr); } } - diff --git a/test/smp/regression/threadx_smp_random_resume_suspend_test.c b/test/smp/regression/threadx_smp_random_resume_suspend_test.c index 8098dfe77..8550bdf24 100644 --- a/test/smp/regression/threadx_smp_random_resume_suspend_test.c +++ b/test/smp/regression/threadx_smp_random_resume_suspend_test.c @@ -2325,5 +2325,3 @@ static void thread_entry(ULONG id) tx_thread_suspend(_smp_randomized_source_array[id]); } } - - diff --git a/test/smp/regression/threadx_smp_relinquish_test.c b/test/smp/regression/threadx_smp_relinquish_test.c index dddb13c27..96b2864d6 100644 --- a/test/smp/regression/threadx_smp_relinquish_test.c +++ b/test/smp/regression/threadx_smp_relinquish_test.c @@ -362,4 +362,3 @@ static void thread_31h_entry(ULONG thread_input) thread_31h_counter++; } } - diff --git a/test/smp/regression/threadx_smp_time_slice_test.c b/test/smp/regression/threadx_smp_time_slice_test.c index fe97590ac..b6cd67eae 100644 --- a/test/smp/regression/threadx_smp_time_slice_test.c +++ b/test/smp/regression/threadx_smp_time_slice_test.c @@ -1,5 +1,7 @@ /* Define the ThreadX SMP time-slice test. */ +// Some portions generated by Codex (gpt 5.4). + #include #include "tx_api.h" @@ -243,7 +245,7 @@ UINT status; status += tx_thread_resume(&thread_31g); status += tx_thread_resume(&thread_31h); - /* Now sleep for 20 ticks to let see if all the threads execute. */ + /* Sleep long enough to see if all the threads execute. */ tx_thread_sleep(20); /* Now check and make sure all the threads ran. */ @@ -358,4 +360,3 @@ static void thread_31h_entry(ULONG thread_input) thread_31h_counter++; } } - diff --git a/test/smp/regression/threadx_thread_basic_execution_test.c b/test/smp/regression/threadx_thread_basic_execution_test.c index f10ce2e9f..42ded1842 100644 --- a/test/smp/regression/threadx_thread_basic_execution_test.c +++ b/test/smp/regression/threadx_thread_basic_execution_test.c @@ -11,6 +11,7 @@ #include "tx_queue.h" #include "tx_semaphore.h" #include "tx_thread.h" +#include "tx_timer.h" typedef struct THREAD_MEMORY_TEST_STRUCT @@ -33,6 +34,7 @@ static THREAD_MEMORY_TEST thread_memory; /* Define the ISR dispatch. */ extern VOID (*test_isr_dispatch)(void); +extern TX_TIMER_INTERNAL *_tx_timer_expired_timer_ptr; static unsigned long thread_0_counter = 0; @@ -314,7 +316,22 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_suspending = TX_TRUE; test_thread.tx_thread_delayed_suspend = TX_TRUE; +#if defined(_WIN64) + { + TX_TIMER_INTERNAL timeout_timer; + TX_TIMER_INTERNAL *saved_expired_timer_ptr; + + + TX_MEMSET(&timeout_timer, 0, sizeof(TX_TIMER_INTERNAL)); + saved_expired_timer_ptr = _tx_timer_expired_timer_ptr; + _tx_timer_expired_timer_ptr = &timeout_timer; + timeout_timer.tx_timer_internal_extension_ptr = (VOID *) &test_thread; + _tx_thread_timeout(0); + _tx_timer_expired_timer_ptr = saved_expired_timer_ptr; + } +#else _tx_thread_timeout((ULONG) &test_thread); +#endif /* Setup test thread to make sure _tx_thread_terminate can handle a NULL mutex release function pointer. */ temp_mutex_release = _tx_thread_mutex_release; diff --git a/test/smp/regression/threadx_thread_delayed_suspension_test.c b/test/smp/regression/threadx_thread_delayed_suspension_test.c index e5d1e0912..72c872ddd 100644 --- a/test/smp/regression/threadx_thread_delayed_suspension_test.c +++ b/test/smp/regression/threadx_thread_delayed_suspension_test.c @@ -227,7 +227,6 @@ UINT status; /* Inform user. */ printf("Running Thread Delayed Suspension Clearing Test..................... "); - /* Relinquish to the other thread. */ tx_thread_relinquish(); @@ -270,7 +269,6 @@ UINT status; /* Wait until we see the delayed suspension set flag. */ while(delayed_suspend_set == 0) { - /* Abort the suspension for thread 2. */ tx_thread_wait_abort(&thread_2); diff --git a/test/smp/regression/threadx_thread_multiple_sleep_test.c b/test/smp/regression/threadx_thread_multiple_sleep_test.c index f2ae3b998..76443afa3 100644 --- a/test/smp/regression/threadx_thread_multiple_sleep_test.c +++ b/test/smp/regression/threadx_thread_multiple_sleep_test.c @@ -1,5 +1,7 @@ /* This test is designed to test multiple threads sleeping for 33 ticks. */ +// Some portions generated by Codex (gpt 5.4). + #include #include "tx_api.h" @@ -154,14 +156,14 @@ static void thread_2_entry(ULONG thread_input) static void thread_3_entry(ULONG thread_input) { - /* Inform user. */ printf("Running Thread Multiple Thread Sleep for 33 Test.................... "); /* Clear the tick count. */ tx_time_set(0); - /* Sleep for 100 ticks (+1 in case tick before threads 0,1,2 have run). */ + /* Sleep for the target interval, with one extra tick in the default case + in case the first tick arrives before threads 0, 1, and 2 have run. */ tx_thread_sleep(101); /* Determine if the sleep was accurate. */ @@ -181,4 +183,3 @@ static void thread_3_entry(ULONG thread_input) test_control_return(1); } } - diff --git a/test/smp/regression/threadx_thread_relinquish_test.c b/test/smp/regression/threadx_thread_relinquish_test.c index 7b46c8204..7c7efbd18 100644 --- a/test/smp/regression/threadx_thread_relinquish_test.c +++ b/test/smp/regression/threadx_thread_relinquish_test.c @@ -218,7 +218,6 @@ CHAR *pointer; static void thread_0_entry(ULONG thread_input) { - /* Check for correct input value and execution of other threads. */ if ((thread_input != 0) || (thread_1_counter) || (thread_2_counter) || (thread_3_counter)) @@ -234,7 +233,6 @@ static void thread_0_entry(ULONG thread_input) static void thread_1_entry(ULONG thread_input) { - /* Check for correct input value and execution of other threads. */ if ((thread_input != 1) || (thread_0_counter != 1) || (thread_2_counter) || (thread_3_counter)) @@ -250,7 +248,6 @@ static void thread_1_entry(ULONG thread_input) static void thread_2_entry(ULONG thread_input) { - /* Check for correct input value and execution of other threads. */ if ((thread_input != 2) || (thread_0_counter != 1) || (thread_1_counter != 1) || (thread_3_counter)) @@ -455,5 +452,3 @@ static void thread_9_entry(ULONG thread_input) tx_thread_relinquish(); } } - - diff --git a/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c b/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c index 344672461..addb28757 100644 --- a/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c +++ b/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c @@ -311,7 +311,6 @@ volatile ULONG value = 0; #endif while (isr_test_suspend_interrupted_condition != TX_TRUE) { - /* Sleep to get a frest timer slot. */ tx_thread_sleep(1); @@ -432,4 +431,3 @@ volatile ULONG value = 0; test_control_return(0); } } - diff --git a/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c b/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c index 5a65fced9..d5241cc3b 100644 --- a/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c +++ b/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c @@ -269,4 +269,3 @@ static void timer_0_entry(ULONG input) { timer_0_counter++; } - diff --git a/test/smp/regression/threadx_timer_multiple_accuracy_test.c b/test/smp/regression/threadx_timer_multiple_accuracy_test.c index af9957d8b..206f28025 100644 --- a/test/smp/regression/threadx_timer_multiple_accuracy_test.c +++ b/test/smp/regression/threadx_timer_multiple_accuracy_test.c @@ -183,4 +183,3 @@ static void timer_2_expiration(ULONG timer_input) /* Process timer expiration. */ timer_2_counter++; } - diff --git a/test/smp/regression/threadx_timer_simple_test.c b/test/smp/regression/threadx_timer_simple_test.c index b763ad553..b7c3f7c75 100644 --- a/test/smp/regression/threadx_timer_simple_test.c +++ b/test/smp/regression/threadx_timer_simple_test.c @@ -596,7 +596,6 @@ ULONG exclusion_map; /* Create a timer for the test. */ tx_timer_create(&timer_0, "timer 0", timer_entry, 0, 1, 1, TX_AUTO_ACTIVATE); - /* Setup the ISR. */ test_isr_dispatch = test_isr; diff --git a/test/tx/cmake/CMakeLists.txt b/test/tx/cmake/CMakeLists.txt index 2dd16ade5..97b3615bd 100644 --- a/test/tx/cmake/CMakeLists.txt +++ b/test/tx/cmake/CMakeLists.txt @@ -2,8 +2,16 @@ cmake_minimum_required(VERSION 3.13 FATAL_ERROR) cmake_policy(SET CMP0054 NEW) cmake_policy(SET CMP0057 NEW) +if((DEFINED THREADX_ARCH) AND ((THREADX_ARCH STREQUAL "win32") OR (THREADX_ARCH STREQUAL "win64"))) + set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) +endif() + project(threadx_test LANGUAGES C) +set(CMAKE_C_STANDARD 99) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS OFF) + # Set build configurations set(BUILD_CONFIGURATIONS default_build_coverage disable_notify_callbacks_build stack_checking_build stack_checking_rand_fill_build trace_build) @@ -22,24 +30,30 @@ endif() message(STATUS "Build type: ${CMAKE_BUILD_TYPE}") message(STATUS "Using toolchain file: ${CMAKE_TOOLCHAIN_FILE}.") -set(default_build_coverage -DTX_QUEUE_MESSAGE_MAX_SIZE=32) -set(disable_notify_callbacks_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_DISABLE_NOTIFY_CALLBACKS) -set(stack_checking_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_ENABLE_STACK_CHECKING) -set(stack_checking_rand_fill_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_ENABLE_STACK_CHECKING -DTX_ENABLE_RANDOM_NUMBER_STACK_FILLING) -set(trace_build -DTX_QUEUE_MESSAGE_MAX_SIZE=32 -DTX_ENABLE_EVENT_TRACE) +set(default_build_coverage TX_QUEUE_MESSAGE_MAX_SIZE=32) +set(disable_notify_callbacks_build TX_QUEUE_MESSAGE_MAX_SIZE=32 TX_DISABLE_NOTIFY_CALLBACKS) +set(stack_checking_build TX_QUEUE_MESSAGE_MAX_SIZE=32 TX_ENABLE_STACK_CHECKING) +set(stack_checking_rand_fill_build TX_QUEUE_MESSAGE_MAX_SIZE=32 TX_ENABLE_STACK_CHECKING TX_ENABLE_RANDOM_NUMBER_STACK_FILLING) +set(trace_build TX_QUEUE_MESSAGE_MAX_SIZE=32 TX_ENABLE_EVENT_TRACE) -add_compile_options( - -m32 - -std=c99 - -ggdb - -g3 - -gdwarf-2 - -fdiagnostics-color - -Werror - -DTX_REGRESSION_TEST - -DTEST_STACK_SIZE_PRINTF=4096 +add_compile_definitions( + TX_REGRESSION_TEST + TEST_STACK_SIZE_PRINTF=4096 ${${CMAKE_BUILD_TYPE}}) -add_link_options(-m32) + +if(MSVC) + add_compile_options(/W3 /Zi) + add_link_options(/DEBUG /INCREMENTAL:NO) +else() + add_compile_options( + -m32 + -ggdb + -g3 + -gdwarf-2 + -fdiagnostics-color + -Werror) + add_link_options(-m32) +endif() enable_testing() @@ -49,26 +63,32 @@ add_subdirectory(samples) # Coverage if(CMAKE_BUILD_TYPE MATCHES ".*_coverage") - target_compile_options(threadx PRIVATE -fprofile-arcs -ftest-coverage) - target_link_options(threadx PRIVATE -fprofile-arcs -ftest-coverage) + if(NOT MSVC) + target_compile_options(threadx PRIVATE -fprofile-arcs -ftest-coverage) + target_link_options(threadx PRIVATE -fprofile-arcs -ftest-coverage) + endif() endif() -target_compile_options( - threadx - PRIVATE -Werror - -Wall - -Wextra - -pedantic - -fmessage-length=0 - -fsigned-char - -ffunction-sections - -fdata-sections - -Wunused - -Wuninitialized - -Wmissing-declarations - -Wconversion - -Wpointer-arith - # -Wshadow - -Wlogical-op - -Waggregate-return - -Wfloat-equal) +if(MSVC) + target_compile_options(threadx PRIVATE /W3) +else() + target_compile_options( + threadx + PRIVATE -Werror + -Wall + -Wextra + -pedantic + -fmessage-length=0 + -fsigned-char + -ffunction-sections + -fdata-sections + -Wunused + -Wuninitialized + -Wmissing-declarations + -Wconversion + -Wpointer-arith + # -Wshadow + -Wlogical-op + -Waggregate-return + -Wfloat-equal) +endif() diff --git a/test/tx/cmake/regression/CMakeLists.txt b/test/tx/cmake/regression/CMakeLists.txt index d60743fac..25029ab91 100644 --- a/test/tx/cmake/regression/CMakeLists.txt +++ b/test/tx/cmake/regression/CMakeLists.txt @@ -4,6 +4,14 @@ cmake_policy(SET CMP0057 NEW) project(regression_test LANGUAGES C) set(SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/../../regression) +set(REPO_ROOT ${CMAKE_CURRENT_LIST_DIR}/../../../..) +set(PORT_LOW_LEVEL_SOURCE ${REPO_ROOT}/ports/${THREADX_ARCH}/${THREADX_TOOLCHAIN}/src/tx_initialize_low_level.c) +set(GENERATED_LOW_LEVEL_SOURCE ${CMAKE_CURRENT_BINARY_DIR}/tx_initialize_low_level.c) +set(TESTCONTROL_WEAK_DEFAULTS_SOURCE ${REPO_ROOT}/test/shared/regression/testcontrol_weak_defaults.c) + +if(NOT EXISTS ${PORT_LOW_LEVEL_SOURCE}) + message(FATAL_ERROR "Unable to locate tx_initialize_low_level.c for ${THREADX_ARCH}/${THREADX_TOOLCHAIN}") +endif() set(regression_test_cases ${SOURCE_DIR}/threadx_block_memory_basic_test.c @@ -104,19 +112,32 @@ set(regression_test_cases ${SOURCE_DIR}/threadx_initialize_kernel_setup_test.c) add_custom_command( - OUTPUT ${SOURCE_DIR}/tx_initialize_low_level.c - COMMAND bash ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.sh + OUTPUT ${GENERATED_LOW_LEVEL_SOURCE} + COMMAND ${CMAKE_COMMAND} + -DSOURCE_FILE=${PORT_LOW_LEVEL_SOURCE} + -DOUTPUT_FILE=${GENERATED_LOW_LEVEL_SOURCE} + -P ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.cmake + DEPENDS ${PORT_LOW_LEVEL_SOURCE} ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.cmake COMMENT "Generating tx_initialize_low_level.c for test") -add_library(test_utility ${SOURCE_DIR}/tx_initialize_low_level.c - ${SOURCE_DIR}/testcontrol.c) -target_link_libraries(test_utility PUBLIC azrtos::threadx) -target_compile_definitions(test_utility PUBLIC CTEST BATCH_TEST - TEST_STACK_SIZE_PRINTF=4096) +add_library(test_utility OBJECT ${GENERATED_LOW_LEVEL_SOURCE} + ${SOURCE_DIR}/testcontrol.c + ${TESTCONTROL_WEAK_DEFAULTS_SOURCE}) +target_compile_definitions(test_utility PRIVATE CTEST BATCH_TEST + TEST_STACK_SIZE_PRINTF=4096) +target_link_libraries(test_utility PRIVATE azrtos::threadx) foreach(test_case ${regression_test_cases}) get_filename_component(test_name ${test_case} NAME_WE) - add_executable(${test_name} ${test_case}) - target_link_libraries(${test_name} PRIVATE test_utility) + + if(test_name STREQUAL "threadx_initialize_kernel_setup_test") + add_executable(${test_name} ${test_case}) + else() + add_executable(${test_name} ${test_case} $) + target_compile_definitions(${test_name} PRIVATE CTEST BATCH_TEST + TEST_STACK_SIZE_PRINTF=4096) + endif() + + target_link_libraries(${test_name} PRIVATE azrtos::threadx) add_test(${CMAKE_BUILD_TYPE}::${test_name} ${test_name}) endforeach() diff --git a/test/tx/cmake/regression/generate_test_file.cmake b/test/tx/cmake/regression/generate_test_file.cmake new file mode 100644 index 000000000..d37e744b3 --- /dev/null +++ b/test/tx/cmake/regression/generate_test_file.cmake @@ -0,0 +1,42 @@ +if(NOT DEFINED SOURCE_FILE) + message(FATAL_ERROR "SOURCE_FILE is required") +endif() + +if(NOT DEFINED OUTPUT_FILE) + message(FATAL_ERROR "OUTPUT_FILE is required") +endif() + +file(STRINGS "${SOURCE_FILE}" FILE_LINES) + +set(UPDATED_FILE_CONTENTS "") +set(DISPATCH_DECLARATION "VOID test_interrupt_dispatch(VOID);") +set(DISPATCH_CALL "test_interrupt_dispatch();") +set(DECLARATION_INSERTED FALSE) +set(CALL_INSERTED FALSE) + +foreach(FILE_LINE IN LISTS FILE_LINES) + if((NOT DECLARATION_INSERTED) AND + ((FILE_LINE MATCHES "^void[ \t]+\\*_tx_linux_timer_interrupt\\(void \\*p\\);[ \t]*$") + OR + (FILE_LINE MATCHES "^VOID CALLBACK[ \t]+_tx_win32_timer_interrupt\\(UINT wTimerID, UINT msg, DWORD_PTR dwUser, DWORD_PTR dw1, DWORD_PTR dw2\\);[ \t]*$"))) + string(APPEND UPDATED_FILE_CONTENTS "${FILE_LINE}\n${DISPATCH_DECLARATION}\n") + set(DECLARATION_INSERTED TRUE) + elseif((NOT CALL_INSERTED) AND (FILE_LINE MATCHES "^([ \t]*)_tx_timer_interrupt\\(\\);[ \t]*$")) + string(APPEND UPDATED_FILE_CONTENTS "${CMAKE_MATCH_1}${DISPATCH_CALL}\n${FILE_LINE}\n") + set(CALL_INSERTED TRUE) + else() + string(APPEND UPDATED_FILE_CONTENTS "${FILE_LINE}\n") + endif() +endforeach() + +if(NOT CALL_INSERTED) + message(FATAL_ERROR "Unable to insert test interrupt dispatcher call into ${SOURCE_FILE}") +endif() + +if(NOT DECLARATION_INSERTED) + message(FATAL_ERROR "Unable to insert test interrupt dispatcher declaration into ${SOURCE_FILE}") +endif() + +get_filename_component(OUTPUT_DIRECTORY "${OUTPUT_FILE}" DIRECTORY) +file(MAKE_DIRECTORY "${OUTPUT_DIRECTORY}") +file(WRITE "${OUTPUT_FILE}" "${UPDATED_FILE_CONTENTS}") diff --git a/test/tx/regression/testcontrol.c b/test/tx/regression/testcontrol.c index 4944784a6..68f1158ee 100644 --- a/test/tx/regression/testcontrol.c +++ b/test/tx/regression/testcontrol.c @@ -1,4 +1,5 @@ /* This is the test control routine of the ThreadX kernel. All tests are dispatched from this routine. */ +// Some portions generated by Codex (gpt 5.4). #include "tx_api.h" #include @@ -122,7 +123,6 @@ typedef struct TEST_ENTRY_STRUCT VOID (*test_entry)(void *); } TEST_ENTRY; - /* Define the prototypes for the test entry points. */ void threadx_block_memory_basic_application_define(void *); @@ -483,7 +483,6 @@ UINT i, j; TX_THREAD *thread_ptr; #endif - /* Initialize the test error/success counters. */ test_control_successful_tests = 0; test_control_failed_tests = 0; @@ -565,6 +564,7 @@ TX_THREAD *thread_ptr; /* Clear the ISR dispatch. */ test_isr_dispatch = TX_NULL; + /* Ensure that _tx_thread_time_slice can handle NULL thread, note that current thread pointer is NULL at this point. */ _tx_thread_time_slice(); @@ -586,7 +586,7 @@ TX_THREAD *thread_ptr; init_test_thread.tx_thread_ready_previous = &init_test_thread; _tx_thread_time_slice(); _tx_thread_current_ptr = TX_NULL; - +#ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Test to make sure _tx_thread_shell_entry can handle a NULL mutex release function pointer. */ temp_mutex_release = _tx_thread_mutex_release; temp_thread = _tx_thread_execute_ptr; @@ -605,6 +605,7 @@ TX_THREAD *thread_ptr; _tx_thread_current_ptr = TX_NULL; _tx_thread_execute_ptr = temp_thread; _tx_thread_mutex_release = temp_mutex_release; /* Recover Mutex release pointer. */ +#endif /* Test _tx_thread_system_suspend when not current, preemption is needed but disabled. */ temp_thread = _tx_thread_execute_ptr; @@ -1413,14 +1414,3 @@ void test_exit_notify(TX_THREAD *thread_ptr, UINT type) } -__attribute__((weak)) void abort_all_threads_suspended_on_mutex(void) -{ -} - -__attribute__((weak)) void suspend_lowest_priority(void) -{ -} - -__attribute__((weak)) void abort_and_resume_byte_allocating_thread(void) -{ -} diff --git a/test/tx/regression/threadx_block_memory_basic_test.c b/test/tx/regression/threadx_block_memory_basic_test.c index b2dccbff6..c49effe7a 100644 --- a/test/tx/regression/threadx_block_memory_basic_test.c +++ b/test/tx/regression/threadx_block_memory_basic_test.c @@ -3,6 +3,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" typedef struct BLOCK_MEMORY_TEST_STRUCT { @@ -86,7 +87,7 @@ CHAR *pointer; /* Attempt to create a block pool from a timer. */ pointer = (CHAR *) 0x30000; - status = tx_block_pool_create(&pool_3, "pool 3", 100, pointer, 320); + status = tx_block_pool_create(&pool_3, "pool 3", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); /* Check status. */ if (status != TX_CALLER_ERROR) @@ -146,7 +147,7 @@ UINT status; } /* Attempt to create a block pool from an ISR. */ - status = tx_block_pool_create(&pool_3, "pool 3", 100, (void *) 0x100000, 320); + status = tx_block_pool_create(&pool_3, "pool 3", 100, (void *) 0x100000, TX_TEST_BLOCK_POOL_BYTES(100, 3)); /* Check status. */ if (status != TX_CALLER_ERROR) @@ -217,8 +218,8 @@ CHAR *pointer; } /* Create block pools 0 and 1. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); - pointer = pointer + 340; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -228,8 +229,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, 340); - pointer = pointer + 340; + status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -265,7 +266,7 @@ CHAR *pointer_2; CHAR *pointer_3; CHAR *pointer_4; INT i; -unsigned long fake_block[20]; +TX_TEST_POINTER_WORD fake_block[20]; /* Inform user. */ @@ -316,7 +317,7 @@ unsigned long fake_block[20]; /* Try to release a block that points to a non-pool. */ fake_block[0] = 0; - fake_block[1] = (unsigned long) &fake_block[0]; + TX_TEST_STORE_POINTER(fake_block[1], &fake_block[0]); status = tx_block_release(&fake_block[2]); /* Check status. */ diff --git a/test/tx/regression/threadx_block_memory_error_detection_test.c b/test/tx/regression/threadx_block_memory_error_detection_test.c index e06c4d174..e9869b1eb 100644 --- a/test/tx/regression/threadx_block_memory_error_detection_test.c +++ b/test/tx/regression/threadx_block_memory_error_detection_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -49,18 +50,18 @@ INT status; pointer = pointer + TEST_STACK_SIZE_PRINTF; /* Create block pool 0. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); - pointer = pointer + 340; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); #ifndef TX_DISABLE_ERROR_CHECKING /* skip this test and pretend it passed */ /* Create block pool again to get pool_ptr error. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 320); + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); if (status != TX_POOL_ERROR) return; /* Create block pool with NULL pointer. */ - status = tx_block_pool_create(TX_NULL, "pool 0", 100, pointer, 320); + status = tx_block_pool_create(TX_NULL, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); if (status != TX_POOL_ERROR) { @@ -69,7 +70,7 @@ INT status; } /* Create block pool pointer if NULL start. */ - status = tx_block_pool_create(&pool_1, "pool 0", 100, NULL, 320); + status = tx_block_pool_create(&pool_1, "pool 0", 100, NULL, TX_TEST_BLOCK_POOL_BYTES(100, 3)); if (status != TX_PTR_ERROR) { @@ -128,11 +129,11 @@ INT i; #ifndef TX_DISABLE_ERROR_CHECKING /* skip this test and pretend it passed */ - status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, 340); - pointer = pointer + 340; + status = tx_block_pool_create(&pool_1, "pool 1", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Attempt to create a pool with an invalid size. */ - status = _txe_block_pool_create(&pool_2, "pool 2", 100, pointer, 320, 777777); + status = _txe_block_pool_create(&pool_2, "pool 2", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3), 777777); if (status != TX_POOL_ERROR) { @@ -384,4 +385,3 @@ INT i; printf("SUCCESS!\n"); test_control_return(0); } - diff --git a/test/tx/regression/threadx_block_memory_suspension_test.c b/test/tx/regression/threadx_block_memory_suspension_test.c index 3b49f5d9b..9ce8939c5 100644 --- a/test/tx/regression/threadx_block_memory_suspension_test.c +++ b/test/tx/regression/threadx_block_memory_suspension_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -83,8 +84,8 @@ CHAR *pointer; } /* Create block pool. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); - pointer = pointer + 340; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -308,4 +309,3 @@ CHAR *pointer_1; } } - diff --git a/test/tx/regression/threadx_block_memory_suspension_timeout_test.c b/test/tx/regression/threadx_block_memory_suspension_timeout_test.c index a2be3c6c9..d3f8d4935 100644 --- a/test/tx/regression/threadx_block_memory_suspension_timeout_test.c +++ b/test/tx/regression/threadx_block_memory_suspension_timeout_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -84,8 +85,8 @@ CHAR *pointer; } /* Create block pool. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); - pointer = pointer + 340; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -209,4 +210,3 @@ CHAR *pointer_1; thread_2_counter++; } } - diff --git a/test/tx/regression/threadx_block_memory_thread_terminate_test.c b/test/tx/regression/threadx_block_memory_thread_terminate_test.c index c568d9a20..291ab0187 100644 --- a/test/tx/regression/threadx_block_memory_thread_terminate_test.c +++ b/test/tx/regression/threadx_block_memory_thread_terminate_test.c @@ -3,6 +3,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -69,8 +70,8 @@ CHAR *pointer; } /* Create block pool. */ - status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, 340); - pointer = pointer + 340; + status = tx_block_pool_create(&pool_0, "pool 0", 100, pointer, TX_TEST_BLOCK_POOL_BYTES(100, 3)); + pointer = pointer + TX_TEST_BLOCK_POOL_BYTES(100, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -182,4 +183,3 @@ CHAR *pointer_1; thread_1_counter++; } } - diff --git a/test/tx/regression/threadx_byte_memory_basic_test.c b/test/tx/regression/threadx_byte_memory_basic_test.c index d153ccafa..aff266fdd 100644 --- a/test/tx/regression/threadx_byte_memory_basic_test.c +++ b/test/tx/regression/threadx_byte_memory_basic_test.c @@ -3,6 +3,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" /* Per-allocation overhead in byte pools: next pointer + ALIGN_TYPE alignment marker. */ #define BYTE_POOL_OVERHEAD (sizeof(UCHAR *) + sizeof(ALIGN_TYPE)) @@ -100,7 +101,7 @@ CHAR *pointer; /* Attempt to create a byte pool from a timer. */ pointer = (CHAR *) 0x30000; - status = tx_byte_pool_create(&pool_2, "pool 2", pointer, 108); + status = tx_byte_pool_create(&pool_2, "pool 2", pointer, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_CALLER_ERROR) @@ -112,7 +113,7 @@ CHAR *pointer; /* Attempt to create a byte pool with an invalid size. */ status = _txe_byte_pool_create(&pool_3, "pool 3", pointer, - 108, (sizeof(TX_BYTE_POOL)+1)); + TX_TEST_BYTE_POOL_BYTES(108), (sizeof(TX_BYTE_POOL)+1)); /* Check status. */ if (status != TX_POOL_ERROR) @@ -195,7 +196,7 @@ UINT status; /* Attempt to create a byte pool from an ISR. */ - status = tx_byte_pool_create(&pool_2, "pool 0", (void *) 0x100000, 108); + status = tx_byte_pool_create(&pool_2, "pool 0", (void *) 0x100000, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_CALLER_ERROR) @@ -265,8 +266,8 @@ CHAR *pointer; } /* Create byte pools 0 and 1. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, POOL_0_SIZE); - pointer = pointer + POOL_0_SIZE; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_CAPACITY_BYTES(24, 3)); + pointer = pointer + TX_TEST_BYTE_POOL_CAPACITY_BYTES(24, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -276,8 +277,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_byte_pool_create(&pool_1, "pool 1", pointer, 200); - pointer = pointer + 200; + status = tx_byte_pool_create(&pool_1, "pool 1", pointer, TX_TEST_BYTE_POOL_BYTES(200)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(200); /* Check status. */ if (status != TX_SUCCESS) @@ -288,9 +289,9 @@ CHAR *pointer; } /* Test for search pointer issue on wrapped seach with prior block to search pointer merged. */ - status = tx_byte_pool_create(&pool_4, "pool 4", pointer, POOL_4_SIZE); + status = tx_byte_pool_create(&pool_4, "pool 4", pointer, TX_TEST_BYTE_POOL_CAPACITY_BYTES(84, 3)); pool_4_memory = pointer; - pointer = pointer + POOL_4_SIZE; + pointer = pointer + TX_TEST_BYTE_POOL_CAPACITY_BYTES(84, 3); /* Check status. */ if (status != TX_SUCCESS) @@ -362,7 +363,7 @@ CHAR *pointer_2; CHAR *pointer_3; CHAR *pointer_4; INT i; -ULONG array[20]; +TX_TEST_POINTER_WORD array[20]; UCHAR *save_search; @@ -403,7 +404,7 @@ UCHAR *save_search; /* Try to create a NULL pool. */ pointer_1 = (CHAR *) 0x30000; - status = tx_byte_pool_create(TX_NULL, "pool 0", pointer_1, 108); + status = tx_byte_pool_create(TX_NULL, "pool 0", pointer_1, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_POOL_ERROR) @@ -415,7 +416,7 @@ UCHAR *save_search; } /* Try to create the same pool. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer_1, 108); + status = tx_byte_pool_create(&pool_0, "pool 0", pointer_1, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_POOL_ERROR) @@ -427,7 +428,7 @@ UCHAR *save_search; } /* Try to create a pool with a NULL start address. */ - status = tx_byte_pool_create(&pool_2, "pool 2", TX_NULL, 108); + status = tx_byte_pool_create(&pool_2, "pool 2", TX_NULL, TX_TEST_BYTE_POOL_BYTES(108)); /* Check status. */ if (status != TX_PTR_ERROR) @@ -635,7 +636,7 @@ UCHAR *save_search; /* Test another bad block release.... pool pointer is not a valid pool! */ array[0] = 0; - array[1] = (ULONG) &array[3]; + TX_TEST_STORE_POINTER(array[1], &array[3]); array[2] = 0; array[3] = 0; status = _tx_byte_release(&array[2]); @@ -874,7 +875,7 @@ UCHAR *save_search; } /* Move the search pointer to the third block to exercise that code in the byte search algorithm. */ - pool_0.tx_byte_pool_search = (UCHAR *) pointer_3 - BYTE_POOL_OVERHEAD; + pool_0.tx_byte_pool_search = (UCHAR *) pointer_3 - TX_TEST_BYTE_POOL_SEARCH_OFFSET; /* Now allocate the block again. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_2, 24, TX_NO_WAIT); @@ -894,7 +895,7 @@ UCHAR *save_search; status += tx_byte_release(pointer_1); /* Move the search pointer to the third block to exercise that code in the byte search algorithm. */ - pool_0.tx_byte_pool_search = (UCHAR *) pointer_3 - BYTE_POOL_OVERHEAD; + pool_0.tx_byte_pool_search = (UCHAR *) pointer_3 - TX_TEST_BYTE_POOL_SEARCH_OFFSET; /* Allocate a large block to force the search pointer update. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_3, 88, TX_NO_WAIT); @@ -970,7 +971,7 @@ UCHAR *save_search; } /* Create pool 4. */ - status = tx_byte_pool_create(&pool_4, "pool 4", pool_4_memory, POOL_4_SIZE); + status = tx_byte_pool_create(&pool_4, "pool 4", pool_4_memory, TX_TEST_BYTE_POOL_CAPACITY_BYTES(84, 3)); /* Check status. */ if (status != TX_SUCCESS) @@ -1070,4 +1071,3 @@ UCHAR *save_search; printf("SUCCESS!\n"); test_control_return(0); } - diff --git a/test/tx/regression/threadx_byte_memory_information_test.c b/test/tx/regression/threadx_byte_memory_information_test.c index 8a6192694..df607acb4 100644 --- a/test/tx/regression/threadx_byte_memory_information_test.c +++ b/test/tx/regression/threadx_byte_memory_information_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" #include "tx_byte_pool.h" @@ -193,7 +194,7 @@ CHAR *pointer; } /* Create the byte_pool with one byte. */ - status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, 100); + status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(100)); pointer = pointer + 100; /* Check for status. */ diff --git a/test/tx/regression/threadx_byte_memory_prioritize_test.c b/test/tx/regression/threadx_byte_memory_prioritize_test.c index 294071350..9160db91a 100644 --- a/test/tx/regression/threadx_byte_memory_prioritize_test.c +++ b/test/tx/regression/threadx_byte_memory_prioritize_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" /* Define the ISR dispatch. */ @@ -197,7 +198,7 @@ CHAR *pointer; } /* Create the byte_pool with one byte. */ - status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, 100); + status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(100)); pointer = pointer + 100; /* Check for status. */ @@ -495,4 +496,3 @@ VOID *pointer; thread_6_counter++; } } - diff --git a/test/tx/regression/threadx_byte_memory_suspension_test.c b/test/tx/regression/threadx_byte_memory_suspension_test.c index ba159894b..2736195dc 100644 --- a/test/tx/regression/threadx_byte_memory_suspension_test.c +++ b/test/tx/regression/threadx_byte_memory_suspension_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -121,8 +122,8 @@ CHAR *pointer; } /* Create byte pool 0. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(108)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(108); /* Check status. */ if (status != TX_SUCCESS) diff --git a/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c b/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c index 5e94df97a..c5f8adac1 100644 --- a/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c +++ b/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -85,8 +86,8 @@ CHAR *pointer; } /* Create byte pool 0. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(108)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(108); /* Check status. */ if (status != TX_SUCCESS) diff --git a/test/tx/regression/threadx_byte_memory_thread_contention_test.c b/test/tx/regression/threadx_byte_memory_thread_contention_test.c index da2634e31..1c4deedaa 100644 --- a/test/tx/regression/threadx_byte_memory_thread_contention_test.c +++ b/test/tx/regression/threadx_byte_memory_thread_contention_test.c @@ -3,6 +3,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -89,8 +90,8 @@ CHAR *pointer; } /* Create byte pool 0. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(108)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(108); /* Save off the intial pool size. */ initial_pool_size = pool_0.tx_byte_pool_available; diff --git a/test/tx/regression/threadx_byte_memory_thread_terminate_test.c b/test/tx/regression/threadx_byte_memory_thread_terminate_test.c index 4805ba571..35a4615aa 100644 --- a/test/tx/regression/threadx_byte_memory_thread_terminate_test.c +++ b/test/tx/regression/threadx_byte_memory_thread_terminate_test.c @@ -2,6 +2,7 @@ #include #include "tx_api.h" +#include "threadx_test_port.h" static unsigned long thread_0_counter = 0; static TX_THREAD thread_0; @@ -68,8 +69,8 @@ CHAR *pointer; } /* Create byte pools 0 and 1. */ - status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); - pointer = pointer + 108; + status = tx_byte_pool_create(&pool_0, "pool 0", pointer, TX_TEST_BYTE_POOL_BYTES(108)); + pointer = pointer + TX_TEST_BYTE_POOL_BYTES(108); /* Check status. */ if (status != TX_SUCCESS) @@ -174,4 +175,3 @@ CHAR *pointer; thread_1_counter++; } } - diff --git a/test/tx/regression/threadx_event_flag_isr_set_clear_test.c b/test/tx/regression/threadx_event_flag_isr_set_clear_test.c index 7f89a06fb..4cb004d51 100644 --- a/test/tx/regression/threadx_event_flag_isr_set_clear_test.c +++ b/test/tx/regression/threadx_event_flag_isr_set_clear_test.c @@ -355,5 +355,3 @@ static void timer_0_entry(ULONG input) { timer_0_counter++; } - - diff --git a/test/tx/regression/threadx_event_flag_suspension_timeout_test.c b/test/tx/regression/threadx_event_flag_suspension_timeout_test.c index f4ee39955..fea08bb65 100644 --- a/test/tx/regression/threadx_event_flag_suspension_timeout_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_timeout_test.c @@ -181,9 +181,9 @@ UINT status; /* Check the run counters. Depending on the starting time relative to the tick boundary, thread 1 can run either 32 or 33 rounds and thread 2 can run 13 or 14 rounds. This variance applies to any - platform with non-deterministic tick alignment (Linux, QEMU, etc.). */ - if (((thread_1_counter != 32) && (thread_1_counter != 33)) || - ((thread_2_counter != 13) && (thread_2_counter != 14))) + platform with non-deterministic tick alignment (Linux, QEMU, Windows, etc.). */ + if (((thread_1_counter < 32UL) || (thread_1_counter > 33UL)) || + ((thread_2_counter < 13UL) || (thread_2_counter > 14UL))) { /* Event flag error. */ diff --git a/test/tx/regression/threadx_initialize_kernel_setup_test.c b/test/tx/regression/threadx_initialize_kernel_setup_test.c index 2ef8e1580..7f12b872f 100644 --- a/test/tx/regression/threadx_initialize_kernel_setup_test.c +++ b/test/tx/regression/threadx_initialize_kernel_setup_test.c @@ -1,6 +1,8 @@ /* This test is designed to test kernel setup functionality in ThreadX. */ +// Some portions generated by Codex (gpt 5.4). #include +#include #include "tx_api.h" #include "tx_initialize.h" #include "tx_thread.h" @@ -30,20 +32,7 @@ UINT test_byte_pool_create_init; UINT test_block_pool_create_init; UINT test_timer_create_init; - -__attribute__((weak)) void abort_all_threads_suspended_on_mutex(void) -{ -} - -__attribute__((weak)) void suspend_lowest_priority(void) -{ -} - -__attribute__((weak)) void abort_and_resume_byte_allocating_thread(void) -{ -} - -void main() +int main(void) { /* Setup the ThreadX kernel. */ @@ -59,6 +48,8 @@ void main() printf("Running Initialize Kernel Setup Test................................ ERROR!\n"); exit(1); } + + return(0); } void test_application_define(void *first_unused_memory){} @@ -78,4 +69,4 @@ void delete_timer_thread(void) _tx_thread_delete(&_tx_timer_thread); } -#endif \ No newline at end of file +#endif diff --git a/test/tx/regression/threadx_semaphore_timeout_test.c b/test/tx/regression/threadx_semaphore_timeout_test.c index 96585337a..c2fa83ae5 100644 --- a/test/tx/regression/threadx_semaphore_timeout_test.c +++ b/test/tx/regression/threadx_semaphore_timeout_test.c @@ -163,5 +163,3 @@ ULONG now; test_control_return(0); } } - - diff --git a/test/tx/regression/threadx_test_port.h b/test/tx/regression/threadx_test_port.h new file mode 100644 index 000000000..b8502b4de --- /dev/null +++ b/test/tx/regression/threadx_test_port.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * Copyright (C) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Codex (gpt 5.4). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +#ifndef THREADX_TEST_PORT_H +#define THREADX_TEST_PORT_H + +#include "tx_api.h" + +/* Preserve the original 32-bit test expectations for pool capacity. */ + +#define TX_TEST_BYTE_POOL_BASELINE_OVERHEAD ((ULONG) (2U * sizeof(ULONG))) +#define TX_TEST_BYTE_POOL_OVERHEAD ((ULONG) (sizeof(VOID *) + sizeof(ALIGN_TYPE))) +#define TX_TEST_BYTE_POOL_ALIGN(a) ((ULONG) (((((ULONG) (a)) + ((ULONG) sizeof(ALIGN_TYPE)) - ((ULONG) 1)) / ((ULONG) sizeof(ALIGN_TYPE))) * ((ULONG) sizeof(ALIGN_TYPE)))) +#define TX_TEST_BYTE_POOL_BYTES(a) ((ULONG) ((a) + (2U * (TX_TEST_BYTE_POOL_OVERHEAD - TX_TEST_BYTE_POOL_BASELINE_OVERHEAD)))) +#define TX_TEST_BYTE_POOL_CAPACITY_BYTES(a, b) ((ULONG) (((b) * TX_TEST_BYTE_POOL_ALIGN(a)) + (((b) + 1U) * TX_TEST_BYTE_POOL_OVERHEAD))) +#define TX_TEST_BYTE_POOL_SEARCH_OFFSET TX_TEST_BYTE_POOL_OVERHEAD + +#define TX_TEST_BLOCK_POOL_ALIGN(a) ((ULONG) (((((ULONG) (a)) + ((ULONG) sizeof(ALIGN_TYPE)) - ((ULONG) 1)) / ((ULONG) sizeof(ALIGN_TYPE))) * ((ULONG) sizeof(ALIGN_TYPE)))) +#define TX_TEST_BLOCK_POOL_BYTES(a, b) ((ULONG) ((b) * (TX_TEST_BLOCK_POOL_ALIGN(a) + ((ULONG) sizeof(UCHAR *))))) + +typedef ALIGN_TYPE TX_TEST_POINTER_WORD; + +#define TX_TEST_STORE_POINTER(a, b) (a) = ((TX_TEST_POINTER_WORD) TX_POINTER_TO_ALIGN_TYPE_CONVERT(b)) + +#endif diff --git a/test/tx/regression/threadx_thread_basic_execution_test.c b/test/tx/regression/threadx_thread_basic_execution_test.c index af2c8fa1c..a0f65a8cc 100644 --- a/test/tx/regression/threadx_thread_basic_execution_test.c +++ b/test/tx/regression/threadx_thread_basic_execution_test.c @@ -11,6 +11,7 @@ #include "tx_queue.h" #include "tx_semaphore.h" #include "tx_thread.h" +#include "tx_timer.h" typedef struct THREAD_MEMORY_TEST_STRUCT @@ -52,6 +53,9 @@ static unsigned long timer_executed = 0; static unsigned long isr_executed = 0; +extern TX_TIMER_INTERNAL *_tx_timer_expired_timer_ptr; + + /* Define task prototypes. */ static void thread_0_entry(ULONG task_input); @@ -386,7 +390,22 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_suspending = TX_TRUE; test_thread.tx_thread_delayed_suspend = TX_TRUE; +#if defined(_WIN64) + { + TX_TIMER_INTERNAL timeout_timer; + TX_TIMER_INTERNAL *saved_expired_timer_ptr; + + + TX_MEMSET(&timeout_timer, 0, sizeof(TX_TIMER_INTERNAL)); + saved_expired_timer_ptr = _tx_timer_expired_timer_ptr; + _tx_timer_expired_timer_ptr = &timeout_timer; + timeout_timer.tx_timer_internal_extension_ptr = (VOID *) &test_thread; + _tx_thread_timeout(0); + _tx_timer_expired_timer_ptr = saved_expired_timer_ptr; + } +#else _tx_thread_timeout((ULONG) &test_thread); +#endif /* Setup test thread to make sure _tx_thread_terminate can handle a NULL mutex release function pointer. */ temp_mutex_release = _tx_thread_mutex_release; @@ -975,5 +994,3 @@ TX_INTERRUPT_SAVE_AREA #endif #endif - - diff --git a/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c b/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c index df8bb62b6..99c5b848a 100644 --- a/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c +++ b/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c @@ -89,4 +89,3 @@ ULONG now; test_control_return(1); } } - diff --git a/test/tx/regression/threadx_thread_simple_sleep_test.c b/test/tx/regression/threadx_thread_simple_sleep_test.c index f038fafd5..45d42cb00 100644 --- a/test/tx/regression/threadx_thread_simple_sleep_test.c +++ b/test/tx/regression/threadx_thread_simple_sleep_test.c @@ -84,4 +84,3 @@ ULONG now; test_control_return(1); } } - diff --git a/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c b/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c index 344672461..4b257e8cb 100644 --- a/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c +++ b/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c @@ -432,4 +432,3 @@ volatile ULONG value = 0; test_control_return(0); } } - diff --git a/test/tx/regression/threadx_time_get_set_test.c b/test/tx/regression/threadx_time_get_set_test.c index 06b8e6f53..84b099472 100644 --- a/test/tx/regression/threadx_time_get_set_test.c +++ b/test/tx/regression/threadx_time_get_set_test.c @@ -104,4 +104,3 @@ ULONG current_time; test_control_return(0); } } - diff --git a/test/tx/regression/threadx_timer_multiple_accuracy_test.c b/test/tx/regression/threadx_timer_multiple_accuracy_test.c index af9957d8b..206f28025 100644 --- a/test/tx/regression/threadx_timer_multiple_accuracy_test.c +++ b/test/tx/regression/threadx_timer_multiple_accuracy_test.c @@ -183,4 +183,3 @@ static void timer_2_expiration(ULONG timer_input) /* Process timer expiration. */ timer_2_counter++; } - diff --git a/test/tx/regression/threadx_timer_multiple_test.c b/test/tx/regression/threadx_timer_multiple_test.c index 688a7d5ba..46742a385 100644 --- a/test/tx/regression/threadx_timer_multiple_test.c +++ b/test/tx/regression/threadx_timer_multiple_test.c @@ -346,4 +346,3 @@ static void timer_2_expiration(ULONG timer_input) /* Process timer expiration. */ timer_2_counter++; } - From 7486de06c80aac7ce8b40a9fbbabd448707e1fa8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Wed, 27 May 2026 10:30:57 -0400 Subject: [PATCH 22/29] Refactored, consolidated, and cleaned up RV32/RV64 ports (#536) risc-v: refactor, consolidate, and fix RV32/RV64 ports Consolidates the RISC-V 32-bit and 64-bit GNU/Clang port sources, fixes two pre-existing assembly bugs discovered during testing, and hardens the build infrastructure for both the regression suite and the CORE-V MCU example. --- Port consolidation (RV32 GNU + Clang) --- - Delete ports/risc-v32/clang/src/ (8 .S files had no Clang-specific directives; diverged from GNU only due to missing bug fixes). The Clang port CMakeLists.txt now compiles from ../gnu/src/. - Change .global -> .weak for _tx_initialize_low_level in gnu/src/ to allow BSP-level override without a linker conflict (adopted from Clang port). - Create ports/risc-v32/common/tx_port_riscv32_common.h with all definitions shared between GNU and Clang ports. Reduce both tx_port.h files to thin wrappers. - Add a prominent comment in risc-v64/gnu/inc/tx_port.h explaining why LONG/ULONG are intentionally 32-bit on RV64 (ThreadX ABI requirement, mirrors win64/MSVC LLP64). --- Shared CMake helper --- - Add cmake/threadx_riscv_port.cmake with threadx_add_riscv_port(). All three port CMakeLists.txt files are reduced to ~8 lines each. Include path is relative to CMAKE_CURRENT_LIST_DIR so the helper works whether ports are built standalone or as a subdirectory of the test framework. --- Shared example-build drivers --- - Create canonical driver files under ports/risc-v_common/: inc/csr.h (uintptr_t-based; portable RV32 + RV64) example_build/plic/ (plic.c, plic.h) example_build/uart/ (uart_qemu_ns16550.c/h; static inline putc_nolock) example_build/trap/ (trap_qemu.c; XLEN-portable mcause constants) - Replace per-example copies with symlinks in all qemu_virt and cva6_ariane example directories. - Fix OS_IS_INTERRUPT typo (was OS_IS_INTERUPT) in shared trap_qemu.c. - Gate print_hex() behind TX_RISCV_TRAP_DEBUG. --- Bug fixes in RV32 assembly --- tx_thread_schedule.S: - Solicited-return FP path: reload t0 from the mepc stack slot before csrw mepc, t0. After the FP restore block, t0 held the fcsr value (0 for new threads), which caused mepc = 0 and an immediate instruction-address fault on the first context switch. - Same path: reload t0 from the mstatus stack slot before csrw mstatus, t0 to avoid writing the stale fcsr value into mstatus. tx_thread_system_return.S: - FP callee-saved registers were saved unconditionally before the mstatus.FS check, causing an illegal instruction trap (mcause=0x2) when a thread with FS=Off (lazy FPU, thread has never used FP) voluntarily yielded. - Apply the same FS guard pattern used in tx_thread_context_save.S: read mstatus first, isolate FS[1:0], and skip fsw/fsd if FS == Off. Both bugs were pre-existing on origin/dev and are unrelated to the consolidation changes. --- RV64 64-bit pointer compatibility --- - Add TX_TIMER_INTERNAL_EXTENSION, TX_THREAD_CREATE_TIMEOUT_SETUP, and TX_THREAD_TIMEOUT_POINTER_SETUP to risc-v64/gnu/inc/tx_port.h to store the thread timeout pointer in a VOID * extension field rather than truncating it into a 32-bit ULONG. Mirrors the win64 port pattern. - Define TX_TIMER_EXTENSION_PTR_DEFINED as a portable sentinel. - Update threadx_thread_basic_execution_test.c guard from #if defined(_WIN64) to #if defined(_WIN64) || defined(TX_TIMER_EXTENSION_PTR_DEFINED). - Disable -Wconversion for the RV64 test build: ULONG = unsigned int (32-bit) is intentional for ThreadX ABI but triggers spurious warnings when sizeof() (8 bytes on RV64) appears in arithmetic with ULONG in common/src/. --- Regression suite cmake fixes --- test/tx/cmake/riscv/regression/CMakeLists.txt: - Build testcontrol_weak_defaults.c as a separate OBJECT library and include it in every test executable via $. GNU ld does not extract objects from a static archive to satisfy weak symbols, so bundling it in test_utility was insufficient for the standalone threadx_initialize_kernel_setup_test. test/tx/cmake/regression/CMakeLists.txt, test/smp/cmake/regression/CMakeLists.txt: - Same fix applied to the Linux and SMP regression builds. The symbols abort_all_threads_suspended_on_mutex, suspend_lowest_priority, and abort_and_resume_byte_allocating_thread were introduced by the win64 merge and left the standalone test unlinkable. --- CORE-V MCU toolchain and build fixes --- cmake/riscv64-gcc-rv32imc.cmake: - Resolve riscv64-unknown-elf-gcc via PATH so the riscv-collab toolchain in /opt/riscv/bin is preferred when it appears first. ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c (new): - The riscv-collab toolchain is built without rv32 multilib, so its libgcc does not define __clzsi2 (the helper emitted for __builtin_clz() in fll.c). Add a weak __clzsi2 fallback so the build is self-contained with any riscv64-unknown-elf toolchain. The weak attribute yields to a libgcc-provided strong symbol when the Ubuntu multilib package is used. core_v_mcu/CMakeLists.txt: - Add bsp/clz.c to sources. - Reference CMAKE_TOOLCHAIN_FILE via message(STATUS) to suppress the false- positive "Manually-specified variables were not used by the project" CMake warning and to show the active toolchain at configure time. --- Housekeeping --- - Rename azrtos_test_* -> threadx_test_* (eliminate Azure RTOS branding). - Add RV64 QEMU CI test script: ports/risc-v64/gnu/example_build/qemu_virt/test/ threadx_test_tx_gnu_riscv64_qemu.py - Normalize entry.s -> entry.S in all 4 example directories. - .gitignore: exclude build_m7/ and .codex local artifacts. - CI: comment out the riscv regression workflow job and remove it from the deploy job's needs list (preserved in-place for easy re-enablement). --- Verified --- - 95/95 RV32 regression tests pass (QEMU virt) - 95/95 RV64 regression tests pass (QEMU virt) - All 5 Linux build configurations build cleanly (default_build_coverage, disable_notify_callbacks_build, stack_checking_build, stack_checking_rand_fill_build, trace_build) - CORE-V MCU example_build links cleanly with /opt/riscv toolchain Co-authored-by: Copilot 223556219+Copilot@users.noreply.github.com --- .github/workflows/regression_test.yml | 37 +- .gitignore | 4 + cmake/riscv64-gcc-rv32imc.cmake | 18 +- cmake/threadx_riscv_port.cmake | 50 +++ ports/cortex_m33/gnu/CMakeLists.txt | 11 +- .../gnu/example_build/sample_threadx.c | 370 ++++++++++++++++ .../tx_initialize_low_level.S | 0 ports/cortex_m55/gnu/CMakeLists.txt | 11 +- .../gnu/example_build/sample_threadx.c | 370 ++++++++++++++++ .../tx_initialize_low_level.S | 0 ports/cortex_m85/gnu/CMakeLists.txt | 11 +- .../gnu/example_build/sample_threadx.c | 370 ++++++++++++++++ .../tx_initialize_low_level.S | 0 ports/risc-v32/clang/CMakeLists.txt | 26 +- .../qemu_virt/build_threadx_sample.sh | 2 +- .../clang/example_build/qemu_virt/csr.h | 344 +-------------- .../qemu_virt/{entry.s => entry.S} | 0 .../clang/example_build/qemu_virt/plic.c | 73 +--- .../clang/example_build/qemu_virt/plic.h | 50 +-- .../clang/example_build/qemu_virt/trap.c | 68 +-- .../clang/example_build/qemu_virt/uart.c | 103 +---- .../clang/example_build/qemu_virt/uart.h | 24 +- ports/risc-v32/clang/inc/tx_port.h | 230 +--------- .../clang/src/tx_initialize_low_level.S | 112 ----- .../clang/src/tx_thread_context_restore.S | 410 ------------------ .../clang/src/tx_thread_context_save.S | 271 ------------ .../clang/src/tx_thread_interrupt_control.S | 88 ---- ports/risc-v32/clang/src/tx_thread_schedule.S | 318 -------------- .../clang/src/tx_thread_stack_build.S | 221 ---------- .../clang/src/tx_thread_system_return.S | 168 ------- ports/risc-v32/clang/src/tx_timer_interrupt.S | 204 --------- .../risc-v32/common/tx_port_riscv32_common.h | 268 ++++++++++++ ports/risc-v32/gnu/CMakeLists.txt | 26 +- .../example_build/core_v_mcu/CMakeLists.txt | 5 + .../gnu/example_build/core_v_mcu/bsp/clz.c | 29 ++ .../cva6_ariane/{entry.s => entry.S} | 0 .../gnu/example_build/cva6_ariane/plic.c | 73 +--- .../gnu/example_build/cva6_ariane/plic.h | 50 +-- .../example_build/qemu_virt/CMakeLists.txt | 4 +- .../qemu_virt/build_libthreadx.sh | 2 +- .../gnu/example_build/qemu_virt/csr.h | 344 +-------------- .../qemu_virt/{entry.s => entry.S} | 0 .../gnu/example_build/qemu_virt/plic.c | 73 +--- .../gnu/example_build/qemu_virt/plic.h | 50 +-- ...py => threadx_test_tx_gnu_riscv32_qemu.py} | 0 .../gnu/example_build/qemu_virt/trap.c | 68 +-- .../gnu/example_build/qemu_virt/uart.c | 103 +---- .../gnu/example_build/qemu_virt/uart.h | 24 +- ports/risc-v32/gnu/inc/tx_port.h | 221 +--------- .../gnu/src/tx_initialize_low_level.S | 2 +- ports/risc-v32/gnu/src/tx_thread_schedule.S | 2 + .../gnu/src/tx_thread_system_return.S | 18 +- ports/risc-v64/gnu/CMakeLists.txt | 21 +- .../qemu_virt/build_libthreadx.sh | 2 +- .../gnu/example_build/qemu_virt/csr.h | 376 +--------------- .../qemu_virt/{entry.s => entry.S} | 0 .../gnu/example_build/qemu_virt/plic.c | 73 +--- .../gnu/example_build/qemu_virt/plic.h | 52 +-- .../test/threadx_test_tx_gnu_riscv64_qemu.py | 275 ++++++++++++ .../gnu/example_build/qemu_virt/trap.c | 47 +- .../gnu/example_build/qemu_virt/uart.c | 101 +---- .../gnu/example_build/qemu_virt/uart.h | 23 +- ports/risc-v64/gnu/inc/tx_port.h | 23 + ports/risc-v_common/example_build/plic/plic.c | 79 ++++ ports/risc-v_common/example_build/plic/plic.h | 48 ++ .../example_build/trap/trap_qemu.c | 92 ++++ .../example_build/uart/uart_qemu_ns16550.c | 99 +++++ .../example_build/uart/uart_qemu_ns16550.h | 22 + ports/risc-v_common/inc/csr.h | 356 +++++++++++++++ test/smp/cmake/regression/CMakeLists.txt | 14 +- test/tx/cmake/regression/CMakeLists.txt | 14 +- test/tx/cmake/riscv/CMakeLists.txt | 10 +- test/tx/cmake/riscv/regression/CMakeLists.txt | 16 +- .../threadx_thread_basic_execution_test.c | 3 +- 74 files changed, 2625 insertions(+), 4447 deletions(-) create mode 100644 cmake/threadx_riscv_port.cmake create mode 100644 ports/cortex_m33/gnu/example_build/sample_threadx.c rename ports/cortex_m33/gnu/{src => example_build}/tx_initialize_low_level.S (100%) create mode 100644 ports/cortex_m55/gnu/example_build/sample_threadx.c rename ports/cortex_m55/gnu/{src => example_build}/tx_initialize_low_level.S (100%) create mode 100644 ports/cortex_m85/gnu/example_build/sample_threadx.c rename ports/cortex_m85/gnu/{src => example_build}/tx_initialize_low_level.S (100%) mode change 100644 => 120000 ports/risc-v32/clang/example_build/qemu_virt/csr.h rename ports/risc-v32/clang/example_build/qemu_virt/{entry.s => entry.S} (100%) mode change 100644 => 120000 ports/risc-v32/clang/example_build/qemu_virt/plic.c mode change 100644 => 120000 ports/risc-v32/clang/example_build/qemu_virt/plic.h mode change 100644 => 120000 ports/risc-v32/clang/example_build/qemu_virt/trap.c mode change 100644 => 120000 ports/risc-v32/clang/example_build/qemu_virt/uart.c mode change 100644 => 120000 ports/risc-v32/clang/example_build/qemu_virt/uart.h delete mode 100644 ports/risc-v32/clang/src/tx_initialize_low_level.S delete mode 100644 ports/risc-v32/clang/src/tx_thread_context_restore.S delete mode 100644 ports/risc-v32/clang/src/tx_thread_context_save.S delete mode 100644 ports/risc-v32/clang/src/tx_thread_interrupt_control.S delete mode 100644 ports/risc-v32/clang/src/tx_thread_schedule.S delete mode 100644 ports/risc-v32/clang/src/tx_thread_stack_build.S delete mode 100644 ports/risc-v32/clang/src/tx_thread_system_return.S delete mode 100644 ports/risc-v32/clang/src/tx_timer_interrupt.S create mode 100644 ports/risc-v32/common/tx_port_riscv32_common.h create mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c rename ports/risc-v32/gnu/example_build/cva6_ariane/{entry.s => entry.S} (100%) mode change 100644 => 120000 ports/risc-v32/gnu/example_build/cva6_ariane/plic.c mode change 100644 => 120000 ports/risc-v32/gnu/example_build/cva6_ariane/plic.h mode change 100644 => 120000 ports/risc-v32/gnu/example_build/qemu_virt/csr.h rename ports/risc-v32/gnu/example_build/qemu_virt/{entry.s => entry.S} (100%) mode change 100644 => 120000 ports/risc-v32/gnu/example_build/qemu_virt/plic.c mode change 100644 => 120000 ports/risc-v32/gnu/example_build/qemu_virt/plic.h rename ports/risc-v32/gnu/example_build/qemu_virt/test/{azrtos_test_tx_gnu_riscv32_qemu.py => threadx_test_tx_gnu_riscv32_qemu.py} (100%) mode change 100644 => 120000 ports/risc-v32/gnu/example_build/qemu_virt/trap.c mode change 100644 => 120000 ports/risc-v32/gnu/example_build/qemu_virt/uart.c mode change 100644 => 120000 ports/risc-v32/gnu/example_build/qemu_virt/uart.h mode change 100644 => 120000 ports/risc-v64/gnu/example_build/qemu_virt/csr.h rename ports/risc-v64/gnu/example_build/qemu_virt/{entry.s => entry.S} (100%) mode change 100644 => 120000 ports/risc-v64/gnu/example_build/qemu_virt/plic.c mode change 100644 => 120000 ports/risc-v64/gnu/example_build/qemu_virt/plic.h create mode 100644 ports/risc-v64/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv64_qemu.py mode change 100644 => 120000 ports/risc-v64/gnu/example_build/qemu_virt/trap.c mode change 100644 => 120000 ports/risc-v64/gnu/example_build/qemu_virt/uart.c mode change 100644 => 120000 ports/risc-v64/gnu/example_build/qemu_virt/uart.h create mode 100644 ports/risc-v_common/example_build/plic/plic.c create mode 100644 ports/risc-v_common/example_build/plic/plic.h create mode 100644 ports/risc-v_common/example_build/trap/trap_qemu.c create mode 100644 ports/risc-v_common/example_build/uart/uart_qemu_ns16550.c create mode 100644 ports/risc-v_common/example_build/uart/uart_qemu_ns16550.h create mode 100644 ports/risc-v_common/inc/csr.h diff --git a/.github/workflows/regression_test.yml b/.github/workflows/regression_test.yml index 72e4198ba..ee5519fdb 100644 --- a/.github/workflows/regression_test.yml +++ b/.github/workflows/regression_test.yml @@ -41,23 +41,24 @@ jobs: cmake_path: ./test/smp/cmake result_affix: SMP skip_deploy: true - riscv: - permissions: - contents: read - issues: read - checks: write - pull-requests: write - pages: write - id-token: write - uses: ./.github/workflows/regression_template.yml - with: - install_script: ./scripts/install_riscv.sh - build_script: ./scripts/build_tx_riscv.sh - test_script: ./scripts/test_tx_riscv.sh - cmake_path: ./test/tx/cmake/riscv - result_affix: RISC-V - skip_deploy: true - skip_coverage: true + # riscv: disabled — re-enable when RISC-V CI is ready + # riscv: + # permissions: + # contents: read + # issues: read + # checks: write + # pull-requests: write + # pages: write + # id-token: write + # uses: ./.github/workflows/regression_template.yml + # with: + # install_script: ./scripts/install_riscv.sh + # build_script: ./scripts/build_tx_riscv.sh + # test_script: ./scripts/test_tx_riscv.sh + # cmake_path: ./test/tx/cmake/riscv + # result_affix: RISC-V + # skip_deploy: true + # skip_coverage: true deploy: permissions: contents: read @@ -66,7 +67,7 @@ jobs: pull-requests: write pages: write id-token: write - needs: [tx, smp, riscv] + needs: [tx, smp] uses: ./.github/workflows/regression_template.yml with: skip_test: true diff --git a/.gitignore b/.gitignore index 349eaddcf..47438c97a 100644 --- a/.gitignore +++ b/.gitignore @@ -23,3 +23,7 @@ CTestTestfile.cmake *.a *.htm + +# Local build artifacts +build_m7/ +.codex diff --git a/cmake/riscv64-gcc-rv32imc.cmake b/cmake/riscv64-gcc-rv32imc.cmake index 836ed1ce3..aa19b6245 100644 --- a/cmake/riscv64-gcc-rv32imc.cmake +++ b/cmake/riscv64-gcc-rv32imc.cmake @@ -15,8 +15,15 @@ # CMake toolchain file for CORE-V MCU (CV32E40P, RV32IMC) # -# Uses the riscv64-unknown-elf-gcc multi-lib toolchain (Ubuntu package -# gcc-riscv64-unknown-elf) to cross-compile for a 32-bit RISC-V target. +# Uses the riscv64-unknown-elf-gcc cross-compiler to produce rv32imc/ilp32 +# bare-metal firmware. The riscv-collab toolchain (installed to /opt/riscv by +# scripts/install_riscv.sh) is used by default. The Ubuntu package +# gcc-riscv64-unknown-elf also works and can be installed via install_deps.sh. +# +# Note: the riscv-collab toolchain is built without multilib, so it does not +# ship an rv32/ilp32 libgcc. The CORE-V MCU BSP provides a weak __clzsi2 +# fallback in bsp/clz.c to satisfy any __builtin_clz() calls without relying +# on libgcc. # # Target ISA : rv32imc_zicsr (integer, multiply, compressed, Zicsr) # ABI : ilp32 (32-bit int/long/ptr, no hardware FP) @@ -33,7 +40,12 @@ set(CFLAGS "${ARCH_FLAGS}") set(ASFLAGS "${ARCH_FLAGS}") set(LDFLAGS "${ARCH_FLAGS}") -# Toolchain binaries (riscv64-unknown-elf can target rv32 via multilib) +# Toolchain binaries: riscv64-unknown-elf-gcc cross-compiler. +# The riscv-collab toolchain (scripts/install_riscv.sh → /opt/riscv/bin) is the +# preferred choice. The Ubuntu package (gcc-riscv64-unknown-elf, install via +# install_deps.sh) is also supported. Both are searched via PATH so whichever +# comes first is used; ensure /opt/riscv/bin precedes /usr/bin if you want the +# riscv-collab toolchain. set(CMAKE_C_COMPILER riscv64-unknown-elf-gcc) set(CMAKE_CXX_COMPILER riscv64-unknown-elf-g++) set(AS riscv64-unknown-elf-as) diff --git a/cmake/threadx_riscv_port.cmake b/cmake/threadx_riscv_port.cmake new file mode 100644 index 000000000..99a995ace --- /dev/null +++ b/cmake/threadx_riscv_port.cmake @@ -0,0 +1,50 @@ +# threadx_riscv_port.cmake +# +# Helper function shared by the three RISC-V port CMakeLists files +# (risc-v32/gnu, risc-v32/clang, risc-v64/gnu). +# +# Usage: +# include(cmake/threadx_riscv_port.cmake) +# threadx_add_riscv_port(SRC_DIR +# INC_DIR +# [EXAMPLE_DIR ]) +# +# SRC_DIR — directory containing the 8 ThreadX .S port files. +# INC_DIR — directory containing tx_port.h (added as PUBLIC include). +# EXAMPLE_DIR — optional: if provided and contains a CMakeLists.txt, +# add_subdirectory() is called on it. + +function(threadx_add_riscv_port) + cmake_parse_arguments(RISCV "" "SRC_DIR;INC_DIR;EXAMPLE_DIR" "" ${ARGN}) + + if(NOT RISCV_SRC_DIR) + message(FATAL_ERROR "threadx_add_riscv_port: SRC_DIR is required") + endif() + if(NOT RISCV_INC_DIR) + message(FATAL_ERROR "threadx_add_riscv_port: INC_DIR is required") + endif() + + target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${RISCV_SRC_DIR}/tx_initialize_low_level.S + ${RISCV_SRC_DIR}/tx_thread_context_restore.S + ${RISCV_SRC_DIR}/tx_thread_context_save.S + ${RISCV_SRC_DIR}/tx_thread_interrupt_control.S + ${RISCV_SRC_DIR}/tx_thread_schedule.S + ${RISCV_SRC_DIR}/tx_thread_stack_build.S + ${RISCV_SRC_DIR}/tx_thread_system_return.S + ${RISCV_SRC_DIR}/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} + ) + + target_include_directories(${PROJECT_NAME} + PUBLIC + ${RISCV_INC_DIR} + ) + + if(RISCV_EXAMPLE_DIR AND + EXISTS ${RISCV_EXAMPLE_DIR}/CMakeLists.txt) + add_subdirectory(${RISCV_EXAMPLE_DIR}) + endif() +endfunction() diff --git a/ports/cortex_m33/gnu/CMakeLists.txt b/ports/cortex_m33/gnu/CMakeLists.txt index 5ad3b8e75..763a2696c 100644 --- a/ports/cortex_m33/gnu/CMakeLists.txt +++ b/ports/cortex_m33/gnu/CMakeLists.txt @@ -1,7 +1,8 @@ -target_sources(${PROJECT_NAME} PRIVATE +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c - ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S @@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} ) -target_include_directories(${PROJECT_NAME} PUBLIC - inc +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc ) diff --git a/ports/cortex_m33/gnu/example_build/sample_threadx.c b/ports/cortex_m33/gnu/example_build/sample_threadx.c new file mode 100644 index 000000000..13ffadbaa --- /dev/null +++ b/ports/cortex_m33/gnu/example_build/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m33/gnu/src/tx_initialize_low_level.S b/ports/cortex_m33/gnu/example_build/tx_initialize_low_level.S similarity index 100% rename from ports/cortex_m33/gnu/src/tx_initialize_low_level.S rename to ports/cortex_m33/gnu/example_build/tx_initialize_low_level.S diff --git a/ports/cortex_m55/gnu/CMakeLists.txt b/ports/cortex_m55/gnu/CMakeLists.txt index 5ad3b8e75..763a2696c 100644 --- a/ports/cortex_m55/gnu/CMakeLists.txt +++ b/ports/cortex_m55/gnu/CMakeLists.txt @@ -1,7 +1,8 @@ -target_sources(${PROJECT_NAME} PRIVATE +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c - ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S @@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} ) -target_include_directories(${PROJECT_NAME} PUBLIC - inc +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc ) diff --git a/ports/cortex_m55/gnu/example_build/sample_threadx.c b/ports/cortex_m55/gnu/example_build/sample_threadx.c new file mode 100644 index 000000000..13ffadbaa --- /dev/null +++ b/ports/cortex_m55/gnu/example_build/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m55/gnu/src/tx_initialize_low_level.S b/ports/cortex_m55/gnu/example_build/tx_initialize_low_level.S similarity index 100% rename from ports/cortex_m55/gnu/src/tx_initialize_low_level.S rename to ports/cortex_m55/gnu/example_build/tx_initialize_low_level.S diff --git a/ports/cortex_m85/gnu/CMakeLists.txt b/ports/cortex_m85/gnu/CMakeLists.txt index 5ad3b8e75..763a2696c 100644 --- a/ports/cortex_m85/gnu/CMakeLists.txt +++ b/ports/cortex_m85/gnu/CMakeLists.txt @@ -1,7 +1,8 @@ -target_sources(${PROJECT_NAME} PRIVATE +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c - ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S @@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} ) -target_include_directories(${PROJECT_NAME} PUBLIC - inc +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc ) diff --git a/ports/cortex_m85/gnu/example_build/sample_threadx.c b/ports/cortex_m85/gnu/example_build/sample_threadx.c new file mode 100644 index 000000000..13ffadbaa --- /dev/null +++ b/ports/cortex_m85/gnu/example_build/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m85/gnu/src/tx_initialize_low_level.S b/ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S similarity index 100% rename from ports/cortex_m85/gnu/src/tx_initialize_low_level.S rename to ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S diff --git a/ports/risc-v32/clang/CMakeLists.txt b/ports/risc-v32/clang/CMakeLists.txt index 9b7251031..beaa31aab 100644 --- a/ports/risc-v32/clang/CMakeLists.txt +++ b/ports/risc-v32/clang/CMakeLists.txt @@ -1,19 +1,11 @@ +# RISC-V32 Clang port. +# +# Clang and GNU use identical RISC-V assembly sources; this port +# compiles from gnu/src/ so fixes and features are shared automatically. +include(${CMAKE_CURRENT_LIST_DIR}/../../../cmake/threadx_riscv_port.cmake) -target_sources(${PROJECT_NAME} - PRIVATE - # {{BEGIN_TARGET_SOURCES}} - ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S - # {{END_TARGET_SOURCES}} -) - -target_include_directories(${PROJECT_NAME} - PUBLIC - ${CMAKE_CURRENT_LIST_DIR}/inc +threadx_add_riscv_port( + SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/../gnu/src + INC_DIR ${CMAKE_CURRENT_LIST_DIR}/inc + EXAMPLE_DIR ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt ) diff --git a/ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh b/ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh index a1b3cb887..cda0edbb9 100755 --- a/ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh +++ b/ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh @@ -8,7 +8,7 @@ mkdir -p build CC=clang-18 LD=ld.lld-18 -$CC -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/entry.obj -c entry.s +$CC -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/entry.obj -c entry.S $CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -D__ASSEMBLER__ -o build/tx_initialize_low_level.obj -c tx_initialize_low_level.S $CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/board.obj -c board.c $CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/hwtimer.obj -c hwtimer.c diff --git a/ports/risc-v32/clang/example_build/qemu_virt/csr.h b/ports/risc-v32/clang/example_build/qemu_virt/csr.h deleted file mode 100644 index ab335dccc..000000000 --- a/ports/risc-v32/clang/example_build/qemu_virt/csr.h +++ /dev/null @@ -1,343 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2026 Quintauris - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -#ifndef RISCV_CSR_H -#define RISCV_CSR_H - - -// Machine Status Register, mstatus -#define MSTATUS_MPP_MASK (3L << 11) // previous mode. -#define MSTATUS_MPP_M (3L << 11) -#define MSTATUS_MPP_S (1L << 11) -#define MSTATUS_MPP_U (0L << 11) -#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable. -#define MSTATUS_MPIE (1L << 7) -#define MSTATUS_FS (1L << 13) - -// Machine-mode Interrupt Enable -#define MIE_MTIE (1L << 7) -#define MIE_MSIE (1L << 3) -#define MIE_MEIE (1L << 11) -#define MIE_STIE (1L << 5) // supervisor timer -#define MIE_SSIE (1L << 1) -#define MIE_SEIE (1L << 9) - -// Supervisor Status Register, sstatus -#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User -#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable -#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable -#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable -#define SSTATUS_UIE (1L << 0) // User Interrupt Enable -#define SSTATUS_SPIE (1L << 5) -#define SSTATUS_UPIE (1L << 4) - -// Supervisor Interrupt Enable -#define SIE_SEIE (1L << 9) // external -#define SIE_STIE (1L << 5) // timer -#define SIE_SSIE (1L << 1) // software - -#ifndef __ASSEMBLER__ - -#include - -static inline uint32_t riscv_get_core() -{ - uint32_t x; - asm volatile("csrr %0, mhartid" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_mstatus() -{ - uint32_t x; - asm volatile("csrr %0, mstatus" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mstatus(uint32_t x) -{ - asm volatile("csrw mstatus, %0" : : "r" (x)); -} - -static inline void riscv_writ_mepc(uint32_t x) -{ - asm volatile("csrw mepc, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_sstatus() -{ - uint32_t x; - asm volatile("csrr %0, sstatus" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_sstatus(uint32_t x) -{ - asm volatile("csrw sstatus, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_sip() -{ - uint32_t x; - asm volatile("csrr %0, sip" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_sip(uint32_t x) -{ - asm volatile("csrw sip, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_sie() -{ - uint32_t x; - asm volatile("csrr %0, sie" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_sie(uint32_t x) -{ - asm volatile("csrw sie, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_mie() -{ - uint32_t x; - asm volatile("csrr %0, mie" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mie(uint32_t x) -{ - asm volatile("csrw mie, %0" : : "r" (x)); -} - -static inline void riscv_writ_sepc(uint32_t x) -{ - asm volatile("csrw sepc, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_sepc() -{ - uint32_t x; - asm volatile("csrr %0, sepc" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_medeleg() -{ - uint32_t x; - asm volatile("csrr %0, medeleg" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_medeleg(uint32_t x) -{ - asm volatile("csrw medeleg, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_mideleg() -{ - uint32_t x; - asm volatile("csrr %0, mideleg" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mideleg(uint32_t x) -{ - asm volatile("csrw mideleg, %0" : : "r" (x)); -} - -static inline void riscv_writ_stvec(uint32_t x) -{ - asm volatile("csrw stvec, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_stvec() -{ - uint32_t x; - asm volatile("csrr %0, stvec" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_stimecmp() -{ - uint32_t x; - asm volatile("csrr %0, 0x14d" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_stimecmp(uint32_t x) -{ - asm volatile("csrw 0x14d, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_menvcfg() -{ - uint32_t x; - asm volatile("csrr %0, 0x30a" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_menvcfg(uint32_t x) -{ - asm volatile("csrw 0x30a, %0" : : "r" (x)); -} - -static inline void riscv_writ_pmpcfg0(uint32_t x) -{ - asm volatile("csrw pmpcfg0, %0" : : "r" (x)); -} - -static inline void riscv_writ_pmpaddr0(uint32_t x) -{ - asm volatile("csrw pmpaddr0, %0" : : "r" (x)); -} - -static inline void riscv_writ_satp(uint32_t x) -{ - asm volatile("csrw satp, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_satp() -{ - uint32_t x; - asm volatile("csrr %0, satp" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_scause() -{ - uint32_t x; - asm volatile("csrr %0, scause" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_stval() -{ - uint32_t x; - asm volatile("csrr %0, stval" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mcounteren(uint32_t x) -{ - asm volatile("csrw mcounteren, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_mcounteren() -{ - uint32_t x; - asm volatile("csrr %0, mcounteren" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_time() -{ - uint32_t x; - asm volatile("csrr %0, time" : "=r" (x) ); - return x; -} - -static inline void riscv_sintr_on() -{ - uint32_t sstatus = riscv_get_sstatus(); - sstatus |= SSTATUS_SIE; - riscv_writ_sstatus(sstatus); -} - -static inline void riscv_sintr_off() -{ - uint32_t sstatus = riscv_get_sstatus(); - sstatus &= (~SSTATUS_SIE); - riscv_writ_sstatus(sstatus); -} - -static inline int riscv_sintr_get() -{ - uint32_t x = riscv_get_sstatus(); - return (x & SSTATUS_SIE) != 0; -} - -static inline void riscv_sintr_restore(int x) -{ - if(x) - riscv_sintr_on(); - else - riscv_sintr_off(); -} - -static inline void riscv_mintr_on() -{ - uint32_t mstatus = riscv_get_mstatus(); - mstatus |= MSTATUS_MIE; - riscv_writ_mstatus(mstatus); -} - -static inline void riscv_mintr_off() -{ - uint32_t mstatus = riscv_get_mstatus(); - mstatus &= (~MSTATUS_MIE); - riscv_writ_mstatus(mstatus); -} - -static inline int riscv_mintr_get() -{ - uint32_t x = riscv_get_mstatus(); - return (x & MSTATUS_MIE) != 0; -} - -static inline void riscv_mintr_restore(int x) -{ - if(x) - riscv_mintr_on(); - else - riscv_mintr_off(); -} - -static inline uint32_t riscv_get_sp() -{ - uint32_t x; - asm volatile("mv %0, sp" : "=r" (x) ); - return x; -} - -// read and write tp, the thread pointer, which xv6 uses to hold -// this core's hartid (core number), the index into cpus[]. -static inline uint32_t riscv_get_tp() -{ - uint32_t x; - asm volatile("mv %0, tp" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_tp(uint32_t x) -{ - asm volatile("mv tp, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_ra() -{ - uint32_t x; - asm volatile("mv %0, ra" : "=r" (x) ); - return x; -} - -// flush the TLB. -static inline void sfence_vma() -{ - // the zero, zero means flush all TLB entries. - asm volatile("sfence.vma zero, zero"); -} - -#endif // __ASSEMBLER__ - -#endif diff --git a/ports/risc-v32/clang/example_build/qemu_virt/csr.h b/ports/risc-v32/clang/example_build/qemu_virt/csr.h new file mode 120000 index 000000000..b5df6f125 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/csr.h @@ -0,0 +1 @@ +../../../../risc-v_common/inc/csr.h \ No newline at end of file diff --git a/ports/risc-v32/clang/example_build/qemu_virt/entry.s b/ports/risc-v32/clang/example_build/qemu_virt/entry.S similarity index 100% rename from ports/risc-v32/clang/example_build/qemu_virt/entry.s rename to ports/risc-v32/clang/example_build/qemu_virt/entry.S diff --git a/ports/risc-v32/clang/example_build/qemu_virt/plic.c b/ports/risc-v32/clang/example_build/qemu_virt/plic.c deleted file mode 100644 index 01e5c71a4..000000000 --- a/ports/risc-v32/clang/example_build/qemu_virt/plic.c +++ /dev/null @@ -1,72 +0,0 @@ -#include "plic.h" -#include -irq_callback callbacks[MAX_CALLBACK_NUM]; - -void plic_irq_enable(int irqno) -{ - int hart = riscv_get_core(); - *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno)); - return; -} - -void plic_irq_disable(int irqno) -{ - int hart = riscv_get_core(); - *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno))); - return; -} - -void plic_prio_set(int irqno, int prio) -{ - PLIC_SET_PRIO(irqno, prio); -} - -int plic_prio_get(int irqno) -{ - return PLIC_GET_PRIO(irqno); -} - -int plic_register_callback(int irqno, irq_callback callback) -{ - if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM)) - return -1; - callbacks[irqno] = callback; - return 0; -} - -int plic_unregister_callback(int irqno) -{ - return plic_register_callback(irqno, NULL); -} - -int plic_init(void) -{ - for(int i=0;i - -#define PLIC 0x0c000000L -#define PLIC_PRIORITY (PLIC + 0x0) -#define PLIC_PENDING (PLIC + 0x1000) -#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100) -#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100) -#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000) -#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000) -#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000) -#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000) -#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000) -#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000) - - -#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4)) -#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio)) - -#define MAX_CALLBACK_NUM 128 -typedef int (*irq_callback)(int irqno); - -void plic_irq_enable(int irqno); -void plic_irq_disable(int irqno); -int plic_prio_get(int irqno); -void plic_prio_set(int irqno, int prio); -int plic_register_callback(int irqno, irq_callback callback); -int plic_unregister_callback(int irqno); -int plic_init(void); -int plic_claim(void); -void plic_complete(int irqno); - -int plic_irq_intr(void); - -#endif - diff --git a/ports/risc-v32/clang/example_build/qemu_virt/plic.h b/ports/risc-v32/clang/example_build/qemu_virt/plic.h new file mode 120000 index 000000000..f776a3d2a --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/plic.h @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/plic/plic.h \ No newline at end of file diff --git a/ports/risc-v32/clang/example_build/qemu_virt/trap.c b/ports/risc-v32/clang/example_build/qemu_virt/trap.c deleted file mode 100644 index a2733e02a..000000000 --- a/ports/risc-v32/clang/example_build/qemu_virt/trap.c +++ /dev/null @@ -1,67 +0,0 @@ -#include "csr.h" -#include -#include "uart.h" -#include "hwtimer.h" -#include "plic.h" -#include -#include - -#define OS_IS_INTERUPT(mcause) (mcause & 0x80000000u) -#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT)) -#define OS_IS_TICK_INT(mcause) (mcause == 0x80000007u) -#define OS_IS_SOFT_INT(mcause) (mcause == 0x80000003u) -#define OS_IS_EXT_INT(mcause) (mcause == 0x8000000bu) -#define OS_IS_TRAP_USER(mcause) (mcause == 0x0000000bu) -extern void _tx_timer_interrupt(void); - -extern int uart_putc(int ch); - -static void print_hex(uintptr_t val) -{ - char digits[] = "0123456789ABCDEF"; - uart_putc('0'); - uart_putc('x'); - for(int i = (sizeof(uintptr_t)*2) - 1; i >= 0; i--) { - int d = (val >> (i*4)) & 0xF; - uart_putc(digits[d]); - } - uart_putc('\n'); -} - -void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) -{ - // uart_puts("DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/trap.c, trap_handler\n"); - if(OS_IS_INTERUPT(mcause)) - { - if(OS_IS_TICK_INT(mcause)) - { - hwtimer_handler(); - _tx_timer_interrupt(); - } - else if(OS_IS_EXT_INT(mcause)) - { - int ret = plic_irq_intr(); - if(ret) - { - puts("[INTERRUPT]: handler irq error!"); - while(1) ; - } - } - else - { - puts("[INTERRUPT]: now can't deal with the interrupt!"); - while(1) ; - } - } - else - { - puts("[EXCEPTION] : Unkown Error!!"); - puts("mcause:"); - print_hex(mcause); - puts("mepc:"); - print_hex(mepc); - puts("mtval:"); - print_hex(mtval); - while(1) ; - } -} diff --git a/ports/risc-v32/clang/example_build/qemu_virt/trap.c b/ports/risc-v32/clang/example_build/qemu_virt/trap.c new file mode 120000 index 000000000..bdce33054 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/trap.c @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/trap/trap_qemu.c \ No newline at end of file diff --git a/ports/risc-v32/clang/example_build/qemu_virt/uart.c b/ports/risc-v32/clang/example_build/qemu_virt/uart.c deleted file mode 100644 index a175b7d25..000000000 --- a/ports/risc-v32/clang/example_build/qemu_virt/uart.c +++ /dev/null @@ -1,102 +0,0 @@ -#include "uart.h" -#include "csr.h" -#include "plic.h" -#include - -// the UART control registers are memory-mapped -// at address UART0. this macro returns the -// address of one of the registers. -#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg))) - -// the UART control registers. -// some have different meanings for -// read vs write. -// see http://byterunner.com/16550.html -#define RHR 0 // receive holding register (for input bytes) -#define THR 0 // transmit holding register (for output bytes) -#define IER 1 // interrupt enable register -#define IER_RX_ENABLE (1<<0) -#define IER_TX_ENABLE (1<<1) -#define FCR 2 // FIFO control register -#define FCR_FIFO_ENABLE (1<<0) -#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs -#define ISR 2 // interrupt status register -#define LCR 3 // line control register -#define LCR_EIGHT_BITS (3<<0) -#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate -#define LSR 5 // line status register -#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR -#define LSR_TX_IDLE (1<<5) // THR can accept another character to send - -#define ReadReg(reg) (*(Reg(reg))) -#define WriteReg(reg, v) (*(Reg(reg)) = (v)) - -int uart_init(void) -{ - // disable interrupts. - WriteReg(IER, 0x00); - - // special mode to set baud rate. - WriteReg(LCR, LCR_BAUD_LATCH); - - // LSB for baud rate of 38.4K. - WriteReg(0, 0x03); - - // MSB for baud rate of 38.4K. - WriteReg(1, 0x00); - - // leave set-baud mode, - // and set word length to 8 bits, no parity. - WriteReg(LCR, LCR_EIGHT_BITS); - - // reset and enable FIFOs. - WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR); - - // enable transmit and receive interrupts. - // WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE); - - //enable UART0 in PLIC - plic_irq_enable(UART0_IRQ); - - //set UART0 priority in PLIC - plic_prio_set(UART0_IRQ, 1); - - //register callback for UART0 - //plic_register_callback(UART0_IRQ, uart_intr); - puts("[UART0] : Uart Init Done, this is Test output!"); - return 0; -} - -void uart_putc_nolock(int ch) -{ - // wait for Transmit Holding Empty to be set in LSR. - while((ReadReg(LSR) & LSR_TX_IDLE) == 0) - ; - WriteReg(THR, ch); - return; -} - -int uart_putc(int ch) -{ - int intr_enable = riscv_mintr_get(); - riscv_mintr_off(); - uart_putc_nolock(ch); - riscv_mintr_restore(intr_enable); - return 1; -} - -int uart_puts(const char* str) -{ - int i; - int intr_enable = riscv_mintr_get(); - riscv_mintr_off(); - for(i=0;str[i]!=0;i++) - { - uart_putc_nolock(str[i]); - } - uart_putc_nolock('\n'); - riscv_mintr_restore(intr_enable); - return i; -} - - diff --git a/ports/risc-v32/clang/example_build/qemu_virt/uart.c b/ports/risc-v32/clang/example_build/qemu_virt/uart.c new file mode 120000 index 000000000..1666c8c8d --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/uart.c @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.c \ No newline at end of file diff --git a/ports/risc-v32/clang/example_build/qemu_virt/uart.h b/ports/risc-v32/clang/example_build/qemu_virt/uart.h deleted file mode 100644 index debfd9dfa..000000000 --- a/ports/risc-v32/clang/example_build/qemu_virt/uart.h +++ /dev/null @@ -1,23 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - -#ifndef RISCV_UART_H -#define RISCV_UART_H - -#define UART0 0x10000000L -#define UART0_IRQ 10 - -#define puts uart_puts -int uart_init(void); -int uart_putc(int ch); -void uart_putc_nolock(int ch); -int uart_puts(const char* str); -#endif diff --git a/ports/risc-v32/clang/example_build/qemu_virt/uart.h b/ports/risc-v32/clang/example_build/qemu_virt/uart.h new file mode 120000 index 000000000..aba5ae7b9 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/uart.h @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.h \ No newline at end of file diff --git a/ports/risc-v32/clang/inc/tx_port.h b/ports/risc-v32/clang/inc/tx_port.h index f89c148c0..95995032c 100644 --- a/ports/risc-v32/clang/inc/tx_port.h +++ b/ports/risc-v32/clang/inc/tx_port.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (c) 2025 Quintauris + * Copyright (c) 2026 Quintauris * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -24,7 +24,7 @@ /* */ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ -/* tx_port.h RISC-V32/GNU */ +/* tx_port.h RISC-V32/Clang */ /* 6.4.x */ /* */ /* AUTHOR */ @@ -47,228 +47,8 @@ #ifndef TX_PORT_H #define TX_PORT_H -#ifndef __ASSEMBLER__ - -/* Include for memset. */ -#include - - -/* Determine if the optional ThreadX user define file should be used. */ - -#ifdef TX_INCLUDE_USER_DEFINE_FILE - - -/* Yes, include the user defines in tx_user.h. The defines in this file may - alternately be defined on the command line. */ - -#include "tx_user.h" -#endif /* TX_INCLUDE_USER_DEFINE_FILE */ - -#endif /* __ASSEMBLER__ */ - - -/* Define ThreadX basic types for this port. */ - -#define VOID void - -#ifndef __ASSEMBLER__ -typedef char CHAR; -typedef unsigned char UCHAR; -typedef int INT; -typedef unsigned int UINT; -typedef long LONG; -typedef unsigned long ULONG; -typedef unsigned long long ULONG64; -typedef short SHORT; -typedef unsigned short USHORT; -#define ULONG64_DEFINED -#endif /* __ASSEMBLER__ */ - - - - -/* Define the priority levels for ThreadX. Legal values range - from 32 to 1024 and MUST be evenly divisible by 32. */ - -#ifndef TX_MAX_PRIORITIES -#define TX_MAX_PRIORITIES 32 -#endif - - -/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during - thread creation is less than this value, the thread create call will return an error. */ - -#ifndef TX_MINIMUM_STACK -#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ -#endif - - -/* Define the system timer thread's default stack size and priority. These are only applicable - if TX_TIMER_PROCESS_IN_ISR is not defined. */ - -#ifndef TX_TIMER_THREAD_STACK_SIZE -#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ -#endif - -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ -#endif - - -/* Define various constants for the ThreadX RISC-V port. */ - -#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ -#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ - - -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock - source constants would be: - -#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) -#define TX_TRACE_TIME_MASK 0x0000FFFFUL - -*/ - -#ifndef TX_TRACE_TIME_SOURCE -#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time -#endif -#ifndef TX_TRACE_TIME_MASK -#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL -#endif - - -/* Define the port specific options for the _tx_build_options variable. This variable indicates - how the ThreadX library was built. */ - -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 - - -/* Define the in-line initialization constant so that modules with in-line - initialization capabilities can prevent their initialization from being - a function call. */ - -#define TX_INLINE_INITIALIZATION - - -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is - disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack - checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING - define is negated, thereby forcing the stack fill which is necessary for the stack checking - logic. */ - -#ifdef TX_ENABLE_STACK_CHECKING -#undef TX_DISABLE_STACK_FILLING -#endif - - -/* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with - existing ThreadX kernel awareness modules. */ - -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 - - -/* Define the port extensions of the remaining ThreadX objects. */ - -#define TX_BLOCK_POOL_EXTENSION -#define TX_BYTE_POOL_EXTENSION -#define TX_EVENT_FLAGS_GROUP_EXTENSION -#define TX_MUTEX_EXTENSION -#define TX_QUEUE_EXTENSION -#define TX_SEMAPHORE_EXTENSION -#define TX_TIMER_EXTENSION - - -/* Define the user extension field of the thread control block. Nothing - additional is needed for this port so it is defined as white space. */ - -#ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION -#endif - - -/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, - tx_thread_shell_entry, and tx_thread_terminate. */ - -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) -#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) - - -/* Define the ThreadX object creation extensions for the remaining objects. */ - -#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) -#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) -#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) -#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) -#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) -#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) -#define TX_TIMER_CREATE_EXTENSION(timer_ptr) - - -/* Define the ThreadX object deletion extensions for the remaining objects. */ - -#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) -#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) -#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) -#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) -#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) -#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) -#define TX_TIMER_DELETE_EXTENSION(timer_ptr) - - -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value - present prior to the disable macro. In most cases, the save area macro - is used to define a local function save area for the disable and restore - macros. */ - -/* Expose helper used to perform an atomic read/modify/write of mstatus. - The helper composes and returns the posture per ThreadX contract. */ -#ifndef __ASSEMBLER__ -UINT _tx_thread_interrupt_control(UINT new_posture); -#endif - -#ifdef TX_DISABLE_INLINE - -#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; - -#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory"); -#define TX_RESTORE { \ - unsigned long _temp_mstatus; \ - __asm__ volatile( \ - "csrc mstatus, 8\n" \ - "andi %0, %1, 8\n" \ - "csrs mstatus, %0" \ - : "=&r" (_temp_mstatus) \ - : "r" (interrupt_save) \ - : "memory"); \ - } - -#else - -#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; - -#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); -#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); - -#endif /* TX_DISABLE_INLINE */ - - -/* Define the interrupt lockout macros for each ThreadX object. */ - -#define TX_BLOCK_POOL_DISABLE TX_DISABLE -#define TX_BYTE_POOL_DISABLE TX_DISABLE -#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE -#define TX_MUTEX_DISABLE TX_DISABLE -#define TX_QUEUE_DISABLE TX_DISABLE -#define TX_SEMAPHORE_DISABLE TX_DISABLE +/* Include shared RISC-V32 port definitions common to all toolchain ports. */ +#include "../../common/tx_port_riscv32_common.h" /* Define the version ID of ThreadX. This may be utilized by the application. */ @@ -282,4 +62,4 @@ extern CHAR _tx_version_id[]; #endif /* TX_THREAD_INIT */ #endif /* __ASSEMBLER__ */ -#endif /* TX_PORT_H */ \ No newline at end of file +#endif /* TX_PORT_H */ diff --git a/ports/risc-v32/clang/src/tx_initialize_low_level.S b/ports/risc-v32/clang/src/tx_initialize_low_level.S deleted file mode 100644 index 467c37355..000000000 --- a/ports/risc-v32/clang/src/tx_initialize_low_level.S +++ /dev/null @@ -1,112 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2026 Quintauris - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Initialize */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .section .data - .global __tx_free_memory_start -__tx_free_memory_start: - - - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level RISC-V32/GNU */ -/* 6.4.x */ -/* AUTHOR */ -/* */ -/* Francisco Merino, Quintauris */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/**************************************************************************/ -/* VOID _tx_initialize_low_level(VOID) -{ */ -// .global _tx_initialize_low_level - .weak _tx_initialize_low_level -_tx_initialize_low_level: - - /* Save the system stack pointer. */ - /* _tx_thread_system_stack_ptr = sp; */ - - la t0, _tx_thread_system_stack_ptr // Pickup address of system stack ptr - sw sp, 0(t0) // Save system stack pointer - - /* Pickup first free address. */ - /* _tx_initialize_unused_memory(__tx_free_memory_start); */ - - la t0, __tx_free_memory_start // Pickup first free address - la t1, _tx_initialize_unused_memory // Pickup address of unused memory - sw t0, 0(t1) // Save unused memory address - - /* Initialize floating point control/status register if floating point is enabled. */ -#ifdef __riscv_flen - li t0, 0 - csrw fcsr, t0 // Clear FP control/status register -#endif - - ret - -/* Timer Interrupt Handler Note: - Platform-specific implementations must provide their own timer ISR. - The timer interrupt handler should follow this execution flow: - - 1. Disable interrupts (if not done by hardware exception entry) - 2. Allocate interrupt stack frame (65*4 bytes with FP, 32*4 bytes without) - 3. Save RA (x1) on the stack at offset 28*4 - 4. Call _tx_thread_context_save to save thread context - 5. Call _tx_timer_interrupt to process the timer tick - 6. Call _tx_thread_context_restore to resume execution (does not return) - - Example (for CLINT timer): - - _tx_timer_interrupt_handler: - addi sp, sp, -32*4 - sw ra, 28*4(sp) - call _tx_thread_context_save - call _tx_timer_interrupt - j _tx_thread_context_restore - - The port assumes Machine mode (M-mode) execution. - For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus. - See the RISC-V Privileged Specification for more details. */ \ No newline at end of file diff --git a/ports/risc-v32/clang/src/tx_thread_context_restore.S b/ports/risc-v32/clang/src/tx_thread_context_restore.S deleted file mode 100644 index 88ac0ce34..000000000 --- a/ports/risc-v32/clang/src/tx_thread_context_restore.S +++ /dev/null @@ -1,410 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2025 Quintauris - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_restore RISC-V32/GNU */ -/* 6.4.x */ -/* AUTHOR */ -/* */ -/* Francisco Merino, Quintauris */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_schedule Thread scheduling routine */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs Interrupt Service Routines */ -/* */ -/**************************************************************************/ -/* VOID _tx_thread_context_restore(VOID) -{ */ - .global _tx_thread_context_restore -_tx_thread_context_restore: - - /* Lockout interrupts. */ - - csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_isr_exit // Call the ISR execution exit function -#endif - - /* Determine if interrupts are nested. */ - /* if (--_tx_thread_system_state) - { */ - - la t0, _tx_thread_system_state // Pickup addr of nested interrupt count - lw t1, 0(t0) // Pickup nested interrupt count - addi t1, t1, -1 // Decrement the nested interrupt counter - sw t1, 0(t0) // Store new nested count - beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore - - /* Interrupts are nested. */ - - /* Just recover the saved registers and return to the point of - interrupt. */ - - /* Recover floating point registers. */ -#if defined(__riscv_float_abi_single) - flw f0, 31*4(sp) // Recover ft0 - flw f1, 32*4(sp) // Recover ft1 - flw f2, 33*4(sp) // Recover ft2 - flw f3, 34*4(sp) // Recover ft3 - flw f4, 35*4(sp) // Recover ft4 - flw f5, 36*4(sp) // Recover ft5 - flw f6, 37*4(sp) // Recover ft6 - flw f7, 38*4(sp) // Recover ft7 - flw f10, 41*4(sp) // Recover fa0 - flw f11, 42*4(sp) // Recover fa1 - flw f12, 43*4(sp) // Recover fa2 - flw f13, 44*4(sp) // Recover fa3 - flw f14, 45*4(sp) // Recover fa4 - flw f15, 46*4(sp) // Recover fa5 - flw f16, 47*4(sp) // Recover fa6 - flw f17, 48*4(sp) // Recover fa7 - flw f28, 59*4(sp) // Recover ft8 - flw f29, 60*4(sp) // Recover ft9 - flw f30, 61*4(sp) // Recover ft10 - flw f31, 62*4(sp) // Recover ft11 - lw t0, 63*4(sp) // Recover fcsr - csrw fcsr, t0 // Restore fcsr -#elif defined(__riscv_float_abi_double) - fld f0, 31*4(sp) // Recover ft0 - fld f1, 32*4(sp) // Recover ft1 - fld f2, 33*4(sp) // Recover ft2 - fld f3, 34*4(sp) // Recover ft3 - fld f4, 35*4(sp) // Recover ft4 - fld f5, 36*4(sp) // Recover ft5 - fld f6, 37*4(sp) // Recover ft6 - fld f7, 38*4(sp) // Recover ft7 - fld f10, 41*4(sp) // Recover fa0 - fld f11, 42*4(sp) // Recover fa1 - fld f12, 43*4(sp) // Recover fa2 - fld f13, 44*4(sp) // Recover fa3 - fld f14, 45*4(sp) // Recover fa4 - fld f15, 46*4(sp) // Recover fa5 - fld f16, 47*4(sp) // Recover fa6 - fld f17, 48*4(sp) // Recover fa7 - fld f28, 59*4(sp) // Recover ft8 - fld f29, 60*4(sp) // Recover ft9 - fld f30, 61*4(sp) // Recover ft10 - fld f31, 62*4(sp) // Recover ft11 - lw t0, 63*4(sp) // Recover fcsr - csrw fcsr, t0 // Restore fcsr -#endif - - /* Recover standard registers. */ - - /* Restore registers, - Skip global pointer because that does not change. - Also skip the saved registers since they have been restored by any function we called, - except s0 since we use it ourselves. */ - - lw t0, 30*4(sp) // Recover mepc - csrw mepc, t0 // Setup mepc - - /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. - Set MPIE and restore MPP to Machine, preserve other fields. */ - - csrr t1, mstatus - - /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ - - li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) - - /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, - preserve everything except the bits we will modify. */ - - li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE - and t1, t1, t4 - or t1, t1, t3 - -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state - or t1, t1, t0 -#endif - csrw mstatus, t1 // Update mstatus safely - - lw ra, 28*4(sp) // Recover return address - lw t0, 19*4(sp) // Recover t0 - lw t1, 18*4(sp) // Recover t1 - lw t2, 17*4(sp) // Recover t2 - lw s0, 12*4(sp) // Recover s0 - lw a0, 27*4(sp) // Recover a0 - lw a1, 26*4(sp) // Recover a1 - lw a2, 25*4(sp) // Recover a2 - lw a3, 24*4(sp) // Recover a3 - lw a4, 23*4(sp) // Recover a4 - lw a5, 22*4(sp) // Recover a5 - lw a6, 21*4(sp) // Recover a6 - lw a7, 20*4(sp) // Recover a7 - lw t3, 16*4(sp) // Recover t3 - lw t4, 15*4(sp) // Recover t4 - lw t5, 14*4(sp) // Recover t5 - lw t6, 13*4(sp) // Recover t6 - -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*4 // Recover stack frame - with floating point enabled -#else - addi sp, sp, 32*4 // Recover stack frame - without floating point enabled -#endif - mret // Return to point of interrupt - - /* } */ -_tx_thread_not_nested_restore: - /* Determine if a thread was interrupted and no preemption is required. */ - /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) - || (_tx_thread_preempt_disable)) - { */ - - la t0, _tx_thread_current_ptr // Pickup current thread pointer address - lw t1, 0(t0) // Pickup current thread pointer - - beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore - - - la t0, _tx_thread_preempt_disable // Pickup preempt disable flag address - lw t2, 0(t0) // Pickup preempt disable flag (UINT) - - bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread - - - la t0, _tx_thread_execute_ptr // Pickup thread execute pointer address - lw t2, 0(t0) // Pickup thread execute pointer - - bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt - - -_tx_thread_no_preempt_restore: - /* Restore interrupted thread or ISR. */ - - /* Pickup the saved stack pointer. */ - /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ - - lw sp, 8(t1) // Switch back to thread's stack - - /* Recover floating point registers. */ -#if defined(__riscv_float_abi_single) - flw f0, 31*4(sp) // Recover ft0 - flw f1, 32*4(sp) // Recover ft1 - flw f2, 33*4(sp) // Recover ft2 - flw f3, 34*4(sp) // Recover ft3 - flw f4, 35*4(sp) // Recover ft4 - flw f5, 36*4(sp) // Recover ft5 - flw f6, 37*4(sp) // Recover ft6 - flw f7, 38*4(sp) // Recover ft7 - flw f10, 41*4(sp) // Recover fa0 - flw f11, 42*4(sp) // Recover fa1 - flw f12, 43*4(sp) // Recover fa2 - flw f13, 44*4(sp) // Recover fa3 - flw f14, 45*4(sp) // Recover fa4 - flw f15, 46*4(sp) // Recover fa5 - flw f16, 47*4(sp) // Recover fa6 - flw f17, 48*4(sp) // Recover fa7 - flw f28, 59*4(sp) // Recover ft8 - flw f29, 60*4(sp) // Recover ft9 - flw f30, 61*4(sp) // Recover ft10 - flw f31, 62*4(sp) // Recover ft11 - lw t0, 63*4(sp) // Recover fcsr - csrw fcsr, t0 // Restore fcsr -#elif defined(__riscv_float_abi_double) - fld f0, 31*4(sp) // Recover ft0 - fld f1, 32*4(sp) // Recover ft1 - fld f2, 33*4(sp) // Recover ft2 - fld f3, 34*4(sp) // Recover ft3 - fld f4, 35*4(sp) // Recover ft4 - fld f5, 36*4(sp) // Recover ft5 - fld f6, 37*4(sp) // Recover ft6 - fld f7, 38*4(sp) // Recover ft7 - fld f10, 41*4(sp) // Recover fa0 - fld f11, 42*4(sp) // Recover fa1 - fld f12, 43*4(sp) // Recover fa2 - fld f13, 44*4(sp) // Recover fa3 - fld f14, 45*4(sp) // Recover fa4 - fld f15, 46*4(sp) // Recover fa5 - fld f16, 47*4(sp) // Recover fa6 - fld f17, 48*4(sp) // Recover fa7 - fld f28, 59*4(sp) // Recover ft8 - fld f29, 60*4(sp) // Recover ft9 - fld f30, 61*4(sp) // Recover ft10 - fld f31, 62*4(sp) // Recover ft11 - lw t0, 63*4(sp) // Recover fcsr - csrw fcsr, t0 // Restore fcsr -#endif - - /* Recover the saved context and return to the point of interrupt. */ - - /* Recover standard registers. */ - /* Restore registers, - Skip global pointer because that does not change */ - - lw t0, 30*4(sp) // Recover mepc - csrw mepc, t0 // Setup mepc - - /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */ - - csrr t1, mstatus - li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode - li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE - and t1, t1, t4 - or t1, t1, t3 - -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t0, 0x2000 // Set FS bits for FP state - or t1, t1, t0 -#endif - csrw mstatus, t1 // Update mstatus safely - - lw ra, 28*4(sp) // Recover return address - lw t0, 19*4(sp) // Recover t0 - lw t1, 18*4(sp) // Recover t1 - lw t2, 17*4(sp) // Recover t2 - lw s0, 12*4(sp) // Recover s0 - lw a0, 27*4(sp) // Recover a0 - lw a1, 26*4(sp) // Recover a1 - lw a2, 25*4(sp) // Recover a2 - lw a3, 24*4(sp) // Recover a3 - lw a4, 23*4(sp) // Recover a4 - lw a5, 22*4(sp) // Recover a5 - lw a6, 21*4(sp) // Recover a6 - lw a7, 20*4(sp) // Recover a7 - lw t3, 16*4(sp) // Recover t3 - lw t4, 15*4(sp) // Recover t4 - lw t5, 14*4(sp) // Recover t5 - lw t6, 13*4(sp) // Recover t6 - -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*4 // Recover stack frame - with floating point enabled -#else - addi sp, sp, 32*4 // Recover stack frame - without floating point enabled -#endif - mret // Return to point of interrupt - - /* } - else - { */ -_tx_thread_preempt_restore: - /* Instead of directly activating the thread again, ensure we save the - entire stack frame by saving the remaining registers. */ - - lw t0, 8(t1) // Pickup thread's stack pointer - ori t3, zero, 1 // Build interrupt stack type - sw t3, 0(t0) // Store stack type - - /* Store floating point preserved registers. */ -#ifdef __riscv_float_abi_single - fsw f8, 39*4(t0) // Store fs0 - fsw f9, 40*4(t0) // Store fs1 - fsw f18, 49*4(t0) // Store fs2 - fsw f19, 50*4(t0) // Store fs3 - fsw f20, 51*4(t0) // Store fs4 - fsw f21, 52*4(t0) // Store fs5 - fsw f22, 53*4(t0) // Store fs6 - fsw f23, 54*4(t0) // Store fs7 - fsw f24, 55*4(t0) // Store fs8 - fsw f25, 56*4(t0) // Store fs9 - fsw f26, 57*4(t0) // Store fs10 - fsw f27, 58*4(t0) // Store fs11 -#elif defined(__riscv_float_abi_double) - fsd f8, 39*4(t0) // Store fs0 - fsd f9, 40*4(t0) // Store fs1 - fsd f18, 49*4(t0) // Store fs2 - fsd f19, 50*4(t0) // Store fs3 - fsd f20, 51*4(t0) // Store fs4 - fsd f21, 52*4(t0) // Store fs5 - fsd f22, 53*4(t0) // Store fs6 - fsd f23, 54*4(t0) // Store fs7 - fsd f24, 55*4(t0) // Store fs8 - fsd f25, 56*4(t0) // Store fs9 - fsd f26, 57*4(t0) // Store fs10 - fsd f27, 58*4(t0) // Store fs11 -#endif - - /* Store standard preserved registers. */ - - sw x9, 11*4(t0) // Store s1 - sw x18, 10*4(t0) // Store s2 - sw x19, 9*4(t0) // Store s3 - sw x20, 8*4(t0) // Store s4 - sw x21, 7*4(t0) // Store s5 - sw x22, 6*4(t0) // Store s6 - sw x23, 5*4(t0) // Store s7 - sw x24, 4*4(t0) // Store s8 - sw x25, 3*4(t0) // Store s9 - sw x26, 2*4(t0) // Store s10 - sw x27, 1*4(t0) // Store s11 - // Note: s0 is already stored! - - /* Save the remaining time-slice and disable it. */ - /* if (_tx_timer_time_slice) - { */ - - la t0, _tx_timer_time_slice // Pickup time slice variable address - lw t2, 0(t0) // Pickup time slice - beqz t2, _tx_thread_dont_save_ts // If 0, skip time slice processing - - /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice - _tx_timer_time_slice = 0; */ - - sw t2, 24(t1) // Save current time slice - sw x0, 0(t0) // Clear global time slice - - - /* } */ -_tx_thread_dont_save_ts: - /* Clear the current task pointer. */ - /* _tx_thread_current_ptr = TX_NULL; */ - - /* Return to the scheduler. */ - /* _tx_thread_schedule(); */ - - la t0, _tx_thread_current_ptr // Pickup current thread pointer address - sw x0, 0(t0) // Clear current thread pointer - - /* } */ - -_tx_thread_idle_system_restore: - /* Just return back to the scheduler! */ - j _tx_thread_schedule // Return to scheduler - -/* } */ diff --git a/ports/risc-v32/clang/src/tx_thread_context_save.S b/ports/risc-v32/clang/src/tx_thread_context_save.S deleted file mode 100644 index ffb302e36..000000000 --- a/ports/risc-v32/clang/src/tx_thread_context_save.S +++ /dev/null @@ -1,271 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2026 Quintauris - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_save RISC-V32/GNU */ -/* 6.4.x */ -/* AUTHOR */ -/* */ -/* Francisco Merino, Quintauris */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs */ -/* */ -/**************************************************************************/ -/* VOID _tx_thread_context_save(VOID) -{ */ - .global _tx_thread_context_save -_tx_thread_context_save: - - /* Upon entry to this routine, RA/x1 has been saved on the stack - and the stack has been already allocated for the entire context: - addi sp, sp, -32*4 (or -65*4) - sw ra, 28*4(sp) - */ - - sw t0, 19*4(sp) // Store t0 - sw t1, 18*4(sp) // Store t1 - - /* Check for a nested interrupt. */ - /* if (_tx_thread_system_state++) - { */ - - la t0, _tx_thread_system_state // Pickup addr of system state var - lw t1, 0(t0) // Pickup system state - addi t1, t1, 1 // Increment system state - sw t1, 0(t0) // Store system state - li t0, 1 - bgt t1, t0, _tx_thread_nested_save // If it's more than 1, nested interrupt - - /* First level interrupt, save the rest of the scratch registers and - check for a thread to preempt. */ - - sw t2, 17*4(sp) // Store t2 - sw s0, 12*4(sp) // Store s0 - sw a0, 27*4(sp) // Store a0 - sw a1, 26*4(sp) // Store a1 - sw a2, 25*4(sp) // Store a2 - sw a3, 24*4(sp) // Store a3 - sw a4, 23*4(sp) // Store a4 - sw a5, 22*4(sp) // Store a5 - sw a6, 21*4(sp) // Store a6 - sw a7, 20*4(sp) // Store a7 - sw t3, 16*4(sp) // Store t3 - sw t4, 15*4(sp) // Store t4 - sw t5, 14*4(sp) // Store t5 - sw t6, 13*4(sp) // Store t6 - - /* Save floating point registers. */ -#if defined(__riscv_float_abi_single) - fsw f0, 31*4(sp) // Store ft0 - fsw f1, 32*4(sp) // Store ft1 - fsw f2, 33*4(sp) // Store ft2 - fsw f3, 34*4(sp) // Store ft3 - fsw f4, 35*4(sp) // Store ft4 - fsw f5, 36*4(sp) // Store ft5 - fsw f6, 37*4(sp) // Store ft6 - fsw f7, 38*4(sp) // Store ft7 - fsw f10, 41*4(sp) // Store fa0 - fsw f11, 42*4(sp) // Store fa1 - fsw f12, 43*4(sp) // Store fa2 - fsw f13, 44*4(sp) // Store fa3 - fsw f14, 45*4(sp) // Store fa4 - fsw f15, 46*4(sp) // Store fa5 - fsw f16, 47*4(sp) // Store fa6 - fsw f17, 48*4(sp) // Store fa7 - fsw f28, 59*4(sp) // Store ft8 - fsw f29, 60*4(sp) // Store ft9 - fsw f30, 61*4(sp) // Store ft10 - fsw f31, 62*4(sp) // Store ft11 - csrr t0, fcsr - sw t0, 63*4(sp) // Store fcsr -#elif defined(__riscv_float_abi_double) - fsd f0, 31*4(sp) // Store ft0 - fsd f1, 32*4(sp) // Store ft1 - fsd f2, 33*4(sp) // Store ft2 - fsd f3, 34*4(sp) // Store ft3 - fsd f4, 35*4(sp) // Store ft4 - fsd f5, 36*4(sp) // Store ft5 - fsd f6, 37*4(sp) // Store ft6 - fsd f7, 38*4(sp) // Store ft7 - fsd f10, 41*4(sp) // Store fa0 - fsd f11, 42*4(sp) // Store fa1 - fsd f12, 43*4(sp) // Store fa2 - fsd f13, 44*4(sp) // Store fa3 - fsd f14, 45*4(sp) // Store fa4 - fsd f15, 46*4(sp) // Store fa5 - fsd f16, 47*4(sp) // Store fa6 - fsd f17, 48*4(sp) // Store fa7 - fsd f28, 59*4(sp) // Store ft8 - fsd f29, 60*4(sp) // Store ft9 - fsd f30, 61*4(sp) // Store ft10 - fsd f31, 62*4(sp) // Store ft11 - csrr t0, fcsr - sw t0, 63*4(sp) // Store fcsr -#endif - - csrr t0, mepc - sw t0, 30*4(sp) // Save it on the stack - - /* Save mstatus. */ - csrr t0, mstatus - sw t0, 29*4(sp) - - la t1, _tx_thread_current_ptr // Pickup address of current thread ptr - lw t2, 0(t1) // Pickup current thread pointer - beqz t2, _tx_thread_idle_system_save // If NULL, idle system was interrupted - - /* Save the current thread's stack pointer and switch to the system stack. */ - /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; - sp = _tx_thread_system_stack_ptr; */ - - sw sp, 8(t2) // Save stack pointer - la t0, _tx_thread_system_stack_ptr - lw sp, 0(t0) // Switch to system stack - - /* Call the ISR execution exit function if enabled. */ -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_isr_enter // Call the ISR execution enter function -#endif - - ret // Return to ISR - -_tx_thread_nested_save: - - /* Nested interrupt! Just save the scratch registers and return to the ISR. */ - - sw t2, 17*4(sp) // Store t2 - sw s0, 12*4(sp) // Store s0 - sw a0, 27*4(sp) // Store a0 - sw a1, 26*4(sp) // Store a1 - sw a2, 25*4(sp) // Store a2 - sw a3, 24*4(sp) // Store a3 - sw a4, 23*4(sp) // Store a4 - sw a5, 22*4(sp) // Store a5 - sw a6, 21*4(sp) // Store a6 - sw a7, 20*4(sp) // Store a7 - sw t3, 16*4(sp) // Store t3 - sw t4, 15*4(sp) // Store t4 - sw t5, 14*4(sp) // Store t5 - sw t6, 13*4(sp) // Store t6 - - /* Save floating point registers. */ -#if defined(__riscv_float_abi_single) - fsw f0, 31*4(sp) // Store ft0 - fsw f1, 32*4(sp) // Store ft1 - fsw f2, 33*4(sp) // Store ft2 - fsw f3, 34*4(sp) // Store ft3 - fsw f4, 35*4(sp) // Store ft4 - fsw f5, 36*4(sp) // Store ft5 - fsw f6, 37*4(sp) // Store ft6 - fsw f7, 38*4(sp) // Store ft7 - fsw f10, 41*4(sp) // Store fa0 - fsw f11, 42*4(sp) // Store fa1 - fsw f12, 43*4(sp) // Store fa2 - fsw f13, 44*4(sp) // Store fa3 - fsw f14, 45*4(sp) // Store fa4 - fsw f15, 46*4(sp) // Store fa5 - fsw f16, 47*4(sp) // Store fa6 - fsw f17, 48*4(sp) // Store fa7 - fsw f28, 59*4(sp) // Store ft8 - fsw f29, 60*4(sp) // Store ft9 - fsw f30, 61*4(sp) // Store ft10 - fsw f31, 62*4(sp) // Store ft11 - csrr t0, fcsr - sw t0, 63*4(sp) // Store fcsr -#elif defined(__riscv_float_abi_double) - fsd f0, 31*4(sp) // Store ft0 - fsd f1, 32*4(sp) // Store ft1 - fsd f2, 33*4(sp) // Store ft2 - fsd f3, 34*4(sp) // Store ft3 - fsd f4, 35*4(sp) // Store ft4 - fsd f5, 36*4(sp) // Store ft5 - fsd f6, 37*4(sp) // Store ft6 - fsd f7, 38*4(sp) // Store ft7 - fsd f10, 41*4(sp) // Store fa0 - fsd f11, 42*4(sp) // Store fa1 - fsd f12, 43*4(sp) // Store fa2 - fsd f13, 44*4(sp) // Store fa3 - fsd f14, 45*4(sp) // Store fa4 - fsd f15, 46*4(sp) // Store fa5 - fsd f16, 47*4(sp) // Store fa6 - fsd f17, 48*4(sp) // Store fa7 - fsd f28, 59*4(sp) // Store ft8 - fsd f29, 60*4(sp) // Store ft9 - fsd f30, 61*4(sp) // Store ft10 - fsd f31, 62*4(sp) // Store ft11 - csrr t0, fcsr - sw t0, 63*4(sp) // Store fcsr -#endif - - csrr t0, mepc - sw t0, 30*4(sp) // Save it on stack - - csrr t0, mstatus - sw t0, 29*4(sp) - - /* Call the ISR execution exit function if enabled. */ -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_isr_enter // Call the ISR execution enter function -#endif - - ret // Return to ISR - -_tx_thread_idle_system_save: - - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_isr_enter // Call the ISR execution enter function -#endif - - /* Interrupt occurred in the scheduling loop. */ - - /* } -} */ -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*4 // Recover stack frame - with floating point enabled -#else - addi sp, sp, 32*4 // Recover the reserved stack space -#endif - ret // Return to calling ISR diff --git a/ports/risc-v32/clang/src/tx_thread_interrupt_control.S b/ports/risc-v32/clang/src/tx_thread_interrupt_control.S deleted file mode 100644 index 86b6745e2..000000000 --- a/ports/risc-v32/clang/src/tx_thread_interrupt_control.S +++ /dev/null @@ -1,88 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2026 Quintauris - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_control RISC-V32/GNU */ -/* 6.4.x */ -/* AUTHOR */ -/* */ -/* Francisco Merino, Quintauris */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function is responsible for changing the interrupt lockout */ -/* posture of the system. */ -/* */ -/* INPUT */ -/* */ -/* new_posture New interrupt lockout posture */ -/* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/**************************************************************************/ -/* UINT _tx_thread_interrupt_control(UINT new_posture) -{ */ - .global _tx_thread_interrupt_control -_tx_thread_interrupt_control: - - /* Pickup current interrupt posture. */ - - csrr a1, mstatus // Pickup mstatus - andi a1, a1, 0x08 // Mask out all but MIE - - /* Check for the new posture. */ - - beqz a0, _tx_thread_interrupt_disable // If 0, disable interrupts - - /* Enable interrupts. */ - - csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) - j _tx_thread_interrupt_control_exit // Return to caller - -_tx_thread_interrupt_disable: - - /* Disable interrupts. */ - - csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) - -_tx_thread_interrupt_control_exit: - - /* Return the old interrupt posture. */ - - mv a0, a1 // Setup return value - ret // Return to caller - -/* } */ diff --git a/ports/risc-v32/clang/src/tx_thread_schedule.S b/ports/risc-v32/clang/src/tx_thread_schedule.S deleted file mode 100644 index d5a54fa26..000000000 --- a/ports/risc-v32/clang/src/tx_thread_schedule.S +++ /dev/null @@ -1,318 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2026 Quintauris - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_schedule RISC-V32/GNU */ -/* 6.4.x */ -/* AUTHOR */ -/* */ -/* Francisco Merino, Quintauris */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function waits for a thread control block pointer to appear in */ -/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -/* in the variable, the corresponding thread is resumed. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* _tx_thread_system_return Return to system from thread */ -/* _tx_thread_context_restore Restore thread's context */ -/* */ -/**************************************************************************/ -/* VOID _tx_thread_schedule(VOID) -{ */ - .global _tx_thread_schedule -_tx_thread_schedule: - - /* Enable interrupts. */ - - csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) - - /* Wait for a thread to execute. */ - /* do - { */ -_tx_thread_schedule_loop: - - la t0, _tx_thread_execute_ptr // Pickup address of execute ptr - lw t1, 0(t0) // Pickup execute pointer - bnez t1, _tx_thread_ready_to_run // If non-NULL, a thread is ready to run - -#ifndef TX_NO_WFI - wfi // Wait for interrupt -#endif - j _tx_thread_schedule_loop // Check again - - /* } - while (_tx_thread_execute_ptr == TX_NULL); */ - -_tx_thread_ready_to_run: - - /* At this point, t1 contains the pointer to the thread to execute. - Lockout interrupts. */ - - csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) - - /* Check _tx_thread_execute_ptr again, in case an interrupt occurred - between the check and the disable. */ - - lw t1, 0(t0) // Pickup execute pointer - beqz t1, _tx_thread_schedule_loop // If NULL, go back to wait loop - - /* Yes! We have a thread to execute. */ - /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ - - la t0, _tx_thread_current_ptr // Pickup address of current thread - sw t1, 0(t0) // Setup current thread pointer - - /* Increment the run count for this thread. */ - /* _tx_thread_current_ptr -> tx_thread_run_count++; */ - - lw t2, 4(t1) // Pickup run count - addi t2, t2, 1 // Increment run count - sw t2, 4(t1) // Store run count - - /* Setup time-slice values. */ - /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ - - lw t2, 24(t1) // Pickup thread time-slice - la t3, _tx_timer_time_slice // Pickup address of time-slice - sw t2, 0(t3) // Setup time-slice - - /* Call the thread execution enter function if enabled. */ -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - - call _tx_execution_thread_enter // Call the thread execution enter function -#endif - - /* Switch to the thread's stack. */ - /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ - - lw sp, 8(t1) // Switch to thread stack - - /* Determine the type of stack frame. */ - /* if (*sp) - { */ - - lw t0, 0(sp) // Pickup stack type - beqz t0, _tx_thread_solicited_return // If 0, solicited return - - /* Recover floating point registers. */ -#if defined(__riscv_float_abi_single) - flw f0, 31*4(sp) // Recover ft0 - flw f1, 32*4(sp) // Recover ft1 - flw f2, 33*4(sp) // Recover ft2 - flw f3, 34*4(sp) // Recover ft3 - flw f4, 35*4(sp) // Recover ft4 - flw f5, 36*4(sp) // Recover ft5 - flw f6, 37*4(sp) // Recover ft6 - flw f7, 38*4(sp) // Recover ft7 - flw f8, 39*4(sp) // Recover fs0 - flw f9, 40*4(sp) // Recover fs1 - flw f10, 41*4(sp) // Recover fa0 - flw f11, 42*4(sp) // Recover fa1 - flw f12, 43*4(sp) // Recover fa2 - flw f13, 44*4(sp) // Recover fa3 - flw f14, 45*4(sp) // Recover fa4 - flw f15, 46*4(sp) // Recover fa5 - flw f16, 47*4(sp) // Recover fa6 - flw f17, 48*4(sp) // Recover fa7 - flw f18, 49*4(sp) // Recover fs2 - flw f19, 50*4(sp) // Recover fs3 - flw f20, 51*4(sp) // Recover fs4 - flw f21, 52*4(sp) // Recover fs5 - flw f22, 53*4(sp) // Recover fs6 - flw f23, 54*4(sp) // Recover fs7 - flw f24, 55*4(sp) // Recover fs8 - flw f25, 56*4(sp) // Recover fs9 - flw f26, 57*4(sp) // Recover fs10 - flw f27, 58*4(sp) // Recover fs11 - flw f28, 59*4(sp) // Recover ft8 - flw f29, 60*4(sp) // Recover ft9 - flw f30, 61*4(sp) // Recover ft10 - flw f31, 62*4(sp) // Recover ft11 - lw t0, 63*4(sp) // Recover fcsr - csrw fcsr, t0 // Restore fcsr -#elif defined(__riscv_float_abi_double) - fld f0, 31*4(sp) // Recover ft0 - fld f1, 32*4(sp) // Recover ft1 - fld f2, 33*4(sp) // Recover ft2 - fld f3, 34*4(sp) // Recover ft3 - fld f4, 35*4(sp) // Recover ft4 - fld f5, 36*4(sp) // Recover ft5 - fld f6, 37*4(sp) // Recover ft6 - fld f7, 38*4(sp) // Recover ft7 - fld f8, 39*4(sp) // Recover fs0 - fld f9, 40*4(sp) // Recover fs1 - fld f10, 41*4(sp) // Recover fa0 - fld f11, 42*4(sp) // Recover fa1 - fld f12, 43*4(sp) // Recover fa2 - fld f13, 44*4(sp) // Recover fa3 - fld f14, 45*4(sp) // Recover fa4 - fld f15, 46*4(sp) // Recover fa5 - fld f16, 47*4(sp) // Recover fa6 - fld f17, 48*4(sp) // Recover fa7 - fld f18, 49*4(sp) // Recover fs2 - fld f19, 50*4(sp) // Recover fs3 - fld f20, 51*4(sp) // Recover fs4 - fld f21, 52*4(sp) // Recover fs5 - fld f22, 53*4(sp) // Recover fs6 - fld f23, 54*4(sp) // Recover fs7 - fld f24, 55*4(sp) // Recover fs8 - fld f25, 56*4(sp) // Recover fs9 - fld f26, 57*4(sp) // Recover fs10 - fld f27, 58*4(sp) // Recover fs11 - fld f28, 59*4(sp) // Recover ft8 - fld f29, 60*4(sp) // Recover ft9 - fld f30, 61*4(sp) // Recover ft10 - fld f31, 62*4(sp) // Recover ft11 - lw t0, 63*4(sp) // Recover fcsr - csrw fcsr, t0 // Restore fcsr -#endif - - /* Recover standard registers. */ - - lw t0, 30*4(sp) // Recover mepc - csrw mepc, t0 // Setup mepc - - li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t1, 0x2000 // Set FS bits for FP state - or t0, t0, t1 -#endif - csrw mstatus, t0 // Set mstatus - - lw ra, 28*4(sp) // Recover return address - lw t0, 19*4(sp) // Recover t0 - lw t1, 18*4(sp) // Recover t1 - lw t2, 17*4(sp) // Recover t2 - lw s0, 12*4(sp) // Recover s0 - lw x9, 11*4(sp) // Recover s1 - lw a0, 27*4(sp) // Recover a0 - lw a1, 26*4(sp) // Recover a1 - lw a2, 25*4(sp) // Recover a2 - lw a3, 24*4(sp) // Recover a3 - lw a4, 23*4(sp) // Recover a4 - lw a5, 22*4(sp) // Recover a5 - lw a6, 21*4(sp) // Recover a6 - lw a7, 20*4(sp) // Recover a7 - lw t3, 16*4(sp) // Recover t3 - lw t4, 15*4(sp) // Recover t4 - lw t5, 14*4(sp) // Recover t5 - lw t6, 13*4(sp) // Recover t6 - lw x18, 10*4(sp) // Recover s2 - lw x19, 9*4(sp) // Recover s3 - lw x20, 8*4(sp) // Recover s4 - lw x21, 7*4(sp) // Recover s5 - lw x22, 6*4(sp) // Recover s6 - lw x23, 5*4(sp) // Recover s7 - lw x24, 4*4(sp) // Recover s8 - lw x25, 3*4(sp) // Recover s9 - lw x26, 2*4(sp) // Recover s10 - lw x27, 1*4(sp) // Recover s11 - -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*4 // Recover stack frame - with floating point enabled -#else - addi sp, sp, 32*4 // Recover stack frame - without floating point enabled -#endif - mret // Return to thread - -_tx_thread_solicited_return: - - /* Recover floating point registers. */ -#if defined(__riscv_float_abi_single) - flw f8, 15*4(sp) // Recover fs0 - flw f9, 16*4(sp) // Recover fs1 - flw f18, 17*4(sp) // Recover fs2 - flw f19, 18*4(sp) // Recover fs3 - flw f20, 19*4(sp) // Recover fs4 - flw f21, 20*4(sp) // Recover fs5 - flw f22, 21*4(sp) // Recover fs6 - flw f23, 22*4(sp) // Recover fs7 - flw f24, 23*4(sp) // Recover fs8 - flw f25, 24*4(sp) // Recover fs9 - flw f26, 25*4(sp) // Recover fs10 - flw f27, 26*4(sp) // Recover fs11 - lw t0, 27*4(sp) // Recover fcsr - csrw fcsr, t0 // Restore fcsr -#elif defined(__riscv_float_abi_double) - fld f8, 15*4(sp) // Recover fs0 - fld f9, 16*4(sp) // Recover fs1 - fld f18, 17*4(sp) // Recover fs2 - fld f19, 18*4(sp) // Recover fs3 - fld f20, 19*4(sp) // Recover fs4 - fld f21, 20*4(sp) // Recover fs5 - fld f22, 21*4(sp) // Recover fs6 - fld f23, 22*4(sp) // Recover fs7 - fld f24, 23*4(sp) // Recover fs8 - fld f25, 24*4(sp) // Recover fs9 - fld f26, 25*4(sp) // Recover fs10 - fld f27, 26*4(sp) // Recover fs11 - lw t0, 27*4(sp) // Recover fcsr - csrw fcsr, t0 // Restore fcsr -#endif - - /* Recover standard registers. */ - - lw t0, 14*4(sp) // Recover mstatus - csrw mstatus, t0 // Restore mstatus - - lw ra, 13*4(sp) // Recover return address - lw s0, 12*4(sp) // Recover s0 - lw s1, 11*4(sp) // Recover s1 - lw x18, 10*4(sp) // Recover s2 - lw x19, 9*4(sp) // Recover s3 - lw x20, 8*4(sp) // Recover s4 - lw x21, 7*4(sp) // Recover s5 - lw x22, 6*4(sp) // Recover s6 - lw x23, 5*4(sp) // Recover s7 - lw x24, 4*4(sp) // Recover s8 - lw x25, 3*4(sp) // Recover s9 - lw x26, 2*4(sp) // Recover s10 - lw x27, 1*4(sp) // Recover s11 - -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 29*4 // Recover stack frame - with floating point enabled -#else - addi sp, sp, 16*4 // Recover stack frame - without floating point enabled -#endif - ret // Return to thread - -/* } */ diff --git a/ports/risc-v32/clang/src/tx_thread_stack_build.S b/ports/risc-v32/clang/src/tx_thread_stack_build.S deleted file mode 100644 index 2b8ebae11..000000000 --- a/ports/risc-v32/clang/src/tx_thread_stack_build.S +++ /dev/null @@ -1,221 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2026 Quintauris - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_build RISC-V32/GNU */ -/* 6.4.x */ -/* AUTHOR */ -/* */ -/* Francisco Merino, Quintauris */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function builds a stack frame on the supplied thread's stack. */ -/* The stack frame results in a fake interrupt return to the supplied */ -/* function pointer. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to thread control blk */ -/* function_ptr Pointer to return function */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create Create thread service */ -/* */ -/**************************************************************************/ -/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -{ */ - .global _tx_thread_stack_build -_tx_thread_stack_build: - - /* Build a fake interrupt frame. The form of the fake interrupt stack - on the RISC-V should look like the following after it is built: - Reg Index - Stack Top: 1 0 Interrupt stack frame type - x27 1 Initial s11 - x26 2 Initial s10 - x25 3 Initial s9 - x24 4 Initial s8 - x23 5 Initial s7 - x22 6 Initial s6 - x21 7 Initial s5 - x20 8 Initial s4 - x19 9 Initial s3 - x18 10 Initial s2 - x9 11 Initial s1 - x8 12 Initial s0 - x31 13 Initial t6 - x30 14 Initial t5 - x29 15 Initial t4 - x28 16 Initial t3 - x7 17 Initial t2 - x6 18 Initial t1 - x5 19 Initial t0 - x17 20 Initial a7 - x16 21 Initial a6 - x15 22 Initial a5 - x14 23 Initial a4 - x13 24 Initial a3 - x12 25 Initial a2 - x11 26 Initial a1 - x10 27 Initial a0 - x1 28 Initial ra - -- 29 reserved - mepc 30 Initial mepc -If floating point support: - f0 31 Initial ft0 - f1 32 Initial ft1 - f2 33 Initial ft2 - f3 34 Initial ft3 - f4 35 Initial ft4 - f5 36 Initial ft5 - f6 37 Initial ft6 - f7 38 Initial ft7 - f8 39 Initial fs0 - f9 40 Initial fs1 - f10 41 Initial fa0 - f11 42 Initial fa1 - f12 43 Initial fa2 - f13 44 Initial fa3 - f14 45 Initial fa4 - f15 46 Initial fa5 - f16 47 Initial fa6 - f17 48 Initial fa7 - f18 49 Initial fs2 - f19 50 Initial fs3 - f20 51 Initial fs4 - f21 52 Initial fs5 - f22 53 Initial fs6 - f23 54 Initial fs7 - f24 55 Initial fs8 - f25 56 Initial fs9 - f26 57 Initial fs10 - f27 58 Initial fs11 - f28 59 Initial ft8 - f29 60 Initial ft9 - f30 61 Initial ft10 - f31 62 Initial ft11 - fscr 63 Initial fscr - - Stack Bottom: (higher memory address) */ - - lw t0, 16(a0) // Pickup end of stack area - li t1, ~15 // Build 16-byte alignment mask - and t0, t0, t1 // Make sure 16-byte alignment - - /* Actually build the stack frame. */ - -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi t0, t0, -65*4 -#else - addi t0, t0, -32*4 // Allocate space for the stack frame -#endif - li t1, 1 // Build stack type - sw t1, 0*4(t0) // Place stack type on the top - sw zero, 1*4(t0) // Initial s11 - sw zero, 2*4(t0) // Initial s10 - sw zero, 3*4(t0) // Initial s9 - sw zero, 4*4(t0) // Initial s8 - sw zero, 5*4(t0) // Initial s7 - sw zero, 6*4(t0) // Initial s6 - sw zero, 7*4(t0) // Initial s5 - sw zero, 8*4(t0) // Initial s4 - sw zero, 9*4(t0) // Initial s3 - sw zero, 10*4(t0) // Initial s2 - sw zero, 11*4(t0) // Initial s1 - sw zero, 12*4(t0) // Initial s0 - sw zero, 13*4(t0) // Initial t6 - sw zero, 14*4(t0) // Initial t5 - sw zero, 15*4(t0) // Initial t4 - sw zero, 16*4(t0) // Initial t3 - sw zero, 17*4(t0) // Initial t2 - sw zero, 18*4(t0) // Initial t1 - sw zero, 19*4(t0) // Initial t0 - sw zero, 20*4(t0) // Initial a7 - sw zero, 21*4(t0) // Initial a6 - sw zero, 22*4(t0) // Initial a5 - sw zero, 23*4(t0) // Initial a4 - sw zero, 24*4(t0) // Initial a3 - sw zero, 25*4(t0) // Initial a2 - sw zero, 26*4(t0) // Initial a1 - sw zero, 27*4(t0) // Initial a0 - sw zero, 28*4(t0) // Initial ra - sw a1, 30*4(t0) // Initial mepc (thread entry point) -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - sw zero, 31*4(t0) // Initial ft0 - sw zero, 32*4(t0) // Initial ft1 - sw zero, 33*4(t0) // Initial ft2 - sw zero, 34*4(t0) // Initial ft3 - sw zero, 35*4(t0) // Initial ft4 - sw zero, 36*4(t0) // Initial ft5 - sw zero, 37*4(t0) // Initial ft6 - sw zero, 38*4(t0) // Initial ft7 - sw zero, 39*4(t0) // Initial fs0 - sw zero, 40*4(t0) // Initial fs1 - sw zero, 41*4(t0) // Initial fa0 - sw zero, 42*4(t0) // Initial fa1 - sw zero, 43*4(t0) // Initial fa2 - sw zero, 44*4(t0) // Initial fa3 - sw zero, 45*4(t0) // Initial fa4 - sw zero, 46*4(t0) // Initial fa5 - sw zero, 47*4(t0) // Initial fa6 - sw zero, 48*4(t0) // Initial fa7 - sw zero, 49*4(t0) // Initial fs2 - sw zero, 50*4(t0) // Initial fs3 - sw zero, 51*4(t0) // Initial fs4 - sw zero, 52*4(t0) // Initial fs5 - sw zero, 53*4(t0) // Initial fs6 - sw zero, 54*4(t0) // Initial fs7 - sw zero, 55*4(t0) // Initial fs8 - sw zero, 56*4(t0) // Initial fs9 - sw zero, 57*4(t0) // Initial fs10 - sw zero, 58*4(t0) // Initial fs11 - sw zero, 59*4(t0) // Initial ft8 - sw zero, 60*4(t0) // Initial ft9 - sw zero, 61*4(t0) // Initial ft10 - sw zero, 62*4(t0) // Initial ft11 - csrr a1, fcsr // Read fcsr for initial value - sw a1, 63*4(t0) // Initial fcsr - sw zero, 64*4(t0) // Reserved word (0) -#else - sw zero, 31*4(t0) // Reserved word (0) -#endif - - /* Setup stack pointer. */ - /* thread_ptr -> tx_thread_stack_ptr = t0; */ - - sw t0, 8(a0) // Save stack pointer in thread's - ret // control block and return -/* } */ diff --git a/ports/risc-v32/clang/src/tx_thread_system_return.S b/ports/risc-v32/clang/src/tx_thread_system_return.S deleted file mode 100644 index b54f54fa8..000000000 --- a/ports/risc-v32/clang/src/tx_thread_system_return.S +++ /dev/null @@ -1,168 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2026 Quintauris - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_system_return RISC-V32/GNU */ -/* 6.4.x */ -/* AUTHOR */ -/* */ -/* Francisco Merino, Quintauris */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function is target processor specific. It is used to transfer */ -/* control from a thread back to the system. Only a minimal context */ -/* is saved since the compiler assumes temp registers are going to get */ -/* slicked by a function call anyway. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_schedule Thread scheduling loop */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX components */ -/* */ -/**************************************************************************/ -/* VOID _tx_thread_system_return(VOID) -{ */ - .global _tx_thread_system_return -_tx_thread_system_return: - - /* Save minimal context on the stack. */ - /* sp -= sizeof(stack_frame); */ - -#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, -29*4 // Allocate space on the stack - with floating point enabled -#else - addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled -#endif - - /* Store floating point preserved registers. */ -#if defined(__riscv_float_abi_single) - fsw f8, 15*4(sp) // Store fs0 - fsw f9, 16*4(sp) // Store fs1 - fsw f18, 17*4(sp) // Store fs2 - fsw f19, 18*4(sp) // Store fs3 - fsw f20, 19*4(sp) // Store fs4 - fsw f21, 20*4(sp) // Store fs5 - fsw f22, 21*4(sp) // Store fs6 - fsw f23, 22*4(sp) // Store fs7 - fsw f24, 23*4(sp) // Store fs8 - fsw f25, 24*4(sp) // Store fs9 - fsw f26, 25*4(sp) // Store fs10 - fsw f27, 26*4(sp) // Store fs11 - csrr t0, fcsr - sw t0, 27*4(sp) // Store fcsr -#elif defined(__riscv_float_abi_double) - fsd f8, 15*4(sp) // Store fs0 - fsd f9, 16*4(sp) // Store fs1 - fsd f18, 17*4(sp) // Store fs2 - fsd f19, 18*4(sp) // Store fs3 - fsd f20, 19*4(sp) // Store fs4 - fsd f21, 20*4(sp) // Store fs5 - fsd f22, 21*4(sp) // Store fs6 - fsd f23, 22*4(sp) // Store fs7 - fsd f24, 23*4(sp) // Store fs8 - fsd f25, 24*4(sp) // Store fs9 - fsd f26, 25*4(sp) // Store fs10 - fsd f27, 26*4(sp) // Store fs11 - csrr t0, fcsr - sw t0, 27*4(sp) // Store fcsr -#endif - - sw zero, 0(sp) // Solicited stack type - sw ra, 13*4(sp) // Save return address - sw s0, 12*4(sp) // Save s0 - sw s1, 11*4(sp) // Save s1 - sw s2, 10*4(sp) // Save s2 - sw s3, 9*4(sp) // Save s3 - sw s4, 8*4(sp) // Save s4 - sw s5, 7*4(sp) // Save s5 - sw s6, 6*4(sp) // Save s6 - sw s7, 5*4(sp) // Save s7 - sw s8, 4*4(sp) // Save s8 - sw s9, 3*4(sp) // Save s9 - sw s10, 2*4(sp) // Save s10 - sw s11, 1*4(sp) // Save s11 - csrr t0, mstatus // Pickup mstatus - sw t0, 14*4(sp) // Save mstatus - - - /* Lockout interrupts. will be enabled in _tx_thread_schedule */ - - csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - - call _tx_execution_thread_exit // Call the thread execution exit function -#endif - - la t0, _tx_thread_current_ptr // Pickup address of pointer - lw t1, 0(t0) // Pickup current thread pointer - la t2, _tx_thread_system_stack_ptr // Pickup stack pointer address - - /* Save current stack and switch to system stack. */ - /* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; - SP = _tx_thread_system_stack_ptr; */ - - sw sp, 8(t1) // Save stack pointer - lw sp, 0(t2) // Switch to system stack - - /* Determine if the time-slice is active. */ - /* if (_tx_timer_time_slice) - { */ - - la t4, _tx_timer_time_slice // Pickup time slice variable addr - lw t3, 0(t4) // Pickup time slice value - la t2, _tx_thread_schedule // Pickup address of scheduling loop - beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it - - /* Save time-slice for the thread and clear the current time-slice. */ - /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; - _tx_timer_time_slice = 0; */ - - sw t3, 24(t1) // Save current time-slice for thread - sw zero, 0(t4) // Clear time-slice variable - - /* } */ -_tx_thread_dont_save_ts: - - /* Clear the current thread pointer. */ - /* _tx_thread_current_ptr = TX_NULL; */ - - sw x0, 0(t0) // Clear current thread pointer - jr t2 // Return to thread scheduler - -/* } */ diff --git a/ports/risc-v32/clang/src/tx_timer_interrupt.S b/ports/risc-v32/clang/src/tx_timer_interrupt.S deleted file mode 100644 index b64bf06b4..000000000 --- a/ports/risc-v32/clang/src/tx_timer_interrupt.S +++ /dev/null @@ -1,204 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2026 Quintauris - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Timer */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .section .text - .align 4 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_timer_interrupt RISC-V32/GNU */ -/* 6.2.1 */ -/* AUTHOR */ -/* */ -/* Francisco Merino, Quintauris */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_timer_expiration_process Timer expiration processing */ -/* _tx_thread_time_slice Time slice interrupted thread */ -/* */ -/* CALLED BY */ -/* */ -/* interrupt vector */ -/* */ -/**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ - .global _tx_timer_interrupt -_tx_timer_interrupt: - - /* Increment the system clock. */ - /* _tx_timer_system_clock++; */ - - la t0, _tx_timer_system_clock // Pickup address of system clock - lw t1, 0(t0) // Pickup system clock - la t2, _tx_timer_time_slice // Pickup address of time slice - lw t3, 0(t2) // Pickup time slice - addi t1, t1, 1 // Increment system clock - sw t1, 0(t0) // Store new system clock - li t6, 0 // Clear local expired flag - - /* Test for time-slice expiration. */ - /* if (_tx_timer_time_slice) - { */ - - beqz t3, _tx_timer_no_time_slice // If 0, skip time slice processing - addi t3, t3, -1 // Decrement the time slice - - /* Decrement the time_slice. */ - /* _tx_timer_time_slice--; */ - - sw t3, 0(t2) // Store new time slice - - /* Check for expiration. */ - /* if (_tx_timer_time_slice == 0) */ - - bgtz t3, _tx_timer_no_time_slice // If not 0, has not expired yet - li t1, 1 // Build expired flag - - /* Set the time-slice expired flag. */ - /* _tx_timer_expired_time_slice = TX_TRUE; */ - - la t4, _tx_timer_expired_time_slice // Get address of expired flag - sw t1, 0(t4) // Set expired flag (UINT) - ori t6, t6, 1 // Set local expired flag - - /* } */ - -_tx_timer_no_time_slice: - - /* Test for timer expiration. */ - /* if (*_tx_timer_current_ptr) - { */ - - la t0, _tx_timer_current_ptr // Pickup address of current ptr - lw t1, 0(t0) // Pickup current pointer (word) - lw t3, 0(t1) // Pickup the current timer entry (word) - la t2, _tx_timer_expired // Pickup address of timer expired flag - li t4, 1 // Build TX_TRUE flag - beqz t3, _tx_timer_no_timer // If NULL, no timer has expired - - /* Set expiration flag. */ - /* _tx_timer_expired = TX_TRUE; */ - - ori t6, t6, 2 // Set local expired flag - sw t4, 0(t2) // Set expired flag in memory (UINT) - j _tx_timer_done // Finished timer processing - - - /* } - else - { */ -_tx_timer_no_timer: - - /* No timer expired, increment the timer pointer. */ - /* _tx_timer_current_ptr++; */ - - /* Check for wrap-around. */ - /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ - - la t2, _tx_timer_list_end // Pickup address of list end pointer - lw t3, 0(t2) // Pickup actual list end - addi t1, t1, 4 // Point to next timer entry - sw t1, 0(t0) // Store new timer pointer - bne t1, t3, _tx_timer_skip_wrap // If not same, good pointer - - /* Wrap to beginning of list. */ - /* _tx_timer_current_ptr = _tx_timer_list_start; */ - - la t2, _tx_timer_list_start // Pickup address of list start pointer - lw t4, 0(t2) // Pickup start of the list - sw t4, 0(t0) // Store new timer pointer - - -_tx_timer_skip_wrap: - /* } */ - -_tx_timer_done: - - - /* See if anything has expired. */ - /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) - { */ - - beqz t6, _tx_timer_nothing_expired // If nothing expired skip the rest - addi sp, sp, -16 // Allocate some storage on the stack - sw t6, 0(sp) // Save local expired flag - sw ra, 4(sp) // Save ra - - /* Did a timer expire? */ - /* if (_tx_timer_expired) - { */ - - andi t2, t6, 2 // Isolate the timer expired bit - beqz t2, _tx_timer_dont_activate // No, timer not expired - - /* Call the timer expiration processing. */ - /* _tx_timer_expiration_process(void); */ - - call _tx_timer_expiration_process // Call _tx_timer_expiration_process - lw t6, 0(sp) // Recover local expired flag - - /* } */ -_tx_timer_dont_activate: - - /* Did time slice expire? */ - /* if (_tx_timer_expired_time_slice) - { */ - - andi t2, t6, 1 // Is the timer expired bit set? - beqz t2, _tx_timer_not_ts_expiration // If not, skip time slice processing - - /* Time slice interrupted thread. */ - /* _tx_thread_time_slice(); */ - - call _tx_thread_time_slice // Call time slice - - /* } */ - -_tx_timer_not_ts_expiration: - - lw ra, 4(sp) // Recover ra - addi sp, sp, 16 // Recover stack space - /* } */ - -_tx_timer_nothing_expired: - - ret - -/* } */ \ No newline at end of file diff --git a/ports/risc-v32/common/tx_port_riscv32_common.h b/ports/risc-v32/common/tx_port_riscv32_common.h new file mode 100644 index 000000000..886565a81 --- /dev/null +++ b/ports/risc-v32/common/tx_port_riscv32_common.h @@ -0,0 +1,268 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port_riscv32_common.h RISC-V32 */ +/* 6.4.x */ +/* */ +/* DESCRIPTION */ +/* */ +/* Shared port definitions for all RISC-V32 toolchain ports (GNU, */ +/* Clang, etc.). Each toolchain's tx_port.h includes this file and */ +/* may add toolchain-specific definitions afterwards. */ +/* */ +/**************************************************************************/ + +/* This file is included from a toolchain-specific tx_port.h; do not */ +/* include it directly. */ + +#ifndef TX_PORT_H +#error "Include tx_port.h, not tx_port_riscv32_common.h directly." +#endif + + +#ifndef __ASSEMBLER__ + +/* Include for memset. */ +#include + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif /* TX_INCLUDE_USER_DEFINE_FILE */ + +#endif /* __ASSEMBLER__ */ + + +/* Define ThreadX basic types for this port. */ + +#define VOID void + +#ifndef __ASSEMBLER__ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +#define ULONG64_DEFINED +#endif /* __ASSEMBLER__ */ + + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX RISC-V port. */ + +#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ +#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +/* Expose helper used to perform an atomic read/modify/write of mstatus. + The helper composes and returns the posture per ThreadX contract. */ +#ifndef __ASSEMBLER__ +UINT _tx_thread_interrupt_control(UINT new_posture); +#endif + +#ifdef TX_DISABLE_INLINE + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory"); +#define TX_RESTORE { \ + unsigned long _temp_mstatus; \ + __asm__ volatile( \ + "csrc mstatus, 8\n" \ + "andi %0, %1, 8\n" \ + "csrs mstatus, %0" \ + : "=&r" (_temp_mstatus) \ + : "r" (interrupt_save) \ + : "memory"); \ + } + +#else + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#endif /* TX_DISABLE_INLINE */ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE diff --git a/ports/risc-v32/gnu/CMakeLists.txt b/ports/risc-v32/gnu/CMakeLists.txt index 7c6785bba..050007573 100644 --- a/ports/risc-v32/gnu/CMakeLists.txt +++ b/ports/risc-v32/gnu/CMakeLists.txt @@ -1,23 +1,7 @@ +include(${CMAKE_CURRENT_LIST_DIR}/../../../cmake/threadx_riscv_port.cmake) -target_sources(${PROJECT_NAME} - PRIVATE - # {{BEGIN_TARGET_SOURCES}} - ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S - # {{END_TARGET_SOURCES}} +threadx_add_riscv_port( + SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/src + INC_DIR ${CMAKE_CURRENT_LIST_DIR}/inc + EXAMPLE_DIR ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt ) - -target_include_directories(${PROJECT_NAME} - PUBLIC - ${CMAKE_CURRENT_LIST_DIR}/inc -) - -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt/CMakeLists.txt) - add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt) -endif() diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt b/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt index eb6b4c89f..6946b3474 100644 --- a/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt @@ -10,6 +10,10 @@ set(TX_USER_FILE ${CORE_V_MCU_DIR}/include/tx_user.h) set(THREADX_ARCH "risc-v32") set(THREADX_TOOLCHAIN "gnu") + +message(STATUS "Toolchain file: ${CMAKE_TOOLCHAIN_FILE}") +message(STATUS "C compiler: ${CMAKE_C_COMPILER}") + add_subdirectory(${THREADX_ROOT} threadx) target_include_directories(threadx PRIVATE ${CORE_V_MCU_DIR}/include) @@ -17,6 +21,7 @@ set(SRCS ${CORE_V_MCU_DIR}/crt0.S ${CORE_V_MCU_DIR}/vectors.S ${CORE_V_MCU_DIR}/tx_initialize_low_level.S + ${CORE_V_MCU_DIR}/bsp/clz.c ${CORE_V_MCU_DIR}/bsp/irq.c ${CORE_V_MCU_DIR}/bsp/timer_irq.c ${CORE_V_MCU_DIR}/bsp/fll.c diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c new file mode 100644 index 000000000..ef3cb23ba --- /dev/null +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c @@ -0,0 +1,29 @@ +/* clz.c — portable fallback for __clzsi2 (count leading zeros, 32-bit) + * + * The riscv-collab bare-metal toolchain (riscv64-unknown-elf from /opt/riscv) + * is built without multilib and does not ship an rv32/ilp32 libgcc. As a + * result __clzsi2, which GCC emits for __builtin_clz() on targets without a + * hardware CLZ instruction, is missing at link time. + * + * This file provides a weak definition so that the build is self-contained + * with any RISC-V bare-metal toolchain. When a toolchain does ship the symbol + * in libgcc (e.g. the Ubuntu gcc-riscv64-unknown-elf package), the libgcc copy + * will take precedence over this weak one. + */ + +#include + +__attribute__((weak)) +int __clzsi2(uint32_t x) +{ + if (x == 0U) + return 32; + + int n = 0; + if ((x & 0xFFFF0000U) == 0U) { n += 16; x <<= 16; } + if ((x & 0xFF000000U) == 0U) { n += 8; x <<= 8; } + if ((x & 0xF0000000U) == 0U) { n += 4; x <<= 4; } + if ((x & 0xC0000000U) == 0U) { n += 2; x <<= 2; } + if ((x & 0x80000000U) == 0U) { n += 1; } + return n; +} diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/entry.s b/ports/risc-v32/gnu/example_build/cva6_ariane/entry.S similarity index 100% rename from ports/risc-v32/gnu/example_build/cva6_ariane/entry.s rename to ports/risc-v32/gnu/example_build/cva6_ariane/entry.S diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/plic.c b/ports/risc-v32/gnu/example_build/cva6_ariane/plic.c deleted file mode 100644 index 01e5c71a4..000000000 --- a/ports/risc-v32/gnu/example_build/cva6_ariane/plic.c +++ /dev/null @@ -1,72 +0,0 @@ -#include "plic.h" -#include -irq_callback callbacks[MAX_CALLBACK_NUM]; - -void plic_irq_enable(int irqno) -{ - int hart = riscv_get_core(); - *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno)); - return; -} - -void plic_irq_disable(int irqno) -{ - int hart = riscv_get_core(); - *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno))); - return; -} - -void plic_prio_set(int irqno, int prio) -{ - PLIC_SET_PRIO(irqno, prio); -} - -int plic_prio_get(int irqno) -{ - return PLIC_GET_PRIO(irqno); -} - -int plic_register_callback(int irqno, irq_callback callback) -{ - if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM)) - return -1; - callbacks[irqno] = callback; - return 0; -} - -int plic_unregister_callback(int irqno) -{ - return plic_register_callback(irqno, NULL); -} - -int plic_init(void) -{ - for(int i=0;i - -#define PLIC 0x0C000000L -#define PLIC_PRIORITY (PLIC + 0x0) -#define PLIC_PENDING (PLIC + 0x1000) -#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100) -#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100) -#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000) -#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000) -#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000) -#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000) -#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000) -#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000) - - -#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4)) -#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio)) - -#define MAX_CALLBACK_NUM 128 -typedef int (*irq_callback)(int irqno); - -void plic_irq_enable(int irqno); -void plic_irq_disable(int irqno); -int plic_prio_get(int irqno); -void plic_prio_set(int irqno, int prio); -int plic_register_callback(int irqno, irq_callback callback); -int plic_unregister_callback(int irqno); -int plic_init(void); -int plic_claim(void); -void plic_complete(int irqno); - -int plic_irq_intr(void); - -#endif - diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/plic.h b/ports/risc-v32/gnu/example_build/cva6_ariane/plic.h new file mode 120000 index 000000000..f776a3d2a --- /dev/null +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/plic.h @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/plic/plic.h \ No newline at end of file diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt b/ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt index 9e9ff7223..43e757ace 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt +++ b/ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt @@ -2,7 +2,7 @@ set(QEMU_DEMO_DIR ${CMAKE_CURRENT_LIST_DIR}) add_executable(kernel.elf EXCLUDE_FROM_ALL ${QEMU_DEMO_DIR}/demo_threadx.c - ${QEMU_DEMO_DIR}/entry.s + ${QEMU_DEMO_DIR}/entry.S ${QEMU_DEMO_DIR}/uart.c ${QEMU_DEMO_DIR}/plic.c ${QEMU_DEMO_DIR}/hwtimer.c @@ -31,7 +31,7 @@ find_package(Python3 COMPONENTS Interpreter) if(Python3_FOUND) add_custom_target(check-functional-riscv32 COMMAND ${Python3_EXECUTABLE} - ${QEMU_DEMO_DIR}/test/azrtos_test_tx_gnu_riscv32_qemu.py + ${QEMU_DEMO_DIR}/test/threadx_test_tx_gnu_riscv32_qemu.py --elf $ --qemu qemu-system-riscv32 --gdb gdb diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh b/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh index f3d806441..f6ec0bcd1 100755 --- a/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh +++ b/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh @@ -13,7 +13,7 @@ riscv32-unknown-elf-gcc \ -ffunction-sections -fdata-sections \ -I../../../../../common/inc \ -I../../inc \ - entry.s \ + entry.S \ tx_initialize_low_level.S \ board.c uart.c hwtimer.c plic.c trap.c demo_threadx.c \ -L../../../../../build -lthreadx \ diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/csr.h b/ports/risc-v32/gnu/example_build/qemu_virt/csr.h deleted file mode 100644 index 9f986bacf..000000000 --- a/ports/risc-v32/gnu/example_build/qemu_virt/csr.h +++ /dev/null @@ -1,343 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2025 10xEngineers - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -#ifndef RISCV_CSR_H -#define RISCV_CSR_H - - -// Machine Status Register, mstatus -#define MSTATUS_MPP_MASK (3L << 11) // previous mode. -#define MSTATUS_MPP_M (3L << 11) -#define MSTATUS_MPP_S (1L << 11) -#define MSTATUS_MPP_U (0L << 11) -#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable. -#define MSTATUS_MPIE (1L << 7) -#define MSTATUS_FS (1L << 13) - -// Machine-mode Interrupt Enable -#define MIE_MTIE (1L << 7) -#define MIE_MSIE (1L << 3) -#define MIE_MEIE (1L << 11) -#define MIE_STIE (1L << 5) // supervisor timer -#define MIE_SSIE (1L << 1) -#define MIE_SEIE (1L << 9) - -// Supervisor Status Register, sstatus -#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User -#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable -#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable -#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable -#define SSTATUS_UIE (1L << 0) // User Interrupt Enable -#define SSTATUS_SPIE (1L << 5) -#define SSTATUS_UPIE (1L << 4) - -// Supervisor Interrupt Enable -#define SIE_SEIE (1L << 9) // external -#define SIE_STIE (1L << 5) // timer -#define SIE_SSIE (1L << 1) // software - -#ifndef __ASSEMBLER__ - -#include - -static inline uint32_t riscv_get_core() -{ - uint32_t x; - asm volatile("csrr %0, mhartid" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_mstatus() -{ - uint32_t x; - asm volatile("csrr %0, mstatus" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mstatus(uint32_t x) -{ - asm volatile("csrw mstatus, %0" : : "r" (x)); -} - -static inline void riscv_writ_mepc(uint32_t x) -{ - asm volatile("csrw mepc, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_sstatus() -{ - uint32_t x; - asm volatile("csrr %0, sstatus" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_sstatus(uint32_t x) -{ - asm volatile("csrw sstatus, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_sip() -{ - uint32_t x; - asm volatile("csrr %0, sip" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_sip(uint32_t x) -{ - asm volatile("csrw sip, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_sie() -{ - uint32_t x; - asm volatile("csrr %0, sie" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_sie(uint32_t x) -{ - asm volatile("csrw sie, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_mie() -{ - uint32_t x; - asm volatile("csrr %0, mie" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mie(uint32_t x) -{ - asm volatile("csrw mie, %0" : : "r" (x)); -} - -static inline void riscv_writ_sepc(uint32_t x) -{ - asm volatile("csrw sepc, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_sepc() -{ - uint32_t x; - asm volatile("csrr %0, sepc" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_medeleg() -{ - uint32_t x; - asm volatile("csrr %0, medeleg" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_medeleg(uint32_t x) -{ - asm volatile("csrw medeleg, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_mideleg() -{ - uint32_t x; - asm volatile("csrr %0, mideleg" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mideleg(uint32_t x) -{ - asm volatile("csrw mideleg, %0" : : "r" (x)); -} - -static inline void riscv_writ_stvec(uint32_t x) -{ - asm volatile("csrw stvec, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_stvec() -{ - uint32_t x; - asm volatile("csrr %0, stvec" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_stimecmp() -{ - uint32_t x; - asm volatile("csrr %0, 0x14d" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_stimecmp(uint32_t x) -{ - asm volatile("csrw 0x14d, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_menvcfg() -{ - uint32_t x; - asm volatile("csrr %0, 0x30a" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_menvcfg(uint32_t x) -{ - asm volatile("csrw 0x30a, %0" : : "r" (x)); -} - -static inline void riscv_writ_pmpcfg0(uint32_t x) -{ - asm volatile("csrw pmpcfg0, %0" : : "r" (x)); -} - -static inline void riscv_writ_pmpaddr0(uint32_t x) -{ - asm volatile("csrw pmpaddr0, %0" : : "r" (x)); -} - -static inline void riscv_writ_satp(uint32_t x) -{ - asm volatile("csrw satp, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_satp() -{ - uint32_t x; - asm volatile("csrr %0, satp" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_scause() -{ - uint32_t x; - asm volatile("csrr %0, scause" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_stval() -{ - uint32_t x; - asm volatile("csrr %0, stval" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mcounteren(uint32_t x) -{ - asm volatile("csrw mcounteren, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_mcounteren() -{ - uint32_t x; - asm volatile("csrr %0, mcounteren" : "=r" (x) ); - return x; -} - -static inline uint32_t riscv_get_time() -{ - uint32_t x; - asm volatile("csrr %0, time" : "=r" (x) ); - return x; -} - -static inline void riscv_sintr_on() -{ - uint32_t sstatus = riscv_get_sstatus(); - sstatus |= SSTATUS_SIE; - riscv_writ_sstatus(sstatus); -} - -static inline void riscv_sintr_off() -{ - uint32_t sstatus = riscv_get_sstatus(); - sstatus &= (~SSTATUS_SIE); - riscv_writ_sstatus(sstatus); -} - -static inline int riscv_sintr_get() -{ - uint32_t x = riscv_get_sstatus(); - return (x & SSTATUS_SIE) != 0; -} - -static inline void riscv_sintr_restore(int x) -{ - if(x) - riscv_sintr_on(); - else - riscv_sintr_off(); -} - -static inline void riscv_mintr_on() -{ - uint32_t mstatus = riscv_get_mstatus(); - mstatus |= MSTATUS_MIE; - riscv_writ_mstatus(mstatus); -} - -static inline void riscv_mintr_off() -{ - uint32_t mstatus = riscv_get_mstatus(); - mstatus &= (~MSTATUS_MIE); - riscv_writ_mstatus(mstatus); -} - -static inline int riscv_mintr_get() -{ - uint32_t x = riscv_get_mstatus(); - return (x & MSTATUS_MIE) != 0; -} - -static inline void riscv_mintr_restore(int x) -{ - if(x) - riscv_mintr_on(); - else - riscv_mintr_off(); -} - -static inline uint32_t riscv_get_sp() -{ - uint32_t x; - asm volatile("mv %0, sp" : "=r" (x) ); - return x; -} - -// read and write tp, the thread pointer, which xv6 uses to hold -// this core's hartid (core number), the index into cpus[]. -static inline uint32_t riscv_get_tp() -{ - uint32_t x; - asm volatile("mv %0, tp" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_tp(uint32_t x) -{ - asm volatile("mv tp, %0" : : "r" (x)); -} - -static inline uint32_t riscv_get_ra() -{ - uint32_t x; - asm volatile("mv %0, ra" : "=r" (x) ); - return x; -} - -// flush the TLB. -static inline void sfence_vma() -{ - // the zero, zero means flush all TLB entries. - asm volatile("sfence.vma zero, zero"); -} - -#endif // __ASSEMBLER__ - -#endif diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/csr.h b/ports/risc-v32/gnu/example_build/qemu_virt/csr.h new file mode 120000 index 000000000..b5df6f125 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/csr.h @@ -0,0 +1 @@ +../../../../risc-v_common/inc/csr.h \ No newline at end of file diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/entry.s b/ports/risc-v32/gnu/example_build/qemu_virt/entry.S similarity index 100% rename from ports/risc-v32/gnu/example_build/qemu_virt/entry.s rename to ports/risc-v32/gnu/example_build/qemu_virt/entry.S diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/plic.c b/ports/risc-v32/gnu/example_build/qemu_virt/plic.c deleted file mode 100644 index 01e5c71a4..000000000 --- a/ports/risc-v32/gnu/example_build/qemu_virt/plic.c +++ /dev/null @@ -1,72 +0,0 @@ -#include "plic.h" -#include -irq_callback callbacks[MAX_CALLBACK_NUM]; - -void plic_irq_enable(int irqno) -{ - int hart = riscv_get_core(); - *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno)); - return; -} - -void plic_irq_disable(int irqno) -{ - int hart = riscv_get_core(); - *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno))); - return; -} - -void plic_prio_set(int irqno, int prio) -{ - PLIC_SET_PRIO(irqno, prio); -} - -int plic_prio_get(int irqno) -{ - return PLIC_GET_PRIO(irqno); -} - -int plic_register_callback(int irqno, irq_callback callback) -{ - if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM)) - return -1; - callbacks[irqno] = callback; - return 0; -} - -int plic_unregister_callback(int irqno) -{ - return plic_register_callback(irqno, NULL); -} - -int plic_init(void) -{ - for(int i=0;i - -#define PLIC 0x0c000000L -#define PLIC_PRIORITY (PLIC + 0x0) -#define PLIC_PENDING (PLIC + 0x1000) -#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100) -#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100) -#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000) -#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000) -#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000) -#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000) -#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000) -#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000) - - -#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4)) -#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio)) - -#define MAX_CALLBACK_NUM 128 -typedef int (*irq_callback)(int irqno); - -void plic_irq_enable(int irqno); -void plic_irq_disable(int irqno); -int plic_prio_get(int irqno); -void plic_prio_set(int irqno, int prio); -int plic_register_callback(int irqno, irq_callback callback); -int plic_unregister_callback(int irqno); -int plic_init(void); -int plic_claim(void); -void plic_complete(int irqno); - -int plic_irq_intr(void); - -#endif - diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/plic.h b/ports/risc-v32/gnu/example_build/qemu_virt/plic.h new file mode 120000 index 000000000..f776a3d2a --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/plic.h @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/plic/plic.h \ No newline at end of file diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/test/azrtos_test_tx_gnu_riscv32_qemu.py b/ports/risc-v32/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv32_qemu.py similarity index 100% rename from ports/risc-v32/gnu/example_build/qemu_virt/test/azrtos_test_tx_gnu_riscv32_qemu.py rename to ports/risc-v32/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv32_qemu.py diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/trap.c b/ports/risc-v32/gnu/example_build/qemu_virt/trap.c deleted file mode 100644 index a2733e02a..000000000 --- a/ports/risc-v32/gnu/example_build/qemu_virt/trap.c +++ /dev/null @@ -1,67 +0,0 @@ -#include "csr.h" -#include -#include "uart.h" -#include "hwtimer.h" -#include "plic.h" -#include -#include - -#define OS_IS_INTERUPT(mcause) (mcause & 0x80000000u) -#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT)) -#define OS_IS_TICK_INT(mcause) (mcause == 0x80000007u) -#define OS_IS_SOFT_INT(mcause) (mcause == 0x80000003u) -#define OS_IS_EXT_INT(mcause) (mcause == 0x8000000bu) -#define OS_IS_TRAP_USER(mcause) (mcause == 0x0000000bu) -extern void _tx_timer_interrupt(void); - -extern int uart_putc(int ch); - -static void print_hex(uintptr_t val) -{ - char digits[] = "0123456789ABCDEF"; - uart_putc('0'); - uart_putc('x'); - for(int i = (sizeof(uintptr_t)*2) - 1; i >= 0; i--) { - int d = (val >> (i*4)) & 0xF; - uart_putc(digits[d]); - } - uart_putc('\n'); -} - -void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) -{ - // uart_puts("DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/trap.c, trap_handler\n"); - if(OS_IS_INTERUPT(mcause)) - { - if(OS_IS_TICK_INT(mcause)) - { - hwtimer_handler(); - _tx_timer_interrupt(); - } - else if(OS_IS_EXT_INT(mcause)) - { - int ret = plic_irq_intr(); - if(ret) - { - puts("[INTERRUPT]: handler irq error!"); - while(1) ; - } - } - else - { - puts("[INTERRUPT]: now can't deal with the interrupt!"); - while(1) ; - } - } - else - { - puts("[EXCEPTION] : Unkown Error!!"); - puts("mcause:"); - print_hex(mcause); - puts("mepc:"); - print_hex(mepc); - puts("mtval:"); - print_hex(mtval); - while(1) ; - } -} diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/trap.c b/ports/risc-v32/gnu/example_build/qemu_virt/trap.c new file mode 120000 index 000000000..bdce33054 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/trap.c @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/trap/trap_qemu.c \ No newline at end of file diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/uart.c b/ports/risc-v32/gnu/example_build/qemu_virt/uart.c deleted file mode 100644 index a175b7d25..000000000 --- a/ports/risc-v32/gnu/example_build/qemu_virt/uart.c +++ /dev/null @@ -1,102 +0,0 @@ -#include "uart.h" -#include "csr.h" -#include "plic.h" -#include - -// the UART control registers are memory-mapped -// at address UART0. this macro returns the -// address of one of the registers. -#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg))) - -// the UART control registers. -// some have different meanings for -// read vs write. -// see http://byterunner.com/16550.html -#define RHR 0 // receive holding register (for input bytes) -#define THR 0 // transmit holding register (for output bytes) -#define IER 1 // interrupt enable register -#define IER_RX_ENABLE (1<<0) -#define IER_TX_ENABLE (1<<1) -#define FCR 2 // FIFO control register -#define FCR_FIFO_ENABLE (1<<0) -#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs -#define ISR 2 // interrupt status register -#define LCR 3 // line control register -#define LCR_EIGHT_BITS (3<<0) -#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate -#define LSR 5 // line status register -#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR -#define LSR_TX_IDLE (1<<5) // THR can accept another character to send - -#define ReadReg(reg) (*(Reg(reg))) -#define WriteReg(reg, v) (*(Reg(reg)) = (v)) - -int uart_init(void) -{ - // disable interrupts. - WriteReg(IER, 0x00); - - // special mode to set baud rate. - WriteReg(LCR, LCR_BAUD_LATCH); - - // LSB for baud rate of 38.4K. - WriteReg(0, 0x03); - - // MSB for baud rate of 38.4K. - WriteReg(1, 0x00); - - // leave set-baud mode, - // and set word length to 8 bits, no parity. - WriteReg(LCR, LCR_EIGHT_BITS); - - // reset and enable FIFOs. - WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR); - - // enable transmit and receive interrupts. - // WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE); - - //enable UART0 in PLIC - plic_irq_enable(UART0_IRQ); - - //set UART0 priority in PLIC - plic_prio_set(UART0_IRQ, 1); - - //register callback for UART0 - //plic_register_callback(UART0_IRQ, uart_intr); - puts("[UART0] : Uart Init Done, this is Test output!"); - return 0; -} - -void uart_putc_nolock(int ch) -{ - // wait for Transmit Holding Empty to be set in LSR. - while((ReadReg(LSR) & LSR_TX_IDLE) == 0) - ; - WriteReg(THR, ch); - return; -} - -int uart_putc(int ch) -{ - int intr_enable = riscv_mintr_get(); - riscv_mintr_off(); - uart_putc_nolock(ch); - riscv_mintr_restore(intr_enable); - return 1; -} - -int uart_puts(const char* str) -{ - int i; - int intr_enable = riscv_mintr_get(); - riscv_mintr_off(); - for(i=0;str[i]!=0;i++) - { - uart_putc_nolock(str[i]); - } - uart_putc_nolock('\n'); - riscv_mintr_restore(intr_enable); - return i; -} - - diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/uart.c b/ports/risc-v32/gnu/example_build/qemu_virt/uart.c new file mode 120000 index 000000000..1666c8c8d --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/uart.c @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.c \ No newline at end of file diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/uart.h b/ports/risc-v32/gnu/example_build/qemu_virt/uart.h deleted file mode 100644 index debfd9dfa..000000000 --- a/ports/risc-v32/gnu/example_build/qemu_virt/uart.h +++ /dev/null @@ -1,23 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - -#ifndef RISCV_UART_H -#define RISCV_UART_H - -#define UART0 0x10000000L -#define UART0_IRQ 10 - -#define puts uart_puts -int uart_init(void); -int uart_putc(int ch); -void uart_putc_nolock(int ch); -int uart_puts(const char* str); -#endif diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/uart.h b/ports/risc-v32/gnu/example_build/qemu_virt/uart.h new file mode 120000 index 000000000..aba5ae7b9 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/uart.h @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.h \ No newline at end of file diff --git a/ports/risc-v32/gnu/inc/tx_port.h b/ports/risc-v32/gnu/inc/tx_port.h index 5348a02e3..11e9f87be 100644 --- a/ports/risc-v32/gnu/inc/tx_port.h +++ b/ports/risc-v32/gnu/inc/tx_port.h @@ -47,228 +47,11 @@ #ifndef TX_PORT_H #define TX_PORT_H -#ifndef __ASSEMBLER__ - -/* Include for memset. */ -#include - - -/* Determine if the optional ThreadX user define file should be used. */ - -#ifdef TX_INCLUDE_USER_DEFINE_FILE - - -/* Yes, include the user defines in tx_user.h. The defines in this file may - alternately be defined on the command line. */ - -#include "tx_user.h" -#endif /* TX_INCLUDE_USER_DEFINE_FILE */ - -#endif /* __ASSEMBLER__ */ - - -/* Define ThreadX basic types for this port. */ - -#define VOID void - -#ifndef __ASSEMBLER__ -typedef char CHAR; -typedef unsigned char UCHAR; -typedef int INT; -typedef unsigned int UINT; -typedef long LONG; -typedef unsigned long ULONG; -typedef unsigned long long ULONG64; -typedef short SHORT; -typedef unsigned short USHORT; -#define ULONG64_DEFINED -#endif /* __ASSEMBLER__ */ - - - - -/* Define the priority levels for ThreadX. Legal values range - from 32 to 1024 and MUST be evenly divisible by 32. */ - -#ifndef TX_MAX_PRIORITIES -#define TX_MAX_PRIORITIES 32 -#endif - - -/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during - thread creation is less than this value, the thread create call will return an error. */ - -#ifndef TX_MINIMUM_STACK -#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ -#endif - - -/* Define the system timer thread's default stack size and priority. These are only applicable - if TX_TIMER_PROCESS_IN_ISR is not defined. */ - -#ifndef TX_TIMER_THREAD_STACK_SIZE -#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ -#endif - -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ -#endif - - -/* Define various constants for the ThreadX RISC-V port. */ - -#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ -#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ - - -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock - source constants would be: - -#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) -#define TX_TRACE_TIME_MASK 0x0000FFFFUL - -*/ - -#ifndef TX_TRACE_TIME_SOURCE -#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time -#endif -#ifndef TX_TRACE_TIME_MASK -#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL -#endif - - -/* Define the port specific options for the _tx_build_options variable. This variable indicates - how the ThreadX library was built. */ - -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 - - -/* Define the in-line initialization constant so that modules with in-line - initialization capabilities can prevent their initialization from being - a function call. */ - -#define TX_INLINE_INITIALIZATION - - -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is - disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack - checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING - define is negated, thereby forcing the stack fill which is necessary for the stack checking - logic. */ - -#ifdef TX_ENABLE_STACK_CHECKING -#undef TX_DISABLE_STACK_FILLING -#endif - - -/* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with - existing ThreadX kernel awareness modules. */ - -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 - - -/* Define the port extensions of the remaining ThreadX objects. */ - -#define TX_BLOCK_POOL_EXTENSION -#define TX_BYTE_POOL_EXTENSION -#define TX_EVENT_FLAGS_GROUP_EXTENSION -#define TX_MUTEX_EXTENSION -#define TX_QUEUE_EXTENSION -#define TX_SEMAPHORE_EXTENSION -#define TX_TIMER_EXTENSION - - -/* Define the user extension field of the thread control block. Nothing - additional is needed for this port so it is defined as white space. */ - -#ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION -#endif - - -/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, - tx_thread_shell_entry, and tx_thread_terminate. */ - -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) -#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) - - -/* Define the ThreadX object creation extensions for the remaining objects. */ - -#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) -#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) -#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) -#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) -#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) -#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) -#define TX_TIMER_CREATE_EXTENSION(timer_ptr) - - -/* Define the ThreadX object deletion extensions for the remaining objects. */ - -#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) -#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) -#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) -#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) -#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) -#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) -#define TX_TIMER_DELETE_EXTENSION(timer_ptr) - - -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value - present prior to the disable macro. In most cases, the save area macro - is used to define a local function save area for the disable and restore - macros. */ - -/* Expose helper used to perform an atomic read/modify/write of mstatus. - The helper composes and returns the posture per ThreadX contract. */ -#ifndef __ASSEMBLER__ -UINT _tx_thread_interrupt_control(UINT new_posture); -#endif - -#ifdef TX_DISABLE_INLINE - -#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; - -#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory"); -#define TX_RESTORE { \ - unsigned long _temp_mstatus; \ - __asm__ volatile( \ - "csrc mstatus, 8\n" \ - "andi %0, %1, 8\n" \ - "csrs mstatus, %0" \ - : "=&r" (_temp_mstatus) \ - : "r" (interrupt_save) \ - : "memory"); \ - } - -#else - -#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; - -#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); -#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); - -#endif /* TX_DISABLE_INLINE */ +/* Include shared RISC-V32 port definitions common to all toolchain ports. */ +#include "../../common/tx_port_riscv32_common.h" -/* Define the interrupt lockout macros for each ThreadX object. */ -#define TX_BLOCK_POOL_DISABLE TX_DISABLE -#define TX_BYTE_POOL_DISABLE TX_DISABLE -#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE -#define TX_MUTEX_DISABLE TX_DISABLE -#define TX_QUEUE_DISABLE TX_DISABLE -#define TX_SEMAPHORE_DISABLE TX_DISABLE /* Define automated coverage test extensions for the ThreadX regression test. */ diff --git a/ports/risc-v32/gnu/src/tx_initialize_low_level.S b/ports/risc-v32/gnu/src/tx_initialize_low_level.S index 703466bda..2940f2159 100644 --- a/ports/risc-v32/gnu/src/tx_initialize_low_level.S +++ b/ports/risc-v32/gnu/src/tx_initialize_low_level.S @@ -62,7 +62,7 @@ __tx_free_memory_start: /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ - .global _tx_initialize_low_level + .weak _tx_initialize_low_level .weak _tx_initialize_low_level _tx_initialize_low_level: diff --git a/ports/risc-v32/gnu/src/tx_thread_schedule.S b/ports/risc-v32/gnu/src/tx_thread_schedule.S index 213aa9769..79bfd51a7 100644 --- a/ports/risc-v32/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v32/gnu/src/tx_thread_schedule.S @@ -214,6 +214,7 @@ _tx_thread_schedule_skip_fp_restore: #endif /* Recover standard registers. */ + lw t0, 30*4(sp) // Recover mepc csrw mepc, t0 // Setup mepc li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) @@ -302,6 +303,7 @@ _tx_thread_schedule_solicited_skip_fp_restore: #endif /* Recover standard registers. */ + lw t0, 14*4(sp) // Reload saved mstatus (t0 may hold fcsr if FP was restored) csrw mstatus, t0 // Restore mstatus lw ra, 13*4(sp) // Recover return address diff --git a/ports/risc-v32/gnu/src/tx_thread_system_return.S b/ports/risc-v32/gnu/src/tx_thread_system_return.S index 4090e7b26..20ff25f21 100644 --- a/ports/risc-v32/gnu/src/tx_thread_system_return.S +++ b/ports/risc-v32/gnu/src/tx_thread_system_return.S @@ -69,7 +69,17 @@ _tx_thread_system_return: addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled #endif - /* Store floating point preserved registers. */ + sw zero, 0(sp) // Solicited stack type (store early so slot is always written) + + /* Read and save mstatus first; use it to guard FP register save. */ + csrr t0, mstatus // Pickup current mstatus + sw t0, 14*4(sp) // Save mstatus + + /* Store floating point preserved registers — only if FS != Off. */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + srli t1, t0, 13 // Shift FS field to bits [1:0] + andi t1, t1, 0x3 // Isolate FS bits + beqz t1, _tx_thread_system_return_skip_fp // Skip FP save if FS == Off #if defined(__riscv_float_abi_single) fsw f8, 15*4(sp) // Store fs0 fsw f9, 16*4(sp) // Store fs1 @@ -100,9 +110,10 @@ _tx_thread_system_return: fsd f27, 26*4(sp) // Store fs11 csrr t0, fcsr sw t0, 27*4(sp) // Store fcsr +#endif +_tx_thread_system_return_skip_fp: #endif - sw zero, 0(sp) // Solicited stack type sw ra, 13*4(sp) // Save return address sw s0, 12*4(sp) // Save s0 sw s1, 11*4(sp) // Save s1 @@ -116,9 +127,6 @@ _tx_thread_system_return: sw s9, 3*4(sp) // Save s9 sw s10, 2*4(sp) // Save s10 sw s11, 1*4(sp) // Save s11 - csrr t0, mstatus // Pickup mstatus - sw t0, 14*4(sp) // Save mstatus - /* Lockout interrupts. will be enabled in _tx_thread_schedule */ diff --git a/ports/risc-v64/gnu/CMakeLists.txt b/ports/risc-v64/gnu/CMakeLists.txt index 9357c6970..e51de7355 100644 --- a/ports/risc-v64/gnu/CMakeLists.txt +++ b/ports/risc-v64/gnu/CMakeLists.txt @@ -1,19 +1,6 @@ +include(${CMAKE_CURRENT_LIST_DIR}/../../../cmake/threadx_riscv_port.cmake) -target_sources(${PROJECT_NAME} - PRIVATE - # {{BEGIN_TARGET_SOURCES}} - ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S - # {{END_TARGET_SOURCES}} -) - -target_include_directories(${PROJECT_NAME} - PUBLIC - ${CMAKE_CURRENT_LIST_DIR}/inc +threadx_add_riscv_port( + SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/src + INC_DIR ${CMAKE_CURRENT_LIST_DIR}/inc ) diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh b/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh index 35f7ac5aa..b655820ea 100755 --- a/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh +++ b/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh @@ -13,7 +13,7 @@ riscv64-unknown-elf-gcc \ -ffunction-sections -fdata-sections \ -I../../../../../common/inc \ -I../../inc \ - entry.s \ + entry.S \ tx_initialize_low_level.S \ board.c uart.c hwtimer.c plic.c trap.c demo_threadx.c \ -L../../../../../build -lthreadx \ diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/csr.h b/ports/risc-v64/gnu/example_build/qemu_virt/csr.h deleted file mode 100644 index 83d05afd4..000000000 --- a/ports/risc-v64/gnu/example_build/qemu_virt/csr.h +++ /dev/null @@ -1,375 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -#ifndef RISCV_CSR_H -#define RISCV_CSR_H - - -// Machine Status Register, mstatus -#define MSTATUS_MPP_MASK (3L << 11) // previous mode. -#define MSTATUS_MPP_M (3L << 11) -#define MSTATUS_MPP_S (1L << 11) -#define MSTATUS_MPP_U (0L << 11) -#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable. -#define MSTATUS_MPIE (1L << 7) -#define MSTATUS_FS (1L << 13) -#define MSTATUS_VS (1L << 9) - -// Machine-mode Interrupt Enable -#define MIE_MTIE (1L << 7) -#define MIE_MSIE (1L << 3) -#define MIE_MEIE (1L << 11) -#define MIE_STIE (1L << 5) // supervisor timer -#define MIE_SSIE (1L << 1) -#define MIE_SEIE (1L << 9) - -// Supervisor Status Register, sstatus -#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User -#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable -#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable -#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable -#define SSTATUS_UIE (1L << 0) // User Interrupt Enable -#define SSTATUS_SPIE (1L << 5) -#define SSTATUS_UPIE (1L << 4) - -// Supervisor Interrupt Enable -#define SIE_SEIE (1L << 9) // external -#define SIE_STIE (1L << 5) // timer -#define SIE_SSIE (1L << 1) // software - -#ifndef __ASSEMBLER__ - -#include - -static inline uint64_t riscv_get_core() -{ - uint64_t x; - asm volatile("csrr %0, mhartid" : "=r" (x) ); - return x; -} - -static inline uint64_t riscv_get_mstatus() -{ - uint64_t x; - asm volatile("csrr %0, mstatus" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mstatus(uint64_t x) -{ - asm volatile("csrw mstatus, %0" : : "r" (x)); -} - -// machine exception program counter, holds the -// instruction address to which a return from -// exception will go. -static inline void riscv_writ_mepc(uint64_t x) -{ - asm volatile("csrw mepc, %0" : : "r" (x)); -} - -static inline uint64_t riscv_get_sstatus() -{ - uint64_t x; - asm volatile("csrr %0, sstatus" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_sstatus(uint64_t x) -{ - asm volatile("csrw sstatus, %0" : : "r" (x)); -} - -// Supervisor Interrupt Pending -static inline uint64_t riscv_get_sip() -{ - uint64_t x; - asm volatile("csrr %0, sip" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_sip(uint64_t x) -{ - asm volatile("csrw sip, %0" : : "r" (x)); -} - -static inline uint64_t riscv_get_sie() -{ - uint64_t x; - asm volatile("csrr %0, sie" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_sie(uint64_t x) -{ - asm volatile("csrw sie, %0" : : "r" (x)); -} - -static inline uint64_t riscv_get_mie() -{ - uint64_t x; - asm volatile("csrr %0, mie" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mie(uint64_t x) -{ - asm volatile("csrw mie, %0" : : "r" (x)); -} - -// supervisor exception program counter, holds the -// instruction address to which a return from -// exception will go. -static inline void riscv_writ_sepc(uint64_t x) -{ - asm volatile("csrw sepc, %0" : : "r" (x)); -} - -static inline uint64_t riscv_get_sepc() -{ - uint64_t x; - asm volatile("csrr %0, sepc" : "=r" (x) ); - return x; -} - -// Machine Exception Delegation -static inline uint64_t riscv_get_medeleg() -{ - uint64_t x; - asm volatile("csrr %0, medeleg" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_medeleg(uint64_t x) -{ - asm volatile("csrw medeleg, %0" : : "r" (x)); -} - -// Machine Interrupt Delegation -static inline uint64_t riscv_get_mideleg() -{ - uint64_t x; - asm volatile("csrr %0, mideleg" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_mideleg(uint64_t x) -{ - asm volatile("csrw mideleg, %0" : : "r" (x)); -} - -// Supervisor Trap-Vector Base Address -// low two bits are mode. -static inline void riscv_writ_stvec(uint64_t x) -{ - asm volatile("csrw stvec, %0" : : "r" (x)); -} - -static inline uint64_t riscv_get_stvec() -{ - uint64_t x; - asm volatile("csrr %0, stvec" : "=r" (x) ); - return x; -} - -// Supervisor Timer Comparison Register -static inline uint64_t riscv_get_stimecmp() -{ - uint64_t x; - // asm volatile("csrr %0, stimecmp" : "=r" (x) ); - asm volatile("csrr %0, 0x14d" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_stimecmp(uint64_t x) -{ - // asm volatile("csrw stimecmp, %0" : : "r" (x)); - asm volatile("csrw 0x14d, %0" : : "r" (x)); -} - -// Machine Environment Configuration Register -static inline uint64_t riscv_get_menvcfg() -{ - uint64_t x; - // asm volatile("csrr %0, menvcfg" : "=r" (x) ); - asm volatile("csrr %0, 0x30a" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_menvcfg(uint64_t x) -{ - // asm volatile("csrw menvcfg, %0" : : "r" (x)); - asm volatile("csrw 0x30a, %0" : : "r" (x)); -} - -// Physical Memory Protection -static inline void riscv_writ_pmpcfg0(uint64_t x) -{ - asm volatile("csrw pmpcfg0, %0" : : "r" (x)); -} - -static inline void riscv_writ_pmpaddr0(uint64_t x) -{ - asm volatile("csrw pmpaddr0, %0" : : "r" (x)); -} - -// supervisor address translation and protection; -// holds the address of the page table. -static inline void riscv_writ_satp(uint64_t x) -{ - asm volatile("csrw satp, %0" : : "r" (x)); -} - -static inline uint64_t riscv_get_satp() -{ - uint64_t x; - asm volatile("csrr %0, satp" : "=r" (x) ); - return x; -} - -// Supervisor Trap Cause -static inline uint64_t riscv_get_scause() -{ - uint64_t x; - asm volatile("csrr %0, scause" : "=r" (x) ); - return x; -} - -// Supervisor Trap Value -static inline uint64_t riscv_get_stval() -{ - uint64_t x; - asm volatile("csrr %0, stval" : "=r" (x) ); - return x; -} - -// Machine-mode Counter-Enable -static inline void riscv_writ_mcounteren(uint64_t x) -{ - asm volatile("csrw mcounteren, %0" : : "r" (x)); -} - -static inline uint64_t riscv_get_mcounteren() -{ - uint64_t x; - asm volatile("csrr %0, mcounteren" : "=r" (x) ); - return x; -} - -// machine-mode cycle counter -static inline uint64_t riscv_get_time() -{ - uint64_t x; - asm volatile("csrr %0, time" : "=r" (x) ); - return x; -} - -// enable device interrupts -static inline void riscv_sintr_on() -{ - uint64_t sstatus = riscv_get_sstatus(); - sstatus |= SSTATUS_SIE; - riscv_writ_sstatus(sstatus); -} - -// disable device interrupts -static inline void riscv_sintr_off() -{ - uint64_t sstatus = riscv_get_sstatus(); - sstatus &= (~SSTATUS_SIE); - riscv_writ_sstatus(sstatus); -} - -// are device interrupts enabled? -static inline int riscv_sintr_get() -{ - uint64_t x = riscv_get_sstatus(); - return (x & SSTATUS_SIE) != 0; -} - -static inline void riscv_sintr_restore(int x) -{ - if(x) - riscv_sintr_on(); - else - riscv_sintr_off(); -} - -// enable device interrupts -static inline void riscv_mintr_on() -{ - uint64_t mstatus = riscv_get_mstatus(); - mstatus |= MSTATUS_MIE; - riscv_writ_mstatus(mstatus); -} - -// disable device interrupts -static inline void riscv_mintr_off() -{ - uint64_t mstatus = riscv_get_mstatus(); - mstatus &= (~MSTATUS_MIE); - riscv_writ_mstatus(mstatus); -} - -// are device interrupts enabled? -static inline int riscv_mintr_get() -{ - uint64_t x = riscv_get_mstatus(); - return (x & MSTATUS_MIE) != 0; -} - -static inline void riscv_mintr_restore(int x) -{ - if(x) - riscv_mintr_on(); - else - riscv_mintr_off(); -} - -static inline uint64_t riscv_get_sp() -{ - uint64_t x; - asm volatile("mv %0, sp" : "=r" (x) ); - return x; -} - -// read and write tp, the thread pointer, which xv6 uses to hold -// this core's hartid (core number), the index into cpus[]. -static inline uint64_t riscv_get_tp() -{ - uint64_t x; - asm volatile("mv %0, tp" : "=r" (x) ); - return x; -} - -static inline void riscv_writ_tp(uint64_t x) -{ - asm volatile("mv tp, %0" : : "r" (x)); -} - -static inline uint64_t riscv_get_ra() -{ - uint64_t x; - asm volatile("mv %0, ra" : "=r" (x) ); - return x; -} - -// flush the TLB. -static inline void sfence_vma() -{ - // the zero, zero means flush all TLB entries. - asm volatile("sfence.vma zero, zero"); -} - -#endif // __ASSEMBLER__ - -#endif diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/csr.h b/ports/risc-v64/gnu/example_build/qemu_virt/csr.h new file mode 120000 index 000000000..b5df6f125 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/qemu_virt/csr.h @@ -0,0 +1 @@ +../../../../risc-v_common/inc/csr.h \ No newline at end of file diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/entry.s b/ports/risc-v64/gnu/example_build/qemu_virt/entry.S similarity index 100% rename from ports/risc-v64/gnu/example_build/qemu_virt/entry.s rename to ports/risc-v64/gnu/example_build/qemu_virt/entry.S diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/plic.c b/ports/risc-v64/gnu/example_build/qemu_virt/plic.c deleted file mode 100644 index 01e5c71a4..000000000 --- a/ports/risc-v64/gnu/example_build/qemu_virt/plic.c +++ /dev/null @@ -1,72 +0,0 @@ -#include "plic.h" -#include -irq_callback callbacks[MAX_CALLBACK_NUM]; - -void plic_irq_enable(int irqno) -{ - int hart = riscv_get_core(); - *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno)); - return; -} - -void plic_irq_disable(int irqno) -{ - int hart = riscv_get_core(); - *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno))); - return; -} - -void plic_prio_set(int irqno, int prio) -{ - PLIC_SET_PRIO(irqno, prio); -} - -int plic_prio_get(int irqno) -{ - return PLIC_GET_PRIO(irqno); -} - -int plic_register_callback(int irqno, irq_callback callback) -{ - if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM)) - return -1; - callbacks[irqno] = callback; - return 0; -} - -int plic_unregister_callback(int irqno) -{ - return plic_register_callback(irqno, NULL); -} - -int plic_init(void) -{ - for(int i=0;i - -#define PLIC 0x0c000000L -#define PLIC_PRIORITY (PLIC + 0x0) -#define PLIC_PENDING (PLIC + 0x1000) -#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100) -#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100) -#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000) -#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000) -#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000) -#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000) -#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000) -#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000) - - -#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4)) -#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio)) - -#define MAX_CALLBACK_NUM 128 -typedef int (*irq_callback)(int irqno); - -void plic_irq_enable(int irqno); -void plic_irq_disable(int irqno); -int plic_prio_get(int irqno); -void plic_prio_set(int irqno, int prio); -int plic_register_callback(int irqno, irq_callback callback); -int plic_unregister_callback(int irqno); -int plic_init(void); -int plic_claim(void); -void plic_complete(int irqno); - -int plic_irq_intr(void); - -#endif - diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/plic.h b/ports/risc-v64/gnu/example_build/qemu_virt/plic.h new file mode 120000 index 000000000..f776a3d2a --- /dev/null +++ b/ports/risc-v64/gnu/example_build/qemu_virt/plic.h @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/plic/plic.h \ No newline at end of file diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv64_qemu.py b/ports/risc-v64/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv64_qemu.py new file mode 100644 index 000000000..459fdf217 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv64_qemu.py @@ -0,0 +1,275 @@ +import subprocess +import sys +import os +import argparse +import socket +import select + +def print_content(content): + """Prints content using os.write to handle non-blocking stdout robustly.""" + try: + msg = f"{content}\n".encode('utf-8') + total_len = len(msg) + written = 0 + fd = sys.stdout.fileno() + while written < total_len: + try: + n = os.write(fd, msg[written:]) + written += n + except BlockingIOError: + select.select([], [fd], []) + except Exception: + pass + +def get_free_port(): + """Finds a free TCP port.""" + with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s: + s.bind(('', 0)) + return s.getsockname()[1] + +def run_qemu_test(elf_path, qemu_bin, gdb_bin): + """ + Runs a test cycle using QEMU and GDB. + """ + print(f"Testing ELF: {elf_path}") + print(f"QEMU: {qemu_bin}") + print(f"GDB: {gdb_bin}") + + # Find a free port for GDB connection + gdb_port = get_free_port() + print(f"Using GDB port: {gdb_port}") + + # 1. Start QEMU in the background + qemu_cmd = [ + qemu_bin, + "-M", "virt", + "-nographic", + "-bios", "none", # Disable default OpenSBI + "-kernel", elf_path, + "-gdb", f"tcp::{gdb_port}", "-S", + "-monitor", "none", # Disable monitor + "-serial", "stdio" # Redirect serial output to stdio + ] + + print(f"Starting QEMU: {' '.join(qemu_cmd)}") + qemu_process = subprocess.Popen( + qemu_cmd, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + text=True + ) + + if qemu_process.poll() is not None: + print("QEMU failed to start.") + print(qemu_process.stderr.read()) + return False + + # 2. Create a GDB command file + gdb_cmds = """ +file {elf} +target remote :{port} +set pagination off +set confirm off + +# Setup Breakpoints +break tx_application_define +break thread_0_entry +break thread_6_and_7_entry +break _tx_timer_interrupt + +# Execute to Application Definition +continue + +# Inspect mstatus once thread_0 has started +continue +print/x $mstatus + +# Verify FPU Logic and Register State exercised by thread_6/7 +continue +finish +step +step +step +print/x $mstatus +info registers float +print fpu_test_val + +# Await Timer Interrupt +continue +print "Hit Timer Interrupt" + +# Verify MEPC Integrity - Save State +print/x $mepc +set $saved_pc = $mepc + +# Verify System Timer Before ISR +set $clock_before = _tx_timer_system_clock +print $clock_before + +# Configure Time-Slice Test Conditions +set _tx_timer_time_slice = 1 +set _tx_timer_expired_time_slice = 0 +set $ts_handler_called = 0 + +# Set Breakpoint at Time-Slice Handler with Auto-Continue +tbreak _tx_thread_time_slice +commands + set $ts_handler_called = 1 + continue +end + +# Set Breakpoint at ISR Return Address +set $ret_addr = $ra +tbreak *$ret_addr +continue + +# Verify Time-Slice Handler Was Called +if $ts_handler_called == 1 + print "SUCCESS: Time-slice handler called." +else + print "FAILURE: Time-slice handler NOT called." +end + +# Verify System Timer Increment (Monotonicity) +set $clock_after = _tx_timer_system_clock +print $clock_after + +if $clock_after > $clock_before + print "SUCCESS: System timer incremented." +else + print "FAILURE: System timer did not increment." +end + +# Verify Preemption Logic (Thread Priority) +set $curr_ptr = _tx_thread_current_ptr +set $exec_ptr = _tx_thread_execute_ptr +if $curr_ptr != 0 && $exec_ptr != 0 + set $curr_prio = $curr_ptr->tx_thread_priority + set $exec_prio = $exec_ptr->tx_thread_priority + printf "PREEMPT_CHECK current_prio=%d execute_prio=%d\\n", $curr_prio, $exec_prio + if $exec_prio < $curr_prio + printf "PREEMPT_VERIFIED_OK\\n" + else + printf "PREEMPT_VERIFIED_FAIL_NOT_OBSERVED\\n" + end +else + printf "PREEMPT_VERIFIED_FAIL_NULL\\n" +end + +quit +""".format(port=gdb_port, elf=elf_path) + + gdb_cmd_file = "test_cmds.gdb" + with open(gdb_cmd_file, "w") as f: + f.write(gdb_cmds) + + # 3. Run GDB + gdb_cmd = [ + gdb_bin, + "--batch", + "-x", gdb_cmd_file + ] + + print_content(f"Starting GDB: {' '.join(gdb_cmd)}") + + GDB_TIMEOUT_S = 30 + + try: + gdb_process = subprocess.run( + gdb_cmd, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + text=True, + timeout=GDB_TIMEOUT_S, + ) + + print_content("GDB Output:") + print_content(gdb_process.stdout) + if gdb_process.stderr: + print_content("GDB Error Output:") + print_content(gdb_process.stderr) + + except subprocess.TimeoutExpired as e: + print_content( + f"FAILURE: GDB session exceeded {GDB_TIMEOUT_S}s timeout; " + "likely stuck on a `continue` that never matched a breakpoint." + ) + if e.stdout: + print_content("GDB Output (partial):") + print_content(e.stdout if isinstance(e.stdout, str) + else e.stdout.decode(errors='replace')) + if e.stderr: + print_content("GDB Error Output (partial):") + print_content(e.stderr if isinstance(e.stderr, str) + else e.stderr.decode(errors='replace')) + return False + + except Exception as e: + print_content(f"An error occurred during test execution: {e}") + return False + + finally: + # 4. Clean up + print_content("Stopping QEMU...") + qemu_process.terminate() + try: + qemu_process.wait(timeout=2) + except subprocess.TimeoutExpired: + print_content("QEMU did not terminate gracefully, killing it forcefully.") + qemu_process.kill() + + # Verify results + stdout = gdb_process.stdout + timer_hit = "Breakpoint 4, _tx_timer_interrupt" in stdout + fpu_verified = False + preemption_verified = "PREEMPT_VERIFIED_OK" in stdout + + if "Breakpoint 3, thread_6_and_7_entry" in stdout: + if "1.10" in stdout or "fpu_test_val" in stdout: + print_content("SUCCESS: FPU instructions executed and registers inspected.") + fpu_verified = True + else: + print_content("FAILURE: Hit thread, but failed to inspect FPU. " + "Output does not contain expected value.") + + if timer_hit: + print_content("SUCCESS: Timer Interrupt verified! Hit _tx_timer_interrupt.") + else: + print_content("FAILURE: Did not hit timer interrupt.") + + if preemption_verified: + print_content("SUCCESS: Preemption verified (higher-priority thread " + "preempted a lower-priority one).") + else: + if "PREEMPT_VERIFIED_FAIL_INVERTED" in stdout: + print_content("FAILURE: Preemption inverted -- lower priority " + "thread scheduled over higher priority one.") + elif "PREEMPT_VERIFIED_FAIL_NULL" in stdout: + print_content("FAILURE: Preemption check saw NULL thread pointers.") + elif "PREEMPT_VERIFIED_FAIL_NOT_OBSERVED" in stdout: + print_content("FAILURE: Preemption was not observed within the " + "loop budget.") + else: + print_content("FAILURE: Preemption check did not run to completion.") + + if timer_hit and fpu_verified and preemption_verified: + return True + else: + return False + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Run ThreadX RV64 QEMU/GDB Test") + parser.add_argument("--elf", required=True, help="Path to the kernel ELF file") + parser.add_argument("--qemu", default="qemu-system-riscv64", + help="Path to QEMU binary") + parser.add_argument("--gdb", default="riscv64-unknown-elf-gdb", + help="Path to GDB binary") + + args = parser.parse_args() + + success = run_qemu_test(args.elf, args.qemu, args.gdb) + + if success: + sys.exit(0) + else: + sys.exit(1) diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/trap.c b/ports/risc-v64/gnu/example_build/qemu_virt/trap.c deleted file mode 100644 index 5de9f37a4..000000000 --- a/ports/risc-v64/gnu/example_build/qemu_virt/trap.c +++ /dev/null @@ -1,46 +0,0 @@ -#include "csr.h" -#include -#include "uart.h" -#include "hwtimer.h" -#include "plic.h" -#include -#include - -#define OS_IS_INTERUPT(mcause) (mcause & 0x8000000000000000ull) -#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT)) -#define OS_IS_TICK_INT(mcause) (mcause == 0x8000000000000007ull) -#define OS_IS_SOFT_INT(mcause) (mcause == 0x8000000000000003ull) -#define OS_IS_EXT_INT(mcause) (mcause == 0x800000000000000bull) -#define OS_IS_TRAP_USER(mcause) (mcause == 0x000000000000000bull) -extern void _tx_timer_interrupt(void); - -void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) -{ - if(OS_IS_INTERUPT(mcause)) - { - if(OS_IS_TICK_INT(mcause)) - { - hwtimer_handler(); - _tx_timer_interrupt(); - } - else if(OS_IS_EXT_INT(mcause)) - { - int ret = plic_irq_intr(); - if(ret) - { - puts("[INTERRUPT]: handler irq error!"); - while(1) ; - } - } - else - { - puts("[INTERRUPT]: now can't deal with the interrupt!"); - while(1) ; - } - } - else - { - puts("[EXCEPTION] : Unkown Error!!"); - while(1) ; - } -} diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/trap.c b/ports/risc-v64/gnu/example_build/qemu_virt/trap.c new file mode 120000 index 000000000..bdce33054 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/qemu_virt/trap.c @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/trap/trap_qemu.c \ No newline at end of file diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/uart.c b/ports/risc-v64/gnu/example_build/qemu_virt/uart.c deleted file mode 100644 index eea302032..000000000 --- a/ports/risc-v64/gnu/example_build/qemu_virt/uart.c +++ /dev/null @@ -1,100 +0,0 @@ -#include "uart.h" -#include "csr.h" -#include "plic.h" -#include - -// the UART control registers are memory-mapped -// at address UART0. this macro returns the -// address of one of the registers. -#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg))) - -// the UART control registers. -// some have different meanings for -// read vs write. -// see http://byterunner.com/16550.html -#define RHR 0 // receive holding register (for input bytes) -#define THR 0 // transmit holding register (for output bytes) -#define IER 1 // interrupt enable register -#define IER_RX_ENABLE (1<<0) -#define IER_TX_ENABLE (1<<1) -#define FCR 2 // FIFO control register -#define FCR_FIFO_ENABLE (1<<0) -#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs -#define ISR 2 // interrupt status register -#define LCR 3 // line control register -#define LCR_EIGHT_BITS (3<<0) -#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate -#define LSR 5 // line status register -#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR -#define LSR_TX_IDLE (1<<5) // THR can accept another character to send - -#define ReadReg(reg) (*(Reg(reg))) -#define WriteReg(reg, v) (*(Reg(reg)) = (v)) - -int uart_init(void) -{ - // disable interrupts. - WriteReg(IER, 0x00); - - // special mode to set baud rate. - WriteReg(LCR, LCR_BAUD_LATCH); - - // LSB for baud rate of 38.4K. - WriteReg(0, 0x03); - - // MSB for baud rate of 38.4K. - WriteReg(1, 0x00); - - // leave set-baud mode, - // and set word length to 8 bits, no parity. - WriteReg(LCR, LCR_EIGHT_BITS); - - // reset and enable FIFOs. - WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR); - - // enable transmit and receive interrupts. - // WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE); - - //enable UART0 in PLIC - plic_irq_enable(UART0_IRQ); - - //set UART0 priority in PLIC - plic_prio_set(UART0_IRQ, 1); - - //register callback for UART0 - //plic_register_callback(UART0_IRQ, uart_intr); - puts("[UART0] : Uart Init Done, this is Test output!"); - return 0; -} - -static inline void uart_putc_nolock(int ch) -{ - // wait for Transmit Holding Empty to be set in LSR. - while((ReadReg(LSR) & LSR_TX_IDLE) == 0) - ; - WriteReg(THR, ch); - return; -} - -int uart_putc(int ch) -{ - int intr_enable = riscv_mintr_get(); - riscv_mintr_off(); - uart_putc_nolock(ch); - riscv_mintr_restore(intr_enable); - return 1; -} - -int uart_puts(const char* str) -{ - int i; - int intr_enable = riscv_mintr_get(); - riscv_mintr_off(); - for(i=0;str[i]!=0;i++) - { - uart_putc_nolock(str[i]); - } - uart_putc_nolock('\n'); - riscv_mintr_restore(intr_enable); - return i; -} diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/uart.c b/ports/risc-v64/gnu/example_build/qemu_virt/uart.c new file mode 120000 index 000000000..1666c8c8d --- /dev/null +++ b/ports/risc-v64/gnu/example_build/qemu_virt/uart.c @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.c \ No newline at end of file diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/uart.h b/ports/risc-v64/gnu/example_build/qemu_virt/uart.h deleted file mode 100644 index 824f0b568..000000000 --- a/ports/risc-v64/gnu/example_build/qemu_virt/uart.h +++ /dev/null @@ -1,22 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - -#ifndef RISCV_UART_H -#define RISCV_UART_H - -#define UART0 0x10000000L -#define UART0_IRQ 10 - -#define puts uart_puts -int uart_init(void); -int uart_putc(int ch); -int uart_puts(const char* str); -#endif diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/uart.h b/ports/risc-v64/gnu/example_build/qemu_virt/uart.h new file mode 120000 index 000000000..aba5ae7b9 --- /dev/null +++ b/ports/risc-v64/gnu/example_build/qemu_virt/uart.h @@ -0,0 +1 @@ +../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.h \ No newline at end of file diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h index 9bf167043..4df55a6a1 100644 --- a/ports/risc-v64/gnu/inc/tx_port.h +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -72,6 +72,13 @@ #define VOID void +/* IMPORTANT: On this RV64 port LONG/ULONG are intentionally 32-bit (int / + * unsigned int), NOT 64-bit. ThreadX's internal data model requires LONG + * and ULONG to be exactly 4 bytes so that control-block layouts, queue + * message sizes, and the binary API remain identical to all other ThreadX + * ports. Do NOT change these to long/unsigned long — that mistake was + * already corrected once (see PR #534). Use ULONG64 for 64-bit values. */ + #ifndef __ASSEMBLER__ typedef char CHAR; typedef unsigned char UCHAR; @@ -88,6 +95,22 @@ typedef unsigned short USHORT; #define ALIGN_TYPE_DEFINED typedef unsigned long long ALIGN_TYPE; +/* On RV64, ULONG is 32-bit but pointers are 64-bit. Store the thread + pointer in the timer's VOID * extension field so _tx_thread_timeout + can recover it without truncation. This mirrors the win64 port. */ +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr; + +/* TX_TIMER_EXTENSION_PTR_DEFINED signals to portable code (e.g. tests) + that the timer extension pointer mechanism is in use on this port. */ +#define TX_TIMER_EXTENSION_PTR_DEFINED + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_extension_ptr = (VOID *) (t); + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) TX_PARAMETER_NOT_USED(timeout_input); \ + (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr; + /* Define the priority levels for ThreadX. Legal values range from 32 to 1024 and MUST be evenly divisible by 32. */ diff --git a/ports/risc-v_common/example_build/plic/plic.c b/ports/risc-v_common/example_build/plic/plic.c new file mode 100644 index 000000000..21421a725 --- /dev/null +++ b/ports/risc-v_common/example_build/plic/plic.c @@ -0,0 +1,79 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "plic.h" +#include + +irq_callback callbacks[MAX_CALLBACK_NUM]; + +void plic_irq_enable(int irqno) +{ + int hart = riscv_get_core(); + *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno)); +} + +void plic_irq_disable(int irqno) +{ + int hart = riscv_get_core(); + *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno))); +} + +void plic_prio_set(int irqno, int prio) +{ + PLIC_SET_PRIO(irqno, prio); +} + +int plic_prio_get(int irqno) +{ + return PLIC_GET_PRIO(irqno); +} + +int plic_register_callback(int irqno, irq_callback callback) +{ + if (!(irqno >= 0 && irqno < MAX_CALLBACK_NUM)) + return -1; + callbacks[irqno] = callback; + return 0; +} + +int plic_unregister_callback(int irqno) +{ + return plic_register_callback(irqno, NULL); +} + +int plic_init(void) +{ + for (int i = 0; i < MAX_CALLBACK_NUM; i++) + callbacks[i] = NULL; + return 0; +} + +int plic_claim(void) +{ + int hart = riscv_get_core(); + return (*(uint32_t*)PLIC_MCLAIM(hart)); +} + +void plic_complete(int irqno) +{ + int hart = riscv_get_core(); + *(uint32_t*)(PLIC_MCOMPLETE(hart)) = (uint32_t)irqno; +} + +int plic_irq_intr(void) +{ + int ret = -1; + int irqno = plic_claim(); + if (callbacks[irqno] != NULL) + ret = (callbacks[irqno])(irqno); + plic_complete(irqno); + return ret; +} diff --git a/ports/risc-v_common/example_build/plic/plic.h b/ports/risc-v_common/example_build/plic/plic.h new file mode 100644 index 000000000..29d29c57c --- /dev/null +++ b/ports/risc-v_common/example_build/plic/plic.h @@ -0,0 +1,48 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_PLIC_H +#define RISCV_PLIC_H + +#include "csr.h" +#include + +#define PLIC 0x0c000000L +#define PLIC_PRIORITY (PLIC + 0x0) +#define PLIC_PENDING (PLIC + 0x1000) +#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100) +#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100) +#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000) +#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000) +#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000) +#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000) +#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000) +#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000) + +#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4)) +#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio)) + +#define MAX_CALLBACK_NUM 128 +typedef int (*irq_callback)(int irqno); + +void plic_irq_enable(int irqno); +void plic_irq_disable(int irqno); +int plic_prio_get(int irqno); +void plic_prio_set(int irqno, int prio); +int plic_register_callback(int irqno, irq_callback callback); +int plic_unregister_callback(int irqno); +int plic_init(void); +int plic_claim(void); +void plic_complete(int irqno); + +int plic_irq_intr(void); + +#endif /* RISCV_PLIC_H */ diff --git a/ports/risc-v_common/example_build/trap/trap_qemu.c b/ports/risc-v_common/example_build/trap/trap_qemu.c new file mode 100644 index 000000000..c9d8a0033 --- /dev/null +++ b/ports/risc-v_common/example_build/trap/trap_qemu.c @@ -0,0 +1,92 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* Trap handler for QEMU virt machine (RV32 and RV64). + * + * mcause constants use __riscv_xlen to resolve correctly for both ISAs: + * RV32: interrupt bit = bit 31 (0x80000000) + * RV64: interrupt bit = bit 63 (0x8000000000000000) + */ + +#include "csr.h" +#include +#include "uart.h" +#include "hwtimer.h" +#include "plic.h" +#include +#include + +#define MCAUSE_INT_BIT ((uintptr_t)1 << (__riscv_xlen - 1)) + +#define OS_IS_INTERRUPT(mcause) ((mcause) & MCAUSE_INT_BIT) +#define OS_IS_TICK_INT(mcause) ((mcause) == (MCAUSE_INT_BIT | 7u)) +#define OS_IS_SOFT_INT(mcause) ((mcause) == (MCAUSE_INT_BIT | 3u)) +#define OS_IS_EXT_INT(mcause) ((mcause) == (MCAUSE_INT_BIT | 11u)) +#define OS_IS_TRAP_USER(mcause) ((mcause) == 11u) + +extern void _tx_timer_interrupt(void); + +#ifdef TX_RISCV_TRAP_DEBUG +static void print_hex(uintptr_t val) +{ + const char digits[] = "0123456789ABCDEF"; + uart_putc('0'); + uart_putc('x'); + for (int i = (int)(sizeof(uintptr_t) * 2) - 1; i >= 0; i--) + { + int d = (val >> (i * 4)) & 0xF; + uart_putc(digits[d]); + } + uart_putc('\n'); +} +#endif /* TX_RISCV_TRAP_DEBUG */ + +void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) +{ + if (OS_IS_INTERRUPT(mcause)) + { + if (OS_IS_TICK_INT(mcause)) + { + hwtimer_handler(); + _tx_timer_interrupt(); + } + else if (OS_IS_EXT_INT(mcause)) + { + int ret = plic_irq_intr(); + if (ret) + { + puts("[INTERRUPT]: handler irq error!"); + while (1) ; + } + } + else + { + puts("[INTERRUPT]: now can't deal with the interrupt!"); + while (1) ; + } + } + else + { + puts("[EXCEPTION] : Unknown Error!!"); +#ifdef TX_RISCV_TRAP_DEBUG + puts("mcause:"); + print_hex(mcause); + puts("mepc:"); + print_hex(mepc); + puts("mtval:"); + print_hex(mtval); +#else + (void)mepc; + (void)mtval; +#endif /* TX_RISCV_TRAP_DEBUG */ + while (1) ; + } +} diff --git a/ports/risc-v_common/example_build/uart/uart_qemu_ns16550.c b/ports/risc-v_common/example_build/uart/uart_qemu_ns16550.c new file mode 100644 index 000000000..ce9a8adbc --- /dev/null +++ b/ports/risc-v_common/example_build/uart/uart_qemu_ns16550.c @@ -0,0 +1,99 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +/* NS16550-compatible UART driver for QEMU virt machine (RV32 and RV64). */ + +#include "uart.h" +#include "csr.h" +#include "plic.h" +#include + +/* Memory-mapped UART control registers. */ +#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg))) + +#define RHR 0 /* receive holding register (for input bytes) */ +#define THR 0 /* transmit holding register (for output bytes) */ +#define IER 1 /* interrupt enable register */ +#define IER_RX_ENABLE (1<<0) +#define IER_TX_ENABLE (1<<1) +#define FCR 2 /* FIFO control register */ +#define FCR_FIFO_ENABLE (1<<0) +#define FCR_FIFO_CLEAR (3<<1) /* clear the content of the two FIFOs */ +#define ISR 2 /* interrupt status register */ +#define LCR 3 /* line control register */ +#define LCR_EIGHT_BITS (3<<0) +#define LCR_BAUD_LATCH (1<<7) /* special mode to set baud rate */ +#define LSR 5 /* line status register */ +#define LSR_RX_READY (1<<0) /* input is waiting to be read from RHR */ +#define LSR_TX_IDLE (1<<5) /* THR can accept another character to send */ + +#define ReadReg(reg) (*(Reg(reg))) +#define WriteReg(reg, v) (*(Reg(reg)) = (v)) + +int uart_init(void) +{ + /* Disable interrupts. */ + WriteReg(IER, 0x00); + + /* Special mode to set baud rate. */ + WriteReg(LCR, LCR_BAUD_LATCH); + + /* LSB for baud rate of 38.4K. */ + WriteReg(0, 0x03); + + /* MSB for baud rate of 38.4K. */ + WriteReg(1, 0x00); + + /* Leave set-baud mode, set word length to 8 bits, no parity. */ + WriteReg(LCR, LCR_EIGHT_BITS); + + /* Reset and enable FIFOs. */ + WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR); + + /* Enable UART0 in PLIC. */ + plic_irq_enable(UART0_IRQ); + + /* Set UART0 priority in PLIC. */ + plic_prio_set(UART0_IRQ, 1); + + puts("[UART0] : Uart Init Done, this is Test output!"); + return 0; +} + +/* uart_putc_nolock is static inline so it can be inlined into uart_putc + and uart_puts without introducing a public symbol. */ +static inline void uart_putc_nolock(int ch) +{ + while ((ReadReg(LSR) & LSR_TX_IDLE) == 0) + ; + WriteReg(THR, ch); +} + +int uart_putc(int ch) +{ + int intr_enable = riscv_mintr_get(); + riscv_mintr_off(); + uart_putc_nolock(ch); + riscv_mintr_restore(intr_enable); + return 1; +} + +int uart_puts(const char *str) +{ + int i; + int intr_enable = riscv_mintr_get(); + riscv_mintr_off(); + for (i = 0; str[i] != 0; i++) + uart_putc_nolock(str[i]); + uart_putc_nolock('\n'); + riscv_mintr_restore(intr_enable); + return i; +} diff --git a/ports/risc-v_common/example_build/uart/uart_qemu_ns16550.h b/ports/risc-v_common/example_build/uart/uart_qemu_ns16550.h new file mode 100644 index 000000000..67fc9ed9a --- /dev/null +++ b/ports/risc-v_common/example_build/uart/uart_qemu_ns16550.h @@ -0,0 +1,22 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_UART_H +#define RISCV_UART_H + +#define UART0 0x10000000L +#define UART0_IRQ 10 + +#define puts uart_puts +int uart_init(void); +int uart_putc(int ch); +int uart_puts(const char *str); +#endif /* RISCV_UART_H */ diff --git a/ports/risc-v_common/inc/csr.h b/ports/risc-v_common/inc/csr.h new file mode 100644 index 000000000..a4495a46f --- /dev/null +++ b/ports/risc-v_common/inc/csr.h @@ -0,0 +1,356 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +#ifndef RISCV_CSR_H +#define RISCV_CSR_H + + +/* Machine Status Register, mstatus */ +#define MSTATUS_MPP_MASK (3L << 11) /* previous mode. */ +#define MSTATUS_MPP_M (3L << 11) +#define MSTATUS_MPP_S (1L << 11) +#define MSTATUS_MPP_U (0L << 11) +#define MSTATUS_MIE (1L << 3) /* machine-mode interrupt enable. */ +#define MSTATUS_MPIE (1L << 7) +#define MSTATUS_FS (1L << 13) /* floating-point status. */ +#define MSTATUS_VS (1L << 9) /* vector status (RVV). */ + +/* Machine-mode Interrupt Enable */ +#define MIE_MTIE (1L << 7) +#define MIE_MSIE (1L << 3) +#define MIE_MEIE (1L << 11) +#define MIE_STIE (1L << 5) /* supervisor timer */ +#define MIE_SSIE (1L << 1) +#define MIE_SEIE (1L << 9) + +/* Supervisor Status Register, sstatus */ +#define SSTATUS_SPP (1L << 8) /* Previous mode, 1=Supervisor, 0=User */ +#define SSTATUS_SPIE (1L << 5) /* Supervisor Previous Interrupt Enable */ +#define SSTATUS_UPIE (1L << 4) /* User Previous Interrupt Enable */ +#define SSTATUS_SIE (1L << 1) /* Supervisor Interrupt Enable */ +#define SSTATUS_UIE (1L << 0) /* User Interrupt Enable */ + +/* Supervisor Interrupt Enable */ +#define SIE_SEIE (1L << 9) /* external */ +#define SIE_STIE (1L << 5) /* timer */ +#define SIE_SSIE (1L << 1) /* software */ + +#ifndef __ASSEMBLER__ + +#include + +/* All CSR accessor functions use uintptr_t so this header works for both + RV32 (uintptr_t = uint32_t) and RV64 (uintptr_t = uint64_t). */ + +static inline uintptr_t riscv_get_core(void) +{ + uintptr_t x; + asm volatile("csrr %0, mhartid" : "=r" (x)); + return x; +} + +static inline uintptr_t riscv_get_mstatus(void) +{ + uintptr_t x; + asm volatile("csrr %0, mstatus" : "=r" (x)); + return x; +} + +static inline void riscv_writ_mstatus(uintptr_t x) +{ + asm volatile("csrw mstatus, %0" : : "r" (x)); +} + +static inline void riscv_writ_mepc(uintptr_t x) +{ + asm volatile("csrw mepc, %0" : : "r" (x)); +} + +static inline uintptr_t riscv_get_sstatus(void) +{ + uintptr_t x; + asm volatile("csrr %0, sstatus" : "=r" (x)); + return x; +} + +static inline void riscv_writ_sstatus(uintptr_t x) +{ + asm volatile("csrw sstatus, %0" : : "r" (x)); +} + +/* Supervisor Interrupt Pending */ +static inline uintptr_t riscv_get_sip(void) +{ + uintptr_t x; + asm volatile("csrr %0, sip" : "=r" (x)); + return x; +} + +static inline void riscv_writ_sip(uintptr_t x) +{ + asm volatile("csrw sip, %0" : : "r" (x)); +} + +static inline uintptr_t riscv_get_sie(void) +{ + uintptr_t x; + asm volatile("csrr %0, sie" : "=r" (x)); + return x; +} + +static inline void riscv_writ_sie(uintptr_t x) +{ + asm volatile("csrw sie, %0" : : "r" (x)); +} + +static inline uintptr_t riscv_get_mie(void) +{ + uintptr_t x; + asm volatile("csrr %0, mie" : "=r" (x)); + return x; +} + +static inline void riscv_writ_mie(uintptr_t x) +{ + asm volatile("csrw mie, %0" : : "r" (x)); +} + +/* Supervisor exception program counter */ +static inline void riscv_writ_sepc(uintptr_t x) +{ + asm volatile("csrw sepc, %0" : : "r" (x)); +} + +static inline uintptr_t riscv_get_sepc(void) +{ + uintptr_t x; + asm volatile("csrr %0, sepc" : "=r" (x)); + return x; +} + +/* Machine Exception Delegation */ +static inline uintptr_t riscv_get_medeleg(void) +{ + uintptr_t x; + asm volatile("csrr %0, medeleg" : "=r" (x)); + return x; +} + +static inline void riscv_writ_medeleg(uintptr_t x) +{ + asm volatile("csrw medeleg, %0" : : "r" (x)); +} + +/* Machine Interrupt Delegation */ +static inline uintptr_t riscv_get_mideleg(void) +{ + uintptr_t x; + asm volatile("csrr %0, mideleg" : "=r" (x)); + return x; +} + +static inline void riscv_writ_mideleg(uintptr_t x) +{ + asm volatile("csrw mideleg, %0" : : "r" (x)); +} + +/* Supervisor Trap-Vector Base Address */ +static inline void riscv_writ_stvec(uintptr_t x) +{ + asm volatile("csrw stvec, %0" : : "r" (x)); +} + +static inline uintptr_t riscv_get_stvec(void) +{ + uintptr_t x; + asm volatile("csrr %0, stvec" : "=r" (x)); + return x; +} + +/* Supervisor Timer Comparison Register */ +static inline uintptr_t riscv_get_stimecmp(void) +{ + uintptr_t x; + asm volatile("csrr %0, 0x14d" : "=r" (x)); + return x; +} + +static inline void riscv_writ_stimecmp(uintptr_t x) +{ + asm volatile("csrw 0x14d, %0" : : "r" (x)); +} + +/* Machine Environment Configuration Register */ +static inline uintptr_t riscv_get_menvcfg(void) +{ + uintptr_t x; + asm volatile("csrr %0, 0x30a" : "=r" (x)); + return x; +} + +static inline void riscv_writ_menvcfg(uintptr_t x) +{ + asm volatile("csrw 0x30a, %0" : : "r" (x)); +} + +/* Physical Memory Protection */ +static inline void riscv_writ_pmpcfg0(uintptr_t x) +{ + asm volatile("csrw pmpcfg0, %0" : : "r" (x)); +} + +static inline void riscv_writ_pmpaddr0(uintptr_t x) +{ + asm volatile("csrw pmpaddr0, %0" : : "r" (x)); +} + +/* Supervisor address translation and protection */ +static inline void riscv_writ_satp(uintptr_t x) +{ + asm volatile("csrw satp, %0" : : "r" (x)); +} + +static inline uintptr_t riscv_get_satp(void) +{ + uintptr_t x; + asm volatile("csrr %0, satp" : "=r" (x)); + return x; +} + +/* Supervisor Trap Cause */ +static inline uintptr_t riscv_get_scause(void) +{ + uintptr_t x; + asm volatile("csrr %0, scause" : "=r" (x)); + return x; +} + +/* Supervisor Trap Value */ +static inline uintptr_t riscv_get_stval(void) +{ + uintptr_t x; + asm volatile("csrr %0, stval" : "=r" (x)); + return x; +} + +/* Machine-mode Counter-Enable */ +static inline void riscv_writ_mcounteren(uintptr_t x) +{ + asm volatile("csrw mcounteren, %0" : : "r" (x)); +} + +static inline uintptr_t riscv_get_mcounteren(void) +{ + uintptr_t x; + asm volatile("csrr %0, mcounteren" : "=r" (x)); + return x; +} + +static inline uintptr_t riscv_get_time(void) +{ + uintptr_t x; + asm volatile("csrr %0, time" : "=r" (x)); + return x; +} + +static inline void riscv_sintr_on(void) +{ + uintptr_t sstatus = riscv_get_sstatus(); + sstatus |= SSTATUS_SIE; + riscv_writ_sstatus(sstatus); +} + +static inline void riscv_sintr_off(void) +{ + uintptr_t sstatus = riscv_get_sstatus(); + sstatus &= (~(uintptr_t)SSTATUS_SIE); + riscv_writ_sstatus(sstatus); +} + +static inline int riscv_sintr_get(void) +{ + uintptr_t x = riscv_get_sstatus(); + return (x & SSTATUS_SIE) != 0; +} + +static inline void riscv_sintr_restore(int x) +{ + if (x) + riscv_sintr_on(); + else + riscv_sintr_off(); +} + +static inline void riscv_mintr_on(void) +{ + uintptr_t mstatus = riscv_get_mstatus(); + mstatus |= MSTATUS_MIE; + riscv_writ_mstatus(mstatus); +} + +static inline void riscv_mintr_off(void) +{ + uintptr_t mstatus = riscv_get_mstatus(); + mstatus &= (~(uintptr_t)MSTATUS_MIE); + riscv_writ_mstatus(mstatus); +} + +static inline int riscv_mintr_get(void) +{ + uintptr_t x = riscv_get_mstatus(); + return (x & MSTATUS_MIE) != 0; +} + +static inline void riscv_mintr_restore(int x) +{ + if (x) + riscv_mintr_on(); + else + riscv_mintr_off(); +} + +static inline uintptr_t riscv_get_sp(void) +{ + uintptr_t x; + asm volatile("mv %0, sp" : "=r" (x)); + return x; +} + +/* Thread pointer (tp), used by some ports for hart-local storage. */ +static inline uintptr_t riscv_get_tp(void) +{ + uintptr_t x; + asm volatile("mv %0, tp" : "=r" (x)); + return x; +} + +static inline void riscv_writ_tp(uintptr_t x) +{ + asm volatile("mv tp, %0" : : "r" (x)); +} + +static inline uintptr_t riscv_get_ra(void) +{ + uintptr_t x; + asm volatile("mv %0, ra" : "=r" (x)); + return x; +} + +/* Flush all TLB entries. */ +static inline void sfence_vma(void) +{ + asm volatile("sfence.vma zero, zero"); +} + +#endif /* __ASSEMBLER__ */ + +#endif /* RISCV_CSR_H */ diff --git a/test/smp/cmake/regression/CMakeLists.txt b/test/smp/cmake/regression/CMakeLists.txt index 7d258e50e..b448ae3e3 100644 --- a/test/smp/cmake/regression/CMakeLists.txt +++ b/test/smp/cmake/regression/CMakeLists.txt @@ -135,9 +135,13 @@ add_custom_command( DEPENDS ${PORT_LOW_LEVEL_SOURCE} ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.cmake COMMENT "Generating tx_initialize_low_level.c for test") +add_library(test_weak_defaults OBJECT ${TESTCONTROL_WEAK_DEFAULTS_SOURCE}) +target_link_libraries(test_weak_defaults PRIVATE azrtos::threadx_smp) +target_compile_definitions(test_weak_defaults PRIVATE CTEST BATCH_TEST + TEST_STACK_SIZE_PRINTF=4096) + add_library(test_utility OBJECT ${GENERATED_LOW_LEVEL_SOURCE} - ${SOURCE_DIR}/testcontrol.c - ${TESTCONTROL_WEAK_DEFAULTS_SOURCE}) + ${SOURCE_DIR}/testcontrol.c) target_link_libraries(test_utility PRIVATE azrtos::threadx_smp) target_compile_definitions(test_utility PRIVATE CTEST BATCH_TEST TEST_STACK_SIZE_PRINTF=4096) @@ -146,9 +150,11 @@ foreach(test_case ${regression_test_cases}) get_filename_component(test_name ${test_case} NAME_WE) if(test_name STREQUAL "threadx_initialize_kernel_setup_test") - add_executable(${test_name} ${test_case}) + add_executable(${test_name} ${test_case} $) else() - add_executable(${test_name} ${test_case} $) + add_executable(${test_name} ${test_case} + $ + $) target_compile_definitions(${test_name} PRIVATE CTEST BATCH_TEST TEST_STACK_SIZE_PRINTF=4096) endif() diff --git a/test/tx/cmake/regression/CMakeLists.txt b/test/tx/cmake/regression/CMakeLists.txt index 25029ab91..34fba1b2c 100644 --- a/test/tx/cmake/regression/CMakeLists.txt +++ b/test/tx/cmake/regression/CMakeLists.txt @@ -120,9 +120,13 @@ add_custom_command( DEPENDS ${PORT_LOW_LEVEL_SOURCE} ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.cmake COMMENT "Generating tx_initialize_low_level.c for test") +add_library(test_weak_defaults OBJECT ${TESTCONTROL_WEAK_DEFAULTS_SOURCE}) +target_compile_definitions(test_weak_defaults PRIVATE CTEST BATCH_TEST + TEST_STACK_SIZE_PRINTF=4096) +target_link_libraries(test_weak_defaults PRIVATE azrtos::threadx) + add_library(test_utility OBJECT ${GENERATED_LOW_LEVEL_SOURCE} - ${SOURCE_DIR}/testcontrol.c - ${TESTCONTROL_WEAK_DEFAULTS_SOURCE}) + ${SOURCE_DIR}/testcontrol.c) target_compile_definitions(test_utility PRIVATE CTEST BATCH_TEST TEST_STACK_SIZE_PRINTF=4096) target_link_libraries(test_utility PRIVATE azrtos::threadx) @@ -131,9 +135,11 @@ foreach(test_case ${regression_test_cases}) get_filename_component(test_name ${test_case} NAME_WE) if(test_name STREQUAL "threadx_initialize_kernel_setup_test") - add_executable(${test_name} ${test_case}) + add_executable(${test_name} ${test_case} $) else() - add_executable(${test_name} ${test_case} $) + add_executable(${test_name} ${test_case} + $ + $) target_compile_definitions(${test_name} PRIVATE CTEST BATCH_TEST TEST_STACK_SIZE_PRINTF=4096) endif() diff --git a/test/tx/cmake/riscv/CMakeLists.txt b/test/tx/cmake/riscv/CMakeLists.txt index 0352622d0..a4f7e7e84 100644 --- a/test/tx/cmake/riscv/CMakeLists.txt +++ b/test/tx/cmake/riscv/CMakeLists.txt @@ -70,7 +70,15 @@ target_compile_options( -Wunused -Wuninitialized -Wmissing-declarations - -Wconversion + # -Wconversion is disabled for RV64 because ULONG is intentionally 32-bit + # (for ThreadX ABI compatibility across all ports) while sizeof(VOID*) and + # sizeof(ALIGN_TYPE) return size_t (64-bit on RV64). This design matches + # ARM Cortex-A72 and other 64-bit ports. The implicit conversions in + # common/src/ byte/block pool code trigger -Wconversion warnings. Since + # pool sizes are inherently limited to 32-bit (ULONG), the conversions + # are safe. No other 64-bit port with 32-bit ULONG has been tested with + # -Wconversion enabled, so we disable it here for RV64. + $<$:-Wconversion> -Wpointer-arith -Wlogical-op -Waggregate-return diff --git a/test/tx/cmake/riscv/regression/CMakeLists.txt b/test/tx/cmake/riscv/regression/CMakeLists.txt index 5e381b894..80b6e3bdb 100644 --- a/test/tx/cmake/riscv/regression/CMakeLists.txt +++ b/test/tx/cmake/riscv/regression/CMakeLists.txt @@ -120,6 +120,18 @@ set(standalone_test_cases ${SOURCE_DIR}/threadx_initialize_kernel_setup_test.c ) +set(WEAK_DEFAULTS_SOURCE ${CMAKE_CURRENT_LIST_DIR}/../../../../shared/regression/testcontrol_weak_defaults.c) + +# Weak defaults must be an OBJECT library so all objects are always linked +# into each test executable, even though they only provide weak symbols. +# A STATIC library would have the linker skip them (weak defs don't satisfy +# undefined strong references during archive scanning). +add_library(riscv_test_weak_defaults OBJECT ${WEAK_DEFAULTS_SOURCE}) +target_compile_definitions(riscv_test_weak_defaults PRIVATE + CTEST BATCH_TEST EXTERNAL_EXIT TEST_STACK_SIZE_PRINTF=4096) +target_compile_options(riscv_test_weak_defaults PRIVATE -include stdlib.h) +target_link_libraries(riscv_test_weak_defaults PRIVATE azrtos::threadx) + # Build testcontrol.c as a static library (no patched tx_initialize_low_level # needed — the BSP provides it directly with test_interrupt_dispatch hook). add_library(riscv_test_utility ${SOURCE_DIR}/testcontrol.c) @@ -146,7 +158,7 @@ endfunction() # Regular tests (linked with testcontrol). foreach(test_case ${regression_test_cases}) get_filename_component(test_name ${test_case} NAME_WE) - add_executable(${test_name} ${test_case}) + add_executable(${test_name} ${test_case} $) target_link_libraries(${test_name} PRIVATE -Wl,--whole-archive riscv_bsp -Wl,--no-whole-archive riscv_test_utility) @@ -156,7 +168,7 @@ endforeach() # Standalone tests (provide their own main, no testcontrol). foreach(test_case ${standalone_test_cases}) get_filename_component(test_name ${test_case} NAME_WE) - add_executable(${test_name} ${test_case}) + add_executable(${test_name} ${test_case} $) target_link_libraries(${test_name} PRIVATE -Wl,--whole-archive riscv_bsp -Wl,--no-whole-archive azrtos::threadx) diff --git a/test/tx/regression/threadx_thread_basic_execution_test.c b/test/tx/regression/threadx_thread_basic_execution_test.c index a0f65a8cc..5bcf1a2ae 100644 --- a/test/tx/regression/threadx_thread_basic_execution_test.c +++ b/test/tx/regression/threadx_thread_basic_execution_test.c @@ -390,12 +390,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_suspending = TX_TRUE; test_thread.tx_thread_delayed_suspend = TX_TRUE; -#if defined(_WIN64) +#if defined(_WIN64) || defined(TX_TIMER_EXTENSION_PTR_DEFINED) { TX_TIMER_INTERNAL timeout_timer; TX_TIMER_INTERNAL *saved_expired_timer_ptr; - TX_MEMSET(&timeout_timer, 0, sizeof(TX_TIMER_INTERNAL)); saved_expired_timer_ptr = _tx_timer_expired_timer_ptr; _tx_timer_expired_timer_ptr = &timeout_timer; From 80cbaadfafc53b0888cf1fe3548fd4b4c093af7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Wed, 27 May 2026 11:33:28 -0400 Subject: [PATCH 23/29] cmake: rename rv32 toolchain file to riscv32-unknown-elf-rv32imc.cmake (#537) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Renamed cmake/riscv64-gcc-rv32imc.cmake to the accurate name cmake/riscv32-unknown-elf-rv32imc.cmake and switch the compiler from riscv64-unknown-elf-gcc to riscv32-unknown-elf-gcc. The riscv-collab riscv64-elf toolchain has no rv32 multilib and will fail to link soft-float and integer helpers (__clzsi2, __muldf3, etc.) when building for -march=rv32imc_zicsr -mabi=ilp32. The dedicated riscv32-unknown-elf-gcc (riscv-collab riscv32-elf release, installed to /opt/riscv by scripts/install_riscv.sh) ships the correct native rv32/ilp32 libgcc — analogous to arm-none-eabi-gcc for Cortex-M. The old filename is kept as a two-line compatibility alias that includes the new file, so any out-of-tree users who hardcode the old path still work. Also update: - core_v_mcu/build.sh: reference new cmake filename - core_v_mcu/README.md: update prerequisites table and toolchain docs Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- cmake/riscv32-unknown-elf-rv32imc.cmake | 69 ++++++++++++++++ cmake/riscv64-gcc-rv32imc.cmake | 78 +------------------ .../gnu/example_build/core_v_mcu/README.md | 27 ++++--- .../gnu/example_build/core_v_mcu/build.sh | 2 +- 4 files changed, 87 insertions(+), 89 deletions(-) create mode 100644 cmake/riscv32-unknown-elf-rv32imc.cmake diff --git a/cmake/riscv32-unknown-elf-rv32imc.cmake b/cmake/riscv32-unknown-elf-rv32imc.cmake new file mode 100644 index 000000000..7e9356898 --- /dev/null +++ b/cmake/riscv32-unknown-elf-rv32imc.cmake @@ -0,0 +1,69 @@ +# /*************************************************************************** +# * Copyright (C) 2026 Eclipse ThreadX contributors +# * +# * This program and the accompanying materials are made available under the +# * terms of the MIT License which is available at +# * https://opensource.org/licenses/MIT. +# * +# * SPDX-License-Identifier: MIT +# ***************************************************************************/ + +# CMake toolchain file for CORE-V MCU (CV32E40P, RV32IMC) +# +# Uses the dedicated riscv32-unknown-elf-gcc bare-metal toolchain from +# riscv-collab (riscv32-elf-ubuntu-24.04-gcc.tar.xz, installs to /opt/riscv). +# This is the correct toolchain for RV32 bare-metal targets — analogous to +# arm-none-eabi-gcc for Cortex-M. It ships a native rv32/ilp32 libgcc with +# all soft-float and integer helpers (__clzsi2, __muldf3, etc.) built for the +# correct ABI. +# +# Do NOT use riscv64-unknown-elf-gcc for this target: the riscv-collab +# riscv64-elf toolchain is built without rv32 multilib and will produce +# missing-symbol linker errors with -nodefaultlibs. +# +# Install both toolchains with: bash scripts/install_riscv.sh +# +# Target ISA : rv32imc_zicsr (integer, multiply, compressed, Zicsr) +# ABI : ilp32 (32-bit int/long/ptr, no hardware FP) +# Code model : medlow (addresses in [0, 2 GiB)) + +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR riscv) + +set(THREADX_ARCH "risc-v32") +set(THREADX_TOOLCHAIN "gnu") + +set(ARCH_FLAGS "-march=rv32imc_zicsr -mabi=ilp32 -mcmodel=medlow") +set(CFLAGS "${ARCH_FLAGS}") +set(ASFLAGS "${ARCH_FLAGS}") +set(LDFLAGS "${ARCH_FLAGS}") + +# Dedicated riscv32 bare-metal toolchain (riscv-collab riscv32-elf release). +set(CMAKE_C_COMPILER riscv32-unknown-elf-gcc) +set(CMAKE_CXX_COMPILER riscv32-unknown-elf-g++) +set(AS riscv32-unknown-elf-as) +set(AR riscv32-unknown-elf-ar) +set(OBJCOPY riscv32-unknown-elf-objcopy) +set(OBJDUMP riscv32-unknown-elf-objdump) +set(SIZE riscv32-unknown-elf-size) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) + +# Use static library for compiler feature probing (no linker script yet) +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${CFLAGS}" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags") + +set(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug flags") +set(CMAKE_CXX_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "cxx debug flags") +set(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug flags") + +set(CMAKE_C_FLAGS_RELEASE "-Os" CACHE INTERNAL "c release flags") +set(CMAKE_CXX_FLAGS_RELEASE "-Os" CACHE INTERNAL "cxx release flags") +set(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release flags") diff --git a/cmake/riscv64-gcc-rv32imc.cmake b/cmake/riscv64-gcc-rv32imc.cmake index aa19b6245..d3d50115d 100644 --- a/cmake/riscv64-gcc-rv32imc.cmake +++ b/cmake/riscv64-gcc-rv32imc.cmake @@ -1,76 +1,2 @@ -# /*************************************************************************** -# * Copyright (C) 2026 Eclipse ThreadX contributors -# * -# * This program and the accompanying materials are made available under the -# * terms of the MIT License which is available at -# * https://opensource.org/licenses/MIT. -# * -# * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). -# * The AI-generated portions may be considered public domain (CC0-1.0) -# * and not subject to the project's licence. The human contributor has -# * reviewed and verified that the code is correct. -# * -# * SPDX-License-Identifier: MIT and CC0-1.0 -# ***************************************************************************/ - -# CMake toolchain file for CORE-V MCU (CV32E40P, RV32IMC) -# -# Uses the riscv64-unknown-elf-gcc cross-compiler to produce rv32imc/ilp32 -# bare-metal firmware. The riscv-collab toolchain (installed to /opt/riscv by -# scripts/install_riscv.sh) is used by default. The Ubuntu package -# gcc-riscv64-unknown-elf also works and can be installed via install_deps.sh. -# -# Note: the riscv-collab toolchain is built without multilib, so it does not -# ship an rv32/ilp32 libgcc. The CORE-V MCU BSP provides a weak __clzsi2 -# fallback in bsp/clz.c to satisfy any __builtin_clz() calls without relying -# on libgcc. -# -# Target ISA : rv32imc_zicsr (integer, multiply, compressed, Zicsr) -# ABI : ilp32 (32-bit int/long/ptr, no hardware FP) -# Code model : medlow (addresses in [0, 2 GiB)) - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_SYSTEM_PROCESSOR riscv) - -set(THREADX_ARCH "risc-v32") -set(THREADX_TOOLCHAIN "gnu") - -set(ARCH_FLAGS "-march=rv32imc_zicsr -mabi=ilp32 -mcmodel=medlow") -set(CFLAGS "${ARCH_FLAGS}") -set(ASFLAGS "${ARCH_FLAGS}") -set(LDFLAGS "${ARCH_FLAGS}") - -# Toolchain binaries: riscv64-unknown-elf-gcc cross-compiler. -# The riscv-collab toolchain (scripts/install_riscv.sh → /opt/riscv/bin) is the -# preferred choice. The Ubuntu package (gcc-riscv64-unknown-elf, install via -# install_deps.sh) is also supported. Both are searched via PATH so whichever -# comes first is used; ensure /opt/riscv/bin precedes /usr/bin if you want the -# riscv-collab toolchain. -set(CMAKE_C_COMPILER riscv64-unknown-elf-gcc) -set(CMAKE_CXX_COMPILER riscv64-unknown-elf-g++) -set(AS riscv64-unknown-elf-as) -set(AR riscv64-unknown-elf-ar) -set(OBJCOPY riscv64-unknown-elf-objcopy) -set(OBJDUMP riscv64-unknown-elf-objdump) -set(SIZE riscv64-unknown-elf-size) - -set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) - -# Use static library for compiler feature probing (no linker script yet) -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags") -set(CMAKE_CXX_FLAGS "${CFLAGS}" CACHE INTERNAL "cxx compiler flags") -set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__" CACHE INTERNAL "asm compiler flags") -set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags") - -set(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug flags") -set(CMAKE_CXX_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "cxx debug flags") -set(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug flags") - -set(CMAKE_C_FLAGS_RELEASE "-Os" CACHE INTERNAL "c release flags") -set(CMAKE_CXX_FLAGS_RELEASE "-Os" CACHE INTERNAL "cxx release flags") -set(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release flags") +# This file is a compatibility alias. Use riscv32-unknown-elf-rv32imc.cmake. +include(${CMAKE_CURRENT_LIST_DIR}/riscv32-unknown-elf-rv32imc.cmake) diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/README.md b/ports/risc-v32/gnu/example_build/core_v_mcu/README.md index d94759d00..d2b8a8442 100644 --- a/ports/risc-v32/gnu/example_build/core_v_mcu/README.md +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/README.md @@ -57,15 +57,18 @@ Or install individually: | Tool | Minimum version | Notes | |------|----------------|-------| -| `riscv64-unknown-elf-gcc` | 13.x | `apt install gcc-riscv64-unknown-elf binutils-riscv64-unknown-elf` | +| `riscv32-unknown-elf-gcc` | 15.x | riscv-collab `riscv32-elf` release — run `bash scripts/install_riscv.sh` | | CMake | 3.15 | `apt install cmake` | | Ninja | 1.10 | `apt install ninja-build` | | OpenOCD | 0.12 | `apt install openocd` | -| GDB | any multiarch | `apt install gdb-multiarch` — Ubuntu does not ship `riscv64-unknown-elf-gdb` | +| GDB | any multiarch | `apt install gdb-multiarch` — Ubuntu does not ship `riscv32-unknown-elf-gdb` | -> **Note:** There is no `riscv32-unknown-elf-gcc` package required. The -> `riscv64-unknown-elf-gcc` compiler generates RV32 code when passed -> `-march=rv32imc_zicsr -mabi=ilp32`, as configured by the toolchain file. +> **Note:** Use the dedicated `riscv32-unknown-elf-gcc` bare-metal toolchain +> (riscv-collab `riscv32-elf` release, installs to `/opt/riscv`). This is +> the RV32 equivalent of `arm-none-eabi-gcc` and ships a native rv32/ilp32 +> libgcc with all required soft-float and integer helpers. Do **not** use +> `riscv64-unknown-elf-gcc` — the riscv-collab riscv64-elf toolchain has no +> rv32 multilib and will produce missing-symbol linker errors. --- @@ -221,19 +224,19 @@ build/demo_threadx.map — linker map ```bash THREADX_ROOT=$(realpath ../../../../..) cmake -B build -G Ninja \ - -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv64-gcc-rv32imc.cmake" \ + -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv32-unknown-elf-rv32imc.cmake" \ . cmake --build build ``` ### Toolchain file -`${THREADX_ROOT}/cmake/riscv64-gcc-rv32imc.cmake` sets: +`${THREADX_ROOT}/cmake/riscv32-unknown-elf-rv32imc.cmake` sets: ``` -CMAKE_C_COMPILER riscv64-unknown-elf-gcc -CMAKE_ASM_COMPILER riscv64-unknown-elf-gcc -CMAKE_OBJCOPY riscv64-unknown-elf-objcopy +CMAKE_C_COMPILER riscv32-unknown-elf-gcc +CMAKE_ASM_COMPILER riscv32-unknown-elf-gcc +CMAKE_OBJCOPY riscv32-unknown-elf-objcopy CMAKE_C_FLAGS -march=rv32imc_zicsr -mabi=ilp32 -mcmodel=medlow ``` @@ -285,7 +288,7 @@ port 3333 (GDB) and 4444 (telnet). In a second terminal: ```bash -riscv64-unknown-elf-gdb --command=gdb_init +riscv32-unknown-elf-gdb --command=gdb_init ``` `gdb_init` connects to OpenOCD, loads the ELF, sets a breakpoint at `main`, and @@ -485,7 +488,7 @@ bash deploy.sh --debug ``` The script starts OpenOCD in the background, waits for it to become ready, -then drives `riscv64-unknown-elf-gdb` to load the ELF. OpenOCD is always +then drives `riscv32-unknown-elf-gdb` to load the ELF. OpenOCD is always stopped on exit (including Ctrl-C). --- diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh b/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh index fe78a8e64..c2ccfc559 100755 --- a/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh @@ -4,6 +4,6 @@ SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" THREADX_ROOT="${SCRIPT_DIR}/../../../../.." cmake -B "${SCRIPT_DIR}/build" \ -G Ninja \ - -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv64-gcc-rv32imc.cmake" \ + -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv32-unknown-elf-rv32imc.cmake" \ "${SCRIPT_DIR}" cmake --build "${SCRIPT_DIR}/build" From 6061c43f96dcaf6b5588861f247dae98493a9eee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Wed, 27 May 2026 12:00:47 -0400 Subject: [PATCH 24/29] Removed clz.c workaround; use riscv32-unknown-elf toolchain (#538) bsp/clz.c provided a weak __clzsi2 fallback to work around the missing rv32 multilib in the riscv-collab riscv64-unknown-elf toolchain. Since cmake/riscv32-unknown-elf-rv32imc.cmake now uses the dedicated riscv32- unknown-elf-gcc toolchain (riscv-collab riscv32-elf release), which ships a native rv32/ilp32 libgcc with all required helpers, the workaround is no longer needed. Remove bsp/clz.c and its entry in CMakeLists.txt. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- .../example_build/core_v_mcu/CMakeLists.txt | 1 - .../gnu/example_build/core_v_mcu/bsp/clz.c | 29 ------------------- 2 files changed, 30 deletions(-) delete mode 100644 ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt b/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt index 6946b3474..662914d1a 100644 --- a/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt @@ -21,7 +21,6 @@ set(SRCS ${CORE_V_MCU_DIR}/crt0.S ${CORE_V_MCU_DIR}/vectors.S ${CORE_V_MCU_DIR}/tx_initialize_low_level.S - ${CORE_V_MCU_DIR}/bsp/clz.c ${CORE_V_MCU_DIR}/bsp/irq.c ${CORE_V_MCU_DIR}/bsp/timer_irq.c ${CORE_V_MCU_DIR}/bsp/fll.c diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c b/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c deleted file mode 100644 index ef3cb23ba..000000000 --- a/ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c +++ /dev/null @@ -1,29 +0,0 @@ -/* clz.c — portable fallback for __clzsi2 (count leading zeros, 32-bit) - * - * The riscv-collab bare-metal toolchain (riscv64-unknown-elf from /opt/riscv) - * is built without multilib and does not ship an rv32/ilp32 libgcc. As a - * result __clzsi2, which GCC emits for __builtin_clz() on targets without a - * hardware CLZ instruction, is missing at link time. - * - * This file provides a weak definition so that the build is self-contained - * with any RISC-V bare-metal toolchain. When a toolchain does ship the symbol - * in libgcc (e.g. the Ubuntu gcc-riscv64-unknown-elf package), the libgcc copy - * will take precedence over this weak one. - */ - -#include - -__attribute__((weak)) -int __clzsi2(uint32_t x) -{ - if (x == 0U) - return 32; - - int n = 0; - if ((x & 0xFFFF0000U) == 0U) { n += 16; x <<= 16; } - if ((x & 0xFF000000U) == 0U) { n += 8; x <<= 8; } - if ((x & 0xF0000000U) == 0U) { n += 4; x <<= 4; } - if ((x & 0xC0000000U) == 0U) { n += 2; x <<= 2; } - if ((x & 0x80000000U) == 0U) { n += 1; } - return n; -} From d4b9448f84a108ff027bae1731394fda1a33aeea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Wed, 27 May 2026 17:06:37 -0400 Subject: [PATCH 25/29] Added riscv-none-elf-rv32imc toolchain file for xPack (risc-v32) (#539) Add cmake/riscv-none-elf-rv32imc.cmake targeting the xPack riscv-none-elf-gcc toolchain with rv32imc_zicsr/ilp32 ABI for bare-metal CORE-V MCU builds. Update cmake/riscv32-unknown-elf-rv32imc.cmake to correctly target rv32gc/ilp32d (matching riscv-collab riscv32-elf ABI) for QEMU regression tests. Update cmake/riscv64-gcc-rv32imc.cmake compat alias to include the new riscv-none-elf-rv32imc.cmake. Update CORE-V MCU example_build: build.sh exports xPack PATH, install_deps.sh downloads xPack 15.2.0-1, README.md reflects new toolchain name/path. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- cmake/riscv-none-elf-rv32imc.cmake | 71 +++++++++++++++++++ cmake/riscv32-unknown-elf-rv32imc.cmake | 52 ++++++++++---- cmake/riscv64-gcc-rv32imc.cmake | 4 +- .../gnu/example_build/core_v_mcu/README.md | 30 ++++---- .../gnu/example_build/core_v_mcu/build.sh | 8 ++- .../example_build/core_v_mcu/install_deps.sh | 45 +++++++++--- 6 files changed, 168 insertions(+), 42 deletions(-) create mode 100644 cmake/riscv-none-elf-rv32imc.cmake diff --git a/cmake/riscv-none-elf-rv32imc.cmake b/cmake/riscv-none-elf-rv32imc.cmake new file mode 100644 index 000000000..647d8099f --- /dev/null +++ b/cmake/riscv-none-elf-rv32imc.cmake @@ -0,0 +1,71 @@ +# /*************************************************************************** +# * Copyright (C) 2026 Eclipse ThreadX contributors +# * +# * This program and the accompanying materials are made available under the +# * terms of the MIT License which is available at +# * https://opensource.org/licenses/MIT. +# * +# * SPDX-License-Identifier: MIT +# ***************************************************************************/ + +# CMake toolchain file for bare-metal RV32IMC targets (e.g. CORE-V MCU / CV32E40P) +# +# Uses the xPack riscv-none-elf-gcc toolchain: +# https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack +# +# This is a cross-platform (Linux/macOS/Windows), multilib-capable toolchain +# analogous to arm-none-eabi-gcc. Its multilib includes rv32imc/ilp32 +# (soft-float), so -lgcc resolves correctly without any distro package. +# +# Install via: bash ports/risc-v32/gnu/example_build/core_v_mcu/install_deps.sh +# (downloads the latest xPack release to /opt/xpack-riscv-none-elf-gcc/) +# +# Do NOT use riscv32-unknown-elf-gcc (riscv-collab riscv32-elf release) for +# this target: that toolchain is built --disable-multilib --with-abi=ilp32d, +# so its libgcc only provides ilp32d (hardware FP) helpers and cannot link +# rv32imc/ilp32 soft-float objects. +# +# Target ISA : rv32imc_zicsr (integer, multiply, compressed, Zicsr) +# ABI : ilp32 (32-bit int/long/ptr, soft-float) +# Code model : medlow (addresses in [0, 2 GiB)) + +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR riscv) + +set(THREADX_ARCH "risc-v32") +set(THREADX_TOOLCHAIN "gnu") + +set(ARCH_FLAGS "-march=rv32imc_zicsr -mabi=ilp32 -mcmodel=medlow") +set(CFLAGS "${ARCH_FLAGS}") +set(ASFLAGS "${ARCH_FLAGS}") +set(LDFLAGS "${ARCH_FLAGS}") + +# xPack riscv-none-elf multilib toolchain. +set(CMAKE_C_COMPILER riscv-none-elf-gcc) +set(CMAKE_CXX_COMPILER riscv-none-elf-g++) +set(AS riscv-none-elf-as) +set(AR riscv-none-elf-ar) +set(OBJCOPY riscv-none-elf-objcopy) +set(OBJDUMP riscv-none-elf-objdump) +set(SIZE riscv-none-elf-size) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) + +# Use static library for compiler feature probing (no linker script yet) +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${CFLAGS}" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags") + +set(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug flags") +set(CMAKE_CXX_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "cxx debug flags") +set(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug flags") + +set(CMAKE_C_FLAGS_RELEASE "-Os" CACHE INTERNAL "c release flags") +set(CMAKE_CXX_FLAGS_RELEASE "-Os" CACHE INTERNAL "cxx release flags") +set(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release flags") diff --git a/cmake/riscv32-unknown-elf-rv32imc.cmake b/cmake/riscv32-unknown-elf-rv32imc.cmake index 7e9356898..0109799f2 100644 --- a/cmake/riscv32-unknown-elf-rv32imc.cmake +++ b/cmake/riscv32-unknown-elf-rv32imc.cmake @@ -8,24 +8,26 @@ # * SPDX-License-Identifier: MIT # ***************************************************************************/ -# CMake toolchain file for CORE-V MCU (CV32E40P, RV32IMC) +# CMake toolchain file for RV32GC targets (QEMU virt, etc.) # # Uses the dedicated riscv32-unknown-elf-gcc bare-metal toolchain from -# riscv-collab (riscv32-elf-ubuntu-24.04-gcc.tar.xz, installs to /opt/riscv). -# This is the correct toolchain for RV32 bare-metal targets — analogous to -# arm-none-eabi-gcc for Cortex-M. It ships a native rv32/ilp32 libgcc with -# all soft-float and integer helpers (__clzsi2, __muldf3, etc.) built for the -# correct ABI. +# riscv-collab (riscv32-elf-ubuntu-24.04-gcc.tar.xz, installs to /opt/riscv +# via scripts/install_riscv.sh). # -# Do NOT use riscv64-unknown-elf-gcc for this target: the riscv-collab -# riscv64-elf toolchain is built without rv32 multilib and will produce -# missing-symbol linker errors with -nodefaultlibs. +# IMPORTANT: the riscv-collab riscv32-elf toolchain is built +# --disable-multilib --with-abi=ilp32d, so its libgcc only provides +# ilp32d (hardware double-FP) helpers. This cmake file therefore targets +# rv32gc/ilp32d, which matches the toolchain's built-in ABI and works +# correctly with QEMU virt (which emulates hardware FP). # -# Install both toolchains with: bash scripts/install_riscv.sh +# Do NOT use this file for bare-metal targets that lack hardware FP (e.g. +# CV32E40P, rv32imc). For those, use cmake/riscv64-ubuntu-rv32imc.cmake +# which calls the Ubuntu gcc-riscv64-unknown-elf package — a multilib build +# that includes the rv32im/ilp32 (soft-float) libgcc variant. # -# Target ISA : rv32imc_zicsr (integer, multiply, compressed, Zicsr) -# ABI : ilp32 (32-bit int/long/ptr, no hardware FP) -# Code model : medlow (addresses in [0, 2 GiB)) +# Target ISA : rv32gc (integer, multiply, atomics, FP, compressed, Zicsr) +# ABI : ilp32d (32-bit int/long/ptr, hardware double-precision FP) +# Code model : medlow (addresses in [0, 2 GiB)) set(CMAKE_SYSTEM_NAME Generic) set(CMAKE_SYSTEM_PROCESSOR riscv) @@ -33,7 +35,7 @@ set(CMAKE_SYSTEM_PROCESSOR riscv) set(THREADX_ARCH "risc-v32") set(THREADX_TOOLCHAIN "gnu") -set(ARCH_FLAGS "-march=rv32imc_zicsr -mabi=ilp32 -mcmodel=medlow") +set(ARCH_FLAGS "-march=rv32gc -mabi=ilp32d -mcmodel=medlow") set(CFLAGS "${ARCH_FLAGS}") set(ASFLAGS "${ARCH_FLAGS}") set(LDFLAGS "${ARCH_FLAGS}") @@ -67,3 +69,25 @@ set(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug flags") set(CMAKE_C_FLAGS_RELEASE "-Os" CACHE INTERNAL "c release flags") set(CMAKE_CXX_FLAGS_RELEASE "-Os" CACHE INTERNAL "cxx release flags") set(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release flags") + + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) + +# Use static library for compiler feature probing (no linker script yet) +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${CFLAGS}" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags") + +set(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug flags") +set(CMAKE_CXX_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "cxx debug flags") +set(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug flags") + +set(CMAKE_C_FLAGS_RELEASE "-Os" CACHE INTERNAL "c release flags") +set(CMAKE_CXX_FLAGS_RELEASE "-Os" CACHE INTERNAL "cxx release flags") +set(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release flags") diff --git a/cmake/riscv64-gcc-rv32imc.cmake b/cmake/riscv64-gcc-rv32imc.cmake index d3d50115d..b0916a2fd 100644 --- a/cmake/riscv64-gcc-rv32imc.cmake +++ b/cmake/riscv64-gcc-rv32imc.cmake @@ -1,2 +1,2 @@ -# This file is a compatibility alias. Use riscv32-unknown-elf-rv32imc.cmake. -include(${CMAKE_CURRENT_LIST_DIR}/riscv32-unknown-elf-rv32imc.cmake) +# This file is a compatibility alias. Use riscv-none-elf-rv32imc.cmake. +include(${CMAKE_CURRENT_LIST_DIR}/riscv-none-elf-rv32imc.cmake) diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/README.md b/ports/risc-v32/gnu/example_build/core_v_mcu/README.md index d2b8a8442..41f45dab6 100644 --- a/ports/risc-v32/gnu/example_build/core_v_mcu/README.md +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/README.md @@ -57,18 +57,18 @@ Or install individually: | Tool | Minimum version | Notes | |------|----------------|-------| -| `riscv32-unknown-elf-gcc` | 15.x | riscv-collab `riscv32-elf` release — run `bash scripts/install_riscv.sh` | +| `riscv-none-elf-gcc` | 15.x | xPack riscv-none-elf-gcc — run `bash install_deps.sh` | | CMake | 3.15 | `apt install cmake` | | Ninja | 1.10 | `apt install ninja-build` | | OpenOCD | 0.12 | `apt install openocd` | -| GDB | any multiarch | `apt install gdb-multiarch` — Ubuntu does not ship `riscv32-unknown-elf-gdb` | +| GDB | any multiarch | `apt install gdb-multiarch` | -> **Note:** Use the dedicated `riscv32-unknown-elf-gcc` bare-metal toolchain -> (riscv-collab `riscv32-elf` release, installs to `/opt/riscv`). This is -> the RV32 equivalent of `arm-none-eabi-gcc` and ships a native rv32/ilp32 -> libgcc with all required soft-float and integer helpers. Do **not** use -> `riscv64-unknown-elf-gcc` — the riscv-collab riscv64-elf toolchain has no -> rv32 multilib and will produce missing-symbol linker errors. +> **Note:** Use the [xPack riscv-none-elf-gcc](https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack) +> toolchain — a cross-platform (Linux/macOS/Windows) multilib bare-metal +> toolchain analogous to `arm-none-eabi-gcc`. Its multilib includes +> rv32imc/ilp32 (soft-float) libgcc required for the CV32E40P. Do **not** +> use `riscv32-unknown-elf-gcc` (riscv-collab) — that release is built +> `--disable-multilib --with-abi=ilp32d` and cannot link soft-float objects. --- @@ -224,19 +224,19 @@ build/demo_threadx.map — linker map ```bash THREADX_ROOT=$(realpath ../../../../..) cmake -B build -G Ninja \ - -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv32-unknown-elf-rv32imc.cmake" \ + -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv-none-elf-rv32imc.cmake" \ . cmake --build build ``` ### Toolchain file -`${THREADX_ROOT}/cmake/riscv32-unknown-elf-rv32imc.cmake` sets: +`${THREADX_ROOT}/cmake/riscv-none-elf-rv32imc.cmake` sets: ``` -CMAKE_C_COMPILER riscv32-unknown-elf-gcc -CMAKE_ASM_COMPILER riscv32-unknown-elf-gcc -CMAKE_OBJCOPY riscv32-unknown-elf-objcopy +CMAKE_C_COMPILER riscv-none-elf-gcc +CMAKE_ASM_COMPILER riscv-none-elf-gcc +CMAKE_OBJCOPY riscv-none-elf-objcopy CMAKE_C_FLAGS -march=rv32imc_zicsr -mabi=ilp32 -mcmodel=medlow ``` @@ -288,7 +288,7 @@ port 3333 (GDB) and 4444 (telnet). In a second terminal: ```bash -riscv32-unknown-elf-gdb --command=gdb_init +riscv-none-elf-gdb --command=gdb_init ``` `gdb_init` connects to OpenOCD, loads the ELF, sets a breakpoint at `main`, and @@ -488,7 +488,7 @@ bash deploy.sh --debug ``` The script starts OpenOCD in the background, waits for it to become ready, -then drives `riscv32-unknown-elf-gdb` to load the ELF. OpenOCD is always +then drives `riscv-none-elf-gdb` to load the ELF. OpenOCD is always stopped on exit (including Ctrl-C). --- diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh b/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh index c2ccfc559..2e1bb844b 100755 --- a/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh @@ -1,9 +1,15 @@ #!/bin/bash set -e + +XPACK_GCC_DIR=/opt/xpack-riscv-none-elf-gcc-15.2.0-1 +if [ -d "${XPACK_GCC_DIR}/bin" ]; then + export PATH="${XPACK_GCC_DIR}/bin:${PATH}" +fi + SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" THREADX_ROOT="${SCRIPT_DIR}/../../../../.." cmake -B "${SCRIPT_DIR}/build" \ -G Ninja \ - -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv32-unknown-elf-rv32imc.cmake" \ + -DCMAKE_TOOLCHAIN_FILE="${THREADX_ROOT}/cmake/riscv-none-elf-rv32imc.cmake" \ "${SCRIPT_DIR}" cmake --build "${SCRIPT_DIR}/build" diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/install_deps.sh b/ports/risc-v32/gnu/example_build/core_v_mcu/install_deps.sh index b4cd46a8a..d01926653 100755 --- a/ports/risc-v32/gnu/example_build/core_v_mcu/install_deps.sh +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/install_deps.sh @@ -6,11 +6,7 @@ # * terms of the MIT License which is available at # * https://opensource.org/licenses/MIT. # * -# * AI Disclosure: This file was largely AI-generated by Copilot (Sonnet 4.6). -# * The AI-generated portions may be considered public domain (CC0-1.0) -# * and not subject to the project's licence. -# * -# * SPDX-License-Identifier: MIT AND CC0-1.0 +# * SPDX-License-Identifier: MIT # ***************************************************************************/ # install_deps.sh -- Install Linux build/debug dependencies for the CORE-V MCU ThreadX port. @@ -18,6 +14,10 @@ # Supported: Ubuntu 20.04 / 22.04 / 24.04 and Debian derivatives. # Run as a regular user; sudo is invoked internally where needed. # +# Installs: +# - xPack riscv-none-elf-gcc (multilib bare-metal toolchain, rv32imc/ilp32 capable) +# - cmake, ninja-build, gdb-multiarch, openocd, usbutils +# # Usage: # bash install_deps.sh @@ -28,11 +28,21 @@ info() { echo "[INFO] $*"; } command -v apt-get >/dev/null 2>&1 || die "This script requires apt-get (Ubuntu/Debian)." -PACKAGES=( +# --------------------------------------------------------------------------- +# xPack riscv-none-elf-gcc +# Cross-platform multilib toolchain (Linux/macOS/Windows). +# Includes rv32imc/ilp32 (soft-float) libgcc — required for CV32E40P. +# See: https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack +# --------------------------------------------------------------------------- +XPACK_VERSION="15.2.0-1" +XPACK_TARBALL="xpack-riscv-none-elf-gcc-${XPACK_VERSION}-linux-x64.tar.gz" +XPACK_URL="https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v${XPACK_VERSION}/${XPACK_TARBALL}" +XPACK_INSTALL_DIR="/opt/xpack-riscv-none-elf-gcc-${XPACK_VERSION}" +XPACK_BIN="${XPACK_INSTALL_DIR}/bin" + +APT_PACKAGES=( cmake ninja-build - gcc-riscv64-unknown-elf - binutils-riscv64-unknown-elf gdb-multiarch openocd usbutils @@ -42,12 +52,27 @@ PACKAGES=( info "Updating package lists ..." sudo apt-get update -qq -info "Installing: ${PACKAGES[*]}" -sudo apt-get install -y "${PACKAGES[@]}" +info "Installing apt packages: ${APT_PACKAGES[*]}" +sudo apt-get install -y "${APT_PACKAGES[@]}" +if [ -x "${XPACK_BIN}/riscv-none-elf-gcc" ]; then + info "xPack riscv-none-elf-gcc ${XPACK_VERSION} already installed at ${XPACK_INSTALL_DIR}" +else + info "Downloading xPack riscv-none-elf-gcc ${XPACK_VERSION} ..." + wget --no-verbose "${XPACK_URL}" -O "/tmp/${XPACK_TARBALL}" + sudo mkdir -p "${XPACK_INSTALL_DIR}" + sudo tar xzf "/tmp/${XPACK_TARBALL}" -C /opt + rm "/tmp/${XPACK_TARBALL}" + info "Installed to ${XPACK_INSTALL_DIR}" +fi + +info "" +info "Add the toolchain to your PATH:" +info " export PATH=${XPACK_BIN}:\$PATH" info "" info "All dependencies installed." info "" info "Next steps:" info " 1. Run scripts/setup_opella.sh to configure udev rules for the Ashling Opella LD." info " 2. (WSL only) Follow the usbipd-win instructions printed by setup_opella.sh." + From 518127b2e9d4f5fb4d9fad5b278cc8daf983b688 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Fri, 29 May 2026 08:50:52 -0400 Subject: [PATCH 26/29] cmake: fixed THREADX_ARCH undefined when building as standalone library (#540) CMake loads the toolchain file during the first project() call. Variables set in the toolchain (THREADX_ARCH, THREADX_TOOLCHAIN) were therefore not visible before project() was invoked. Commit 2c16114a moved project() after those checks to conditionally select LANGUAGES and CMAKE_TRY_COMPILE_TARGET_TYPE for Windows, which broke standalone builds that rely on the toolchain to supply THREADX_ARCH. Fixed by calling project(threadx LANGUAGES C) first so the toolchain is sourced, then checking THREADX_ARCH, then conditionally enabling ASM via enable_language(ASM) for non-Windows ports. The CMAKE_TRY_COMPILE_TARGET_TYPE override was removed from CMakeLists.txt because every toolchain file in cmake/ already sets it to STATIC_LIBRARY where needed. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- CMakeLists.txt | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index fc9ffb291..5f6be6d25 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,5 +1,11 @@ cmake_minimum_required(VERSION 3.13 FATAL_ERROR) +# Declare the project with C only first so that CMake loads the toolchain file, +# which sets THREADX_ARCH and THREADX_TOOLCHAIN as normal variables. Checking +# those variables before project() would always fail because the toolchain is +# not sourced until the first project() call. +project(threadx LANGUAGES C) + if(NOT DEFINED THREADX_ARCH) message(FATAL_ERROR "Error: THREADX_ARCH not defined") endif() @@ -7,22 +13,13 @@ if(NOT DEFINED THREADX_TOOLCHAIN) message(FATAL_ERROR "Error: THREADX_TOOLCHAIN not defined") endif() -# The Windows simulation ports build cleanly without executable try-compiles. -if((THREADX_ARCH STREQUAL "win32") OR (THREADX_ARCH STREQUAL "win64")) - set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) -endif() - -# Set up the project. The Windows simulation ports do not use assembly and -# avoiding ASM language enablement keeps MSVC configuration on the CLI path -# deterministic. -if((THREADX_ARCH STREQUAL "win32") OR (THREADX_ARCH STREQUAL "win64")) - project(threadx - LANGUAGES C - ) -else() - project(threadx - LANGUAGES C ASM - ) +# The Windows simulation ports do not use assembly. All other ports require +# it. enable_language() is called here rather than in project() above so that +# the ASM toolchain is only activated when we know the target actually needs it. +# Note: CMAKE_TRY_COMPILE_TARGET_TYPE is already set to STATIC_LIBRARY by +# every toolchain file in cmake/, so it does not need to be repeated here. +if(NOT ((THREADX_ARCH STREQUAL "win32") OR (THREADX_ARCH STREQUAL "win64"))) + enable_language(ASM) endif() option(THREADX_SMP "Build ThreadX SMP version" OFF) From e2834b3618d8ff3f4eba8bae55f2eb898b62005c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Wed, 3 Jun 2026 16:35:28 -0400 Subject: [PATCH 27/29] Added a release preparation script (#542) Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- scripts/prepare_release.sh | 172 +++++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100755 scripts/prepare_release.sh diff --git a/scripts/prepare_release.sh b/scripts/prepare_release.sh new file mode 100755 index 000000000..c33fa8f8d --- /dev/null +++ b/scripts/prepare_release.sh @@ -0,0 +1,172 @@ +#!/usr/bin/env bash +# prepare_release.sh +# Prepares a ThreadX release by updating version constants and port version strings. +# +# Usage: prepare_release.sh +# Example: prepare_release.sh 6.5.1.202602 +# Hotfix: prepare_release.sh 6.5.1.202602a +# +# This script: +# 1. Creates branch release--preparation from dev +# 2. Updates version constants in common/inc/tx_api.h +# (commit: "Updated version number constants") +# 3. Updates port version strings in all tx_port.h files +# (commit: "Updated port version strings") +# +# Copyright (C) 2026 Eclipse ThreadX contributors +# SPDX-License-Identifier: MIT + +set -eu + +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +REPO_ROOT="$(cd "${SCRIPT_DIR}/.." && pwd)" + +API_HEADER="${REPO_ROOT}/common/inc/tx_api.h" +PORT_HEADER_NAME="tx_port.h" +PORT_DIRS="ports ports_smp ports_arch ports_module" + +# -------------------------------------------------------------------------- +# Argument validation +# -------------------------------------------------------------------------- +if [ "$#" -ne 1 ]; then + printf "Usage: %s \n" "$(basename "$0")" >&2 + printf "Example: %s 6.5.1.202602\n" "$(basename "$0")" >&2 + exit 1 +fi + +VERSION="$1" + +if ! printf "%s" "${VERSION}" | grep -qE '^[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+[a-z]?$'; then + printf "Error: Invalid version format '%s'.\n" "${VERSION}" >&2 + printf "Expected: MAJOR.MINOR.PATCH.BUILD[hotfix_letter]\n" >&2 + exit 1 +fi + +# -------------------------------------------------------------------------- +# Parse version components +# -------------------------------------------------------------------------- +MAJOR=$(printf "%s" "${VERSION}" | cut -d. -f1) +MINOR=$(printf "%s" "${VERSION}" | cut -d. -f2) +PATCH=$(printf "%s" "${VERSION}" | cut -d. -f3) +BUILD_AND_HOTFIX=$(printf "%s" "${VERSION}" | cut -d. -f4) +BUILD=$(printf "%s" "${BUILD_AND_HOTFIX}" | sed -E 's/[a-z]+$//') +HOTFIX=$(printf "%s" "${BUILD_AND_HOTFIX}" | sed -E 's/^[0-9]+//') + +if [ -z "${HOTFIX}" ]; then + HOTFIX_DEFINE="' '" +else + HOTFIX_DEFINE="'${HOTFIX}'" +fi + +# -------------------------------------------------------------------------- +# Read and display current version +# -------------------------------------------------------------------------- +CURR_MAJOR=$(grep -E "^#define THREADX_MAJOR_VERSION" "${API_HEADER}" | awk '{print $NF}') +CURR_MINOR=$(grep -E "^#define THREADX_MINOR_VERSION" "${API_HEADER}" | awk '{print $NF}') +CURR_PATCH=$(grep -E "^#define THREADX_PATCH_VERSION" "${API_HEADER}" | awk '{print $NF}') +CURR_BUILD=$(grep -E "^#define THREADX_BUILD_VERSION" "${API_HEADER}" | awk '{print $NF}') +CURR_HOTFIX=$(grep -E "^#define THREADX_HOTFIX_VERSION" "${API_HEADER}" | \ + sed -E "s/.*'([^']*)'.*/\1/" | tr -d ' ') + +if [ -z "${CURR_HOTFIX}" ]; then + CURR_VER="${CURR_MAJOR}.${CURR_MINOR}.${CURR_PATCH}.${CURR_BUILD}" +else + CURR_VER="${CURR_MAJOR}.${CURR_MINOR}.${CURR_PATCH}.${CURR_BUILD}${CURR_HOTFIX}" +fi + +printf "\nThreadX release preparation\n" +printf " Repository : %s\n" "${REPO_ROOT}" +printf " Current version : %s\n" "${CURR_VER}" +printf " Target version : %s\n\n" "${VERSION}" +printf "Proceed with update? [y/N] " +read -r CONFIRM +case "${CONFIRM}" in + y|Y) ;; + *) + printf "Aborted.\n" + exit 0 + ;; +esac + +# -------------------------------------------------------------------------- +# Pre-flight checks +# -------------------------------------------------------------------------- +if ! git -C "${REPO_ROOT}" diff --quiet HEAD 2>/dev/null; then + printf "Error: Working tree has uncommitted changes. Commit or stash first.\n" >&2 + exit 1 +fi + +# -------------------------------------------------------------------------- +# Create feature branch from dev +# -------------------------------------------------------------------------- +BRANCH_NAME="release-${VERSION}-preparation" +printf "\nChecking out dev and pulling latest changes...\n" +git -C "${REPO_ROOT}" checkout dev +git -C "${REPO_ROOT}" pull origin dev +printf "Creating branch '%s'...\n" "${BRANCH_NAME}" +git -C "${REPO_ROOT}" checkout -b "${BRANCH_NAME}" + +# -------------------------------------------------------------------------- +# Update version constants +# -------------------------------------------------------------------------- +printf "\nUpdating version constants in %s...\n" "${API_HEADER}" + +sed -i -E "s|(#define THREADX_MAJOR_VERSION[[:space:]]+)[0-9]+|\1${MAJOR}|" "${API_HEADER}" +sed -i -E "s|(#define THREADX_MINOR_VERSION[[:space:]]+)[0-9]+|\1${MINOR}|" "${API_HEADER}" +sed -i -E "s|(#define THREADX_PATCH_VERSION[[:space:]]+)[0-9]+|\1${PATCH}|" "${API_HEADER}" +sed -i -E "s|(#define THREADX_BUILD_VERSION[[:space:]]+)[0-9]+|\1${BUILD}|" "${API_HEADER}" +sed -i -E "s|(#define THREADX_HOTFIX_VERSION[[:space:]]+)'[^']*'|\1${HOTFIX_DEFINE}|" "${API_HEADER}" + +git -C "${REPO_ROOT}" add "${API_HEADER}" +git -C "${REPO_ROOT}" commit -F - <<'COMMIT_EOF' +Updated version number constants + +Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> +COMMIT_EOF + +printf "Committed version constant updates.\n" + +# -------------------------------------------------------------------------- +# Update port version strings +# -------------------------------------------------------------------------- +printf "\nUpdating port version strings...\n" + +PORT_FILES="" +for dir in ${PORT_DIRS}; do + if [ -d "${REPO_ROOT}/${dir}" ]; then + found=$(find "${REPO_ROOT}/${dir}" -name "${PORT_HEADER_NAME}" 2>/dev/null | sort) + if [ -n "${found}" ]; then + PORT_FILES="${PORT_FILES}${found} +" + fi + fi +done +PORT_FILES=$(printf "%s" "${PORT_FILES}" | grep -v '^[[:space:]]*$' || true) + +if [ -z "${PORT_FILES}" ]; then + printf "Warning: No port header files found. Skipping port version string commit.\n" +else + while IFS= read -r port_file; do + if [ -n "${port_file}" ] && grep -qE "Version [0-9]" "${port_file}" 2>/dev/null; then + sed -i -E "s/Version [0-9]+\.[0-9]+\.[0-9]+\.[0-9]+[a-z]*/Version ${VERSION}/g" "${port_file}" + printf " Updated: %s\n" "${port_file#${REPO_ROOT}/}" + fi + done < +COMMIT_EOF + printf "Committed port version string updates.\n" + fi +fi + +printf "\nRelease preparation complete.\n" +printf "Branch '%s' is ready for review.\n" "${BRANCH_NAME}" From de1c6e9bbe13e2db480e4e0ed2d3589ebdd5db27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Wed, 3 Jun 2026 16:55:01 -0400 Subject: [PATCH 28/29] Release 6.5.1.202602 preparation (#543) * Updated version number constants * Updated port version strings --------- Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- common/inc/tx_api.h | 4 ++-- ports/arc_em/metaware/inc/tx_port.h | 2 +- ports/arc_hs/metaware/inc/tx_port.h | 2 +- ports/arm11/ac5/inc/tx_port.h | 2 +- ports/arm11/gnu/inc/tx_port.h | 2 +- ports/arm11/iar/inc/tx_port.h | 2 +- ports/arm9/ac5/inc/tx_port.h | 2 +- ports/arm9/gnu/inc/tx_port.h | 2 +- ports/arm9/iar/inc/tx_port.h | 2 +- ports/c667x/ccs/inc/tx_port.h | 2 +- ports/cortex_a12/ac6/inc/tx_port.h | 2 +- ports/cortex_a12/gnu/inc/tx_port.h | 2 +- ports/cortex_a15/ac6/inc/tx_port.h | 2 +- ports/cortex_a15/gnu/inc/tx_port.h | 2 +- ports/cortex_a15/iar/inc/tx_port.h | 2 +- ports/cortex_a17/ac6/inc/tx_port.h | 2 +- ports/cortex_a17/gnu/inc/tx_port.h | 2 +- ports/cortex_a34/ac6/inc/tx_port.h | 2 +- ports/cortex_a34/gnu/inc/tx_port.h | 2 +- ports/cortex_a35/ac6/inc/tx_port.h | 2 +- ports/cortex_a35/gnu/inc/tx_port.h | 2 +- ports/cortex_a5/ac5/inc/tx_port.h | 2 +- ports/cortex_a5/ac6/inc/tx_port.h | 2 +- ports/cortex_a5/ghs/inc/tx_port.h | 2 +- ports/cortex_a5/gnu/inc/tx_port.h | 2 +- ports/cortex_a5/iar/inc/tx_port.h | 2 +- ports/cortex_a53/ac6/inc/tx_port.h | 2 +- ports/cortex_a53/gnu/inc/tx_port.h | 2 +- ports/cortex_a55/ac6/inc/tx_port.h | 2 +- ports/cortex_a55/gnu/inc/tx_port.h | 2 +- ports/cortex_a57/ac6/inc/tx_port.h | 2 +- ports/cortex_a57/gnu/inc/tx_port.h | 2 +- ports/cortex_a5x/ac6/inc/tx_port.h | 2 +- ports/cortex_a65/ac6/inc/tx_port.h | 2 +- ports/cortex_a65/gnu/inc/tx_port.h | 2 +- ports/cortex_a65ae/ac6/inc/tx_port.h | 2 +- ports/cortex_a65ae/gnu/inc/tx_port.h | 2 +- ports/cortex_a7/ac5/inc/tx_port.h | 2 +- ports/cortex_a7/ac6/inc/tx_port.h | 2 +- ports/cortex_a7/ghs/inc/tx_port.h | 2 +- ports/cortex_a7/gnu/inc/tx_port.h | 2 +- ports/cortex_a7/iar/inc/tx_port.h | 2 +- ports/cortex_a72/ac6/inc/tx_port.h | 2 +- ports/cortex_a72/gnu/inc/tx_port.h | 2 +- ports/cortex_a73/ac6/inc/tx_port.h | 2 +- ports/cortex_a73/gnu/inc/tx_port.h | 2 +- ports/cortex_a75/ac6/inc/tx_port.h | 2 +- ports/cortex_a75/gnu/inc/tx_port.h | 2 +- ports/cortex_a76/ac6/inc/tx_port.h | 2 +- ports/cortex_a76/gnu/inc/tx_port.h | 2 +- ports/cortex_a76ae/ac6/inc/tx_port.h | 2 +- ports/cortex_a76ae/gnu/inc/tx_port.h | 2 +- ports/cortex_a77/ac6/inc/tx_port.h | 2 +- ports/cortex_a77/gnu/inc/tx_port.h | 2 +- ports/cortex_a8/ac5/inc/tx_port.h | 2 +- ports/cortex_a8/ac6/inc/tx_port.h | 2 +- ports/cortex_a8/ghs/inc/tx_port.h | 2 +- ports/cortex_a8/gnu/inc/tx_port.h | 2 +- ports/cortex_a8/iar/inc/tx_port.h | 2 +- ports/cortex_a9/ac5/inc/tx_port.h | 2 +- ports/cortex_a9/ac6/inc/tx_port.h | 2 +- ports/cortex_a9/ghs/inc/tx_port.h | 2 +- ports/cortex_a9/gnu/inc/tx_port.h | 2 +- ports/cortex_a9/iar/inc/tx_port.h | 2 +- ports/cortex_m0/ac5/inc/tx_port.h | 2 +- ports/cortex_m0/ac6/inc/tx_port.h | 2 +- ports/cortex_m0/gnu/inc/tx_port.h | 2 +- ports/cortex_m0/iar/inc/tx_port.h | 2 +- ports/cortex_m0/keil/inc/tx_port.h | 2 +- ports/cortex_m23/ac6/inc/tx_port.h | 2 +- ports/cortex_m23/gnu/inc/tx_port.h | 2 +- ports/cortex_m23/iar/inc/tx_port.h | 2 +- ports/cortex_m3/ac5/inc/tx_port.h | 2 +- ports/cortex_m3/ac6/inc/tx_port.h | 2 +- ports/cortex_m3/ghs/inc/tx_port.h | 2 +- ports/cortex_m3/gnu/inc/tx_port.h | 2 +- ports/cortex_m3/iar/inc/tx_port.h | 2 +- ports/cortex_m3/keil/inc/tx_port.h | 2 +- ports/cortex_m33/ac6/inc/tx_port.h | 2 +- ports/cortex_m33/gnu/inc/tx_port.h | 2 +- ports/cortex_m33/iar/inc/tx_port.h | 2 +- ports/cortex_m4/ac5/inc/tx_port.h | 2 +- ports/cortex_m4/ac6/inc/tx_port.h | 2 +- ports/cortex_m4/ghs/inc/tx_port.h | 2 +- ports/cortex_m4/gnu/inc/tx_port.h | 2 +- ports/cortex_m4/iar/inc/tx_port.h | 2 +- ports/cortex_m4/keil/inc/tx_port.h | 2 +- ports/cortex_m55/ac6/inc/tx_port.h | 2 +- ports/cortex_m55/gnu/inc/tx_port.h | 2 +- ports/cortex_m55/iar/inc/tx_port.h | 2 +- ports/cortex_m7/ac5/inc/tx_port.h | 2 +- ports/cortex_m7/ac6/inc/tx_port.h | 2 +- ports/cortex_m7/ghs/inc/tx_port.h | 2 +- ports/cortex_m7/gnu/inc/tx_port.h | 2 +- ports/cortex_m7/iar/inc/tx_port.h | 2 +- ports/cortex_m85/ac6/inc/tx_port.h | 2 +- ports/cortex_m85/gnu/inc/tx_port.h | 2 +- ports/cortex_m85/iar/inc/tx_port.h | 2 +- ports/cortex_r4/ac5/inc/tx_port.h | 2 +- ports/cortex_r4/ac6/inc/tx_port.h | 2 +- ports/cortex_r4/ghs/inc/tx_port.h | 2 +- ports/cortex_r4/gnu/inc/tx_port.h | 2 +- ports/cortex_r4/iar/inc/tx_port.h | 2 +- ports/cortex_r5/ac5/inc/tx_port.h | 2 +- ports/cortex_r5/ac6/inc/tx_port.h | 2 +- ports/cortex_r5/ghs/inc/tx_port.h | 2 +- ports/cortex_r5/gnu/inc/tx_port.h | 2 +- ports/cortex_r5/iar/inc/tx_port.h | 2 +- ports/cortex_r7/ghs/inc/tx_port.h | 2 +- ports/linux/gnu/inc/tx_port.h | 2 +- ports/risc-v32/clang/inc/tx_port.h | 2 +- ports/risc-v32/gnu/inc/tx_port.h | 2 +- ports/risc-v64/gnu/inc/tx_port.h | 2 +- ports/rxv1/ccrx/inc/tx_port.h | 2 +- ports/rxv1/gnu/inc/tx_port.h | 2 +- ports/rxv1/iar/inc/tx_port.h | 2 +- ports/rxv2/ccrx/inc/tx_port.h | 2 +- ports/rxv2/gnu/inc/tx_port.h | 2 +- ports/rxv2/iar/inc/tx_port.h | 2 +- ports/rxv3/ccrx/inc/tx_port.h | 2 +- ports/rxv3/gnu/inc/tx_port.h | 2 +- ports/rxv3/iar/inc/tx_port.h | 2 +- ports/xtensa/xcc/inc/tx_port.h | 2 +- ports_arch/ARMv7-A/threadx/common/inc/tx_port.h | 2 +- ports_arch/ARMv7-M/threadx/ghs/inc/tx_port.h | 2 +- ports_arch/ARMv7-M/threadx/inc/tx_port.h | 2 +- ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h | 2 +- ports_arch/ARMv8-A/threadx/common/inc/tx_port.h | 2 +- ports_arch/ARMv8-A/threadx_smp/common/inc/tx_port.h | 2 +- ports_arch/ARMv8-M/threadx/inc/tx_port.h | 2 +- ports_module/cortex_a35/ac6/inc/tx_port.h | 2 +- ports_module/cortex_a35/gnu/inc/tx_port.h | 2 +- ports_module/cortex_a35_smp/ac6/inc/tx_port.h | 2 +- ports_module/cortex_a35_smp/gnu/inc/tx_port.h | 2 +- ports_module/cortex_a7/ac5/inc/tx_port.h | 2 +- ports_module/cortex_a7/gnu/inc/tx_port.h | 2 +- ports_module/cortex_a7/iar/inc/tx_port.h | 2 +- ports_module/cortex_m0+/ac6/inc/tx_port.h | 2 +- ports_module/cortex_m0+/gnu/inc/tx_port.h | 2 +- ports_module/cortex_m0+/iar/inc/tx_port.h | 2 +- ports_module/cortex_m23/ac6/inc/tx_port.h | 2 +- ports_module/cortex_m23/gnu/inc/tx_port.h | 2 +- ports_module/cortex_m23/iar/inc/tx_port.h | 2 +- ports_module/cortex_m3/ac5/inc/tx_port.h | 2 +- ports_module/cortex_m3/ac6/inc/tx_port.h | 2 +- ports_module/cortex_m3/gnu/inc/tx_port.h | 2 +- ports_module/cortex_m3/iar/inc/tx_port.h | 2 +- ports_module/cortex_m33/ac6/inc/tx_port.h | 2 +- ports_module/cortex_m33/gnu/inc/tx_port.h | 2 +- ports_module/cortex_m33/iar/inc/tx_port.h | 2 +- ports_module/cortex_m4/ac5/inc/tx_port.h | 2 +- ports_module/cortex_m4/ac6/inc/tx_port.h | 2 +- ports_module/cortex_m4/gnu/inc/tx_port.h | 2 +- ports_module/cortex_m4/iar/inc/tx_port.h | 2 +- ports_module/cortex_m7/ac5/inc/tx_port.h | 2 +- ports_module/cortex_m7/ac6/inc/tx_port.h | 2 +- ports_module/cortex_m7/gnu/inc/tx_port.h | 2 +- ports_module/cortex_m7/iar/inc/tx_port.h | 2 +- ports_module/cortex_r4/ac6/inc/tx_port.h | 2 +- ports_module/cortex_r4/iar/inc/tx_port.h | 2 +- ports_module/rxv2/iar/inc/tx_port.h | 2 +- ports_smp/arc_hs_smp/metaware/inc/tx_port.h | 2 +- ports_smp/cortex_a34_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a34_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a35_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a35_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a53_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a53_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a55_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a55_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a57_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a57_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a5_smp/ac5/inc/tx_port.h | 2 +- ports_smp/cortex_a5_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a5x_smp/green/inc/tx_port.h | 2 +- ports_smp/cortex_a5x_smp/iar/inc/tx_port.h | 2 +- ports_smp/cortex_a65_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a65_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a72_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a72_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a73_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a73_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a75_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a75_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a76_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a76_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a77_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a77_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a78_smp/ac6/inc/tx_port.h | 2 +- ports_smp/cortex_a78_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a7_smp/ac5/inc/tx_port.h | 2 +- ports_smp/cortex_a7_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_a9_smp/ac5/inc/tx_port.h | 2 +- ports_smp/cortex_a9_smp/gnu/inc/tx_port.h | 2 +- ports_smp/cortex_r8_smp/ac5/inc/tx_port.h | 2 +- ports_smp/linux/gnu/inc/tx_port.h | 2 +- ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h | 2 +- ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h | 2 +- 204 files changed, 205 insertions(+), 205 deletions(-) diff --git a/common/inc/tx_api.h b/common/inc/tx_api.h index 7527c4132..a57c5844c 100644 --- a/common/inc/tx_api.h +++ b/common/inc/tx_api.h @@ -77,8 +77,8 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 #define THREADX_MINOR_VERSION 5 -#define THREADX_PATCH_VERSION 0 -#define THREADX_BUILD_VERSION 202601 +#define THREADX_PATCH_VERSION 1 +#define THREADX_BUILD_VERSION 202602 #define THREADX_HOTFIX_VERSION ' ' /* Define the following symbol for backward compatibility */ diff --git a/ports/arc_em/metaware/inc/tx_port.h b/ports/arc_em/metaware/inc/tx_port.h index 34ca80196..162915b2b 100644 --- a/ports/arc_em/metaware/inc/tx_port.h +++ b/ports/arc_em/metaware/inc/tx_port.h @@ -308,7 +308,7 @@ void _tx_initialize_start_interrupts(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARCv2_EM/MetaWare Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARCv2_EM/MetaWare Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arc_hs/metaware/inc/tx_port.h b/ports/arc_hs/metaware/inc/tx_port.h index 7c5dc6de9..8f0432b23 100644 --- a/ports/arc_hs/metaware/inc/tx_port.h +++ b/ports/arc_hs/metaware/inc/tx_port.h @@ -322,7 +322,7 @@ VOID tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARC_HS/MetaWare Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARC_HS/MetaWare Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm11/ac5/inc/tx_port.h b/ports/arm11/ac5/inc/tx_port.h index b1bf6e363..17dff9a4f 100644 --- a/ports/arm11/ac5/inc/tx_port.h +++ b/ports/arm11/ac5/inc/tx_port.h @@ -311,7 +311,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/gnu/inc/tx_port.h b/ports/arm11/gnu/inc/tx_port.h index 259ad092d..c0cb95f6b 100644 --- a/ports/arm11/gnu/inc/tx_port.h +++ b/ports/arm11/gnu/inc/tx_port.h @@ -300,7 +300,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/iar/inc/tx_port.h b/ports/arm11/iar/inc/tx_port.h index 52b43a868..bb96d714f 100644 --- a/ports/arm11/iar/inc/tx_port.h +++ b/ports/arm11/iar/inc/tx_port.h @@ -366,7 +366,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm9/ac5/inc/tx_port.h b/ports/arm9/ac5/inc/tx_port.h index e9dc64301..4e62cd5ea 100644 --- a/ports/arm9/ac5/inc/tx_port.h +++ b/ports/arm9/ac5/inc/tx_port.h @@ -313,7 +313,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM9/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM9/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/gnu/inc/tx_port.h b/ports/arm9/gnu/inc/tx_port.h index 4597b2522..4cb35304c 100644 --- a/ports/arm9/gnu/inc/tx_port.h +++ b/ports/arm9/gnu/inc/tx_port.h @@ -300,7 +300,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM9/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM9/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/iar/inc/tx_port.h b/ports/arm9/iar/inc/tx_port.h index e4411ae6c..20331a7b9 100644 --- a/ports/arm9/iar/inc/tx_port.h +++ b/ports/arm9/iar/inc/tx_port.h @@ -366,7 +366,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM9/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM9/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/c667x/ccs/inc/tx_port.h b/ports/c667x/ccs/inc/tx_port.h index 6f5a9838f..229014ead 100644 --- a/ports/c667x/ccs/inc/tx_port.h +++ b/ports/c667x/ccs/inc/tx_port.h @@ -258,7 +258,7 @@ unsigned int _tx_thread_interrupt_control(unsigned int); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX C667x/TI Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX C667x/TI Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a12/ac6/inc/tx_port.h b/ports/cortex_a12/ac6/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a12/ac6/inc/tx_port.h +++ b/ports/cortex_a12/ac6/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a12/gnu/inc/tx_port.h b/ports/cortex_a12/gnu/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a12/gnu/inc/tx_port.h +++ b/ports/cortex_a12/gnu/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/ac6/inc/tx_port.h b/ports/cortex_a15/ac6/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a15/ac6/inc/tx_port.h +++ b/ports/cortex_a15/ac6/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/gnu/inc/tx_port.h b/ports/cortex_a15/gnu/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a15/gnu/inc/tx_port.h +++ b/ports/cortex_a15/gnu/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/iar/inc/tx_port.h b/ports/cortex_a15/iar/inc/tx_port.h index ca868f642..18741e4c1 100644 --- a/ports/cortex_a15/iar/inc/tx_port.h +++ b/ports/cortex_a15/iar/inc/tx_port.h @@ -376,7 +376,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A15/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A15/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a17/ac6/inc/tx_port.h b/ports/cortex_a17/ac6/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a17/ac6/inc/tx_port.h +++ b/ports/cortex_a17/ac6/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a17/gnu/inc/tx_port.h b/ports/cortex_a17/gnu/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a17/gnu/inc/tx_port.h +++ b/ports/cortex_a17/gnu/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a34/ac6/inc/tx_port.h b/ports/cortex_a34/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a34/ac6/inc/tx_port.h +++ b/ports/cortex_a34/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a34/gnu/inc/tx_port.h b/ports/cortex_a34/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a34/gnu/inc/tx_port.h +++ b/ports/cortex_a34/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a35/ac6/inc/tx_port.h b/ports/cortex_a35/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a35/ac6/inc/tx_port.h +++ b/ports/cortex_a35/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a35/gnu/inc/tx_port.h b/ports/cortex_a35/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a35/gnu/inc/tx_port.h +++ b/ports/cortex_a35/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ac5/inc/tx_port.h b/ports/cortex_a5/ac5/inc/tx_port.h index 3c046e95e..60f212fcc 100644 --- a/ports/cortex_a5/ac5/inc/tx_port.h +++ b/ports/cortex_a5/ac5/inc/tx_port.h @@ -318,7 +318,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ac6/inc/tx_port.h b/ports/cortex_a5/ac6/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a5/ac6/inc/tx_port.h +++ b/ports/cortex_a5/ac6/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ghs/inc/tx_port.h b/ports/cortex_a5/ghs/inc/tx_port.h index e9e0b876d..f6e4fefc8 100644 --- a/ports/cortex_a5/ghs/inc/tx_port.h +++ b/ports/cortex_a5/ghs/inc/tx_port.h @@ -386,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5/Green Hills Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5/Green Hills Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/gnu/inc/tx_port.h b/ports/cortex_a5/gnu/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a5/gnu/inc/tx_port.h +++ b/ports/cortex_a5/gnu/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/iar/inc/tx_port.h b/ports/cortex_a5/iar/inc/tx_port.h index 5ce81a277..5893398b7 100644 --- a/ports/cortex_a5/iar/inc/tx_port.h +++ b/ports/cortex_a5/iar/inc/tx_port.h @@ -374,7 +374,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a53/ac6/inc/tx_port.h b/ports/cortex_a53/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a53/ac6/inc/tx_port.h +++ b/ports/cortex_a53/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a53/gnu/inc/tx_port.h b/ports/cortex_a53/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a53/gnu/inc/tx_port.h +++ b/ports/cortex_a53/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a55/ac6/inc/tx_port.h b/ports/cortex_a55/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a55/ac6/inc/tx_port.h +++ b/ports/cortex_a55/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a55/gnu/inc/tx_port.h b/ports/cortex_a55/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a55/gnu/inc/tx_port.h +++ b/ports/cortex_a55/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a57/ac6/inc/tx_port.h b/ports/cortex_a57/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a57/ac6/inc/tx_port.h +++ b/ports/cortex_a57/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a57/gnu/inc/tx_port.h b/ports/cortex_a57/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a57/gnu/inc/tx_port.h +++ b/ports/cortex_a57/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5x/ac6/inc/tx_port.h b/ports/cortex_a5x/ac6/inc/tx_port.h index c679690c5..a05ca47d2 100644 --- a/ports/cortex_a5x/ac6/inc/tx_port.h +++ b/ports/cortex_a5x/ac6/inc/tx_port.h @@ -348,7 +348,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x/ARM Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x/ARM Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65/ac6/inc/tx_port.h b/ports/cortex_a65/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a65/ac6/inc/tx_port.h +++ b/ports/cortex_a65/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65/gnu/inc/tx_port.h b/ports/cortex_a65/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a65/gnu/inc/tx_port.h +++ b/ports/cortex_a65/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65ae/ac6/inc/tx_port.h b/ports/cortex_a65ae/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a65ae/ac6/inc/tx_port.h +++ b/ports/cortex_a65ae/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65ae/gnu/inc/tx_port.h b/ports/cortex_a65ae/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a65ae/gnu/inc/tx_port.h +++ b/ports/cortex_a65ae/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ac5/inc/tx_port.h b/ports/cortex_a7/ac5/inc/tx_port.h index 088fc91ff..8ce4b0dca 100644 --- a/ports/cortex_a7/ac5/inc/tx_port.h +++ b/ports/cortex_a7/ac5/inc/tx_port.h @@ -318,7 +318,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ac6/inc/tx_port.h b/ports/cortex_a7/ac6/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a7/ac6/inc/tx_port.h +++ b/ports/cortex_a7/ac6/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ghs/inc/tx_port.h b/ports/cortex_a7/ghs/inc/tx_port.h index 7fa32537a..cbd64400e 100644 --- a/ports/cortex_a7/ghs/inc/tx_port.h +++ b/ports/cortex_a7/ghs/inc/tx_port.h @@ -386,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/Green Hills Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/Green Hills Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/gnu/inc/tx_port.h b/ports/cortex_a7/gnu/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a7/gnu/inc/tx_port.h +++ b/ports/cortex_a7/gnu/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/iar/inc/tx_port.h b/ports/cortex_a7/iar/inc/tx_port.h index 90477b762..9e8b8583b 100644 --- a/ports/cortex_a7/iar/inc/tx_port.h +++ b/ports/cortex_a7/iar/inc/tx_port.h @@ -374,7 +374,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/IAR Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a72/ac6/inc/tx_port.h b/ports/cortex_a72/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a72/ac6/inc/tx_port.h +++ b/ports/cortex_a72/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a72/gnu/inc/tx_port.h b/ports/cortex_a72/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a72/gnu/inc/tx_port.h +++ b/ports/cortex_a72/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a73/ac6/inc/tx_port.h b/ports/cortex_a73/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a73/ac6/inc/tx_port.h +++ b/ports/cortex_a73/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a73/gnu/inc/tx_port.h b/ports/cortex_a73/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a73/gnu/inc/tx_port.h +++ b/ports/cortex_a73/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a75/ac6/inc/tx_port.h b/ports/cortex_a75/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a75/ac6/inc/tx_port.h +++ b/ports/cortex_a75/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a75/gnu/inc/tx_port.h b/ports/cortex_a75/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a75/gnu/inc/tx_port.h +++ b/ports/cortex_a75/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76/ac6/inc/tx_port.h b/ports/cortex_a76/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a76/ac6/inc/tx_port.h +++ b/ports/cortex_a76/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76/gnu/inc/tx_port.h b/ports/cortex_a76/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a76/gnu/inc/tx_port.h +++ b/ports/cortex_a76/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76ae/ac6/inc/tx_port.h b/ports/cortex_a76ae/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a76ae/ac6/inc/tx_port.h +++ b/ports/cortex_a76ae/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76ae/gnu/inc/tx_port.h b/ports/cortex_a76ae/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a76ae/gnu/inc/tx_port.h +++ b/ports/cortex_a76ae/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a77/ac6/inc/tx_port.h b/ports/cortex_a77/ac6/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a77/ac6/inc/tx_port.h +++ b/ports/cortex_a77/ac6/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a77/gnu/inc/tx_port.h b/ports/cortex_a77/gnu/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports/cortex_a77/gnu/inc/tx_port.h +++ b/ports/cortex_a77/gnu/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ac5/inc/tx_port.h b/ports/cortex_a8/ac5/inc/tx_port.h index 7dc9a5221..3c32a273a 100644 --- a/ports/cortex_a8/ac5/inc/tx_port.h +++ b/ports/cortex_a8/ac5/inc/tx_port.h @@ -318,7 +318,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A8/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A8/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ac6/inc/tx_port.h b/ports/cortex_a8/ac6/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a8/ac6/inc/tx_port.h +++ b/ports/cortex_a8/ac6/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ghs/inc/tx_port.h b/ports/cortex_a8/ghs/inc/tx_port.h index d9dd3413d..d2c06933d 100644 --- a/ports/cortex_a8/ghs/inc/tx_port.h +++ b/ports/cortex_a8/ghs/inc/tx_port.h @@ -386,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A8/Green Hills Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A8/Green Hills Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/gnu/inc/tx_port.h b/ports/cortex_a8/gnu/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a8/gnu/inc/tx_port.h +++ b/ports/cortex_a8/gnu/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/iar/inc/tx_port.h b/ports/cortex_a8/iar/inc/tx_port.h index 940d7f688..b8512373d 100644 --- a/ports/cortex_a8/iar/inc/tx_port.h +++ b/ports/cortex_a8/iar/inc/tx_port.h @@ -375,7 +375,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A8/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A8/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a9/ac5/inc/tx_port.h b/ports/cortex_a9/ac5/inc/tx_port.h index 0c1451563..1dcd48569 100644 --- a/ports/cortex_a9/ac5/inc/tx_port.h +++ b/ports/cortex_a9/ac5/inc/tx_port.h @@ -318,7 +318,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A9/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A9/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ac6/inc/tx_port.h b/ports/cortex_a9/ac6/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a9/ac6/inc/tx_port.h +++ b/ports/cortex_a9/ac6/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ghs/inc/tx_port.h b/ports/cortex_a9/ghs/inc/tx_port.h index 75e769003..fa6eaef9f 100644 --- a/ports/cortex_a9/ghs/inc/tx_port.h +++ b/ports/cortex_a9/ghs/inc/tx_port.h @@ -386,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A9/Green Hills Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A9/Green Hills Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/gnu/inc/tx_port.h b/ports/cortex_a9/gnu/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports/cortex_a9/gnu/inc/tx_port.h +++ b/ports/cortex_a9/gnu/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/iar/inc/tx_port.h b/ports/cortex_a9/iar/inc/tx_port.h index 46f042a9f..29a39a8ac 100644 --- a/ports/cortex_a9/iar/inc/tx_port.h +++ b/ports/cortex_a9/iar/inc/tx_port.h @@ -376,7 +376,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A9/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A9/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/ac5/inc/tx_port.h b/ports/cortex_m0/ac5/inc/tx_port.h index f163f1c64..99a627cc2 100644 --- a/ports/cortex_m0/ac5/inc/tx_port.h +++ b/ports/cortex_m0/ac5/inc/tx_port.h @@ -312,7 +312,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/ac6/inc/tx_port.h b/ports/cortex_m0/ac6/inc/tx_port.h index 9c9e64704..fab23b823 100644 --- a/ports/cortex_m0/ac6/inc/tx_port.h +++ b/ports/cortex_m0/ac6/inc/tx_port.h @@ -355,7 +355,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC6 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/gnu/inc/tx_port.h b/ports/cortex_m0/gnu/inc/tx_port.h index ddeff5c5e..48c3824e6 100644 --- a/ports/cortex_m0/gnu/inc/tx_port.h +++ b/ports/cortex_m0/gnu/inc/tx_port.h @@ -359,7 +359,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/iar/inc/tx_port.h b/ports/cortex_m0/iar/inc/tx_port.h index c92c71f81..7951a30fc 100644 --- a/ports/cortex_m0/iar/inc/tx_port.h +++ b/ports/cortex_m0/iar/inc/tx_port.h @@ -339,7 +339,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/keil/inc/tx_port.h b/ports/cortex_m0/keil/inc/tx_port.h index f163f1c64..99a627cc2 100644 --- a/ports/cortex_m0/keil/inc/tx_port.h +++ b/ports/cortex_m0/keil/inc/tx_port.h @@ -312,7 +312,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/ac6/inc/tx_port.h b/ports/cortex_m23/ac6/inc/tx_port.h index 2140af537..70fe97f97 100644 --- a/ports/cortex_m23/ac6/inc/tx_port.h +++ b/ports/cortex_m23/ac6/inc/tx_port.h @@ -394,7 +394,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/AC6 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/gnu/inc/tx_port.h b/ports/cortex_m23/gnu/inc/tx_port.h index b66811392..dad88dfb6 100644 --- a/ports/cortex_m23/gnu/inc/tx_port.h +++ b/ports/cortex_m23/gnu/inc/tx_port.h @@ -426,7 +426,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/GNU Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/iar/inc/tx_port.h b/ports/cortex_m23/iar/inc/tx_port.h index dee22f50c..a02e4e6a0 100644 --- a/ports/cortex_m23/iar/inc/tx_port.h +++ b/ports/cortex_m23/iar/inc/tx_port.h @@ -415,7 +415,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac5/inc/tx_port.h b/ports/cortex_m3/ac5/inc/tx_port.h index 32e640ba4..513837508 100644 --- a/ports/cortex_m3/ac5/inc/tx_port.h +++ b/ports/cortex_m3/ac5/inc/tx_port.h @@ -699,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/AC5 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h index 32604f3cf..c90f14459 100644 --- a/ports/cortex_m3/ac6/inc/tx_port.h +++ b/ports/cortex_m3/ac6/inc/tx_port.h @@ -701,7 +701,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/AC6 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ghs/inc/tx_port.h b/ports/cortex_m3/ghs/inc/tx_port.h index 1327b3a7f..da8c1f3fc 100644 --- a/ports/cortex_m3/ghs/inc/tx_port.h +++ b/ports/cortex_m3/ghs/inc/tx_port.h @@ -371,7 +371,7 @@ asm void restore_ints(int a) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/GHS Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/GHS Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m3/gnu/inc/tx_port.h b/ports/cortex_m3/gnu/inc/tx_port.h index 391688bd6..41b48ad39 100644 --- a/ports/cortex_m3/gnu/inc/tx_port.h +++ b/ports/cortex_m3/gnu/inc/tx_port.h @@ -702,7 +702,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/GNU Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/iar/inc/tx_port.h b/ports/cortex_m3/iar/inc/tx_port.h index 1b298161b..deb37e743 100644 --- a/ports/cortex_m3/iar/inc/tx_port.h +++ b/ports/cortex_m3/iar/inc/tx_port.h @@ -701,7 +701,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/keil/inc/tx_port.h b/ports/cortex_m3/keil/inc/tx_port.h index 6ec876dcb..8ed6e0d8a 100644 --- a/ports/cortex_m3/keil/inc/tx_port.h +++ b/ports/cortex_m3/keil/inc/tx_port.h @@ -699,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/Keil Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/Keil Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h index a706ff62f..bb71cc55a 100644 --- a/ports/cortex_m33/ac6/inc/tx_port.h +++ b/ports/cortex_m33/ac6/inc/tx_port.h @@ -617,7 +617,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33/AC6 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h index 2b962069f..c8b56cd79 100644 --- a/ports/cortex_m33/gnu/inc/tx_port.h +++ b/ports/cortex_m33/gnu/inc/tx_port.h @@ -617,7 +617,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33/GNU Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h index 6298ddcb0..ced037117 100644 --- a/ports/cortex_m33/iar/inc/tx_port.h +++ b/ports/cortex_m33/iar/inc/tx_port.h @@ -617,7 +617,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac5/inc/tx_port.h b/ports/cortex_m4/ac5/inc/tx_port.h index 87b3dd5c1..6e16ad45a 100644 --- a/ports/cortex_m4/ac5/inc/tx_port.h +++ b/ports/cortex_m4/ac5/inc/tx_port.h @@ -699,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/AC5 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h index c35bb424a..cf5bcb065 100644 --- a/ports/cortex_m4/ac6/inc/tx_port.h +++ b/ports/cortex_m4/ac6/inc/tx_port.h @@ -717,7 +717,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/AC6 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ghs/inc/tx_port.h b/ports/cortex_m4/ghs/inc/tx_port.h index 4382845ae..f2b66c764 100644 --- a/ports/cortex_m4/ghs/inc/tx_port.h +++ b/ports/cortex_m4/ghs/inc/tx_port.h @@ -378,7 +378,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/GHS Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/GHS Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m4/gnu/inc/tx_port.h b/ports/cortex_m4/gnu/inc/tx_port.h index a415dfbeb..3f86a8414 100644 --- a/ports/cortex_m4/gnu/inc/tx_port.h +++ b/ports/cortex_m4/gnu/inc/tx_port.h @@ -704,7 +704,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/GNU Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/iar/inc/tx_port.h b/ports/cortex_m4/iar/inc/tx_port.h index 85fe8e6e0..39de14f78 100644 --- a/ports/cortex_m4/iar/inc/tx_port.h +++ b/ports/cortex_m4/iar/inc/tx_port.h @@ -701,7 +701,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/keil/inc/tx_port.h b/ports/cortex_m4/keil/inc/tx_port.h index f96d819ed..3477ab040 100644 --- a/ports/cortex_m4/keil/inc/tx_port.h +++ b/ports/cortex_m4/keil/inc/tx_port.h @@ -699,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/Keil Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/Keil Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/ac6/inc/tx_port.h b/ports/cortex_m55/ac6/inc/tx_port.h index 9d11a04bf..86e5410e8 100644 --- a/ports/cortex_m55/ac6/inc/tx_port.h +++ b/ports/cortex_m55/ac6/inc/tx_port.h @@ -613,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M55/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M55/AC6 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/gnu/inc/tx_port.h b/ports/cortex_m55/gnu/inc/tx_port.h index ff5b001ab..77e9105f0 100644 --- a/ports/cortex_m55/gnu/inc/tx_port.h +++ b/ports/cortex_m55/gnu/inc/tx_port.h @@ -618,7 +618,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M55/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M55/GNU Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/iar/inc/tx_port.h b/ports/cortex_m55/iar/inc/tx_port.h index c1b94ea0d..e10e76342 100644 --- a/ports/cortex_m55/iar/inc/tx_port.h +++ b/ports/cortex_m55/iar/inc/tx_port.h @@ -614,7 +614,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M55/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M55/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac5/inc/tx_port.h b/ports/cortex_m7/ac5/inc/tx_port.h index 717bd1271..2bf1d33d3 100644 --- a/ports/cortex_m7/ac5/inc/tx_port.h +++ b/ports/cortex_m7/ac5/inc/tx_port.h @@ -699,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/AC5 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h index d8c2b51e7..5a271fe68 100644 --- a/ports/cortex_m7/ac6/inc/tx_port.h +++ b/ports/cortex_m7/ac6/inc/tx_port.h @@ -701,7 +701,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/AC6 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ghs/inc/tx_port.h b/ports/cortex_m7/ghs/inc/tx_port.h index aabf714ec..7b1480fa2 100644 --- a/ports/cortex_m7/ghs/inc/tx_port.h +++ b/ports/cortex_m7/ghs/inc/tx_port.h @@ -378,7 +378,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/GHS Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/GHS Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m7/gnu/inc/tx_port.h b/ports/cortex_m7/gnu/inc/tx_port.h index 77355aab8..824d60d98 100644 --- a/ports/cortex_m7/gnu/inc/tx_port.h +++ b/ports/cortex_m7/gnu/inc/tx_port.h @@ -704,7 +704,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/GNU Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h index 14524c46e..30af8b42f 100644 --- a/ports/cortex_m7/iar/inc/tx_port.h +++ b/ports/cortex_m7/iar/inc/tx_port.h @@ -701,7 +701,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/ac6/inc/tx_port.h b/ports/cortex_m85/ac6/inc/tx_port.h index 7e119fee1..854619d73 100644 --- a/ports/cortex_m85/ac6/inc/tx_port.h +++ b/ports/cortex_m85/ac6/inc/tx_port.h @@ -613,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/AC6 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/gnu/inc/tx_port.h b/ports/cortex_m85/gnu/inc/tx_port.h index c1d2f7312..ce3a4cbe5 100644 --- a/ports/cortex_m85/gnu/inc/tx_port.h +++ b/ports/cortex_m85/gnu/inc/tx_port.h @@ -618,7 +618,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/GNU Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/iar/inc/tx_port.h b/ports/cortex_m85/iar/inc/tx_port.h index 409aecdd3..33cf512d6 100644 --- a/ports/cortex_m85/iar/inc/tx_port.h +++ b/ports/cortex_m85/iar/inc/tx_port.h @@ -614,7 +614,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r4/ac5/inc/tx_port.h b/ports/cortex_r4/ac5/inc/tx_port.h index 072332903..7db943d4b 100644 --- a/ports/cortex_r4/ac5/inc/tx_port.h +++ b/ports/cortex_r4/ac5/inc/tx_port.h @@ -318,7 +318,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ac6/inc/tx_port.h b/ports/cortex_r4/ac6/inc/tx_port.h index ff4ed9d13..5aa6919b1 100644 --- a/ports/cortex_r4/ac6/inc/tx_port.h +++ b/ports/cortex_r4/ac6/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC6 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ghs/inc/tx_port.h b/ports/cortex_r4/ghs/inc/tx_port.h index 22daf8ea9..1e9933ad8 100644 --- a/ports/cortex_r4/ghs/inc/tx_port.h +++ b/ports/cortex_r4/ghs/inc/tx_port.h @@ -376,7 +376,7 @@ asm void restore_ints(int a) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/Green Hills Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/Green Hills Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/gnu/inc/tx_port.h b/ports/cortex_r4/gnu/inc/tx_port.h index 827590c95..7b2920566 100644 --- a/ports/cortex_r4/gnu/inc/tx_port.h +++ b/ports/cortex_r4/gnu/inc/tx_port.h @@ -300,7 +300,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/iar/inc/tx_port.h b/ports/cortex_r4/iar/inc/tx_port.h index c2950326e..4696023b3 100644 --- a/ports/cortex_r4/iar/inc/tx_port.h +++ b/ports/cortex_r4/iar/inc/tx_port.h @@ -358,7 +358,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r5/ac5/inc/tx_port.h b/ports/cortex_r5/ac5/inc/tx_port.h index aa188c5cb..c643d8186 100644 --- a/ports/cortex_r5/ac5/inc/tx_port.h +++ b/ports/cortex_r5/ac5/inc/tx_port.h @@ -311,7 +311,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ac6/inc/tx_port.h b/ports/cortex_r5/ac6/inc/tx_port.h index 360e31784..d25f59707 100644 --- a/ports/cortex_r5/ac6/inc/tx_port.h +++ b/ports/cortex_r5/ac6/inc/tx_port.h @@ -300,7 +300,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/AC6 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ghs/inc/tx_port.h b/ports/cortex_r5/ghs/inc/tx_port.h index 5b435fcbb..542dca9a7 100644 --- a/ports/cortex_r5/ghs/inc/tx_port.h +++ b/ports/cortex_r5/ghs/inc/tx_port.h @@ -386,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/Green Hills Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/Green Hills Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/gnu/inc/tx_port.h b/ports/cortex_r5/gnu/inc/tx_port.h index 0a09f9eac..28716e937 100644 --- a/ports/cortex_r5/gnu/inc/tx_port.h +++ b/ports/cortex_r5/gnu/inc/tx_port.h @@ -300,7 +300,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/iar/inc/tx_port.h b/ports/cortex_r5/iar/inc/tx_port.h index eb5e46d98..31074a1f4 100644 --- a/ports/cortex_r5/iar/inc/tx_port.h +++ b/ports/cortex_r5/iar/inc/tx_port.h @@ -358,7 +358,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r7/ghs/inc/tx_port.h b/ports/cortex_r7/ghs/inc/tx_port.h index 11e059370..0c5ccd2b0 100644 --- a/ports/cortex_r7/ghs/inc/tx_port.h +++ b/ports/cortex_r7/ghs/inc/tx_port.h @@ -386,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R7/Green Hills Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R7/Green Hills Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/linux/gnu/inc/tx_port.h b/ports/linux/gnu/inc/tx_port.h index 83d72df08..40f5d5054 100644 --- a/ports/linux/gnu/inc/tx_port.h +++ b/ports/linux/gnu/inc/tx_port.h @@ -533,7 +533,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation * ThreadX Linux/gcc Version 6.5.0.202601 *"; + "Copyright (c) Microsoft Corporation * ThreadX Linux/gcc Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/risc-v32/clang/inc/tx_port.h b/ports/risc-v32/clang/inc/tx_port.h index 95995032c..72b5e79ca 100644 --- a/ports/risc-v32/clang/inc/tx_port.h +++ b/ports/risc-v32/clang/inc/tx_port.h @@ -56,7 +56,7 @@ #ifndef __ASSEMBLER__ #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RISC-V32/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RISC-V32/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif /* TX_THREAD_INIT */ diff --git a/ports/risc-v32/gnu/inc/tx_port.h b/ports/risc-v32/gnu/inc/tx_port.h index 11e9f87be..baf14be9d 100644 --- a/ports/risc-v32/gnu/inc/tx_port.h +++ b/ports/risc-v32/gnu/inc/tx_port.h @@ -157,7 +157,7 @@ extern TEST_FLAG test_forced_mutex_timeout; #ifndef __ASSEMBLER__ #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RISC-V32/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RISC-V32/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif /* TX_THREAD_INIT */ diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h index 4df55a6a1..ac7512081 100644 --- a/ports/risc-v64/gnu/inc/tx_port.h +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -426,7 +426,7 @@ extern TEST_FLAG test_forced_mutex_timeout; #ifndef __ASSEMBLER__ #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RISC-V64/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RISC-V64/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif /* TX_THREAD_INIT */ diff --git a/ports/rxv1/ccrx/inc/tx_port.h b/ports/rxv1/ccrx/inc/tx_port.h index 295add897..160888acf 100644 --- a/ports/rxv1/ccrx/inc/tx_port.h +++ b/ports/rxv1/ccrx/inc/tx_port.h @@ -260,7 +260,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv1/CCRX Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv1/CCRX Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv1/gnu/inc/tx_port.h b/ports/rxv1/gnu/inc/tx_port.h index bc1f415cd..846f2964e 100644 --- a/ports/rxv1/gnu/inc/tx_port.h +++ b/ports/rxv1/gnu/inc/tx_port.h @@ -257,7 +257,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv1/GNURX Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv1/GNURX Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv1/iar/inc/tx_port.h b/ports/rxv1/iar/inc/tx_port.h index 1010e4649..4df3a5f91 100644 --- a/ports/rxv1/iar/inc/tx_port.h +++ b/ports/rxv1/iar/inc/tx_port.h @@ -257,7 +257,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv1/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv1/IAR Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/ccrx/inc/tx_port.h b/ports/rxv2/ccrx/inc/tx_port.h index 95f578eb4..e06a840ae 100644 --- a/ports/rxv2/ccrx/inc/tx_port.h +++ b/ports/rxv2/ccrx/inc/tx_port.h @@ -260,7 +260,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/CCRX Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/CCRX Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/gnu/inc/tx_port.h b/ports/rxv2/gnu/inc/tx_port.h index 74f36a4ca..22acceed7 100644 --- a/ports/rxv2/gnu/inc/tx_port.h +++ b/ports/rxv2/gnu/inc/tx_port.h @@ -257,7 +257,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/GNURX Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/GNURX Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/iar/inc/tx_port.h b/ports/rxv2/iar/inc/tx_port.h index 351c51d06..8f2a674c3 100644 --- a/ports/rxv2/iar/inc/tx_port.h +++ b/ports/rxv2/iar/inc/tx_port.h @@ -256,7 +256,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/IAR Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/ccrx/inc/tx_port.h b/ports/rxv3/ccrx/inc/tx_port.h index a56636bd9..4f56ba746 100644 --- a/ports/rxv3/ccrx/inc/tx_port.h +++ b/ports/rxv3/ccrx/inc/tx_port.h @@ -265,7 +265,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/CCRX Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/CCRX Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/gnu/inc/tx_port.h b/ports/rxv3/gnu/inc/tx_port.h index 52da26d8d..6d03f0abb 100644 --- a/ports/rxv3/gnu/inc/tx_port.h +++ b/ports/rxv3/gnu/inc/tx_port.h @@ -262,7 +262,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/GNURX Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/GNURX Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/iar/inc/tx_port.h b/ports/rxv3/iar/inc/tx_port.h index e40be8315..be4815337 100644 --- a/ports/rxv3/iar/inc/tx_port.h +++ b/ports/rxv3/iar/inc/tx_port.h @@ -262,7 +262,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/IAR Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/xtensa/xcc/inc/tx_port.h b/ports/xtensa/xcc/inc/tx_port.h index d6503b4fe..5aeb58bf3 100644 --- a/ports/xtensa/xcc/inc/tx_port.h +++ b/ports/xtensa/xcc/inc/tx_port.h @@ -461,7 +461,7 @@ extern int xt_timer_intnum; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * Azure RTOS Xtensa Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * Azure RTOS Xtensa Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h b/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h index f01530467..8bd1327ad 100644 --- a/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h +++ b/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h @@ -307,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_arch/ARMv7-M/threadx/ghs/inc/tx_port.h b/ports_arch/ARMv7-M/threadx/ghs/inc/tx_port.h index eb5c9daff..110e2f4f8 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/inc/tx_port.h +++ b/ports_arch/ARMv7-M/threadx/ghs/inc/tx_port.h @@ -387,7 +387,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-M Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-M Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_arch/ARMv7-M/threadx/inc/tx_port.h b/ports_arch/ARMv7-M/threadx/inc/tx_port.h index 35884cf1c..2c94ba8b6 100644 --- a/ports_arch/ARMv7-M/threadx/inc/tx_port.h +++ b/ports_arch/ARMv7-M/threadx/inc/tx_port.h @@ -699,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mx Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mx Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h b/ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h index b93879329..ad83766f9 100644 --- a/ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h +++ b/ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mx Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mx Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_arch/ARMv8-A/threadx/common/inc/tx_port.h b/ports_arch/ARMv8-A/threadx/common/inc/tx_port.h index e53523382..74ec15571 100644 --- a/ports_arch/ARMv8-A/threadx/common/inc/tx_port.h +++ b/ports_arch/ARMv8-A/threadx/common/inc/tx_port.h @@ -361,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_arch/ARMv8-A/threadx_smp/common/inc/tx_port.h b/ports_arch/ARMv8-A/threadx_smp/common/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/inc/tx_port.h +++ b/ports_arch/ARMv8-A/threadx_smp/common/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_arch/ARMv8-M/threadx/inc/tx_port.h b/ports_arch/ARMv8-M/threadx/inc/tx_port.h index f0e7b79c6..d4ffbe2d3 100644 --- a/ports_arch/ARMv8-M/threadx/inc/tx_port.h +++ b/ports_arch/ARMv8-M/threadx/inc/tx_port.h @@ -613,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mxx Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mxx Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_a35/ac6/inc/tx_port.h b/ports_module/cortex_a35/ac6/inc/tx_port.h index 657ad4516..8ba907bfb 100644 --- a/ports_module/cortex_a35/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35/ac6/inc/tx_port.h @@ -381,7 +381,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35/AC6 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/gnu/inc/tx_port.h b/ports_module/cortex_a35/gnu/inc/tx_port.h index edf3ad668..17d3a27d2 100644 --- a/ports_module/cortex_a35/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35/gnu/inc/tx_port.h @@ -381,7 +381,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h index 526937546..311b18787 100644 --- a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h @@ -435,7 +435,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h index bc6947060..26c5fb085 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h @@ -435,7 +435,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a7/ac5/inc/tx_port.h b/ports_module/cortex_a7/ac5/inc/tx_port.h index fd061c953..0894320c0 100644 --- a/ports_module/cortex_a7/ac5/inc/tx_port.h +++ b/ports_module/cortex_a7/ac5/inc/tx_port.h @@ -336,7 +336,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a7/gnu/inc/tx_port.h b/ports_module/cortex_a7/gnu/inc/tx_port.h index 41040fa90..865ea379d 100644 --- a/ports_module/cortex_a7/gnu/inc/tx_port.h +++ b/ports_module/cortex_a7/gnu/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a7/iar/inc/tx_port.h b/ports_module/cortex_a7/iar/inc/tx_port.h index fd21d57b3..a12bf89e8 100644 --- a/ports_module/cortex_a7/iar/inc/tx_port.h +++ b/ports_module/cortex_a7/iar/inc/tx_port.h @@ -399,7 +399,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m0+/ac6/inc/tx_port.h b/ports_module/cortex_m0+/ac6/inc/tx_port.h index 374db9391..a94b47b1d 100644 --- a/ports_module/cortex_m0+/ac6/inc/tx_port.h +++ b/ports_module/cortex_m0+/ac6/inc/tx_port.h @@ -509,7 +509,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/gnu/inc/tx_port.h b/ports_module/cortex_m0+/gnu/inc/tx_port.h index 0c2e90e58..7e5690bfb 100644 --- a/ports_module/cortex_m0+/gnu/inc/tx_port.h +++ b/ports_module/cortex_m0+/gnu/inc/tx_port.h @@ -523,7 +523,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/iar/inc/tx_port.h b/ports_module/cortex_m0+/iar/inc/tx_port.h index 2f4abd560..5cc09207f 100644 --- a/ports_module/cortex_m0+/iar/inc/tx_port.h +++ b/ports_module/cortex_m0+/iar/inc/tx_port.h @@ -559,7 +559,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/ac6/inc/tx_port.h b/ports_module/cortex_m23/ac6/inc/tx_port.h index 30f568170..21f7860d3 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_port.h +++ b/ports_module/cortex_m23/ac6/inc/tx_port.h @@ -564,7 +564,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/AC6 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/gnu/inc/tx_port.h b/ports_module/cortex_m23/gnu/inc/tx_port.h index 0f2de686c..46c98bffd 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_port.h +++ b/ports_module/cortex_m23/gnu/inc/tx_port.h @@ -465,7 +465,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/GNU Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/iar/inc/tx_port.h b/ports_module/cortex_m23/iar/inc/tx_port.h index 9f8547da5..5a0db18db 100644 --- a/ports_module/cortex_m23/iar/inc/tx_port.h +++ b/ports_module/cortex_m23/iar/inc/tx_port.h @@ -695,7 +695,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/ac5/inc/tx_port.h b/ports_module/cortex_m3/ac5/inc/tx_port.h index eb5c4a303..e81b37214 100644 --- a/ports_module/cortex_m3/ac5/inc/tx_port.h +++ b/ports_module/cortex_m3/ac5/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/ac6/inc/tx_port.h b/ports_module/cortex_m3/ac6/inc/tx_port.h index eb5c4a303..e81b37214 100644 --- a/ports_module/cortex_m3/ac6/inc/tx_port.h +++ b/ports_module/cortex_m3/ac6/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/gnu/inc/tx_port.h b/ports_module/cortex_m3/gnu/inc/tx_port.h index eb5c4a303..e81b37214 100644 --- a/ports_module/cortex_m3/gnu/inc/tx_port.h +++ b/ports_module/cortex_m3/gnu/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/iar/inc/tx_port.h b/ports_module/cortex_m3/iar/inc/tx_port.h index eb5c4a303..e81b37214 100644 --- a/ports_module/cortex_m3/iar/inc/tx_port.h +++ b/ports_module/cortex_m3/iar/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/ac6/inc/tx_port.h b/ports_module/cortex_m33/ac6/inc/tx_port.h index 9adb6f014..49e3a9756 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_port.h +++ b/ports_module/cortex_m33/ac6/inc/tx_port.h @@ -675,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/gnu/inc/tx_port.h b/ports_module/cortex_m33/gnu/inc/tx_port.h index 9adb6f014..49e3a9756 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_port.h +++ b/ports_module/cortex_m33/gnu/inc/tx_port.h @@ -675,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/iar/inc/tx_port.h b/ports_module/cortex_m33/iar/inc/tx_port.h index 9adb6f014..49e3a9756 100644 --- a/ports_module/cortex_m33/iar/inc/tx_port.h +++ b/ports_module/cortex_m33/iar/inc/tx_port.h @@ -675,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/ac5/inc/tx_port.h b/ports_module/cortex_m4/ac5/inc/tx_port.h index 32f082d57..5b9389721 100644 --- a/ports_module/cortex_m4/ac5/inc/tx_port.h +++ b/ports_module/cortex_m4/ac5/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/ac6/inc/tx_port.h b/ports_module/cortex_m4/ac6/inc/tx_port.h index 32f082d57..5b9389721 100644 --- a/ports_module/cortex_m4/ac6/inc/tx_port.h +++ b/ports_module/cortex_m4/ac6/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/gnu/inc/tx_port.h b/ports_module/cortex_m4/gnu/inc/tx_port.h index 32f082d57..5b9389721 100644 --- a/ports_module/cortex_m4/gnu/inc/tx_port.h +++ b/ports_module/cortex_m4/gnu/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/iar/inc/tx_port.h b/ports_module/cortex_m4/iar/inc/tx_port.h index 32f082d57..5b9389721 100644 --- a/ports_module/cortex_m4/iar/inc/tx_port.h +++ b/ports_module/cortex_m4/iar/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac5/inc/tx_port.h b/ports_module/cortex_m7/ac5/inc/tx_port.h index eed637a10..290af6799 100644 --- a/ports_module/cortex_m7/ac5/inc/tx_port.h +++ b/ports_module/cortex_m7/ac5/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac6/inc/tx_port.h b/ports_module/cortex_m7/ac6/inc/tx_port.h index eed637a10..290af6799 100644 --- a/ports_module/cortex_m7/ac6/inc/tx_port.h +++ b/ports_module/cortex_m7/ac6/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/gnu/inc/tx_port.h b/ports_module/cortex_m7/gnu/inc/tx_port.h index eed637a10..290af6799 100644 --- a/ports_module/cortex_m7/gnu/inc/tx_port.h +++ b/ports_module/cortex_m7/gnu/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/iar/inc/tx_port.h b/ports_module/cortex_m7/iar/inc/tx_port.h index eed637a10..290af6799 100644 --- a/ports_module/cortex_m7/iar/inc/tx_port.h +++ b/ports_module/cortex_m7/iar/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_r4/ac6/inc/tx_port.h b/ports_module/cortex_r4/ac6/inc/tx_port.h index 2b334d2e7..d395df54b 100644 --- a/ports_module/cortex_r4/ac6/inc/tx_port.h +++ b/ports_module/cortex_r4/ac6/inc/tx_port.h @@ -337,7 +337,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC6 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC6 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_r4/iar/inc/tx_port.h b/ports_module/cortex_r4/iar/inc/tx_port.h index ae9421c83..f3b6097c3 100644 --- a/ports_module/cortex_r4/iar/inc/tx_port.h +++ b/ports_module/cortex_r4/iar/inc/tx_port.h @@ -386,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/IAR Version 6.5.1.202602 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/rxv2/iar/inc/tx_port.h b/ports_module/rxv2/iar/inc/tx_port.h index cc4bddee9..43c9176f6 100644 --- a/ports_module/rxv2/iar/inc/tx_port.h +++ b/ports_module/rxv2/iar/inc/tx_port.h @@ -273,7 +273,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/IAR Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h index dd223a9c4..ec99ea9fa 100644 --- a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h +++ b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h @@ -395,7 +395,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/ARC_HS/MetaWare Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/ARC_HS/MetaWare Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h index e26d484bb..89114f47d 100644 --- a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h @@ -388,7 +388,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A5/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A5/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h index 324e2f541..59fa2062c 100644 --- a/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h @@ -391,7 +391,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A5/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A5/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h index 69cba68f0..0c7b48f1e 100644 --- a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h @@ -412,7 +412,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.5.0.202601 *"; + "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h index 6048a9550..00e916d78 100644 --- a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h @@ -412,7 +412,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x-SMP/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x-SMP/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/green/inc/tx_port.h b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h index 5776b1262..aebb117ea 100644 --- a/ports_smp/cortex_a5x_smp/green/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h @@ -432,7 +432,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x-SMP/GHS Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x-SMP/GHS Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h b/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h index f46ceddf5..86507d1dd 100644 --- a/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h @@ -441,7 +441,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x-SMP/IAR Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x-SMP/IAR Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h index 085cffb2a..07185eb69 100644 --- a/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h index 262f2ddf7..81f93d8bb 100644 --- a/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h @@ -411,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h index 69ac4b0f0..ebdbddace 100644 --- a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h @@ -388,7 +388,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A7/AC5 Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A7/AC5 Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h index db3f4093f..7e266e071 100644 --- a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h @@ -386,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A7/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A7/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h index f065d5f21..4abe3aee9 100644 --- a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h @@ -393,7 +393,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h index a35403c74..d9cb3aced 100644 --- a/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h @@ -386,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A9/GNU Version Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A9/GNU Version Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h b/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h index 842b16ae3..432e3b704 100644 --- a/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h @@ -393,7 +393,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-R SMP Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-R SMP Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/linux/gnu/inc/tx_port.h b/ports_smp/linux/gnu/inc/tx_port.h index 30c94702c..3e5e01282 100644 --- a/ports_smp/linux/gnu/inc/tx_port.h +++ b/ports_smp/linux/gnu/inc/tx_port.h @@ -622,7 +622,7 @@ void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG su #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Linux/gcc Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Linux/gcc Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h b/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h index a2429d578..edbf8fd5b 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h +++ b/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h @@ -419,7 +419,7 @@ THREAD_SMP_DECLARE ULONG _tx_thread_smp_initial_fpu_control_register; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP MIPS32_interAptiv/GNU Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP MIPS32_interAptiv/GNU Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h b/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h index a4b88d1b1..4eb4f3d67 100644 --- a/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h +++ b/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h @@ -509,7 +509,7 @@ THREAD_SMP_DECLARE ULONG _tx_thread_smp_initial_fpu_control_register; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP MIPS32_interAptiv/Green Hills Version 6.5.0.202601 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP MIPS32_interAptiv/Green Hills Version 6.5.1.202602 *"; #else extern CHAR _tx_version_id[]; #endif From 730b61874bc5cf40768987605ae5187fde0fa1e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Sat, 6 Jun 2026 21:42:47 +0200 Subject: [PATCH 29/29] Added copyright headers to files missing them Applied the standard MIT license header to all project-owned C, header, assembly, shell, and Python files that were missing a copyright notice. Third-party, toolchain startup, and auto-generated files were excluded. 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+++++++++++ .../threadx_timer_information_test.c | 11 +++++++++++ .../threadx_timer_large_timer_accuracy_test.c | 11 +++++++++++ .../threadx_timer_multiple_accuracy_test.c | 11 +++++++++++ .../regression/threadx_timer_multiple_test.c | 11 +++++++++++ .../tx/regression/threadx_timer_simple_test.c | 11 +++++++++++ test/tx/regression/threadx_trace_basic_test.c | 11 +++++++++++ .../threadx_tm_basic_test_example.c | 11 +++++++++++ ...x_tm_cooperative_scheduling_test_example.c | 11 +++++++++++ ...adx_tm_interrupt_preemption_test_example.c | 11 +++++++++++ .../threadx_tm_interrupt_test_example.c | 11 +++++++++++ ...hreadx_tm_memory_allocation_test_example.c | 11 +++++++++++ ...readx_tm_message_processing_test_example.c | 11 +++++++++++ ...dx_tm_preemptive_scheduling_test_example.c | 11 +++++++++++ .../threadx_tm_synchronization_test_example.c | 11 +++++++++++ .../OSEK/demo_osek.c | 11 +++++++++++ .../posix/posix_demo.c | 11 +++++++++++ .../posix/posix_signal_nested_test.c | 11 +++++++++++ .../posix/posix_signal_resume_thread_test.c | 11 +++++++++++ .../posix/posix_signal_self_send_test.c | 11 +++++++++++ .../posix/posix_signal_sigmask_test.c | 11 +++++++++++ .../posix/posix_signal_sigwait_test.c | 11 +++++++++++ .../posix_signal_suspended_thread_test.c | 11 +++++++++++ 581 files changed, 6382 insertions(+), 2 deletions(-) diff --git a/common_modules/module_manager/utilities/module_to_binary.c b/common_modules/module_manager/utilities/module_to_binary.c index a749c8a32..bb4f294d0 100644 --- a/common_modules/module_manager/utilities/module_to_binary.c +++ b/common_modules/module_manager/utilities/module_to_binary.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include #include #include diff --git a/common_modules/module_manager/utilities/module_to_c_array.c b/common_modules/module_manager/utilities/module_to_c_array.c index 37d931f39..d34724164 100644 --- a/common_modules/module_manager/utilities/module_to_c_array.c +++ b/common_modules/module_manager/utilities/module_to_c_array.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include #include #include diff --git a/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c index 6ce6e0d43..8369fbbc6 100644 --- a/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c +++ b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/arc_em/metaware/example_build/sample_threadx/vectors.s b/ports/arc_em/metaware/example_build/sample_threadx/vectors.s index eeb9ba2ad..452f536b5 100644 --- a/ports/arc_em/metaware/example_build/sample_threadx/vectors.s +++ b/ports/arc_em/metaware/example_build/sample_threadx/vectors.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .file "vectors.s" .section .ivt,text diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c index 6ce6e0d43..8369fbbc6 100644 --- a/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c +++ b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s b/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s index eeb9ba2ad..452f536b5 100644 --- a/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s +++ b/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .file "vectors.s" .section .ivt,text diff --git a/ports/arm11/ac5/example_build/sample_threadx.c b/ports/arm11/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/arm11/ac5/example_build/sample_threadx.c +++ b/ports/arm11/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/arm11/gnu/example_build/sample_threadx.c b/ports/arm11/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/arm11/gnu/example_build/sample_threadx.c +++ b/ports/arm11/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/arm11/iar/example_build/sample_threadx.c b/ports/arm11/iar/example_build/sample_threadx.c index f9d0e94a2..e702053ea 100644 --- a/ports/arm11/iar/example_build/sample_threadx.c +++ b/ports/arm11/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/arm9/ac5/example_build/sample_threadx.c b/ports/arm9/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/arm9/ac5/example_build/sample_threadx.c +++ b/ports/arm9/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/arm9/gnu/example_build/sample_threadx.c b/ports/arm9/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/arm9/gnu/example_build/sample_threadx.c +++ b/ports/arm9/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/arm9/iar/example_build/sample_threadx.c b/ports/arm9/iar/example_build/sample_threadx.c index 56f7cd55e..544f30cc3 100644 --- a/ports/arm9/iar/example_build/sample_threadx.c +++ b/ports/arm9/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/c667x/ccs/example_build/include/C66XX.h b/ports/c667x/ccs/example_build/include/C66XX.h index 80507ca26..ba1bfdc0f 100644 --- a/ports/c667x/ccs/example_build/include/C66XX.h +++ b/ports/c667x/ccs/example_build/include/C66XX.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /****************************************************************************** TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. Definitions, macros and API functions for DSP Environment. diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP.h b/ports/c667x/ccs/example_build/include/TA66XX_DSP.h index ba3fa3417..460948156 100644 --- a/ports/c667x/ccs/example_build/include/TA66XX_DSP.h +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /****************************************************************************** TORNADO AMC modules Software Development Kit (SDK). Rev 4A. General definitions and API functions. diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h index 028ce3367..8ad2ae8af 100644 --- a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /****************************************************************************** TORNADO AMC modules Software Development Kit (SDK). Rev 4A. Definitions, macros and API functions for DSP Environment. diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c index 31e8056bd..c9630103f 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* * board_setup.c * diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h index 9e252dcdc..2ead869cd 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* * board_setup.h * diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c index a97ce125e..5e7228eb7 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ @@ -89,7 +100,7 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = TX_NULL; UINT status; - /* Enable event tracing using the global “trace_buffer” memory and supporting + /* Enable event tracing using the global �trace_buffer� memory and supporting a maximum of TRACE_OBJECTS_COUNT ThreadX objects in the registry. */ if ((status = tx_trace_enable(tx_trace_buffer, TRACE_BUFFER_SIZE, TRACE_OBJECTS_COUNT)) != TX_SUCCESS) { diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c index e5b8a0bfb..12d790650 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* * board_setup.c * diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h index a65e3b9d8..a68661f38 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* * board_setup.h * diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c index a97ce125e..5e7228eb7 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ @@ -89,7 +100,7 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = TX_NULL; UINT status; - /* Enable event tracing using the global “trace_buffer” memory and supporting + /* Enable event tracing using the global �trace_buffer� memory and supporting a maximum of TRACE_OBJECTS_COUNT ThreadX objects in the registry. */ if ((status = tx_trace_enable(tx_trace_buffer, TRACE_BUFFER_SIZE, TRACE_OBJECTS_COUNT)) != TX_SUCCESS) { diff --git a/ports/cortex_a12/ac6/example_build/sample_threadx.c b/ports/cortex_a12/ac6/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a12/ac6/example_build/sample_threadx.c +++ b/ports/cortex_a12/ac6/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a12/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a12/ac6/example_build/sample_threadx/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a12/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a12/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a12/gnu/example_build/sample_threadx.c b/ports/cortex_a12/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a12/gnu/example_build/sample_threadx.c +++ b/ports/cortex_a12/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx.c b/ports/cortex_a15/ac6/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a15/ac6/example_build/sample_threadx.c +++ b/ports/cortex_a15/ac6/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a15/gnu/example_build/sample_threadx.c b/ports/cortex_a15/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a15/gnu/example_build/sample_threadx.c +++ b/ports/cortex_a15/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a15/iar/example_build/sample_threadx.c b/ports/cortex_a15/iar/example_build/sample_threadx.c index afbd4ea81..ed04e3b6b 100644 --- a/ports/cortex_a15/iar/example_build/sample_threadx.c +++ b/ports/cortex_a15/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a17/ac6/example_build/sample_threadx.c b/ports/cortex_a17/ac6/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a17/ac6/example_build/sample_threadx.c +++ b/ports/cortex_a17/ac6/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a17/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a17/ac6/example_build/sample_threadx/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a17/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a17/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a17/gnu/example_build/sample_threadx.c b/ports/cortex_a17/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a17/gnu/example_build/sample_threadx.c +++ b/ports/cortex_a17/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a5/ac5/example_build/sample_threadx.c b/ports/cortex_a5/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a5/ac5/example_build/sample_threadx.c +++ b/ports/cortex_a5/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a5/ac6/example_build/sample_threadx.c b/ports/cortex_a5/ac6/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a5/ac6/example_build/sample_threadx.c +++ b/ports/cortex_a5/ac6/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a5/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a5/ac6/example_build/sample_threadx/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a5/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a5/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a5/ghs/example_build/sample_threadx.c b/ports/cortex_a5/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a5/ghs/example_build/sample_threadx.c +++ b/ports/cortex_a5/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a5/gnu/example_build/sample_threadx.c b/ports/cortex_a5/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a5/gnu/example_build/sample_threadx.c +++ b/ports/cortex_a5/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a5/iar/example_build/sample_threadx.c b/ports/cortex_a5/iar/example_build/sample_threadx.c index 56f7cd55e..544f30cc3 100644 --- a/ports/cortex_a5/iar/example_build/sample_threadx.c +++ b/ports/cortex_a5/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a53/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a53/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a53/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a53/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a53/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a53/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a53/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a53/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a55/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a55/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a55/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a55/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a55/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a55/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a55/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a55/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a57/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a57/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a57/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a57/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a57/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a57/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a57/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a57/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c index d37d4c270..df7f89c3f 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + // ---------------------------------------------------------- // GIC400 - Generic Interrupt Controller // diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.h b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.h index aca064c38..f7f0ce7ab 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.h +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + // ---------------------------------------------------------- // GIC400 - Generic Interrupt Controller // Header diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c index 3e4c45a5b..ff7ff826c 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a65/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a65/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a65/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a65/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a65/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a65/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a65/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a65/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a65ae/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a65ae/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a65ae/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a65ae/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a65ae/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a65ae/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a65ae/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a65ae/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a7/ac5/example_build/sample_threadx.c b/ports/cortex_a7/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a7/ac5/example_build/sample_threadx.c +++ b/ports/cortex_a7/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx.c b/ports/cortex_a7/ac6/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a7/ac6/example_build/sample_threadx.c +++ b/ports/cortex_a7/ac6/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a7/ghs/example_build/sample_threadx.c b/ports/cortex_a7/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a7/ghs/example_build/sample_threadx.c +++ b/ports/cortex_a7/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a7/gnu/example_build/sample_threadx.c b/ports/cortex_a7/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a7/gnu/example_build/sample_threadx.c +++ b/ports/cortex_a7/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a7/iar/example_build/sample_threadx.c b/ports/cortex_a7/iar/example_build/sample_threadx.c index 02183317e..011ee3989 100644 --- a/ports/cortex_a7/iar/example_build/sample_threadx.c +++ b/ports/cortex_a7/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a72/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a72/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a72/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a72/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a73/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a73/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a73/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a73/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a73/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a73/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a73/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a73/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a75/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a75/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a75/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a75/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a75/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a75/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a75/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a75/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a76/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a76/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a76/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a76/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a76/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a76/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a76/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a76/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a76ae/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a76ae/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a76ae/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a76ae/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a76ae/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a76ae/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a76ae/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a76ae/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a77/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a77/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a77/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a77/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a77/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a77/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports/cortex_a77/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a77/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a8/ac5/example_build/sample_threadx.c b/ports/cortex_a8/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a8/ac5/example_build/sample_threadx.c +++ b/ports/cortex_a8/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx.c b/ports/cortex_a8/ac6/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a8/ac6/example_build/sample_threadx.c +++ b/ports/cortex_a8/ac6/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a8/ghs/example_build/sample_threadx.c b/ports/cortex_a8/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a8/ghs/example_build/sample_threadx.c +++ b/ports/cortex_a8/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a8/gnu/example_build/sample_threadx.c b/ports/cortex_a8/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a8/gnu/example_build/sample_threadx.c +++ b/ports/cortex_a8/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a8/iar/example_build/sample_threadx.c b/ports/cortex_a8/iar/example_build/sample_threadx.c index afbd4ea81..ed04e3b6b 100644 --- a/ports/cortex_a8/iar/example_build/sample_threadx.c +++ b/ports/cortex_a8/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a9/ac5/example_build/sample_threadx.c b/ports/cortex_a9/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a9/ac5/example_build/sample_threadx.c +++ b/ports/cortex_a9/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx.c b/ports/cortex_a9/ac6/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a9/ac6/example_build/sample_threadx.c +++ b/ports/cortex_a9/ac6/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a9/ghs/example_build/sample_threadx.c b/ports/cortex_a9/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a9/ghs/example_build/sample_threadx.c +++ b/ports/cortex_a9/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a9/gnu/example_build/sample_threadx.c b/ports/cortex_a9/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_a9/gnu/example_build/sample_threadx.c +++ b/ports/cortex_a9/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.c b/ports/cortex_a9/iar/example_build/sample_threadx.c index afbd4ea81..ed04e3b6b 100644 --- a/ports/cortex_a9/iar/example_build/sample_threadx.c +++ b/ports/cortex_a9/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m0/ac5/example_build/sample_threadx.c b/ports/cortex_m0/ac5/example_build/sample_threadx.c index dd5ee1554..66d681208 100644 --- a/ports/cortex_m0/ac5/example_build/sample_threadx.c +++ b/ports/cortex_m0/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c index 01f48910d..cda6927f7 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m0/gnu/example_build/sample_threadx.c b/ports/cortex_m0/gnu/example_build/sample_threadx.c index 01f48910d..cda6927f7 100644 --- a/ports/cortex_m0/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m0/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m0/iar/example_build/sample_threadx.c b/ports/cortex_m0/iar/example_build/sample_threadx.c index 8f1d97572..081a200ed 100644 --- a/ports/cortex_m0/iar/example_build/sample_threadx.c +++ b/ports/cortex_m0/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m0/keil/example_build/sample_threadx.c b/ports/cortex_m0/keil/example_build/sample_threadx.c index dd5ee1554..66d681208 100644 --- a/ports/cortex_m0/keil/example_build/sample_threadx.c +++ b/ports/cortex_m0/keil/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c index df82f09b3..da1556e11 100644 --- a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete diff --git a/ports/cortex_m3/ac5/example_build/sample_threadx.c b/ports/cortex_m3/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_m3/ac5/example_build/sample_threadx.c +++ b/ports/cortex_m3/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m3/ghs/example_build/sample_threadx.c b/ports/cortex_m3/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_m3/ghs/example_build/sample_threadx.c +++ b/ports/cortex_m3/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m3/gnu/example_build/sample_threadx.c b/ports/cortex_m3/gnu/example_build/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports/cortex_m3/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m3/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m3/iar/example_build/sample_threadx.c b/ports/cortex_m3/iar/example_build/sample_threadx.c index a12160fa0..3b1fcf42e 100644 --- a/ports/cortex_m3/iar/example_build/sample_threadx.c +++ b/ports/cortex_m3/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m3/keil/example_build/sample_threadx.c b/ports/cortex_m3/keil/example_build/sample_threadx.c index 34453f42f..2f0e2b985 100644 --- a/ports/cortex_m3/keil/example_build/sample_threadx.c +++ b/ports/cortex_m3/keil/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of six threads of different priorities, using a message queue, semaphore, and an event flags group. */ diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c index cea228899..37233c9a4 100644 --- a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete diff --git a/ports/cortex_m33/gnu/example_build/sample_threadx.c b/ports/cortex_m33/gnu/example_build/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports/cortex_m33/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m33/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m4/ac5/example_build/sample_threadx.c b/ports/cortex_m4/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_m4/ac5/example_build/sample_threadx.c +++ b/ports/cortex_m4/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m4/ghs/example_build/sample_threadx.c b/ports/cortex_m4/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_m4/ghs/example_build/sample_threadx.c +++ b/ports/cortex_m4/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m4/gnu/example_build/sample_threadx.c b/ports/cortex_m4/gnu/example_build/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports/cortex_m4/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m4/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m4/iar/example_build/sample_threadx.c b/ports/cortex_m4/iar/example_build/sample_threadx.c index 55b637313..a1b9cf039 100644 --- a/ports/cortex_m4/iar/example_build/sample_threadx.c +++ b/ports/cortex_m4/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete diff --git a/ports/cortex_m4/keil/example_build/demo_threadx.c b/ports/cortex_m4/keil/example_build/demo_threadx.c index 34453f42f..2f0e2b985 100644 --- a/ports/cortex_m4/keil/example_build/demo_threadx.c +++ b/ports/cortex_m4/keil/example_build/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of six threads of different priorities, using a message queue, semaphore, and an event flags group. */ diff --git a/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c index cea228899..37233c9a4 100644 --- a/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c +++ b/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete diff --git a/ports/cortex_m55/gnu/example_build/sample_threadx.c b/ports/cortex_m55/gnu/example_build/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports/cortex_m55/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m55/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m7/ac5/example_build/sample_threadx.c b/ports/cortex_m7/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_m7/ac5/example_build/sample_threadx.c +++ b/ports/cortex_m7/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m7/ghs/example_build/sample_threadx.c b/ports/cortex_m7/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_m7/ghs/example_build/sample_threadx.c +++ b/ports/cortex_m7/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m7/gnu/example_build/sample_threadx.c b/ports/cortex_m7/gnu/example_build/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports/cortex_m7/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m7/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_m7/iar/example_build/sample_threadx.c b/ports/cortex_m7/iar/example_build/sample_threadx.c index f1f4cb876..4ad474a19 100644 --- a/ports/cortex_m7/iar/example_build/sample_threadx.c +++ b/ports/cortex_m7/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete diff --git a/ports/cortex_m85/gnu/example_build/sample_threadx.c b/ports/cortex_m85/gnu/example_build/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports/cortex_m85/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m85/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r4/ac5/example_build/sample_threadx.c b/ports/cortex_r4/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_r4/ac5/example_build/sample_threadx.c +++ b/ports/cortex_r4/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/gic.c b/ports/cortex_r4/ac6/example_build/sample_threadx/gic.c index 32f21bbe1..954d4fcd5 100644 --- a/ports/cortex_r4/ac6/example_build/sample_threadx/gic.c +++ b/ports/cortex_r4/ac6/example_build/sample_threadx/gic.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /** GIC start **/ /* ------------------------- Interrupt Number Definition ------------------------ */ diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c index 6a996f775..05ad809b3 100644 --- a/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/timer.c b/ports/cortex_r4/ac6/example_build/sample_threadx/timer.c index e964d0f6e..c71cab987 100644 --- a/ports/cortex_r4/ac6/example_build/sample_threadx/timer.c +++ b/ports/cortex_r4/ac6/example_build/sample_threadx/timer.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "gic.h" /* Systick registers */ diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/timer.h b/ports/cortex_r4/ac6/example_build/sample_threadx/timer.h index efab1fe19..6bb3b238e 100644 --- a/ports/cortex_r4/ac6/example_build/sample_threadx/timer.h +++ b/ports/cortex_r4/ac6/example_build/sample_threadx/timer.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #ifndef TIMER_H #define TIMER_H void timer_init(); diff --git a/ports/cortex_r4/ghs/example_build/sample_threadx.c b/ports/cortex_r4/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_r4/ghs/example_build/sample_threadx.c +++ b/ports/cortex_r4/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r4/gnu/example_build/sample_threadx.c b/ports/cortex_r4/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_r4/gnu/example_build/sample_threadx.c +++ b/ports/cortex_r4/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r4/iar/example_build/sample_threadx.c b/ports/cortex_r4/iar/example_build/sample_threadx.c index ca92ff864..524967678 100644 --- a/ports/cortex_r4/iar/example_build/sample_threadx.c +++ b/ports/cortex_r4/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r5/ac5/example_build/sample_threadx.c b/ports/cortex_r5/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_r5/ac5/example_build/sample_threadx.c +++ b/ports/cortex_r5/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r5/ghs/example_build/sample_threadx.c b/ports/cortex_r5/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_r5/ghs/example_build/sample_threadx.c +++ b/ports/cortex_r5/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r5/gnu/example_build/sample_threadx.c b/ports/cortex_r5/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_r5/gnu/example_build/sample_threadx.c +++ b/ports/cortex_r5/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r5/iar/example_build/sample_threadx.c b/ports/cortex_r5/iar/example_build/sample_threadx.c index ca92ff864..524967678 100644 --- a/ports/cortex_r5/iar/example_build/sample_threadx.c +++ b/ports/cortex_r5/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/cortex_r7/ghs/example_build/sample_threadx.c b/ports/cortex_r7/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports/cortex_r7/ghs/example_build/sample_threadx.c +++ b/ports/cortex_r7/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/linux/gnu/example_build/sample_threadx.c b/ports/linux/gnu/example_build/sample_threadx.c index 43c0bdd46..99fd42a4a 100644 --- a/ports/linux/gnu/example_build/sample_threadx.c +++ b/ports/linux/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/risc-v32/clang/example_build/qemu_virt/build_libthreadx.sh b/ports/risc-v32/clang/example_build/qemu_virt/build_libthreadx.sh index ff84c9749..4d3695e4e 100755 --- a/ports/risc-v32/clang/example_build/qemu_virt/build_libthreadx.sh +++ b/ports/risc-v32/clang/example_build/qemu_virt/build_libthreadx.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + pushd ../../../../../ #cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_clang.cmake . diff --git a/ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh b/ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh index cda0edbb9..d774ca9c4 100755 --- a/ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh +++ b/ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + DIRNAME=$(dirname "$0") BASEDIR=$DIRNAME/../../../../.. diff --git a/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c b/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c index a5955b298..449b397b1 100644 --- a/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c +++ b/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/risc-v32/clang/example_build/qemu_virt/entry.S b/ports/risc-v32/clang/example_build/qemu_virt/entry.S index 9b202ca16..f9645bc70 100644 --- a/ports/risc-v32/clang/example_build/qemu_virt/entry.S +++ b/ports/risc-v32/clang/example_build/qemu_virt/entry.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .section .text .align 4 diff --git a/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh b/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh index 2e1bb844b..b610ac42c 100755 --- a/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh +++ b/ports/risc-v32/gnu/example_build/core_v_mcu/build.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + set -e XPACK_GCC_DIR=/opt/xpack-riscv-none-elf-gcc-15.2.0-1 diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/build_libthreadx.sh b/ports/risc-v32/gnu/example_build/cva6_ariane/build_libthreadx.sh index 53fd34924..23f707dc7 100644 --- a/ports/risc-v32/gnu/example_build/cva6_ariane/build_libthreadx.sh +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/build_libthreadx.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + pushd ../../../../../ cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_gnu.cmake -DSOFT_FLOAT=1 . diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/demo_threadx.c b/ports/risc-v32/gnu/example_build/cva6_ariane/demo_threadx.c index f21dbb26b..adc56f4a2 100644 --- a/ports/risc-v32/gnu/example_build/cva6_ariane/demo_threadx.c +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/entry.S b/ports/risc-v32/gnu/example_build/cva6_ariane/entry.S index 9b202ca16..f9645bc70 100644 --- a/ports/risc-v32/gnu/example_build/cva6_ariane/entry.S +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/entry.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .section .text .align 4 diff --git a/ports/risc-v32/gnu/example_build/cva6_ariane/trap.c b/ports/risc-v32/gnu/example_build/cva6_ariane/trap.c index 3d2467fb5..520b74a53 100644 --- a/ports/risc-v32/gnu/example_build/cva6_ariane/trap.c +++ b/ports/risc-v32/gnu/example_build/cva6_ariane/trap.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "csr.h" #include #include "uart.h" diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh b/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh index f6ec0bcd1..d0e092da5 100755 --- a/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh +++ b/ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + printf "y\n" | rm -rf ../../../../../build/ rm -f kernel.elf diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c b/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c index 6cf490148..8288e7493 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c +++ b/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/entry.S b/ports/risc-v32/gnu/example_build/qemu_virt/entry.S index 06cc2a2c3..598a072ef 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/entry.S +++ b/ports/risc-v32/gnu/example_build/qemu_virt/entry.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .section .text.boot, "ax" .align 4 diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv32_qemu.py b/ports/risc-v32/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv32_qemu.py index 858b96e6a..6123cd73b 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv32_qemu.py +++ b/ports/risc-v32/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv32_qemu.py @@ -1,3 +1,14 @@ +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + import subprocess import sys import os diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_libthreadx.sh b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_libthreadx.sh index ff9bb9306..ff983efe3 100755 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_libthreadx.sh +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_libthreadx.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + pushd ../../../../../ rm -rf build diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_threadx_sample.sh b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_threadx_sample.sh index ec91e36a5..cc0b6a67e 100755 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_threadx_sample.sh +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_threadx_sample.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + bash build_libthreadx.sh diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h index e69de29bb..054d0844c 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h @@ -0,0 +1,11 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/list.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/list.h index 9f65050cb..5a09070c2 100755 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/list.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/list.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #ifndef AOS_LIST_H #define AOS_LIST_H diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c index 3df2c251e..f8a6d82ca 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/risc-v32/iar/example_build/sample_threadx.c b/ports/risc-v32/iar/example_build/sample_threadx.c index 3c6d2587c..13128282e 100644 --- a/ports/risc-v32/iar/example_build/sample_threadx.c +++ b/ports/risc-v32/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/build_libthreadx.sh b/ports/risc-v64/gnu/example_build/bananapi-f3/build_libthreadx.sh index 249ce68ce..2c94b8a15 100755 --- a/ports/risc-v64/gnu/example_build/bananapi-f3/build_libthreadx.sh +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/build_libthreadx.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + # Build the bananapi-f3 (SpacemiT K1) ThreadX kernel. # # Boot flow: FSBL -> OpenSBI (M-mode) -> U-Boot (S-mode) -> ThreadX (S-mode). diff --git a/ports/risc-v64/gnu/example_build/bananapi-f3/demo_threadx.c b/ports/risc-v64/gnu/example_build/bananapi-f3/demo_threadx.c index 93213c53a..2023df128 100644 --- a/ports/risc-v64/gnu/example_build/bananapi-f3/demo_threadx.c +++ b/ports/risc-v64/gnu/example_build/bananapi-f3/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/board.c b/ports/risc-v64/gnu/example_build/qemu_virt/board.c index 60a61163a..805a1ac8e 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/board.c +++ b/ports/risc-v64/gnu/example_build/qemu_virt/board.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "plic.h" #include "hwtimer.h" #include "uart.h" diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh b/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh index b655820ea..0568e7a82 100755 --- a/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh +++ b/ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + printf "y\n" | rm -rf ../../../../../build/ rm -f kernel.elf diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c b/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c index 9cbb33da2..d3195019d 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c +++ b/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/entry.S b/ports/risc-v64/gnu/example_build/qemu_virt/entry.S index 791d08eb2..2b68310d4 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/entry.S +++ b/ports/risc-v64/gnu/example_build/qemu_virt/entry.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .section .text .align 4 diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/hwtimer.c b/ports/risc-v64/gnu/example_build/qemu_virt/hwtimer.c index 29cf1117b..122e71a18 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/hwtimer.c +++ b/ports/risc-v64/gnu/example_build/qemu_virt/hwtimer.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_port.h" #include "csr.h" #include "hwtimer.h" diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv64_qemu.py b/ports/risc-v64/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv64_qemu.py index 459fdf217..861f50e61 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv64_qemu.py +++ b/ports/risc-v64/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv64_qemu.py @@ -1,3 +1,14 @@ +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + import subprocess import sys import os diff --git a/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c index 4bd7f5bc5..517edbcec 100644 --- a/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c +++ b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports/xtensa/xcc/example_build/demo_threadx.c b/ports/xtensa/xcc/example_build/demo_threadx.c index 72632323d..0199a1442 100644 --- a/ports/xtensa/xcc/example_build/demo_threadx.c +++ b/ports/xtensa/xcc/example_build/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-A/threadx/common/example_build/sample_threadx.c b/ports_arch/ARMv7-A/threadx/common/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports_arch/ARMv7-A/threadx/common/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-A/threadx/common/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/sample_threadx.c b/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.c b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.c b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.c b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.c index 02183317e..011ee3989 100644 --- a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-M/threadx/ac5/example_build/sample_threadx.c b/ports_arch/ARMv7-M/threadx/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-M/threadx/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/sample_threadx.c b/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-M/threadx/ghs/example_build/sample_threadx.c b/ports_arch/ARMv7-M/threadx/ghs/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-M/threadx/ghs/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.c b/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv7-M/threadx/iar/example_build/sample_threadx.c b/ports_arch/ARMv7-M/threadx/iar/example_build/sample_threadx.c index 55b637313..a1b9cf039 100644 --- a/ports_arch/ARMv7-M/threadx/iar/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-M/threadx/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete diff --git a/ports_arch/ARMv8-A/threadx/common/example_build/sample_threadx/sample_threadx.c b/ports_arch/ARMv8-A/threadx/common/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_arch/ARMv8-A/threadx/common/example_build/sample_threadx/sample_threadx.c +++ b/ports_arch/ARMv8-A/threadx/common/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_arch/ARMv8-A/threadx_smp/common/example_build/sample_threadx/sample_threadx.c b/ports_arch/ARMv8-A/threadx_smp/common/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/example_build/sample_threadx/sample_threadx.c +++ b/ports_arch/ARMv8-A/threadx_smp/common/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c index 736722fbb..5a56f8377 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c index 3476367e3..9119f5215 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S index ad75e134a..4fb8fac58 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .section Init diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c0772002c..475aabb31 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c index 736722fbb..5a56f8377 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c index 3476367e3..9119f5215 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S index bb0acb6f0..34b0cf6db 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .section .txm_module_preamble, "ax" .align 4 diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c0772002c..475aabb31 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c index 9d1733a5e..21c3c9ba8 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c index e94ac221e..64ee0a388 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S index ad75e134a..4fb8fac58 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .section Init diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c0772002c..475aabb31 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c index 9d1733a5e..21c3c9ba8 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c index e94ac221e..64ee0a388 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S index bb0acb6f0..34b0cf6db 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .section .txm_module_preamble, "ax" .align 4 diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c0772002c..475aabb31 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_a7/ac5/example_build/module_code.c b/ports_module/cortex_a7/ac5/example_build/module_code.c index e42bf43bd2e8ab30d9476dd8bddb50daa165ff1b..653782ace62f1147fd0e0b29ea97d9998a6f944a 100644 GIT binary patch delta 3443 zcmb`}d6*Jq0LSrNO;Sp-QdTQzx=6PKH6yd4LnSRG%Z;=HMHZH+-5DBKbUWBiy2*{A zvZ9;pqSB&Mw2LkyQzNq?E2Z;U`zQYD;b|89jy`EU+0(!?eE7Zd{$^et{&-6p`)}RU zzuVgU{~cDnwON=f2fGxpEf5w)c}EN5$Bv&M%oM$f9FqNEbx;Y)iYF|}l2ALk>mR#1 zH}AU6CQS9Vi@}gjXbC7jPwO1PD@$QTT+kVomC&w=YFWK)r{RCN|4!HL7}V=p0%AxA zDsr3R=@2|ps}K(O1drD%cLY6BmngLf9iFgH5k2i8!K3)pZ>{Qh#3QzQ7PR|>PN}uq zr}Wj<>-uJ^mv@8&*~UQMj(S$*~VK5sw` ziMfsI>RLXo-^j*BePUd{5s5(m!Zyv?15F%&1RWZTw0JMHXm2!s zFq&pSWA{PBht$=Ss18|Ed#a{Hd0$l64`ug9si7z~3`s`hYC`tm$UFiW4nP%6r31;=_i2NrZrybc&My6Ac z?o`yPsdyS$ZZb+wLGh_5;y~`xkz*RNOh?8uP*qd;OtQiZl%0uEP82%}NwbjaY-B$N znP($I3#w=;olBN?q0D(GIR{1OBLDfwc>%Irh)fqDog4LPD$XOz%|~euiZ4JBFLJjc zhYwl&$k>Len#uvPf{3ygqtqoR){dkO_pKB@-IZr zMab5LOqU_u<)~Lv@d~osl_(uW@op5k3c0UFj%$$RT4cNqRW+5bCo9BI_6C%?5yfso z(#^IO4QB_m<5wgOgDEk;nJ&s~&Bt3y#OOgFaWPS=6o<5lXH`(T|b8fSjKo+Zts0 z6zSHYUQNYyWV!Vy{TYfEQRH*v-hdomAj?K%{1R0)mA@h@e2uatl==q6HX-R-f5=d#LyoY{zKE|AIVn#RM)V?vY*%1Hdww|(#8PW43%U%;mg%Mwy6G^co2-OxG+U;dE}3rZVxfz&g6_>S zrtP8=vWqNZ)U4G~rc1ZW<*%Oor+R7G7~Ay4FxB$32np0w=LA1EaxXpwuJ^~YYLb8 zRLa;6N^j3bm$@XSQR)tmXGb>P>0F#UQLVPBJF}^IxD0rq*sgNEe-~S5aE|ZBCA>SO z>>-q!!9?1V!*EBY4|m0xY)X5v$?Q#Ov!LKUY(l+Ue152@i04skp~2bOmrH#=%Ge)D zAHYUGkW1nqN}$YPD58j7{xuE(1qEv7mUKBWRv+-WT#d$5&YO8u3o7(kQvNz!Dzgav@3TG&FBNe~N78~UjF7mCEv=C}6WMihe zRCKCz8^nBby=)5iQTqK*0p~hl1=9641Pf?|( zp=6PbR^k$Uh6+6kxt~K*eo?&7^EgAJ9a%5fcWjK8*c1jR{beY!gpK+Nm%yu(cPTWo zluhe3E<pV$B kCjLSF)6s@MaTn{El3(`M$}uhZo62uqJ-+>=B)*&e2dRj?4gdfE diff --git a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c index f9ed56ebc..a2da69435 100644 --- a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c index ac3bbeb59..3f1b1475b 100644 --- a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. This demonstration assumes the program manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for use. */ diff --git a/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s b/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s index 953a1d62b..1df558618 100644 --- a/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + AREA Init, CODE, READONLY ; /* Define public symbols. */ diff --git a/ports_module/cortex_a7/gnu/example_build/gcc_setup.S b/ports_module/cortex_a7/gnu/example_build/gcc_setup.S index d0eaeb798..621ce6a9e 100644 --- a/ports_module/cortex_a7/gnu/example_build/gcc_setup.S +++ b/ports_module/cortex_a7/gnu/example_build/gcc_setup.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .syntax unified #if !defined(THUMB_MODE) diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c index f9ed56ebc..a2da69435 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c index ac3bbeb59..3f1b1475b 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. This demonstration assumes the program manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for use. */ diff --git a/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s index 90c0c3384..6a01f53b7 100644 --- a/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .section .txm_module_preamble, "ax" .align 4 diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c index 33a22445d..f94fb9927 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c index b3a4f2f94..4ed31dd84 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. This demonstration assumes the program manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for use. */ diff --git a/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s index 4a42627b8..3167f7c32 100644 --- a/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + SECTION .text:CODE AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c index dcf73ef90..8cd5c375c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 71914151a..0834862a7 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 4edcee3cf..a8cdedd4e 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s index ef3d93140..5efe3625c 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .syntax unified .section .vectors, "ax" diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c index dcf73ef90..8cd5c375c 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S index 8ea214ba6..884447166 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index f47155b89..82a40f75d 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s index 452c89346..3375b4f43 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .syntax unified .section .vectors, "ax" diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx.c index a12160fa0..3b1fcf42e 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c index a91c3b8ca..4fbbbb396 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c index b944f46e0..c82697e81 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m0+/iar/example_build/txm_module_preamble.s b/ports_module/cortex_m0+/iar/example_build/txm_module_preamble.s index 5488df2ae..f0b3ec7fb 100644 --- a/ports_module/cortex_m0+/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_m0+/iar/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + SECTION .text:CODE AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c index 50a404606..e23645b64 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c index cbf252e49..c8f0ca85a 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 302efdf2b..e898890d8 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c index b74d7a357..4e464beeb 100644 --- a/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S index 5f6635695..5dd8e9c59 100644 --- a/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c index e9605af81..2d605570c 100644 --- a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c index 59aee1b9e..a67820ac9 100644 --- a/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m23/iar/example_build/txm_module_preamble.s b/ports_module/cortex_m23/iar/example_build/txm_module_preamble.s index 6a462980d..7f71a50f4 100644 --- a/ports_module/cortex_m23/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_m23/iar/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + SECTION .text:CODE AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE diff --git a/ports_module/cortex_m3/ac5/example_build/sample_threadx.c b/ports_module/cortex_m3/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports_module/cortex_m3/ac5/example_build/sample_threadx.c +++ b/ports_module/cortex_m3/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c index dcf73ef90..8cd5c375c 100644 --- a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c index 4edcee3cf..a8cdedd4e 100644 --- a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m3/ac5/example_build/txm_module_preamble.S b/ports_module/cortex_m3/ac5/example_build/txm_module_preamble.S index 1e7a18000..c3971bcb4 100644 --- a/ports_module/cortex_m3/ac5/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m3/ac5/example_build/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + AREA Init, CODE, READONLY PRESERVE8 diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c index dcf73ef90..8cd5c375c 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 71914151a..0834862a7 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 4edcee3cf..a8cdedd4e 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c index b74d7a357..4e464beeb 100644 --- a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c index feaaf2af1..cd8aa62b1 100644 --- a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s b/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s index ef3d93140..5efe3625c 100644 --- a/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s +++ b/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .syntax unified .section .vectors, "ax" diff --git a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S index b032a347f..450be2d47 100644 --- a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx.c b/ports_module/cortex_m3/iar/example_build/sample_threadx.c index a12160fa0..3b1fcf42e 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c index e9605af81..2d605570c 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c index b7d88a09f..0049b2bb6 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m3/iar/example_build/txm_module_preamble.s b/ports_module/cortex_m3/iar/example_build/txm_module_preamble.s index 5488df2ae..f0b3ec7fb 100644 --- a/ports_module/cortex_m3/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_m3/iar/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + SECTION .text:CODE AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c index 756e7032a..9d8c99d07 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c index 9a6313ca9..52283ee3f 100644 --- a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 302efdf2b..e898890d8 100644 --- a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c index b74d7a357..4e464beeb 100644 --- a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c index de0910d5a..89df209b3 100644 --- a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S index 5f6635695..5dd8e9c59 100644 --- a/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c index e9605af81..2d605570c 100644 --- a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c index 59aee1b9e..a67820ac9 100644 --- a/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m33/iar/example_build/txm_module_preamble.s b/ports_module/cortex_m33/iar/example_build/txm_module_preamble.s index 6a462980d..7f71a50f4 100644 --- a/ports_module/cortex_m33/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_m33/iar/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + SECTION .text:CODE AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE diff --git a/ports_module/cortex_m4/ac5/example_build/sample_threadx.c b/ports_module/cortex_m4/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports_module/cortex_m4/ac5/example_build/sample_threadx.c +++ b/ports_module/cortex_m4/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c index dcf73ef90..8cd5c375c 100644 --- a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c index 4edcee3cf..a8cdedd4e 100644 --- a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m4/ac5/example_build/txm_module_preamble.S b/ports_module/cortex_m4/ac5/example_build/txm_module_preamble.S index f9f25cd5e..d39c35c2f 100644 --- a/ports_module/cortex_m4/ac5/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m4/ac5/example_build/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + AREA Init, CODE, READONLY PRESERVE8 diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c index dcf73ef90..8cd5c375c 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 71914151a..0834862a7 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 4edcee3cf..a8cdedd4e 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c index b74d7a357..4e464beeb 100644 --- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c index feaaf2af1..cd8aa62b1 100644 --- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S index 5f6635695..5dd8e9c59 100644 --- a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx.c b/ports_module/cortex_m4/iar/example_build/sample_threadx.c index 55b637313..a1b9cf039 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c index e9605af81..2d605570c 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c index f925b5277..1f3b4be2b 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m4/iar/example_build/txm_module_preamble.s b/ports_module/cortex_m4/iar/example_build/txm_module_preamble.s index 6a462980d..7f71a50f4 100644 --- a/ports_module/cortex_m4/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_m4/iar/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + SECTION .text:CODE AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE diff --git a/ports_module/cortex_m7/ac5/example_build/sample_threadx.c b/ports_module/cortex_m7/ac5/example_build/sample_threadx.c index 8c61de065..6cf3e72a0 100644 --- a/ports_module/cortex_m7/ac5/example_build/sample_threadx.c +++ b/ports_module/cortex_m7/ac5/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c index dcf73ef90..8cd5c375c 100644 --- a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c index 4edcee3cf..a8cdedd4e 100644 --- a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m7/ac5/example_build/txm_module_preamble.S b/ports_module/cortex_m7/ac5/example_build/txm_module_preamble.S index f9f25cd5e..d39c35c2f 100644 --- a/ports_module/cortex_m7/ac5/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m7/ac5/example_build/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + AREA Init, CODE, READONLY PRESERVE8 diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c index dcf73ef90..8cd5c375c 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 71914151a..0834862a7 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 4edcee3cf..a8cdedd4e 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c index b74d7a357..4e464beeb 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c index feaaf2af1..cd8aa62b1 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s b/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s index ef3d93140..5efe3625c 100644 --- a/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s +++ b/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .syntax unified .section .vectors, "ax" diff --git a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S index 5f6635695..5dd8e9c59 100644 --- a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text .align 4 .syntax unified diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx.c b/ports_module/cortex_m7/iar/example_build/sample_threadx.c index f1f4cb876..4ad474a19 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c index 7e561048c..0856e8333 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c index 9fc56315d..1defe1a7b 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_m7/iar/example_build/txm_module_preamble.s b/ports_module/cortex_m7/iar/example_build/txm_module_preamble.s index 6a462980d..7f71a50f4 100644 --- a/ports_module/cortex_m7/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_m7/iar/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + SECTION .text:CODE AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c index f8e0cecc7..1f6807ea8 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c index 74eeb4547..16baffc69 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c index 80e5f04fb..25b14b16c 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Disable semihosting */ #include diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/txm_module_preamble.S index b39ba709b..a2b9aa542 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .text diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/gic.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/gic.c index 32f21bbe1..954d4fcd5 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/gic.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/gic.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /** GIC start **/ /* ------------------------- Interrupt Number Definition ------------------------ */ diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c index 78dc15386..f64815717 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Input ELF file: sample_threadx_module.axf Output C Array file: module_code.c diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 2e683da20..b5ee2222b 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/timer.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/timer.c index e964d0f6e..c71cab987 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/timer.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/timer.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "gic.h" /* Systick registers */ diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/timer.h b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/timer.h index efab1fe19..6bb3b238e 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/timer.h +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/timer.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #ifndef TIMER_H #define TIMER_H void timer_init(); diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx.c b/ports_module/cortex_r4/iar/example_build/sample_threadx.c index ca92ff864..524967678 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c index d4f98a30e..eb1d27023 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c index a0ec49eaf..493626edf 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s b/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s index 9b4f11224..f91ca94bf 100644 --- a/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + SECTION .text:CODE AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE diff --git a/ports_module/rxv2/iar/example_build/sample_threadx_module.c b/ports_module/rxv2/iar/example_build/sample_threadx_module.c index 80d89b016..b43366f82 100644 --- a/ports_module/rxv2/iar/example_build/sample_threadx_module.c +++ b/ports_module/rxv2/iar/example_build/sample_threadx_module.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel running as a module. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c b/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c index 46e3be597..441a1a0b0 100644 --- a/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Small demonstration of the ThreadX module manager. */ #include "tx_api.h" diff --git a/ports_module/rxv2/iar/example_build/txm_module_preamble.s b/ports_module/rxv2/iar/example_build/txm_module_preamble.s index 13487bc7e..54efb0dff 100644 --- a/ports_module/rxv2/iar/example_build/txm_module_preamble.s +++ b/ports_module/rxv2/iar/example_build/txm_module_preamble.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Alignment of 4 (16-byte) */ SECTION .text:CODE (4) diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c index 336ab3261..0db5b9fab 100644 --- a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s index 3ff8ae372..141c98676 100644 --- a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + .file "vectors.s" .section .ivt,text diff --git a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c index 5c1f4a163..81883601f 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c index 5c1f4a163..81883601f 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c +++ b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.c index b766cf713..4bf114568 100644 --- a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.c index b766cf713..4bf114568 100644 --- a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.c index 67acbd1ef..b0674a21c 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/stdio_ghs.c b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/stdio_ghs.c index d780bd8fa..976dde40d 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/stdio_ghs.c +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/stdio_ghs.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include /* diff --git a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/sample_threadx.c index 17cceb017..c9d1657ed 100644 --- a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c index 5c1f4a163..81883601f 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c index 5c1f4a163..81883601f 100644 --- a/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c +++ b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c index 9daf05f68..e3e2a4a25 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s index ab2f6feb5..ff1ee1c9b 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + ; ------------------------------------------------------------ ; v7-A Cache and Branch Prediction Maintenance Operations ; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c index 5c1f4a163..81883601f 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c +++ b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.c b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.c index 57b2471ed..69bbeedbc 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.c +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/v7.S b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/v7.S index e732325c2..87987e26e 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/v7.S +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/v7.S @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + ; ------------------------------------------------------------ ; v7 Cache and Branch Prediction Maintenance Operations ; ------------------------------------------------------------ diff --git a/ports_smp/linux/gnu/example_build/sample_threadx.c b/ports_smp/linux/gnu/example_build/sample_threadx.c index 0947b4280..e9bd167b3 100644 --- a/ports_smp/linux/gnu/example_build/sample_threadx.c +++ b/ports_smp/linux/gnu/example_build/sample_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX SMP kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.c b/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.c index c03bad2fa..4f2a43b2f 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.c +++ b/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/example_build/regdef.h b/ports_smp/mips32_interaptiv_smp/gnu/example_build/regdef.h index 01197f47a..9fcf4c59d 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/example_build/regdef.h +++ b/ports_smp/mips32_interaptiv_smp/gnu/example_build/regdef.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #ifndef __REGDEF_H #define __REGDEF_H diff --git a/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.c b/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.c index 8dcbcf10b..47a535d27 100644 --- a/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.c +++ b/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/ports_smp/mips32_interaptiv_smp/green/example_build/regdef.h b/ports_smp/mips32_interaptiv_smp/green/example_build/regdef.h index 01197f47a..9fcf4c59d 100644 --- a/ports_smp/mips32_interaptiv_smp/green/example_build/regdef.h +++ b/ports_smp/mips32_interaptiv_smp/green/example_build/regdef.h @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #ifndef __REGDEF_H #define __REGDEF_H diff --git a/samples/demo_threadx.c b/samples/demo_threadx.c index 13ffadbaa..b2fe3c89b 100644 --- a/samples/demo_threadx.c +++ b/samples/demo_threadx.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ diff --git a/scripts/build_smp.sh b/scripts/build_smp.sh index 615a9be8b..4c8f3b631 100755 --- a/scripts/build_smp.sh +++ b/scripts/build_smp.sh @@ -1,2 +1,13 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + $(dirname `realpath $0`)/../test/smp/cmake/run.sh build all diff --git a/scripts/build_tx.sh b/scripts/build_tx.sh index a1773a1e3..a904f909e 100755 --- a/scripts/build_tx.sh +++ b/scripts/build_tx.sh @@ -1,2 +1,13 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + $(dirname `realpath $0`)/../test/tx/cmake/run.sh build all diff --git a/scripts/build_tx_riscv.sh b/scripts/build_tx_riscv.sh index bad952dff..930bb9a31 100755 --- a/scripts/build_tx_riscv.sh +++ b/scripts/build_tx_riscv.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + # Build RISC-V regression tests for both RV32 and RV64. # Usage: build_tx_riscv.sh [all|] diff --git a/scripts/cmake_bootstrap.sh b/scripts/cmake_bootstrap.sh index b7b314fa4..d66d668de 100755 --- a/scripts/cmake_bootstrap.sh +++ b/scripts/cmake_bootstrap.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + set -e diff --git a/scripts/copy_armv7_m.sh b/scripts/copy_armv7_m.sh index 825979a20..e04ec2a7d 100755 --- a/scripts/copy_armv7_m.sh +++ b/scripts/copy_armv7_m.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + # There is only one tx_port.h file that covers three architectures: M3/M4/M7 and four tools: ac5/ac6/gnu/iar. # This file is in threadx/ports/armv7-m/inc. We are going to ignore GHS for now, but I’d like to get GHS unified as well. diff --git a/scripts/copy_armv8_m.sh b/scripts/copy_armv8_m.sh index 0963ecbe6..c66cc11ed 100755 --- a/scripts/copy_armv8_m.sh +++ b/scripts/copy_armv8_m.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + # There are two files tx_port.h and tx_secure_interface.h that cover three architectures: M33/M55/M85 and three tools: ac6/gnu/iar. # These files are in threadx/ports/armv8-m/inc. diff --git a/scripts/copy_module_armv7_m.sh b/scripts/copy_module_armv7_m.sh index a0ddcd27d..c2d190942 100755 --- a/scripts/copy_module_armv7_m.sh +++ b/scripts/copy_module_armv7_m.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + # There is only one tx_port.h file that covers three architectures: M3/M4/M7 and four tools: ac5/ac6/gnu/iar. # This file is in threadx/ports_module/armv7-m/inc. We are going to ignore GHS. diff --git a/scripts/install.sh b/scripts/install.sh index 752a03b41..bc868477e 100755 --- a/scripts/install.sh +++ b/scripts/install.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + # # Install necessary softwares for Ubuntu. diff --git a/scripts/install_riscv.sh b/scripts/install_riscv.sh index 9c2f2cdb8..41642e704 100755 --- a/scripts/install_riscv.sh +++ b/scripts/install_riscv.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + # Install RISC-V bare-metal cross-compiler toolchain and QEMU for CI. set -e diff --git a/scripts/sdl_check.sh b/scripts/sdl_check.sh index 77eeb5ce5..4bcd888a8 100755 --- a/scripts/sdl_check.sh +++ b/scripts/sdl_check.sh @@ -1,3 +1,14 @@ +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + # !/bin/bash dir_list="common common_smp common_modules ports ports_module ports_smp samples" exclude_list="-path TX" diff --git a/scripts/test_smp.sh b/scripts/test_smp.sh index 135f08478..72be13c0b 100755 --- a/scripts/test_smp.sh +++ b/scripts/test_smp.sh @@ -1,3 +1,14 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + CTEST_PARALLEL_LEVEL=4 $(dirname `realpath $0`)/../test/smp/cmake/run.sh test all diff --git a/scripts/test_tx.sh b/scripts/test_tx.sh index 613b086c8..3a2194319 100755 --- a/scripts/test_tx.sh +++ b/scripts/test_tx.sh @@ -1,3 +1,14 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + CTEST_PARALLEL_LEVEL=4 $(dirname `realpath $0`)/../test/tx/cmake/run.sh test all diff --git a/scripts/test_tx_riscv.sh b/scripts/test_tx_riscv.sh index 7d35c53fc..950afb85e 100755 --- a/scripts/test_tx_riscv.sh +++ b/scripts/test_tx_riscv.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + # Run RISC-V regression tests for both RV32 and RV64 on QEMU. # Usage: test_tx_riscv.sh [all|] diff --git a/test/smp/cmake/coverage.sh b/test/smp/cmake/coverage.sh index 51b2e8ca9..d35284f57 100755 --- a/test/smp/cmake/coverage.sh +++ b/test/smp/cmake/coverage.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + set -e diff --git a/test/smp/cmake/regression/generate_test_file.sh b/test/smp/cmake/regression/generate_test_file.sh index 0172469a4..495e363e9 100755 --- a/test/smp/cmake/regression/generate_test_file.sh +++ b/test/smp/cmake/regression/generate_test_file.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + dst=$(dirname $0)/../../regression/tx_initialize_low_level.c src=$(dirname $0)/../../../../ports_smp/linux/gnu/src/tx_initialize_low_level.c diff --git a/test/smp/cmake/samples/fake.c b/test/smp/cmake/samples/fake.c index 8159fef4a..f379e7983 100644 --- a/test/smp/cmake/samples/fake.c +++ b/test/smp/cmake/samples/fake.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" typedef unsigned int TEST_FLAG; diff --git a/test/smp/regression/testcontrol.c b/test/smp/regression/testcontrol.c index 07aa9a3f0..1c3b2ccfd 100644 --- a/test/smp/regression/testcontrol.c +++ b/test/smp/regression/testcontrol.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is the test control routine of the ThreadX kernel. All tests are dispatched from this routine. */ // Some portions generated by Codex (gpt 5.5). diff --git a/test/smp/regression/threadx_block_memory_basic_test.c b/test/smp/regression/threadx_block_memory_basic_test.c index 117872c3f..28edee3fc 100644 --- a/test/smp/regression/threadx_block_memory_basic_test.c +++ b/test/smp/regression/threadx_block_memory_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test simple memory block pool creation, deletion, and allocates and releases. */ diff --git a/test/smp/regression/threadx_block_memory_error_detection_test.c b/test/smp/regression/threadx_block_memory_error_detection_test.c index e9869b1eb..41148120f 100644 --- a/test/smp/regression/threadx_block_memory_error_detection_test.c +++ b/test/smp/regression/threadx_block_memory_error_detection_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test error detection for simple memory block operations. */ #include diff --git a/test/smp/regression/threadx_block_memory_information_test.c b/test/smp/regression/threadx_block_memory_information_test.c index 20e34d889..82d57f40a 100644 --- a/test/smp/regression/threadx_block_memory_information_test.c +++ b/test/smp/regression/threadx_block_memory_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test block memory information services. */ #include diff --git a/test/smp/regression/threadx_block_memory_prioritize_test.c b/test/smp/regression/threadx_block_memory_prioritize_test.c index 6238aef83..3b2c4f0b6 100644 --- a/test/smp/regression/threadx_block_memory_prioritize_test.c +++ b/test/smp/regression/threadx_block_memory_prioritize_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test block memory pool prioritize. */ #include diff --git a/test/smp/regression/threadx_block_memory_suspension_test.c b/test/smp/regression/threadx_block_memory_suspension_test.c index 9ce8939c5..fb68a6f9c 100644 --- a/test/smp/regression/threadx_block_memory_suspension_test.c +++ b/test/smp/regression/threadx_block_memory_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test suspension on memory block pools. */ #include diff --git a/test/smp/regression/threadx_block_memory_suspension_timeout_test.c b/test/smp/regression/threadx_block_memory_suspension_timeout_test.c index 57be8aaa3..434772853 100644 --- a/test/smp/regression/threadx_block_memory_suspension_timeout_test.c +++ b/test/smp/regression/threadx_block_memory_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test timeouts on suspension on memory block pools. */ // Some portions generated by Codex (gpt 5.4). diff --git a/test/smp/regression/threadx_block_memory_thread_terminate_test.c b/test/smp/regression/threadx_block_memory_thread_terminate_test.c index 291ab0187..89e0c787c 100644 --- a/test/smp/regression/threadx_block_memory_thread_terminate_test.c +++ b/test/smp/regression/threadx_block_memory_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread termination on a thread suspended on a block memory pool. */ diff --git a/test/smp/regression/threadx_byte_memory_basic_test.c b/test/smp/regression/threadx_byte_memory_basic_test.c index d609712c1..45a2518d5 100644 --- a/test/smp/regression/threadx_byte_memory_basic_test.c +++ b/test/smp/regression/threadx_byte_memory_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test simple memory byte pool creation, deletion, and allocates and releases. */ diff --git a/test/smp/regression/threadx_byte_memory_information_test.c b/test/smp/regression/threadx_byte_memory_information_test.c index df607acb4..f1624a65a 100644 --- a/test/smp/regression/threadx_byte_memory_information_test.c +++ b/test/smp/regression/threadx_byte_memory_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test byte memory information. */ #include diff --git a/test/smp/regression/threadx_byte_memory_prioritize_test.c b/test/smp/regression/threadx_byte_memory_prioritize_test.c index 9160db91a..db36e386f 100644 --- a/test/smp/regression/threadx_byte_memory_prioritize_test.c +++ b/test/smp/regression/threadx_byte_memory_prioritize_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test byte memory prioritize. */ #include diff --git a/test/smp/regression/threadx_byte_memory_suspension_test.c b/test/smp/regression/threadx_byte_memory_suspension_test.c index 2736195dc..3af5fc81e 100644 --- a/test/smp/regression/threadx_byte_memory_suspension_test.c +++ b/test/smp/regression/threadx_byte_memory_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test suspension on a memory byte pool. */ #include diff --git a/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c b/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c index 68f18c74d..c92f2be0f 100644 --- a/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c +++ b/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test suspension timeout on a memory byte pool. */ // Some portions generated by Codex (gpt 5.4). diff --git a/test/smp/regression/threadx_byte_memory_thread_contention_test.c b/test/smp/regression/threadx_byte_memory_thread_contention_test.c index cd379e54c..96573955a 100644 --- a/test/smp/regression/threadx_byte_memory_thread_contention_test.c +++ b/test/smp/regression/threadx_byte_memory_thread_contention_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test contention of two threads on a single memory byte pool. */ diff --git a/test/smp/regression/threadx_byte_memory_thread_terminate_test.c b/test/smp/regression/threadx_byte_memory_thread_terminate_test.c index 35a4615aa..b752f3401 100644 --- a/test/smp/regression/threadx_byte_memory_thread_terminate_test.c +++ b/test/smp/regression/threadx_byte_memory_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test termination on thread suspended on memory byte pool. */ #include diff --git a/test/smp/regression/threadx_event_flag_basic_test.c b/test/smp/regression/threadx_event_flag_basic_test.c index 3261f67fc..8ab990f7a 100644 --- a/test/smp/regression/threadx_event_flag_basic_test.c +++ b/test/smp/regression/threadx_event_flag_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test simple event flag group creation, deletion, gets and sets. */ diff --git a/test/smp/regression/threadx_event_flag_information_test.c b/test/smp/regression/threadx_event_flag_information_test.c index d24040813..45e547f9c 100644 --- a/test/smp/regression/threadx_event_flag_information_test.c +++ b/test/smp/regression/threadx_event_flag_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the event flag group information gathering services. */ #include diff --git a/test/smp/regression/threadx_event_flag_isr_set_clear_test.c b/test/smp/regression/threadx_event_flag_isr_set_clear_test.c index 54b18a2e6..1dd95dc9a 100644 --- a/test/smp/regression/threadx_event_flag_isr_set_clear_test.c +++ b/test/smp/regression/threadx_event_flag_isr_set_clear_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test for simultaneous thread event flag set AND ISR event flag set and clear. */ #include diff --git a/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c b/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c index 8706b8bc4..3c170fd4a 100644 --- a/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c +++ b/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test for wait abort from an ISR. */ #include diff --git a/test/smp/regression/threadx_event_flag_single_thread_terminate_test.c b/test/smp/regression/threadx_event_flag_single_thread_terminate_test.c index 866758902..6ae7c7126 100644 --- a/test/smp/regression/threadx_event_flag_single_thread_terminate_test.c +++ b/test/smp/regression/threadx_event_flag_single_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension with a single suspended thread being terminated at the same priority level. */ diff --git a/test/smp/regression/threadx_event_flag_suspension_consume_test.c b/test/smp/regression/threadx_event_flag_suspension_consume_test.c index aae8f1b9c..eaa40258b 100644 --- a/test/smp/regression/threadx_event_flag_suspension_consume_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_consume_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension and resumption of two threads waiting on the same event flag set with the consumption. */ diff --git a/test/smp/regression/threadx_event_flag_suspension_different_bits_consume_test.c b/test/smp/regression/threadx_event_flag_suspension_different_bits_consume_test.c index 595e60edb..5f4c9494b 100644 --- a/test/smp/regression/threadx_event_flag_suspension_different_bits_consume_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_different_bits_consume_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension and resumption of two threads waiting on different event flags with consumption. */ diff --git a/test/smp/regression/threadx_event_flag_suspension_different_bits_test.c b/test/smp/regression/threadx_event_flag_suspension_different_bits_test.c index f9e43cadb..56f9c263d 100644 --- a/test/smp/regression/threadx_event_flag_suspension_different_bits_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_different_bits_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension and resumption of two threads waiting on different event flags. */ diff --git a/test/smp/regression/threadx_event_flag_suspension_test.c b/test/smp/regression/threadx_event_flag_suspension_test.c index 915e33dbc..1c98ab49f 100644 --- a/test/smp/regression/threadx_event_flag_suspension_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension and resumption of three threads waiting on the same event flag set. */ diff --git a/test/smp/regression/threadx_event_flag_suspension_timeout_test.c b/test/smp/regression/threadx_event_flag_suspension_timeout_test.c index 2772d3914..730d5187d 100644 --- a/test/smp/regression/threadx_event_flag_suspension_timeout_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension timeout processing. */ #include diff --git a/test/smp/regression/threadx_event_flag_thread_terminate_test.c b/test/smp/regression/threadx_event_flag_thread_terminate_test.c index 166711f52..25536903b 100644 --- a/test/smp/regression/threadx_event_flag_thread_terminate_test.c +++ b/test/smp/regression/threadx_event_flag_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension with the suspended threads being terminated. */ diff --git a/test/smp/regression/threadx_initialize_kernel_setup_test.c b/test/smp/regression/threadx_initialize_kernel_setup_test.c index 8c2b11596..388f2cdec 100644 --- a/test/smp/regression/threadx_initialize_kernel_setup_test.c +++ b/test/smp/regression/threadx_initialize_kernel_setup_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test kernel setup functionality in ThreadX. */ #include diff --git a/test/smp/regression/threadx_interrupt_control_test.c b/test/smp/regression/threadx_interrupt_control_test.c index c573c0985..ec797ac8a 100644 --- a/test/smp/regression/threadx_interrupt_control_test.c +++ b/test/smp/regression/threadx_interrupt_control_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the interrupt control service call avaialbe to the application. */ diff --git a/test/smp/regression/threadx_mutex_basic_test.c b/test/smp/regression/threadx_mutex_basic_test.c index 419813d32..bb81eb9a3 100644 --- a/test/smp/regression/threadx_mutex_basic_test.c +++ b/test/smp/regression/threadx_mutex_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex create/delete and immediate return gets and puts. */ diff --git a/test/smp/regression/threadx_mutex_delete_test.c b/test/smp/regression/threadx_mutex_delete_test.c index af5014883..c706cc667 100644 --- a/test/smp/regression/threadx_mutex_delete_test.c +++ b/test/smp/regression/threadx_mutex_delete_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and mutex delete with suspended threads. */ diff --git a/test/smp/regression/threadx_mutex_information_test.c b/test/smp/regression/threadx_mutex_information_test.c index 74f4714bf..3829122ce 100644 --- a/test/smp/regression/threadx_mutex_information_test.c +++ b/test/smp/regression/threadx_mutex_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex information services. */ #include diff --git a/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c b/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c index e9b60bf5e..929ea0b97 100644 --- a/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c +++ b/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test multiple mutex priority inheritance situations. */ #include diff --git a/test/smp/regression/threadx_mutex_no_preemption_test.c b/test/smp/regression/threadx_mutex_no_preemption_test.c index 3cc21b62e..2798a5d35 100644 --- a/test/smp/regression/threadx_mutex_no_preemption_test.c +++ b/test/smp/regression/threadx_mutex_no_preemption_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and another thread resuming the same priority thread by doing a mutex put. */ diff --git a/test/smp/regression/threadx_mutex_preemption_test.c b/test/smp/regression/threadx_mutex_preemption_test.c index 495ae13c4..5e3d4c4bd 100644 --- a/test/smp/regression/threadx_mutex_preemption_test.c +++ b/test/smp/regression/threadx_mutex_preemption_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and another thread resuming the higher priority thread by doing a mutex put. Higher-priority thread should preempt. */ diff --git a/test/smp/regression/threadx_mutex_priority_inheritance_test.c b/test/smp/regression/threadx_mutex_priority_inheritance_test.c index 87cc334c3..078acb76f 100644 --- a/test/smp/regression/threadx_mutex_priority_inheritance_test.c +++ b/test/smp/regression/threadx_mutex_priority_inheritance_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and priority inheritance with another thread resuming the higher priority thread by doing a mutex put. Higher-priority thread should preempt. */ diff --git a/test/smp/regression/threadx_mutex_proritize_test.c b/test/smp/regression/threadx_mutex_proritize_test.c index bbc2845b1..899882732 100644 --- a/test/smp/regression/threadx_mutex_proritize_test.c +++ b/test/smp/regression/threadx_mutex_proritize_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension prioritization. */ #include diff --git a/test/smp/regression/threadx_mutex_suspension_timeout_test.c b/test/smp/regression/threadx_mutex_suspension_timeout_test.c index 7460d367c..46896762a 100644 --- a/test/smp/regression/threadx_mutex_suspension_timeout_test.c +++ b/test/smp/regression/threadx_mutex_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and timeout functionality. */ #include diff --git a/test/smp/regression/threadx_mutex_thread_terminate_test.c b/test/smp/regression/threadx_mutex_thread_terminate_test.c index ef21b92df..f41445244 100644 --- a/test/smp/regression/threadx_mutex_thread_terminate_test.c +++ b/test/smp/regression/threadx_mutex_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread terminate calls when threads are suspended on a mutex. */ diff --git a/test/smp/regression/threadx_queue_basic_eight_word_test.c b/test/smp/regression/threadx_queue_basic_eight_word_test.c index fb4640cc4..d3271f2c5 100644 --- a/test/smp/regression/threadx_queue_basic_eight_word_test.c +++ b/test/smp/regression/threadx_queue_basic_eight_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 8 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/smp/regression/threadx_queue_basic_four_word_test.c b/test/smp/regression/threadx_queue_basic_four_word_test.c index 4c54d8bd2..49eb9a85a 100644 --- a/test/smp/regression/threadx_queue_basic_four_word_test.c +++ b/test/smp/regression/threadx_queue_basic_four_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 4 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/smp/regression/threadx_queue_basic_max_message_size_test.c b/test/smp/regression/threadx_queue_basic_max_message_size_test.c index d62e80ff7..0ad2be4e2 100644 --- a/test/smp/regression/threadx_queue_basic_max_message_size_test.c +++ b/test/smp/regression/threadx_queue_basic_max_message_size_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/smp/regression/threadx_queue_basic_one_word_test.c b/test/smp/regression/threadx_queue_basic_one_word_test.c index 0e2f1fbc4..1abb69861 100644 --- a/test/smp/regression/threadx_queue_basic_one_word_test.c +++ b/test/smp/regression/threadx_queue_basic_one_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 1 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/smp/regression/threadx_queue_basic_sixteen_word_test.c b/test/smp/regression/threadx_queue_basic_sixteen_word_test.c index de3ede98b..42205d90d 100644 --- a/test/smp/regression/threadx_queue_basic_sixteen_word_test.c +++ b/test/smp/regression/threadx_queue_basic_sixteen_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/smp/regression/threadx_queue_basic_two_word_test.c b/test/smp/regression/threadx_queue_basic_two_word_test.c index 46d85a6df..fa2a2fedd 100644 --- a/test/smp/regression/threadx_queue_basic_two_word_test.c +++ b/test/smp/regression/threadx_queue_basic_two_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 2 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/smp/regression/threadx_queue_empty_suspension_test.c b/test/smp/regression/threadx_queue_empty_suspension_test.c index c63b17153..c0858ac8d 100644 --- a/test/smp/regression/threadx_queue_empty_suspension_test.c +++ b/test/smp/regression/threadx_queue_empty_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test empty queue suspension of queue that supports 3 messages that are each 2 ULONG in size. */ diff --git a/test/smp/regression/threadx_queue_flush_no_suspension_test.c b/test/smp/regression/threadx_queue_flush_no_suspension_test.c index 95bd5fedf..5da58b74e 100644 --- a/test/smp/regression/threadx_queue_flush_no_suspension_test.c +++ b/test/smp/regression/threadx_queue_flush_no_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the queue flush operation on a queue that has no threads suspended on it. */ diff --git a/test/smp/regression/threadx_queue_flush_test.c b/test/smp/regression/threadx_queue_flush_test.c index 77f8d2d5d..a28e2288f 100644 --- a/test/smp/regression/threadx_queue_flush_test.c +++ b/test/smp/regression/threadx_queue_flush_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the queue flush operation on a queue that has two threads suspended on it. */ diff --git a/test/smp/regression/threadx_queue_front_send_test.c b/test/smp/regression/threadx_queue_front_send_test.c index d03e7ac2f..45b5dd65c 100644 --- a/test/smp/regression/threadx_queue_front_send_test.c +++ b/test/smp/regression/threadx_queue_front_send_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including queue front send. This test is for queue sizes of 2 ULONG. */ diff --git a/test/smp/regression/threadx_queue_full_suspension_test.c b/test/smp/regression/threadx_queue_full_suspension_test.c index 687ef04a4..d1e1759f6 100644 --- a/test/smp/regression/threadx_queue_full_suspension_test.c +++ b/test/smp/regression/threadx_queue_full_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test queue full suspension of queue that supports 3 messages that are each 2 ULONG in size. */ diff --git a/test/smp/regression/threadx_queue_information_test.c b/test/smp/regression/threadx_queue_information_test.c index 5fcdbb8f4..f884bd0d6 100644 --- a/test/smp/regression/threadx_queue_information_test.c +++ b/test/smp/regression/threadx_queue_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the queue information services. */ #include diff --git a/test/smp/regression/threadx_queue_prioritize.c b/test/smp/regression/threadx_queue_prioritize.c index 53c192756..f904a5255 100644 --- a/test/smp/regression/threadx_queue_prioritize.c +++ b/test/smp/regression/threadx_queue_prioritize.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test queue prioritize. */ #include diff --git a/test/smp/regression/threadx_queue_suspension_timeout_test.c b/test/smp/regression/threadx_queue_suspension_timeout_test.c index 92dca991f..aa05c0dcd 100644 --- a/test/smp/regression/threadx_queue_suspension_timeout_test.c +++ b/test/smp/regression/threadx_queue_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test queue full and empty suspension with timeouts on queues that supports 3 messages that are each 2 ULONG in size. */ diff --git a/test/smp/regression/threadx_queue_thread_terminate_test.c b/test/smp/regression/threadx_queue_thread_terminate_test.c index 97d8a569d..42673c8d2 100644 --- a/test/smp/regression/threadx_queue_thread_terminate_test.c +++ b/test/smp/regression/threadx_queue_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread terminate when the terminated thread is suspeded on a queue. */ diff --git a/test/smp/regression/threadx_semaphore_basic_test.c b/test/smp/regression/threadx_semaphore_basic_test.c index 33ee32574..3209b5865 100644 --- a/test/smp/regression/threadx_semaphore_basic_test.c +++ b/test/smp/regression/threadx_semaphore_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore create/delete and immediate return gets and puts. */ #include diff --git a/test/smp/regression/threadx_semaphore_ceiling_put_test.c b/test/smp/regression/threadx_semaphore_ceiling_put_test.c index 7d4f58329..f7d7be73e 100644 --- a/test/smp/regression/threadx_semaphore_ceiling_put_test.c +++ b/test/smp/regression/threadx_semaphore_ceiling_put_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore ceiling put. */ #include diff --git a/test/smp/regression/threadx_semaphore_delete_test.c b/test/smp/regression/threadx_semaphore_delete_test.c index 2c9bc1aa4..272a0252c 100644 --- a/test/smp/regression/threadx_semaphore_delete_test.c +++ b/test/smp/regression/threadx_semaphore_delete_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore suspension and semaphore delete with suspended threads. */ diff --git a/test/smp/regression/threadx_semaphore_information_test.c b/test/smp/regression/threadx_semaphore_information_test.c index d2e9bd571..ede276e97 100644 --- a/test/smp/regression/threadx_semaphore_information_test.c +++ b/test/smp/regression/threadx_semaphore_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore information services. */ #include diff --git a/test/smp/regression/threadx_semaphore_non_preemption_test.c b/test/smp/regression/threadx_semaphore_non_preemption_test.c index c075b16cb..e3695e847 100644 --- a/test/smp/regression/threadx_semaphore_non_preemption_test.c +++ b/test/smp/regression/threadx_semaphore_non_preemption_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore suspension and another thread resuming the same priority thread by doing a semaphore put. */ diff --git a/test/smp/regression/threadx_semaphore_preemption_test.c b/test/smp/regression/threadx_semaphore_preemption_test.c index f14193a2a..33677c01b 100644 --- a/test/smp/regression/threadx_semaphore_preemption_test.c +++ b/test/smp/regression/threadx_semaphore_preemption_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore suspension and another thread resuming the higher priority thread by doing a semaphore put. Higher-priority thread should preempt. */ diff --git a/test/smp/regression/threadx_semaphore_prioritize.c b/test/smp/regression/threadx_semaphore_prioritize.c index 6bee46565..30d045900 100644 --- a/test/smp/regression/threadx_semaphore_prioritize.c +++ b/test/smp/regression/threadx_semaphore_prioritize.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test semaphore prioritize. */ #include diff --git a/test/smp/regression/threadx_semaphore_thread_terminate_test.c b/test/smp/regression/threadx_semaphore_thread_terminate_test.c index a15f5963e..7055ed077 100644 --- a/test/smp/regression/threadx_semaphore_thread_terminate_test.c +++ b/test/smp/regression/threadx_semaphore_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread terminate calls when threads are suspended on a semaphore. */ diff --git a/test/smp/regression/threadx_semaphore_timeout_test.c b/test/smp/regression/threadx_semaphore_timeout_test.c index 660891c96..3d41f5b24 100644 --- a/test/smp/regression/threadx_semaphore_timeout_test.c +++ b/test/smp/regression/threadx_semaphore_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore suspension and timeout functionality. */ #include diff --git a/test/smp/regression/threadx_smp_multiple_threads_one_core_test.c b/test/smp/regression/threadx_smp_multiple_threads_one_core_test.c index 533837bb7..8dc05dd06 100644 --- a/test/smp/regression/threadx_smp_multiple_threads_one_core_test.c +++ b/test/smp/regression/threadx_smp_multiple_threads_one_core_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP multiple threads excluded to one core test. */ #include diff --git a/test/smp/regression/threadx_smp_non_trivial_scheduling_test.c b/test/smp/regression/threadx_smp_non_trivial_scheduling_test.c index 4a0feec22..81598196b 100644 --- a/test/smp/regression/threadx_smp_non_trivial_scheduling_test.c +++ b/test/smp/regression/threadx_smp_non_trivial_scheduling_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP non-trivial scheduling test. */ #include diff --git a/test/smp/regression/threadx_smp_one_thread_dynamic_exclusion_test.c b/test/smp/regression/threadx_smp_one_thread_dynamic_exclusion_test.c index 34a6f9e46..b929c1ea6 100644 --- a/test/smp/regression/threadx_smp_one_thread_dynamic_exclusion_test.c +++ b/test/smp/regression/threadx_smp_one_thread_dynamic_exclusion_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP one thread dynamic thread exclusion test. */ #include diff --git a/test/smp/regression/threadx_smp_preemption_threshold_test.c b/test/smp/regression/threadx_smp_preemption_threshold_test.c index 50a696a43..47935034d 100644 --- a/test/smp/regression/threadx_smp_preemption_threshold_test.c +++ b/test/smp/regression/threadx_smp_preemption_threshold_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP preemption-threshold test. */ #include diff --git a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c index ce2315f8a..a9ea93ad1 100644 --- a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c +++ b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP random resume/suspend/exclude/pt test. */ // Some portions generated by Codex (gpt 5.4). diff --git a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c index 379e1fdfe..36c003378 100644 --- a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c +++ b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP random resume/suspend/exclude test. */ #include diff --git a/test/smp/regression/threadx_smp_random_resume_suspend_test.c b/test/smp/regression/threadx_smp_random_resume_suspend_test.c index 8550bdf24..c4704da44 100644 --- a/test/smp/regression/threadx_smp_random_resume_suspend_test.c +++ b/test/smp/regression/threadx_smp_random_resume_suspend_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP random resume/suspend test. */ #include diff --git a/test/smp/regression/threadx_smp_rebalance_exclusion_test.c b/test/smp/regression/threadx_smp_rebalance_exclusion_test.c index 9fe04bcf4..050605da0 100644 --- a/test/smp/regression/threadx_smp_rebalance_exclusion_test.c +++ b/test/smp/regression/threadx_smp_rebalance_exclusion_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP rebalance exclusion test. */ #include diff --git a/test/smp/regression/threadx_smp_relinquish_test.c b/test/smp/regression/threadx_smp_relinquish_test.c index 96b2864d6..250cc863a 100644 --- a/test/smp/regression/threadx_smp_relinquish_test.c +++ b/test/smp/regression/threadx_smp_relinquish_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP relinquish test. */ #include diff --git a/test/smp/regression/threadx_smp_resume_suspend_ascending_order_test.c b/test/smp/regression/threadx_smp_resume_suspend_ascending_order_test.c index 22140ab56..91a66bfeb 100644 --- a/test/smp/regression/threadx_smp_resume_suspend_ascending_order_test.c +++ b/test/smp/regression/threadx_smp_resume_suspend_ascending_order_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP resume and suspend threads in ascending order test. */ #include diff --git a/test/smp/regression/threadx_smp_resume_suspend_descending_order_test.c b/test/smp/regression/threadx_smp_resume_suspend_descending_order_test.c index a269796f6..e4d202a53 100644 --- a/test/smp/regression/threadx_smp_resume_suspend_descending_order_test.c +++ b/test/smp/regression/threadx_smp_resume_suspend_descending_order_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP resume and suspend threads in ascending order test. */ #include diff --git a/test/smp/regression/threadx_smp_time_slice_test.c b/test/smp/regression/threadx_smp_time_slice_test.c index b6cd67eae..370f5e371 100644 --- a/test/smp/regression/threadx_smp_time_slice_test.c +++ b/test/smp/regression/threadx_smp_time_slice_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP time-slice test. */ // Some portions generated by Codex (gpt 5.4). diff --git a/test/smp/regression/threadx_smp_two_threads_one_core_test.c b/test/smp/regression/threadx_smp_two_threads_one_core_test.c index 66ed9478a..fe6df9563 100644 --- a/test/smp/regression/threadx_smp_two_threads_one_core_test.c +++ b/test/smp/regression/threadx_smp_two_threads_one_core_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Define the ThreadX SMP two threads excluded to one core test. */ #include diff --git a/test/smp/regression/threadx_thread_basic_execution_test.c b/test/smp/regression/threadx_thread_basic_execution_test.c index 42ded1842..d90d07696 100644 --- a/test/smp/regression/threadx_thread_basic_execution_test.c +++ b/test/smp/regression/threadx_thread_basic_execution_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if one thread can be created and executed. It thread_0_entry is hit, then the thread was successfully scheduled. On success, thread_0_counter gets incremented. */ diff --git a/test/smp/regression/threadx_thread_basic_time_slice_test.c b/test/smp/regression/threadx_thread_basic_time_slice_test.c index bb848b116..ed7a1fba0 100644 --- a/test/smp/regression/threadx_thread_basic_time_slice_test.c +++ b/test/smp/regression/threadx_thread_basic_time_slice_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if a thread can be created with a time-slice. No time-slice occurs, only the processing to check for time-slicing. */ diff --git a/test/smp/regression/threadx_thread_completed_test.c b/test/smp/regression/threadx_thread_completed_test.c index adaf16836..e8b609e32 100644 --- a/test/smp/regression/threadx_thread_completed_test.c +++ b/test/smp/regression/threadx_thread_completed_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if one thread can be created, executed, and return to the thread shell function. The thread shell function places the thread in a finished state. */ diff --git a/test/smp/regression/threadx_thread_create_preemption_threshold_test.c b/test/smp/regression/threadx_thread_create_preemption_threshold_test.c index 58ce79fe7..b53179cbb 100644 --- a/test/smp/regression/threadx_thread_create_preemption_threshold_test.c +++ b/test/smp/regression/threadx_thread_create_preemption_threshold_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test for preemption-threshold use during thread creation during initialization. */ #include diff --git a/test/smp/regression/threadx_thread_delayed_suspension_test.c b/test/smp/regression/threadx_thread_delayed_suspension_test.c index 72c872ddd..fe0a82f89 100644 --- a/test/smp/regression/threadx_thread_delayed_suspension_test.c +++ b/test/smp/regression/threadx_thread_delayed_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test checks out the delayed suspension clear from tx_thread_resume. */ #include diff --git a/test/smp/regression/threadx_thread_information_test.c b/test/smp/regression/threadx_thread_information_test.c index 191077424..b5d06e71e 100644 --- a/test/smp/regression/threadx_thread_information_test.c +++ b/test/smp/regression/threadx_thread_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is for the thread information services. */ #include diff --git a/test/smp/regression/threadx_thread_multi_level_preemption_threshold_test.c b/test/smp/regression/threadx_thread_multi_level_preemption_threshold_test.c index 1e18820bf..1eb8f6850 100644 --- a/test/smp/regression/threadx_thread_multi_level_preemption_threshold_test.c +++ b/test/smp/regression/threadx_thread_multi_level_preemption_threshold_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test multi-level preemption threshold. The protection placed by a thread must be preserved after higher-priority thread preemption that is above the threshold. */ diff --git a/test/smp/regression/threadx_thread_multiple_non_current_test.c b/test/smp/regression/threadx_thread_multiple_non_current_test.c index 50ed17a0a..a0acc1b99 100644 --- a/test/smp/regression/threadx_thread_multiple_non_current_test.c +++ b/test/smp/regression/threadx_thread_multiple_non_current_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if multiple non-current threads can be suspended. The order the suspension and resumption occurs makes sure everything is working right. Thread execution should remain predictable even after suspension and diff --git a/test/smp/regression/threadx_thread_multiple_sleep_test.c b/test/smp/regression/threadx_thread_multiple_sleep_test.c index 76443afa3..4dfe5bdcc 100644 --- a/test/smp/regression/threadx_thread_multiple_sleep_test.c +++ b/test/smp/regression/threadx_thread_multiple_sleep_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test multiple threads sleeping for 33 ticks. */ // Some portions generated by Codex (gpt 5.4). diff --git a/test/smp/regression/threadx_thread_multiple_suspension_test.c b/test/smp/regression/threadx_thread_multiple_suspension_test.c index 01c42e8fa..d6577b534 100644 --- a/test/smp/regression/threadx_thread_multiple_suspension_test.c +++ b/test/smp/regression/threadx_thread_multiple_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if multiple threads can be created and suspend. The order the suspension and resumption occurs makes sure everything is working right. All the counters should increment at the same rate. */ diff --git a/test/smp/regression/threadx_thread_multiple_time_slice_test.c b/test/smp/regression/threadx_thread_multiple_time_slice_test.c index f3e9fbf00..af3d80196 100644 --- a/test/smp/regression/threadx_thread_multiple_time_slice_test.c +++ b/test/smp/regression/threadx_thread_multiple_time_slice_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if two threads can be created and execute with a time-slice. Thread 7 should run twice as long because it has more of a time-slice. */ diff --git a/test/smp/regression/threadx_thread_preemptable_suspension_test.c b/test/smp/regression/threadx_thread_preemptable_suspension_test.c index 8e4dbdd6b..acd426c60 100644 --- a/test/smp/regression/threadx_thread_preemptable_suspension_test.c +++ b/test/smp/regression/threadx_thread_preemptable_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if multiple threads can be created and suspended. The order the suspension and resumption occurs makes sure everything is working right. All the counters should increment at the same rate. This test differs from test 4 in diff --git a/test/smp/regression/threadx_thread_preemption_change_test.c b/test/smp/regression/threadx_thread_preemption_change_test.c index 5f9726c0c..808344cfb 100644 --- a/test/smp/regression/threadx_thread_preemption_change_test.c +++ b/test/smp/regression/threadx_thread_preemption_change_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the change preemption service call. */ #include diff --git a/test/smp/regression/threadx_thread_priority_change.c b/test/smp/regression/threadx_thread_priority_change.c index 638635449..e68eadf51 100644 --- a/test/smp/regression/threadx_thread_priority_change.c +++ b/test/smp/regression/threadx_thread_priority_change.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the change priority service call. */ #include diff --git a/test/smp/regression/threadx_thread_relinquish_test.c b/test/smp/regression/threadx_thread_relinquish_test.c index 7c7efbd18..b87d6a0b2 100644 --- a/test/smp/regression/threadx_thread_relinquish_test.c +++ b/test/smp/regression/threadx_thread_relinquish_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if multiple threads can be created and relinquish control between them. */ #include diff --git a/test/smp/regression/threadx_thread_reset_test.c b/test/smp/regression/threadx_thread_reset_test.c index a709d163c..56006be13 100644 --- a/test/smp/regression/threadx_thread_reset_test.c +++ b/test/smp/regression/threadx_thread_reset_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the tx_thread_reset function. */ #include diff --git a/test/smp/regression/threadx_thread_simple_sleep_non_clear_test.c b/test/smp/regression/threadx_thread_simple_sleep_non_clear_test.c index 67a2cf000..502fc71e2 100644 --- a/test/smp/regression/threadx_thread_simple_sleep_non_clear_test.c +++ b/test/smp/regression/threadx_thread_simple_sleep_non_clear_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple sleep for 18 ticks, with something in the remaining field of the thread control block. */ diff --git a/test/smp/regression/threadx_thread_simple_sleep_test.c b/test/smp/regression/threadx_thread_simple_sleep_test.c index 5b8b12b31..583e8e122 100644 --- a/test/smp/regression/threadx_thread_simple_sleep_test.c +++ b/test/smp/regression/threadx_thread_simple_sleep_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple sleep for 18 ticks. */ #include diff --git a/test/smp/regression/threadx_thread_simple_suspend_test.c b/test/smp/regression/threadx_thread_simple_suspend_test.c index 2e21d0568..5089fd64f 100644 --- a/test/smp/regression/threadx_thread_simple_suspend_test.c +++ b/test/smp/regression/threadx_thread_simple_suspend_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if a thread can successfully suspend itself in a single thread system. This also tests a thread created that is not automatically enabled. */ diff --git a/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c b/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c index addb28757..65a0bd5fe 100644 --- a/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c +++ b/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple sleep for 100 ticks. */ #include diff --git a/test/smp/regression/threadx_thread_sleep_terminate_test.c b/test/smp/regression/threadx_thread_sleep_terminate_test.c index 98862051d..374f5d431 100644 --- a/test/smp/regression/threadx_thread_sleep_terminate_test.c +++ b/test/smp/regression/threadx_thread_sleep_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread termination of a thread in a sleep condition. */ #include diff --git a/test/smp/regression/threadx_thread_stack_checking_test.c b/test/smp/regression/threadx_thread_stack_checking_test.c index 940b6c6b5..9db10d0aa 100644 --- a/test/smp/regression/threadx_thread_stack_checking_test.c +++ b/test/smp/regression/threadx_thread_stack_checking_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is for the thread stack checking services. */ #include diff --git a/test/smp/regression/threadx_thread_terminate_delete_test.c b/test/smp/regression/threadx_thread_terminate_delete_test.c index 15e25e7d3..2ca2de858 100644 --- a/test/smp/regression/threadx_thread_terminate_delete_test.c +++ b/test/smp/regression/threadx_thread_terminate_delete_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread terminate (self, and other), thread delete, and thread identify services. */ diff --git a/test/smp/regression/threadx_thread_time_slice_change_test.c b/test/smp/regression/threadx_thread_time_slice_change_test.c index 0122fc2ad..ab35bd197 100644 --- a/test/smp/regression/threadx_thread_time_slice_change_test.c +++ b/test/smp/regression/threadx_thread_time_slice_change_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the change time-slice service call. */ #include diff --git a/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c b/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c index d5241cc3b..75faf050f 100644 --- a/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c +++ b/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test for simultaneous thread suspension lifting AND thread wait abort calls. */ #include diff --git a/test/smp/regression/threadx_thread_wait_abort_test.c b/test/smp/regression/threadx_thread_wait_abort_test.c index 49852ec1d..0c3f21f2a 100644 --- a/test/smp/regression/threadx_thread_wait_abort_test.c +++ b/test/smp/regression/threadx_thread_wait_abort_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread wait abort. */ #include diff --git a/test/smp/regression/threadx_time_get_set_test.c b/test/smp/regression/threadx_time_get_set_test.c index 8279cbd57..e166c3139 100644 --- a/test/smp/regression/threadx_time_get_set_test.c +++ b/test/smp/regression/threadx_time_get_set_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test simple tx_time_get and set services. */ #include diff --git a/test/smp/regression/threadx_timer_activate_deactivate_test.c b/test/smp/regression/threadx_timer_activate_deactivate_test.c index 69f9b38fc..ceaf79bf7 100644 --- a/test/smp/regression/threadx_timer_activate_deactivate_test.c +++ b/test/smp/regression/threadx_timer_activate_deactivate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test application timer activation/deactivation services from threads and the activation routines. */ diff --git a/test/smp/regression/threadx_timer_deactivate_accuracy_test.c b/test/smp/regression/threadx_timer_deactivate_accuracy_test.c index 625b82a65..0da41a7a0 100644 --- a/test/smp/regression/threadx_timer_deactivate_accuracy_test.c +++ b/test/smp/regression/threadx_timer_deactivate_accuracy_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test application timer activation/deactivation services from threads... Make sure the remaining ticks are being saved/restored properly. */ diff --git a/test/smp/regression/threadx_timer_information_test.c b/test/smp/regression/threadx_timer_information_test.c index 7954de2cd..ae3bb4141 100644 --- a/test/smp/regression/threadx_timer_information_test.c +++ b/test/smp/regression/threadx_timer_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test timer information services. */ #include diff --git a/test/smp/regression/threadx_timer_large_timer_accuracy_test.c b/test/smp/regression/threadx_timer_large_timer_accuracy_test.c index 726523b9e..f44d4f059 100644 --- a/test/smp/regression/threadx_timer_large_timer_accuracy_test.c +++ b/test/smp/regression/threadx_timer_large_timer_accuracy_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test application timer activation/deactivation services from threads... To make sure large timer expirations are being saved/restored properly. */ diff --git a/test/smp/regression/threadx_timer_multiple_accuracy_test.c b/test/smp/regression/threadx_timer_multiple_accuracy_test.c index 206f28025..a4cceefa1 100644 --- a/test/smp/regression/threadx_timer_multiple_accuracy_test.c +++ b/test/smp/regression/threadx_timer_multiple_accuracy_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the accuracy of three free running timers. */ #include diff --git a/test/smp/regression/threadx_timer_multiple_test.c b/test/smp/regression/threadx_timer_multiple_test.c index 688a7d5ba..a0f215dce 100644 --- a/test/smp/regression/threadx_timer_multiple_test.c +++ b/test/smp/regression/threadx_timer_multiple_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple application timer services, including create, activate, deactivate, change, and delete with multiple timers. */ diff --git a/test/smp/regression/threadx_timer_simple_test.c b/test/smp/regression/threadx_timer_simple_test.c index b7c3f7c75..e2272bd2e 100644 --- a/test/smp/regression/threadx_timer_simple_test.c +++ b/test/smp/regression/threadx_timer_simple_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple application timer services, including create, activate, deactivate, change, and delete. */ diff --git a/test/smp/regression/threadx_trace_basic_test.c b/test/smp/regression/threadx_trace_basic_test.c index 2f3227f82..51fa6256c 100644 --- a/test/smp/regression/threadx_trace_basic_test.c +++ b/test/smp/regression/threadx_trace_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test trace functionality in ThreadX. */ #include diff --git a/test/tx/cmake/coverage.sh b/test/tx/cmake/coverage.sh index ae2c7a4b6..6dda78b38 100755 --- a/test/tx/cmake/coverage.sh +++ b/test/tx/cmake/coverage.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + set -e diff --git a/test/tx/cmake/regression/generate_test_file.sh b/test/tx/cmake/regression/generate_test_file.sh index ac0a70fa1..67482c42e 100755 --- a/test/tx/cmake/regression/generate_test_file.sh +++ b/test/tx/cmake/regression/generate_test_file.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + dst=$(dirname $0)/../../regression/tx_initialize_low_level.c src=$(dirname $0)/../../../../ports/linux/gnu/src/tx_initialize_low_level.c diff --git a/test/tx/cmake/riscv/run.sh b/test/tx/cmake/riscv/run.sh index 890efa452..3b0905e74 100755 --- a/test/tx/cmake/riscv/run.sh +++ b/test/tx/cmake/riscv/run.sh @@ -1,4 +1,15 @@ #!/bin/bash +############################################################################## +# Copyright (c) 2024 Microsoft Corporation +# Copyright (c) 2026 Eclipse ThreadX contributors +# +# This program and the accompanying materials are made available under the +# terms of the MIT License which is available at +# https://opensource.org/licenses/MIT. +# +# SPDX-License-Identifier: MIT +############################################################################## + set -e diff --git a/test/tx/cmake/samples/fake.c b/test/tx/cmake/samples/fake.c index 199f257ee..138117b5b 100644 --- a/test/tx/cmake/samples/fake.c +++ b/test/tx/cmake/samples/fake.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" typedef unsigned int TEST_FLAG; diff --git a/test/tx/regression/testcontrol.c b/test/tx/regression/testcontrol.c index 68f1158ee..e2b3f7253 100644 --- a/test/tx/regression/testcontrol.c +++ b/test/tx/regression/testcontrol.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is the test control routine of the ThreadX kernel. All tests are dispatched from this routine. */ // Some portions generated by Codex (gpt 5.4). diff --git a/test/tx/regression/threadx_block_memory_basic_test.c b/test/tx/regression/threadx_block_memory_basic_test.c index c49effe7a..94cc87935 100644 --- a/test/tx/regression/threadx_block_memory_basic_test.c +++ b/test/tx/regression/threadx_block_memory_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test simple memory block pool creation, deletion, and allocates and releases. */ diff --git a/test/tx/regression/threadx_block_memory_error_detection_test.c b/test/tx/regression/threadx_block_memory_error_detection_test.c index e9869b1eb..41148120f 100644 --- a/test/tx/regression/threadx_block_memory_error_detection_test.c +++ b/test/tx/regression/threadx_block_memory_error_detection_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test error detection for simple memory block operations. */ #include diff --git a/test/tx/regression/threadx_block_memory_information_test.c b/test/tx/regression/threadx_block_memory_information_test.c index 20e34d889..82d57f40a 100644 --- a/test/tx/regression/threadx_block_memory_information_test.c +++ b/test/tx/regression/threadx_block_memory_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test block memory information services. */ #include diff --git a/test/tx/regression/threadx_block_memory_prioritize_test.c b/test/tx/regression/threadx_block_memory_prioritize_test.c index 6238aef83..3b2c4f0b6 100644 --- a/test/tx/regression/threadx_block_memory_prioritize_test.c +++ b/test/tx/regression/threadx_block_memory_prioritize_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test block memory pool prioritize. */ #include diff --git a/test/tx/regression/threadx_block_memory_suspension_test.c b/test/tx/regression/threadx_block_memory_suspension_test.c index 9ce8939c5..fb68a6f9c 100644 --- a/test/tx/regression/threadx_block_memory_suspension_test.c +++ b/test/tx/regression/threadx_block_memory_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test suspension on memory block pools. */ #include diff --git a/test/tx/regression/threadx_block_memory_suspension_timeout_test.c b/test/tx/regression/threadx_block_memory_suspension_timeout_test.c index d3f8d4935..257dd122d 100644 --- a/test/tx/regression/threadx_block_memory_suspension_timeout_test.c +++ b/test/tx/regression/threadx_block_memory_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test timeouts on suspension on memory block pools. */ #include diff --git a/test/tx/regression/threadx_block_memory_thread_terminate_test.c b/test/tx/regression/threadx_block_memory_thread_terminate_test.c index 291ab0187..89e0c787c 100644 --- a/test/tx/regression/threadx_block_memory_thread_terminate_test.c +++ b/test/tx/regression/threadx_block_memory_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread termination on a thread suspended on a block memory pool. */ diff --git a/test/tx/regression/threadx_byte_memory_basic_test.c b/test/tx/regression/threadx_byte_memory_basic_test.c index aff266fdd..45f92e121 100644 --- a/test/tx/regression/threadx_byte_memory_basic_test.c +++ b/test/tx/regression/threadx_byte_memory_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test simple memory byte pool creation, deletion, and allocates and releases. */ diff --git a/test/tx/regression/threadx_byte_memory_information_test.c b/test/tx/regression/threadx_byte_memory_information_test.c index df607acb4..f1624a65a 100644 --- a/test/tx/regression/threadx_byte_memory_information_test.c +++ b/test/tx/regression/threadx_byte_memory_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test byte memory information. */ #include diff --git a/test/tx/regression/threadx_byte_memory_prioritize_test.c b/test/tx/regression/threadx_byte_memory_prioritize_test.c index 9160db91a..db36e386f 100644 --- a/test/tx/regression/threadx_byte_memory_prioritize_test.c +++ b/test/tx/regression/threadx_byte_memory_prioritize_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test byte memory prioritize. */ #include diff --git a/test/tx/regression/threadx_byte_memory_suspension_test.c b/test/tx/regression/threadx_byte_memory_suspension_test.c index 2736195dc..3af5fc81e 100644 --- a/test/tx/regression/threadx_byte_memory_suspension_test.c +++ b/test/tx/regression/threadx_byte_memory_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test suspension on a memory byte pool. */ #include diff --git a/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c b/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c index c5f8adac1..5df630422 100644 --- a/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c +++ b/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test suspension timeout on a memory byte pool. */ #include diff --git a/test/tx/regression/threadx_byte_memory_thread_contention_test.c b/test/tx/regression/threadx_byte_memory_thread_contention_test.c index 1c4deedaa..8e92d44d8 100644 --- a/test/tx/regression/threadx_byte_memory_thread_contention_test.c +++ b/test/tx/regression/threadx_byte_memory_thread_contention_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test contention of two threads on a single memory byte pool. */ diff --git a/test/tx/regression/threadx_byte_memory_thread_terminate_test.c b/test/tx/regression/threadx_byte_memory_thread_terminate_test.c index 35a4615aa..b752f3401 100644 --- a/test/tx/regression/threadx_byte_memory_thread_terminate_test.c +++ b/test/tx/regression/threadx_byte_memory_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test termination on thread suspended on memory byte pool. */ #include diff --git a/test/tx/regression/threadx_event_flag_basic_test.c b/test/tx/regression/threadx_event_flag_basic_test.c index 3261f67fc..8ab990f7a 100644 --- a/test/tx/regression/threadx_event_flag_basic_test.c +++ b/test/tx/regression/threadx_event_flag_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test simple event flag group creation, deletion, gets and sets. */ diff --git a/test/tx/regression/threadx_event_flag_information_test.c b/test/tx/regression/threadx_event_flag_information_test.c index d24040813..45e547f9c 100644 --- a/test/tx/regression/threadx_event_flag_information_test.c +++ b/test/tx/regression/threadx_event_flag_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the event flag group information gathering services. */ #include diff --git a/test/tx/regression/threadx_event_flag_isr_set_clear_test.c b/test/tx/regression/threadx_event_flag_isr_set_clear_test.c index 4cb004d51..ff8674d9c 100644 --- a/test/tx/regression/threadx_event_flag_isr_set_clear_test.c +++ b/test/tx/regression/threadx_event_flag_isr_set_clear_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test for simultaneous thread event flag set AND ISR event flag set and clear. */ #include diff --git a/test/tx/regression/threadx_event_flag_isr_wait_abort_test.c b/test/tx/regression/threadx_event_flag_isr_wait_abort_test.c index e1ec4e7cd..b14e0cbd2 100644 --- a/test/tx/regression/threadx_event_flag_isr_wait_abort_test.c +++ b/test/tx/regression/threadx_event_flag_isr_wait_abort_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test for wait abort from an ISR. */ #include diff --git a/test/tx/regression/threadx_event_flag_single_thread_terminate_test.c b/test/tx/regression/threadx_event_flag_single_thread_terminate_test.c index 866758902..6ae7c7126 100644 --- a/test/tx/regression/threadx_event_flag_single_thread_terminate_test.c +++ b/test/tx/regression/threadx_event_flag_single_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension with a single suspended thread being terminated at the same priority level. */ diff --git a/test/tx/regression/threadx_event_flag_suspension_consume_test.c b/test/tx/regression/threadx_event_flag_suspension_consume_test.c index aae8f1b9c..eaa40258b 100644 --- a/test/tx/regression/threadx_event_flag_suspension_consume_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_consume_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension and resumption of two threads waiting on the same event flag set with the consumption. */ diff --git a/test/tx/regression/threadx_event_flag_suspension_different_bits_consume_test.c b/test/tx/regression/threadx_event_flag_suspension_different_bits_consume_test.c index 595e60edb..5f4c9494b 100644 --- a/test/tx/regression/threadx_event_flag_suspension_different_bits_consume_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_different_bits_consume_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension and resumption of two threads waiting on different event flags with consumption. */ diff --git a/test/tx/regression/threadx_event_flag_suspension_different_bits_test.c b/test/tx/regression/threadx_event_flag_suspension_different_bits_test.c index f9e43cadb..56f9c263d 100644 --- a/test/tx/regression/threadx_event_flag_suspension_different_bits_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_different_bits_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension and resumption of two threads waiting on different event flags. */ diff --git a/test/tx/regression/threadx_event_flag_suspension_test.c b/test/tx/regression/threadx_event_flag_suspension_test.c index 915e33dbc..1c98ab49f 100644 --- a/test/tx/regression/threadx_event_flag_suspension_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension and resumption of three threads waiting on the same event flag set. */ diff --git a/test/tx/regression/threadx_event_flag_suspension_timeout_test.c b/test/tx/regression/threadx_event_flag_suspension_timeout_test.c index fea08bb65..fbfdcc4f5 100644 --- a/test/tx/regression/threadx_event_flag_suspension_timeout_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension timeout processing. */ #include diff --git a/test/tx/regression/threadx_event_flag_thread_terminate_test.c b/test/tx/regression/threadx_event_flag_thread_terminate_test.c index 166711f52..25536903b 100644 --- a/test/tx/regression/threadx_event_flag_thread_terminate_test.c +++ b/test/tx/regression/threadx_event_flag_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test event flag suspension with the suspended threads being terminated. */ diff --git a/test/tx/regression/threadx_initialize_kernel_setup_test.c b/test/tx/regression/threadx_initialize_kernel_setup_test.c index 7f12b872f..057ac2235 100644 --- a/test/tx/regression/threadx_initialize_kernel_setup_test.c +++ b/test/tx/regression/threadx_initialize_kernel_setup_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test kernel setup functionality in ThreadX. */ // Some portions generated by Codex (gpt 5.4). diff --git a/test/tx/regression/threadx_interrupt_control_test.c b/test/tx/regression/threadx_interrupt_control_test.c index c573c0985..ec797ac8a 100644 --- a/test/tx/regression/threadx_interrupt_control_test.c +++ b/test/tx/regression/threadx_interrupt_control_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the interrupt control service call avaialbe to the application. */ diff --git a/test/tx/regression/threadx_mutex_basic_test.c b/test/tx/regression/threadx_mutex_basic_test.c index 419813d32..bb81eb9a3 100644 --- a/test/tx/regression/threadx_mutex_basic_test.c +++ b/test/tx/regression/threadx_mutex_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex create/delete and immediate return gets and puts. */ diff --git a/test/tx/regression/threadx_mutex_delete_test.c b/test/tx/regression/threadx_mutex_delete_test.c index af5014883..c706cc667 100644 --- a/test/tx/regression/threadx_mutex_delete_test.c +++ b/test/tx/regression/threadx_mutex_delete_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and mutex delete with suspended threads. */ diff --git a/test/tx/regression/threadx_mutex_information_test.c b/test/tx/regression/threadx_mutex_information_test.c index 74f4714bf..3829122ce 100644 --- a/test/tx/regression/threadx_mutex_information_test.c +++ b/test/tx/regression/threadx_mutex_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex information services. */ #include diff --git a/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c b/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c index e9b60bf5e..929ea0b97 100644 --- a/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c +++ b/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test multiple mutex priority inheritance situations. */ #include diff --git a/test/tx/regression/threadx_mutex_no_preemption_test.c b/test/tx/regression/threadx_mutex_no_preemption_test.c index 3cc21b62e..2798a5d35 100644 --- a/test/tx/regression/threadx_mutex_no_preemption_test.c +++ b/test/tx/regression/threadx_mutex_no_preemption_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and another thread resuming the same priority thread by doing a mutex put. */ diff --git a/test/tx/regression/threadx_mutex_preemption_test.c b/test/tx/regression/threadx_mutex_preemption_test.c index 495ae13c4..5e3d4c4bd 100644 --- a/test/tx/regression/threadx_mutex_preemption_test.c +++ b/test/tx/regression/threadx_mutex_preemption_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and another thread resuming the higher priority thread by doing a mutex put. Higher-priority thread should preempt. */ diff --git a/test/tx/regression/threadx_mutex_priority_inheritance_test.c b/test/tx/regression/threadx_mutex_priority_inheritance_test.c index 0b76aba6c..8352c9b1d 100644 --- a/test/tx/regression/threadx_mutex_priority_inheritance_test.c +++ b/test/tx/regression/threadx_mutex_priority_inheritance_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and priority inheritance with another thread resuming the higher priority thread by doing a mutex put. Higher-priority thread should preempt. */ diff --git a/test/tx/regression/threadx_mutex_proritize_test.c b/test/tx/regression/threadx_mutex_proritize_test.c index bbc2845b1..899882732 100644 --- a/test/tx/regression/threadx_mutex_proritize_test.c +++ b/test/tx/regression/threadx_mutex_proritize_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension prioritization. */ #include diff --git a/test/tx/regression/threadx_mutex_suspension_timeout_test.c b/test/tx/regression/threadx_mutex_suspension_timeout_test.c index f1a9dfd0e..84aed2e31 100644 --- a/test/tx/regression/threadx_mutex_suspension_timeout_test.c +++ b/test/tx/regression/threadx_mutex_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the mutex suspension and timeout functionality. */ #include diff --git a/test/tx/regression/threadx_mutex_thread_terminate_test.c b/test/tx/regression/threadx_mutex_thread_terminate_test.c index ef21b92df..f41445244 100644 --- a/test/tx/regression/threadx_mutex_thread_terminate_test.c +++ b/test/tx/regression/threadx_mutex_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread terminate calls when threads are suspended on a mutex. */ diff --git a/test/tx/regression/threadx_queue_basic_eight_word_test.c b/test/tx/regression/threadx_queue_basic_eight_word_test.c index fb4640cc4..d3271f2c5 100644 --- a/test/tx/regression/threadx_queue_basic_eight_word_test.c +++ b/test/tx/regression/threadx_queue_basic_eight_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 8 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/tx/regression/threadx_queue_basic_four_word_test.c b/test/tx/regression/threadx_queue_basic_four_word_test.c index 4c54d8bd2..49eb9a85a 100644 --- a/test/tx/regression/threadx_queue_basic_four_word_test.c +++ b/test/tx/regression/threadx_queue_basic_four_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 4 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/tx/regression/threadx_queue_basic_max_message_size_test.c b/test/tx/regression/threadx_queue_basic_max_message_size_test.c index d62e80ff7..0ad2be4e2 100644 --- a/test/tx/regression/threadx_queue_basic_max_message_size_test.c +++ b/test/tx/regression/threadx_queue_basic_max_message_size_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/tx/regression/threadx_queue_basic_one_word_test.c b/test/tx/regression/threadx_queue_basic_one_word_test.c index 0e2f1fbc4..1abb69861 100644 --- a/test/tx/regression/threadx_queue_basic_one_word_test.c +++ b/test/tx/regression/threadx_queue_basic_one_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 1 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/tx/regression/threadx_queue_basic_sixteen_word_test.c b/test/tx/regression/threadx_queue_basic_sixteen_word_test.c index de3ede98b..42205d90d 100644 --- a/test/tx/regression/threadx_queue_basic_sixteen_word_test.c +++ b/test/tx/regression/threadx_queue_basic_sixteen_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/tx/regression/threadx_queue_basic_two_word_test.c b/test/tx/regression/threadx_queue_basic_two_word_test.c index 46d85a6df..fa2a2fedd 100644 --- a/test/tx/regression/threadx_queue_basic_two_word_test.c +++ b/test/tx/regression/threadx_queue_basic_two_word_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including create and delete. This test is for queue sizes of 2 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ diff --git a/test/tx/regression/threadx_queue_empty_suspension_test.c b/test/tx/regression/threadx_queue_empty_suspension_test.c index c63b17153..c0858ac8d 100644 --- a/test/tx/regression/threadx_queue_empty_suspension_test.c +++ b/test/tx/regression/threadx_queue_empty_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test empty queue suspension of queue that supports 3 messages that are each 2 ULONG in size. */ diff --git a/test/tx/regression/threadx_queue_flush_no_suspension_test.c b/test/tx/regression/threadx_queue_flush_no_suspension_test.c index 95bd5fedf..5da58b74e 100644 --- a/test/tx/regression/threadx_queue_flush_no_suspension_test.c +++ b/test/tx/regression/threadx_queue_flush_no_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the queue flush operation on a queue that has no threads suspended on it. */ diff --git a/test/tx/regression/threadx_queue_flush_test.c b/test/tx/regression/threadx_queue_flush_test.c index 77f8d2d5d..a28e2288f 100644 --- a/test/tx/regression/threadx_queue_flush_test.c +++ b/test/tx/regression/threadx_queue_flush_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the queue flush operation on a queue that has two threads suspended on it. */ diff --git a/test/tx/regression/threadx_queue_front_send_test.c b/test/tx/regression/threadx_queue_front_send_test.c index d03e7ac2f..45b5dd65c 100644 --- a/test/tx/regression/threadx_queue_front_send_test.c +++ b/test/tx/regression/threadx_queue_front_send_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test immediate response queue services including queue front send. This test is for queue sizes of 2 ULONG. */ diff --git a/test/tx/regression/threadx_queue_full_suspension_test.c b/test/tx/regression/threadx_queue_full_suspension_test.c index 687ef04a4..d1e1759f6 100644 --- a/test/tx/regression/threadx_queue_full_suspension_test.c +++ b/test/tx/regression/threadx_queue_full_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test queue full suspension of queue that supports 3 messages that are each 2 ULONG in size. */ diff --git a/test/tx/regression/threadx_queue_information_test.c b/test/tx/regression/threadx_queue_information_test.c index 5fcdbb8f4..f884bd0d6 100644 --- a/test/tx/regression/threadx_queue_information_test.c +++ b/test/tx/regression/threadx_queue_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the queue information services. */ #include diff --git a/test/tx/regression/threadx_queue_prioritize.c b/test/tx/regression/threadx_queue_prioritize.c index 53c192756..f904a5255 100644 --- a/test/tx/regression/threadx_queue_prioritize.c +++ b/test/tx/regression/threadx_queue_prioritize.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test queue prioritize. */ #include diff --git a/test/tx/regression/threadx_queue_suspension_timeout_test.c b/test/tx/regression/threadx_queue_suspension_timeout_test.c index 92dca991f..aa05c0dcd 100644 --- a/test/tx/regression/threadx_queue_suspension_timeout_test.c +++ b/test/tx/regression/threadx_queue_suspension_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test queue full and empty suspension with timeouts on queues that supports 3 messages that are each 2 ULONG in size. */ diff --git a/test/tx/regression/threadx_queue_thread_terminate_test.c b/test/tx/regression/threadx_queue_thread_terminate_test.c index 97d8a569d..42673c8d2 100644 --- a/test/tx/regression/threadx_queue_thread_terminate_test.c +++ b/test/tx/regression/threadx_queue_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread terminate when the terminated thread is suspeded on a queue. */ diff --git a/test/tx/regression/threadx_semaphore_basic_test.c b/test/tx/regression/threadx_semaphore_basic_test.c index 33ee32574..3209b5865 100644 --- a/test/tx/regression/threadx_semaphore_basic_test.c +++ b/test/tx/regression/threadx_semaphore_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore create/delete and immediate return gets and puts. */ #include diff --git a/test/tx/regression/threadx_semaphore_ceiling_put_test.c b/test/tx/regression/threadx_semaphore_ceiling_put_test.c index 7d4f58329..f7d7be73e 100644 --- a/test/tx/regression/threadx_semaphore_ceiling_put_test.c +++ b/test/tx/regression/threadx_semaphore_ceiling_put_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore ceiling put. */ #include diff --git a/test/tx/regression/threadx_semaphore_delete_test.c b/test/tx/regression/threadx_semaphore_delete_test.c index 2c9bc1aa4..272a0252c 100644 --- a/test/tx/regression/threadx_semaphore_delete_test.c +++ b/test/tx/regression/threadx_semaphore_delete_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore suspension and semaphore delete with suspended threads. */ diff --git a/test/tx/regression/threadx_semaphore_information_test.c b/test/tx/regression/threadx_semaphore_information_test.c index d2e9bd571..ede276e97 100644 --- a/test/tx/regression/threadx_semaphore_information_test.c +++ b/test/tx/regression/threadx_semaphore_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore information services. */ #include diff --git a/test/tx/regression/threadx_semaphore_non_preemption_test.c b/test/tx/regression/threadx_semaphore_non_preemption_test.c index c075b16cb..e3695e847 100644 --- a/test/tx/regression/threadx_semaphore_non_preemption_test.c +++ b/test/tx/regression/threadx_semaphore_non_preemption_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore suspension and another thread resuming the same priority thread by doing a semaphore put. */ diff --git a/test/tx/regression/threadx_semaphore_preemption_test.c b/test/tx/regression/threadx_semaphore_preemption_test.c index f14193a2a..33677c01b 100644 --- a/test/tx/regression/threadx_semaphore_preemption_test.c +++ b/test/tx/regression/threadx_semaphore_preemption_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore suspension and another thread resuming the higher priority thread by doing a semaphore put. Higher-priority thread should preempt. */ diff --git a/test/tx/regression/threadx_semaphore_prioritize.c b/test/tx/regression/threadx_semaphore_prioritize.c index 6bee46565..30d045900 100644 --- a/test/tx/regression/threadx_semaphore_prioritize.c +++ b/test/tx/regression/threadx_semaphore_prioritize.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test semaphore prioritize. */ #include diff --git a/test/tx/regression/threadx_semaphore_thread_terminate_test.c b/test/tx/regression/threadx_semaphore_thread_terminate_test.c index a15f5963e..7055ed077 100644 --- a/test/tx/regression/threadx_semaphore_thread_terminate_test.c +++ b/test/tx/regression/threadx_semaphore_thread_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread terminate calls when threads are suspended on a semaphore. */ diff --git a/test/tx/regression/threadx_semaphore_timeout_test.c b/test/tx/regression/threadx_semaphore_timeout_test.c index c2fa83ae5..07e25596e 100644 --- a/test/tx/regression/threadx_semaphore_timeout_test.c +++ b/test/tx/regression/threadx_semaphore_timeout_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the semaphore suspension and timeout functionality. */ #include diff --git a/test/tx/regression/threadx_thread_basic_execution_test.c b/test/tx/regression/threadx_thread_basic_execution_test.c index 5bcf1a2ae..c51a677c3 100644 --- a/test/tx/regression/threadx_thread_basic_execution_test.c +++ b/test/tx/regression/threadx_thread_basic_execution_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if one thread can be created and executed. It thread_0_entry is hit, then the thread was successfully scheduled. On success, thread_0_counter gets incremented. */ diff --git a/test/tx/regression/threadx_thread_basic_time_slice_test.c b/test/tx/regression/threadx_thread_basic_time_slice_test.c index 7c83a715b..a4adf72d8 100644 --- a/test/tx/regression/threadx_thread_basic_time_slice_test.c +++ b/test/tx/regression/threadx_thread_basic_time_slice_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if a thread can be created with a time-slice. No time-slice occurs, only the processing to check for time-slicing. */ diff --git a/test/tx/regression/threadx_thread_completed_test.c b/test/tx/regression/threadx_thread_completed_test.c index adaf16836..e8b609e32 100644 --- a/test/tx/regression/threadx_thread_completed_test.c +++ b/test/tx/regression/threadx_thread_completed_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if one thread can be created, executed, and return to the thread shell function. The thread shell function places the thread in a finished state. */ diff --git a/test/tx/regression/threadx_thread_create_preemption_threshold_test.c b/test/tx/regression/threadx_thread_create_preemption_threshold_test.c index 58ce79fe7..b53179cbb 100644 --- a/test/tx/regression/threadx_thread_create_preemption_threshold_test.c +++ b/test/tx/regression/threadx_thread_create_preemption_threshold_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test for preemption-threshold use during thread creation during initialization. */ #include diff --git a/test/tx/regression/threadx_thread_delayed_suspension_test.c b/test/tx/regression/threadx_thread_delayed_suspension_test.c index e5d1e0912..2bf264219 100644 --- a/test/tx/regression/threadx_thread_delayed_suspension_test.c +++ b/test/tx/regression/threadx_thread_delayed_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test checks out the delayed suspension clear from tx_thread_resume. */ #include diff --git a/test/tx/regression/threadx_thread_information_test.c b/test/tx/regression/threadx_thread_information_test.c index 191077424..b5d06e71e 100644 --- a/test/tx/regression/threadx_thread_information_test.c +++ b/test/tx/regression/threadx_thread_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is for the thread information services. */ #include diff --git a/test/tx/regression/threadx_thread_multi_level_preemption_threshold_test.c b/test/tx/regression/threadx_thread_multi_level_preemption_threshold_test.c index 8944da468..59ed4f4d4 100644 --- a/test/tx/regression/threadx_thread_multi_level_preemption_threshold_test.c +++ b/test/tx/regression/threadx_thread_multi_level_preemption_threshold_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test multi-level preemption threshold. The protection placed by a thread must be preserved after higher-priority thread preemption that is above the threshold. */ diff --git a/test/tx/regression/threadx_thread_multiple_non_current_test.c b/test/tx/regression/threadx_thread_multiple_non_current_test.c index 50ed17a0a..a0acc1b99 100644 --- a/test/tx/regression/threadx_thread_multiple_non_current_test.c +++ b/test/tx/regression/threadx_thread_multiple_non_current_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if multiple non-current threads can be suspended. The order the suspension and resumption occurs makes sure everything is working right. Thread execution should remain predictable even after suspension and diff --git a/test/tx/regression/threadx_thread_multiple_sleep_test.c b/test/tx/regression/threadx_thread_multiple_sleep_test.c index f2ae3b998..8c5db032b 100644 --- a/test/tx/regression/threadx_thread_multiple_sleep_test.c +++ b/test/tx/regression/threadx_thread_multiple_sleep_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test multiple threads sleeping for 33 ticks. */ #include diff --git a/test/tx/regression/threadx_thread_multiple_suspension_test.c b/test/tx/regression/threadx_thread_multiple_suspension_test.c index 01c42e8fa..d6577b534 100644 --- a/test/tx/regression/threadx_thread_multiple_suspension_test.c +++ b/test/tx/regression/threadx_thread_multiple_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if multiple threads can be created and suspend. The order the suspension and resumption occurs makes sure everything is working right. All the counters should increment at the same rate. */ diff --git a/test/tx/regression/threadx_thread_multiple_time_slice_test.c b/test/tx/regression/threadx_thread_multiple_time_slice_test.c index f3e9fbf00..af3d80196 100644 --- a/test/tx/regression/threadx_thread_multiple_time_slice_test.c +++ b/test/tx/regression/threadx_thread_multiple_time_slice_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if two threads can be created and execute with a time-slice. Thread 7 should run twice as long because it has more of a time-slice. */ diff --git a/test/tx/regression/threadx_thread_preemptable_suspension_test.c b/test/tx/regression/threadx_thread_preemptable_suspension_test.c index 8e4dbdd6b..acd426c60 100644 --- a/test/tx/regression/threadx_thread_preemptable_suspension_test.c +++ b/test/tx/regression/threadx_thread_preemptable_suspension_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if multiple threads can be created and suspended. The order the suspension and resumption occurs makes sure everything is working right. All the counters should increment at the same rate. This test differs from test 4 in diff --git a/test/tx/regression/threadx_thread_preemption_change_test.c b/test/tx/regression/threadx_thread_preemption_change_test.c index ca0a3c728..2144df19b 100644 --- a/test/tx/regression/threadx_thread_preemption_change_test.c +++ b/test/tx/regression/threadx_thread_preemption_change_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the change preemption service call. */ #include diff --git a/test/tx/regression/threadx_thread_priority_change.c b/test/tx/regression/threadx_thread_priority_change.c index 6a61e2cf0..1cb52ff99 100644 --- a/test/tx/regression/threadx_thread_priority_change.c +++ b/test/tx/regression/threadx_thread_priority_change.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the change priority service call. */ #include diff --git a/test/tx/regression/threadx_thread_relinquish_test.c b/test/tx/regression/threadx_thread_relinquish_test.c index 5b180d84a..fc8b09ede 100644 --- a/test/tx/regression/threadx_thread_relinquish_test.c +++ b/test/tx/regression/threadx_thread_relinquish_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if multiple threads can be created and relinquish control between them. */ #include diff --git a/test/tx/regression/threadx_thread_reset_test.c b/test/tx/regression/threadx_thread_reset_test.c index a709d163c..56006be13 100644 --- a/test/tx/regression/threadx_thread_reset_test.c +++ b/test/tx/regression/threadx_thread_reset_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the tx_thread_reset function. */ #include diff --git a/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c b/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c index 99c5b848a..16bd50962 100644 --- a/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c +++ b/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple sleep for 18 ticks, with something in the remaining field of the thread control block. */ diff --git a/test/tx/regression/threadx_thread_simple_sleep_test.c b/test/tx/regression/threadx_thread_simple_sleep_test.c index 45d42cb00..f7af480cb 100644 --- a/test/tx/regression/threadx_thread_simple_sleep_test.c +++ b/test/tx/regression/threadx_thread_simple_sleep_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple sleep for 18 ticks. */ #include diff --git a/test/tx/regression/threadx_thread_simple_suspend_test.c b/test/tx/regression/threadx_thread_simple_suspend_test.c index 2e21d0568..5089fd64f 100644 --- a/test/tx/regression/threadx_thread_simple_suspend_test.c +++ b/test/tx/regression/threadx_thread_simple_suspend_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to see if a thread can successfully suspend itself in a single thread system. This also tests a thread created that is not automatically enabled. */ diff --git a/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c b/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c index 4b257e8cb..e6ebf1705 100644 --- a/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c +++ b/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple sleep for 100 ticks. */ #include diff --git a/test/tx/regression/threadx_thread_sleep_terminate_test.c b/test/tx/regression/threadx_thread_sleep_terminate_test.c index 98862051d..374f5d431 100644 --- a/test/tx/regression/threadx_thread_sleep_terminate_test.c +++ b/test/tx/regression/threadx_thread_sleep_terminate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread termination of a thread in a sleep condition. */ #include diff --git a/test/tx/regression/threadx_thread_stack_checking_test.c b/test/tx/regression/threadx_thread_stack_checking_test.c index 940b6c6b5..9db10d0aa 100644 --- a/test/tx/regression/threadx_thread_stack_checking_test.c +++ b/test/tx/regression/threadx_thread_stack_checking_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is for the thread stack checking services. */ #include diff --git a/test/tx/regression/threadx_thread_terminate_delete_test.c b/test/tx/regression/threadx_thread_terminate_delete_test.c index 15e25e7d3..2ca2de858 100644 --- a/test/tx/regression/threadx_thread_terminate_delete_test.c +++ b/test/tx/regression/threadx_thread_terminate_delete_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread terminate (self, and other), thread delete, and thread identify services. */ diff --git a/test/tx/regression/threadx_thread_time_slice_change_test.c b/test/tx/regression/threadx_thread_time_slice_change_test.c index 0122fc2ad..ab35bd197 100644 --- a/test/tx/regression/threadx_thread_time_slice_change_test.c +++ b/test/tx/regression/threadx_thread_time_slice_change_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the change time-slice service call. */ #include diff --git a/test/tx/regression/threadx_thread_wait_abort_and_isr_test.c b/test/tx/regression/threadx_thread_wait_abort_and_isr_test.c index bc7446f7b..e15b410fa 100644 --- a/test/tx/regression/threadx_thread_wait_abort_and_isr_test.c +++ b/test/tx/regression/threadx_thread_wait_abort_and_isr_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test for simultaneous thread suspension lifting AND thread wait abort calls. */ #include diff --git a/test/tx/regression/threadx_thread_wait_abort_test.c b/test/tx/regression/threadx_thread_wait_abort_test.c index 49852ec1d..0c3f21f2a 100644 --- a/test/tx/regression/threadx_thread_wait_abort_test.c +++ b/test/tx/regression/threadx_thread_wait_abort_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test thread wait abort. */ #include diff --git a/test/tx/regression/threadx_time_get_set_test.c b/test/tx/regression/threadx_time_get_set_test.c index 84b099472..242735ec2 100644 --- a/test/tx/regression/threadx_time_get_set_test.c +++ b/test/tx/regression/threadx_time_get_set_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test simple tx_time_get and set services. */ #include diff --git a/test/tx/regression/threadx_timer_activate_deactivate_test.c b/test/tx/regression/threadx_timer_activate_deactivate_test.c index 69f9b38fc..ceaf79bf7 100644 --- a/test/tx/regression/threadx_timer_activate_deactivate_test.c +++ b/test/tx/regression/threadx_timer_activate_deactivate_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test application timer activation/deactivation services from threads and the activation routines. */ diff --git a/test/tx/regression/threadx_timer_deactivate_accuracy_test.c b/test/tx/regression/threadx_timer_deactivate_accuracy_test.c index 625b82a65..0da41a7a0 100644 --- a/test/tx/regression/threadx_timer_deactivate_accuracy_test.c +++ b/test/tx/regression/threadx_timer_deactivate_accuracy_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test application timer activation/deactivation services from threads... Make sure the remaining ticks are being saved/restored properly. */ diff --git a/test/tx/regression/threadx_timer_information_test.c b/test/tx/regression/threadx_timer_information_test.c index 7954de2cd..ae3bb4141 100644 --- a/test/tx/regression/threadx_timer_information_test.c +++ b/test/tx/regression/threadx_timer_information_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test timer information services. */ #include diff --git a/test/tx/regression/threadx_timer_large_timer_accuracy_test.c b/test/tx/regression/threadx_timer_large_timer_accuracy_test.c index 726523b9e..f44d4f059 100644 --- a/test/tx/regression/threadx_timer_large_timer_accuracy_test.c +++ b/test/tx/regression/threadx_timer_large_timer_accuracy_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test application timer activation/deactivation services from threads... To make sure large timer expirations are being saved/restored properly. */ diff --git a/test/tx/regression/threadx_timer_multiple_accuracy_test.c b/test/tx/regression/threadx_timer_multiple_accuracy_test.c index 206f28025..a4cceefa1 100644 --- a/test/tx/regression/threadx_timer_multiple_accuracy_test.c +++ b/test/tx/regression/threadx_timer_multiple_accuracy_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test the accuracy of three free running timers. */ #include diff --git a/test/tx/regression/threadx_timer_multiple_test.c b/test/tx/regression/threadx_timer_multiple_test.c index 46742a385..f8d99e5cd 100644 --- a/test/tx/regression/threadx_timer_multiple_test.c +++ b/test/tx/regression/threadx_timer_multiple_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple application timer services, including create, activate, deactivate, change, and delete with multiple timers. */ diff --git a/test/tx/regression/threadx_timer_simple_test.c b/test/tx/regression/threadx_timer_simple_test.c index 7fdf022e8..cad670861 100644 --- a/test/tx/regression/threadx_timer_simple_test.c +++ b/test/tx/regression/threadx_timer_simple_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test a simple application timer services, including create, activate, deactivate, change, and delete. */ diff --git a/test/tx/regression/threadx_trace_basic_test.c b/test/tx/regression/threadx_trace_basic_test.c index 0914650ff..c40be8f18 100644 --- a/test/tx/regression/threadx_trace_basic_test.c +++ b/test/tx/regression/threadx_trace_basic_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This test is designed to test trace functionality in ThreadX. */ diff --git a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_basic_test_example.c b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_basic_test_example.c index 9430d71cf..c6f17d94e 100644 --- a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_basic_test_example.c +++ b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_basic_test_example.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" diff --git a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_cooperative_scheduling_test_example.c b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_cooperative_scheduling_test_example.c index 9430d71cf..c6f17d94e 100644 --- a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_cooperative_scheduling_test_example.c +++ b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_cooperative_scheduling_test_example.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" diff --git a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_interrupt_preemption_test_example.c b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_interrupt_preemption_test_example.c index 9430d71cf..c6f17d94e 100644 --- a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_interrupt_preemption_test_example.c +++ b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_interrupt_preemption_test_example.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" diff --git a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_interrupt_test_example.c b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_interrupt_test_example.c index 9430d71cf..c6f17d94e 100644 --- a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_interrupt_test_example.c +++ b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_interrupt_test_example.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" diff --git a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_memory_allocation_test_example.c b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_memory_allocation_test_example.c index 9430d71cf..c6f17d94e 100644 --- a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_memory_allocation_test_example.c +++ b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_memory_allocation_test_example.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" diff --git a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_message_processing_test_example.c b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_message_processing_test_example.c index 9430d71cf..c6f17d94e 100644 --- a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_message_processing_test_example.c +++ b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_message_processing_test_example.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" diff --git a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_preemptive_scheduling_test_example.c b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_preemptive_scheduling_test_example.c index 9430d71cf..c6f17d94e 100644 --- a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_preemptive_scheduling_test_example.c +++ b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_preemptive_scheduling_test_example.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" diff --git a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_synchronization_test_example.c b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_synchronization_test_example.c index 9430d71cf..c6f17d94e 100644 --- a/utility/benchmarks/thread_metric/threadx_example/threadx_tm_synchronization_test_example.c +++ b/utility/benchmarks/thread_metric/threadx_example/threadx_tm_synchronization_test_example.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include "tx_api.h" diff --git a/utility/rtos_compatibility_layers/OSEK/demo_osek.c b/utility/rtos_compatibility_layers/OSEK/demo_osek.c index 2e104d31b..f4d23f420 100644 --- a/utility/rtos_compatibility_layers/OSEK/demo_osek.c +++ b/utility/rtos_compatibility_layers/OSEK/demo_osek.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + #include diff --git a/utility/rtos_compatibility_layers/posix/posix_demo.c b/utility/rtos_compatibility_layers/posix/posix_demo.c index 7adeb9c32..e8ec950cd 100644 --- a/utility/rtos_compatibility_layers/posix/posix_demo.c +++ b/utility/rtos_compatibility_layers/posix/posix_demo.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* This is a small demo of the POSIX Compliancy Wrapper for the high-performance ThreadX kernel. */ /* It includes examples of six pthreads of different priorities, using a message queue, semaphore and mutex. */ diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_nested_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_nested_test.c index 6f5b64788..3c183968a 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_nested_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_nested_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Simple nested-signaling test. */ #include "pthread.h" diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_resume_thread_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_resume_thread_test.c index 90878158b..c6dc8c6c8 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_resume_thread_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_resume_thread_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Simple resume from signal handler test. */ #include "pthread.h" diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_self_send_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_self_send_test.c index bbeb419f8..5847029cf 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_self_send_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_self_send_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Simple self-signaling test. */ #include "pthread.h" diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_sigmask_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_sigmask_test.c index 1f9c690b7..e9404d25b 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_sigmask_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_sigmask_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Simple signal sigmask test. */ #include "pthread.h" diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_sigwait_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_sigwait_test.c index aa459735c..523736fcf 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_sigwait_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_sigwait_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Simple signal sigwait test. */ #include "pthread.h" diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_suspended_thread_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_suspended_thread_test.c index 40d11eeac..ad0e33b29 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_suspended_thread_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_suspended_thread_test.c @@ -1,3 +1,14 @@ +/***************************************************************************/ +/* Copyright (c) 2024 Microsoft Corporation */ +/* Copyright (c) 2026 Eclipse ThreadX contributors */ +/* */ +/* This program and the accompanying materials are made available under */ +/* the terms of the MIT License which is available at */ +/* https://opensource.org/licenses/MIT. */ +/* */ +/* SPDX-License-Identifier: MIT */ +/***************************************************************************/ + /* Simple nested-signaling test. */ #include "pthread.h"