diff --git a/RTX_Blinky/Abstract.txt b/RTX_Blinky/Abstract.txt new file mode 100644 index 0000000..15627ac --- /dev/null +++ b/RTX_Blinky/Abstract.txt @@ -0,0 +1,17 @@ +The 'RTX_Blinky' project is a simple CMSIS RTOS Kernel based example for +ST 'STM32F072RB' microcontroller using ST 'STM32F072-Discovery' Evaluation Board. +Compliant to Cortex Microcontroller Software Interface Standard (CMSIS). + +Example functionality: + - Clock Settings: + - XTAL = HSI = 8.00 MHz + - SYSCLK = 48.00 MHz + + - 4 LEDs blink. + - blinking is paused while holding down the USER button. + + +The Blinky example is available in different targets: + + STM32F072 Flash: configured for on-chip Flash + (used for production or target debugging) diff --git a/RTX_Blinky/DAC_DRV.c b/RTX_Blinky/DAC_DRV.c new file mode 100644 index 0000000..256012e --- /dev/null +++ b/RTX_Blinky/DAC_DRV.c @@ -0,0 +1,56 @@ + +/** @file DAC_DRV.c + * @brief DAC Driver for the STM32F072RB. + * @author Dennis Law + * @date April 2016 + */ + +#include "DAC_DRV.h" + +/** @brief Reads the output register of channel 1. + * @returns The value of DAC_DOR1 register. + */ +uint32_t DAC_read(void) +{ + return (DAC->DOR1 & 0x00000FFF); +} + +/** @brief Writes an analog value to channel 1. + * @param data The data to be written to the data register. + * + * @details The user input value is written to the 12 bit right aligned + * register, DAC_DHR12R1. The output voltage is calculated using the formula + * + * DAC(output) = V(DDA) * DOR / 4095 + * + */ +void DAC_write(uint32_t data) +{ + DAC->DHR12R1 = (data & 0x00000FFF); +} + +/** @brief Enables channel 1. + */ +void DAC_enable(void) +{ + DAC->CR |= DAC_CR_EN1; +} + +/** @brief Initializes channel 1 in Single Mode with no triggerring. + */ +void DAC_init(void) +{ + /* Enable clock for DAC peripheral */ + RCC->APB1ENR |= RCC_APB1ENR_DACEN; + + /* Set corresponding GPIO pin as analog input with no pull + resistors */ + GPIOA->MODER |= GPIO_MODER_MODER4; + GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR4); + + /* Disable triggerring */ + DAC->CR &= ~(DAC_CR_TEN1); + + /* Enable output buffer */ + DAC->CR |= DAC_CR_BOFF1; +} diff --git a/RTX_Blinky/DAC_DRV.h b/RTX_Blinky/DAC_DRV.h new file mode 100644 index 0000000..ee07853 --- /dev/null +++ b/RTX_Blinky/DAC_DRV.h @@ -0,0 +1,20 @@ + +/** @file DAC_DRV.h + * @brief DAC Driver include file for the STM32F072RB. + * @author Dennis Law + * @date April 2016 + */ + +#ifndef DAC_DRV_H +#define DAC_DRV_H + +#include "stm32f0xx.h" +#include + +uint32_t DAC_read(void); +void DAC_write(uint32_t data); +void DAC_load_data_buffer(uint32_t data); +void DAC_enable(void); +void DAC_init(void); + +#endif /* DAC_DRV_H */ diff --git a/RTX_Blinky/Flash/RTX_Blinky.axf b/RTX_Blinky/Flash/RTX_Blinky.axf new file mode 100644 index 0000000..657025a Binary files /dev/null and b/RTX_Blinky/Flash/RTX_Blinky.axf differ diff --git a/RTX_Blinky/Flash/RTX_Blinky.build_log.htm b/RTX_Blinky/Flash/RTX_Blinky.build_log.htm new file mode 100644 index 0000000..2b0cbb9 --- /dev/null +++ b/RTX_Blinky/Flash/RTX_Blinky.build_log.htm @@ -0,0 +1,113 @@ + + +
+
µVision Build Log

+
Tool Versions:

+IDE-Version: µVision V5.17.0.0
+Copyright (C) 2015 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: Patrick Tiong, DNA , LIC=----
+ 
+Tool Versions:
+Toolchain:       MDK-Lite  Version: 5.17
+Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 1 (build 61)
+Assembler:       Armasm.exe V5.06 update 1 (build 61)
+Linker/Locator:  ArmLink.exe V5.06 update 1 (build 61)
+Library Manager: ArmAr.exe V5.06 update 1 (build 61)
+Hex Converter:   FromElf.exe V5.06 update 1 (build 61)
+CPU DLL:         SARMCM3.DLL V5.17
+Dialog DLL:      DARMCM1.DLL V1.12.0.0
+Target DLL:      STLink\ST-LINKIII-KEIL_SWO.dll V2.0.18.0
+Dialog DLL:      TARMCM1.DLL V1.9.0.0
+ 
+
Project:

+C:\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX_Blinky\RTX_Blinky.uvprojx
+Project File Date:  04/24/2016
+
+
Output:

+*** Using Compiler 'V5.06 update 1 (build 61)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+Rebuild target 'STM32F072 Flash'
+compiling Buttons_STM32F072-Discovery.c...
+compiling DAC_DRV.c...
+compiling RTX_Blinky.c...
+compiling RTX_Conf_CM.c...
+assembling startup_stm32f072xb.s...
+compiling LED_STM32F072-Discovery.c...
+compiling system_stm32f0xx.c...
+linking...
+Program Size: Code=6332 RO-data=360 RW-data=624 ZI-data=2688  
+".\Flash\RTX_Blinky.axf" - 0 Error(s), 0 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.4.5.0.pack
+                ::CMSIS:RTOS:1.0 (API)
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: RTOS Version: 1.0
+   * Component: Keil RTX Version: 4.80.0
+   * Component: CORE Version: 4.3.0
+
+Package Vendor: Keil
+                http://www.keil.com/pack/Keil.MDK-Middleware.7.0.0.pack
+                ::Board Support:LED:1.00 (API)
+                Keil MDK-ARM Professional Middleware for ARM Cortex-M based devices
+   * Component: LED Version: 1.00
+   * Component: Buttons Version: 1.00
+
+Package Vendor: Keil
+                http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack
+                Keil.STM32F072-Discovery::Board Support:LED:1.0.0
+                STMicroelectronics STM32F0 Series Device Support and Examples
+   * Component: LED Version: 1.0.0
+   * Component: Buttons Version: 1.0.0
+   * Component: Startup Version: 2.2.3
+
+
Collection of Component include folders:

+  C:\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX_Blinky\RTE
+  C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include
+  C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC
+  C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board
+  C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include
+
+
Collection of Component Files used:

+
+   * Component: ::CMSIS:RTOS:1.0 (API)
+
+   * Component: ARM::CMSIS:RTOS:Keil RTX:4.80.0
+      Source file:   CMSIS\RTOS\RTX\UserCodeTemplates\MemPool.c
+      Include file:  CMSIS\RTOS\RTX\UserCodeTemplates\osObjects.h
+      Source file:   CMSIS\RTOS\RTX\Templates\RTX_Conf_CM.c
+      Source file:   CMSIS\RTOS\RTX\UserCodeTemplates\Mutex.c
+      Source file:   CMSIS\RTOS\RTX\UserCodeTemplates\main.c
+      Source file:   CMSIS\RTOS\RTX\UserCodeTemplates\MailQueue.c
+      Source file:   CMSIS\RTOS\RTX\UserCodeTemplates\Semaphore.c
+      Source file:   CMSIS\RTOS\RTX\SRC\ARM\SVC_Table.s
+      Source file:   CMSIS\RTOS\RTX\UserCodeTemplates\Thread.c
+      Include file:  CMSIS\RTOS\RTX\INC\cmsis_os.h
+      Source file:   CMSIS\RTOS\RTX\UserCodeTemplates\MsgQueue.c
+      Source file:   CMSIS\RTOS\RTX\UserCodeTemplates\Timer.c
+      Library file:  CMSIS\RTOS\RTX\LIB\ARM\RTX_CM0.lib
+
+   * Component: ARM::CMSIS:CORE:4.3.0
+
+   * Component: ::Board Support:LED:1.00 (API)
+      Include file:  Board\Board_LED.h
+
+   * Component: ::Board Support:Buttons:1.00 (API)
+      Include file:  Board\Board_Buttons.h
+
+   * Component: Keil.STM32F072-Discovery::Board Support:LED:1.0.0
+      Source file:   Boards\ST\STM32F072-Discovery\Common\LED_STM32F072-Discovery.c
+
+   * Component: Keil.STM32F072-Discovery::Board Support:Buttons:1.0.0
+      Source file:   Boards\ST\STM32F072-Discovery\Common\Buttons_STM32F072-Discovery.c
+
+   * Component: Keil::Device:Startup:2.2.3
+      Source file:   Device\Source\ARM\startup_stm32f072xb.s
+      Source file:   Device\Source\system_stm32f0xx.c
+      Source file:   Device\Source\ARM\STM32F0xx_OPT.s
+Build Time Elapsed:  00:00:01
+
+ + diff --git a/RTX_Blinky/Flash/RTX_Blinky.htm b/RTX_Blinky/Flash/RTX_Blinky.htm new file mode 100644 index 0000000..8cd3447 --- /dev/null +++ b/RTX_Blinky/Flash/RTX_Blinky.htm @@ -0,0 +1,973 @@ + + +Static Call Graph - [.\Flash\RTX_Blinky.axf] +
+

Static Call Graph for image .\Flash\RTX_Blinky.axf

+

#<CALLGRAPH># ARM Linker, 5060061: Last Updated: Mon Apr 25 21:44:24 2016 +

+

Maximum Stack Usage = 108 bytes + Unknown(Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+main ⇒ osKernelInitialize ⇒ svcKernelInitialize ⇒ svcThreadCreate ⇒ rt_tsk_create ⇒ rt_init_context ⇒ rt_init_stack +

+

+Mutually Recursive functions +

  • NMI_Handler   ⇒   NMI_Handler
    +
  • HardFault_Handler   ⇒   HardFault_Handler
    +
  • ADC1_COMP_IRQHandler   ⇒   ADC1_COMP_IRQHandler
    + +

    +

    +Function Pointers +

    +

    +

    +Global Symbols +

    +

    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000)) +
    [Address Reference Count : 1]

    +

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) + +

    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Calls]

    + +

    __main_after_scatterload (Thumb, 0 bytes, Stack size 0 bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Called By]

    + +

    __rt_final_cpp (Thumb, 0 bytes, Stack size 0 bytes, entry10a.o(.ARM.Collect$$$$0000000D)) + +

    __rt_final_exit (Thumb, 0 bytes, Stack size 0 bytes, entry11a.o(.ARM.Collect$$$$0000000F)) + +

    _main_clock (Thumb, 0 bytes, Stack size 0 bytes, entry7b.o(.ARM.Collect$$$$00000008)) + +

    _main_cpp_init (Thumb, 0 bytes, Stack size 0 bytes, entry8b.o(.ARM.Collect$$$$0000000A)) + +

    _main_init (Thumb, 18 bytes, Stack size 0 bytes, rtx_conf_cm.o(.ARM.Collect$$$$000000FF)) +

    [Stack]

    +
    [Calls] + +

    rt_set_PSP (Thumb, 6 bytes, Stack size 0 bytes, hal_cm0.o(.emb_text), UNUSED) + +

    rt_get_PSP (Thumb, 6 bytes, Stack size 0 bytes, hal_cm0.o(.emb_text)) +

    [Called By]

    + +

    os_set_env (Thumb, 32 bytes, Stack size 0 bytes, hal_cm0.o(.emb_text), UNUSED) + +

    _alloc_box (Thumb, 28 bytes, Stack size 0 bytes, hal_cm0.o(.emb_text), UNUSED) + +

    _free_box (Thumb, 28 bytes, Stack size 0 bytes, hal_cm0.o(.emb_text), UNUSED) + +

    SVC_Handler (Thumb, 136 bytes, Stack size 0 bytes, hal_cm0.o(.emb_text)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    PendSV_Handler (Thumb, 72 bytes, Stack size 0 bytes, hal_cm0.o(.emb_text)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    SysTick_Handler (Thumb, 8 bytes, Stack size 0 bytes, hal_cm0.o(.emb_text)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    OS_Tick_Handler (Thumb, 12 bytes, Stack size 0 bytes, hal_cm0.o(.emb_text), UNUSED) +

    [Calls]

    + +

    SystemCoreClockConfigure (Thumb, 196 bytes, Stack size 0 bytes, rtx_blinky.o(.text)) +

    [Called By]

    + +

    blinkLED (Thumb, 62 bytes, Stack size 16 bytes, rtx_blinky.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    main (Thumb, 184 bytes, Stack size 0 bytes, rtx_blinky.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    DAC_read (Thumb, 10 bytes, Stack size 0 bytes, dac_drv.o(.text), UNUSED) + +

    DAC_write (Thumb, 10 bytes, Stack size 0 bytes, dac_drv.o(.text)) +

    [Called By]

    + +

    DAC_enable (Thumb, 14 bytes, Stack size 0 bytes, dac_drv.o(.text)) +

    [Called By]

    + +

    DAC_init (Thumb, 74 bytes, Stack size 0 bytes, dac_drv.o(.text)) +

    [Called By]

    + +

    Buttons_Initialize (Thumb, 54 bytes, Stack size 0 bytes, buttons_stm32f072-discovery.o(.text)) +

    [Called By]

    + +

    Buttons_Uninitialize (Thumb, 20 bytes, Stack size 0 bytes, buttons_stm32f072-discovery.o(.text), UNUSED) + +

    Buttons_GetState (Thumb, 22 bytes, Stack size 0 bytes, buttons_stm32f072-discovery.o(.text), UNUSED) + +

    Buttons_GetCount (Thumb, 4 bytes, Stack size 0 bytes, buttons_stm32f072-discovery.o(.text)) +

    [Called By]

    + +

    LED_Off (Thumb, 28 bytes, Stack size 0 bytes, led_stm32f072-discovery.o(.text)) +

    [Called By]

    + +

    LED_On (Thumb, 26 bytes, Stack size 0 bytes, led_stm32f072-discovery.o(.text)) +

    [Called By]

    + +

    LED_SetOut (Thumb, 42 bytes, Stack size 12 bytes, led_stm32f072-discovery.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    LED_Initialize (Thumb, 110 bytes, Stack size 4 bytes, led_stm32f072-discovery.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    LED_Uninitialize (Thumb, 4 bytes, Stack size 0 bytes, led_stm32f072-discovery.o(.text), UNUSED) + +

    LED_GetCount (Thumb, 4 bytes, Stack size 0 bytes, led_stm32f072-discovery.o(.text)) +

    [Called By]

    + +

    os_idle_demon (Thumb, 4 bytes, Stack size 0 bytes, rtx_conf_cm.o(.text)) +
    [Address Reference Count : 1]

    +

    os_error (Thumb, 34 bytes, Stack size 0 bytes, rtx_conf_cm.o(.text)) +

    [Called By]

    + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +

    [Calls]

    +
    [Called By] +
    [Address Reference Count : 1] +

    HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +

    [Calls]

    +
    [Called By] +
    [Address Reference Count : 1] +

    ADC1_COMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +

    [Calls]

    +
    [Called By] +
    [Address Reference Count : 1] +

    CEC_CAN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    DMA1_Channel2_3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    DMA1_Channel4_5_6_7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI0_1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI2_3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI4_15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    PVD_VDDIO2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    RCC_CRS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM16_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM17_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM1_BRK_UP_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    TSC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    USART3_4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    USB_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f072xb.o(.text)) +
    [Address Reference Count : 1]

    +

    SystemInit (Thumb, 102 bytes, Stack size 0 bytes, system_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SystemCoreClockUpdate (Thumb, 188 bytes, Stack size 24 bytes, system_stm32f0xx.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    __aeabi_uidiv (Thumb, 0 bytes, Stack size 12 bytes, uidiv.o(.text), UNUSED) + +

    __aeabi_uidivmod (Thumb, 44 bytes, Stack size 12 bytes, uidiv.o(.text)) +

    [Stack]

    +
    [Called By] + +

    __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text)) +

    [Calls]

    +
    [Called By] + +

    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) + +

    __decompress (Thumb, 0 bytes, Stack size unknown bytes, __dczerorl.o(.text), UNUSED) + +

    __decompress0 (Thumb, 58 bytes, Stack size unknown bytes, __dczerorl.o(.text), UNUSED) + +

    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) + +

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) + +

    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) + +

    _init_box (Thumb, 72 bytes, Stack size 8 bytes, rt_membox.o(i._init_box)) +

    [Stack]

    +
    [Called By] + +

    isrMessageGet (Thumb, 46 bytes, Stack size 16 bytes, rt_cmsis.o(i.isrMessageGet)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    isrMessagePut (Thumb, 48 bytes, Stack size 16 bytes, rt_cmsis.o(i.isrMessagePut)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    isr_mbx_receive (Thumb, 70 bytes, Stack size 8 bytes, rt_mailbox.o(i.isr_mbx_receive)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    isr_mbx_send (Thumb, 12 bytes, Stack size 8 bytes, rt_mailbox.o(i.isr_mbx_send)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    osKernelInitialize (Thumb, 36 bytes, Stack size 8 bytes, rt_cmsis.o(i.osKernelInitialize)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    osKernelStart (Thumb, 100 bytes, Stack size 40 bytes, rt_cmsis.o(i.osKernelStart)) +

    [Stack]

    +
    [Called By] + +

    osMessageGet (Thumb, 24 bytes, Stack size 8 bytes, rt_cmsis.o(i.osMessageGet)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    osSignalWait (Thumb, 22 bytes, Stack size 8 bytes, rt_cmsis.o(i.osSignalWait)) +

    [Stack]

    +
    [Called By] + +

    osThreadCreate (Thumb, 44 bytes, Stack size 8 bytes, rt_cmsis.o(i.osThreadCreate)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    osThreadExit (Thumb, 14 bytes, Stack size 0 bytes, rt_cmsis.o(i.osThreadExit)) +
    [Address Reference Count : 1]

    +

    osTimerCall (Thumb, 10 bytes, Stack size 8 bytes, rt_cmsis.o(i.osTimerCall)) +

    [Stack]

    +
    [Called By] + +

    osTimerThread (Thumb, 38 bytes, Stack size 0 bytes, rt_cmsis.o(i.osTimerThread)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    os_tick_init (Thumb, 32 bytes, Stack size 0 bytes, rt_system.o(i.os_tick_init)) +

    [Called By]

    + +

    os_tick_irqack (Thumb, 2 bytes, Stack size 0 bytes, rt_system.o(i.os_tick_irqack), UNUSED) +

    [Called By]

    + +

    rt_alloc_box (Thumb, 30 bytes, Stack size 0 bytes, rt_membox.o(i.rt_alloc_box)) +

    [Called By]

    +
    [Address Reference Count : 1] +

    rt_alloc_mem (Thumb, 66 bytes, Stack size 8 bytes, rt_memory.o(i.rt_alloc_mem)) +

    [Stack]

    +
    [Called By] + +

    rt_block (Thumb, 42 bytes, Stack size 16 bytes, rt_task.o(i.rt_block)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_chk_robin (Thumb, 56 bytes, Stack size 8 bytes, rt_robin.o(i.rt_chk_robin)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_dec_dly (Thumb, 108 bytes, Stack size 16 bytes, rt_list.o(i.rt_dec_dly)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_dispatch (Thumb, 56 bytes, Stack size 16 bytes, rt_task.o(i.rt_dispatch)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_evt_psh (Thumb, 74 bytes, Stack size 8 bytes, rt_event.o(i.rt_evt_psh)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_evt_wait (Thumb, 58 bytes, Stack size 16 bytes, rt_event.o(i.rt_evt_wait)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_free_box (Thumb, 38 bytes, Stack size 0 bytes, rt_membox.o(i.rt_free_box)) +

    [Called By]

    +
    [Address Reference Count : 1] +

    rt_free_mem (Thumb, 48 bytes, Stack size 0 bytes, rt_memory.o(i.rt_free_mem)) +

    [Called By]

    + +

    rt_get_first (Thumb, 42 bytes, Stack size 0 bytes, rt_list.o(i.rt_get_first)) +

    [Called By]

    + +

    rt_init_mem (Thumb, 28 bytes, Stack size 0 bytes, rt_memory.o(i.rt_init_mem)) +

    [Called By]

    + +

    rt_init_robin (Thumb, 14 bytes, Stack size 0 bytes, rt_robin.o(i.rt_init_robin)) +

    [Called By]

    + +

    rt_init_stack (Thumb, 106 bytes, Stack size 20 bytes, hal_cm.o(i.rt_init_stack)) +

    [Stack]

    +
    [Called By] + +

    rt_mbx_check (Thumb, 8 bytes, Stack size 0 bytes, rt_mailbox.o(i.rt_mbx_check)) +

    [Called By]

    + +

    rt_mbx_init (Thumb, 30 bytes, Stack size 0 bytes, rt_mailbox.o(i.rt_mbx_init)) +

    [Called By]

    + +

    rt_mbx_psh (Thumb, 204 bytes, Stack size 24 bytes, rt_mailbox.o(i.rt_mbx_psh)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_mbx_wait (Thumb, 170 bytes, Stack size 16 bytes, rt_mailbox.o(i.rt_mbx_wait)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_pop_req (Thumb, 100 bytes, Stack size 16 bytes, rt_system.o(i.rt_pop_req)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_psh_req (Thumb, 24 bytes, Stack size 0 bytes, rt_system.o(i.rt_psh_req)) +

    [Called By]

    + +

    rt_psq_enq (Thumb, 60 bytes, Stack size 16 bytes, rt_list.o(i.rt_psq_enq)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_put_dly (Thumb, 74 bytes, Stack size 8 bytes, rt_list.o(i.rt_put_dly)) +

    [Stack]

    +
    [Called By] + +

    rt_put_prio (Thumb, 60 bytes, Stack size 12 bytes, rt_list.o(i.rt_put_prio)) +

    [Stack]

    +
    [Called By] + +

    rt_put_rdy_first (Thumb, 14 bytes, Stack size 0 bytes, rt_list.o(i.rt_put_rdy_first)) +

    [Called By]

    + +

    rt_resort_prio (Thumb, 44 bytes, Stack size 8 bytes, rt_list.o(i.rt_resort_prio)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_ret_val (Thumb, 6 bytes, Stack size 0 bytes, hal_cm.o(i.rt_ret_val)) +

    [Called By]

    + +

    rt_ret_val2 (Thumb, 8 bytes, Stack size 0 bytes, hal_cm.o(i.rt_ret_val2)) +

    [Called By]

    + +

    rt_rmv_dly (Thumb, 42 bytes, Stack size 8 bytes, rt_list.o(i.rt_rmv_dly)) +

    [Stack]

    +
    [Called By] + +

    rt_rmv_list (Thumb, 46 bytes, Stack size 0 bytes, rt_list.o(i.rt_rmv_list)) +

    [Called By]

    + +

    rt_sem_psh (Thumb, 48 bytes, Stack size 8 bytes, rt_semaphore.o(i.rt_sem_psh)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_stk_check (Thumb, 30 bytes, Stack size 8 bytes, rt_system.o(i.rt_stk_check)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_switch_req (Thumb, 10 bytes, Stack size 0 bytes, rt_task.o(i.rt_switch_req)) +

    [Called By]

    + +

    rt_sys_init (Thumb, 134 bytes, Stack size 16 bytes, rt_task.o(i.rt_sys_init)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_sys_start (Thumb, 82 bytes, Stack size 8 bytes, rt_task.o(i.rt_sys_start)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_systick (Thumb, 48 bytes, Stack size 8 bytes, rt_system.o(i.rt_systick)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_tsk_create (Thumb, 106 bytes, Stack size 40 bytes, rt_task.o(i.rt_tsk_create)) +

    [Stack]

    +
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    [Called By] + +

    rt_tsk_delete (Thumb, 318 bytes, Stack size 24 bytes, rt_task.o(i.rt_tsk_delete)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_tsk_prio (Thumb, 112 bytes, Stack size 16 bytes, rt_task.o(i.rt_tsk_prio)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_tsk_self (Thumb, 12 bytes, Stack size 0 bytes, rt_task.o(i.rt_tsk_self)) +

    [Called By]

    + +

    svcKernelInitialize (Thumb, 86 bytes, Stack size 8 bytes, rt_cmsis.o(i.svcKernelInitialize)) +

    [Stack]

    +
    [Calls] +
    [Called By] +
    [Address Reference Count : 1] +

    svcKernelStart (Thumb, 66 bytes, Stack size 16 bytes, rt_cmsis.o(i.svcKernelStart)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    svcMessageCreate (Thumb, 42 bytes, Stack size 8 bytes, rt_cmsis.o(i.svcMessageCreate)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    svcMessageGet (Thumb, 60 bytes, Stack size 24 bytes, rt_cmsis.o(i.svcMessageGet)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    svcSignalWait (Thumb, 82 bytes, Stack size 16 bytes, rt_cmsis.o(i.svcSignalWait)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    svcThreadCreate (Thumb, 106 bytes, Stack size 16 bytes, rt_cmsis.o(i.svcThreadCreate)) +

    [Stack]

    +
    [Calls] +
    [Called By] +
    [Address Reference Count : 1] +

    svcThreadGetId (Thumb, 22 bytes, Stack size 8 bytes, rt_cmsis.o(i.svcThreadGetId)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    svcThreadTerminate (Thumb, 56 bytes, Stack size 8 bytes, rt_cmsis.o(i.svcThreadTerminate)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    svcTimerCall (Thumb, 28 bytes, Stack size 8 bytes, rt_cmsis.o(i.svcTimerCall)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    sysTimerTick (Thumb, 78 bytes, Stack size 24 bytes, rt_cmsis.o(i.sysTimerTick)) +

    [Stack]

    +
    [Calls] +
    [Called By] +

    +

    +Local Symbols +

    +

    rt_id2obj (Thumb, 8 bytes, Stack size 0 bytes, rt_cmsis.o(i.rt_id2obj)) +

    [Called By]

    + +

    rt_ms2tick (Thumb, 56 bytes, Stack size 8 bytes, rt_cmsis.o(i.rt_ms2tick)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    rt_tid2ptcb (Thumb, 18 bytes, Stack size 0 bytes, rt_cmsis.o(i.rt_tid2ptcb)) +

    [Called By]

    + +

    rt_timer_insert (Thumb, 52 bytes, Stack size 12 bytes, rt_cmsis.o(i.rt_timer_insert)) +

    [Stack]

    +
    [Called By] + +

    rt_init_context (Thumb, 66 bytes, Stack size 16 bytes, rt_task.o(i.rt_init_context)) +

    [Stack]

    +
    [Calls] +
    [Called By] +

    +

    +Undefined Global Symbols +

    diff --git a/RTX_Blinky/Flash/RTX_Blinky.lnp b/RTX_Blinky/Flash/RTX_Blinky.lnp new file mode 100644 index 0000000..895df0f --- /dev/null +++ b/RTX_Blinky/Flash/RTX_Blinky.lnp @@ -0,0 +1,13 @@ +--cpu Cortex-M0 +".\flash\rtx_blinky.o" +".\flash\dac_drv.o" +".\flash\buttons_stm32f072-discovery.o" +".\flash\led_stm32f072-discovery.o" +"C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\LIB\ARM\RTX_CM0.lib" +".\flash\rtx_conf_cm.o" +".\flash\startup_stm32f072xb.o" +".\flash\system_stm32f0xx.o" +--library_type=microlib --strict --scatter ".\Flash\RTX_Blinky.sct" +--summary_stderr --info summarysizes --map --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\Flash\RTX_Blinky.map" -o .\Flash\RTX_Blinky.axf \ No newline at end of file diff --git a/RTX_Blinky/Flash/RTX_Blinky.map b/RTX_Blinky/Flash/RTX_Blinky.map new file mode 100644 index 0000000..446460e --- /dev/null +++ b/RTX_Blinky/Flash/RTX_Blinky.map @@ -0,0 +1,1186 @@ +Component: ARM Compiler 5.06 update 1 (build 61) Tool: armlink [4d35a8] + +============================================================================== + +Section Cross References + + rtx_blinky.o(.text) refers to led_stm32f072-discovery.o(.text) for LED_GetCount + rtx_blinky.o(.text) refers to rt_cmsis.o(i.osSignalWait) for osSignalWait + rtx_blinky.o(.text) refers to buttons_stm32f072-discovery.o(.text) for Buttons_GetCount + rtx_blinky.o(.text) refers to rt_cmsis.o(i.osKernelInitialize) for osKernelInitialize + rtx_blinky.o(.text) refers to system_stm32f0xx.o(.text) for SystemCoreClockUpdate + rtx_blinky.o(.text) refers to rt_cmsis.o(i.osThreadCreate) for osThreadCreate + rtx_blinky.o(.text) refers to rt_cmsis.o(i.osKernelStart) for osKernelStart + rtx_blinky.o(.text) refers to dac_drv.o(.text) for DAC_init + rtx_blinky.o(.text) refers to rtx_blinky.o(.constdata) for os_thread_def_blinkLED + rtx_blinky.o(.text) refers to rtx_blinky.o(.data) for tid_blinkLED + rtx_blinky.o(.text) refers to rtx_blinky.o(.bss) for DAC_value2 + rtx_blinky.o(.constdata) refers to rtx_blinky.o(.text) for blinkLED + led_stm32f072-discovery.o(.text) refers to led_stm32f072-discovery.o(.constdata) for led_mask + rtx_conf_cm.o(.ARM.Collect$$$$000000FF) refers to rt_cmsis.o(i.osKernelInitialize) for osKernelInitialize + rtx_conf_cm.o(.ARM.Collect$$$$000000FF) refers to rt_cmsis.o(i.osThreadCreate) for osThreadCreate + rtx_conf_cm.o(.ARM.Collect$$$$000000FF) refers to rt_cmsis.o(i.osKernelStart) for osKernelStart + rtx_conf_cm.o(.ARM.Collect$$$$000000FF) refers to rtx_conf_cm.o(.data) for .data + rtx_conf_cm.o(.constdata) refers to rt_cmsis.o(i.osTimerThread) for osTimerThread + rtx_conf_cm.o(.constdata) refers to rtx_conf_cm.o(.bss) for os_messageQ_q_osTimerMessageQ + rtx_conf_cm.o(.data) refers to rtx_blinky.o(.text) for main + startup_stm32f072xb.o(RESET) refers to startup_stm32f072xb.o(STACK) for __initial_sp + startup_stm32f072xb.o(RESET) refers to startup_stm32f072xb.o(.text) for Reset_Handler + startup_stm32f072xb.o(RESET) refers to hal_cm0.o(.emb_text) for SVC_Handler + startup_stm32f072xb.o(.text) refers to system_stm32f0xx.o(.text) for SystemInit + startup_stm32f072xb.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main + system_stm32f0xx.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod + system_stm32f0xx.o(.text) refers to system_stm32f0xx.o(.data) for SystemCoreClock + system_stm32f0xx.o(.text) refers to system_stm32f0xx.o(.constdata) for AHBPrescTable + rt_cmsis.o(i.isrMessageGet) refers to rt_mailbox.o(i.isr_mbx_receive) for isr_mbx_receive + rt_cmsis.o(i.isrMessagePut) refers to rt_mailbox.o(i.rt_mbx_check) for rt_mbx_check + rt_cmsis.o(i.isrMessagePut) refers to rt_mailbox.o(i.isr_mbx_send) for isr_mbx_send + rt_cmsis.o(i.isrSemaphoreRelease) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.isrSemaphoreRelease) refers to rt_semaphore.o(i.isr_sem_send) for isr_sem_send + rt_cmsis.o(i.isrSignalSet) refers to rt_cmsis.o(i.rt_tid2ptcb) for rt_tid2ptcb + rt_cmsis.o(i.isrSignalSet) refers to rt_event.o(i.isr_evt_set) for isr_evt_set + rt_cmsis.o(i.osDelay) refers to rt_cmsis.o(i.svcDelay) for svcDelay + rt_cmsis.o(i.osKernelInitialize) refers to rt_cmsis.o(i.svcKernelInitialize) for svcKernelInitialize + rt_cmsis.o(i.osKernelRunning) refers to rt_cmsis.o(i.svcKernelRunning) for svcKernelRunning + rt_cmsis.o(i.osKernelRunning) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.osKernelStart) refers to rtx_conf_cm.o(.constdata) for os_flags + rt_cmsis.o(i.osKernelStart) refers to rt_cmsis.o(i.svcKernelStart) for svcKernelStart + rt_cmsis.o(i.osKernelSysTick) refers to rt_cmsis.o(i.svcKernelSysTick) for svcKernelSysTick + rt_cmsis.o(i.osMailAlloc) refers to rt_cmsis.o(i.sysMailAlloc) for sysMailAlloc + rt_cmsis.o(i.osMailCAlloc) refers to rt_cmsis.o(i.sysMailAlloc) for sysMailAlloc + rt_cmsis.o(i.osMailCAlloc) refers to rt_cmsis.o(i.rt_clr_box) for rt_clr_box + rt_cmsis.o(i.osMailCreate) refers to rt_cmsis.o(i.svcMailCreate) for svcMailCreate + rt_cmsis.o(i.osMailCreate) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.osMailFree) refers to rt_cmsis.o(i.sysMailFree) for sysMailFree + rt_cmsis.o(i.osMailGet) refers to rt_cmsis.o(i.osMessageGet) for osMessageGet + rt_cmsis.o(i.osMailPut) refers to rt_cmsis.o(i.osMessagePut) for osMessagePut + rt_cmsis.o(i.osMessageCreate) refers to rt_cmsis.o(i.svcMessageCreate) for svcMessageCreate + rt_cmsis.o(i.osMessageCreate) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.osMessageGet) refers to rt_cmsis.o(i.isrMessageGet) for isrMessageGet + rt_cmsis.o(i.osMessageGet) refers to rt_cmsis.o(i.svcMessageGet) for svcMessageGet + rt_cmsis.o(i.osMessagePut) refers to rt_cmsis.o(i.isrMessagePut) for isrMessagePut + rt_cmsis.o(i.osMessagePut) refers to rt_cmsis.o(i.svcMessagePut) for svcMessagePut + rt_cmsis.o(i.osMutexCreate) refers to rt_cmsis.o(i.svcMutexCreate) for svcMutexCreate + rt_cmsis.o(i.osMutexCreate) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.osMutexDelete) refers to rt_cmsis.o(i.svcMutexDelete) for svcMutexDelete + rt_cmsis.o(i.osMutexRelease) refers to rt_cmsis.o(i.svcMutexRelease) for svcMutexRelease + rt_cmsis.o(i.osMutexWait) refers to rt_cmsis.o(i.svcMutexWait) for svcMutexWait + rt_cmsis.o(i.osPoolAlloc) refers to rt_cmsis.o(i.sysPoolAlloc) for sysPoolAlloc + rt_cmsis.o(i.osPoolCAlloc) refers to rt_cmsis.o(i.rt_clr_box) for rt_clr_box + rt_cmsis.o(i.osPoolCAlloc) refers to rt_cmsis.o(i.sysPoolAlloc) for sysPoolAlloc + rt_cmsis.o(i.osPoolCreate) refers to rt_cmsis.o(i.svcPoolCreate) for svcPoolCreate + rt_cmsis.o(i.osPoolCreate) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.osPoolFree) refers to rt_cmsis.o(i.sysPoolFree) for sysPoolFree + rt_cmsis.o(i.osSemaphoreCreate) refers to rt_cmsis.o(i.svcSemaphoreCreate) for svcSemaphoreCreate + rt_cmsis.o(i.osSemaphoreCreate) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.osSemaphoreDelete) refers to rt_cmsis.o(i.svcSemaphoreDelete) for svcSemaphoreDelete + rt_cmsis.o(i.osSemaphoreRelease) refers to rt_cmsis.o(i.isrSemaphoreRelease) for isrSemaphoreRelease + rt_cmsis.o(i.osSemaphoreRelease) refers to rt_cmsis.o(i.svcSemaphoreRelease) for svcSemaphoreRelease + rt_cmsis.o(i.osSemaphoreWait) refers to rt_cmsis.o(i.svcSemaphoreWait) for svcSemaphoreWait + rt_cmsis.o(i.osSignalClear) refers to rt_cmsis.o(i.svcSignalClear) for svcSignalClear + rt_cmsis.o(i.osSignalSet) refers to rt_cmsis.o(i.isrSignalSet) for isrSignalSet + rt_cmsis.o(i.osSignalSet) refers to rt_cmsis.o(i.svcSignalSet) for svcSignalSet + rt_cmsis.o(i.osSignalWait) refers to rt_cmsis.o(i.svcSignalWait) for svcSignalWait + rt_cmsis.o(i.osThreadCreate) refers to rt_cmsis.o(i.svcThreadCreate) for svcThreadCreate + rt_cmsis.o(i.osThreadCreate) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.osThreadExit) refers to rt_cmsis.o(i.svcThreadGetId) for svcThreadGetId + rt_cmsis.o(i.osThreadExit) refers to rt_cmsis.o(i.svcThreadTerminate) for svcThreadTerminate + rt_cmsis.o(i.osThreadGetId) refers to rt_cmsis.o(i.svcThreadGetId) for svcThreadGetId + rt_cmsis.o(i.osThreadGetPriority) refers to rt_cmsis.o(i.svcThreadGetPriority) for svcThreadGetPriority + rt_cmsis.o(i.osThreadSetPriority) refers to rt_cmsis.o(i.svcThreadSetPriority) for svcThreadSetPriority + rt_cmsis.o(i.osThreadTerminate) refers to rt_cmsis.o(i.svcThreadTerminate) for svcThreadTerminate + rt_cmsis.o(i.osThreadYield) refers to rt_cmsis.o(i.svcThreadYield) for svcThreadYield + rt_cmsis.o(i.osTimerCall) refers to rt_cmsis.o(i.svcTimerCall) for svcTimerCall + rt_cmsis.o(i.osTimerCreate) refers to rt_cmsis.o(i.svcTimerCreate) for svcTimerCreate + rt_cmsis.o(i.osTimerCreate) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.osTimerDelete) refers to rt_cmsis.o(i.svcTimerDelete) for svcTimerDelete + rt_cmsis.o(i.osTimerStart) refers to rt_cmsis.o(i.svcTimerStart) for svcTimerStart + rt_cmsis.o(i.osTimerStop) refers to rt_cmsis.o(i.svcTimerStop) for svcTimerStop + rt_cmsis.o(i.osTimerThread) refers to rt_cmsis.o(i.osMessageGet) for osMessageGet + rt_cmsis.o(i.osTimerThread) refers to rt_cmsis.o(i.osTimerCall) for osTimerCall + rt_cmsis.o(i.osTimerThread) refers to rtx_conf_cm.o(.data) for osMessageQId_osTimerMessageQ + rt_cmsis.o(i.os_resume) refers to rt_system.o(i.rt_resume) for rt_resume + rt_cmsis.o(i.os_suspend) refers to rt_system.o(i.rt_suspend) for rt_suspend + rt_cmsis.o(i.rt_ms2tick) refers to uidiv.o(.text) for __aeabi_uidivmod + rt_cmsis.o(i.rt_ms2tick) refers to rtx_conf_cm.o(.constdata) for os_clockrate + rt_cmsis.o(i.rt_timer_insert) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.rt_timer_remove) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.svcDelay) refers to rt_cmsis.o(i.rt_ms2tick) for rt_ms2tick + rt_cmsis.o(i.svcDelay) refers to rt_time.o(i.rt_dly_wait) for rt_dly_wait + rt_cmsis.o(i.svcKernelInitialize) refers to rt_memory.o(i.rt_init_mem) for rt_init_mem + rt_cmsis.o(i.svcKernelInitialize) refers to rt_task.o(i.rt_sys_init) for rt_sys_init + rt_cmsis.o(i.svcKernelInitialize) refers to rt_cmsis.o(i.svcMessageCreate) for svcMessageCreate + rt_cmsis.o(i.svcKernelInitialize) refers to rt_cmsis.o(i.svcThreadCreate) for svcThreadCreate + rt_cmsis.o(i.svcKernelInitialize) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.svcKernelInitialize) refers to rtx_conf_cm.o(.bss) for os_stack_mem + rt_cmsis.o(i.svcKernelInitialize) refers to rtx_conf_cm.o(.constdata) for os_stack_sz + rt_cmsis.o(i.svcKernelInitialize) refers to rt_task.o(.data) for os_tsk + rt_cmsis.o(i.svcKernelInitialize) refers to rtx_conf_cm.o(.data) for osMessageQId_osTimerMessageQ + rt_cmsis.o(i.svcKernelRunning) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.svcKernelStart) refers to rt_task.o(i.rt_tsk_prio) for rt_tsk_prio + rt_cmsis.o(i.svcKernelStart) refers to rt_task.o(i.rt_sys_start) for rt_sys_start + rt_cmsis.o(i.svcKernelStart) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.svcKernelStart) refers to rt_task.o(.data) for os_tsk + rt_cmsis.o(i.svcKernelSysTick) refers to rt_system.o(i.os_tick_val) for os_tick_val + rt_cmsis.o(i.svcKernelSysTick) refers to rt_system.o(i.os_tick_ovf) for os_tick_ovf + rt_cmsis.o(i.svcKernelSysTick) refers to rtx_conf_cm.o(.constdata) for os_trv + rt_cmsis.o(i.svcKernelSysTick) refers to rt_time.o(.data) for os_time + rt_cmsis.o(i.svcMailCreate) refers to rt_membox.o(i._init_box) for _init_box + rt_cmsis.o(i.svcMailCreate) refers to rt_mailbox.o(i.rt_mbx_init) for rt_mbx_init + rt_cmsis.o(i.svcMessageCreate) refers to rt_mailbox.o(i.rt_mbx_init) for rt_mbx_init + rt_cmsis.o(i.svcMessageGet) refers to rt_cmsis.o(i.rt_ms2tick) for rt_ms2tick + rt_cmsis.o(i.svcMessageGet) refers to rt_mailbox.o(i.rt_mbx_wait) for rt_mbx_wait + rt_cmsis.o(i.svcMessagePut) refers to rt_cmsis.o(i.rt_ms2tick) for rt_ms2tick + rt_cmsis.o(i.svcMessagePut) refers to rt_mailbox.o(i.rt_mbx_send) for rt_mbx_send + rt_cmsis.o(i.svcMutexCreate) refers to rt_mutex.o(i.rt_mut_init) for rt_mut_init + rt_cmsis.o(i.svcMutexDelete) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcMutexDelete) refers to rt_mutex.o(i.rt_mut_delete) for rt_mut_delete + rt_cmsis.o(i.svcMutexRelease) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcMutexRelease) refers to rt_mutex.o(i.rt_mut_release) for rt_mut_release + rt_cmsis.o(i.svcMutexWait) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcMutexWait) refers to rt_cmsis.o(i.rt_ms2tick) for rt_ms2tick + rt_cmsis.o(i.svcMutexWait) refers to rt_mutex.o(i.rt_mut_wait) for rt_mut_wait + rt_cmsis.o(i.svcPoolCreate) refers to rt_membox.o(i._init_box) for _init_box + rt_cmsis.o(i.svcSemaphoreCreate) refers to rt_semaphore.o(i.rt_sem_init) for rt_sem_init + rt_cmsis.o(i.svcSemaphoreDelete) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcSemaphoreDelete) refers to rt_semaphore.o(i.rt_sem_delete) for rt_sem_delete + rt_cmsis.o(i.svcSemaphoreRelease) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcSemaphoreRelease) refers to rt_semaphore.o(i.rt_sem_send) for rt_sem_send + rt_cmsis.o(i.svcSemaphoreWait) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcSemaphoreWait) refers to rt_cmsis.o(i.rt_ms2tick) for rt_ms2tick + rt_cmsis.o(i.svcSemaphoreWait) refers to rt_semaphore.o(i.rt_sem_wait) for rt_sem_wait + rt_cmsis.o(i.svcSignalClear) refers to rt_cmsis.o(i.rt_tid2ptcb) for rt_tid2ptcb + rt_cmsis.o(i.svcSignalClear) refers to rt_event.o(i.rt_evt_clr) for rt_evt_clr + rt_cmsis.o(i.svcSignalSet) refers to rt_cmsis.o(i.rt_tid2ptcb) for rt_tid2ptcb + rt_cmsis.o(i.svcSignalSet) refers to rt_event.o(i.rt_evt_set) for rt_evt_set + rt_cmsis.o(i.svcSignalWait) refers to rt_cmsis.o(i.rt_ms2tick) for rt_ms2tick + rt_cmsis.o(i.svcSignalWait) refers to rt_event.o(i.rt_evt_wait) for rt_evt_wait + rt_cmsis.o(i.svcSignalWait) refers to rt_task.o(.data) for os_tsk + rt_cmsis.o(i.svcThreadCreate) refers to rt_memory.o(i.rt_alloc_mem) for rt_alloc_mem + rt_cmsis.o(i.svcThreadCreate) refers to rt_task.o(i.rt_tsk_create) for rt_tsk_create + rt_cmsis.o(i.svcThreadCreate) refers to rt_memory.o(i.rt_free_mem) for rt_free_mem + rt_cmsis.o(i.svcThreadCreate) refers to rtx_conf_cm.o(.bss) for os_stack_mem + rt_cmsis.o(i.svcThreadCreate) refers to rt_cmsis.o(i.osThreadExit) for osThreadExit + rt_cmsis.o(i.svcThreadGetId) refers to rt_task.o(i.rt_tsk_self) for rt_tsk_self + rt_cmsis.o(i.svcThreadGetId) refers to rtx_conf_cm.o(.bss) for os_active_TCB + rt_cmsis.o(i.svcThreadGetPriority) refers to rt_cmsis.o(i.rt_tid2ptcb) for rt_tid2ptcb + rt_cmsis.o(i.svcThreadSetPriority) refers to rt_cmsis.o(i.rt_tid2ptcb) for rt_tid2ptcb + rt_cmsis.o(i.svcThreadSetPriority) refers to rt_task.o(i.rt_tsk_prio) for rt_tsk_prio + rt_cmsis.o(i.svcThreadTerminate) refers to rt_cmsis.o(i.rt_tid2ptcb) for rt_tid2ptcb + rt_cmsis.o(i.svcThreadTerminate) refers to rt_task.o(i.rt_tsk_delete) for rt_tsk_delete + rt_cmsis.o(i.svcThreadTerminate) refers to rt_memory.o(i.rt_free_mem) for rt_free_mem + rt_cmsis.o(i.svcThreadTerminate) refers to rtx_conf_cm.o(.bss) for os_stack_mem + rt_cmsis.o(i.svcThreadYield) refers to rt_task.o(i.rt_tsk_pass) for rt_tsk_pass + rt_cmsis.o(i.svcTimerCall) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcTimerCreate) refers to rtx_conf_cm.o(.data) for osThreadId_osTimerThread + rt_cmsis.o(i.svcTimerDelete) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcTimerDelete) refers to rt_cmsis.o(i.rt_timer_remove) for rt_timer_remove + rt_cmsis.o(i.svcTimerStart) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcTimerStart) refers to rt_cmsis.o(i.__ARM_common_ll_muluu) for __ARM_common_ll_muluu + rt_cmsis.o(i.svcTimerStart) refers to uldiv.o(.text) for __aeabi_uldivmod + rt_cmsis.o(i.svcTimerStart) refers to rt_cmsis.o(i.rt_timer_remove) for rt_timer_remove + rt_cmsis.o(i.svcTimerStart) refers to rt_cmsis.o(i.rt_timer_insert) for rt_timer_insert + rt_cmsis.o(i.svcTimerStart) refers to rtx_conf_cm.o(.constdata) for os_clockrate + rt_cmsis.o(i.svcTimerStop) refers to rt_cmsis.o(i.rt_id2obj) for rt_id2obj + rt_cmsis.o(i.svcTimerStop) refers to rt_cmsis.o(i.rt_timer_remove) for rt_timer_remove + rt_cmsis.o(i.sysMailAlloc) refers to rt_membox.o(i.rt_alloc_box) for rt_alloc_box + rt_cmsis.o(i.sysMailAlloc) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_cmsis.o(i.sysMailAlloc) refers to rt_cmsis.o(i.rt_ms2tick) for rt_ms2tick + rt_cmsis.o(i.sysMailAlloc) refers to rt_task.o(i.rt_block) for rt_block + rt_cmsis.o(i.sysMailAlloc) refers to rt_task.o(.data) for os_tsk + rt_cmsis.o(i.sysMailFree) refers to rt_membox.o(i.rt_free_box) for rt_free_box + rt_cmsis.o(i.sysMailFree) refers to rt_list.o(i.rt_psq_enq) for rt_psq_enq + rt_cmsis.o(i.sysMailFree) refers to rt_system.o(i.rt_psh_req) for rt_psh_req + rt_cmsis.o(i.sysMailFree) refers to rt_membox.o(i.rt_alloc_box) for rt_alloc_box + rt_cmsis.o(i.sysMailFree) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_cmsis.o(i.sysMailFree) refers to hal_cm.o(i.rt_ret_val) for rt_ret_val + rt_cmsis.o(i.sysMailFree) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_cmsis.o(i.sysMailFree) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_cmsis.o(i.sysPoolAlloc) refers to rt_membox.o(i.rt_alloc_box) for rt_alloc_box + rt_cmsis.o(i.sysPoolFree) refers to rt_membox.o(i.rt_free_box) for rt_free_box + rt_cmsis.o(i.sysTimerTick) refers to rt_cmsis.o(i.isrMessagePut) for isrMessagePut + rt_cmsis.o(i.sysTimerTick) refers to rtx_conf_cm.o(.text) for os_error + rt_cmsis.o(i.sysTimerTick) refers to rt_cmsis.o(i.rt_timer_insert) for rt_timer_insert + rt_cmsis.o(i.sysTimerTick) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.sysTimerTick) refers to rtx_conf_cm.o(.data) for osMessageQId_osTimerMessageQ + rt_cmsis.o(i.sysUserTimerUpdate) refers to rt_cmsis.o(i.sysTimerTick) for sysTimerTick + rt_cmsis.o(i.sysUserTimerUpdate) refers to rt_cmsis.o(.data) for .data + rt_cmsis.o(i.sysUserTimerWakeupTime) refers to rt_cmsis.o(.data) for .data + rt_task.o(i.rt_block) refers to rt_list.o(i.rt_put_dly) for rt_put_dly + rt_task.o(i.rt_block) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_task.o(i.rt_block) refers to rt_task.o(i.rt_switch_req) for rt_switch_req + rt_task.o(i.rt_block) refers to rt_task.o(.data) for .data + rt_task.o(i.rt_block) refers to rt_list.o(.bss) for os_rdy + rt_task.o(i.rt_dispatch) refers to rt_list.o(i.rt_put_rdy_first) for rt_put_rdy_first + rt_task.o(i.rt_dispatch) refers to rt_task.o(i.rt_switch_req) for rt_switch_req + rt_task.o(i.rt_dispatch) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_task.o(i.rt_dispatch) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_task.o(i.rt_dispatch) refers to rt_task.o(.data) for .data + rt_task.o(i.rt_dispatch) refers to rt_list.o(.bss) for os_rdy + rt_task.o(i.rt_init_context) refers to rt_membox.o(i.rt_alloc_box) for rt_alloc_box + rt_task.o(i.rt_init_context) refers to hal_cm.o(i.rt_init_stack) for rt_init_stack + rt_task.o(i.rt_init_context) refers to rtx_conf_cm.o(.bss) for mp_stk + rt_task.o(i.rt_switch_req) refers to rt_task.o(.data) for .data + rt_task.o(i.rt_sys_init) refers to rt_membox.o(i._init_box) for _init_box + rt_task.o(i.rt_sys_init) refers to rt_task.o(i.rt_init_context) for rt_init_context + rt_task.o(i.rt_sys_init) refers to rt_robin.o(i.rt_init_robin) for rt_init_robin + rt_task.o(i.rt_sys_init) refers to rtx_conf_cm.o(.bss) for os_active_TCB + rt_task.o(i.rt_sys_init) refers to rtx_conf_cm.o(.constdata) for os_maxtaskrun + rt_task.o(i.rt_sys_init) refers to rtx_conf_cm.o(.data) for m_tmr + rt_task.o(i.rt_sys_init) refers to rt_task.o(.bss) for .bss + rt_task.o(i.rt_sys_init) refers to rtx_conf_cm.o(.text) for os_idle_demon + rt_task.o(i.rt_sys_init) refers to rt_list.o(.bss) for os_rdy + rt_task.o(i.rt_sys_init) refers to rt_task.o(.data) for .data + rt_task.o(i.rt_sys_start) refers to rt_system.o(i.os_tick_init) for os_tick_init + rt_task.o(i.rt_sys_start) refers to rt_system.o(.data) for os_tick_irqn + rt_task.o(i.rt_tsk_create) refers to rt_membox.o(i.rt_alloc_box) for rt_alloc_box + rt_task.o(i.rt_tsk_create) refers to rt_task.o(i.rt_init_context) for rt_init_context + rt_task.o(i.rt_tsk_create) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_task.o(i.rt_tsk_create) refers to rtx_conf_cm.o(.bss) for mp_tcb + rt_task.o(i.rt_tsk_create) refers to rtx_conf_cm.o(.constdata) for os_maxtaskrun + rt_task.o(i.rt_tsk_delete) refers to hal_cm0.o(.emb_text) for rt_get_PSP + rt_task.o(i.rt_tsk_delete) refers to rt_system.o(i.rt_stk_check) for rt_stk_check + rt_task.o(i.rt_tsk_delete) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_task.o(i.rt_tsk_delete) refers to hal_cm.o(i.rt_ret_val) for rt_ret_val + rt_task.o(i.rt_tsk_delete) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_task.o(i.rt_tsk_delete) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_task.o(i.rt_tsk_delete) refers to rt_membox.o(i.rt_free_box) for rt_free_box + rt_task.o(i.rt_tsk_delete) refers to rt_list.o(i.rt_rmv_list) for rt_rmv_list + rt_task.o(i.rt_tsk_delete) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_task.o(i.rt_tsk_delete) refers to rt_task.o(.data) for .data + rt_task.o(i.rt_tsk_delete) refers to rt_list.o(.bss) for os_rdy + rt_task.o(i.rt_tsk_delete) refers to rtx_conf_cm.o(.bss) for os_active_TCB + rt_task.o(i.rt_tsk_delete) refers to rtx_conf_cm.o(.constdata) for os_maxtaskrun + rt_task.o(i.rt_tsk_pass) refers to rt_list.o(i.rt_get_same_rdy_prio) for rt_get_same_rdy_prio + rt_task.o(i.rt_tsk_pass) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_task.o(i.rt_tsk_pass) refers to rt_task.o(i.rt_switch_req) for rt_switch_req + rt_task.o(i.rt_tsk_pass) refers to rt_task.o(.data) for .data + rt_task.o(i.rt_tsk_pass) refers to rt_list.o(.bss) for os_rdy + rt_task.o(i.rt_tsk_prio) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_task.o(i.rt_tsk_prio) refers to rt_list.o(i.rt_resort_prio) for rt_resort_prio + rt_task.o(i.rt_tsk_prio) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_task.o(i.rt_tsk_prio) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_task.o(i.rt_tsk_prio) refers to rt_task.o(.data) for .data + rt_task.o(i.rt_tsk_prio) refers to rtx_conf_cm.o(.constdata) for os_maxtaskrun + rt_task.o(i.rt_tsk_prio) refers to rtx_conf_cm.o(.bss) for os_active_TCB + rt_task.o(i.rt_tsk_prio) refers to rt_list.o(.bss) for os_rdy + rt_task.o(i.rt_tsk_self) refers to rt_task.o(.data) for .data + rt_system.o(i.os_tick_init) refers to rtx_conf_cm.o(.constdata) for os_trv + rt_system.o(i.os_tick_val) refers to rtx_conf_cm.o(.constdata) for os_trv + rt_system.o(i.rt_pop_req) refers to rt_list.o(i.rt_put_rdy_first) for rt_put_rdy_first + rt_system.o(i.rt_pop_req) refers to rt_semaphore.o(i.rt_sem_psh) for rt_sem_psh + rt_system.o(i.rt_pop_req) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_system.o(i.rt_pop_req) refers to rt_task.o(i.rt_switch_req) for rt_switch_req + rt_system.o(i.rt_pop_req) refers to rt_event.o(i.rt_evt_psh) for rt_evt_psh + rt_system.o(i.rt_pop_req) refers to rt_mailbox.o(i.rt_mbx_psh) for rt_mbx_psh + rt_system.o(i.rt_pop_req) refers to rt_task.o(.data) for os_tsk + rt_system.o(i.rt_pop_req) refers to rtx_conf_cm.o(.bss) for os_fifo + rt_system.o(i.rt_pop_req) refers to rt_list.o(.bss) for os_rdy + rt_system.o(i.rt_psh_req) refers to rt_system.o(.data) for .data + rt_system.o(i.rt_resume) refers to rt_list.o(i.rt_put_rdy_first) for rt_put_rdy_first + rt_system.o(i.rt_resume) refers to rt_list.o(i.rt_dec_dly) for rt_dec_dly + rt_system.o(i.rt_resume) refers to rt_cmsis.o(i.sysUserTimerUpdate) for sysUserTimerUpdate + rt_system.o(i.rt_resume) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_system.o(i.rt_resume) refers to rt_task.o(i.rt_switch_req) for rt_switch_req + rt_system.o(i.rt_resume) refers to rt_system.o(i.rt_tsk_unlock) for rt_tsk_unlock + rt_system.o(i.rt_resume) refers to rt_task.o(.data) for os_tsk + rt_system.o(i.rt_resume) refers to rt_robin.o(.data) for os_robin + rt_system.o(i.rt_resume) refers to rt_list.o(.bss) for os_dly + rt_system.o(i.rt_resume) refers to rt_time.o(.data) for os_time + rt_system.o(i.rt_stk_check) refers to rtx_conf_cm.o(.text) for os_error + rt_system.o(i.rt_stk_check) refers to rt_task.o(.data) for os_tsk + rt_system.o(i.rt_suspend) refers to rt_system.o(i.rt_tsk_lock) for rt_tsk_lock + rt_system.o(i.rt_suspend) refers to rt_cmsis.o(i.sysUserTimerWakeupTime) for sysUserTimerWakeupTime + rt_system.o(i.rt_suspend) refers to rt_list.o(.bss) for os_dly + rt_system.o(i.rt_systick) refers to rt_list.o(i.rt_put_rdy_first) for rt_put_rdy_first + rt_system.o(i.rt_systick) refers to rt_robin.o(i.rt_chk_robin) for rt_chk_robin + rt_system.o(i.rt_systick) refers to rt_list.o(i.rt_dec_dly) for rt_dec_dly + rt_system.o(i.rt_systick) refers to rt_cmsis.o(i.sysTimerTick) for sysTimerTick + rt_system.o(i.rt_systick) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_system.o(i.rt_systick) refers to rt_task.o(i.rt_switch_req) for rt_switch_req + rt_system.o(i.rt_systick) refers to rt_task.o(.data) for os_tsk + rt_system.o(i.rt_systick) refers to rt_time.o(.data) for os_time + rt_system.o(i.rt_systick) refers to rt_list.o(.bss) for os_rdy + rt_system.o(i.rt_tsk_lock) refers to rt_system.o(.data) for .data + rt_system.o(i.rt_tsk_unlock) refers to rt_system.o(.data) for .data + rt_event.o(i.isr_evt_set) refers to rt_list.o(i.rt_psq_enq) for rt_psq_enq + rt_event.o(i.isr_evt_set) refers to rt_system.o(i.rt_psh_req) for rt_psh_req + rt_event.o(i.isr_evt_set) refers to rtx_conf_cm.o(.bss) for os_active_TCB + rt_event.o(i.rt_evt_clr) refers to rtx_conf_cm.o(.bss) for os_active_TCB + rt_event.o(i.rt_evt_get) refers to rt_task.o(.data) for os_tsk + rt_event.o(i.rt_evt_psh) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_event.o(i.rt_evt_psh) refers to hal_cm.o(i.rt_ret_val2) for rt_ret_val2 + rt_event.o(i.rt_evt_psh) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_event.o(i.rt_evt_psh) refers to rt_list.o(.bss) for os_rdy + rt_event.o(i.rt_evt_set) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_event.o(i.rt_evt_set) refers to hal_cm.o(i.rt_ret_val2) for rt_ret_val2 + rt_event.o(i.rt_evt_set) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_event.o(i.rt_evt_set) refers to rtx_conf_cm.o(.bss) for os_active_TCB + rt_event.o(i.rt_evt_wait) refers to rt_task.o(i.rt_block) for rt_block + rt_event.o(i.rt_evt_wait) refers to rt_task.o(.data) for os_tsk + rt_list.o(i.rt_dec_dly) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_list.o(i.rt_dec_dly) refers to rt_list.o(.bss) for .bss + rt_list.o(i.rt_dec_dly) refers to rt_time.o(.data) for os_time + rt_list.o(i.rt_get_same_rdy_prio) refers to rt_list.o(.bss) for .bss + rt_list.o(i.rt_get_same_rdy_prio) refers to rt_task.o(.data) for os_tsk + rt_list.o(i.rt_psq_enq) refers to rtx_conf_cm.o(.text) for os_error + rt_list.o(i.rt_psq_enq) refers to rtx_conf_cm.o(.bss) for os_fifo + rt_list.o(i.rt_put_dly) refers to rt_list.o(.bss) for .bss + rt_list.o(i.rt_put_rdy_first) refers to rt_list.o(.bss) for .bss + rt_list.o(i.rt_resort_prio) refers to rt_list.o(i.rt_rmv_list) for rt_rmv_list + rt_list.o(i.rt_resort_prio) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_list.o(i.rt_resort_prio) refers to rt_list.o(.bss) for .bss + rt_list.o(i.rt_rmv_list) refers to rt_list.o(.bss) for .bss + rt_mailbox.o(i.isr_mbx_receive) refers to rt_list.o(i.rt_psq_enq) for rt_psq_enq + rt_mailbox.o(i.isr_mbx_receive) refers to rt_system.o(i.rt_psh_req) for rt_psh_req + rt_mailbox.o(i.isr_mbx_send) refers to rt_list.o(i.rt_psq_enq) for rt_psq_enq + rt_mailbox.o(i.isr_mbx_send) refers to rt_system.o(i.rt_psh_req) for rt_psh_req + rt_mailbox.o(i.rt_mbx_psh) refers to rt_membox.o(i.rt_alloc_box) for rt_alloc_box + rt_mailbox.o(i.rt_mbx_psh) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_mailbox.o(i.rt_mbx_psh) refers to hal_cm.o(i.rt_ret_val) for rt_ret_val + rt_mailbox.o(i.rt_mbx_psh) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_mailbox.o(i.rt_mbx_psh) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_mailbox.o(i.rt_mbx_psh) refers to hal_cm.o(i.rt_ret_val2) for rt_ret_val2 + rt_mailbox.o(i.rt_mbx_psh) refers to rtx_conf_cm.o(.text) for os_error + rt_mailbox.o(i.rt_mbx_psh) refers to rt_list.o(.bss) for os_rdy + rt_mailbox.o(i.rt_mbx_send) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_mailbox.o(i.rt_mbx_send) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_mailbox.o(i.rt_mbx_send) refers to hal_cm.o(i.rt_ret_val2) for rt_ret_val2 + rt_mailbox.o(i.rt_mbx_send) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_mailbox.o(i.rt_mbx_send) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_mailbox.o(i.rt_mbx_send) refers to rt_task.o(i.rt_block) for rt_block + rt_mailbox.o(i.rt_mbx_send) refers to rt_task.o(.data) for os_tsk + rt_mailbox.o(i.rt_mbx_wait) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_mailbox.o(i.rt_mbx_wait) refers to hal_cm.o(i.rt_ret_val) for rt_ret_val + rt_mailbox.o(i.rt_mbx_wait) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_mailbox.o(i.rt_mbx_wait) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_mailbox.o(i.rt_mbx_wait) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_mailbox.o(i.rt_mbx_wait) refers to rt_task.o(i.rt_block) for rt_block + rt_mailbox.o(i.rt_mbx_wait) refers to rt_task.o(.data) for os_tsk + rt_semaphore.o(i.isr_sem_send) refers to rt_list.o(i.rt_psq_enq) for rt_psq_enq + rt_semaphore.o(i.isr_sem_send) refers to rt_system.o(i.rt_psh_req) for rt_psh_req + rt_semaphore.o(i.rt_sem_delete) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_semaphore.o(i.rt_sem_delete) refers to hal_cm.o(i.rt_ret_val) for rt_ret_val + rt_semaphore.o(i.rt_sem_delete) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_semaphore.o(i.rt_sem_delete) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_semaphore.o(i.rt_sem_delete) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_semaphore.o(i.rt_sem_delete) refers to rt_list.o(.bss) for os_rdy + rt_semaphore.o(i.rt_sem_delete) refers to rt_task.o(.data) for os_tsk + rt_semaphore.o(i.rt_sem_psh) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_semaphore.o(i.rt_sem_psh) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_semaphore.o(i.rt_sem_psh) refers to hal_cm.o(i.rt_ret_val) for rt_ret_val + rt_semaphore.o(i.rt_sem_psh) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_semaphore.o(i.rt_sem_psh) refers to rt_list.o(.bss) for os_rdy + rt_semaphore.o(i.rt_sem_send) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_semaphore.o(i.rt_sem_send) refers to hal_cm.o(i.rt_ret_val) for rt_ret_val + rt_semaphore.o(i.rt_sem_send) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_semaphore.o(i.rt_sem_send) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_semaphore.o(i.rt_sem_wait) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_semaphore.o(i.rt_sem_wait) refers to rt_task.o(i.rt_block) for rt_block + rt_semaphore.o(i.rt_sem_wait) refers to rt_task.o(.data) for os_tsk + rt_time.o(i.rt_dly_wait) refers to rt_task.o(i.rt_block) for rt_block + rt_time.o(i.rt_itv_set) refers to rt_task.o(.data) for os_tsk + rt_time.o(i.rt_itv_set) refers to rt_time.o(.data) for .data + rt_time.o(i.rt_itv_wait) refers to rt_task.o(i.rt_block) for rt_block + rt_time.o(i.rt_itv_wait) refers to rt_task.o(.data) for os_tsk + rt_time.o(i.rt_itv_wait) refers to rt_time.o(.data) for .data + rt_time.o(i.rt_time_get) refers to rt_time.o(.data) for .data + rt_mutex.o(i.rt_mut_delete) refers to rt_list.o(i.rt_resort_prio) for rt_resort_prio + rt_mutex.o(i.rt_mut_delete) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_mutex.o(i.rt_mut_delete) refers to hal_cm.o(i.rt_ret_val) for rt_ret_val + rt_mutex.o(i.rt_mut_delete) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_mutex.o(i.rt_mut_delete) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_mutex.o(i.rt_mut_delete) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_mutex.o(i.rt_mut_delete) refers to rt_task.o(.data) for os_tsk + rt_mutex.o(i.rt_mut_delete) refers to rt_list.o(.bss) for os_rdy + rt_mutex.o(i.rt_mut_release) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_mutex.o(i.rt_mut_release) refers to hal_cm.o(i.rt_ret_val) for rt_ret_val + rt_mutex.o(i.rt_mut_release) refers to rt_list.o(i.rt_rmv_dly) for rt_rmv_dly + rt_mutex.o(i.rt_mut_release) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_mutex.o(i.rt_mut_release) refers to rt_task.o(i.rt_dispatch) for rt_dispatch + rt_mutex.o(i.rt_mut_release) refers to rt_task.o(.data) for os_tsk + rt_mutex.o(i.rt_mut_release) refers to rt_list.o(.bss) for os_rdy + rt_mutex.o(i.rt_mut_wait) refers to rt_list.o(i.rt_resort_prio) for rt_resort_prio + rt_mutex.o(i.rt_mut_wait) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_mutex.o(i.rt_mut_wait) refers to rt_task.o(i.rt_block) for rt_block + rt_mutex.o(i.rt_mut_wait) refers to rt_task.o(.data) for os_tsk + rt_membox.o(i._calloc_box) refers to hal_cm0.o(.emb_text) for _alloc_box + hal_cm.o(i.rt_init_stack) refers to rtx_conf_cm.o(.constdata) for os_stackinfo + rt_robin.o(i.rt_chk_robin) refers to rt_list.o(i.rt_get_first) for rt_get_first + rt_robin.o(i.rt_chk_robin) refers to rt_list.o(i.rt_put_prio) for rt_put_prio + rt_robin.o(i.rt_chk_robin) refers to rt_robin.o(.data) for .data + rt_robin.o(i.rt_chk_robin) refers to rt_list.o(.bss) for os_rdy + rt_robin.o(i.rt_chk_robin) refers to rt_time.o(.data) for os_time + rt_robin.o(i.rt_init_robin) refers to rt_robin.o(.data) for .data + rt_robin.o(i.rt_init_robin) refers to rtx_conf_cm.o(.constdata) for os_rrobin + hal_cm0.o(.emb_text) refers to rtx_conf_cm.o(.constdata) for os_flags + hal_cm0.o(.emb_text) refers to rt_membox.o(i.rt_alloc_box) for rt_alloc_box + hal_cm0.o(.emb_text) refers to rt_membox.o(i.rt_free_box) for rt_free_box + hal_cm0.o(.emb_text) refers to rt_system.o(i.rt_stk_check) for rt_stk_check + hal_cm0.o(.emb_text) refers to rt_task.o(.data) for os_tsk + hal_cm0.o(.emb_text) refers to svc_table.o(SVC_TABLE) for SVC_Count + hal_cm0.o(.emb_text) refers to rt_system.o(i.rt_pop_req) for rt_pop_req + hal_cm0.o(.emb_text) refers to rt_system.o(i.rt_systick) for rt_systick + hal_cm0.o(.emb_text) refers to rt_system.o(i.os_tick_irqack) for os_tick_irqack + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to rtx_conf_cm.o(.ARM.Collect$$$$000000FF) for _main_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk + uldiv.o(.text) refers to llushr.o(.text) for __aeabi_llsr + uldiv.o(.text) refers to llshl.o(.text) for __aeabi_llsl + entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 + entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f072xb.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f072xb.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload + init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload + + +============================================================================== + +Removing Unused input sections from the image. + + Removing rtx_blinky.o(.rev16_text), (4 bytes). + Removing rtx_blinky.o(.revsh_text), (4 bytes). + Removing dac_drv.o(.rev16_text), (4 bytes). + Removing dac_drv.o(.revsh_text), (4 bytes). + Removing buttons_stm32f072-discovery.o(.rev16_text), (4 bytes). + Removing buttons_stm32f072-discovery.o(.revsh_text), (4 bytes). + Removing led_stm32f072-discovery.o(.rev16_text), (4 bytes). + Removing led_stm32f072-discovery.o(.revsh_text), (4 bytes). + Removing startup_stm32f072xb.o(HEAP), (512 bytes). + Removing system_stm32f0xx.o(.rev16_text), (4 bytes). + Removing system_stm32f0xx.o(.revsh_text), (4 bytes). + Removing rt_cmsis.o(.rev16_text), (4 bytes). + Removing rt_cmsis.o(.revsh_text), (4 bytes). + Removing rt_cmsis.o(i.isrSemaphoreRelease), (44 bytes). + Removing rt_cmsis.o(i.isrSignalSet), (38 bytes). + Removing rt_cmsis.o(i.osDelay), (28 bytes). + Removing rt_cmsis.o(i.osKernelRunning), (40 bytes). + Removing rt_cmsis.o(i.osKernelSysTick), (28 bytes). + Removing rt_cmsis.o(i.osMailAlloc), (32 bytes). + Removing rt_cmsis.o(i.osMailCAlloc), (52 bytes). + Removing rt_cmsis.o(i.osMailCreate), (52 bytes). + Removing rt_cmsis.o(i.osMailFree), (32 bytes). + Removing rt_cmsis.o(i.osMailGet), (24 bytes). + Removing rt_cmsis.o(i.osMailPut), (28 bytes). + Removing rt_cmsis.o(i.osMessageCreate), (52 bytes). + Removing rt_cmsis.o(i.osMessagePut), (28 bytes). + Removing rt_cmsis.o(i.osMutexCreate), (52 bytes). + Removing rt_cmsis.o(i.osMutexDelete), (28 bytes). + Removing rt_cmsis.o(i.osMutexRelease), (28 bytes). + Removing rt_cmsis.o(i.osMutexWait), (28 bytes). + Removing rt_cmsis.o(i.osPoolAlloc), (36 bytes). + Removing rt_cmsis.o(i.osPoolCAlloc), (56 bytes). + Removing rt_cmsis.o(i.osPoolCreate), (52 bytes). + Removing rt_cmsis.o(i.osPoolFree), (36 bytes). + Removing rt_cmsis.o(i.osSemaphoreCreate), (52 bytes). + Removing rt_cmsis.o(i.osSemaphoreDelete), (28 bytes). + Removing rt_cmsis.o(i.osSemaphoreRelease), (28 bytes). + Removing rt_cmsis.o(i.osSemaphoreWait), (28 bytes). + Removing rt_cmsis.o(i.osSignalClear), (28 bytes). + Removing rt_cmsis.o(i.osSignalSet), (28 bytes). + Removing rt_cmsis.o(i.osThreadGetId), (28 bytes). + Removing rt_cmsis.o(i.osThreadGetPriority), (28 bytes). + Removing rt_cmsis.o(i.osThreadSetPriority), (28 bytes). + Removing rt_cmsis.o(i.osThreadTerminate), (28 bytes). + Removing rt_cmsis.o(i.osThreadYield), (28 bytes). + Removing rt_cmsis.o(i.osTimerCreate), (52 bytes). + Removing rt_cmsis.o(i.osTimerDelete), (28 bytes). + Removing rt_cmsis.o(i.osTimerStart), (28 bytes). + Removing rt_cmsis.o(i.osTimerStop), (28 bytes). + Removing rt_cmsis.o(i.osWait), (4 bytes). + Removing rt_cmsis.o(i.os_resume), (16 bytes). + Removing rt_cmsis.o(i.os_suspend), (16 bytes). + Removing rt_cmsis.o(i.rt_clr_box), (26 bytes). + Removing rt_cmsis.o(i.rt_timer_remove), (68 bytes). + Removing rt_cmsis.o(i.svcDelay), (18 bytes). + Removing rt_cmsis.o(i.svcKernelRunning), (12 bytes). + Removing rt_cmsis.o(i.svcKernelSysTick), (56 bytes). + Removing rt_cmsis.o(i.svcMailCreate), (78 bytes). + Removing rt_cmsis.o(i.svcMessagePut), (56 bytes). + Removing rt_cmsis.o(i.svcMutexCreate), (32 bytes). + Removing rt_cmsis.o(i.svcMutexDelete), (28 bytes). + Removing rt_cmsis.o(i.svcMutexRelease), (36 bytes). + Removing rt_cmsis.o(i.svcMutexWait), (56 bytes). + Removing rt_cmsis.o(i.svcPoolCreate), (46 bytes). + Removing rt_cmsis.o(i.svcSemaphoreCreate), (44 bytes). + Removing rt_cmsis.o(i.svcSemaphoreDelete), (28 bytes). + Removing rt_cmsis.o(i.svcSemaphoreRelease), (44 bytes). + Removing rt_cmsis.o(i.svcSemaphoreWait), (52 bytes). + Removing rt_cmsis.o(i.svcSignalClear), (38 bytes). + Removing rt_cmsis.o(i.svcSignalSet), (38 bytes). + Removing rt_cmsis.o(i.svcThreadGetPriority), (20 bytes). + Removing rt_cmsis.o(i.svcThreadSetPriority), (48 bytes). + Removing rt_cmsis.o(i.svcThreadYield), (10 bytes). + Removing rt_cmsis.o(i.svcTimerCreate), (64 bytes). + Removing rt_cmsis.o(i.svcTimerDelete), (40 bytes). + Removing rt_cmsis.o(i.svcTimerStart), (108 bytes). + Removing rt_cmsis.o(i.svcTimerStop), (38 bytes). + Removing rt_cmsis.o(i.sysMailAlloc), (100 bytes). + Removing rt_cmsis.o(i.sysMailFree), (106 bytes). + Removing rt_cmsis.o(i.sysPoolAlloc), (12 bytes). + Removing rt_cmsis.o(i.sysPoolFree), (22 bytes). + Removing rt_cmsis.o(i.sysUserTimerUpdate), (48 bytes). + Removing rt_cmsis.o(i.sysUserTimerWakeupTime), (24 bytes). + Removing rt_task.o(i.rt_tsk_pass), (44 bytes). + Removing rt_system.o(.emb_text), (0 bytes). + Removing rt_system.o(i.os_tick_ovf), (16 bytes). + Removing rt_system.o(i.os_tick_val), (20 bytes). + Removing rt_system.o(i.rt_resume), (136 bytes). + Removing rt_system.o(i.rt_suspend), (40 bytes). + Removing rt_system.o(i.rt_tsk_lock), (84 bytes). + Removing rt_system.o(i.rt_tsk_unlock), (84 bytes). + Removing rt_event.o(i.isr_evt_set), (36 bytes). + Removing rt_event.o(i.rt_evt_clr), (28 bytes). + Removing rt_event.o(i.rt_evt_get), (12 bytes). + Removing rt_event.o(i.rt_evt_set), (92 bytes). + Removing rt_list.o(i.rt_get_same_rdy_prio), (36 bytes). + Removing rt_mailbox.o(i.rt_mbx_send), (148 bytes). + Removing rt_semaphore.o(i.isr_sem_send), (14 bytes). + Removing rt_semaphore.o(i.rt_sem_delete), (96 bytes). + Removing rt_semaphore.o(i.rt_sem_init), (12 bytes). + Removing rt_semaphore.o(i.rt_sem_send), (44 bytes). + Removing rt_semaphore.o(i.rt_sem_wait), (68 bytes). + Removing rt_time.o(i.rt_dly_wait), (10 bytes). + Removing rt_time.o(i.rt_itv_set), (24 bytes). + Removing rt_time.o(i.rt_itv_wait), (44 bytes). + Removing rt_time.o(i.rt_time_get), (12 bytes). + Removing rt_mutex.o(i.rt_mut_delete), (180 bytes). + Removing rt_mutex.o(i.rt_mut_init), (16 bytes). + Removing rt_mutex.o(i.rt_mut_release), (216 bytes). + Removing rt_mutex.o(i.rt_mut_wait), (112 bytes). + Removing rt_membox.o(i._calloc_box), (32 bytes). + Removing rt_cmsis.o(i.__ARM_common_ll_muluu), (48 bytes). + +112 unused section(s) (total 4958 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/../cmprslib/zerorunl.c 0x00000000 Number 0 __dczerorl.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE + ..\HAL_CM.c 0x00000000 Number 0 hal_cm.o ABSOLUTE + ..\\rt_CMSIS.c 0x00000000 Number 0 rt_cmsis.o ABSOLUTE + ..\\rt_System.c 0x00000000 Number 0 rt_system.o ABSOLUTE + ..\rt_CMSIS.c 0x00000000 Number 0 rt_cmsis.o ABSOLUTE + ..\rt_Event.c 0x00000000 Number 0 rt_event.o ABSOLUTE + ..\rt_List.c 0x00000000 Number 0 rt_list.o ABSOLUTE + ..\rt_Mailbox.c 0x00000000 Number 0 rt_mailbox.o ABSOLUTE + ..\rt_MemBox.c 0x00000000 Number 0 rt_membox.o ABSOLUTE + ..\rt_Memory.c 0x00000000 Number 0 rt_memory.o ABSOLUTE + ..\rt_Mutex.c 0x00000000 Number 0 rt_mutex.o ABSOLUTE + ..\rt_Robin.c 0x00000000 Number 0 rt_robin.o ABSOLUTE + ..\rt_Semaphore.c 0x00000000 Number 0 rt_semaphore.o ABSOLUTE + ..\rt_System.c 0x00000000 Number 0 rt_system.o ABSOLUTE + ..\rt_Task.c 0x00000000 Number 0 rt_task.o ABSOLUTE + ..\rt_Time.c 0x00000000 Number 0 rt_time.o ABSOLUTE + C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Boards\ST\STM32F072-Discovery\Common\Buttons_STM32F072-Discovery.c 0x00000000 Number 0 buttons_stm32f072-discovery.o ABSOLUTE + C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Boards\ST\STM32F072-Discovery\Common\LED_STM32F072-Discovery.c 0x00000000 Number 0 led_stm32f072-discovery.o ABSOLUTE + C:\\Keil_v5\\ARM\\PACK\\Keil\\STM32F0xx_DFP\\1.5.0\\Boards\\ST\\STM32F072-Discovery\\Common\\Buttons_STM32F072-Discovery.c 0x00000000 Number 0 buttons_stm32f072-discovery.o ABSOLUTE + C:\\Keil_v5\\ARM\\PACK\\Keil\\STM32F0xx_DFP\\1.5.0\\Boards\\ST\\STM32F072-Discovery\\Common\\LED_STM32F072-Discovery.c 0x00000000 Number 0 led_stm32f072-discovery.o ABSOLUTE + DAC_DRV.c 0x00000000 Number 0 dac_drv.o ABSOLUTE + DAC_DRV.c 0x00000000 Number 0 dac_drv.o ABSOLUTE + HAL_CM0.c 0x00000000 Number 0 hal_cm0.o ABSOLUTE + HAL_CM0.c 0x00000000 Number 0 hal_cm0.o ABSOLUTE + RTE\CMSIS\RTX_Conf_CM.c 0x00000000 Number 0 rtx_conf_cm.o ABSOLUTE + RTE\Device\STM32F072RB\startup_stm32f072xb.s 0x00000000 Number 0 startup_stm32f072xb.o ABSOLUTE + RTE\Device\STM32F072RB\system_stm32f0xx.c 0x00000000 Number 0 system_stm32f0xx.o ABSOLUTE + RTE\\Device\\STM32F072RB\\system_stm32f0xx.c 0x00000000 Number 0 system_stm32f0xx.o ABSOLUTE + RTX_Blinky.c 0x00000000 Number 0 rtx_blinky.o ABSOLUTE + RTX_Blinky.c 0x00000000 Number 0 rtx_blinky.o ABSOLUTE + SVC_Table.s 0x00000000 Number 0 svc_table.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE + init.s 0x00000000 Number 0 init.o ABSOLUTE + RESET 0x08000000 Section 192 startup_stm32f072xb.o(RESET) + .ARM.Collect$$$$00000000 0x080000c0 Section 0 entry.o(.ARM.Collect$$$$00000000) + .ARM.Collect$$$$00000001 0x080000c0 Section 4 entry2.o(.ARM.Collect$$$$00000001) + .ARM.Collect$$$$00000004 0x080000c4 Section 4 entry5.o(.ARM.Collect$$$$00000004) + .ARM.Collect$$$$00000008 0x080000c8 Section 0 entry7b.o(.ARM.Collect$$$$00000008) + .ARM.Collect$$$$0000000A 0x080000c8 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) + .ARM.Collect$$$$0000000D 0x080000c8 Section 0 entry10a.o(.ARM.Collect$$$$0000000D) + .ARM.Collect$$$$0000000F 0x080000c8 Section 0 entry11a.o(.ARM.Collect$$$$0000000F) + .ARM.Collect$$$$000000FF 0x080000c8 Section 0 rtx_conf_cm.o(.ARM.Collect$$$$000000FF) + .ARM.Collect$$$$00002712 0x080000e0 Section 4 entry2.o(.ARM.Collect$$$$00002712) + __lit__00000000 0x080000e0 Data 4 entry2.o(.ARM.Collect$$$$00002712) + .emb_text 0x080000e4 Section 356 hal_cm0.o(.emb_text) + .text 0x08000248 Section 0 rtx_blinky.o(.text) + .text 0x08000424 Section 0 dac_drv.o(.text) + .text 0x08000498 Section 0 buttons_stm32f072-discovery.o(.text) + .text 0x08000500 Section 0 led_stm32f072-discovery.o(.text) + .text 0x080005e4 Section 0 rtx_conf_cm.o(.text) + .text 0x0800060c Section 28 startup_stm32f072xb.o(.text) + .text 0x08000628 Section 0 system_stm32f0xx.o(.text) + .text 0x0800076c Section 0 uidiv.o(.text) + .text 0x08000798 Section 36 init.o(.text) + .text 0x080007bc Section 0 __dczerorl.o(.text) + SVC_TABLE 0x080007f8 Section 4 svc_table.o(SVC_TABLE) + i.__scatterload_copy 0x080007fc Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x0800080a Section 2 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x0800080c Section 14 handlers.o(i.__scatterload_zeroinit) + i._init_box 0x0800081a Section 0 rt_membox.o(i._init_box) + i.isrMessageGet 0x08000862 Section 0 rt_cmsis.o(i.isrMessageGet) + i.isrMessagePut 0x08000890 Section 0 rt_cmsis.o(i.isrMessagePut) + i.isr_mbx_receive 0x080008c0 Section 0 rt_mailbox.o(i.isr_mbx_receive) + i.isr_mbx_send 0x08000906 Section 0 rt_mailbox.o(i.isr_mbx_send) + i.osKernelInitialize 0x08000914 Section 0 rt_cmsis.o(i.osKernelInitialize) + i.osKernelStart 0x0800093c Section 0 rt_cmsis.o(i.osKernelStart) + i.osMessageGet 0x080009a8 Section 0 rt_cmsis.o(i.osMessageGet) + i.osSignalWait 0x080009c4 Section 0 rt_cmsis.o(i.osSignalWait) + i.osThreadCreate 0x080009e0 Section 0 rt_cmsis.o(i.osThreadCreate) + i.osThreadExit 0x08000a14 Section 0 rt_cmsis.o(i.osThreadExit) + i.osTimerCall 0x08000a2c Section 0 rt_cmsis.o(i.osTimerCall) + i.osTimerThread 0x08000a3c Section 0 rt_cmsis.o(i.osTimerThread) + i.os_tick_init 0x08000a68 Section 0 rt_system.o(i.os_tick_init) + i.os_tick_irqack 0x08000a94 Section 0 rt_system.o(i.os_tick_irqack) + i.rt_alloc_box 0x08000a96 Section 0 rt_membox.o(i.rt_alloc_box) + i.rt_alloc_mem 0x08000ab4 Section 0 rt_memory.o(i.rt_alloc_mem) + i.rt_block 0x08000af8 Section 0 rt_task.o(i.rt_block) + i.rt_chk_robin 0x08000b30 Section 0 rt_robin.o(i.rt_chk_robin) + i.rt_dec_dly 0x08000b74 Section 0 rt_list.o(i.rt_dec_dly) + i.rt_dispatch 0x08000be8 Section 0 rt_task.o(i.rt_dispatch) + i.rt_evt_psh 0x08000c28 Section 0 rt_event.o(i.rt_evt_psh) + i.rt_evt_wait 0x08000c78 Section 0 rt_event.o(i.rt_evt_wait) + i.rt_free_box 0x08000cb8 Section 0 rt_membox.o(i.rt_free_box) + i.rt_free_mem 0x08000cde Section 0 rt_memory.o(i.rt_free_mem) + i.rt_get_first 0x08000d0e Section 0 rt_list.o(i.rt_get_first) + i.rt_id2obj 0x08000d38 Section 0 rt_cmsis.o(i.rt_id2obj) + rt_id2obj 0x08000d39 Thumb Code 8 rt_cmsis.o(i.rt_id2obj) + i.rt_init_context 0x08000d40 Section 0 rt_task.o(i.rt_init_context) + rt_init_context 0x08000d41 Thumb Code 66 rt_task.o(i.rt_init_context) + i.rt_init_mem 0x08000d88 Section 0 rt_memory.o(i.rt_init_mem) + i.rt_init_robin 0x08000da4 Section 0 rt_robin.o(i.rt_init_robin) + i.rt_init_stack 0x08000dbc Section 0 hal_cm.o(i.rt_init_stack) + i.rt_mbx_check 0x08000e34 Section 0 rt_mailbox.o(i.rt_mbx_check) + i.rt_mbx_init 0x08000e3c Section 0 rt_mailbox.o(i.rt_mbx_init) + i.rt_mbx_psh 0x08000e60 Section 0 rt_mailbox.o(i.rt_mbx_psh) + i.rt_mbx_wait 0x08000f30 Section 0 rt_mailbox.o(i.rt_mbx_wait) + i.rt_ms2tick 0x08000fe0 Section 0 rt_cmsis.o(i.rt_ms2tick) + rt_ms2tick 0x08000fe1 Thumb Code 56 rt_cmsis.o(i.rt_ms2tick) + i.rt_pop_req 0x08001024 Section 0 rt_system.o(i.rt_pop_req) + i.rt_psh_req 0x08001094 Section 0 rt_system.o(i.rt_psh_req) + i.rt_psq_enq 0x080010b4 Section 0 rt_list.o(i.rt_psq_enq) + i.rt_put_dly 0x080010f4 Section 0 rt_list.o(i.rt_put_dly) + i.rt_put_prio 0x08001144 Section 0 rt_list.o(i.rt_put_prio) + i.rt_put_rdy_first 0x08001180 Section 0 rt_list.o(i.rt_put_rdy_first) + i.rt_resort_prio 0x08001194 Section 0 rt_list.o(i.rt_resort_prio) + i.rt_ret_val 0x080011c4 Section 0 hal_cm.o(i.rt_ret_val) + i.rt_ret_val2 0x080011ca Section 0 hal_cm.o(i.rt_ret_val2) + i.rt_rmv_dly 0x080011d2 Section 0 rt_list.o(i.rt_rmv_dly) + i.rt_rmv_list 0x080011fc Section 0 rt_list.o(i.rt_rmv_list) + i.rt_sem_psh 0x08001230 Section 0 rt_semaphore.o(i.rt_sem_psh) + i.rt_stk_check 0x08001264 Section 0 rt_system.o(i.rt_stk_check) + i.rt_switch_req 0x0800128c Section 0 rt_task.o(i.rt_switch_req) + i.rt_sys_init 0x0800129c Section 0 rt_task.o(i.rt_sys_init) + i.rt_sys_start 0x08001364 Section 0 rt_task.o(i.rt_sys_start) + i.rt_systick 0x080013c8 Section 0 rt_system.o(i.rt_systick) + i.rt_tid2ptcb 0x08001404 Section 0 rt_cmsis.o(i.rt_tid2ptcb) + rt_tid2ptcb 0x08001405 Thumb Code 18 rt_cmsis.o(i.rt_tid2ptcb) + i.rt_timer_insert 0x08001418 Section 0 rt_cmsis.o(i.rt_timer_insert) + rt_timer_insert 0x08001419 Thumb Code 52 rt_cmsis.o(i.rt_timer_insert) + i.rt_tsk_create 0x08001450 Section 0 rt_task.o(i.rt_tsk_create) + i.rt_tsk_delete 0x080014c8 Section 0 rt_task.o(i.rt_tsk_delete) + i.rt_tsk_prio 0x08001620 Section 0 rt_task.o(i.rt_tsk_prio) + i.rt_tsk_self 0x080016a0 Section 0 rt_task.o(i.rt_tsk_self) + i.svcKernelInitialize 0x080016b0 Section 0 rt_cmsis.o(i.svcKernelInitialize) + i.svcKernelStart 0x08001728 Section 0 rt_cmsis.o(i.svcKernelStart) + i.svcMessageCreate 0x08001774 Section 0 rt_cmsis.o(i.svcMessageCreate) + i.svcMessageGet 0x0800179e Section 0 rt_cmsis.o(i.svcMessageGet) + i.svcSignalWait 0x080017dc Section 0 rt_cmsis.o(i.svcSignalWait) + i.svcThreadCreate 0x08001838 Section 0 rt_cmsis.o(i.svcThreadCreate) + i.svcThreadGetId 0x080018b0 Section 0 rt_cmsis.o(i.svcThreadGetId) + i.svcThreadTerminate 0x080018cc Section 0 rt_cmsis.o(i.svcThreadTerminate) + i.svcTimerCall 0x08001908 Section 0 rt_cmsis.o(i.svcTimerCall) + i.sysTimerTick 0x08001924 Section 0 rt_cmsis.o(i.sysTimerTick) + .constdata 0x0800197c Section 16 rtx_blinky.o(.constdata) + .constdata 0x0800198c Section 16 led_stm32f072-discovery.o(.constdata) + .constdata 0x0800199c Section 86 rtx_conf_cm.o(.constdata) + __tagsym$$used 0x080019b8 Number 0 rtx_conf_cm.o(.constdata) + __tagsym$$used 0x080019bc Number 0 rtx_conf_cm.o(.constdata) + __tagsym$$used 0x080019c0 Number 0 rtx_conf_cm.o(.constdata) + __tagsym$$used 0x080019c4 Number 0 rtx_conf_cm.o(.constdata) + .constdata 0x080019f2 Section 16 system_stm32f0xx.o(.constdata) + .data 0x20000000 Section 550 rtx_blinky.o(.data) + .data 0x20000228 Section 32 rtx_conf_cm.o(.data) + .data 0x20000248 Section 4 system_stm32f0xx.o(.data) + .data 0x2000024c Section 8 rt_cmsis.o(.data) + .data 0x20000254 Section 8 rt_task.o(.data) + .data 0x2000025c Section 8 rt_system.o(.data) + os_lock 0x2000025c Data 1 rt_system.o(.data) + os_psh_flag 0x2000025d Data 1 rt_system.o(.data) + pend_flags 0x2000025e Data 1 rt_system.o(.data) + .data 0x20000264 Section 4 rt_time.o(.data) + .data 0x20000268 Section 8 rt_robin.o(.data) + .bss 0x20000270 Section 362 rtx_blinky.o(.bss) + .bss 0x200003e0 Section 1192 rtx_conf_cm.o(.bss) + .bss 0x20000888 Section 52 rt_task.o(.bss) + .bss 0x200008bc Section 48 rt_list.o(.bss) + STACK 0x200008f0 Section 1024 startup_stm32f072xb.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 rtx_blinky.o ABSOLUTE + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _microlib_exit - Undefined Weak Reference + __Vectors_Size 0x000000c0 Number 0 startup_stm32f072xb.o ABSOLUTE + __RL_RTX_VER 0x00000480 Number 0 rt_system.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f072xb.o(RESET) + __Vectors_End 0x080000c0 Data 0 startup_stm32f072xb.o(RESET) + __main 0x080000c1 Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) + _main_stk 0x080000c1 Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) + _main_scatterload 0x080000c5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + __main_after_scatterload 0x080000c9 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + __rt_final_cpp 0x080000c9 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D) + __rt_final_exit 0x080000c9 Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F) + _main_clock 0x080000c9 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) + _main_cpp_init 0x080000c9 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) + _main_init 0x080000c9 Thumb Code 18 rtx_conf_cm.o(.ARM.Collect$$$$000000FF) + rt_set_PSP 0x080000e5 Thumb Code 6 hal_cm0.o(.emb_text) + rt_get_PSP 0x080000eb Thumb Code 6 hal_cm0.o(.emb_text) + os_set_env 0x080000f1 Thumb Code 32 hal_cm0.o(.emb_text) + _alloc_box 0x08000115 Thumb Code 28 hal_cm0.o(.emb_text) + _free_box 0x08000135 Thumb Code 28 hal_cm0.o(.emb_text) + SVC_Handler 0x08000155 Thumb Code 136 hal_cm0.o(.emb_text) + PendSV_Handler 0x080001e9 Thumb Code 72 hal_cm0.o(.emb_text) + SysTick_Handler 0x08000235 Thumb Code 8 hal_cm0.o(.emb_text) + OS_Tick_Handler 0x0800023d Thumb Code 12 hal_cm0.o(.emb_text) + SystemCoreClockConfigure 0x08000249 Thumb Code 196 rtx_blinky.o(.text) + blinkLED 0x0800030d Thumb Code 62 rtx_blinky.o(.text) + main 0x0800034b Thumb Code 184 rtx_blinky.o(.text) + DAC_read 0x08000425 Thumb Code 10 dac_drv.o(.text) + DAC_write 0x0800042f Thumb Code 10 dac_drv.o(.text) + DAC_enable 0x08000439 Thumb Code 14 dac_drv.o(.text) + DAC_init 0x08000447 Thumb Code 74 dac_drv.o(.text) + Buttons_Initialize 0x08000499 Thumb Code 54 buttons_stm32f072-discovery.o(.text) + Buttons_Uninitialize 0x080004cf Thumb Code 20 buttons_stm32f072-discovery.o(.text) + Buttons_GetState 0x080004e3 Thumb Code 22 buttons_stm32f072-discovery.o(.text) + Buttons_GetCount 0x080004f9 Thumb Code 4 buttons_stm32f072-discovery.o(.text) + LED_Off 0x08000501 Thumb Code 28 led_stm32f072-discovery.o(.text) + LED_On 0x0800051d Thumb Code 26 led_stm32f072-discovery.o(.text) + LED_SetOut 0x08000537 Thumb Code 42 led_stm32f072-discovery.o(.text) + LED_Initialize 0x08000561 Thumb Code 110 led_stm32f072-discovery.o(.text) + LED_Uninitialize 0x080005cf Thumb Code 4 led_stm32f072-discovery.o(.text) + LED_GetCount 0x080005d3 Thumb Code 4 led_stm32f072-discovery.o(.text) + os_idle_demon 0x080005e5 Thumb Code 4 rtx_conf_cm.o(.text) + os_error 0x080005e9 Thumb Code 34 rtx_conf_cm.o(.text) + Reset_Handler 0x0800060d Thumb Code 8 startup_stm32f072xb.o(.text) + NMI_Handler 0x08000615 Thumb Code 2 startup_stm32f072xb.o(.text) + HardFault_Handler 0x08000617 Thumb Code 2 startup_stm32f072xb.o(.text) + ADC1_COMP_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + CEC_CAN_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + DMA1_Channel1_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + DMA1_Channel2_3_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + DMA1_Channel4_5_6_7_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + EXTI0_1_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + EXTI2_3_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + EXTI4_15_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + FLASH_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + I2C1_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + I2C2_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + PVD_VDDIO2_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + RCC_CRS_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + RTC_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + SPI1_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + SPI2_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM14_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM15_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM16_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM17_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM1_BRK_UP_TRG_COM_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM1_CC_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM2_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM3_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM6_DAC_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TIM7_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + TSC_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + USART1_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + USART2_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + USART3_4_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + USB_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + WWDG_IRQHandler 0x0800061f Thumb Code 0 startup_stm32f072xb.o(.text) + SystemInit 0x08000629 Thumb Code 102 system_stm32f0xx.o(.text) + SystemCoreClockUpdate 0x0800068f Thumb Code 188 system_stm32f0xx.o(.text) + __aeabi_uidiv 0x0800076d Thumb Code 0 uidiv.o(.text) + __aeabi_uidivmod 0x0800076d Thumb Code 44 uidiv.o(.text) + __scatterload 0x08000799 Thumb Code 28 init.o(.text) + __scatterload_rt2 0x08000799 Thumb Code 0 init.o(.text) + __decompress 0x080007bd Thumb Code 0 __dczerorl.o(.text) + __decompress0 0x080007bd Thumb Code 58 __dczerorl.o(.text) + SVC_Count 0x080007f8 Data 4 svc_table.o(SVC_TABLE) + SVC_Table 0x080007fc Data 0 svc_table.o(SVC_TABLE) + __scatterload_copy 0x080007fd Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_null 0x0800080b Thumb Code 2 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x0800080d Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + _init_box 0x0800081b Thumb Code 72 rt_membox.o(i._init_box) + isrMessageGet 0x08000863 Thumb Code 46 rt_cmsis.o(i.isrMessageGet) + isrMessagePut 0x08000891 Thumb Code 48 rt_cmsis.o(i.isrMessagePut) + isr_mbx_receive 0x080008c1 Thumb Code 70 rt_mailbox.o(i.isr_mbx_receive) + isr_mbx_send 0x08000907 Thumb Code 12 rt_mailbox.o(i.isr_mbx_send) + osKernelInitialize 0x08000915 Thumb Code 36 rt_cmsis.o(i.osKernelInitialize) + osKernelStart 0x0800093d Thumb Code 100 rt_cmsis.o(i.osKernelStart) + osMessageGet 0x080009a9 Thumb Code 24 rt_cmsis.o(i.osMessageGet) + osSignalWait 0x080009c5 Thumb Code 22 rt_cmsis.o(i.osSignalWait) + osThreadCreate 0x080009e1 Thumb Code 44 rt_cmsis.o(i.osThreadCreate) + osThreadExit 0x08000a15 Thumb Code 14 rt_cmsis.o(i.osThreadExit) + osTimerCall 0x08000a2d Thumb Code 10 rt_cmsis.o(i.osTimerCall) + osTimerThread 0x08000a3d Thumb Code 38 rt_cmsis.o(i.osTimerThread) + os_tick_init 0x08000a69 Thumb Code 32 rt_system.o(i.os_tick_init) + os_tick_irqack 0x08000a95 Thumb Code 2 rt_system.o(i.os_tick_irqack) + rt_alloc_box 0x08000a97 Thumb Code 30 rt_membox.o(i.rt_alloc_box) + rt_alloc_mem 0x08000ab5 Thumb Code 66 rt_memory.o(i.rt_alloc_mem) + rt_block 0x08000af9 Thumb Code 42 rt_task.o(i.rt_block) + rt_chk_robin 0x08000b31 Thumb Code 56 rt_robin.o(i.rt_chk_robin) + rt_dec_dly 0x08000b75 Thumb Code 108 rt_list.o(i.rt_dec_dly) + rt_dispatch 0x08000be9 Thumb Code 56 rt_task.o(i.rt_dispatch) + rt_evt_psh 0x08000c29 Thumb Code 74 rt_event.o(i.rt_evt_psh) + rt_evt_wait 0x08000c79 Thumb Code 58 rt_event.o(i.rt_evt_wait) + rt_free_box 0x08000cb9 Thumb Code 38 rt_membox.o(i.rt_free_box) + rt_free_mem 0x08000cdf Thumb Code 48 rt_memory.o(i.rt_free_mem) + rt_get_first 0x08000d0f Thumb Code 42 rt_list.o(i.rt_get_first) + rt_init_mem 0x08000d89 Thumb Code 28 rt_memory.o(i.rt_init_mem) + rt_init_robin 0x08000da5 Thumb Code 14 rt_robin.o(i.rt_init_robin) + rt_init_stack 0x08000dbd Thumb Code 106 hal_cm.o(i.rt_init_stack) + rt_mbx_check 0x08000e35 Thumb Code 8 rt_mailbox.o(i.rt_mbx_check) + rt_mbx_init 0x08000e3d Thumb Code 30 rt_mailbox.o(i.rt_mbx_init) + rt_mbx_psh 0x08000e61 Thumb Code 204 rt_mailbox.o(i.rt_mbx_psh) + rt_mbx_wait 0x08000f31 Thumb Code 170 rt_mailbox.o(i.rt_mbx_wait) + rt_pop_req 0x08001025 Thumb Code 100 rt_system.o(i.rt_pop_req) + rt_psh_req 0x08001095 Thumb Code 24 rt_system.o(i.rt_psh_req) + rt_psq_enq 0x080010b5 Thumb Code 60 rt_list.o(i.rt_psq_enq) + rt_put_dly 0x080010f5 Thumb Code 74 rt_list.o(i.rt_put_dly) + rt_put_prio 0x08001145 Thumb Code 60 rt_list.o(i.rt_put_prio) + rt_put_rdy_first 0x08001181 Thumb Code 14 rt_list.o(i.rt_put_rdy_first) + rt_resort_prio 0x08001195 Thumb Code 44 rt_list.o(i.rt_resort_prio) + rt_ret_val 0x080011c5 Thumb Code 6 hal_cm.o(i.rt_ret_val) + rt_ret_val2 0x080011cb Thumb Code 8 hal_cm.o(i.rt_ret_val2) + rt_rmv_dly 0x080011d3 Thumb Code 42 rt_list.o(i.rt_rmv_dly) + rt_rmv_list 0x080011fd Thumb Code 46 rt_list.o(i.rt_rmv_list) + rt_sem_psh 0x08001231 Thumb Code 48 rt_semaphore.o(i.rt_sem_psh) + rt_stk_check 0x08001265 Thumb Code 30 rt_system.o(i.rt_stk_check) + rt_switch_req 0x0800128d Thumb Code 10 rt_task.o(i.rt_switch_req) + rt_sys_init 0x0800129d Thumb Code 134 rt_task.o(i.rt_sys_init) + rt_sys_start 0x08001365 Thumb Code 82 rt_task.o(i.rt_sys_start) + rt_systick 0x080013c9 Thumb Code 48 rt_system.o(i.rt_systick) + rt_tsk_create 0x08001451 Thumb Code 106 rt_task.o(i.rt_tsk_create) + rt_tsk_delete 0x080014c9 Thumb Code 318 rt_task.o(i.rt_tsk_delete) + rt_tsk_prio 0x08001621 Thumb Code 112 rt_task.o(i.rt_tsk_prio) + rt_tsk_self 0x080016a1 Thumb Code 12 rt_task.o(i.rt_tsk_self) + svcKernelInitialize 0x080016b1 Thumb Code 86 rt_cmsis.o(i.svcKernelInitialize) + svcKernelStart 0x08001729 Thumb Code 66 rt_cmsis.o(i.svcKernelStart) + svcMessageCreate 0x08001775 Thumb Code 42 rt_cmsis.o(i.svcMessageCreate) + svcMessageGet 0x0800179f Thumb Code 60 rt_cmsis.o(i.svcMessageGet) + svcSignalWait 0x080017dd Thumb Code 82 rt_cmsis.o(i.svcSignalWait) + svcThreadCreate 0x08001839 Thumb Code 106 rt_cmsis.o(i.svcThreadCreate) + svcThreadGetId 0x080018b1 Thumb Code 22 rt_cmsis.o(i.svcThreadGetId) + svcThreadTerminate 0x080018cd Thumb Code 56 rt_cmsis.o(i.svcThreadTerminate) + svcTimerCall 0x08001909 Thumb Code 28 rt_cmsis.o(i.svcTimerCall) + sysTimerTick 0x08001925 Thumb Code 78 rt_cmsis.o(i.sysTimerTick) + os_thread_def_blinkLED 0x0800197c Data 16 rtx_blinky.o(.constdata) + led_mask 0x0800198c Data 16 led_stm32f072-discovery.o(.constdata) + os_maxtaskrun 0x0800199c Data 2 rtx_conf_cm.o(.constdata) + os_stackinfo 0x080019a0 Data 4 rtx_conf_cm.o(.constdata) + os_rrobin 0x080019a4 Data 4 rtx_conf_cm.o(.constdata) + os_tickfreq 0x080019a8 Data 4 rtx_conf_cm.o(.constdata) + os_tickus_i 0x080019ac Data 2 rtx_conf_cm.o(.constdata) + os_tickus_f 0x080019ae Data 2 rtx_conf_cm.o(.constdata) + os_trv 0x080019b0 Data 4 rtx_conf_cm.o(.constdata) + os_flags 0x080019b4 Data 1 rtx_conf_cm.o(.constdata) + CMSIS_RTOS_API_Version 0x080019b8 Data 4 rtx_conf_cm.o(.constdata) + CMSIS_RTOS_RTX_Version 0x080019bc Data 4 rtx_conf_cm.o(.constdata) + os_clockrate 0x080019c0 Data 4 rtx_conf_cm.o(.constdata) + os_timernum 0x080019c4 Data 4 rtx_conf_cm.o(.constdata) + mp_tcb_size 0x080019c8 Data 2 rtx_conf_cm.o(.constdata) + mp_stk_size 0x080019cc Data 4 rtx_conf_cm.o(.constdata) + os_stack_sz 0x080019d0 Data 4 rtx_conf_cm.o(.constdata) + os_fifo_size 0x080019d4 Data 1 rtx_conf_cm.o(.constdata) + os_thread_def_osTimerThread 0x080019d8 Data 16 rtx_conf_cm.o(.constdata) + os_messageQ_def_osTimerMessageQ 0x080019e8 Data 8 rtx_conf_cm.o(.constdata) + mp_tmr_size 0x080019f0 Data 2 rtx_conf_cm.o(.constdata) + AHBPrescTable 0x080019f2 Data 16 system_stm32f0xx.o(.constdata) + Region$$Table$$Base 0x08001a04 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08001a24 Number 0 anon$$obj.o(Region$$Table) + tid_blinkLED 0x20000000 Data 4 rtx_blinky.o(.data) + DAC_value 0x20000004 Data 182 rtx_blinky.o(.data) + DAC_value1 0x200000ba Data 362 rtx_blinky.o(.data) + Counter 0x20000224 Data 1 rtx_blinky.o(.data) + Direction 0x20000225 Data 1 rtx_blinky.o(.data) + osThreadId_osTimerThread 0x20000228 Data 4 rtx_conf_cm.o(.data) + osMessageQId_osTimerMessageQ 0x2000022c Data 4 rtx_conf_cm.o(.data) + os_tmr 0x20000230 Data 4 rtx_conf_cm.o(.data) + m_tmr 0x20000234 Data 4 rtx_conf_cm.o(.data) + os_thread_def_main 0x20000238 Data 16 rtx_conf_cm.o(.data) + SystemCoreClock 0x20000248 Data 4 system_stm32f0xx.o(.data) + os_initialized 0x2000024c Data 1 rt_cmsis.o(.data) + os_running 0x2000024d Data 1 rt_cmsis.o(.data) + os_timer_head 0x20000250 Data 4 rt_cmsis.o(.data) + os_tsk 0x20000254 Data 8 rt_task.o(.data) + os_tick_irqn 0x20000260 Data 4 rt_system.o(.data) + os_time 0x20000264 Data 4 rt_time.o(.data) + os_robin 0x20000268 Data 8 rt_robin.o(.data) + DAC_value2 0x20000270 Data 362 rtx_blinky.o(.bss) + mp_tcb 0x200003e0 Data 168 rtx_conf_cm.o(.bss) + mp_stk 0x20000488 Data 416 rtx_conf_cm.o(.bss) + os_stack_mem 0x20000628 Data 432 rtx_conf_cm.o(.bss) + os_fifo 0x200007d8 Data 132 rtx_conf_cm.o(.bss) + os_active_TCB 0x2000085c Data 12 rtx_conf_cm.o(.bss) + os_messageQ_q_osTimerMessageQ 0x20000868 Data 32 rtx_conf_cm.o(.bss) + os_idle_TCB 0x20000888 Data 52 rt_task.o(.bss) + os_rdy 0x200008bc Data 24 rt_list.o(.bss) + os_dly 0x200008d4 Data 24 rt_list.o(.bss) + __initial_sp 0x20000cf0 Data 0 startup_stm32f072xb.o(STACK) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x080000c1 + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00001c94, Max: 0x00020000, ABSOLUTE, COMPRESSED[0x00001c50]) + + Execution Region ER_IROM1 (Base: 0x08000000, Size: 0x00001a24, Max: 0x00020000, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x000000c0 Data RO 164 RESET startup_stm32f072xb.o + 0x080000c0 0x00000000 Code RO 1381 * .ARM.Collect$$$$00000000 mc_p.l(entry.o) + 0x080000c0 0x00000004 Code RO 1388 .ARM.Collect$$$$00000001 mc_p.l(entry2.o) + 0x080000c4 0x00000004 Code RO 1391 .ARM.Collect$$$$00000004 mc_p.l(entry5.o) + 0x080000c8 0x00000000 Code RO 1393 .ARM.Collect$$$$00000008 mc_p.l(entry7b.o) + 0x080000c8 0x00000000 Code RO 1395 .ARM.Collect$$$$0000000A mc_p.l(entry8b.o) + 0x080000c8 0x00000000 Code RO 1396 .ARM.Collect$$$$0000000D mc_p.l(entry10a.o) + 0x080000c8 0x00000000 Code RO 1398 .ARM.Collect$$$$0000000F mc_p.l(entry11a.o) + 0x080000c8 0x00000018 Code RO 133 .ARM.Collect$$$$000000FF rtx_conf_cm.o + 0x080000e0 0x00000004 Code RO 1389 .ARM.Collect$$$$00002712 mc_p.l(entry2.o) + 0x080000e4 0x00000164 Code RO 1368 .emb_text RTX_CM0.lib(hal_cm0.o) + 0x08000248 0x000001dc Code RO 3 .text rtx_blinky.o + 0x08000424 0x00000074 Code RO 72 .text dac_drv.o + 0x08000498 0x00000068 Code RO 92 .text buttons_stm32f072-discovery.o + 0x08000500 0x000000e4 Code RO 112 .text led_stm32f072-discovery.o + 0x080005e4 0x00000026 Code RO 134 .text rtx_conf_cm.o + 0x0800060a 0x00000002 PAD + 0x0800060c 0x0000001c Code RO 165 .text startup_stm32f072xb.o + 0x08000628 0x00000144 Code RO 171 .text system_stm32f0xx.o + 0x0800076c 0x0000002c Code RO 1384 .text mc_p.l(uidiv.o) + 0x08000798 0x00000024 Code RO 1404 .text mc_p.l(init.o) + 0x080007bc 0x0000003a Code RO 1414 .text mc_p.l(__dczerorl.o) + 0x080007f6 0x00000002 PAD + 0x080007f8 0x00000004 Code RO 1378 SVC_TABLE RTX_CM0.lib(svc_table.o) + 0x080007fc 0x0000000e Code RO 1408 i.__scatterload_copy mc_p.l(handlers.o) + 0x0800080a 0x00000002 Code RO 1409 i.__scatterload_null mc_p.l(handlers.o) + 0x0800080c 0x0000000e Code RO 1410 i.__scatterload_zeroinit mc_p.l(handlers.o) + 0x0800081a 0x00000048 Code RO 1270 i._init_box RTX_CM0.lib(rt_membox.o) + 0x08000862 0x0000002e Code RO 198 i.isrMessageGet RTX_CM0.lib(rt_cmsis.o) + 0x08000890 0x00000030 Code RO 199 i.isrMessagePut RTX_CM0.lib(rt_cmsis.o) + 0x080008c0 0x00000046 Code RO 1116 i.isr_mbx_receive RTX_CM0.lib(rt_mailbox.o) + 0x08000906 0x0000000c Code RO 1117 i.isr_mbx_send RTX_CM0.lib(rt_mailbox.o) + 0x08000912 0x00000002 PAD + 0x08000914 0x00000028 Code RO 203 i.osKernelInitialize RTX_CM0.lib(rt_cmsis.o) + 0x0800093c 0x0000006c Code RO 205 i.osKernelStart RTX_CM0.lib(rt_cmsis.o) + 0x080009a8 0x0000001c Code RO 214 i.osMessageGet RTX_CM0.lib(rt_cmsis.o) + 0x080009c4 0x0000001c Code RO 230 i.osSignalWait RTX_CM0.lib(rt_cmsis.o) + 0x080009e0 0x00000034 Code RO 231 i.osThreadCreate RTX_CM0.lib(rt_cmsis.o) + 0x08000a14 0x00000018 Code RO 232 i.osThreadExit RTX_CM0.lib(rt_cmsis.o) + 0x08000a2c 0x00000010 Code RO 238 i.osTimerCall RTX_CM0.lib(rt_cmsis.o) + 0x08000a3c 0x0000002c Code RO 243 i.osTimerThread RTX_CM0.lib(rt_cmsis.o) + 0x08000a68 0x0000002c Code RO 904 i.os_tick_init RTX_CM0.lib(rt_system.o) + 0x08000a94 0x00000002 Code RO 905 i.os_tick_irqack RTX_CM0.lib(rt_system.o) + 0x08000a96 0x0000001e Code RO 1271 i.rt_alloc_box RTX_CM0.lib(rt_membox.o) + 0x08000ab4 0x00000042 Code RO 1299 i.rt_alloc_mem RTX_CM0.lib(rt_memory.o) + 0x08000af6 0x00000002 PAD + 0x08000af8 0x00000038 Code RO 819 i.rt_block RTX_CM0.lib(rt_task.o) + 0x08000b30 0x00000044 Code RO 1347 i.rt_chk_robin RTX_CM0.lib(rt_robin.o) + 0x08000b74 0x00000074 Code RO 1040 i.rt_dec_dly RTX_CM0.lib(rt_list.o) + 0x08000be8 0x00000040 Code RO 820 i.rt_dispatch RTX_CM0.lib(rt_task.o) + 0x08000c28 0x00000050 Code RO 997 i.rt_evt_psh RTX_CM0.lib(rt_event.o) + 0x08000c78 0x00000040 Code RO 999 i.rt_evt_wait RTX_CM0.lib(rt_event.o) + 0x08000cb8 0x00000026 Code RO 1272 i.rt_free_box RTX_CM0.lib(rt_membox.o) + 0x08000cde 0x00000030 Code RO 1300 i.rt_free_mem RTX_CM0.lib(rt_memory.o) + 0x08000d0e 0x0000002a Code RO 1041 i.rt_get_first RTX_CM0.lib(rt_list.o) + 0x08000d38 0x00000008 Code RO 248 i.rt_id2obj RTX_CM0.lib(rt_cmsis.o) + 0x08000d40 0x00000048 Code RO 821 i.rt_init_context RTX_CM0.lib(rt_task.o) + 0x08000d88 0x0000001c Code RO 1301 i.rt_init_mem RTX_CM0.lib(rt_memory.o) + 0x08000da4 0x00000018 Code RO 1348 i.rt_init_robin RTX_CM0.lib(rt_robin.o) + 0x08000dbc 0x00000078 Code RO 1323 i.rt_init_stack RTX_CM0.lib(hal_cm.o) + 0x08000e34 0x00000008 Code RO 1118 i.rt_mbx_check RTX_CM0.lib(rt_mailbox.o) + 0x08000e3c 0x00000024 Code RO 1119 i.rt_mbx_init RTX_CM0.lib(rt_mailbox.o) + 0x08000e60 0x000000d0 Code RO 1120 i.rt_mbx_psh RTX_CM0.lib(rt_mailbox.o) + 0x08000f30 0x000000b0 Code RO 1122 i.rt_mbx_wait RTX_CM0.lib(rt_mailbox.o) + 0x08000fe0 0x00000044 Code RO 249 i.rt_ms2tick RTX_CM0.lib(rt_cmsis.o) + 0x08001024 0x00000070 Code RO 908 i.rt_pop_req RTX_CM0.lib(rt_system.o) + 0x08001094 0x00000020 Code RO 909 i.rt_psh_req RTX_CM0.lib(rt_system.o) + 0x080010b4 0x00000040 Code RO 1043 i.rt_psq_enq RTX_CM0.lib(rt_list.o) + 0x080010f4 0x00000050 Code RO 1044 i.rt_put_dly RTX_CM0.lib(rt_list.o) + 0x08001144 0x0000003c Code RO 1045 i.rt_put_prio RTX_CM0.lib(rt_list.o) + 0x08001180 0x00000014 Code RO 1046 i.rt_put_rdy_first RTX_CM0.lib(rt_list.o) + 0x08001194 0x00000030 Code RO 1047 i.rt_resort_prio RTX_CM0.lib(rt_list.o) + 0x080011c4 0x00000006 Code RO 1324 i.rt_ret_val RTX_CM0.lib(hal_cm.o) + 0x080011ca 0x00000008 Code RO 1325 i.rt_ret_val2 RTX_CM0.lib(hal_cm.o) + 0x080011d2 0x0000002a Code RO 1048 i.rt_rmv_dly RTX_CM0.lib(rt_list.o) + 0x080011fc 0x00000034 Code RO 1049 i.rt_rmv_list RTX_CM0.lib(rt_list.o) + 0x08001230 0x00000034 Code RO 1167 i.rt_sem_psh RTX_CM0.lib(rt_semaphore.o) + 0x08001264 0x00000028 Code RO 911 i.rt_stk_check RTX_CM0.lib(rt_system.o) + 0x0800128c 0x00000010 Code RO 822 i.rt_switch_req RTX_CM0.lib(rt_task.o) + 0x0800129c 0x000000c8 Code RO 823 i.rt_sys_init RTX_CM0.lib(rt_task.o) + 0x08001364 0x00000064 Code RO 824 i.rt_sys_start RTX_CM0.lib(rt_task.o) + 0x080013c8 0x0000003c Code RO 913 i.rt_systick RTX_CM0.lib(rt_system.o) + 0x08001404 0x00000012 Code RO 250 i.rt_tid2ptcb RTX_CM0.lib(rt_cmsis.o) + 0x08001416 0x00000002 PAD + 0x08001418 0x00000038 Code RO 251 i.rt_timer_insert RTX_CM0.lib(rt_cmsis.o) + 0x08001450 0x00000078 Code RO 825 i.rt_tsk_create RTX_CM0.lib(rt_task.o) + 0x080014c8 0x00000158 Code RO 826 i.rt_tsk_delete RTX_CM0.lib(rt_task.o) + 0x08001620 0x00000080 Code RO 828 i.rt_tsk_prio RTX_CM0.lib(rt_task.o) + 0x080016a0 0x00000010 Code RO 829 i.rt_tsk_self RTX_CM0.lib(rt_task.o) + 0x080016b0 0x00000078 Code RO 254 i.svcKernelInitialize RTX_CM0.lib(rt_cmsis.o) + 0x08001728 0x0000004c Code RO 256 i.svcKernelStart RTX_CM0.lib(rt_cmsis.o) + 0x08001774 0x0000002a Code RO 259 i.svcMessageCreate RTX_CM0.lib(rt_cmsis.o) + 0x0800179e 0x0000003c Code RO 260 i.svcMessageGet RTX_CM0.lib(rt_cmsis.o) + 0x080017da 0x00000002 PAD + 0x080017dc 0x0000005c Code RO 273 i.svcSignalWait RTX_CM0.lib(rt_cmsis.o) + 0x08001838 0x00000078 Code RO 274 i.svcThreadCreate RTX_CM0.lib(rt_cmsis.o) + 0x080018b0 0x0000001c Code RO 275 i.svcThreadGetId RTX_CM0.lib(rt_cmsis.o) + 0x080018cc 0x0000003c Code RO 278 i.svcThreadTerminate RTX_CM0.lib(rt_cmsis.o) + 0x08001908 0x0000001c Code RO 280 i.svcTimerCall RTX_CM0.lib(rt_cmsis.o) + 0x08001924 0x00000058 Code RO 289 i.sysTimerTick RTX_CM0.lib(rt_cmsis.o) + 0x0800197c 0x00000010 Data RO 5 .constdata rtx_blinky.o + 0x0800198c 0x00000010 Data RO 113 .constdata led_stm32f072-discovery.o + 0x0800199c 0x00000056 Data RO 136 .constdata rtx_conf_cm.o + 0x080019f2 0x00000010 Data RO 172 .constdata system_stm32f0xx.o + 0x08001a02 0x00000002 PAD + 0x08001a04 0x00000020 Data RO 1406 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Base: 0x20000000, Size: 0x00000cf0, Max: 0x00004000, ABSOLUTE, COMPRESSED[0x0000022c]) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x00000226 Data RW 6 .data rtx_blinky.o + 0x20000226 0x00000002 PAD + 0x20000228 0x00000020 Data RW 137 .data rtx_conf_cm.o + 0x20000248 0x00000004 Data RW 173 .data system_stm32f0xx.o + 0x2000024c 0x00000008 Data RW 292 .data RTX_CM0.lib(rt_cmsis.o) + 0x20000254 0x00000008 Data RW 831 .data RTX_CM0.lib(rt_task.o) + 0x2000025c 0x00000008 Data RW 916 .data RTX_CM0.lib(rt_system.o) + 0x20000264 0x00000004 Data RW 1210 .data RTX_CM0.lib(rt_time.o) + 0x20000268 0x00000008 Data RW 1349 .data RTX_CM0.lib(rt_robin.o) + 0x20000270 0x0000016a Zero RW 4 .bss rtx_blinky.o + 0x200003da 0x00000006 PAD + 0x200003e0 0x000004a8 Zero RW 135 .bss rtx_conf_cm.o + 0x20000888 0x00000034 Zero RW 830 .bss RTX_CM0.lib(rt_task.o) + 0x200008bc 0x00000030 Zero RW 1050 .bss RTX_CM0.lib(rt_list.o) + 0x200008ec 0x00000004 PAD + 0x200008f0 0x00000400 Zero RW 162 STACK startup_stm32f072xb.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 104 4 0 0 0 1040 buttons_stm32f072-discovery.o + 116 8 0 0 0 841 dac_drv.o + 228 14 16 0 0 2268 led_stm32f072-discovery.o + 476 34 16 550 362 10679 rtx_blinky.o + 62 6 86 32 1192 7338 rtx_conf_cm.o + 28 8 192 0 1024 672 startup_stm32f072xb.o + 324 34 16 4 0 1703 system_stm32f0xx.o + + ---------------------------------------------------------------------- + 1340 108 360 588 2584 24541 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 2 0 2 2 6 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 134 14 0 0 0 1663 hal_cm.o + 356 40 0 0 0 832 hal_cm0.o + 1298 156 0 8 0 31456 rt_cmsis.o + 144 12 0 0 0 1359 rt_event.o + 524 34 0 0 48 7993 rt_list.o + 510 16 0 0 0 3781 rt_mailbox.o + 140 0 0 0 0 1933 rt_membox.o + 142 0 0 0 0 2283 rt_memory.o + 92 22 0 8 0 1102 rt_robin.o + 52 4 0 0 0 545 rt_semaphore.o + 290 54 0 8 0 5967 rt_system.o + 1116 178 0 8 52 9149 rt_task.o + 0 0 0 4 0 206 rt_time.o + 4 4 0 0 0 200 svc_table.o + 58 0 0 0 0 0 __dczerorl.o + 0 0 0 0 0 0 entry.o + 0 0 0 0 0 0 entry10a.o + 0 0 0 0 0 0 entry11a.o + 8 4 0 0 0 0 entry2.o + 4 0 0 0 0 0 entry5.o + 0 0 0 0 0 0 entry7b.o + 0 0 0 0 0 0 entry8b.o + 30 0 0 0 0 0 handlers.o + 36 8 0 0 0 68 init.o + 44 0 0 0 0 72 uidiv.o + + ---------------------------------------------------------------------- + 4992 546 0 36 104 68609 Library Totals + 10 0 0 0 4 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 4802 534 0 36 100 68469 RTX_CM0.lib + 180 12 0 0 0 140 mc_p.l + + ---------------------------------------------------------------------- + 4992 546 0 36 104 68609 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 6332 654 360 624 2688 90022 Grand Totals + 6332 654 360 556 2688 90022 ELF Image Totals (compressed) + 6332 654 360 556 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 6692 ( 6.54kB) + Total RW Size (RW Data + ZI Data) 3312 ( 3.23kB) + Total ROM Size (Code + RO Data + RW Data) 7248 ( 7.08kB) + +============================================================================== + diff --git a/RTX_Blinky/Flash/RTX_Blinky.sct b/RTX_Blinky/Flash/RTX_Blinky.sct new file mode 100644 index 0000000..404c8cb --- /dev/null +++ b/RTX_Blinky/Flash/RTX_Blinky.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/RTX_Blinky/Flash/RTX_Blinky_STM32F072 Flash.dep b/RTX_Blinky/Flash/RTX_Blinky_STM32F072 Flash.dep new file mode 100644 index 0000000..1eb0267 --- /dev/null +++ b/RTX_Blinky/Flash/RTX_Blinky_STM32F072 Flash.dep @@ -0,0 +1,62 @@ +Dependencies for Project 'RTX_Blinky', Target 'STM32F072 Flash': (DO NOT MODIFY !) +F (.\RTX_Blinky.c)(0x571E1F37)(-c --cpu Cortex-M0 -D__RTX -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork -I C:\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX_Blinky\RTE -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC -I C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board -I C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include -D__UVISION_VERSION="517" -D_RTE_ -DSTM32F072xB -o .\flash\rtx_blinky.o --omf_browse .\flash\rtx_blinky.crf --depend .\flash\rtx_blinky.d) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC\cmsis_os.h)(0x562747DE) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x55DB2B80) +I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x55DB2B7E) +I (C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board\Board_LED.h)(0x53BB2252) +I (C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board\Board_Buttons.h)(0x53BB2252) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h)(0x5625B70C) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h)(0x56E9F63A) +I (DAC_DRV.h)(0x571CD19D) +F (.\DAC_DRV.c)(0x570658C5)(-c --cpu Cortex-M0 -D__RTX -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork -I C:\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX_Blinky\RTE -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC -I C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board -I C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include -D__UVISION_VERSION="517" -D_RTE_ -DSTM32F072xB -o .\flash\dac_drv.o --omf_browse .\flash\dac_drv.crf --depend .\flash\dac_drv.d) +I (DAC_DRV.h)(0x571CD19D) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h)(0x5625B70C) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x55DB2B80) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h)(0x56E9F63A) +F (.\Abstract.txt)(0x54E42660)() +F (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Boards\ST\STM32F072-Discovery\Common\Buttons_STM32F072-Discovery.c)(0x54E42660)(-c --cpu Cortex-M0 -D__RTX -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork -I C:\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX_Blinky\RTE -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC -I C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board -I C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include -D__UVISION_VERSION="517" -D_RTE_ -DSTM32F072xB -o .\flash\buttons_stm32f072-discovery.o --omf_browse .\flash\buttons_stm32f072-discovery.crf --depend .\flash\buttons_stm32f072-discovery.d) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h)(0x5625B70C) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x55DB2B80) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board\Board_Buttons.h)(0x53BB2252) +F (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Boards\ST\STM32F072-Discovery\Common\LED_STM32F072-Discovery.c)(0x54E42660)(-c --cpu Cortex-M0 -D__RTX -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork -I C:\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX_Blinky\RTE -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC -I C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board -I C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include -D__UVISION_VERSION="517" -D_RTE_ -DSTM32F072xB -o .\flash\led_stm32f072-discovery.o --omf_browse .\flash\led_stm32f072-discovery.crf --depend .\flash\led_stm32f072-discovery.d) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h)(0x5625B70C) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x55DB2B80) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board\Board_LED.h)(0x53BB2252) +F (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\LIB\ARM\RTX_CM0.lib)(0x56245D06)() +F (RTE\CMSIS\RTX_Conf_CM.c)(0x56E9F63A)(-c --cpu Cortex-M0 -D__RTX -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork -I C:\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX_Blinky\RTE -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC -I C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board -I C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include -D__UVISION_VERSION="517" -D_RTE_ -DSTM32F072xB -o .\flash\rtx_conf_cm.o --omf_browse .\flash\rtx_conf_cm.crf --depend .\flash\rtx_conf_cm.d) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC\cmsis_os.h)(0x562747DE) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x55DB2B80) +I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x55DB2B7E) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC\RTX_CM_lib.h)(0x556D30E4) +F (RTE\Device\STM32F072RB\startup_stm32f072xb.s)(0x56E9F63A)(--cpu Cortex-M0 --pd "__RTX SETA 1" --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I C:\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX_Blinky\RTE -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC -I C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board -I C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include --pd "__UVISION_VERSION SETA 517" --pd "_RTE_ SETA 1" --pd "STM32F072xB SETA 1" --list .\flash\startup_stm32f072xb.lst --xref -o .\flash\startup_stm32f072xb.o --depend .\flash\startup_stm32f072xb.d) +F (RTE\Device\STM32F072RB\system_stm32f0xx.c)(0x56E9F63A)(-c --cpu Cortex-M0 -D__RTX -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork -I C:\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX_Blinky\RTE -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC -I C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board -I C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include -D__UVISION_VERSION="517" -D_RTE_ -DSTM32F072xB -o .\flash\system_stm32f0xx.o --omf_browse .\flash\system_stm32f0xx.crf --depend .\flash\system_stm32f0xx.d) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h)(0x56E9F63A) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h)(0x5625B70C) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x55DB2B80) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h)(0x5625A350) +I (C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h)(0x56E9F63A) diff --git a/RTX_Blinky/Flash/buttons_stm32f072-discovery.crf b/RTX_Blinky/Flash/buttons_stm32f072-discovery.crf new file mode 100644 index 0000000..ce8db0a Binary files /dev/null and b/RTX_Blinky/Flash/buttons_stm32f072-discovery.crf differ diff --git a/RTX_Blinky/Flash/buttons_stm32f072-discovery.d b/RTX_Blinky/Flash/buttons_stm32f072-discovery.d new file mode 100644 index 0000000..2f6bb87 --- /dev/null +++ b/RTX_Blinky/Flash/buttons_stm32f072-discovery.d @@ -0,0 +1,10 @@ +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Boards\ST\STM32F072-Discovery\Common\Buttons_STM32F072-Discovery.c +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h +.\flash\buttons_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board\Board_Buttons.h diff --git a/RTX_Blinky/Flash/buttons_stm32f072-discovery.o b/RTX_Blinky/Flash/buttons_stm32f072-discovery.o new file mode 100644 index 0000000..ad22d3a Binary files /dev/null and b/RTX_Blinky/Flash/buttons_stm32f072-discovery.o differ diff --git a/RTX_Blinky/Flash/dac_drv.crf b/RTX_Blinky/Flash/dac_drv.crf new file mode 100644 index 0000000..72515a8 Binary files /dev/null and b/RTX_Blinky/Flash/dac_drv.crf differ diff --git a/RTX_Blinky/Flash/dac_drv.d b/RTX_Blinky/Flash/dac_drv.d new file mode 100644 index 0000000..e5c5b7f --- /dev/null +++ b/RTX_Blinky/Flash/dac_drv.d @@ -0,0 +1,10 @@ +.\flash\dac_drv.o: DAC_DRV.c +.\flash\dac_drv.o: DAC_DRV.h +.\flash\dac_drv.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h +.\flash\dac_drv.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h +.\flash\dac_drv.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h +.\flash\dac_drv.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\flash\dac_drv.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h +.\flash\dac_drv.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h +.\flash\dac_drv.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h +.\flash\dac_drv.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h diff --git a/RTX_Blinky/Flash/dac_drv.o b/RTX_Blinky/Flash/dac_drv.o new file mode 100644 index 0000000..80151e5 Binary files /dev/null and b/RTX_Blinky/Flash/dac_drv.o differ diff --git a/RTX_Blinky/Flash/led_stm32f072-discovery.crf b/RTX_Blinky/Flash/led_stm32f072-discovery.crf new file mode 100644 index 0000000..07e2f3c Binary files /dev/null and b/RTX_Blinky/Flash/led_stm32f072-discovery.crf differ diff --git a/RTX_Blinky/Flash/led_stm32f072-discovery.d b/RTX_Blinky/Flash/led_stm32f072-discovery.d new file mode 100644 index 0000000..adf47f9 --- /dev/null +++ b/RTX_Blinky/Flash/led_stm32f072-discovery.d @@ -0,0 +1,10 @@ +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Boards\ST\STM32F072-Discovery\Common\LED_STM32F072-Discovery.c +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h +.\flash\led_stm32f072-discovery.o: C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board\Board_LED.h diff --git a/RTX_Blinky/Flash/led_stm32f072-discovery.o b/RTX_Blinky/Flash/led_stm32f072-discovery.o new file mode 100644 index 0000000..0d22f24 Binary files /dev/null and b/RTX_Blinky/Flash/led_stm32f072-discovery.o differ diff --git a/RTX_Blinky/Flash/rtx_blinky.crf b/RTX_Blinky/Flash/rtx_blinky.crf new file mode 100644 index 0000000..01ac06f Binary files /dev/null and b/RTX_Blinky/Flash/rtx_blinky.crf differ diff --git a/RTX_Blinky/Flash/rtx_blinky.d b/RTX_Blinky/Flash/rtx_blinky.d new file mode 100644 index 0000000..78d0b37 --- /dev/null +++ b/RTX_Blinky/Flash/rtx_blinky.d @@ -0,0 +1,14 @@ +.\flash\rtx_blinky.o: RTX_Blinky.c +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC\cmsis_os.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board\Board_LED.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.0.0\Board\Board_Buttons.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h +.\flash\rtx_blinky.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h +.\flash\rtx_blinky.o: DAC_DRV.h diff --git a/RTX_Blinky/Flash/rtx_blinky.o b/RTX_Blinky/Flash/rtx_blinky.o new file mode 100644 index 0000000..3855dc5 Binary files /dev/null and b/RTX_Blinky/Flash/rtx_blinky.o differ diff --git a/RTX_Blinky/Flash/rtx_conf_cm.crf b/RTX_Blinky/Flash/rtx_conf_cm.crf new file mode 100644 index 0000000..7de9d8e Binary files /dev/null and b/RTX_Blinky/Flash/rtx_conf_cm.crf differ diff --git a/RTX_Blinky/Flash/rtx_conf_cm.d b/RTX_Blinky/Flash/rtx_conf_cm.d new file mode 100644 index 0000000..2d636ee --- /dev/null +++ b/RTX_Blinky/Flash/rtx_conf_cm.d @@ -0,0 +1,5 @@ +.\flash\rtx_conf_cm.o: RTE\CMSIS\RTX_Conf_CM.c +.\flash\rtx_conf_cm.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC\cmsis_os.h +.\flash\rtx_conf_cm.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\flash\rtx_conf_cm.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.h +.\flash\rtx_conf_cm.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC\RTX_CM_lib.h diff --git a/RTX_Blinky/Flash/rtx_conf_cm.o b/RTX_Blinky/Flash/rtx_conf_cm.o new file mode 100644 index 0000000..1788c9e Binary files /dev/null and b/RTX_Blinky/Flash/rtx_conf_cm.o differ diff --git a/RTX_Blinky/Flash/startup_stm32f072xb.d b/RTX_Blinky/Flash/startup_stm32f072xb.d new file mode 100644 index 0000000..3da6920 --- /dev/null +++ b/RTX_Blinky/Flash/startup_stm32f072xb.d @@ -0,0 +1 @@ +.\flash\startup_stm32f072xb.o: RTE\Device\STM32F072RB\startup_stm32f072xb.s diff --git a/RTX_Blinky/Flash/startup_stm32f072xb.lst b/RTX_Blinky/Flash/startup_stm32f072xb.lst new file mode 100644 index 0000000..fdf5f8d --- /dev/null +++ b/RTX_Blinky/Flash/startup_stm32f072xb.lst @@ -0,0 +1,984 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2016 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f072xb.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Version : V2.2.3 + 5 00000000 ;* Date : 29-January-2016 + 6 00000000 ;* Description : STM32F072x8/STM32F072xB devices + vector table for MDK-ARM toolchain. + 7 00000000 ;* This module performs: + 8 00000000 ;* - Set the initial SP + 9 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 10 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 11 00000000 ;* - Branches to __main in the C li + brary (which eventually + 12 00000000 ;* calls main()). + 13 00000000 ;* After Reset the CortexM0 process + or is in Thread mode, + 14 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 15 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 16 00000000 ;******************************************************* + ************************ + 17 00000000 ;* + 18 00000000 ;* Redistribution and use in source and binary forms, wi + th or without modification, + 19 00000000 ;* are permitted provided that the following conditions + are met: + 20 00000000 ;* 1. Redistributions of source code must retain the a + bove copyright notice, + 21 00000000 ;* this list of conditions and the following discla + imer. + 22 00000000 ;* 2. Redistributions in binary form must reproduce th + e above copyright notice, + 23 00000000 ;* this list of conditions and the following discla + imer in the documentation + 24 00000000 ;* and/or other materials provided with the distrib + ution. + 25 00000000 ;* 3. Neither the name of STMicroelectronics nor the n + ames of its contributors + 26 00000000 ;* may be used to endorse or promote products deriv + ed from this software + 27 00000000 ;* without specific prior written permission. + 28 00000000 ;* + 29 00000000 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AN + D CONTRIBUTORS "AS IS" + 30 00000000 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT + NOT LIMITED TO, THE + 31 00000000 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE + 32 00000000 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + CONTRIBUTORS BE LIABLE + 33 00000000 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPL + ARY, OR CONSEQUENTIAL + 34 00000000 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT O + F SUBSTITUTE GOODS OR + 35 00000000 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER + + + +ARM Macro Assembler Page 2 + + + 36 00000000 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CON + TRACT, STRICT LIABILITY, + 37 00000000 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING I + N ANY WAY OUT OF THE USE + 38 00000000 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + OF SUCH DAMAGE. + 39 00000000 ; + 40 00000000 ;******************************************************* + ************************ + 41 00000000 + 42 00000000 ; Amount of memory (in bytes) allocated for Stack + 43 00000000 ; Tailor this value to your application needs + 44 00000000 ; Stack Configuration + 45 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 46 00000000 ; + 47 00000000 + 48 00000000 00000400 + Stack_Size + EQU 0x00000400 + 49 00000000 + 50 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 51 00000000 Stack_Mem + SPACE Stack_Size + 52 00000400 __initial_sp + 53 00000400 + 54 00000400 + 55 00000400 ; Heap Configuration + 56 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 57 00000400 ; + 58 00000400 + 59 00000400 00000200 + Heap_Size + EQU 0x00000200 + 60 00000400 + 61 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 62 00000000 __heap_base + 63 00000000 Heap_Mem + SPACE Heap_Size + 64 00000200 __heap_limit + 65 00000200 + 66 00000200 PRESERVE8 + 67 00000200 THUMB + 68 00000200 + 69 00000200 + 70 00000200 ; Vector Table Mapped to Address 0 at Reset + 71 00000200 AREA RESET, DATA, READONLY + 72 00000000 EXPORT __Vectors + 73 00000000 EXPORT __Vectors_End + 74 00000000 EXPORT __Vectors_Size + 75 00000000 + 76 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 77 00000004 00000000 DCD Reset_Handler ; Reset Handler + 78 00000008 00000000 DCD NMI_Handler ; NMI Handler + 79 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + + + +ARM Macro Assembler Page 3 + + + 80 00000010 00000000 DCD 0 ; Reserved + 81 00000014 00000000 DCD 0 ; Reserved + 82 00000018 00000000 DCD 0 ; Reserved + 83 0000001C 00000000 DCD 0 ; Reserved + 84 00000020 00000000 DCD 0 ; Reserved + 85 00000024 00000000 DCD 0 ; Reserved + 86 00000028 00000000 DCD 0 ; Reserved + 87 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 88 00000030 00000000 DCD 0 ; Reserved + 89 00000034 00000000 DCD 0 ; Reserved + 90 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 91 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 92 00000040 + 93 00000040 ; External Interrupts + 94 00000040 00000000 DCD WWDG_IRQHandler + ; Window Watchdog + 95 00000044 00000000 DCD PVD_VDDIO2_IRQHandler ; PVD thr + ough EXTI Line dete + ct + 96 00000048 00000000 DCD RTC_IRQHandler ; RTC through EX + TI Line + 97 0000004C 00000000 DCD FLASH_IRQHandler ; FLASH + 98 00000050 00000000 DCD RCC_CRS_IRQHandler + ; RCC and CRS + 99 00000054 00000000 DCD EXTI0_1_IRQHandler + ; EXTI Line 0 and 1 + + 100 00000058 00000000 DCD EXTI2_3_IRQHandler + ; EXTI Line 2 and 3 + + 101 0000005C 00000000 DCD EXTI4_15_IRQHandler + ; EXTI Line 4 to 15 + + 102 00000060 00000000 DCD TSC_IRQHandler ; TS + 103 00000064 00000000 DCD DMA1_Channel1_IRQHandler + ; DMA1 Channel 1 + 104 00000068 00000000 DCD DMA1_Channel2_3_IRQHandler ; DM + A1 Channel 2 and Ch + annel 3 + 105 0000006C 00000000 DCD DMA1_Channel4_5_6_7_IRQHandler + ; DMA1 Channel 4, C + hannel 5, Channel 6 + and Channel 7 + 106 00000070 00000000 DCD ADC1_COMP_IRQHandler ; ADC1, CO + MP1 and COMP2 + 107 00000074 00000000 DCD TIM1_BRK_UP_TRG_COM_IRQHandler + ; TIM1 Break, Updat + e, Trigger and Comm + utation + 108 00000078 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + 109 0000007C 00000000 DCD TIM2_IRQHandler ; TIM2 + 110 00000080 00000000 DCD TIM3_IRQHandler ; TIM3 + 111 00000084 00000000 DCD TIM6_DAC_IRQHandler + ; TIM6 and DAC + 112 00000088 00000000 DCD TIM7_IRQHandler ; TIM7 + 113 0000008C 00000000 DCD TIM14_IRQHandler ; TIM14 + + + +ARM Macro Assembler Page 4 + + + 114 00000090 00000000 DCD TIM15_IRQHandler ; TIM15 + 115 00000094 00000000 DCD TIM16_IRQHandler ; TIM16 + 116 00000098 00000000 DCD TIM17_IRQHandler ; TIM17 + 117 0000009C 00000000 DCD I2C1_IRQHandler ; I2C1 + 118 000000A0 00000000 DCD I2C2_IRQHandler ; I2C2 + 119 000000A4 00000000 DCD SPI1_IRQHandler ; SPI1 + 120 000000A8 00000000 DCD SPI2_IRQHandler ; SPI2 + 121 000000AC 00000000 DCD USART1_IRQHandler ; USART1 + 122 000000B0 00000000 DCD USART2_IRQHandler ; USART2 + 123 000000B4 00000000 DCD USART3_4_IRQHandler + ; USART3 & USART4 + 124 000000B8 00000000 DCD CEC_CAN_IRQHandler + ; CEC and CAN + 125 000000BC 00000000 DCD USB_IRQHandler ; USB + 126 000000C0 + 127 000000C0 __Vectors_End + 128 000000C0 + 129 000000C0 000000C0 + __Vectors_Size + EQU __Vectors_End - __Vectors + 130 000000C0 + 131 000000C0 AREA |.text|, CODE, READONLY + 132 00000000 + 133 00000000 ; Reset handler routine + 134 00000000 Reset_Handler + PROC + 135 00000000 EXPORT Reset_Handler [ +WEAK] + 136 00000000 IMPORT __main + 137 00000000 IMPORT SystemInit + 138 00000000 4804 LDR R0, =SystemInit + 139 00000002 4780 BLX R0 + 140 00000004 4804 LDR R0, =__main + 141 00000006 4700 BX R0 + 142 00000008 ENDP + 143 00000008 + 144 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 145 00000008 + 146 00000008 NMI_Handler + PROC + 147 00000008 EXPORT NMI_Handler +[WEAK] + 148 00000008 E7FE B . + 149 0000000A ENDP + 151 0000000A HardFault_Handler + PROC + 152 0000000A EXPORT HardFault_Handler +[WEAK] + 153 0000000A E7FE B . + 154 0000000C ENDP + 155 0000000C SVC_Handler + PROC + 156 0000000C EXPORT SVC_Handler +[WEAK] + 157 0000000C E7FE B . + 158 0000000E ENDP + 159 0000000E PendSV_Handler + PROC + + + +ARM Macro Assembler Page 5 + + + 160 0000000E EXPORT PendSV_Handler +[WEAK] + 161 0000000E E7FE B . + 162 00000010 ENDP + 163 00000010 SysTick_Handler + PROC + 164 00000010 EXPORT SysTick_Handler +[WEAK] + 165 00000010 E7FE B . + 166 00000012 ENDP + 167 00000012 + 168 00000012 Default_Handler + PROC + 169 00000012 + 170 00000012 EXPORT WWDG_IRQHandler +[WEAK] + 171 00000012 EXPORT PVD_VDDIO2_IRQHandler +[WEAK] + 172 00000012 EXPORT RTC_IRQHandler +[WEAK] + 173 00000012 EXPORT FLASH_IRQHandler +[WEAK] + 174 00000012 EXPORT RCC_CRS_IRQHandler +[WEAK] + 175 00000012 EXPORT EXTI0_1_IRQHandler +[WEAK] + 176 00000012 EXPORT EXTI2_3_IRQHandler +[WEAK] + 177 00000012 EXPORT EXTI4_15_IRQHandler +[WEAK] + 178 00000012 EXPORT TSC_IRQHandler +[WEAK] + 179 00000012 EXPORT DMA1_Channel1_IRQHandler +[WEAK] + 180 00000012 EXPORT DMA1_Channel2_3_IRQHandler +[WEAK] + 181 00000012 EXPORT DMA1_Channel4_5_6_7_IRQHandler +[WEAK] + 182 00000012 EXPORT ADC1_COMP_IRQHandler +[WEAK] + 183 00000012 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler +[WEAK] + 184 00000012 EXPORT TIM1_CC_IRQHandler +[WEAK] + 185 00000012 EXPORT TIM2_IRQHandler +[WEAK] + 186 00000012 EXPORT TIM3_IRQHandler +[WEAK] + 187 00000012 EXPORT TIM6_DAC_IRQHandler +[WEAK] + 188 00000012 EXPORT TIM7_IRQHandler +[WEAK] + 189 00000012 EXPORT TIM14_IRQHandler +[WEAK] + 190 00000012 EXPORT TIM15_IRQHandler +[WEAK] + 191 00000012 EXPORT TIM16_IRQHandler +[WEAK] + 192 00000012 EXPORT TIM17_IRQHandler + + + +ARM Macro Assembler Page 6 + + +[WEAK] + 193 00000012 EXPORT I2C1_IRQHandler +[WEAK] + 194 00000012 EXPORT I2C2_IRQHandler +[WEAK] + 195 00000012 EXPORT SPI1_IRQHandler +[WEAK] + 196 00000012 EXPORT SPI2_IRQHandler +[WEAK] + 197 00000012 EXPORT USART1_IRQHandler +[WEAK] + 198 00000012 EXPORT USART2_IRQHandler +[WEAK] + 199 00000012 EXPORT USART3_4_IRQHandler +[WEAK] + 200 00000012 EXPORT CEC_CAN_IRQHandler +[WEAK] + 201 00000012 EXPORT USB_IRQHandler +[WEAK] + 202 00000012 + 203 00000012 + 204 00000012 WWDG_IRQHandler + 205 00000012 PVD_VDDIO2_IRQHandler + 206 00000012 RTC_IRQHandler + 207 00000012 FLASH_IRQHandler + 208 00000012 RCC_CRS_IRQHandler + 209 00000012 EXTI0_1_IRQHandler + 210 00000012 EXTI2_3_IRQHandler + 211 00000012 EXTI4_15_IRQHandler + 212 00000012 TSC_IRQHandler + 213 00000012 DMA1_Channel1_IRQHandler + 214 00000012 DMA1_Channel2_3_IRQHandler + 215 00000012 DMA1_Channel4_5_6_7_IRQHandler + 216 00000012 ADC1_COMP_IRQHandler + 217 00000012 TIM1_BRK_UP_TRG_COM_IRQHandler + 218 00000012 TIM1_CC_IRQHandler + 219 00000012 TIM2_IRQHandler + 220 00000012 TIM3_IRQHandler + 221 00000012 TIM6_DAC_IRQHandler + 222 00000012 TIM7_IRQHandler + 223 00000012 TIM14_IRQHandler + 224 00000012 TIM15_IRQHandler + 225 00000012 TIM16_IRQHandler + 226 00000012 TIM17_IRQHandler + 227 00000012 I2C1_IRQHandler + 228 00000012 I2C2_IRQHandler + 229 00000012 SPI1_IRQHandler + 230 00000012 SPI2_IRQHandler + 231 00000012 USART1_IRQHandler + 232 00000012 USART2_IRQHandler + 233 00000012 USART3_4_IRQHandler + 234 00000012 CEC_CAN_IRQHandler + 235 00000012 USB_IRQHandler + 236 00000012 + 237 00000012 E7FE B . + 238 00000014 + 239 00000014 ENDP + 240 00000014 + 241 00000014 ALIGN + + + +ARM Macro Assembler Page 7 + + + 242 00000014 + 243 00000014 ;******************************************************* + ************************ + 244 00000014 ; User Stack and Heap initialization + 245 00000014 ;******************************************************* + ************************ + 246 00000014 IF :DEF:__MICROLIB + 247 00000014 + 248 00000014 EXPORT __initial_sp + 249 00000014 EXPORT __heap_base + 250 00000014 EXPORT __heap_limit + 251 00000014 + 252 00000014 ELSE + 267 ENDIF + 268 00000014 + 269 00000014 END + 00000000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw +ork --depend=.\flash\startup_stm32f072xb.d -o.\flash\startup_stm32f072xb.o -IC: +\Users\tiongpatrick\Documents\STM32F0\Example\Boards\ST\STM32F072-Discovery\RTX +_Blinky\RTE -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include -IC:\Keil_v5\AR +M\PACK\ARM\CMSIS\4.5.0\CMSIS\RTOS\RTX\INC -IC:\Keil_v5\ARM\PACK\Keil\MDK-Middle +ware\7.0.0\Board -IC:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include +--predefine="__RTX SETA 1" --predefine="__EVAL SETA 1" --predefine="__MICROLIB +SETA 1" --predefine="__UVISION_VERSION SETA 517" --predefine="_RTE_ SETA 1" --p +redefine="STM32F072xB SETA 1" --list=.\flash\startup_stm32f072xb.lst RTE\Device +\STM32F072RB\startup_stm32f072xb.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 50 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 51 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 52 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 76 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 248 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 61 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 63 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 62 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 249 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s +Comment: __heap_base used once +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 64 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 250 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 71 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 76 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 72 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 129 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +__Vectors_End 000000C0 + +Symbol: __Vectors_End + Definitions + At line 127 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 73 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 129 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 131 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + None +Comment: .text unused +ADC1_COMP_IRQHandler 00000012 + +Symbol: ADC1_COMP_IRQHandler + Definitions + At line 216 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 106 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 182 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +CEC_CAN_IRQHandler 00000012 + +Symbol: CEC_CAN_IRQHandler + Definitions + At line 234 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 124 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 200 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +DMA1_Channel1_IRQHandler 00000012 + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 213 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 103 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 179 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +DMA1_Channel2_3_IRQHandler 00000012 + +Symbol: DMA1_Channel2_3_IRQHandler + Definitions + At line 214 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 104 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 180 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +DMA1_Channel4_5_6_7_IRQHandler 00000012 + +Symbol: DMA1_Channel4_5_6_7_IRQHandler + Definitions + At line 215 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 105 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 181 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +Default_Handler 00000012 + +Symbol: Default_Handler + Definitions + At line 168 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + None +Comment: Default_Handler unused +EXTI0_1_IRQHandler 00000012 + +Symbol: EXTI0_1_IRQHandler + Definitions + At line 209 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 99 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 175 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +EXTI2_3_IRQHandler 00000012 + +Symbol: EXTI2_3_IRQHandler + Definitions + At line 210 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 100 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 176 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +EXTI4_15_IRQHandler 00000012 + +Symbol: EXTI4_15_IRQHandler + Definitions + At line 211 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 101 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 177 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +FLASH_IRQHandler 00000012 + +Symbol: FLASH_IRQHandler + Definitions + At line 207 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 97 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 173 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 151 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 79 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 152 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +I2C1_IRQHandler 00000012 + +Symbol: I2C1_IRQHandler + Definitions + At line 227 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 117 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 193 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +I2C2_IRQHandler 00000012 + +Symbol: I2C2_IRQHandler + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 228 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 118 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 194 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 146 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 78 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 147 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +PVD_VDDIO2_IRQHandler 00000012 + +Symbol: PVD_VDDIO2_IRQHandler + Definitions + At line 205 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 95 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 171 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +PendSV_Handler 0000000E + +Symbol: PendSV_Handler + Definitions + At line 159 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 90 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 160 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +RCC_CRS_IRQHandler 00000012 + +Symbol: RCC_CRS_IRQHandler + Definitions + At line 208 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 98 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 174 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +RTC_IRQHandler 00000012 + +Symbol: RTC_IRQHandler + Definitions + At line 206 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 96 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 172 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 134 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 77 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 135 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +SPI1_IRQHandler 00000012 + +Symbol: SPI1_IRQHandler + Definitions + At line 229 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 119 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 195 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +SPI2_IRQHandler 00000012 + +Symbol: SPI2_IRQHandler + Definitions + At line 230 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 120 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 196 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +SVC_Handler 0000000C + +Symbol: SVC_Handler + Definitions + At line 155 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 87 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 156 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +SysTick_Handler 00000010 + +Symbol: SysTick_Handler + Definitions + At line 163 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 91 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 164 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TIM14_IRQHandler 00000012 + +Symbol: TIM14_IRQHandler + Definitions + At line 223 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 113 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 189 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TIM15_IRQHandler 00000012 + +Symbol: TIM15_IRQHandler + Definitions + At line 224 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 114 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 190 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TIM16_IRQHandler 00000012 + +Symbol: TIM16_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 225 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 115 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 191 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TIM17_IRQHandler 00000012 + +Symbol: TIM17_IRQHandler + Definitions + At line 226 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 116 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 192 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TIM1_BRK_UP_TRG_COM_IRQHandler 00000012 + +Symbol: TIM1_BRK_UP_TRG_COM_IRQHandler + Definitions + At line 217 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 107 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 183 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TIM1_CC_IRQHandler 00000012 + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 218 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 108 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 184 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TIM2_IRQHandler 00000012 + +Symbol: TIM2_IRQHandler + Definitions + At line 219 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 109 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 185 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TIM3_IRQHandler 00000012 + +Symbol: TIM3_IRQHandler + Definitions + At line 220 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 110 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 186 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TIM6_DAC_IRQHandler 00000012 + +Symbol: TIM6_DAC_IRQHandler + Definitions + At line 221 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 111 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 187 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +TIM7_IRQHandler 00000012 + +Symbol: TIM7_IRQHandler + Definitions + At line 222 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 112 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 188 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +TSC_IRQHandler 00000012 + +Symbol: TSC_IRQHandler + Definitions + At line 212 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 102 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 178 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +USART1_IRQHandler 00000012 + +Symbol: USART1_IRQHandler + Definitions + At line 231 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 121 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 197 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +USART2_IRQHandler 00000012 + +Symbol: USART2_IRQHandler + Definitions + At line 232 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 122 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 198 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +USART3_4_IRQHandler 00000012 + +Symbol: USART3_4_IRQHandler + Definitions + At line 233 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 123 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 199 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +USB_IRQHandler 00000012 + +Symbol: USB_IRQHandler + Definitions + At line 235 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 125 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 201 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +WWDG_IRQHandler 00000012 + +Symbol: WWDG_IRQHandler + Definitions + At line 204 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 94 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + At line 170 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + +40 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 59 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 63 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s +Comment: Heap_Size used once +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 48 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 51 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s +Comment: Stack_Size used once +__Vectors_Size 000000C0 + +Symbol: __Vectors_Size + Definitions + At line 129 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 74 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 137 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 138 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 136 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s + Uses + At line 140 in file RTE\Device\STM32F072RB\startup_stm32f072xb.s +Comment: __main used once +2 symbols +393 symbols in table diff --git a/RTX_Blinky/Flash/startup_stm32f072xb.o b/RTX_Blinky/Flash/startup_stm32f072xb.o new file mode 100644 index 0000000..d48b536 Binary files /dev/null and b/RTX_Blinky/Flash/startup_stm32f072xb.o differ diff --git a/RTX_Blinky/Flash/system_stm32f0xx.crf b/RTX_Blinky/Flash/system_stm32f0xx.crf new file mode 100644 index 0000000..6bcffe3 Binary files /dev/null and b/RTX_Blinky/Flash/system_stm32f0xx.crf differ diff --git a/RTX_Blinky/Flash/system_stm32f0xx.d b/RTX_Blinky/Flash/system_stm32f0xx.d new file mode 100644 index 0000000..843282c --- /dev/null +++ b/RTX_Blinky/Flash/system_stm32f0xx.d @@ -0,0 +1,9 @@ +.\flash\system_stm32f0xx.o: RTE\Device\STM32F072RB\system_stm32f0xx.c +.\flash\system_stm32f0xx.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f0xx.h +.\flash\system_stm32f0xx.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\stm32f072xb.h +.\flash\system_stm32f0xx.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cm0.h +.\flash\system_stm32f0xx.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\flash\system_stm32f0xx.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmInstr.h +.\flash\system_stm32f0xx.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\cmsis_armcc.h +.\flash\system_stm32f0xx.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.5.0\CMSIS\Include\core_cmFunc.h +.\flash\system_stm32f0xx.o: C:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include\system_stm32f0xx.h diff --git a/RTX_Blinky/Flash/system_stm32f0xx.o b/RTX_Blinky/Flash/system_stm32f0xx.o new file mode 100644 index 0000000..015ce8e Binary files /dev/null and b/RTX_Blinky/Flash/system_stm32f0xx.o differ diff --git a/RTX_Blinky/RTE/CMSIS/RTX_Conf_CM.c b/RTX_Blinky/RTE/CMSIS/RTX_Conf_CM.c new file mode 100644 index 0000000..b920e92 --- /dev/null +++ b/RTX_Blinky/RTE/CMSIS/RTX_Conf_CM.c @@ -0,0 +1,313 @@ +/*---------------------------------------------------------------------------- + * CMSIS-RTOS - RTX + *---------------------------------------------------------------------------- + * Name: RTX_Conf_CM.C + * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M + * Rev.: V4.70.1 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "cmsis_os.h" + + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Thread Configuration +// ======================= +// +// Number of concurrent running user threads <1-250> +// Defines max. number of user threads that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 2 +#endif + +// Default Thread stack size [bytes] <64-4096:8><#/4> +// Defines default stack size for threads with osThreadDef stacksz = 0 +// Default: 200 +#ifndef OS_STKSIZE + #define OS_STKSIZE 50 // this stack size value is in words +#endif + +// Main Thread stack size [bytes] <64-32768:8><#/4> +// Defines stack size for main thread. +// Default: 200 +#ifndef OS_MAINSTKSIZE + #define OS_MAINSTKSIZE 50 // this stack size value is in words +#endif + +// Number of threads with user-provided stack size <0-250> +// Defines the number of threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4> +// Defines the combined stack size for threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVSTKSIZE + #define OS_PRIVSTKSIZE 0 // this stack size value is in words +#endif + +// Stack overflow checking +// Enable stack overflow checks at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Stack usage watermark +// Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer. +// Enabling this option increases significantly the execution time of osThreadCreate. +#ifndef OS_STKINIT +#define OS_STKINIT 0 +#endif + +// Processor mode for thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 1 +#endif + +// + +// RTX Kernel Timer Tick Configuration +// ====================================== +// Use Cortex-M SysTick timer as RTX Kernel Timer +// Cortex-M processors provide in most cases a SysTick timer that can be used as +// as time-base for RTX. +#ifndef OS_SYSTICK + #define OS_SYSTICK 1 +#endif +// +// RTOS Kernel Timer input clock frequency [Hz] <1-1000000000> +// Defines the input frequency of the RTOS Kernel Timer. +// When the Cortex-M SysTick timer is used, the input clock +// is on most systems identical with the core clock. +#ifndef OS_CLOCK + #define OS_CLOCK 48000000 +#endif + +// RTX Timer tick interval value [us] <1-1000000> +// The RTX Timer tick interval value is used to calculate timeout values. +// When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer. +// Default: 1000 (1ms) +#ifndef OS_TICK + #define OS_TICK 1000 +#endif + +// + +// System Configuration +// ======================= +// +// Round-Robin Thread switching +// =============================== +// +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Defines how long a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// User Timers +// ============== +// Enables user Timers +#ifndef OS_TIMERS + #define OS_TIMERS 1 +#endif + +// Timer Thread Priority +// <1=> Low +// <2=> Below Normal <3=> Normal <4=> Above Normal +// <5=> High +// <6=> Realtime (highest) +// Defines priority for Timer Thread +// Default: High +#ifndef OS_TIMERPRIO + #define OS_TIMERPRIO 5 +#endif + +// Timer Thread stack size [bytes] <64-4096:8><#/4> +// Defines stack size for Timer thread. +// Default: 200 +#ifndef OS_TIMERSTKSZ + #define OS_TIMERSTKSZ 50 // this stack size value is in words +#endif + +// Timer Callback Queue size <1-32> +// Number of concurrent active timer callback functions. +// Default: 4 +#ifndef OS_TIMERCBQS + #define OS_TIMERCBQS 4 +#endif + +// + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the interrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +/// \brief The idle demon is running when no other thread is ready to run +void os_idle_demon (void) { + + for (;;) { + /* HERE: include optional user code to be executed when no thread runs.*/ + } +} + +#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer + +/*--------------------------- os_tick_init ----------------------------------*/ + +/// \brief Initializes an alternative hardware timer as RTX kernel timer +/// \return IRQ number of the alternative hardware timer +int os_tick_init (void) { + return (-1); /* Return IRQ number of timer (0..239) */ +} + +/*--------------------------- os_tick_val -----------------------------------*/ + +/// \brief Get alternative hardware timer's current value (0 .. OS_TRV) +/// \return Current value of the alternative hardware timer +uint32_t os_tick_val (void) { + return (0); +} + +/*--------------------------- os_tick_ovf -----------------------------------*/ + +/// \brief Get alternative hardware timer's overflow flag +/// \return Overflow flag\n +/// - 1 : overflow +/// - 0 : no overflow +uint32_t os_tick_ovf (void) { + return (0); +} + +/*--------------------------- os_tick_irqack --------------------------------*/ + +/// \brief Acknowledge alternative hardware timer interrupt +void os_tick_irqack (void) { + /* ... */ +} + +#endif // (OS_SYSTICK == 0) + +/*--------------------------- os_error --------------------------------------*/ + +/* OS Error Codes */ +#define OS_ERROR_STACK_OVF 1 +#define OS_ERROR_FIFO_OVF 2 +#define OS_ERROR_MBX_OVF 3 +#define OS_ERROR_TIMER_OVF 4 + +extern osThreadId svcThreadGetId (void); + +/// \brief Called when a runtime error is detected +/// \param[in] error_code actual error code that has been detected +void os_error (uint32_t error_code) { + + /* HERE: include optional code to be executed on runtime error. */ + switch (error_code) { + case OS_ERROR_STACK_OVF: + /* Stack overflow detected for the currently running task. */ + /* Thread can be identified by calling svcThreadGetId(). */ + break; + case OS_ERROR_FIFO_OVF: + /* ISR FIFO Queue buffer overflow detected. */ + break; + case OS_ERROR_MBX_OVF: + /* Mailbox overflow detected. */ + break; + case OS_ERROR_TIMER_OVF: + /* User Timer Callback Queue overflow detected. */ + break; + default: + break; + } + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include "RTX_CM_lib.h" + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/RTX_Blinky/RTE/Device/STM32F072RB/startup_stm32f072xb.s b/RTX_Blinky/RTE/Device/STM32F072RB/startup_stm32f072xb.s new file mode 100644 index 0000000..23ba736 --- /dev/null +++ b/RTX_Blinky/RTE/Device/STM32F072RB/startup_stm32f072xb.s @@ -0,0 +1,271 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f072xb.s +;* Author : MCD Application Team +;* Version : V2.2.3 +;* Date : 29-January-2016 +;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD TIM7_IRQHandler ; TIM7 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 & USART4 + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_4_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_6_7_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_4_IRQHandler +CEC_CAN_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/RTX_Blinky/RTE/Device/STM32F072RB/system_stm32f0xx.c b/RTX_Blinky/RTE/Device/STM32F072RB/system_stm32f0xx.c new file mode 100644 index 0000000..83ba81a --- /dev/null +++ b/RTX_Blinky/RTE/Device/STM32F072RB/system_stm32f0xx.c @@ -0,0 +1,334 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @version V2.2.3 + * @date 29-January-2016 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F0xx device + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI48_VALUE */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock there is no need to + call the 2 first functions listed above, since SystemCoreClock variable is + updated automatically. + */ +uint32_t SystemCoreClock = 8000000; + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001U; + +#if defined (STM32F051x8) || defined (STM32F058x8) + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80CU; +#else + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ + RCC->CFGR &= (uint32_t)0x08FFB80CU; +#endif /* STM32F051x8 or STM32F058x8 */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFFU; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFFU; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFFU; + + /* Reset PREDIV[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; + +#if defined (STM32F072xB) || defined (STM32F078xx) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU; +#elif defined (STM32F071xB) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFCEACU; +#elif defined (STM32F091xC) || defined (STM32F098xx) + /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; +#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) + /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; +#elif defined (STM32F051x8) || defined (STM32F058xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEACU; +#elif defined (STM32F042x6) || defined (STM32F048xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU; +#elif defined (STM32F070x6) || defined (STM32F070xB) + /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU; + /* Set default USB clock to PLLCLK, since there is no HSI48 */ + RCC->CFGR3 |= (uint32_t)0x00000080U; +#else + #warning "No target selected" +#endif + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFEU; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000U; + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ + SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/RTX_Blinky/RTE/RTE_Components.h b/RTX_Blinky/RTE/RTE_Components.h new file mode 100644 index 0000000..8eb73bc --- /dev/null +++ b/RTX_Blinky/RTE/RTE_Components.h @@ -0,0 +1,16 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'RTX_Blinky' + * Target: 'STM32F072 Flash' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +#define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTX_Blinky/RTX_Blinky.c b/RTX_Blinky/RTX_Blinky.c new file mode 100644 index 0000000..6ffbebf --- /dev/null +++ b/RTX_Blinky/RTX_Blinky.c @@ -0,0 +1,176 @@ +/*---------------------------------------------------------------------------- + * Name: Blinky.c + * Purpose: LED Flasher + *---------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2015 Keil - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + + +#include "cmsis_os.h" // ARM::CMSIS:RTOS:Keil RTX + +#include "Board_LED.h" // ::Board Support:LED +#include "Board_Buttons.h" // ::Board Support:Buttons + +#include "stm32f0xx.h" // Device header +#include "DAC_DRV.h" + + +/*---------------------------------------------------------------------------- + * SystemCoreClockConfigure: configure SystemCoreClock using HSI + (HSE is not populated on Discovery board) + *----------------------------------------------------------------------------*/ +void SystemCoreClockConfigure(void) { + + RCC->CR |= ((uint32_t)RCC_CR_HSION); // Enable HSI + while ((RCC->CR & RCC_CR_HSIRDY) == 0); // Wait for HSI Ready + + RCC->CFGR = RCC_CFGR_SW_HSI; // HSI is system clock + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI); // Wait for HSI used as system clock + + FLASH->ACR = FLASH_ACR_PRFTBE; // Enable Prefetch Buffer + FLASH->ACR |= FLASH_ACR_LATENCY; // Flash 1 wait state + + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; // HCLK = SYSCLK + RCC->CFGR |= RCC_CFGR_PPRE_DIV1; // PCLK = HCLK + + RCC->CR &= ~RCC_CR_PLLON; // Disable PLL + + // PLL configuration: = HSI/2 * 12 = 48 MHz + RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL); +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + RCC->CFGR2 = (RCC_CFGR2_PREDIV_DIV2); + RCC->CFGR |= (RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLMUL12); +#else + /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + RCC->CFGR |= (RCC_CFGR_PLLSRC_HSI_DIV2 | RCC_CFGR_PLLMUL12); +#endif + + + RCC->CR |= RCC_CR_PLLON; // Enable PLL + while((RCC->CR & RCC_CR_PLLRDY) == 0) __NOP(); // Wait till PLL is ready + + RCC->CFGR &= ~RCC_CFGR_SW; // Select PLL as system clock source + RCC->CFGR |= RCC_CFGR_SW_PLL; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); // Wait till PLL is system clock src +} + + + +/*---------------------------------------------------------------------------- + * blinkLED: blink LED and check button state + *----------------------------------------------------------------------------*/ +void blinkLED(void const *argument) { + int32_t max_num = LED_GetCount(); + int32_t num = 0; + + for (;;) { + LED_On(num); // Turn specified LED on + osSignalWait(0x0001, osWaitForever); + LED_Off(num); // Turn specified LED off + osSignalWait(0x0001, osWaitForever); + + num++; // Change LED number + if (num >= max_num) { + num = 0; // Restart with first LED + } + } + +} + +osThreadId tid_blinkLED; +osThreadDef (blinkLED, osPriorityNormal, 1, 0); +uint16_t DAC_value[91] ={4095,4094,4093,4089,4085,4079,4073,4064,4055,4045, + 4033,4020,4006,3990,3973,3955,3936,3916,3895,3872, + 3848,3823,3797,3769,3741,3711,3681,3649,3616,3582, + 3546,3510,3473,3434,3395,3354,3313,3270,3227,3182, + 3137,3091,3043,2995,2946,2896,2845,2793,2740,2687, + 2632,2577,2521,2464,2407,2349,2290,2230,2170,2109, + 2048,1985,1922,1859,1795,1731,1666,1600,1534,1468, + 1401,1333,1265,1197,1129,1060,991,921,851,781, + 711,641,570,499,428,357,286,214,143,71,0}; + +uint16_t DAC_value1[181] = {4094, 4094, 4093, 4091, 4089, 4086, 4083, 4079, + 4074, 4069, 4063, 4056, 4049, 4042, 4033, 4024, + 4015, 4005, 3994, 3982, 3971, 3958, 3945, 3931, + 3917, 3902, 3887, 3871, 3854, 3837, 3820, 3802, + 3783, 3764, 3744, 3724, 3703, 3682, 3660, 3638, + 3615, 3592, 3568, 3544, 3519, 3494, 3469, 3443, + 3417, 3390, 3363, 3335, 3307, 3279, 3250, 3221, + 3192, 3162, 3132, 3101, 3071, 3039, 3008, 2976, + 2944, 2912, 2880, 2847, 2814, 2781, 2747, 2713, + 2680, 2645, 2611, 2577, 2542, 2507, 2473, 2438, + 2402, 2367, 2332, 2296, 2261, 2225, 2190, 2154, + 2118, 2083, 2047, 2011, 1976, 1940, 1904, 1869, + 1833, 1798, 1762, 1727, 1692, 1656, 1621, 1587, + 1552, 1517, 1483, 1449, 1414, 1381, 1347, 1313, + 1280, 1247, 1214, 1182, 1150, 1118, 1086, 1055, + 1024, 993, 962, 932, 902, 873, 844, 815, + 787, 759, 731, 704, 677, 651, 625, 600, + 575, 550, 526, 502, 479, 456, 434, 412, + 391, 370, 350, 330, 311, 292, 274, 257, + 240, 223, 207, 192, 177, 163, 149, 136, + 123, 112, 100, 89, 79, 70, 61, 52, 45, 38, + 31, 25, 20, 15, 11, 8, 5, 3, 1, 0, 0}; + +uint16_t DAC_value2[181] = {0}; + + +uint8_t Counter =0; +uint8_t Direction =0; + +/*---------------------------------------------------------------------------- + * main: initialize and start the system + *----------------------------------------------------------------------------*/ +int main (void) { + uint32_t button_msk = (1U << Buttons_GetCount()) - 1; + + osKernelInitialize (); // initialize CMSIS-RTOS + + // initialize peripherals + SystemCoreClockConfigure(); // configure System Clock + SystemCoreClockUpdate(); + + LED_Initialize(); // LED Initialization + Buttons_Initialize(); // Buttons Initialization + + // create threads + tid_blinkLED = osThreadCreate (osThread(blinkLED), NULL); + + osKernelStart (); // start thread execution + DAC_init(); + DAC_enable(); + + + for(Counter=0;Counter<182;Counter++) + { + DAC_value2[Counter]=DAC_value1[Counter]/2; + } + Counter=0; + + for (;;) { + if (Counter<=0)Direction=0; + else if (Counter>179)Direction=1; + if (Direction==0)Counter++; + else Counter--; + + DAC_write(DAC_value2[Counter]); + + + +// DAC_write(4000); +// osDelay(100); +// while (Buttons_GetState() & (button_msk)); // Wait while holding USER button +// DAC_write(0); +// osSignalSet(tid_blinkLED, 0x0001); + } +} diff --git a/RTX_Blinky/RTX_Blinky.uvguix b/RTX_Blinky/RTX_Blinky.uvguix new file mode 100644 index 0000000..2bd7680 --- /dev/null +++ b/RTX_Blinky/RTX_Blinky.uvguix @@ -0,0 +1,2601 @@ + + + + -5.1 + +
    ### uVision Project, (C) Keil Software
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    ### uVision Project, (C) Keil Software
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    ### uVision Project, (C) Keil Software
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