🌐 EPIC: Trinity dePIN-Compute — Ternary FPGA → ASIC Mesh-Inference Constellation (NASA-format)

[gHashTag]

EPIC: Trinity dePIN-Compute — Ternary FPGA → ASIC Mesh-Inference Constellation

Document: TR-TRIN-DPC-2026-001 (NASA-format technical report attached as the canonical reference)
Anchor: φ² + φ⁻² = 3 · Zenodo DOI 10.5281/zenodo.19227877
Notification policy: R-silence at boundary. Heartbeat ≤ 7 d (Article V).
Honesty mode: R5 — every metric tagged [VERIFIED] / [CITED] / [DERIVED] / [ASPIRATIONAL].

This EPIC consolidates Issues #14, #16, #17, #18 into a single tracking surface and decomposes the Trinity dePIN-Compute thesis into eight constitutional Articles, five execution lanes (L-DPC1..L-DPC5), and twelve acceptance gates (G1..G12).

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1. Objective

Land the Trinity stack from verified FPGA RTL (PR #11/#12/#13/#15) through real-hardware bench (Issue #14), Node-0 mesh bringup (Issue #17), and a TTSKY26a / TTIHP26a silicon submission, while maintaining full R5-honesty on every public metric.

2. Constitutional Articles (truncated — see TR-TRIN-DPC-2026-001 §3 for full text)

• Article I — φ-Anchor. φ² + φ⁻² = 3 bit-exact across f32 / f64 / gf16. Falsification: any unit-test break in crates/trios-train/tests/phi_anchor.rs.
• Article II — Open-Source Total. Apache-2.0 RTL, MIT/Apache-2.0 toolchain, open PDK only (SKY130 / SG13G2). No NDA-gated module.
• Article III — Zero-Multiplier Discipline. 0 DSP48 enforced; ternary inner-product = popcount(TM(x_codec, y_codec)) − N (FATNN ICCV 2021 Table 1).
• Article IV — R5 Honesty. Every metric carries [VERIFIED] / [CITED] / [DERIVED] / [ASPIRATIONAL] tag.
• Article V — Heartbeat Cadence. ≥ 7 d silence on a CLAIMED lane → ⚠️ heartbeat-overdue; ≥ 14 d → 🔓 lane released.
• Article VI — Atomicity & Idempotence. ONE SHOT bodies regenerated, never hand-edited.
• Article VII — Format Sovereignty (provisional, gated on trios#509). No format-named experiment unless cpu_train.rs::forward() actually invokes the format codec.
• Article VIII — R-silence. No comments without explicit operator command. No emoji at notification boundary.

3. Lanes (claim protocol: comment "CLAIM L-DPCx" to take a lane)

L-DPC1 — Hardware Bench (closes #14)

• Synthesize vsa_matmul.v via openxc7 Docker → bitstream/design_v02.bit
• Flash via trios-fpga flash --xvc <ESP32_IP> until STATUS=0x401079FC (DONE=1)
• trios-fpga bench UART log → tok/s vs PR feat(vsa): iverilog full-chip validation — 16/16 tokens PASS, 1193 tok/s #15 baseline (1193 tok/s [VERIFIED])
• Capture canonical hardware ground-truth into bench/hw_v0.2.json
• Operator-blocking: ESP32 IP not yet supplied

L-DPC2 — Node-0 Mesh (closes #17)

• A. headscale on Railway (1-click template)
• B. tailscale up --advertise-exit-node --hostname node-0-fpga
• C. systemd unit trios-fpga serve --port 7878
• D. MagicDNS node-0-fpga.trinity.mesh:7878/infer returns valid JSON
• ACC-N0-1..ACC-N0-4 from TR-TRIN-DPC-2026-001 §6.2

L-DPC3 — TTSKY26a Silicon Submission ⏰ deadline 2026-05-11

• Place-and-route vsa_matmul + vsa_bind + vsa_bundle + weight SRAM against Tiny Tapeout SKY130 tile budget
• DRC/LVS clean
• Submit before 2026-05-11 close OR document fall-through to TTIHP27a / TTSKY27a
• Schedule-critical: 5 days from EPIC creation date

L-DPC4 — Public-Communications R5 Audit

• Sweep all repo READMEs, docs/, arXiv draft, slides for the corrections in Verification Matrix V-03..V-07:
  • "1675× FPGA→ASIC gap" → "5–35× attainable, subject to measurement" (Boutros TRETS 2018 ground truth)
  • "Helium $500" → "Helium indoor $249 / outdoor $499 (2026)"
  • "Akash $5000" → "Akash GPU rental ~$0.10–$2/hour, marketplace-priced"
  • "efabless MPW" → "Tiny Tapeout (efabless wound down 2025)"
  • "$30/node" → "[ASPIRATIONAL] L4 silicon volume target; current BOM ≈ $175–220 [DERIVED]"
• File docs/research/related-work.md citing AD-1..AD-13 from TR-TRIN-DPC-2026-001 §2

L-DPC5 — arXiv Draft (closes-on partial-merge of L-DPC1..L-DPC4)

• Title (working): "Trinity GF16: A φ-Anchored Ternary Vector-Symbolic Architecture with 0-DSP FPGA Implementation and an Open-Silicon Migration Path"
• Sections: Abstract · Background (BitNet, FATNN, XONN, VSA survey) · φ-Anchor algebra · RTL · iverilog 64/64 result · hardware bench (from L-DPC1) · open-silicon path (from L-DPC3) · dePIN integration · limitations (Article VII gating)
• Submit only after L-DPC1 produces hardware ground truth — R5 forbids arXiv on simulation-only numbers

4. Acceptance Gates

Gate	Description	Method	Lane
G1	Hardware bench tok/s ≥ 1193 ± 5%	UART log captured + checksum	L-DPC1
G2	Bitstream STATUS=0x401079FC verified on real chip	XVC readback	L-DPC1
G3	Mesh ping bidirectional Node-0 ↔ peer	tailscale ping	L-DPC2
G4	HTTP /infer returns expected JSON shape over MagicDNS	curl + schema check	L-DPC2
G5	Exit-node functional from foreign host	external curl ifconfig.me --exit-node node-0-fpga	L-DPC2
G6	TTSKY26a submission filed OR documented deferral	TT submission ID OR ADR-001 fall-through note	L-DPC3
G7	DRC/LVS clean against SKY130 PDK	KLayout report	L-DPC3
G8	All five communications corrections (V-03..V-07) landed	grep audit zero-diff	L-DPC4
G9	docs/research/related-work.md cites AD-1..AD-13	file present + citation count ≥ 13	L-DPC4
G10	arXiv draft submitted with hardware-ground-truth numbers only	submission email + arXiv ID	L-DPC5
G11	EPIC closes only when ≥ 4 of 5 lanes are DONE	manual review	EPIC
G12	No public claim violates Article IV at any point during execution	quarterly R5 audit	EPIC

5. Risk Register (from TR-TRIN-DPC-2026-001 §8 — top 5)

RID	Risk	Likelihood	Impact	Mitigation
R-01	TTSKY26a deadline missed	Medium	High	Decide go/no-go before 2026-05-09; fall-through to TTIHP27a
R-02	trios#509 invalidates IGLA-side weight provenance	High	Medium	FPGA track uses already-merged PR #9 gf16 export; not gated on #509
R-06	Energy-gap claim challenged in peer review	Medium	Medium	L-DPC4 corrections immediate
R-07	BitNet-2B4T outpaces Trinity in model scale	High	Medium	Position as hardware-co-design specialist, not model-scale leader
R-09	ESP32-XVC IP not provided	Currently True	Blocks L-DPC1 Step C	Operator action required

6. Out of Scope (orthogonal tracks)

• IGLA Race / EPIC #446 / PR #515 / trios#509 — separate track, gated on review-merge.
• PhD monograph chapters L1..L33 — phd-chapter-author / phd-monograph-auditor skills.
• RAINFROG-ADOPT — gHashTag/trios-trainer-igla#100.
• L-NG-CTRL leader-port — local branch feat/leader-port-control (D4 directive).

7. Reference Documents

• TR-TRIN-DPC-2026-001 — full NASA-format technical report (37 KB / 489 lines, attached as artifact)
• AD-1 BitNet b1.58 — arXiv:2402.17764
• AD-2 Boutros FPGA→ASIC TRETS 2018 — dl.acm.org/10.1145/3242898
• AD-3 FATNN ICCV 2021 — openaccess.thecvf.com
• AD-6 VSA cross-layer survey — arXiv:2508.14245
• AD-7 DePIN survey — arXiv:2309.16707
• AD-8 Lund FPGA partitioning — LUP 9163353
• AD-9 BitNet 2B4T — arXiv:2504.12285
• AD-11 IHP SG13G2 PDK — github.com/IHP-GmbH/IHP-Open-PDK
• AD-12 Tiny Tapeout shuttle calendar — tinytapeout.com/chips

8. Closes / Tracks

• Closes 📚 RESEARCH: Trinity dePIN-VPN — FPGA Mesh Neural Infrastructure (NASA-format) #16 (superseded by this EPIC + TR-TRIN-DPC-2026-001)
• Tracks 🔨 hw: синтез + прошивка + bench на железе (v0.2-igla-fpga Release) #14 (L-DPC1)
• Tracks 🛠️ SETUP: Trinity Node-0 — полная настройка первого dePIN-узла (FPGA + headscale + exit node) #17 (L-DPC2)
• Tracks 🔬 RESEARCH: FPGA → ASIC → Silicon — Trinity Stack Roadmap (NASA-format) #18 (L-DPC3 + L-DPC5)

phi^2 + phi^-2 = 3 · TRINITY · NEVER STOP

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👑 QUEEN ORDER — new master skill trinity-silicon-tapeout v1.0 ratified · L-DPC3 LIVE

Queen broadcast · φ² + φ⁻² = 3 · 2026-05-08 15:25 +07
Anchor: Zenodo DOI 10.5281/zenodo.19227877
Spark broadcast — 5 threads: trios#380 + #30 + #373 + trinity-fpga#19 + trinity-fpga#20

🎯 New skill — trinity-silicon-tapeout v1.0

A master AGI driver that takes Trinity from FPGA-validated (TRL 6) to silicon-validated (TRL 7) by shepherding L-DPC3 → L-DPC4 → L-DPC5 → CROWN-ASIC across the Tiny Tapeout / IHP / commercial-fab pipeline. Saved to the user's custom-skill library as skill 7f583381-b3dd-4ea3-b366-28d11279ac2d.

🚨 L-DPC3 critical path — T-3 days (deadline 2026-05-11 23:59 UTC)

Lane	Owner skill	Acceptance
L-DPC3-A1 Register + fork TT template	operator	gHashTag/tt-trinity-gf16 exists
L-DPC3-A2 RTL shrink 64×64 → 8×8	coq-runtime-invariants	every const traced in igla_assertions.json::matmul_8x8
L-DPC3-A3 TT wrapper tt_um_trinity_gf16.v	trinity-silicon-tapeout	pinout per references/tt-pinout.md
L-DPC3-A4 Rust-golden parity 100/100	coq-runtime-invariants	falsifier_silicon_hit 0/100
L-DPC3-A5 OpenLane2 sign-off	trinity-silicon-tapeout	cells ≤ 950, DRC=0, LVS match, STA met @ 50 MHz
L-DPC3-A6 info.yaml	trinity-silicon-tapeout	per references/info-yaml-template.yaml
L-DPC3-A7 GH Actions watchdog	apiary-watch	4-h release
L-DPC3-A8 Submit @ app.tinytapeout.com	operator	submission ID committed to trinity-fpga#20 G6
L-DPC3-A9 ADR-001 fall-through	trinity-queen-hive	only if 2026-05-11 22:00 UTC arrives without DRC clean

📜 R-SI rules (silicon edition, non-negotiable)

• R-SI-1 ZERO MULTIPLIERS — XOR + popcount + adders only
• R-SI-2 TERNARY ONLY — weights ∈ {-1, 0, +1} as 2-bit
• R-SI-3 GATE BUDGET ≤ 950 cells per tile
• R-SI-4 50 MHz EXACT, sync reset, no PLL
• R-SI-5 DRC/LVS clean, period
• R-SI-6 Apache 2.0 only
• R-SI-7 R4 trace — every const cited in igla_assertions.json
• R-SI-8 R5 honest — synth log committed verbatim
• R-SI-9 R7 falsifier — uio_out[2] = falsifier_silicon_hit
• R-SI-10 No Python in CROWN RTL CI surface

🔗 Sibling-skill patches (queued)

The following user-custom siblings get a one-block patch that re-routes silicon triggers to the new master:

Sibling	Bump	Patch
trinity-queen-hive	v1.1 → v1.2	silicon triggers + 4th spark thread
coq-runtime-invariants	v1.1 → v1.2	RTL trace + silicon golden
trinity-grandmaster	v1.0 → v1.1	Phase 9 — Silicon
apiary-watch	v1.0 → v1.1	tt-trinity-gf16/actions watchdog
phd-chapter-author	v1.0 → v1.1	Glava 35 trigger
phd-monograph-auditor	v1.0 → v1.1	App.B falsifier-silicon
tailscale-funnel-deploy	optional	OpenLane2 dashboard mirror

Patches in detail in the new skill's references/sibling-patches.md.

🛡 Claim protocol (silicon edition)

🛡 claim L-DPC3-A<n> · agent <codename> · ETA <hh:mm UTC>
💓 heartbeat every 60 min · "💓 L-DPC3-A<n> · <%> · <next>"
✅ done · "✅ L-DPC3-A<n> · PR #NNN · sha <7> · cells=<N>"
🚫 block · "🚫 L-DPC3-A<n> blocked by <reason>" → queen reroutes

🚫 Forbidden

• ❌ * operator anywhere in src/*.v (R-SI-1)
• ❌ Wrong shuttle (TTSKY26a only — TTSKY26c is L-DPC4)
• ❌ clock_hz ≠ 50000000 (R-SI-4)
• ❌ Closing trinity-fpga#20 before G6 + G7 honestly green or honestly deferred via ADR-001
• ❌ Removing the falsifier_silicon_hit assertion to pass CI (R-SI-9 + R5)
• ❌ Treating 2026-05-11 23:59 UTC as soft. Hard or ADR-001.

🧭 Down-stream cascade (post-G6+G7)

• arXiv update — TRL 6 → TRL 7
• Investor pitch — chip-in-hand December 2026
• IHP / NLnet grant — silicon proof attached
• PhD Glava 35 — silicon-validation chapter
• JEPA-T DePIN — on-die proof-of-inference
• Trinity DePIN compute marketplace — RunPod φ-cluster + chip anchor

Battle cry

Coq proves it. FPGA validates it. Silicon lands it.
€170 buys what $1 000 000 used to buy. Three days to TRL 7.

φ² + φ⁻² = 3 · TRINITY · SILICON-FIRST · CLAIM L-DPC3-A1

[gHashTag]

👑 Queen correction — author = Dmitrii Vasilev (NOT "gHashTag")

gHashTag is the GitHub organization name only. The author / human / PhD candidate / paper credit is Dmitrii Vasilev.

Affected artifacts (corrected queen-side just now)

• trinity-silicon-tapeout v1.0 SKILL.md metadata.author → Dmitrii Vasilev
• references/info-yaml-template.yaml project.author → Dmitrii Vasilev · Trinity Stack
• Skill re-validated, re-saved (skill_id 7f583381-…)

Standing rule for ALL future artifacts

• ✅ info.yaml :: author: "Dmitrii Vasilev · Trinity Stack"
• ✅ PhD monograph title page → Dmitrii Vasilev
• ✅ arXiv paper authorship → Dmitrii Vasilev
• ✅ Zenodo metadata creators → Dmitrii Vasilev
• ✅ Apache 2.0 LICENSE Copyright 2026 Dmitrii Vasilev
• ✅ ADR-001 / ADR-002 / ADR-003 sign-offs → Dmitrii Vasilev
• ✅ G6 submission comment → Author: Dmitrii Vasilev
• ❌ NEVER author: gHashTag (org ≠ person — R5 honest)
• ✅ gHashTag/<repo> URLs stay as-is (legitimate org references)

Agents currently working on L-DPC3 / L-DPC4 / L-DPC5 — please verify your draft info.yaml, README headers, and commit author lines before submit.

φ² + φ⁻² = 3 · TRINITY · DMITRII VASILEV · author corrected

[gHashTag]

💰 TTSKY26a — Pricing Reality Check (T-25h to deadline)

Source: app.tinytapeout.com/prepurchase?shuttle=ttsky26a (extracted from JS bundle invoice-DJdkkrYC.js)

Corrected pricing (skill said €170/tile — that was outdated)

Item	Price
1 tile (160×110 µm)	€70
Subsidized DevKit (early-bird)	€100 (80 slots — currently allocated)
Full-price DevKit	€300
Worldwide economy shipping (per DevKit)	€15
Currency	EUR only (no USD)
Closing	2026-05-11 20:00 UTC (not 23:59 — 4-hour earlier than skill assumed)
Fab → delivery	ChipFoundry CI-2605 → chips 2026-10-28 → ship 2026-12-16

Realistic scenarios for L-DPC3

Scenario	€	$ approx
Tile only (no chip in hand)	€70	~$76
Tile + early-bird DevKit + ship (if Efabless-eligible)	€185	~$200
Tile + full DevKit + ship (default fallback)	€385	~$418
Demoscene free-tile + full DevKit + ship	€315	~$340

Discount paths in flight

1. Demoscene competition (announce) — Precision Innovations sponsors a free tile per entrant. Requires VGA Pmod sound/graphics demo. Our tt_um_ghtag_trinity_gf16 is pure dot-product, so a VGA result-visualizer wrapper would be needed (4-6h RTL work). Asking in #competitions Discord whether shuttle has space + whether wrapper qualifies.
2. Efabless early-bird — TT homepage states "Early bird prices are currently reserved for projects affected by the Efabless shutdown." No public form; emailing support@tinytapeout.com with our case (PhD silicon-validation, ex-MPW path, Apache 2.0).
3. ChipFoundry subsidy — 80/80 PCBs allocated. Wait-list inquiry sent.
4. University/School plan — minimum bundle €565, not relevant for solo submission.

Worst-case budget

If neither demoscene nor early-bird lands, €385 (~$418) is the firm price for 1 tile + DevKit + ship before 2026-05-11 20:00 UTC.

Skill update needed (trinity-silicon-tapeout v1.0)

• Phase 5 step 4: change "pay €170" → "pay €70 tile + €100/€300 DevKit + €15 ship"
• Phase 0–6 deadline references: 22:00 UTC safety margin → bring forward to 18:00 UTC (since hard close is 20:00 UTC)
• Demoscene path: add as a separate Phase 1.5 (free tile, but VGA wrapper required)
• Repo template: skill said tt10-verilog-template — actual current is ttsky-verilog-template

🌻 phi^2 + phi^-2 = 3 · TRINITY · NEVER STOP