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Add framebuffer and LCD panel support to device tree #5

@hansemro

Description

@hansemro

Resources:

Device tree resources:

  • Documentation/devicetree/bindings/display/panel/panel-dpi.yaml
  • Documentation/devicetree/bindings/display/panel/panel-simple.yaml
  • Documentation/devicetree/bindings/display/panel/panel-common.yaml

Hardware details:

  • Framebuffer address: 0x9fec4000 (reported by U-Boot)
  • LCD Panel: Hydis HV070WS1-105
    • 1024x600
    • 32 bits/pixel (A8R8B8G8); 24 bits/pixel (R8B8G8)
    • GPTimer10 PWM backlight
    • GPIO 37: switch to LVDS mode (OMAP_RGB_SHTDOWN)
    • GPIO 47 : Enable 3.3V rail (OMAP_3V_ENABLE)
    • GPIO 45: LCD_PWR_ON

Notes:

  • Display Subsystem (DSS): responsible for displaying frame to LCD2 channel by MIPI DPI 1.0

DSS configuration (from 3.4.48):

framebuffers -- overlays -- managers -- displays
FB0 --- GFX --\    LCD ---- (none)
        VID1   \   TV ----- (none)
        VID2    \- LCD2 --- LCD2
        VID3

Timings (pixclock in kHz,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw): 51200,1024/160/150/10,600/12/20/3

dpll4_ck (?) = 1536000000 Hz
DSS_FCLK = (dpll4_ck / 9) = 170666666 Hz
DSS_CLK = DSS_FCLK = 170666666 Hz (?)
PLL2_CLK1 = 153600000 Hz
DISPC_FCLK = PLL2_CLK1 = 153600000 Hz
LCD2_CLK (DSI2 functional clock) = PLL2_CLK1 = 153600000 Hz
LCD2 (lck div) = DISPC_DIVISOR2[23:16] = 1
PCD2 (pck div) = DISPC_DIVISOR2[7:0] = 3
LC2_PCLK  = (LCD2_CLK  / LCD2) / PCD2 = 51200000 Hz

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