`SystemVerilog.definitionParameters` does not enforce uniqueness with other names

[mkorbel1]

Describe the bug

It is possible to name a SystemVerilog parameter using SystemVerilog.definitionParameters with a name that conflicts with other names in that module definition (ports, reserved instance/signal names, etc.). This should not be allowed and uniqueness should be enforced.

To Reproduce

No response

Expected behavior

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Actual behavior

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Additional: Dart SDK info

No response

Additional: pubspec.yaml

Additional: Context

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