diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj
index e42c6e18d..51911160c 100644
--- a/ref_app/target.vcxproj
+++ b/ref_app/target.vcxproj
@@ -1071,6 +1071,12 @@
     <None Include="target\micros\esp32p4_riscv_soc\make\esp32p4_riscv_soc.ld" />
     <None Include="target\micros\esp32p4_riscv_soc\make\esp32p4_riscv_soc_files.gmk" />
     <None Include="target\micros\esp32p4_riscv_soc\make\esp32p4_riscv_soc_flags.gmk" />
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.bin" />
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.elf" />
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.hex" />
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.map" />
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.readelf" />
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\readme.md" />
     <None Include="target\micros\esp32p4_riscv_soc\startup\Code\Startup\boot.s" />
     <None Include="target\micros\lpc11c24\make\lpc11c24.ld" />
     <None Include="target\micros\lpc11c24\make\lpc11c24_files.gmk" />
diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters
index 371d669d2..8c3bc2cf0 100644
--- a/ref_app/target.vcxproj.filters
+++ b/ref_app/target.vcxproj.filters
@@ -361,6 +361,12 @@
     <Filter Include="micros\esp32p4_riscv_soc\startup\Code\StdLib">
       <UniqueIdentifier>{65c5c603-a019-41d0-8a19-3cadaca7fd3c}</UniqueIdentifier>
     </Filter>
+    <Filter Include="micros\esp32p4_riscv_soc\startup\Code\SBL">
+      <UniqueIdentifier>{78721b7f-e97c-4ac7-906a-a571af4377b1}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="micros\esp32p4_riscv_soc\startup\Code\SBL\Output">
+      <UniqueIdentifier>{154f1c39-5085-471e-a5c9-444517255025}</UniqueIdentifier>
+    </Filter>
   </ItemGroup>
   <ItemGroup>
     <None Include="target\app\make\app_files.gmk">
@@ -813,6 +819,24 @@
     <None Include="target\micros\esp32p4_riscv_soc\startup\Code\Startup\boot.s">
       <Filter>micros\esp32p4_riscv_soc\startup\Code\Startup</Filter>
     </None>
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\readme.md">
+      <Filter>micros\esp32p4_riscv_soc\startup\Code\SBL</Filter>
+    </None>
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.bin">
+      <Filter>micros\esp32p4_riscv_soc\startup\Code\SBL\Output</Filter>
+    </None>
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.elf">
+      <Filter>micros\esp32p4_riscv_soc\startup\Code\SBL\Output</Filter>
+    </None>
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.hex">
+      <Filter>micros\esp32p4_riscv_soc\startup\Code\SBL\Output</Filter>
+    </None>
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.map">
+      <Filter>micros\esp32p4_riscv_soc\startup\Code\SBL\Output</Filter>
+    </None>
+    <None Include="target\micros\esp32p4_riscv_soc\startup\Code\SBL\Output\SBL.readelf">
+      <Filter>micros\esp32p4_riscv_soc\startup\Code\SBL\Output</Filter>
+    </None>
   </ItemGroup>
   <ItemGroup>
     <ClCompile Include="Target\Micros\AVR\Startup\int_vect.cpp">
diff --git a/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/readme.md b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/readme.md
new file mode 100644
index 000000000..386402fea
--- /dev/null
+++ b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/readme.md
@@ -0,0 +1,14 @@
+# ESP32-P4 SBL (Secondary Boot Loader)
+
+The SBL (Secondary Boot Loader) is used in combination with the ESP-flash
+tool to boot the multi-core device.
+
+The SBL has been adopted directly from the original work in
+[Chalandi/Baremetal_esp32p4_nosdk](https://github.com/Chalandi/Baremetal_esp32p4_nosdk).
+In that work, the SBL code and build system can be found in the
+[SBL](https://github.com/Chalandi/Baremetal_esp32p4_nosdk/tree/master/Code/SBL) directory.
+
+The original _chalandi_ project has been used locally to build the SBL
+for target `esp32p4_riscv_soc` in the `ref_app`.
+The SBL-Output from that build has been archived and can be found
+in the [Output](./Output) directory.