RISC-V Instruction Set Architecture Support

[IBPX]

Would it be possible to support RISC-V in the future?

GCC has support for RISC-V beginning in version 7.1.

[ccstevens]

Yes, porting to the RISC-V architecture should be possible. At a glance, it looks to be fairly new - lacking a standard supervisor-mode instruction set. Is this correct? It appears that Linux, FreeBSD, NetBSD, and Fedora have added support for RISC-V, so there must be enough documentation to get going.

That said, porting to a new architecture is a large task, starting with getting the third-party tool chain set up to cross compile. We're still on GCC 6.3.0, but it's nice that GCC 7.1 has support. Upgrading GCC would be the first step. Then comes writing the disassembler for the Minoca debugger to allow you to debug the boot process. It also looks like there is QEMU support for RISC-V, which may make getting over the initial boot hurdle easier.

Do you have a RISC-V platform in mind? Any interest in tackling the port yourself? The previous paragraph is fair warning that it's not a one weekend project, but it would be fun.

[IBPX]

At a glance, it looks to be fairly new - lacking a standard supervisor-mode instruction set. Is this correct?

Yes. I believe the supervisor-mode instruction set is currently in the draft stage, while most of the rest of the ISA is standardized.

I do not have a specific platform in mind; RISC-V is very young, and as far as I can tell there are only a handful of chips being made so far.

I would like to work on this, but I believe it is beyond my abilities, and my knowledge of C is very limited. I will definitely be poking around though, and perhaps I will find it easier than expected.

[ccstevens]

Thanks for the added information. If you do start poking around, don't hesitate to ask questions.

If you get to disassembler, the main code is in disasm.c and branches out to the various architectures - armdis.c, x86dis.c, etc. You'd want to add a riscvdis.c file.