diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/.gitignore b/UVM_Framework/UVMF_2022.3/challenge_3/.gitignore
new file mode 100644
index 00000000..b8f99f5b
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/.gitignore
@@ -0,0 +1 @@
+work
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_bench.yaml
new file mode 100644
index 00000000..ae2c602f
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_bench.yaml
@@ -0,0 +1,17 @@
+uvmf:
+ benches:
+ "block_1" :
+ ## Specify the top-level block
+ top_env: "block_1"
+ clock_half_period: "5ns"
+ reset_assertion_level: "True"
+ reset_duration: "200ns"
+ active_passive:
+ - bfm_name: "apb_master"
+ value: "ACTIVE"
+ - bfm_name: "axi_master1"
+ value: "ACTIVE"
+ - bfm_name: "axi_master2"
+ value: "ACTIVE"
+ - bfm_name: "spi_slave"
+ value: "ACTIVE"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_env.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_env.yaml
new file mode 100644
index 00000000..3a54344c
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_env.yaml
@@ -0,0 +1,57 @@
+uvmf:
+ environments:
+ "block_1" :
+ agents :
+ - name: "apb_master"
+ type: "apb_m"
+ initiator_responder: "INITIATOR"
+
+ - name: "axi_master1"
+ type: "axi_m"
+ initiator_responder: "INITIATOR"
+
+ - name: "axi_master2"
+ type: "axi_m"
+ initiator_responder: "INITIATOR"
+
+ - name: "spi_slave"
+ type: "spi_s"
+ initiator_responder: "RESPONDER"
+
+ analysis_components :
+ - name: "block_1_pred"
+ type: "block_1_predictor"
+ - name: "block_1_sb"
+ type: "block_1_scoreboard"
+
+ analysis_ports :
+ - name: "apb_master_ap"
+ trans_type: "apb_m_transaction"
+ connected_to: "apb_master.monitored_ap"
+ - name: "axi_master1_ap"
+ trans_type: "axi_m_transaction"
+ connected_to: "axi_master1.monitored_ap"
+ - name: "axi_master2_ap"
+ trans_type: "axi_m_transaction"
+ connected_to: "axi_master2.monitored_ap"
+ - name: "spi_slave_ap"
+ trans_type: "spi_s_transaction"
+ connected_to: "spi_slave.monitored_ap"
+
+ tlm_connections:
+ - driver: "spi_slave.monitored_ap"
+ receiver: "block_1_sb.spi_ae"
+ - driver: "apb_master.monitored_ap"
+ receiver: "block_1_pred.apb_ae"
+
+ - driver: "axi_master1.monitored_ap"
+ receiver: "block_1_pred.axi_1_ae"
+ - driver: "axi_master2.monitored_ap"
+ receiver: "block_1_pred.axi_2_ae"
+ - driver: "block_1_pred.pre_to_sco_ap"
+ receiver: "block_1_sb.sco_from_pre_ae"
+
+ config_vars :
+ - name: "has_scoreboard"
+ type : "bit"
+ isrand : "False"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_util.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_util.yaml
new file mode 100644
index 00000000..bb4d18b6
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_util.yaml
@@ -0,0 +1,22 @@
+uvmf:
+ util_components:
+ block_1_predictor:
+ analysis_exports:
+ - name: apb_ae
+ type: 'apb_m_transaction'
+ - name: axi_1_ae
+ type: 'axi_m_transaction'
+ - name: axi_2_ae
+ type: 'axi_m_transaction'
+ analysis_ports:
+ - name: pre_to_sco_ap
+ type: 'spi_s_transaction'
+ existing_library_component: 'True'
+ type: predictor
+ block_1_scoreboard:
+ analysis_exports:
+ - name: spi_ae
+ type: 'spi_s_transaction'
+ - name: sco_from_pre_ae
+ type: 'spi_s_transaction'
+ type: scoreboard
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block_1.csh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block_1.csh
new file mode 100644
index 00000000..1ce8d50d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block_1.csh
@@ -0,0 +1,3 @@
+# This is the command to generate you block_1_level bench
+
+python ../../../UVMF_2022.3/scripts/yaml2uvmf.py ../intf/apb_m_intf.yaml ../intf/axi_m_intf.yaml ../intf/spi_s_intf.yaml ../block_1/block1_env.yaml ../block_1/block1_util.yaml ../block_1/block1_bench.yaml
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_bench.yaml
new file mode 100644
index 00000000..8cc83e45
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_bench.yaml
@@ -0,0 +1,12 @@
+uvmf:
+ benches:
+ "block_2" :
+ top_env: "block_2"
+ clock_half_period: "5ns"
+ reset_assertion_level: "True"
+ reset_duration: "200ns"
+ active_passive:
+ - bfm_name: "spi_master"
+ value: "ACTIVE"
+ - bfm_name: "wb_slave"
+ value: "ACTIVE"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_env.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_env.yaml
new file mode 100644
index 00000000..4f1e5ae8
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_env.yaml
@@ -0,0 +1,37 @@
+uvmf:
+ environments:
+ "block_2" :
+ agents :
+ - name: "spi_master"
+ type: "spi_m"
+ initiator_responder: "INITIATOR"
+ - name: "wb_slave"
+ type: "wb_s"
+ initiator_responder: "RESPONDER"
+
+ analysis_components :
+ - name: "block_2_pred"
+ type: "block_2_predictor"
+ - name: "block_2_sb"
+ type: "block_2_scoreboard"
+
+ analysis_ports :
+ - name: "spi_master_ap"
+ trans_type: "spi_m_transaction"
+ connected_to: "spi_master.monitored_ap"
+ - name: "wb_slave_ap"
+ trans_type: "wb_s_transaction"
+ connected_to: "wb_slave.monitored_ap"
+
+ tlm_connections:
+ - driver: "spi_master.monitored_ap"
+ receiver: "block_2_pred.spi_ae"
+ - driver: "wb_slave.monitored_ap"
+ receiver: "block_2_sb.wb_ae"
+ - driver: "block_2_pred.pre_to_sco_ap"
+ receiver: "block_2_sb.sco_from_pre_ae"
+
+ config_vars :
+ - name: "has_scoreboard"
+ type : "bit"
+ isrand : "False"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_util.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_util.yaml
new file mode 100644
index 00000000..ebf62361
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_util.yaml
@@ -0,0 +1,18 @@
+uvmf:
+ util_components:
+ block_2_predictor:
+ analysis_exports:
+ - name: spi_ae
+ type: 'spi_m_transaction'
+ analysis_ports:
+ - name: pre_to_sco_ap
+ type: 'wb_s_transaction'
+ existing_library_component: 'True'
+ type: predictor
+ block_2_scoreboard:
+ analysis_exports:
+ - name: wb_ae
+ type: 'wb_s_transaction'
+ - name: sco_from_pre_ae
+ type: 'wb_s_transaction'
+ type: scoreboard
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block_2.csh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block_2.csh
new file mode 100644
index 00000000..40bf67a3
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block_2.csh
@@ -0,0 +1,3 @@
+# This is the command to generate you block_2_level bench
+
+python ../../../UVMF_2022.3/scripts/yaml2uvmf.py ../intf/spi_m_intf.yaml ../intf/wb_s_intf.yaml ../block_2/block2_env.yaml ../block_2/block2_util.yaml ../block_2/block2_bench.yaml
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_bench.yaml
new file mode 100644
index 00000000..93f82cf6
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_bench.yaml
@@ -0,0 +1,13 @@
+uvmf:
+ benches:
+ "block_3" :
+ ## Specify the top-level block
+ top_env: "block_3"
+ clock_half_period: "5ns"
+ reset_assertion_level: "True"
+ reset_duration: "200ns"
+ active_passive:
+ - bfm_name: "wb_master"
+ value: "ACTIVE"
+ - bfm_name: "axi_slave"
+ value: "ACTIVE"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_env.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_env.yaml
new file mode 100644
index 00000000..21e221b3
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_env.yaml
@@ -0,0 +1,38 @@
+uvmf:
+ environments:
+ "block_3" :
+ agents :
+ - name: "wb_master"
+ type: "wb_m"
+ initiator_responder: "INITIATOR"
+ - name: "axi_slave"
+ type: "axi_s"
+ initiator_responder: "RESPONDER"
+ analysis_components :
+ - name: "block_3_pred"
+ type: "block_3_predictor"
+ - name: "block_3_sb"
+ type: "block_3_scoreboard"
+
+ analysis_ports:
+ - name: wb_master_ap
+ trans_type: wb_m_transaction
+ connected_to: wb_master.monitored_ap
+ - name: axi_slave_ap
+ trans_type: axi_s_transaction
+ connected_to: axi_slave.monitored_ap
+
+ tlm_connections:
+ - driver: wb_master.monitored_ap
+ receiver: block_3_pred.wb_ae
+ - driver: axi_slave.monitored_ap
+ receiver: block_3_sb.axi_ae
+ - driver: block_3_pred.pre_to_sco_ap
+ receiver: block_3_sb.sco_from_pre_ae
+
+ config_vars:
+ - name: "has_scoreboard"
+ type: bit
+ isrand: "False"
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_util.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_util.yaml
new file mode 100644
index 00000000..bf858e70
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_util.yaml
@@ -0,0 +1,17 @@
+uvmf:
+ util_components:
+ block_3_predictor:
+ analysis_exports:
+ - name: wb_ae
+ type: 'wb_m_transaction'
+ analysis_ports:
+ - name: pre_to_sco_ap
+ type: 'axi_s_transaction'
+ type: predictor
+ block_3_scoreboard:
+ analysis_exports:
+ - name: axi_ae
+ type: 'axi_s_transaction'
+ - name: sco_from_pre_ae
+ type: 'axi_s_transaction'
+ type: scoreboard
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block_3.csh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block_3.csh
new file mode 100644
index 00000000..789e5a03
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block_3.csh
@@ -0,0 +1,3 @@
+# This is the command to generate you block_3_level bench
+
+python ../../../UVMF_2022.3/scripts/yaml2uvmf.py ../intf/wb_m_intf.yaml ../intf/axi_s_intf.yaml ../block_3/block3_env.yaml ../block_3/block3_util.yaml ../block_3/block3_bench.yaml
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/apb_m_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/apb_m_intf.yaml
new file mode 100644
index 00000000..057c01f0
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/apb_m_intf.yaml
@@ -0,0 +1,99 @@
+uvmf:
+ interfaces:
+ "apb_m":
+ clock: "pclk"
+ reset: "presetn"
+ veloce_ready: "True"
+ reset_assertion_level: 'False'
+ parameters:
+ - name: "APB_ADDR_WIDTH"
+ type: "int"
+ value: '32'
+ - name: "APB_DATA_WIDTH"
+ type: "int"
+ value: '32'
+ - name: "STRB_LEN"
+ type: "int"
+ value: "APB_ADDR_WIDTH/8"
+ ports:
+ - dir: "output"
+ name: "psel"
+ reset_value: '''b0'
+ width: '16'
+ - dir: "output"
+ name: "penable"
+ reset_value: '''b0'
+ width: '1'
+ - dir: "output"
+ name: "paddr"
+ reset_value: '''b0'
+ width: "APB_ADDR_WIDTH"
+ - dir: "output"
+ name: "pwdata"
+ reset_value: '''b0'
+ width: "APB_DATA_WIDTH"
+ - dir: "output"
+ name: "pwrite"
+ reset_value: '''b0'
+ width: '1'
+ - dir: "output"
+ name: "pstrb"
+ reset_value: '''b0'
+ width: 'STRB_LEN'
+ - dir: "output"
+ name: "pprot"
+ reset_value: '''b0'
+ width: '3'
+ - dir: "input"
+ name: "prdata"
+ reset_value: '''b0'
+ width: "APB_DATA_WIDTH"
+ - dir: "input"
+ name: "pready"
+ reset_value: '0'
+ width: '1'
+ - dir: "input"
+ name: "pslverr"
+ reset_value: '0'
+ width: '1'
+ transaction_vars:
+ - iscompare: 'False'
+ isrand: 'True'
+ name: "psel"
+ type: "bit"
+ - iscompare: 'True'
+ isrand: 'True'
+ name: "penable"
+ type: "bit"
+ - iscompare: 'True'
+ isrand: 'True'
+ name: "paddr"
+ type: "bit [APB_ADDR_WIDTH-1:0]"
+ - iscompare: 'True'
+ isrand: 'True'
+ name: "pwdata"
+ type: "bit [APB_DATA_WIDTH-1:0]"
+ - iscompare: 'True'
+ isrand: 'True'
+ name: "pwrite"
+ type: "bit"
+ - iscompare: 'True'
+ isrand: 'True'
+ name: "pstrb"
+ type: "bit [STRB_LEN:0]"
+ - iscompare: 'True'
+ isrand: 'True'
+ name: "pprot"
+ type: "bit [3:0]"
+ - iscompare: 'True'
+ isrand: 'False'
+ name: "prdata"
+ type: "bit [APB_DATA_WIDTH-1:0]"
+ - iscompare: 'True'
+ isrand: 'False'
+ name: "pready"
+ type: "bit"
+ - iscompare: 'True'
+ isrand: 'False'
+ name: "pslverr"
+ type: "bit"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_m_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_m_intf.yaml
new file mode 100644
index 00000000..6921d053
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_m_intf.yaml
@@ -0,0 +1,396 @@
+uvmf:
+ interfaces:
+ "axi_m":
+ clock: axi_clk
+ reset: rst
+ reset_assertion_level: "False"
+ veloce_ready: "True"
+ parameters:
+ - name: "AW_WIDTH"
+ type: "int"
+ value: "32"
+ - name: "LEN"
+ type: "int"
+ value: "8"
+ - name: "DATA_WIDTH"
+ type: "int"
+ value: "32"
+ - name: "X"
+ type: "int"
+ value: "16"
+ ports:
+ # write address channel
+ - name: awvalid
+ dir: output
+ width: "1"
+ - name: awready
+ dir: input
+ width: "1"
+ - name: awaddr
+ dir: output
+ width: "AW_WIDTH"
+ - name: awsize
+ dir: output
+ width: "3"
+ - name: awburst
+ dir: output
+ width: "2"
+ - name: awcache
+ dir: output
+ width: "4"
+ - name: awprot
+ dir: output
+ width: "3"
+ - name: awid
+ dir: output
+ width: "X"
+ - name: awlen
+ dir: output
+ width: "LEN"
+ - name: awlock
+ dir: output
+ width: "1"
+ - name: awqos
+ dir: output
+ width: "4"
+ - name: awregion
+ dir: output
+ width: "4"
+ - name: awuser
+ dir: output
+ width: "X"
+ # write data channel
+ - name: wvalid
+ dir: output
+ width: "1"
+ - name: wready
+ dir: input
+ width: "1"
+ - name: wlast
+ dir: output
+ width: "1"
+ - name: wdata
+ dir: output
+ width: "DATA_WIDTH"
+ - name: wstrb
+ dir: output
+ width: "DATA_WIDTH/8"
+ - name: wid
+ dir: output
+ width: "X"
+ - name: wuser
+ dir: output
+ width: "X"
+ # write response channel
+ - name: bwvalid
+ dir: input
+ width: "1"
+ - name: bwready
+ dir: output
+ width: "1"
+ - name: bresp
+ dir: input
+ width: "2"
+ - name: bid
+ dir: input
+ width: "X"
+ - name: buser
+ dir: input
+ width: "X"
+ #read address channel
+ - name: arvalid
+ dir: output
+ width: "1"
+ - name: aready
+ dir: input
+ width: "1"
+ - name: araddr
+ dir: output
+ width: "AW_WIDTH"
+ - name: arsize
+ dir: output
+ width: "3"
+ - name: arburst
+ dir: output
+ width: "2"
+ - name: arcache
+ dir: output
+ width: "4"
+ - name: arprot
+ dir: output
+ width: "3"
+ - name: arid
+ dir: output
+ width: "X"
+ - name: arlen
+ dir: output
+ width: "LEN"
+ - name: arlock
+ dir: output
+ width: "1"
+ - name: arqos
+ dir: output
+ width: "4"
+ - name: aregion
+ dir: output
+ width: "4"
+ - name: aruser
+ dir: output
+ width: "X"
+ #read data channel
+ - name: rvalid
+ dir: input
+ width: "1"
+ - name: rready
+ dir: output
+ width: "1"
+ - name: rlast
+ dir: input
+ width: "1"
+ - name: rdata
+ dir: input
+ width: "DATA_WIDTH"
+ - name: rid
+ dir: input
+ width: "X"
+ - name: ruser
+ dir: input
+ width: "X"
+ - name: rresp
+ dir: input
+ width: "2"
+ transaction_vars:
+ #write address channel
+ - name: "awvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awaddr"
+ type: "bit [AW_WIDTH-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awsize"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awburst"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awcache"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awprot"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awid"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awlen"
+ type: "bit [LEN-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awlock"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awqos"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awregion"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "awuser"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ #write data channel
+ - name: "wvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wlast"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wdata"
+ type: "bit [DATA_WIDTH-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "wstrb"
+ type: "bit [DATA_WIDTH/8-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "wid"
+ type: "bit [X-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wuser"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ #write response channel
+ - name: "bwvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "bwready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "bresp"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "bid"
+ type: "bit [X-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "buser"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ #ready address channel
+ - name: "arvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "aready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "araddr"
+ type: "bit [AW_WIDTH-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arsize"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arburst"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arcache"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arprot"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arid"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arlen"
+ type: "bit [LEN-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arlock"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arqos"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "aregion"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "aruser"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ #ready data channel
+
+ - name: "rvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "rready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "rlast"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "rdata"
+ type: "bit [DATA_WIDTH-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "rid"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "ruser"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "rresp"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_s_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_s_intf.yaml
new file mode 100644
index 00000000..0e3aa936
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_s_intf.yaml
@@ -0,0 +1,396 @@
+uvmf:
+ interfaces:
+ "axi_s":
+ clock: axi_clk
+ reset: rst
+ reset_assertion_level: "False"
+ veloce_ready: "True"
+ parameters:
+ - name: "AW_WIDTH"
+ type: "int"
+ value: "32"
+ - name: "LEN"
+ type: "int"
+ value: "8"
+ - name: "DATA_WIDTH"
+ type: "int"
+ value: "32"
+ - name: "X"
+ type: "int"
+ value: "16"
+ ports:
+ # write address channel
+ - name: awvalid
+ dir: input
+ width: "1"
+ - name: awready
+ dir: output
+ width: "1"
+ - name: awaddr
+ dir: input
+ width: "AW_WIDTH"
+ - name: awsize
+ dir: input
+ width: "3"
+ - name: awburst
+ dir: input
+ width: "2"
+ - name: awcache
+ dir: input
+ width: "4"
+ - name: awprot
+ dir: input
+ width: "3"
+ - name: awid
+ dir: input
+ width: "X"
+ - name: awlen
+ dir: input
+ width: "LEN"
+ - name: awlock
+ dir: input
+ width: "1"
+ - name: awqos
+ dir: input
+ width: "4"
+ - name: awregion
+ dir: input
+ width: "4"
+ - name: awuser
+ dir: input
+ width: "X"
+ # write data channel
+ - name: wvalid
+ dir: input
+ width: "1"
+ - name: wready
+ dir: output
+ width: "1"
+ - name: wlast
+ dir: input
+ width: "1"
+ - name: wdata
+ dir: input
+ width: "DATA_WIDTH"
+ - name: wstrb
+ dir: input
+ width: "DATA_WIDTH/8"
+ - name: wid
+ dir: input
+ width: "X"
+ - name: wuser
+ dir: input
+ width: "X"
+ # write response channel
+ - name: bwvalid
+ dir: output
+ width: "1"
+ - name: bwready
+ dir: output
+ width: "1"
+ - name: bresp
+ dir: input
+ width: "2"
+ - name: bid
+ dir: output
+ width: "X"
+ - name: buser
+ dir: output
+ width: "X"
+ #read address channel
+ - name: arvalid
+ dir: input
+ width: "1"
+ - name: aready
+ dir: output
+ width: "1"
+ - name: araddr
+ dir: input
+ width: "AW_WIDTH"
+ - name: arsize
+ dir: input
+ width: "3"
+ - name: arburst
+ dir: input
+ width: "2"
+ - name: arcache
+ dir: input
+ width: "4"
+ - name: arprot
+ dir: input
+ width: "3"
+ - name: arid
+ dir: input
+ width: "X"
+ - name: arlen
+ dir: input
+ width: "LEN"
+ - name: arlock
+ dir: input
+ width: "1"
+ - name: arqos
+ dir: input
+ width: "4"
+ - name: aregion
+ dir: input
+ width: "4"
+ - name: aruser
+ dir: input
+ width: "X"
+ #read data channel
+ - name: rvalid
+ dir: output
+ width: "1"
+ - name: rready
+ dir: input
+ width: "1"
+ - name: rlast
+ dir: output
+ width: "1"
+ - name: rdata
+ dir: output
+ width: "DATA_WIDTH"
+ - name: rid
+ dir: output
+ width: "X"
+ - name: ruser
+ dir: output
+ width: "X"
+ - name: rresp
+ dir: output
+ width: "2"
+ transaction_vars:
+ #write address channel
+ - name: "awvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awaddr"
+ type: "bit [AW_WIDTH-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awsize"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awburst"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awcache"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awprot"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awid"
+ type: "bit [X-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awlen"
+ type: "bit [LEN-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awlock"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awqos"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awregion"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "awuser"
+ type: "bit [X-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ #write data channel
+ - name: "wvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wlast"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wdata"
+ type: "bit [DATA_WIDTH-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wstrb"
+ type: "bit [DATA_WIDTH/8-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wid"
+ type: "bit [X-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "wuser"
+ type: "bit [X-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ #write response channel
+ - name: "bwvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "bwready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "bresp"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "bid"
+ type: "bit [X-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "buser"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ #ready address channeli
+ - name: "arvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "aready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "araddr"
+ type: "bit [AW_WIDTH-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arsize"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arburst"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arcache"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arprot"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arid"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arlen"
+ type: "bit [LEN-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arlock"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "arqos"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "aregion"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "aruser"
+ type: "bit [X-1:0]"
+ isrand: "False"
+ iscompare: "False"
+
+ #ready data channel
+
+ - name: "rvalid"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "rready"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "rlast"
+ type: "bit"
+ isrand: "False"
+ iscompare: "False"
+
+ - name: "rdata"
+ type: "bit [DATA_WIDTH-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "rid"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "ruser"
+ type: "bit [X-1:0]"
+ isrand: "True"
+ iscompare: "False"
+
+ - name: "rresp"
+ type: "bit"
+ isrand: "True"
+ iscompare: "False"
+
+
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_m_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_m_intf.yaml
new file mode 100644
index 00000000..37ddf31a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_m_intf.yaml
@@ -0,0 +1,36 @@
+uvmf:
+ interfaces:
+ "spi_m":
+ clock: "sck"
+ reset: "rst"
+ reset_assertion_level: "True"
+ ports:
+ - name: "sclk"
+ dir: "output"
+ width: "1"
+ reset_value: "'b0"
+ - name: "ss"
+ dir: "output"
+ width: "1"
+ reset_value: "'b0"
+ - name: "mosi"
+ dir: "output"
+ width: '8'
+ reset_value: "'b0"
+ - name: "miso"
+ dir: "input"
+ width: '8'
+ reset_value: "'b0"
+ transaction_vars:
+ - iscompare: "True"
+ isrand: "True"
+ name: "ssel"
+ type: "bit"
+ - iscompare: "True"
+ isrand: "True"
+ name: "mosi"
+ type: "bit [7:0]"
+ - iscompare: "True"
+ isrand: "False"
+ name: "miso"
+ type: "bit [7:0]"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_s_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_s_intf.yaml
new file mode 100644
index 00000000..5b6d832b
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_s_intf.yaml
@@ -0,0 +1,36 @@
+uvmf:
+ interfaces:
+ "spi_s":
+ clock: "sck"
+ reset: "rst"
+ reset_assertion_level: "True"
+ ports:
+ - name: "sclk"
+ dir: "input"
+ width: "1"
+ reset_value: "'b0"
+ - name: "ss"
+ dir: "input"
+ width: "1"
+ reset_value: "'b0"
+ - name: "mosi"
+ dir: "input"
+ width: '8'
+ reset_value: "'b0"
+ - name: "miso"
+ dir: "output"
+ width: '8'
+ reset_value: "'b0"
+ transaction_vars:
+ - iscompare: "True"
+ isrand: "False"
+ name: "ssel"
+ type: "bit"
+ - iscompare: "True"
+ isrand: "False"
+ name: "mosi"
+ type: "bit [7:0]"
+ - iscompare: "True"
+ isrand: "True"
+ name: "miso"
+ type: "bit [7:0]"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_m_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_m_intf.yaml
new file mode 100644
index 00000000..368d70a2
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_m_intf.yaml
@@ -0,0 +1,73 @@
+uvmf:
+ interfaces:
+ "wb_m":
+ clock: "clock"
+ reset: "reset"
+ reset_assertion_level: 'True'
+ parameters:
+ - name: WB_ADDR_WIDTH
+ type: int
+ value: '32'
+ - name: WB_DATA_WIDTH
+ type: int
+ value: '16'
+ ports:
+ - dir: input
+ name: din
+ reset_value: '''b0'
+ width: WB_DATA_WIDTH
+ - dir: output
+ name: dout
+ reset_value: '''b0'
+ width: WB_DATA_WIDTH
+ - dir: input
+ name: "TGD_I"
+ width: WB_DATA_WIDTH
+ - dir: output
+ name: "TGD_O"
+ width: WB_DATA_WIDTH
+ - dir: output
+ name: ack
+ reset_value: 1'b0
+ width: '1'
+ - dir: output
+ name: adr
+ reset_value: '''b0'
+ width: WB_ADDR_WIDTH
+ - dir: output
+ name: cyc
+ reset_value: '0'
+ width: '1'
+ - dir: input
+ name: err
+ reset_value: '''b0'
+ width: '1'
+ - dir: output
+ name: we
+ reset_value: '0'
+ width: '1'
+ - dir: output
+ name: stb
+ reset_value: '0'
+ width: '1'
+ - dir: output
+ name: sel
+ reset_value: '''b0'
+ width: WB_DATA_WIDTH/8
+ transaction_vars:
+ - iscompare: 'True'
+ isrand: 'True'
+ name: data
+ type: "bit [WB_DATA_WIDTH-1:0]"
+ - iscompare: 'True'
+ isrand: 'True'
+ name: byte_select
+ type: "bit [(WB_DATA_WIDTH/8)-1:0]"
+ - iscompare: "True"
+ isrand: "True"
+ name: WrENB
+ type: "bit"
+ - iscompare: "True"
+ isrand: "True"
+ name: selslv
+ type: "bit"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_s_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_s_intf.yaml
new file mode 100644
index 00000000..8d5eadf0
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_s_intf.yaml
@@ -0,0 +1,61 @@
+uvmf:
+ interfaces:
+ "wb_s":
+ clock: "clock"
+ reset: "reset"
+ reset_assertion_level: 'True'
+ parameters:
+ - name: "WB_ADDR_WIDTH"
+ type: int
+ value: '32'
+ - name: "WB_DATA_WIDTH"
+ type: int
+ value: '16'
+ ports:
+ - dir: "input"
+ name: "din"
+ reset_value: '''b0'
+ width: "WB_DATA_WIDTH"
+ - dir: "output"
+ name: "dout"
+ reset_value: '''b0'
+ width: "WB_DATA_WIDTH"
+ - dir: "input"
+ name: "TGD_I"
+ width: "WB_DATA_WIDTH"
+ - dir: "output"
+ name: "TGD_O"
+ width: "WB_DATA_WIDTH"
+ - dir: "output"
+ name: "ack"
+ reset_value: '''b0'
+ width: '1'
+ - dir: "input"
+ name: "adr"
+ reset_value: '''b0'
+ width: "WB_ADDR_WIDTH"
+ - dir: "input"
+ name: "cyc"
+ reset_value: '0'
+ width: '1'
+ - dir: "output"
+ name: "err"
+ reset_value: '''b0'
+ width: '1'
+ - dir: "input"
+ name: "we"
+ reset_value: '0'
+ width: '1'
+ - dir: "input"
+ name: "stb"
+ reset_value: '0'
+ width: '1'
+ - dir: "input"
+ name: "sel"
+ reset_value: '''b0'
+ width: "WB_DATA_WIDTH/8"
+ transaction_vars:
+ - iscompare: 'True'
+ isrand: 'True'
+ name: "data"
+ type: "bit [WB_DATA_WIDTH-1:0]"
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/.project b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/.project
new file mode 100644
index 00000000..f8d875b5
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/.project
@@ -0,0 +1,37 @@
+
+
+ block_1
+
+
+
+
+
+ org.python.pydev.PyDevBuilder
+
+
+
+
+ net.sf.sveditor.core.SVProjectBuilder
+
+
+
+
+
+ net.sf.sveditor.core.SVNature
+ org.python.pydev.pythonNature
+
+
+
+ verification_ip
+ 2
+ UVMF_VIP_LIBRARY_HOME
+
+
+
+
+ UVMF_VIP_LIBRARY_HOME
+ $%7BPARENT-2-PROJECT_LOC%7D/verification_ip
+
+
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/.svproject
new file mode 100644
index 00000000..2bcfbf34
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/.svproject
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/block_1_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/block_1_sve.F
new file mode 100644
index 00000000..08e278c3
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/block_1_sve.F
@@ -0,0 +1,29 @@
+
+// UVM
++incdir+${UVM_HOME}/src
+${UVM_HOME}/src/uvm_pkg.sv
+
+// Common UVMF files
+-f ${UVMF_HOME}/common/common_sve.f
+
+// BFM Files
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_pkg_sve.F
+
+// Environment Files
+-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F
+
+// Bench Files
++incdir+./tb/tests
+./tb/tests/block_1_tests_pkg.sv
+
++incdir+./tb/sequences
+./tb/sequences/block_1_sequences_pkg.sv
+
++incdir+./tb/parameters
+./tb/parameters/block_1_parameters_pkg.sv
+
+./tb/testbench/hdl_top.sv
+./tb/testbench/hvl_top.sv
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/docs/interfaces.csv
new file mode 100644
index 00000000..784f480a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/docs/interfaces.csv
@@ -0,0 +1,16 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+,
+Interface Description, Interface Type, Interface Transaction, Interface Name,
+apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_apb_master_BFM,
+axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master1_BFM,
+axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master2_BFM,
+spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_spi_slave_BFM,
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/dut.compile
new file mode 100644
index 00000000..9b0008fc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/dut.compile
@@ -0,0 +1,6 @@
+
+# pragma uvmf custom dut_compile_info begin
+src:
+ - ./vhdl/vhdl_dut.vhd
+ - ./verilog/verilog_dut.v
+# pragma uvmf custom dut_compile_info end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/verilog/verilog_dut.v
new file mode 100644
index 00000000..96198441
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/verilog/verilog_dut.v
@@ -0,0 +1,21 @@
+module verilog_dut(clk, rst, in_signal, out_signal);
+
+input clk;
+input rst;
+input in_signal;
+output out_signal;
+
+reg out_signal_o;
+
+always @(posedge clk) begin
+ if (rst) begin
+ out_signal_o <= 0;
+ end
+ else begin
+ out_signal_o <= ~in_signal;
+ end
+ end
+
+assign out_signal = out_signal_o;
+
+endmodule
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/verilog/verilog_dut.vinfo
new file mode 100644
index 00000000..87e95f36
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/verilog/verilog_dut.vinfo
@@ -0,0 +1 @@
+verilog_dut.v
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd
new file mode 100644
index 00000000..904aa37d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity vhdl_dut is
+ port ( clk : in std_logic ;
+ rst : in std_logic ;
+ in_signal : in std_logic ;
+ out_signal :out std_logic
+ );
+end vhdl_dut;
+
+architecture rtl of vhdl_dut is
+ begin
+ P1: process
+ variable out_signal_o : std_logic;
+ begin
+ wait until clk'event and clk = '1';
+ out_signal_o := in_signal;
+ out_signal <= out_signal_o;
+ end process;
+ end rtl;
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/Makefile
new file mode 100644
index 00000000..8bf96331
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/Makefile
@@ -0,0 +1,200 @@
+
+#
+#----------------------------------------------------------------------
+#
+# DESCRIPTION: This makefile includes the shared makefile and contains
+# bench level make targets.
+#
+#----------------------------------------------------------------------
+
+
+# pragma uvmf custom additional begin
+# pragma uvmf custom additional end
+
+# *********************************************************************************************
+# UVMF library directory:
+# This variable points to the UVMF release where uvmf_base_pkg directory resides.
+# This variable points to release code that is not user modified.
+# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories.
+# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples.
+UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___
+
+# pragma uvmf custom exports begin
+#
+# Project(s) specific verification IP library:
+# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside.
+# This variable allows for your verification IP to reside independent of project bench and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip
+export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip
+#
+# Project specific bench:
+# Directory where bench specific code is located.
+# This variable allows for project_benches to reside independent of verification IP and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/
+export UVMF_PROJECT_DIR ?= $(PWD)/..
+#
+#
+# pragma uvmf custom exports end
+# *********************************************************************************************
+
+## Check PATH for required vinfo scripts
+PVAL := $(shell command -v make_filelist.py 2> /dev/null)
+ifndef PVAL
+ MFLIST = $(UVMF_HOME)/scripts/make_filelist.py
+else
+ MFLIST = make_filelist.py
+endif
+
+
+# Set test case specific Variables
+TEST_NAME ?= test_top
+
+TEST_SEED ?= random
+UVM_CLI_ARGS =
+
+# Usage of Veloce, etc. to be input by the user (subject to defaults)
+USE_VELOCE ?= 0
+
+# Usage of vinfo flow for generating file list
+USE_VINFO ?= 0
+
+# Usage of Veloce and Questa profilers
+USE_VELOCE_PROFILER ?= 0
+USE_QUESTA_PROFILER ?= 0
+
+
+# Set project Variables
+TEST_PLAN_NAME = block_1_TestPlan
+REPORTING_DO_FILE = block_1_reports_script
+
+
+# Include makefile that includes targets for UVM_VIP_Library packages
+include $(UVMF_HOME)/scripts/Makefile
+
+
+
+
+# Include all requisite interface package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/Makefile
+
+# Include all requisite environment package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/Makefile
+
+
+
+# Add to default compile/load/run arguments
+VCOM_ARGS +=
+
+# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS
+
+VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD)
+
+VELANALYZE_ARGS +=
+VELANALYZE_HVL_ARGS +=
+
+BATCH_VOPT_ARGS +=
+DEBUG_VOPT_ARGS +=
+EXTRA_VOPT_TOPS +=
+COMMON_VSIM_ARGS +=
+COMMON_VSIM_ARGS +=
+
+
+BATCH_VSIM_ARGS += #-uvmcontrol=none
+DEBUG_VSIM_ARGS +=
+EXTRA_VSIM_TOPS +=
+
+# pragma uvmf custom additional_args begin
+# pragma uvmf custom additional_args end
+
+
+# Project bench package source
+block_1_PARAMETERS_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/parameters/block_1_parameters_pkg.sv
+
+
+block_1_SEQUENCES_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/sequences/block_1_sequences_pkg.sv
+
+
+block_1_TEST_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/tests/block_1_tests_pkg.sv
+
+# pragma uvmf custom dut_files begin
+# UVMF_CHANGE_ME : Reference Verilog DUT source.
+block_1_VERILOG_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v
+
+# UVMF_CHANGE_ME : Reference VHDL DUT source.
+block_1_VHDL_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd
+# pragma uvmf custom dut_files end
+
+
+# Project bench package targets
+COMP_block_1_PARAMETERS_PKG_TGT_0 = q_comp_block_1_parameters_pkg
+COMP_block_1_PARAMETERS_PKG_TGT_1 = v_comp_block_1_parameters_pkg
+COMP_block_1_PARAMETERS_PKG_TGT = $(COMP_block_1_PARAMETERS_PKG_TGT_$(USE_VELOCE))
+
+comp_block_1_parameters_pkg: $(COMP_block_1_PARAMETERS_PKG_TGT)
+
+q_comp_block_1_parameters_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_1_PARAMETERS_PKG)
+
+v_comp_block_1_parameters_pkg: q_comp_block_1_parameters_pkg
+ $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_1_PARAMETERS_PKG)
+
+
+comp_block_1_sequence_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_1_SEQUENCES_PKG)
+
+comp_block_1_tests_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_1_TEST_PKG)
+
+# pragma uvmf custom dut_compile_make_target begin
+# UVMF_CHANGE_ME : Add make target to compile your verilog dut here
+comp_block_1_verilog_dut:
+ echo "Compile your verilog DUT here"
+ $(HDL_COMP_CMD) $(block_1_VERILOG_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here
+comp_block_1_vhdl_dut:
+ echo "Compile your vhdl DUT here"
+ $(HDL_COMP_CMD_VHDL) $(block_1_VHDL_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your dut here
+comp_block_1_dut: comp_block_1_vhdl_dut comp_block_1_verilog_dut
+# pragma uvmf custom dut_compile_make_target end
+
+
+BUILD_TGT_0 = make_build
+BUILD_TGT_1 = vinfo_build
+BUILD_TGT = $(BUILD_TGT_$(USE_VINFO))
+
+
+comp_hvl : comp_hvl_core
+
+
+comp_hvl_core : \
+ comp_apb_m_pkg comp_axi_m_pkg comp_spi_s_pkg \
+ comp_block_1_env_pkg \
+ comp_block_1_parameters_pkg comp_block_1_sequence_pkg comp_block_1_tests_pkg
+
+comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg
+
+make_build: comp_block_1_dut comp_uvmf_core comp_hvl comp_test_bench
+
+hvl_build: q_comp_apb_m_pkg q_comp_axi_m_pkg q_comp_spi_s_pkg comp_block_1_env_pkg comp_block_1_sequence_pkg comp_block_1_tests_pkg hvl_comp_testbench link optimize
+
+
+vinfo_build: comp_block_1_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT)
+
+ $(HDL_COMP_CMD) -F hdl.vf
+ $(VEL_COMP)
+
+build: $(BUILD_TGT)
+
+# pragma uvmf custom additional_targets begin
+# pragma uvmf custom additional_targets end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/bcr_testlist
new file mode 100644
index 00000000..def2371e
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/bcr_testlist
@@ -0,0 +1,19 @@
+
+
+
+# Test list for use by RMDB file
+# File syntax is
+# TB_INFO { } { }
+# TB ## All subsequent tests will run on this bench until a different "TB" line is seen
+# TEST <1st_seed> ...
+# If not enough seeds are provided then random seeds are used to pad
+# If no repeat count is given, default is 1
+# pragma uvmf custom tb_info begin
+TB_INFO block_1 { } { }
+# pragma uvmf custom tb_info end
+TB block_1
+# pragma uvmf custom regression_suite begin
+TEST test_top 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/bcr_testlist.yaml
new file mode 100644
index 00000000..e9f7fa3e
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/bcr_testlist.yaml
@@ -0,0 +1,44 @@
+
+
+
+# YAML test list for use by RMDB file
+# File syntax is
+# uvmf_testlist:
+# testbenches:
+# - name:
+# extra_build_options:
+# extra_run_options:
+# - name:
+# ...
+# - name:
+# tests:
+# - name:
+# uvm_testname: (defaults to test_name)
+# testbench: (defaults to last tb name seen)
+# repeat: (defaults to 1)
+# seeds: [,,...,] (defaults to all random)
+# extra_test_options:
+# - name:
+# ...
+# - name:
+# include:
+# - (relative path reference is to the including YAML file)
+# -
+# ...
+# -
+
+uvmf_testlist:
+ testbenches:
+# pragma uvmf custom tb_info begin
+ - name: block_1
+ extra_build_options: ""
+ extra_run_options: ""
+# pragma uvmf custom tb_info end
+ tests:
+ - testbench: block_1
+# pragma uvmf custom regression_suite begin
+ - name: test_top
+ repeat: 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/compile.do
new file mode 100644
index 00000000..9f27636d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/compile.do
@@ -0,0 +1,72 @@
+
+
+##################################################################
+## ENVIRONMENT VARIABLES
+##################################################################
+quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip
+quietly set ::env(UVMF_PROJECT_DIR) ..
+
+## Using VRM means that the build is occuring several more directories deeper underneath
+## the sim directory, need to prepend some more '..'
+if {[info exists ::env(VRM_BUILD)]} {
+ quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)"
+ quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)"
+}
+quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)]
+quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)]
+quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)"
+quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)"
+
+
+###################################################################
+## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED
+###################################################################
+file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA
+file delete -force design.bin qwave.db dpiheader.h visualizer*.ses
+file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini
+file delete -force sv_connect.*
+
+###################################################################
+## COMPILE DUT SOURCE CODE
+###################################################################
+vlib work
+# pragma uvmf custom dut_compile_dofile_target begin
+# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples
+vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v
+vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd
+# pragma uvmf custom dut_compile_dofile_target end
+
+###################################################################
+## COMPILE UVMF BASE/COMMON SOURCE CODE
+###################################################################
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f
+
+
+###################################################################
+## UVMF INTERFACE COMPILATION
+###################################################################
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/compile.do
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/compile.do
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/compile.do
+
+###################################################################
+## UVMF ENVIRONMENT COMPILATION
+###################################################################
+do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/compile.do
+
+###################################################################
+## UVMF BENCHES COMPILATION
+###################################################################
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_1_parameters_pkg.sv
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_1_sequences_pkg.sv
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_1_tests_pkg.sv
+
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f
+
+###################################################################
+## OPTIMIZATION
+###################################################################
+vopt hvl_top hdl_top -o optimized_batch_top_tb
+vopt +acc hvl_top hdl_top -o optimized_debug_top_tb
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hdl.compile
new file mode 100644
index 00000000..8e7bd41a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hdl.compile
@@ -0,0 +1,5 @@
+needs:
+# pragma uvmf custom dut_compile_info begin
+ - ../rtl/dut.compile
+# pragma uvmf custom dut_compile_info end
+ - ../tb/testbench/hdl_top.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hdl.vinfo
new file mode 100644
index 00000000..da27ec77
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hdl.vinfo
@@ -0,0 +1 @@
+@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hvl.compile
new file mode 100644
index 00000000..ce952549
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hvl.compile
@@ -0,0 +1,2 @@
+needs:
+ - ../tb/testbench/hvl_top.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hvl.vinfo
new file mode 100644
index 00000000..d22eff33
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/hvl.vinfo
@@ -0,0 +1 @@
+@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/run.do
new file mode 100644
index 00000000..101ddc48
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/run.do
@@ -0,0 +1,21 @@
+
+
+quietly set svLibs ""
+quietly set extra_vsim_args ""
+
+###################################################################
+## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS
+###################################################################
+if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} {
+ echo "Adding more args to vsim command"
+ quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS)
+}
+
+##################################################################
+## Launch Questa : generate vsim command line and execute
+##################################################################
+# pragma uvmf custom dut_run_dofile_target begin
+# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test
+quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args]
+# pragma uvmf custom dut_run_dofile_target end
+eval $cmd
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/tbx.config
new file mode 100644
index 00000000..eec58168
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/tbx.config
@@ -0,0 +1,10 @@
+
+
+
+
+
+comp -questa
+velsyn -D1S
+rtlc -allow_4ST
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/testlist
new file mode 100644
index 00000000..5ca4f2cc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/testlist
@@ -0,0 +1,20 @@
+
+
+
+
+# Test list for use by RMDB file
+# File syntax is
+# TB_INFO { } { }
+# TB ## All subsequent tests will run on this bench until a different "TB" line is seen
+# TEST <1st_seed> ...
+# If not enough seeds are provided then random seeds are used to pad
+# If no repeat count is given, default is 1
+# pragma uvmf custom tb_info begin
+TB_INFO block_1 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_1 } { }
+# pragma uvmf custom tb_info end
+TB block_1
+# pragma uvmf custom regression_suite begin
+TEST test_top 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/testlist.yaml
new file mode 100644
index 00000000..113ec8a9
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/testlist.yaml
@@ -0,0 +1,44 @@
+
+
+
+# YAML test list for use by RMDB file
+# File syntax is
+# uvmf_testlist:
+# testbenches:
+# - name:
+# extra_build_options:
+# extra_run_options:
+# - name:
+# ...
+# - name:
+# tests:
+# - name:
+# uvm_testname: (defaults to test_name)
+# testbench: (defaults to last tb name seen)
+# repeat: (defaults to 1)
+# seeds: [,,...,] (defaults to all random)
+# extra_test_options:
+# - name:
+# ...
+# - name:
+# include:
+# - (relative path reference is to the including YAML file)
+# -
+# ...
+# -
+
+uvmf_testlist:
+ testbenches:
+# pragma uvmf custom tb_info begin
+ - name: block_1
+ extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_1"
+ extra_run_options: ""
+# pragma uvmf custom tb_info end
+ tests:
+ - testbench: block_1
+# pragma uvmf custom regression_suite begin
+ - name: test_top
+ repeat: 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/top.compile
new file mode 100644
index 00000000..efd51c07
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/top.compile
@@ -0,0 +1,3 @@
+needs:
+ - hvl.compile
+ - hdl.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/veloce.config
new file mode 100644
index 00000000..d0975155
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/veloce.config
@@ -0,0 +1,26 @@
+
+
+
+
+
+# pragma uvmf custom additional begin
+comp -num_boards 1
+comp -hvl questa
+# Please choose the correct emulator type code for
+# comp -platform command or else velcomp will fail
+# Available types are:
+# - Veloce2 Quattro: D2
+# - Veloce2 Maximus: D2M
+# - Veloce Strato TiL, Ti, and Mi: Strato
+# - Veloce Strato M and Strato T: StratoM
+# - comp -platform
+comp -platform Strato
+
+rtlc -enable_tbx_pragma_checks
+rtlc -allow_4ST
+rtlc -allow_MDR
+rtlc -compile_display
+rtlc -xwave_siglist xwaves.sigs
+# pragma uvmf custom additional end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/viswave.do
new file mode 100644
index 00000000..5e690492
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/viswave.do
@@ -0,0 +1,34 @@
+
+
+onerror resume
+wave tags F0
+wave update off
+
+wave spacer -backgroundcolor Salmon { apb_master }
+wave add uvm_test_top.environment.apb_master.apb_master_monitor.txn_stream -radix string -tag F0
+wave group apb_master_bus
+wave add -group apb_master_bus hdl_top.apb_master_bus.* -radix hexadecimal -tag F0
+wave group apb_master_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { axi_master1 }
+wave add uvm_test_top.environment.axi_master1.axi_master1_monitor.txn_stream -radix string -tag F0
+wave group axi_master1_bus
+wave add -group axi_master1_bus hdl_top.axi_master1_bus.* -radix hexadecimal -tag F0
+wave group axi_master1_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { axi_master2 }
+wave add uvm_test_top.environment.axi_master2.axi_master2_monitor.txn_stream -radix string -tag F0
+wave group axi_master2_bus
+wave add -group axi_master2_bus hdl_top.axi_master2_bus.* -radix hexadecimal -tag F0
+wave group axi_master2_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { spi_slave }
+wave add uvm_test_top.environment.spi_slave.spi_slave_monitor.txn_stream -radix string -tag F0
+wave group spi_slave_bus
+wave add -group spi_slave_bus hdl_top.spi_slave_bus.* -radix hexadecimal -tag F0
+wave group spi_slave_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+
+wave update on
+WaveSetStreamView
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/wave.do
new file mode 100644
index 00000000..a290af05
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/wave.do
@@ -0,0 +1,36 @@
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+add wave -noupdate -divider apb_master
+add wave -noupdate /uvm_root/uvm_test_top/environment/apb_master/apb_master_monitor/txn_stream
+add wave -noupdate -group apb_master_bus /hdl_top/apb_master_bus/*
+add wave -noupdate -divider axi_master1
+add wave -noupdate /uvm_root/uvm_test_top/environment/axi_master1/axi_master1_monitor/txn_stream
+add wave -noupdate -group axi_master1_bus /hdl_top/axi_master1_bus/*
+add wave -noupdate -divider axi_master2
+add wave -noupdate /uvm_root/uvm_test_top/environment/axi_master2/axi_master2_monitor/txn_stream
+add wave -noupdate -group axi_master2_bus /hdl_top/axi_master2_bus/*
+add wave -noupdate -divider spi_slave
+add wave -noupdate /uvm_root/uvm_test_top/environment/spi_slave/spi_slave_monitor/txn_stream
+add wave -noupdate -group spi_slave_bus /hdl_top/spi_slave_bus/*
+
+TreeUpdate [SetDefaultTree]
+quietly wave cursor active 0
+configure wave -namecolwidth 472
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {27 ns} {168 ns}
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/xwaves.sigs
new file mode 100644
index 00000000..d75f0a57
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/sim/xwaves.sigs
@@ -0,0 +1,17 @@
+
+
+
+
+
+# pragma uvmf custom additional begin
+
+Group All
+
+#Top level signals
+hdl_top.*
+#Add additional levels or individual signals as needed
+hdl_top.*.*
+
+# pragma uvmf custom additional end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile
new file mode 100644
index 00000000..e2a26586
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile
@@ -0,0 +1,4 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+src:
+ - block_1_parameters_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv
new file mode 100644
index 00000000..455ee2fb
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv
@@ -0,0 +1,40 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package contains test level parameters
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+
+package block_1_parameters_pkg;
+
+ import uvmf_base_pkg_hdl::*;
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+
+ // These parameters are used to uniquely identify each interface. The monitor_bfm and
+ // driver_bfm are placed into and retrieved from the uvm_config_db using these string
+ // names as the field_name. The parameter is also used to enable transaction viewing
+ // from the command line for selected interfaces using the UVM command line processing.
+ parameter string apb_master_BFM = "apb_master_BFM"; /* [0] */
+ parameter string axi_master1_BFM = "axi_master1_BFM"; /* [1] */
+ parameter string axi_master2_BFM = "axi_master2_BFM"; /* [2] */
+ parameter string spi_slave_BFM = "spi_slave_BFM"; /* [3] */
+
+ // pragma uvmf custom package_item_additional begin
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo
new file mode 100644
index 00000000..8b0adcd9
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo
@@ -0,0 +1,2 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+block_1_parameters_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile
new file mode 100644
index 00000000..1497180c
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile
@@ -0,0 +1,9 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile
+ - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile
+ - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile
+ - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile
+ - ../../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile
+ - ../parameters/block_1_parameters_pkg.compile
+src:
+ - block_1_sequences_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv
new file mode 100644
index 00000000..983d03ec
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv
@@ -0,0 +1,53 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package includes all high level sequence classes used
+// in the environment. These include utility sequences and top
+// level sequences.
+//
+// CONTAINS:
+// -
+// -
+//
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+
+package block_1_sequences_pkg;
+ import uvm_pkg::*;
+ import uvmf_base_pkg::*;
+ import apb_m_pkg::*;
+ import apb_m_pkg_hdl::*;
+ import axi_m_pkg::*;
+ import axi_m_pkg_hdl::*;
+ import spi_s_pkg::*;
+ import spi_s_pkg_hdl::*;
+ import block_1_parameters_pkg::*;
+ import block_1_env_pkg::*;
+ `include "uvm_macros.svh"
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+ `include "src/block_1_bench_sequence_base.svh"
+ `include "src/register_test_sequence.svh"
+ `include "src/example_derived_test_sequence.svh"
+
+ // pragma uvmf custom package_item_additional begin
+ // UVMF_CHANGE_ME : When adding new sequences to the src directory
+ // be sure to add the sequence file here so that it will be
+ // compiled as part of the sequence package. Be sure to place
+ // the new sequence after any base sequences of the new sequence.
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo
new file mode 100644
index 00000000..b67a290f
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo
@@ -0,0 +1,8 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo
++incdir+@vinfodir
+block_1_sequences_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh
new file mode 100644
index 00000000..d404b279
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh
@@ -0,0 +1,152 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// Description: This file contains the top level and utility sequences
+// used by test_top. It can be extended to create derivative top
+// level sequences.
+//
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+
+
+typedef block_1_env_configuration block_1_env_configuration_t;
+
+class block_1_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item);
+
+ `uvm_object_utils( block_1_bench_sequence_base );
+
+ // pragma uvmf custom sequences begin
+
+typedef block_1_env_sequence_base #(
+ .CONFIG_T(block_1_env_configuration_t)
+ )
+ block_1_env_sequence_base_t;
+rand block_1_env_sequence_base_t block_1_env_seq;
+
+
+
+ // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios.
+ // Instantiate sequences here
+ typedef apb_m_random_sequence apb_master_random_seq_t;
+ apb_master_random_seq_t apb_master_random_seq;
+ typedef axi_m_random_sequence axi_master1_random_seq_t;
+ axi_master1_random_seq_t axi_master1_random_seq;
+ typedef axi_m_random_sequence axi_master2_random_seq_t;
+ axi_master2_random_seq_t axi_master2_random_seq;
+ typedef spi_s_responder_sequence spi_slave_responder_seq_t;
+ spi_slave_responder_seq_t spi_slave_responder_seq;
+ // pragma uvmf custom sequences end
+
+ // Sequencer handles for each active interface in the environment
+ typedef apb_m_transaction apb_master_transaction_t;
+ uvm_sequencer #(apb_master_transaction_t) apb_master_sequencer;
+ typedef axi_m_transaction axi_master1_transaction_t;
+ uvm_sequencer #(axi_master1_transaction_t) axi_master1_sequencer;
+ typedef axi_m_transaction axi_master2_transaction_t;
+ uvm_sequencer #(axi_master2_transaction_t) axi_master2_sequencer;
+ typedef spi_s_transaction spi_slave_transaction_t;
+ uvm_sequencer #(spi_slave_transaction_t) spi_slave_sequencer;
+
+
+ // Top level environment configuration handle
+ block_1_env_configuration_t top_configuration;
+
+ // Configuration handles to access interface BFM's
+ apb_m_configuration apb_master_config;
+ axi_m_configuration axi_master1_config;
+ axi_m_configuration axi_master2_config;
+ spi_s_configuration spi_slave_config;
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ // ****************************************************************************
+ function new( string name = "" );
+ super.new( name );
+ // Retrieve the configuration handles from the uvm_config_db
+
+ // Retrieve top level configuration handle
+ if ( !uvm_config_db#(block_1_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin
+ `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE);
+ `uvm_fatal("CFG", "uvm_config_db#(block_1_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG");
+ end
+
+ // Retrieve config handles for all agents
+ if( !uvm_config_db #( apb_m_configuration )::get( null , UVMF_CONFIGURATIONS , apb_master_BFM , apb_master_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( apb_m_configuration )::get cannot find resource apb_master_BFM" )
+ if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , axi_master1_BFM , axi_master1_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource axi_master1_BFM" )
+ if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , axi_master2_BFM , axi_master2_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource axi_master2_BFM" )
+ if( !uvm_config_db #( spi_s_configuration )::get( null , UVMF_CONFIGURATIONS , spi_slave_BFM , spi_slave_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( spi_s_configuration )::get cannot find resource spi_slave_BFM" )
+
+ // Assign the sequencer handles from the handles within agent configurations
+ apb_master_sequencer = apb_master_config.get_sequencer();
+ axi_master1_sequencer = axi_master1_config.get_sequencer();
+ axi_master2_sequencer = axi_master2_config.get_sequencer();
+ spi_slave_sequencer = spi_slave_config.get_sequencer();
+
+
+
+ // pragma uvmf custom new begin
+ // pragma uvmf custom new end
+
+ endfunction
+
+ // ****************************************************************************
+ virtual task body();
+ // pragma uvmf custom body begin
+
+ // Construct sequences here
+
+ block_1_env_seq = block_1_env_sequence_base_t::type_id::create("block_1_env_seq");
+
+ apb_master_random_seq = apb_master_random_seq_t::type_id::create("apb_master_random_seq");
+ axi_master1_random_seq = axi_master1_random_seq_t::type_id::create("axi_master1_random_seq");
+ axi_master2_random_seq = axi_master2_random_seq_t::type_id::create("axi_master2_random_seq");
+ spi_slave_responder_seq = spi_slave_responder_seq_t::type_id::create("spi_slave_responder_seq");
+ fork
+ apb_master_config.wait_for_reset();
+ axi_master1_config.wait_for_reset();
+ axi_master2_config.wait_for_reset();
+ spi_slave_config.wait_for_reset();
+ join
+ // Start RESPONDER sequences here
+ fork
+ spi_slave_responder_seq.start(spi_slave_sequencer);
+ join_none
+ // Start INITIATOR sequences here
+ fork
+ repeat (25) apb_master_random_seq.start(apb_master_sequencer);
+ repeat (25) axi_master1_random_seq.start(axi_master1_sequencer);
+ repeat (25) axi_master2_random_seq.start(axi_master2_sequencer);
+ join
+
+block_1_env_seq.start(top_configuration.vsqr);
+
+ // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after
+ // the last sequence to allow for the last sequence item to flow
+ // through the design.
+ fork
+ apb_master_config.wait_for_num_clocks(400);
+ axi_master1_config.wait_for_num_clocks(400);
+ axi_master2_config.wait_for_num_clocks(400);
+ spi_slave_config.wait_for_num_clocks(400);
+ join
+
+ // pragma uvmf custom body end
+ endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh
new file mode 100644
index 00000000..b4127d2f
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh
@@ -0,0 +1,30 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This file contains the top level sequence used in example_derived_test.
+// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base
+// and can override %(benchName)_bench_sequence_base.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class example_derived_test_sequence extends block_1_bench_sequence_base;
+
+ `uvm_object_utils( example_derived_test_sequence );
+
+ function new(string name = "" );
+ super.new(name);
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/src/register_test_sequence.svh
new file mode 100644
index 00000000..dd9e3574
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/sequences/src/register_test_sequence.svh
@@ -0,0 +1,59 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This file contains the top level sequence used in register_test.
+// It uses the UVM built in register test. Specific UVM built-in tests can be
+// selected in the body task.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class register_test_sequence extends block_1_bench_sequence_base;
+
+ `uvm_object_utils( register_test_sequence );
+
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ function new(string name = "" );
+ super.new(name);
+ endfunction
+
+ // ****************************************************************************
+ virtual task body();
+
+ // Reset the DUT
+ fork
+ // pragma uvmf custom register_test_reset begin
+ // UVMF_CHANGE_ME
+ // Select the desired wait_for_reset or provide custom mechanism.
+ // fork-join for this code block may be unnecessary based on your situation.
+ apb_master_config.wait_for_reset();
+ axi_master1_config.wait_for_reset();
+ axi_master2_config.wait_for_reset();
+ spi_slave_config.wait_for_reset();
+ // pragma uvmf custom register_test_reset end
+ join
+
+ // pragma uvmf custom register_test_setup begin
+ // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence.
+ // pragma uvmf custom register_test_setup end
+
+ // pragma uvmf custom register_test_operation begin
+ // UVMF_CHANGE_ME Perform your custom register test
+ // pragma uvmf custom register_test_operation end
+
+ endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hdl_top.compile
new file mode 100644
index 00000000..09b570fb
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hdl_top.compile
@@ -0,0 +1,11 @@
+incdir:
+ - ${uvm_path}/src
+ - .
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+ - ../parameters/block_1_parameters_pkg.compile
+ - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile
+ - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile
+ - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile
+src:
+ - hdl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hdl_top.sv
new file mode 100644
index 00000000..ad500b09
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hdl_top.sv
@@ -0,0 +1,119 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// Description: This top level module instantiates all synthesizable
+// static content. This and tb_top.sv are the two top level modules
+// of the simulation.
+//
+// This module instantiates the following:
+// DUT: The Design Under Test
+// Interfaces: Signal bundles that contain signals connected to DUT
+// Driver BFM's: BFM's that actively drive interface signals
+// Monitor BFM's: BFM's that passively monitor interface signals
+//
+//----------------------------------------------------------------------
+
+//----------------------------------------------------------------------
+//
+
+module hdl_top;
+
+import block_1_parameters_pkg::*;
+import uvmf_base_pkg_hdl::*;
+
+ // pragma attribute hdl_top partition_module_xrtl
+// pragma uvmf custom clock_generator begin
+ bit clk;
+ // Instantiate a clk driver
+ // tbx clkgen
+ initial begin
+ clk = 0;
+ #9ns;
+ forever begin
+ clk = ~clk;
+ #5ns;
+ end
+ end
+// pragma uvmf custom clock_generator end
+
+// pragma uvmf custom reset_generator begin
+ bit rst;
+ // Instantiate a rst driver
+ // tbx clkgen
+ initial begin
+ rst = 1;
+ #200ns;
+ rst = 0;
+ end
+// pragma uvmf custom reset_generator end
+
+ // pragma uvmf custom module_item_additional begin
+ // pragma uvmf custom module_item_additional end
+
+ // Instantiate the signal bundle, monitor bfm and driver bfm for each interface.
+ // The signal bundle, _if, contains signals to be connected to the DUT.
+ // The monitor, monitor_bfm, observes the bus, _if, and captures transactions.
+ // The driver, driver_bfm, drives transactions onto the bus, _if.
+ apb_m_if apb_master_bus(
+ // pragma uvmf custom apb_master_bus_connections begin
+ .pclk(clk), .presetn(rst)
+ // pragma uvmf custom apb_master_bus_connections end
+ );
+ axi_m_if axi_master1_bus(
+ // pragma uvmf custom axi_master1_bus_connections begin
+ .axi_clk(clk), .rst(rst)
+ // pragma uvmf custom axi_master1_bus_connections end
+ );
+ axi_m_if axi_master2_bus(
+ // pragma uvmf custom axi_master2_bus_connections begin
+ .axi_clk(clk), .rst(rst)
+ // pragma uvmf custom axi_master2_bus_connections end
+ );
+ spi_s_if spi_slave_bus(
+ // pragma uvmf custom spi_slave_bus_connections begin
+ .sck(clk), .rst(rst)
+ // pragma uvmf custom spi_slave_bus_connections end
+ );
+ apb_m_monitor_bfm apb_master_mon_bfm(apb_master_bus.monitor_port);
+ axi_m_monitor_bfm axi_master1_mon_bfm(axi_master1_bus.monitor_port);
+ axi_m_monitor_bfm axi_master2_mon_bfm(axi_master2_bus.monitor_port);
+ spi_s_monitor_bfm spi_slave_mon_bfm(spi_slave_bus.monitor_port);
+ apb_m_driver_bfm apb_master_drv_bfm(apb_master_bus.initiator_port);
+ axi_m_driver_bfm axi_master1_drv_bfm(axi_master1_bus.initiator_port);
+ axi_m_driver_bfm axi_master2_drv_bfm(axi_master2_bus.initiator_port);
+ spi_s_driver_bfm spi_slave_drv_bfm(spi_slave_bus.responder_port);
+
+ // pragma uvmf custom dut_instantiation begin
+ // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above
+ // Instantiate your DUT here
+ // These DUT's instantiated to show verilog and vhdl instantiation
+ verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal));
+ vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal));
+ // pragma uvmf custom dut_instantiation end
+
+ initial begin // tbx vif_binding_block
+ import uvm_pkg::uvm_config_db;
+ // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db.
+ // They are placed into the uvm_config_db using the string names defined in the parameters package.
+ // The string names are passed to the agent configurations by test_top through the top level configuration.
+ // They are retrieved by the agents configuration class for use by the agent.
+ uvm_config_db #( virtual apb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , apb_master_BFM , apb_master_mon_bfm );
+ uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master1_BFM , axi_master1_mon_bfm );
+ uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master2_BFM , axi_master2_mon_bfm );
+ uvm_config_db #( virtual spi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_slave_BFM , spi_slave_mon_bfm );
+ uvm_config_db #( virtual apb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , apb_master_BFM , apb_master_drv_bfm );
+ uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master1_BFM , axi_master1_drv_bfm );
+ uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master2_BFM , axi_master2_drv_bfm );
+ uvm_config_db #( virtual spi_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_slave_BFM , spi_slave_drv_bfm );
+ end
+
+endmodule
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hdl_top.vinfo
new file mode 100644
index 00000000..43c7c76e
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hdl_top.vinfo
@@ -0,0 +1,7 @@
+@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_bfm.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_bfm.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_bfm.vinfo
+hdl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hvl_top.compile
new file mode 100644
index 00000000..d8d273c1
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hvl_top.compile
@@ -0,0 +1,7 @@
+incdir:
+ - ${uvm_path}/src
+ - .
+needs:
+ - ../tests/block_1_tests_pkg.compile
+src:
+ - hvl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hvl_top.sv
new file mode 100644
index 00000000..89ae61f4
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hvl_top.sv
@@ -0,0 +1,33 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This module loads the test package and starts the UVM phases.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+module hvl_top;
+
+import uvm_pkg::*;
+import block_1_tests_pkg::*;
+
+ // pragma uvmf custom module_item_additional begin
+ // pragma uvmf custom module_item_additional end
+
+ initial begin
+ $timeformat(-9,3,"ns",5);
+ run_test();
+ end
+
+endmodule
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hvl_top.vinfo
new file mode 100644
index 00000000..7bc43d3a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/hvl_top.vinfo
@@ -0,0 +1,2 @@
+@use $UVMF_PROJECT_DIR/tb/tests/block_1_tests_pkg.vinfo
+hvl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/top_filelist_hdl.f
new file mode 100644
index 00000000..1e9dab65
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/top_filelist_hdl.f
@@ -0,0 +1,3 @@
+$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/top_filelist_hvl.f
new file mode 100644
index 00000000..42383ab2
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/testbench/top_filelist_hvl.f
@@ -0,0 +1,3 @@
+$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/block_1_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/block_1_tests_pkg.compile
new file mode 100644
index 00000000..ccf235f0
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/block_1_tests_pkg.compile
@@ -0,0 +1,10 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile
+ - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile
+ - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile
+ - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile
+ - ../../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile
+ - ../parameters/block_1_parameters_pkg.compile
+ - ../sequences/block_1_sequences_pkg.compile
+src:
+ - block_1_tests_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/block_1_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/block_1_tests_pkg.sv
new file mode 100644
index 00000000..933ace9a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/block_1_tests_pkg.sv
@@ -0,0 +1,56 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package contains all tests currently written for
+// the simulation project. Once compiled, any test can be selected
+// from the vsim command line using +UVM_TESTNAME=yourTestNameHere
+//
+// CONTAINS:
+// -
+// -
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+package block_1_tests_pkg;
+
+ import uvm_pkg::*;
+ import uvmf_base_pkg::*;
+ import block_1_parameters_pkg::*;
+ import block_1_env_pkg::*;
+ import block_1_sequences_pkg::*;
+ import apb_m_pkg::*;
+ import apb_m_pkg_hdl::*;
+ import axi_m_pkg::*;
+ import axi_m_pkg_hdl::*;
+ import spi_s_pkg::*;
+ import spi_s_pkg_hdl::*;
+
+
+ `include "uvm_macros.svh"
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+ `include "src/test_top.svh"
+ `include "src/register_test.svh"
+ `include "src/example_derived_test.svh"
+
+ // pragma uvmf custom package_item_additional begin
+ // UVMF_CHANGE_ME : When adding new tests to the src directory
+ // be sure to add the test file here so that it will be
+ // compiled as part of the test package. Be sure to place
+ // the new test after any base tests of the new test.
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo
new file mode 100644
index 00000000..9fe7bfbf
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo
@@ -0,0 +1,9 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/sequences/block_1_sequences_pkg.vinfo
++incdir+@vinfodir
+block_1_tests_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/src/example_derived_test.svh
new file mode 100644
index 00000000..346ac7c4
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/src/example_derived_test.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+// changes to test_top using the UVM factory type_override:
+//
+// Test scenario:
+// This is a template test that can be used to create future tests.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class example_derived_test extends test_top;
+
+ `uvm_component_utils( example_derived_test );
+
+ function new( string name = "", uvm_component parent = null );
+ super.new( name, parent );
+ endfunction
+
+ virtual function void build_phase(uvm_phase phase);
+ // The factory override below is an example of how to replace the block_1_bench_sequence_base
+ // sequence with the example_derived_test_sequence.
+ block_1_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type());
+ // Execute the build_phase of test_top AFTER all factory overrides have been created.
+ super.build_phase(phase);
+ // pragma uvmf custom configuration_settings_post_randomize begin
+ // UVMF_CHANGE_ME Test specific configuration values can be set here.
+ // The configuration structure has already been randomized.
+ // pragma uvmf custom configuration_settings_post_randomize end
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/src/register_test.svh
new file mode 100644
index 00000000..ae1d329c
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/src/register_test.svh
@@ -0,0 +1,40 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+// changes to test_top using the UVM factory type_override:
+//
+// Test scenario:
+// This is a template test that can be used to create future tests.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class register_test extends test_top;
+
+ `uvm_component_utils( register_test );
+
+ function new( string name = "", uvm_component parent = null );
+ super.new( name, parent );
+ endfunction
+
+ virtual function void build_phase(uvm_phase phase);
+ // The factory override below replaces the block_1_bench_sequence_base
+ // sequence with the register_test_sequence.
+ block_1_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type());
+ // Execute the build_phase of test_top AFTER all factory overrides have been created.
+ super.build_phase(phase);
+ endfunction
+
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/src/test_top.svh
new file mode 100644
index 00000000..124672ba
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/tb/tests/src/test_top.svh
@@ -0,0 +1,82 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+// Description: This top level UVM test is the base class for all
+// future tests created for this project.
+//
+// This test class contains:
+// Configuration: The top level configuration for the project.
+// Environment: The top level environment for the project.
+// Top_level_sequence: The top level sequence for the project.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+typedef block_1_env_configuration block_1_env_configuration_t;
+typedef block_1_environment block_1_environment_t;
+
+class test_top extends uvmf_test_base #(.CONFIG_T(block_1_env_configuration_t),
+ .ENV_T(block_1_environment_t),
+ .TOP_LEVEL_SEQ_T(block_1_bench_sequence_base));
+
+ `uvm_component_utils( test_top );
+
+
+
+ string interface_names[] = {
+ apb_master_BFM /* apb_master [0] */ ,
+ axi_master1_BFM /* axi_master1 [1] */ ,
+ axi_master2_BFM /* axi_master2 [2] */ ,
+ spi_slave_BFM /* spi_slave [3] */
+};
+
+uvmf_active_passive_t interface_activities[] = {
+ ACTIVE /* apb_master [0] */ ,
+ ACTIVE /* axi_master1 [1] */ ,
+ ACTIVE /* axi_master2 [2] */ ,
+ ACTIVE /* spi_slave [3] */ };
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ // ****************************************************************************
+ // FUNCTION: new()
+ // This is the standard systemVerilog constructor. All components are
+ // constructed in the build_phase to allow factory overriding.
+ //
+ function new( string name = "", uvm_component parent = null );
+ super.new( name ,parent );
+ endfunction
+
+
+
+ // ****************************************************************************
+ // FUNCTION: build_phase()
+ // The construction of the configuration and environment classes is done in
+ // the build_phase of uvmf_test_base. Once the configuraton and environment
+ // classes are built then the initialize call is made to perform the
+ // following:
+ // Monitor and driver BFM virtual interface handle passing into agents
+ // Set the active/passive state for each agent
+ // Once this build_phase completes, the build_phase of the environment is
+ // executed which builds the agents.
+ //
+ virtual function void build_phase(uvm_phase phase);
+// pragma uvmf custom build_phase_pre_super begin
+// pragma uvmf custom build_phase_pre_super end
+ super.build_phase(phase);
+ // pragma uvmf custom configuration_settings_post_randomize begin
+ // pragma uvmf custom configuration_settings_post_randomize end
+ configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities);
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/yaml/block_1_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/yaml/block_1_bench.yaml
new file mode 100644
index 00000000..d52f051f
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_1/yaml/block_1_bench.yaml
@@ -0,0 +1,21 @@
+uvmf:
+ benches:
+ block_1:
+ active_passive:
+ - bfm_name: apb_master
+ value: ACTIVE
+ - bfm_name: axi_master1
+ value: ACTIVE
+ - bfm_name: axi_master2
+ value: ACTIVE
+ - bfm_name: spi_slave
+ value: ACTIVE
+ active_passive_default: ACTIVE
+ clock_half_period: 5ns
+ clock_phase_offset: 9ns
+ existing_library_component: 'True'
+ interface_params: []
+ reset_assertion_level: 'True'
+ reset_duration: 200ns
+ top_env: block_1
+ use_dpi_link: 'False'
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/.project b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/.project
new file mode 100644
index 00000000..e070225f
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/.project
@@ -0,0 +1,37 @@
+
+
+ block_2
+
+
+
+
+
+ org.python.pydev.PyDevBuilder
+
+
+
+
+ net.sf.sveditor.core.SVProjectBuilder
+
+
+
+
+
+ net.sf.sveditor.core.SVNature
+ org.python.pydev.pythonNature
+
+
+
+ verification_ip
+ 2
+ UVMF_VIP_LIBRARY_HOME
+
+
+
+
+ UVMF_VIP_LIBRARY_HOME
+ $%7BPARENT-2-PROJECT_LOC%7D/verification_ip
+
+
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/.svproject
new file mode 100644
index 00000000..b5a7f95a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/.svproject
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/block_2_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/block_2_sve.F
new file mode 100644
index 00000000..83f3e49e
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/block_2_sve.F
@@ -0,0 +1,28 @@
+
+// UVM
++incdir+${UVM_HOME}/src
+${UVM_HOME}/src/uvm_pkg.sv
+
+// Common UVMF files
+-f ${UVMF_HOME}/common/common_sve.f
+
+// BFM Files
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_pkg_sve.F
+
+// Environment Files
+-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F
+
+// Bench Files
++incdir+./tb/tests
+./tb/tests/block_2_tests_pkg.sv
+
++incdir+./tb/sequences
+./tb/sequences/block_2_sequences_pkg.sv
+
++incdir+./tb/parameters
+./tb/parameters/block_2_parameters_pkg.sv
+
+./tb/testbench/hdl_top.sv
+./tb/testbench/hvl_top.sv
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/docs/interfaces.csv
new file mode 100644
index 00000000..de1a17a2
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/docs/interfaces.csv
@@ -0,0 +1,14 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+,
+Interface Description, Interface Type, Interface Transaction, Interface Name,
+spi_master, spi_m_driver_bfm spi_m_monitor_bfm, spi_m_transaction, spi_m_pkg_spi_master_BFM,
+wb_slave, wb_s_driver_bfm wb_s_monitor_bfm, wb_s_transaction, wb_s_pkg_wb_slave_BFM,
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/dut.compile
new file mode 100644
index 00000000..9b0008fc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/dut.compile
@@ -0,0 +1,6 @@
+
+# pragma uvmf custom dut_compile_info begin
+src:
+ - ./vhdl/vhdl_dut.vhd
+ - ./verilog/verilog_dut.v
+# pragma uvmf custom dut_compile_info end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/verilog/verilog_dut.v
new file mode 100644
index 00000000..96198441
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/verilog/verilog_dut.v
@@ -0,0 +1,21 @@
+module verilog_dut(clk, rst, in_signal, out_signal);
+
+input clk;
+input rst;
+input in_signal;
+output out_signal;
+
+reg out_signal_o;
+
+always @(posedge clk) begin
+ if (rst) begin
+ out_signal_o <= 0;
+ end
+ else begin
+ out_signal_o <= ~in_signal;
+ end
+ end
+
+assign out_signal = out_signal_o;
+
+endmodule
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/verilog/verilog_dut.vinfo
new file mode 100644
index 00000000..87e95f36
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/verilog/verilog_dut.vinfo
@@ -0,0 +1 @@
+verilog_dut.v
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd
new file mode 100644
index 00000000..904aa37d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity vhdl_dut is
+ port ( clk : in std_logic ;
+ rst : in std_logic ;
+ in_signal : in std_logic ;
+ out_signal :out std_logic
+ );
+end vhdl_dut;
+
+architecture rtl of vhdl_dut is
+ begin
+ P1: process
+ variable out_signal_o : std_logic;
+ begin
+ wait until clk'event and clk = '1';
+ out_signal_o := in_signal;
+ out_signal <= out_signal_o;
+ end process;
+ end rtl;
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/Makefile
new file mode 100644
index 00000000..4bea4673
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/Makefile
@@ -0,0 +1,199 @@
+
+#
+#----------------------------------------------------------------------
+#
+# DESCRIPTION: This makefile includes the shared makefile and contains
+# bench level make targets.
+#
+#----------------------------------------------------------------------
+
+
+# pragma uvmf custom additional begin
+# pragma uvmf custom additional end
+
+# *********************************************************************************************
+# UVMF library directory:
+# This variable points to the UVMF release where uvmf_base_pkg directory resides.
+# This variable points to release code that is not user modified.
+# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories.
+# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples.
+UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___
+
+# pragma uvmf custom exports begin
+#
+# Project(s) specific verification IP library:
+# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside.
+# This variable allows for your verification IP to reside independent of project bench and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip
+export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip
+#
+# Project specific bench:
+# Directory where bench specific code is located.
+# This variable allows for project_benches to reside independent of verification IP and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/
+export UVMF_PROJECT_DIR ?= $(PWD)/..
+#
+#
+# pragma uvmf custom exports end
+# *********************************************************************************************
+
+## Check PATH for required vinfo scripts
+PVAL := $(shell command -v make_filelist.py 2> /dev/null)
+ifndef PVAL
+ MFLIST = $(UVMF_HOME)/scripts/make_filelist.py
+else
+ MFLIST = make_filelist.py
+endif
+
+
+# Set test case specific Variables
+TEST_NAME ?= test_top
+
+TEST_SEED ?= random
+UVM_CLI_ARGS =
+
+# Usage of Veloce, etc. to be input by the user (subject to defaults)
+USE_VELOCE ?= 0
+
+# Usage of vinfo flow for generating file list
+USE_VINFO ?= 0
+
+# Usage of Veloce and Questa profilers
+USE_VELOCE_PROFILER ?= 0
+USE_QUESTA_PROFILER ?= 0
+
+
+# Set project Variables
+TEST_PLAN_NAME = block_2_TestPlan
+REPORTING_DO_FILE = block_2_reports_script
+
+
+# Include makefile that includes targets for UVM_VIP_Library packages
+include $(UVMF_HOME)/scripts/Makefile
+
+
+
+
+# Include all requisite interface package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/Makefile
+
+# Include all requisite environment package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/Makefile
+
+
+
+# Add to default compile/load/run arguments
+VCOM_ARGS +=
+
+# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS
+
+VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD)
+
+VELANALYZE_ARGS +=
+VELANALYZE_HVL_ARGS +=
+
+BATCH_VOPT_ARGS +=
+DEBUG_VOPT_ARGS +=
+EXTRA_VOPT_TOPS +=
+COMMON_VSIM_ARGS +=
+COMMON_VSIM_ARGS +=
+
+
+BATCH_VSIM_ARGS += #-uvmcontrol=none
+DEBUG_VSIM_ARGS +=
+EXTRA_VSIM_TOPS +=
+
+# pragma uvmf custom additional_args begin
+# pragma uvmf custom additional_args end
+
+
+# Project bench package source
+block_2_PARAMETERS_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/parameters/block_2_parameters_pkg.sv
+
+
+block_2_SEQUENCES_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/sequences/block_2_sequences_pkg.sv
+
+
+block_2_TEST_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/tests/block_2_tests_pkg.sv
+
+# pragma uvmf custom dut_files begin
+# UVMF_CHANGE_ME : Reference Verilog DUT source.
+block_2_VERILOG_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v
+
+# UVMF_CHANGE_ME : Reference VHDL DUT source.
+block_2_VHDL_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd
+# pragma uvmf custom dut_files end
+
+
+# Project bench package targets
+COMP_block_2_PARAMETERS_PKG_TGT_0 = q_comp_block_2_parameters_pkg
+COMP_block_2_PARAMETERS_PKG_TGT_1 = v_comp_block_2_parameters_pkg
+COMP_block_2_PARAMETERS_PKG_TGT = $(COMP_block_2_PARAMETERS_PKG_TGT_$(USE_VELOCE))
+
+comp_block_2_parameters_pkg: $(COMP_block_2_PARAMETERS_PKG_TGT)
+
+q_comp_block_2_parameters_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_2_PARAMETERS_PKG)
+
+v_comp_block_2_parameters_pkg: q_comp_block_2_parameters_pkg
+ $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_2_PARAMETERS_PKG)
+
+
+comp_block_2_sequence_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_2_SEQUENCES_PKG)
+
+comp_block_2_tests_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_2_TEST_PKG)
+
+# pragma uvmf custom dut_compile_make_target begin
+# UVMF_CHANGE_ME : Add make target to compile your verilog dut here
+comp_block_2_verilog_dut:
+ echo "Compile your verilog DUT here"
+ $(HDL_COMP_CMD) $(block_2_VERILOG_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here
+comp_block_2_vhdl_dut:
+ echo "Compile your vhdl DUT here"
+ $(HDL_COMP_CMD_VHDL) $(block_2_VHDL_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your dut here
+comp_block_2_dut: comp_block_2_vhdl_dut comp_block_2_verilog_dut
+# pragma uvmf custom dut_compile_make_target end
+
+
+BUILD_TGT_0 = make_build
+BUILD_TGT_1 = vinfo_build
+BUILD_TGT = $(BUILD_TGT_$(USE_VINFO))
+
+
+comp_hvl : comp_hvl_core
+
+
+comp_hvl_core : \
+ comp_spi_m_pkg comp_wb_s_pkg \
+ comp_block_2_env_pkg \
+ comp_block_2_parameters_pkg comp_block_2_sequence_pkg comp_block_2_tests_pkg
+
+comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg
+
+make_build: comp_block_2_dut comp_uvmf_core comp_hvl comp_test_bench
+
+hvl_build: q_comp_spi_m_pkg q_comp_wb_s_pkg comp_block_2_env_pkg comp_block_2_sequence_pkg comp_block_2_tests_pkg hvl_comp_testbench link optimize
+
+
+vinfo_build: comp_block_2_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT)
+
+ $(HDL_COMP_CMD) -F hdl.vf
+ $(VEL_COMP)
+
+build: $(BUILD_TGT)
+
+# pragma uvmf custom additional_targets begin
+# pragma uvmf custom additional_targets end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/bcr_testlist
new file mode 100644
index 00000000..5c61ad72
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/bcr_testlist
@@ -0,0 +1,19 @@
+
+
+
+# Test list for use by RMDB file
+# File syntax is
+# TB_INFO { } { }
+# TB ## All subsequent tests will run on this bench until a different "TB" line is seen
+# TEST <1st_seed> ...
+# If not enough seeds are provided then random seeds are used to pad
+# If no repeat count is given, default is 1
+# pragma uvmf custom tb_info begin
+TB_INFO block_2 { } { }
+# pragma uvmf custom tb_info end
+TB block_2
+# pragma uvmf custom regression_suite begin
+TEST test_top 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/bcr_testlist.yaml
new file mode 100644
index 00000000..1a81a584
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/bcr_testlist.yaml
@@ -0,0 +1,44 @@
+
+
+
+# YAML test list for use by RMDB file
+# File syntax is
+# uvmf_testlist:
+# testbenches:
+# - name:
+# extra_build_options:
+# extra_run_options:
+# - name:
+# ...
+# - name:
+# tests:
+# - name:
+# uvm_testname: (defaults to test_name)
+# testbench: (defaults to last tb name seen)
+# repeat: (defaults to 1)
+# seeds: [,,...,] (defaults to all random)
+# extra_test_options:
+# - name:
+# ...
+# - name:
+# include:
+# - (relative path reference is to the including YAML file)
+# -
+# ...
+# -
+
+uvmf_testlist:
+ testbenches:
+# pragma uvmf custom tb_info begin
+ - name: block_2
+ extra_build_options: ""
+ extra_run_options: ""
+# pragma uvmf custom tb_info end
+ tests:
+ - testbench: block_2
+# pragma uvmf custom regression_suite begin
+ - name: test_top
+ repeat: 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/compile.do
new file mode 100644
index 00000000..74950ae6
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/compile.do
@@ -0,0 +1,71 @@
+
+
+##################################################################
+## ENVIRONMENT VARIABLES
+##################################################################
+quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip
+quietly set ::env(UVMF_PROJECT_DIR) ..
+
+## Using VRM means that the build is occuring several more directories deeper underneath
+## the sim directory, need to prepend some more '..'
+if {[info exists ::env(VRM_BUILD)]} {
+ quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)"
+ quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)"
+}
+quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)]
+quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)]
+quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)"
+quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)"
+
+
+###################################################################
+## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED
+###################################################################
+file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA
+file delete -force design.bin qwave.db dpiheader.h visualizer*.ses
+file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini
+file delete -force sv_connect.*
+
+###################################################################
+## COMPILE DUT SOURCE CODE
+###################################################################
+vlib work
+# pragma uvmf custom dut_compile_dofile_target begin
+# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples
+vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v
+vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd
+# pragma uvmf custom dut_compile_dofile_target end
+
+###################################################################
+## COMPILE UVMF BASE/COMMON SOURCE CODE
+###################################################################
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f
+
+
+###################################################################
+## UVMF INTERFACE COMPILATION
+###################################################################
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/compile.do
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/compile.do
+
+###################################################################
+## UVMF ENVIRONMENT COMPILATION
+###################################################################
+do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/compile.do
+
+###################################################################
+## UVMF BENCHES COMPILATION
+###################################################################
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_2_parameters_pkg.sv
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_2_sequences_pkg.sv
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_2_tests_pkg.sv
+
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f
+
+###################################################################
+## OPTIMIZATION
+###################################################################
+vopt hvl_top hdl_top -o optimized_batch_top_tb
+vopt +acc hvl_top hdl_top -o optimized_debug_top_tb
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hdl.compile
new file mode 100644
index 00000000..8e7bd41a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hdl.compile
@@ -0,0 +1,5 @@
+needs:
+# pragma uvmf custom dut_compile_info begin
+ - ../rtl/dut.compile
+# pragma uvmf custom dut_compile_info end
+ - ../tb/testbench/hdl_top.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hdl.vinfo
new file mode 100644
index 00000000..da27ec77
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hdl.vinfo
@@ -0,0 +1 @@
+@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hvl.compile
new file mode 100644
index 00000000..ce952549
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hvl.compile
@@ -0,0 +1,2 @@
+needs:
+ - ../tb/testbench/hvl_top.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hvl.vinfo
new file mode 100644
index 00000000..d22eff33
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/hvl.vinfo
@@ -0,0 +1 @@
+@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/run.do
new file mode 100644
index 00000000..101ddc48
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/run.do
@@ -0,0 +1,21 @@
+
+
+quietly set svLibs ""
+quietly set extra_vsim_args ""
+
+###################################################################
+## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS
+###################################################################
+if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} {
+ echo "Adding more args to vsim command"
+ quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS)
+}
+
+##################################################################
+## Launch Questa : generate vsim command line and execute
+##################################################################
+# pragma uvmf custom dut_run_dofile_target begin
+# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test
+quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args]
+# pragma uvmf custom dut_run_dofile_target end
+eval $cmd
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/tbx.config
new file mode 100644
index 00000000..eec58168
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/tbx.config
@@ -0,0 +1,10 @@
+
+
+
+
+
+comp -questa
+velsyn -D1S
+rtlc -allow_4ST
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/testlist
new file mode 100644
index 00000000..f92fb15b
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/testlist
@@ -0,0 +1,20 @@
+
+
+
+
+# Test list for use by RMDB file
+# File syntax is
+# TB_INFO { } { }
+# TB ## All subsequent tests will run on this bench until a different "TB" line is seen
+# TEST <1st_seed> ...
+# If not enough seeds are provided then random seeds are used to pad
+# If no repeat count is given, default is 1
+# pragma uvmf custom tb_info begin
+TB_INFO block_2 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_2 } { }
+# pragma uvmf custom tb_info end
+TB block_2
+# pragma uvmf custom regression_suite begin
+TEST test_top 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/testlist.yaml
new file mode 100644
index 00000000..f6cabad6
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/testlist.yaml
@@ -0,0 +1,44 @@
+
+
+
+# YAML test list for use by RMDB file
+# File syntax is
+# uvmf_testlist:
+# testbenches:
+# - name:
+# extra_build_options:
+# extra_run_options:
+# - name:
+# ...
+# - name:
+# tests:
+# - name:
+# uvm_testname: (defaults to test_name)
+# testbench: (defaults to last tb name seen)
+# repeat: (defaults to 1)
+# seeds: [,,...,] (defaults to all random)
+# extra_test_options:
+# - name:
+# ...
+# - name:
+# include:
+# - (relative path reference is to the including YAML file)
+# -
+# ...
+# -
+
+uvmf_testlist:
+ testbenches:
+# pragma uvmf custom tb_info begin
+ - name: block_2
+ extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_2"
+ extra_run_options: ""
+# pragma uvmf custom tb_info end
+ tests:
+ - testbench: block_2
+# pragma uvmf custom regression_suite begin
+ - name: test_top
+ repeat: 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/top.compile
new file mode 100644
index 00000000..efd51c07
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/top.compile
@@ -0,0 +1,3 @@
+needs:
+ - hvl.compile
+ - hdl.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/veloce.config
new file mode 100644
index 00000000..d0975155
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/veloce.config
@@ -0,0 +1,26 @@
+
+
+
+
+
+# pragma uvmf custom additional begin
+comp -num_boards 1
+comp -hvl questa
+# Please choose the correct emulator type code for
+# comp -platform command or else velcomp will fail
+# Available types are:
+# - Veloce2 Quattro: D2
+# - Veloce2 Maximus: D2M
+# - Veloce Strato TiL, Ti, and Mi: Strato
+# - Veloce Strato M and Strato T: StratoM
+# - comp -platform
+comp -platform Strato
+
+rtlc -enable_tbx_pragma_checks
+rtlc -allow_4ST
+rtlc -allow_MDR
+rtlc -compile_display
+rtlc -xwave_siglist xwaves.sigs
+# pragma uvmf custom additional end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/viswave.do
new file mode 100644
index 00000000..e6989769
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/viswave.do
@@ -0,0 +1,22 @@
+
+
+onerror resume
+wave tags F0
+wave update off
+
+wave spacer -backgroundcolor Salmon { spi_master }
+wave add uvm_test_top.environment.spi_master.spi_master_monitor.txn_stream -radix string -tag F0
+wave group spi_master_bus
+wave add -group spi_master_bus hdl_top.spi_master_bus.* -radix hexadecimal -tag F0
+wave group spi_master_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { wb_slave }
+wave add uvm_test_top.environment.wb_slave.wb_slave_monitor.txn_stream -radix string -tag F0
+wave group wb_slave_bus
+wave add -group wb_slave_bus hdl_top.wb_slave_bus.* -radix hexadecimal -tag F0
+wave group wb_slave_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+
+wave update on
+WaveSetStreamView
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/wave.do
new file mode 100644
index 00000000..128637c8
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/wave.do
@@ -0,0 +1,30 @@
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+add wave -noupdate -divider spi_master
+add wave -noupdate /uvm_root/uvm_test_top/environment/spi_master/spi_master_monitor/txn_stream
+add wave -noupdate -group spi_master_bus /hdl_top/spi_master_bus/*
+add wave -noupdate -divider wb_slave
+add wave -noupdate /uvm_root/uvm_test_top/environment/wb_slave/wb_slave_monitor/txn_stream
+add wave -noupdate -group wb_slave_bus /hdl_top/wb_slave_bus/*
+
+TreeUpdate [SetDefaultTree]
+quietly wave cursor active 0
+configure wave -namecolwidth 472
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {27 ns} {168 ns}
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/xwaves.sigs
new file mode 100644
index 00000000..d75f0a57
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/sim/xwaves.sigs
@@ -0,0 +1,17 @@
+
+
+
+
+
+# pragma uvmf custom additional begin
+
+Group All
+
+#Top level signals
+hdl_top.*
+#Add additional levels or individual signals as needed
+hdl_top.*.*
+
+# pragma uvmf custom additional end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile
new file mode 100644
index 00000000..1d5f4608
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile
@@ -0,0 +1,4 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+src:
+ - block_2_parameters_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv
new file mode 100644
index 00000000..67f61b95
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv
@@ -0,0 +1,38 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package contains test level parameters
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+
+package block_2_parameters_pkg;
+
+ import uvmf_base_pkg_hdl::*;
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+
+ // These parameters are used to uniquely identify each interface. The monitor_bfm and
+ // driver_bfm are placed into and retrieved from the uvm_config_db using these string
+ // names as the field_name. The parameter is also used to enable transaction viewing
+ // from the command line for selected interfaces using the UVM command line processing.
+ parameter string spi_master_BFM = "spi_master_BFM"; /* [0] */
+ parameter string wb_slave_BFM = "wb_slave_BFM"; /* [1] */
+
+ // pragma uvmf custom package_item_additional begin
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo
new file mode 100644
index 00000000..7d0528cc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo
@@ -0,0 +1,2 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+block_2_parameters_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile
new file mode 100644
index 00000000..60acb579
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile
@@ -0,0 +1,8 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile
+ - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile
+ - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile
+ - ../../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile
+ - ../parameters/block_2_parameters_pkg.compile
+src:
+ - block_2_sequences_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv
new file mode 100644
index 00000000..3948b622
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv
@@ -0,0 +1,51 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package includes all high level sequence classes used
+// in the environment. These include utility sequences and top
+// level sequences.
+//
+// CONTAINS:
+// -
+// -
+//
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+
+package block_2_sequences_pkg;
+ import uvm_pkg::*;
+ import uvmf_base_pkg::*;
+ import spi_m_pkg::*;
+ import spi_m_pkg_hdl::*;
+ import wb_s_pkg::*;
+ import wb_s_pkg_hdl::*;
+ import block_2_parameters_pkg::*;
+ import block_2_env_pkg::*;
+ `include "uvm_macros.svh"
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+ `include "src/block_2_bench_sequence_base.svh"
+ `include "src/register_test_sequence.svh"
+ `include "src/example_derived_test_sequence.svh"
+
+ // pragma uvmf custom package_item_additional begin
+ // UVMF_CHANGE_ME : When adding new sequences to the src directory
+ // be sure to add the sequence file here so that it will be
+ // compiled as part of the sequence package. Be sure to place
+ // the new sequence after any base sequences of the new sequence.
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo
new file mode 100644
index 00000000..9d82a0e6
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo
@@ -0,0 +1,7 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo
++incdir+@vinfodir
+block_2_sequences_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh
new file mode 100644
index 00000000..37bc195f
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh
@@ -0,0 +1,128 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// Description: This file contains the top level and utility sequences
+// used by test_top. It can be extended to create derivative top
+// level sequences.
+//
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+
+
+typedef block_2_env_configuration block_2_env_configuration_t;
+
+class block_2_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item);
+
+ `uvm_object_utils( block_2_bench_sequence_base );
+
+ // pragma uvmf custom sequences begin
+
+typedef block_2_env_sequence_base #(
+ .CONFIG_T(block_2_env_configuration_t)
+ )
+ block_2_env_sequence_base_t;
+rand block_2_env_sequence_base_t block_2_env_seq;
+
+
+
+ // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios.
+ // Instantiate sequences here
+ typedef spi_m_random_sequence spi_master_random_seq_t;
+ spi_master_random_seq_t spi_master_random_seq;
+ typedef wb_s_responder_sequence wb_slave_responder_seq_t;
+ wb_slave_responder_seq_t wb_slave_responder_seq;
+ // pragma uvmf custom sequences end
+
+ // Sequencer handles for each active interface in the environment
+ typedef spi_m_transaction spi_master_transaction_t;
+ uvm_sequencer #(spi_master_transaction_t) spi_master_sequencer;
+ typedef wb_s_transaction wb_slave_transaction_t;
+ uvm_sequencer #(wb_slave_transaction_t) wb_slave_sequencer;
+
+
+ // Top level environment configuration handle
+ block_2_env_configuration_t top_configuration;
+
+ // Configuration handles to access interface BFM's
+ spi_m_configuration spi_master_config;
+ wb_s_configuration wb_slave_config;
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ // ****************************************************************************
+ function new( string name = "" );
+ super.new( name );
+ // Retrieve the configuration handles from the uvm_config_db
+
+ // Retrieve top level configuration handle
+ if ( !uvm_config_db#(block_2_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin
+ `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE);
+ `uvm_fatal("CFG", "uvm_config_db#(block_2_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG");
+ end
+
+ // Retrieve config handles for all agents
+ if( !uvm_config_db #( spi_m_configuration )::get( null , UVMF_CONFIGURATIONS , spi_master_BFM , spi_master_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( spi_m_configuration )::get cannot find resource spi_master_BFM" )
+ if( !uvm_config_db #( wb_s_configuration )::get( null , UVMF_CONFIGURATIONS , wb_slave_BFM , wb_slave_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( wb_s_configuration )::get cannot find resource wb_slave_BFM" )
+
+ // Assign the sequencer handles from the handles within agent configurations
+ spi_master_sequencer = spi_master_config.get_sequencer();
+ wb_slave_sequencer = wb_slave_config.get_sequencer();
+
+
+
+ // pragma uvmf custom new begin
+ // pragma uvmf custom new end
+
+ endfunction
+
+ // ****************************************************************************
+ virtual task body();
+ // pragma uvmf custom body begin
+
+ // Construct sequences here
+
+ block_2_env_seq = block_2_env_sequence_base_t::type_id::create("block_2_env_seq");
+
+ spi_master_random_seq = spi_master_random_seq_t::type_id::create("spi_master_random_seq");
+ wb_slave_responder_seq = wb_slave_responder_seq_t::type_id::create("wb_slave_responder_seq");
+ fork
+ spi_master_config.wait_for_reset();
+ wb_slave_config.wait_for_reset();
+ join
+ // Start RESPONDER sequences here
+ fork
+ wb_slave_responder_seq.start(wb_slave_sequencer);
+ join_none
+ // Start INITIATOR sequences here
+ fork
+ repeat (25) spi_master_random_seq.start(spi_master_sequencer);
+ join
+
+block_2_env_seq.start(top_configuration.vsqr);
+
+ // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after
+ // the last sequence to allow for the last sequence item to flow
+ // through the design.
+ fork
+ spi_master_config.wait_for_num_clocks(400);
+ wb_slave_config.wait_for_num_clocks(400);
+ join
+
+ // pragma uvmf custom body end
+ endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh
new file mode 100644
index 00000000..8bd3e555
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh
@@ -0,0 +1,30 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This file contains the top level sequence used in example_derived_test.
+// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base
+// and can override %(benchName)_bench_sequence_base.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class example_derived_test_sequence extends block_2_bench_sequence_base;
+
+ `uvm_object_utils( example_derived_test_sequence );
+
+ function new(string name = "" );
+ super.new(name);
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/src/register_test_sequence.svh
new file mode 100644
index 00000000..6948b861
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/sequences/src/register_test_sequence.svh
@@ -0,0 +1,57 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This file contains the top level sequence used in register_test.
+// It uses the UVM built in register test. Specific UVM built-in tests can be
+// selected in the body task.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class register_test_sequence extends block_2_bench_sequence_base;
+
+ `uvm_object_utils( register_test_sequence );
+
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ function new(string name = "" );
+ super.new(name);
+ endfunction
+
+ // ****************************************************************************
+ virtual task body();
+
+ // Reset the DUT
+ fork
+ // pragma uvmf custom register_test_reset begin
+ // UVMF_CHANGE_ME
+ // Select the desired wait_for_reset or provide custom mechanism.
+ // fork-join for this code block may be unnecessary based on your situation.
+ spi_master_config.wait_for_reset();
+ wb_slave_config.wait_for_reset();
+ // pragma uvmf custom register_test_reset end
+ join
+
+ // pragma uvmf custom register_test_setup begin
+ // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence.
+ // pragma uvmf custom register_test_setup end
+
+ // pragma uvmf custom register_test_operation begin
+ // UVMF_CHANGE_ME Perform your custom register test
+ // pragma uvmf custom register_test_operation end
+
+ endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hdl_top.compile
new file mode 100644
index 00000000..96a0acc9
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hdl_top.compile
@@ -0,0 +1,10 @@
+incdir:
+ - ${uvm_path}/src
+ - .
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+ - ../parameters/block_2_parameters_pkg.compile
+ - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile
+ - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile
+src:
+ - hdl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hdl_top.sv
new file mode 100644
index 00000000..5617245e
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hdl_top.sv
@@ -0,0 +1,101 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// Description: This top level module instantiates all synthesizable
+// static content. This and tb_top.sv are the two top level modules
+// of the simulation.
+//
+// This module instantiates the following:
+// DUT: The Design Under Test
+// Interfaces: Signal bundles that contain signals connected to DUT
+// Driver BFM's: BFM's that actively drive interface signals
+// Monitor BFM's: BFM's that passively monitor interface signals
+//
+//----------------------------------------------------------------------
+
+//----------------------------------------------------------------------
+//
+
+module hdl_top;
+
+import block_2_parameters_pkg::*;
+import uvmf_base_pkg_hdl::*;
+
+ // pragma attribute hdl_top partition_module_xrtl
+// pragma uvmf custom clock_generator begin
+ bit clk;
+ // Instantiate a clk driver
+ // tbx clkgen
+ initial begin
+ clk = 0;
+ #9ns;
+ forever begin
+ clk = ~clk;
+ #5ns;
+ end
+ end
+// pragma uvmf custom clock_generator end
+
+// pragma uvmf custom reset_generator begin
+ bit rst;
+ // Instantiate a rst driver
+ // tbx clkgen
+ initial begin
+ rst = 1;
+ #200ns;
+ rst = 0;
+ end
+// pragma uvmf custom reset_generator end
+
+ // pragma uvmf custom module_item_additional begin
+ // pragma uvmf custom module_item_additional end
+
+ // Instantiate the signal bundle, monitor bfm and driver bfm for each interface.
+ // The signal bundle, _if, contains signals to be connected to the DUT.
+ // The monitor, monitor_bfm, observes the bus, _if, and captures transactions.
+ // The driver, driver_bfm, drives transactions onto the bus, _if.
+ spi_m_if spi_master_bus(
+ // pragma uvmf custom spi_master_bus_connections begin
+ .sck(clk), .rst(rst)
+ // pragma uvmf custom spi_master_bus_connections end
+ );
+ wb_s_if wb_slave_bus(
+ // pragma uvmf custom wb_slave_bus_connections begin
+ .clock(clk), .reset(rst)
+ // pragma uvmf custom wb_slave_bus_connections end
+ );
+ spi_m_monitor_bfm spi_master_mon_bfm(spi_master_bus.monitor_port);
+ wb_s_monitor_bfm wb_slave_mon_bfm(wb_slave_bus.monitor_port);
+ spi_m_driver_bfm spi_master_drv_bfm(spi_master_bus.initiator_port);
+ wb_s_driver_bfm wb_slave_drv_bfm(wb_slave_bus.responder_port);
+
+ // pragma uvmf custom dut_instantiation begin
+ // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above
+ // Instantiate your DUT here
+ // These DUT's instantiated to show verilog and vhdl instantiation
+ verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal));
+ vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal));
+ // pragma uvmf custom dut_instantiation end
+
+ initial begin // tbx vif_binding_block
+ import uvm_pkg::uvm_config_db;
+ // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db.
+ // They are placed into the uvm_config_db using the string names defined in the parameters package.
+ // The string names are passed to the agent configurations by test_top through the top level configuration.
+ // They are retrieved by the agents configuration class for use by the agent.
+ uvm_config_db #( virtual spi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_master_BFM , spi_master_mon_bfm );
+ uvm_config_db #( virtual wb_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_slave_BFM , wb_slave_mon_bfm );
+ uvm_config_db #( virtual spi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_master_BFM , spi_master_drv_bfm );
+ uvm_config_db #( virtual wb_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_slave_BFM , wb_slave_drv_bfm );
+ end
+
+endmodule
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hdl_top.vinfo
new file mode 100644
index 00000000..dce0a508
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hdl_top.vinfo
@@ -0,0 +1,6 @@
+@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_bfm.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_bfm.vinfo
+hdl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hvl_top.compile
new file mode 100644
index 00000000..381340b2
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hvl_top.compile
@@ -0,0 +1,7 @@
+incdir:
+ - ${uvm_path}/src
+ - .
+needs:
+ - ../tests/block_2_tests_pkg.compile
+src:
+ - hvl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hvl_top.sv
new file mode 100644
index 00000000..1cd56838
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hvl_top.sv
@@ -0,0 +1,33 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This module loads the test package and starts the UVM phases.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+module hvl_top;
+
+import uvm_pkg::*;
+import block_2_tests_pkg::*;
+
+ // pragma uvmf custom module_item_additional begin
+ // pragma uvmf custom module_item_additional end
+
+ initial begin
+ $timeformat(-9,3,"ns",5);
+ run_test();
+ end
+
+endmodule
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hvl_top.vinfo
new file mode 100644
index 00000000..fd98547a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/hvl_top.vinfo
@@ -0,0 +1,2 @@
+@use $UVMF_PROJECT_DIR/tb/tests/block_2_tests_pkg.vinfo
+hvl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/top_filelist_hdl.f
new file mode 100644
index 00000000..1e9dab65
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/top_filelist_hdl.f
@@ -0,0 +1,3 @@
+$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/top_filelist_hvl.f
new file mode 100644
index 00000000..42383ab2
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/testbench/top_filelist_hvl.f
@@ -0,0 +1,3 @@
+$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/block_2_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/block_2_tests_pkg.compile
new file mode 100644
index 00000000..fcd92c08
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/block_2_tests_pkg.compile
@@ -0,0 +1,9 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile
+ - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile
+ - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile
+ - ../../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile
+ - ../parameters/block_2_parameters_pkg.compile
+ - ../sequences/block_2_sequences_pkg.compile
+src:
+ - block_2_tests_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/block_2_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/block_2_tests_pkg.sv
new file mode 100644
index 00000000..cc8e3ddb
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/block_2_tests_pkg.sv
@@ -0,0 +1,54 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package contains all tests currently written for
+// the simulation project. Once compiled, any test can be selected
+// from the vsim command line using +UVM_TESTNAME=yourTestNameHere
+//
+// CONTAINS:
+// -
+// -
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+package block_2_tests_pkg;
+
+ import uvm_pkg::*;
+ import uvmf_base_pkg::*;
+ import block_2_parameters_pkg::*;
+ import block_2_env_pkg::*;
+ import block_2_sequences_pkg::*;
+ import spi_m_pkg::*;
+ import spi_m_pkg_hdl::*;
+ import wb_s_pkg::*;
+ import wb_s_pkg_hdl::*;
+
+
+ `include "uvm_macros.svh"
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+ `include "src/test_top.svh"
+ `include "src/register_test.svh"
+ `include "src/example_derived_test.svh"
+
+ // pragma uvmf custom package_item_additional begin
+ // UVMF_CHANGE_ME : When adding new tests to the src directory
+ // be sure to add the test file here so that it will be
+ // compiled as part of the test package. Be sure to place
+ // the new test after any base tests of the new test.
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo
new file mode 100644
index 00000000..9992ff94
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo
@@ -0,0 +1,8 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/sequences/block_2_sequences_pkg.vinfo
++incdir+@vinfodir
+block_2_tests_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/src/example_derived_test.svh
new file mode 100644
index 00000000..24753c75
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/src/example_derived_test.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+// changes to test_top using the UVM factory type_override:
+//
+// Test scenario:
+// This is a template test that can be used to create future tests.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class example_derived_test extends test_top;
+
+ `uvm_component_utils( example_derived_test );
+
+ function new( string name = "", uvm_component parent = null );
+ super.new( name, parent );
+ endfunction
+
+ virtual function void build_phase(uvm_phase phase);
+ // The factory override below is an example of how to replace the block_2_bench_sequence_base
+ // sequence with the example_derived_test_sequence.
+ block_2_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type());
+ // Execute the build_phase of test_top AFTER all factory overrides have been created.
+ super.build_phase(phase);
+ // pragma uvmf custom configuration_settings_post_randomize begin
+ // UVMF_CHANGE_ME Test specific configuration values can be set here.
+ // The configuration structure has already been randomized.
+ // pragma uvmf custom configuration_settings_post_randomize end
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/src/register_test.svh
new file mode 100644
index 00000000..2340b0f7
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/src/register_test.svh
@@ -0,0 +1,40 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+// changes to test_top using the UVM factory type_override:
+//
+// Test scenario:
+// This is a template test that can be used to create future tests.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class register_test extends test_top;
+
+ `uvm_component_utils( register_test );
+
+ function new( string name = "", uvm_component parent = null );
+ super.new( name, parent );
+ endfunction
+
+ virtual function void build_phase(uvm_phase phase);
+ // The factory override below replaces the block_2_bench_sequence_base
+ // sequence with the register_test_sequence.
+ block_2_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type());
+ // Execute the build_phase of test_top AFTER all factory overrides have been created.
+ super.build_phase(phase);
+ endfunction
+
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/src/test_top.svh
new file mode 100644
index 00000000..8159d43e
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/tb/tests/src/test_top.svh
@@ -0,0 +1,78 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+// Description: This top level UVM test is the base class for all
+// future tests created for this project.
+//
+// This test class contains:
+// Configuration: The top level configuration for the project.
+// Environment: The top level environment for the project.
+// Top_level_sequence: The top level sequence for the project.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+typedef block_2_env_configuration block_2_env_configuration_t;
+typedef block_2_environment block_2_environment_t;
+
+class test_top extends uvmf_test_base #(.CONFIG_T(block_2_env_configuration_t),
+ .ENV_T(block_2_environment_t),
+ .TOP_LEVEL_SEQ_T(block_2_bench_sequence_base));
+
+ `uvm_component_utils( test_top );
+
+
+
+ string interface_names[] = {
+ spi_master_BFM /* spi_master [0] */ ,
+ wb_slave_BFM /* wb_slave [1] */
+};
+
+uvmf_active_passive_t interface_activities[] = {
+ ACTIVE /* spi_master [0] */ ,
+ ACTIVE /* wb_slave [1] */ };
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ // ****************************************************************************
+ // FUNCTION: new()
+ // This is the standard systemVerilog constructor. All components are
+ // constructed in the build_phase to allow factory overriding.
+ //
+ function new( string name = "", uvm_component parent = null );
+ super.new( name ,parent );
+ endfunction
+
+
+
+ // ****************************************************************************
+ // FUNCTION: build_phase()
+ // The construction of the configuration and environment classes is done in
+ // the build_phase of uvmf_test_base. Once the configuraton and environment
+ // classes are built then the initialize call is made to perform the
+ // following:
+ // Monitor and driver BFM virtual interface handle passing into agents
+ // Set the active/passive state for each agent
+ // Once this build_phase completes, the build_phase of the environment is
+ // executed which builds the agents.
+ //
+ virtual function void build_phase(uvm_phase phase);
+// pragma uvmf custom build_phase_pre_super begin
+// pragma uvmf custom build_phase_pre_super end
+ super.build_phase(phase);
+ // pragma uvmf custom configuration_settings_post_randomize begin
+ // pragma uvmf custom configuration_settings_post_randomize end
+ configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities);
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/yaml/block_2_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/yaml/block_2_bench.yaml
new file mode 100644
index 00000000..ba4bef1c
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_2/yaml/block_2_bench.yaml
@@ -0,0 +1,17 @@
+uvmf:
+ benches:
+ block_2:
+ active_passive:
+ - bfm_name: spi_master
+ value: ACTIVE
+ - bfm_name: wb_slave
+ value: ACTIVE
+ active_passive_default: ACTIVE
+ clock_half_period: 5ns
+ clock_phase_offset: 9ns
+ existing_library_component: 'True'
+ interface_params: []
+ reset_assertion_level: 'True'
+ reset_duration: 200ns
+ top_env: block_2
+ use_dpi_link: 'False'
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/.project b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/.project
new file mode 100644
index 00000000..ba9cab02
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/.project
@@ -0,0 +1,37 @@
+
+
+ block_3
+
+
+
+
+
+ org.python.pydev.PyDevBuilder
+
+
+
+
+ net.sf.sveditor.core.SVProjectBuilder
+
+
+
+
+
+ net.sf.sveditor.core.SVNature
+ org.python.pydev.pythonNature
+
+
+
+ verification_ip
+ 2
+ UVMF_VIP_LIBRARY_HOME
+
+
+
+
+ UVMF_VIP_LIBRARY_HOME
+ $%7BPARENT-2-PROJECT_LOC%7D/verification_ip
+
+
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/.svproject
new file mode 100644
index 00000000..e998cea7
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/.svproject
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/block_3_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/block_3_sve.F
new file mode 100644
index 00000000..0c6abe1a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/block_3_sve.F
@@ -0,0 +1,28 @@
+
+// UVM
++incdir+${UVM_HOME}/src
+${UVM_HOME}/src/uvm_pkg.sv
+
+// Common UVMF files
+-f ${UVMF_HOME}/common/common_sve.f
+
+// BFM Files
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_m_pkg/wb_m_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_pkg_sve.F
+
+// Environment Files
+-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F
+
+// Bench Files
++incdir+./tb/tests
+./tb/tests/block_3_tests_pkg.sv
+
++incdir+./tb/sequences
+./tb/sequences/block_3_sequences_pkg.sv
+
++incdir+./tb/parameters
+./tb/parameters/block_3_parameters_pkg.sv
+
+./tb/testbench/hdl_top.sv
+./tb/testbench/hvl_top.sv
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/docs/interfaces.csv
new file mode 100644
index 00000000..82c2e9d0
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/docs/interfaces.csv
@@ -0,0 +1,14 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+,
+Interface Description, Interface Type, Interface Transaction, Interface Name,
+wb_master, wb_m_driver_bfm wb_m_monitor_bfm, wb_m_transaction, wb_m_pkg_wb_master_BFM,
+axi_slave, axi_s_driver_bfm axi_s_monitor_bfm, axi_s_transaction, axi_s_pkg_axi_slave_BFM,
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/dut.compile
new file mode 100644
index 00000000..9b0008fc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/dut.compile
@@ -0,0 +1,6 @@
+
+# pragma uvmf custom dut_compile_info begin
+src:
+ - ./vhdl/vhdl_dut.vhd
+ - ./verilog/verilog_dut.v
+# pragma uvmf custom dut_compile_info end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/verilog/verilog_dut.v
new file mode 100644
index 00000000..96198441
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/verilog/verilog_dut.v
@@ -0,0 +1,21 @@
+module verilog_dut(clk, rst, in_signal, out_signal);
+
+input clk;
+input rst;
+input in_signal;
+output out_signal;
+
+reg out_signal_o;
+
+always @(posedge clk) begin
+ if (rst) begin
+ out_signal_o <= 0;
+ end
+ else begin
+ out_signal_o <= ~in_signal;
+ end
+ end
+
+assign out_signal = out_signal_o;
+
+endmodule
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/verilog/verilog_dut.vinfo
new file mode 100644
index 00000000..87e95f36
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/verilog/verilog_dut.vinfo
@@ -0,0 +1 @@
+verilog_dut.v
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/vhdl/vhdl_dut.vhd
new file mode 100644
index 00000000..904aa37d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/rtl/vhdl/vhdl_dut.vhd
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity vhdl_dut is
+ port ( clk : in std_logic ;
+ rst : in std_logic ;
+ in_signal : in std_logic ;
+ out_signal :out std_logic
+ );
+end vhdl_dut;
+
+architecture rtl of vhdl_dut is
+ begin
+ P1: process
+ variable out_signal_o : std_logic;
+ begin
+ wait until clk'event and clk = '1';
+ out_signal_o := in_signal;
+ out_signal <= out_signal_o;
+ end process;
+ end rtl;
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/Makefile
new file mode 100644
index 00000000..3866116c
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/Makefile
@@ -0,0 +1,199 @@
+
+#
+#----------------------------------------------------------------------
+#
+# DESCRIPTION: This makefile includes the shared makefile and contains
+# bench level make targets.
+#
+#----------------------------------------------------------------------
+
+
+# pragma uvmf custom additional begin
+# pragma uvmf custom additional end
+
+# *********************************************************************************************
+# UVMF library directory:
+# This variable points to the UVMF release where uvmf_base_pkg directory resides.
+# This variable points to release code that is not user modified.
+# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories.
+# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples.
+UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___
+
+# pragma uvmf custom exports begin
+#
+# Project(s) specific verification IP library:
+# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside.
+# This variable allows for your verification IP to reside independent of project bench and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip
+export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip
+#
+# Project specific bench:
+# Directory where bench specific code is located.
+# This variable allows for project_benches to reside independent of verification IP and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/
+export UVMF_PROJECT_DIR ?= $(PWD)/..
+#
+#
+# pragma uvmf custom exports end
+# *********************************************************************************************
+
+## Check PATH for required vinfo scripts
+PVAL := $(shell command -v make_filelist.py 2> /dev/null)
+ifndef PVAL
+ MFLIST = $(UVMF_HOME)/scripts/make_filelist.py
+else
+ MFLIST = make_filelist.py
+endif
+
+
+# Set test case specific Variables
+TEST_NAME ?= test_top
+
+TEST_SEED ?= random
+UVM_CLI_ARGS =
+
+# Usage of Veloce, etc. to be input by the user (subject to defaults)
+USE_VELOCE ?= 0
+
+# Usage of vinfo flow for generating file list
+USE_VINFO ?= 0
+
+# Usage of Veloce and Questa profilers
+USE_VELOCE_PROFILER ?= 0
+USE_QUESTA_PROFILER ?= 0
+
+
+# Set project Variables
+TEST_PLAN_NAME = block_3_TestPlan
+REPORTING_DO_FILE = block_3_reports_script
+
+
+# Include makefile that includes targets for UVM_VIP_Library packages
+include $(UVMF_HOME)/scripts/Makefile
+
+
+
+
+# Include all requisite interface package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/Makefile
+
+# Include all requisite environment package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/Makefile
+
+
+
+# Add to default compile/load/run arguments
+VCOM_ARGS +=
+
+# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS
+
+VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD)
+
+VELANALYZE_ARGS +=
+VELANALYZE_HVL_ARGS +=
+
+BATCH_VOPT_ARGS +=
+DEBUG_VOPT_ARGS +=
+EXTRA_VOPT_TOPS +=
+COMMON_VSIM_ARGS +=
+COMMON_VSIM_ARGS +=
+
+
+BATCH_VSIM_ARGS += #-uvmcontrol=none
+DEBUG_VSIM_ARGS +=
+EXTRA_VSIM_TOPS +=
+
+# pragma uvmf custom additional_args begin
+# pragma uvmf custom additional_args end
+
+
+# Project bench package source
+block_3_PARAMETERS_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/parameters/block_3_parameters_pkg.sv
+
+
+block_3_SEQUENCES_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/sequences/block_3_sequences_pkg.sv
+
+
+block_3_TEST_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/tests/block_3_tests_pkg.sv
+
+# pragma uvmf custom dut_files begin
+# UVMF_CHANGE_ME : Reference Verilog DUT source.
+block_3_VERILOG_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v
+
+# UVMF_CHANGE_ME : Reference VHDL DUT source.
+block_3_VHDL_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd
+# pragma uvmf custom dut_files end
+
+
+# Project bench package targets
+COMP_block_3_PARAMETERS_PKG_TGT_0 = q_comp_block_3_parameters_pkg
+COMP_block_3_PARAMETERS_PKG_TGT_1 = v_comp_block_3_parameters_pkg
+COMP_block_3_PARAMETERS_PKG_TGT = $(COMP_block_3_PARAMETERS_PKG_TGT_$(USE_VELOCE))
+
+comp_block_3_parameters_pkg: $(COMP_block_3_PARAMETERS_PKG_TGT)
+
+q_comp_block_3_parameters_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_3_PARAMETERS_PKG)
+
+v_comp_block_3_parameters_pkg: q_comp_block_3_parameters_pkg
+ $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_3_PARAMETERS_PKG)
+
+
+comp_block_3_sequence_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_3_SEQUENCES_PKG)
+
+comp_block_3_tests_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_3_TEST_PKG)
+
+# pragma uvmf custom dut_compile_make_target begin
+# UVMF_CHANGE_ME : Add make target to compile your verilog dut here
+comp_block_3_verilog_dut:
+ echo "Compile your verilog DUT here"
+ $(HDL_COMP_CMD) $(block_3_VERILOG_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here
+comp_block_3_vhdl_dut:
+ echo "Compile your vhdl DUT here"
+ $(HDL_COMP_CMD_VHDL) $(block_3_VHDL_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your dut here
+comp_block_3_dut: comp_block_3_vhdl_dut comp_block_3_verilog_dut
+# pragma uvmf custom dut_compile_make_target end
+
+
+BUILD_TGT_0 = make_build
+BUILD_TGT_1 = vinfo_build
+BUILD_TGT = $(BUILD_TGT_$(USE_VINFO))
+
+
+comp_hvl : comp_hvl_core
+
+
+comp_hvl_core : \
+ comp_wb_m_pkg comp_axi_s_pkg \
+ comp_block_3_env_pkg \
+ comp_block_3_parameters_pkg comp_block_3_sequence_pkg comp_block_3_tests_pkg
+
+comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg
+
+make_build: comp_block_3_dut comp_uvmf_core comp_hvl comp_test_bench
+
+hvl_build: q_comp_wb_m_pkg q_comp_axi_s_pkg comp_block_3_env_pkg comp_block_3_sequence_pkg comp_block_3_tests_pkg hvl_comp_testbench link optimize
+
+
+vinfo_build: comp_block_3_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT)
+
+ $(HDL_COMP_CMD) -F hdl.vf
+ $(VEL_COMP)
+
+build: $(BUILD_TGT)
+
+# pragma uvmf custom additional_targets begin
+# pragma uvmf custom additional_targets end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/bcr_testlist
new file mode 100644
index 00000000..482f01fc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/bcr_testlist
@@ -0,0 +1,19 @@
+
+
+
+# Test list for use by RMDB file
+# File syntax is
+# TB_INFO { } { }
+# TB ## All subsequent tests will run on this bench until a different "TB" line is seen
+# TEST <1st_seed> ...
+# If not enough seeds are provided then random seeds are used to pad
+# If no repeat count is given, default is 1
+# pragma uvmf custom tb_info begin
+TB_INFO block_3 { } { }
+# pragma uvmf custom tb_info end
+TB block_3
+# pragma uvmf custom regression_suite begin
+TEST test_top 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/bcr_testlist.yaml
new file mode 100644
index 00000000..ac85d606
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/bcr_testlist.yaml
@@ -0,0 +1,44 @@
+
+
+
+# YAML test list for use by RMDB file
+# File syntax is
+# uvmf_testlist:
+# testbenches:
+# - name:
+# extra_build_options:
+# extra_run_options:
+# - name:
+# ...
+# - name:
+# tests:
+# - name:
+# uvm_testname: (defaults to test_name)
+# testbench: (defaults to last tb name seen)
+# repeat: (defaults to 1)
+# seeds: [,,...,] (defaults to all random)
+# extra_test_options:
+# - name:
+# ...
+# - name:
+# include:
+# - (relative path reference is to the including YAML file)
+# -
+# ...
+# -
+
+uvmf_testlist:
+ testbenches:
+# pragma uvmf custom tb_info begin
+ - name: block_3
+ extra_build_options: ""
+ extra_run_options: ""
+# pragma uvmf custom tb_info end
+ tests:
+ - testbench: block_3
+# pragma uvmf custom regression_suite begin
+ - name: test_top
+ repeat: 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/compile.do
new file mode 100644
index 00000000..dba7d6f1
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/compile.do
@@ -0,0 +1,71 @@
+
+
+##################################################################
+## ENVIRONMENT VARIABLES
+##################################################################
+quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip
+quietly set ::env(UVMF_PROJECT_DIR) ..
+
+## Using VRM means that the build is occuring several more directories deeper underneath
+## the sim directory, need to prepend some more '..'
+if {[info exists ::env(VRM_BUILD)]} {
+ quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)"
+ quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)"
+}
+quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)]
+quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)]
+quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)"
+quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)"
+
+
+###################################################################
+## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED
+###################################################################
+file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA
+file delete -force design.bin qwave.db dpiheader.h visualizer*.ses
+file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini
+file delete -force sv_connect.*
+
+###################################################################
+## COMPILE DUT SOURCE CODE
+###################################################################
+vlib work
+# pragma uvmf custom dut_compile_dofile_target begin
+# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples
+vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v
+vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd
+# pragma uvmf custom dut_compile_dofile_target end
+
+###################################################################
+## COMPILE UVMF BASE/COMMON SOURCE CODE
+###################################################################
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f
+
+
+###################################################################
+## UVMF INTERFACE COMPILATION
+###################################################################
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/compile.do
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/compile.do
+
+###################################################################
+## UVMF ENVIRONMENT COMPILATION
+###################################################################
+do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/compile.do
+
+###################################################################
+## UVMF BENCHES COMPILATION
+###################################################################
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_3_parameters_pkg.sv
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_3_sequences_pkg.sv
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_3_tests_pkg.sv
+
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f
+
+###################################################################
+## OPTIMIZATION
+###################################################################
+vopt hvl_top hdl_top -o optimized_batch_top_tb
+vopt +acc hvl_top hdl_top -o optimized_debug_top_tb
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hdl.compile
new file mode 100644
index 00000000..8e7bd41a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hdl.compile
@@ -0,0 +1,5 @@
+needs:
+# pragma uvmf custom dut_compile_info begin
+ - ../rtl/dut.compile
+# pragma uvmf custom dut_compile_info end
+ - ../tb/testbench/hdl_top.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hdl.vinfo
new file mode 100644
index 00000000..da27ec77
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hdl.vinfo
@@ -0,0 +1 @@
+@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hvl.compile
new file mode 100644
index 00000000..ce952549
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hvl.compile
@@ -0,0 +1,2 @@
+needs:
+ - ../tb/testbench/hvl_top.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hvl.vinfo
new file mode 100644
index 00000000..d22eff33
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/hvl.vinfo
@@ -0,0 +1 @@
+@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/run.do
new file mode 100644
index 00000000..101ddc48
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/run.do
@@ -0,0 +1,21 @@
+
+
+quietly set svLibs ""
+quietly set extra_vsim_args ""
+
+###################################################################
+## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS
+###################################################################
+if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} {
+ echo "Adding more args to vsim command"
+ quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS)
+}
+
+##################################################################
+## Launch Questa : generate vsim command line and execute
+##################################################################
+# pragma uvmf custom dut_run_dofile_target begin
+# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test
+quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args]
+# pragma uvmf custom dut_run_dofile_target end
+eval $cmd
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/tbx.config
new file mode 100644
index 00000000..eec58168
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/tbx.config
@@ -0,0 +1,10 @@
+
+
+
+
+
+comp -questa
+velsyn -D1S
+rtlc -allow_4ST
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/testlist
new file mode 100644
index 00000000..c770870e
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/testlist
@@ -0,0 +1,20 @@
+
+
+
+
+# Test list for use by RMDB file
+# File syntax is
+# TB_INFO { } { }
+# TB ## All subsequent tests will run on this bench until a different "TB" line is seen
+# TEST <1st_seed> ...
+# If not enough seeds are provided then random seeds are used to pad
+# If no repeat count is given, default is 1
+# pragma uvmf custom tb_info begin
+TB_INFO block_3 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_3 } { }
+# pragma uvmf custom tb_info end
+TB block_3
+# pragma uvmf custom regression_suite begin
+TEST test_top 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/testlist.yaml
new file mode 100644
index 00000000..2eb1c8dc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/testlist.yaml
@@ -0,0 +1,44 @@
+
+
+
+# YAML test list for use by RMDB file
+# File syntax is
+# uvmf_testlist:
+# testbenches:
+# - name:
+# extra_build_options:
+# extra_run_options:
+# - name:
+# ...
+# - name:
+# tests:
+# - name:
+# uvm_testname: (defaults to test_name)
+# testbench: (defaults to last tb name seen)
+# repeat: (defaults to 1)
+# seeds: [,,...,] (defaults to all random)
+# extra_test_options:
+# - name:
+# ...
+# - name:
+# include:
+# - (relative path reference is to the including YAML file)
+# -
+# ...
+# -
+
+uvmf_testlist:
+ testbenches:
+# pragma uvmf custom tb_info begin
+ - name: block_3
+ extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_3"
+ extra_run_options: ""
+# pragma uvmf custom tb_info end
+ tests:
+ - testbench: block_3
+# pragma uvmf custom regression_suite begin
+ - name: test_top
+ repeat: 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/top.compile
new file mode 100644
index 00000000..efd51c07
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/top.compile
@@ -0,0 +1,3 @@
+needs:
+ - hvl.compile
+ - hdl.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/veloce.config
new file mode 100644
index 00000000..d0975155
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/veloce.config
@@ -0,0 +1,26 @@
+
+
+
+
+
+# pragma uvmf custom additional begin
+comp -num_boards 1
+comp -hvl questa
+# Please choose the correct emulator type code for
+# comp -platform command or else velcomp will fail
+# Available types are:
+# - Veloce2 Quattro: D2
+# - Veloce2 Maximus: D2M
+# - Veloce Strato TiL, Ti, and Mi: Strato
+# - Veloce Strato M and Strato T: StratoM
+# - comp -platform
+comp -platform Strato
+
+rtlc -enable_tbx_pragma_checks
+rtlc -allow_4ST
+rtlc -allow_MDR
+rtlc -compile_display
+rtlc -xwave_siglist xwaves.sigs
+# pragma uvmf custom additional end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/viswave.do
new file mode 100644
index 00000000..6b69c9ea
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/viswave.do
@@ -0,0 +1,22 @@
+
+
+onerror resume
+wave tags F0
+wave update off
+
+wave spacer -backgroundcolor Salmon { wb_master }
+wave add uvm_test_top.environment.wb_master.wb_master_monitor.txn_stream -radix string -tag F0
+wave group wb_master_bus
+wave add -group wb_master_bus hdl_top.wb_master_bus.* -radix hexadecimal -tag F0
+wave group wb_master_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { axi_slave }
+wave add uvm_test_top.environment.axi_slave.axi_slave_monitor.txn_stream -radix string -tag F0
+wave group axi_slave_bus
+wave add -group axi_slave_bus hdl_top.axi_slave_bus.* -radix hexadecimal -tag F0
+wave group axi_slave_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+
+wave update on
+WaveSetStreamView
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/wave.do
new file mode 100644
index 00000000..ad8536c6
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/wave.do
@@ -0,0 +1,30 @@
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+add wave -noupdate -divider wb_master
+add wave -noupdate /uvm_root/uvm_test_top/environment/wb_master/wb_master_monitor/txn_stream
+add wave -noupdate -group wb_master_bus /hdl_top/wb_master_bus/*
+add wave -noupdate -divider axi_slave
+add wave -noupdate /uvm_root/uvm_test_top/environment/axi_slave/axi_slave_monitor/txn_stream
+add wave -noupdate -group axi_slave_bus /hdl_top/axi_slave_bus/*
+
+TreeUpdate [SetDefaultTree]
+quietly wave cursor active 0
+configure wave -namecolwidth 472
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {27 ns} {168 ns}
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/xwaves.sigs
new file mode 100644
index 00000000..d75f0a57
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/sim/xwaves.sigs
@@ -0,0 +1,17 @@
+
+
+
+
+
+# pragma uvmf custom additional begin
+
+Group All
+
+#Top level signals
+hdl_top.*
+#Add additional levels or individual signals as needed
+hdl_top.*.*
+
+# pragma uvmf custom additional end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/parameters/block_3_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/parameters/block_3_parameters_pkg.compile
new file mode 100644
index 00000000..5315773a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/parameters/block_3_parameters_pkg.compile
@@ -0,0 +1,4 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+src:
+ - block_3_parameters_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/parameters/block_3_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/parameters/block_3_parameters_pkg.sv
new file mode 100644
index 00000000..d23d05b6
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/parameters/block_3_parameters_pkg.sv
@@ -0,0 +1,38 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package contains test level parameters
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+
+package block_3_parameters_pkg;
+
+ import uvmf_base_pkg_hdl::*;
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+
+ // These parameters are used to uniquely identify each interface. The monitor_bfm and
+ // driver_bfm are placed into and retrieved from the uvm_config_db using these string
+ // names as the field_name. The parameter is also used to enable transaction viewing
+ // from the command line for selected interfaces using the UVM command line processing.
+ parameter string wb_master_BFM = "wb_master_BFM"; /* [0] */
+ parameter string axi_slave_BFM = "axi_slave_BFM"; /* [1] */
+
+ // pragma uvmf custom package_item_additional begin
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/parameters/block_3_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/parameters/block_3_parameters_pkg.vinfo
new file mode 100644
index 00000000..2e4b56d0
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/parameters/block_3_parameters_pkg.vinfo
@@ -0,0 +1,2 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+block_3_parameters_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/block_3_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/block_3_sequences_pkg.compile
new file mode 100644
index 00000000..bb608184
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/block_3_sequences_pkg.compile
@@ -0,0 +1,8 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile
+ - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m.compile
+ - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s.compile
+ - ../../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile
+ - ../parameters/block_3_parameters_pkg.compile
+src:
+ - block_3_sequences_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/block_3_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/block_3_sequences_pkg.sv
new file mode 100644
index 00000000..ae20b8a7
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/block_3_sequences_pkg.sv
@@ -0,0 +1,51 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package includes all high level sequence classes used
+// in the environment. These include utility sequences and top
+// level sequences.
+//
+// CONTAINS:
+// -
+// -
+//
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+
+package block_3_sequences_pkg;
+ import uvm_pkg::*;
+ import uvmf_base_pkg::*;
+ import wb_m_pkg::*;
+ import wb_m_pkg_hdl::*;
+ import axi_s_pkg::*;
+ import axi_s_pkg_hdl::*;
+ import block_3_parameters_pkg::*;
+ import block_3_env_pkg::*;
+ `include "uvm_macros.svh"
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+ `include "src/block_3_bench_sequence_base.svh"
+ `include "src/register_test_sequence.svh"
+ `include "src/example_derived_test_sequence.svh"
+
+ // pragma uvmf custom package_item_additional begin
+ // UVMF_CHANGE_ME : When adding new sequences to the src directory
+ // be sure to add the sequence file here so that it will be
+ // compiled as part of the sequence package. Be sure to place
+ // the new sequence after any base sequences of the new sequence.
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/block_3_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/block_3_sequences_pkg.vinfo
new file mode 100644
index 00000000..1e7146b0
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/block_3_sequences_pkg.vinfo
@@ -0,0 +1,7 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/block_3_parameters_pkg.vinfo
++incdir+@vinfodir
+block_3_sequences_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/src/block_3_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/src/block_3_bench_sequence_base.svh
new file mode 100644
index 00000000..5a70a701
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/src/block_3_bench_sequence_base.svh
@@ -0,0 +1,128 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// Description: This file contains the top level and utility sequences
+// used by test_top. It can be extended to create derivative top
+// level sequences.
+//
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+
+
+typedef block_3_env_configuration block_3_env_configuration_t;
+
+class block_3_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item);
+
+ `uvm_object_utils( block_3_bench_sequence_base );
+
+ // pragma uvmf custom sequences begin
+
+typedef block_3_env_sequence_base #(
+ .CONFIG_T(block_3_env_configuration_t)
+ )
+ block_3_env_sequence_base_t;
+rand block_3_env_sequence_base_t block_3_env_seq;
+
+
+
+ // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios.
+ // Instantiate sequences here
+ typedef wb_m_random_sequence wb_master_random_seq_t;
+ wb_master_random_seq_t wb_master_random_seq;
+ typedef axi_s_responder_sequence axi_slave_responder_seq_t;
+ axi_slave_responder_seq_t axi_slave_responder_seq;
+ // pragma uvmf custom sequences end
+
+ // Sequencer handles for each active interface in the environment
+ typedef wb_m_transaction wb_master_transaction_t;
+ uvm_sequencer #(wb_master_transaction_t) wb_master_sequencer;
+ typedef axi_s_transaction axi_slave_transaction_t;
+ uvm_sequencer #(axi_slave_transaction_t) axi_slave_sequencer;
+
+
+ // Top level environment configuration handle
+ block_3_env_configuration_t top_configuration;
+
+ // Configuration handles to access interface BFM's
+ wb_m_configuration wb_master_config;
+ axi_s_configuration axi_slave_config;
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ // ****************************************************************************
+ function new( string name = "" );
+ super.new( name );
+ // Retrieve the configuration handles from the uvm_config_db
+
+ // Retrieve top level configuration handle
+ if ( !uvm_config_db#(block_3_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin
+ `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE);
+ `uvm_fatal("CFG", "uvm_config_db#(block_3_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG");
+ end
+
+ // Retrieve config handles for all agents
+ if( !uvm_config_db #( wb_m_configuration )::get( null , UVMF_CONFIGURATIONS , wb_master_BFM , wb_master_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( wb_m_configuration )::get cannot find resource wb_master_BFM" )
+ if( !uvm_config_db #( axi_s_configuration )::get( null , UVMF_CONFIGURATIONS , axi_slave_BFM , axi_slave_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( axi_s_configuration )::get cannot find resource axi_slave_BFM" )
+
+ // Assign the sequencer handles from the handles within agent configurations
+ wb_master_sequencer = wb_master_config.get_sequencer();
+ axi_slave_sequencer = axi_slave_config.get_sequencer();
+
+
+
+ // pragma uvmf custom new begin
+ // pragma uvmf custom new end
+
+ endfunction
+
+ // ****************************************************************************
+ virtual task body();
+ // pragma uvmf custom body begin
+
+ // Construct sequences here
+
+ block_3_env_seq = block_3_env_sequence_base_t::type_id::create("block_3_env_seq");
+
+ wb_master_random_seq = wb_master_random_seq_t::type_id::create("wb_master_random_seq");
+ axi_slave_responder_seq = axi_slave_responder_seq_t::type_id::create("axi_slave_responder_seq");
+ fork
+ wb_master_config.wait_for_reset();
+ axi_slave_config.wait_for_reset();
+ join
+ // Start RESPONDER sequences here
+ fork
+ axi_slave_responder_seq.start(axi_slave_sequencer);
+ join_none
+ // Start INITIATOR sequences here
+ fork
+ repeat (25) wb_master_random_seq.start(wb_master_sequencer);
+ join
+
+block_3_env_seq.start(top_configuration.vsqr);
+
+ // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after
+ // the last sequence to allow for the last sequence item to flow
+ // through the design.
+ fork
+ wb_master_config.wait_for_num_clocks(400);
+ axi_slave_config.wait_for_num_clocks(400);
+ join
+
+ // pragma uvmf custom body end
+ endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/src/example_derived_test_sequence.svh
new file mode 100644
index 00000000..a97eb77b
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/src/example_derived_test_sequence.svh
@@ -0,0 +1,30 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This file contains the top level sequence used in example_derived_test.
+// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base
+// and can override %(benchName)_bench_sequence_base.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class example_derived_test_sequence extends block_3_bench_sequence_base;
+
+ `uvm_object_utils( example_derived_test_sequence );
+
+ function new(string name = "" );
+ super.new(name);
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/src/register_test_sequence.svh
new file mode 100644
index 00000000..81a4e867
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/sequences/src/register_test_sequence.svh
@@ -0,0 +1,57 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This file contains the top level sequence used in register_test.
+// It uses the UVM built in register test. Specific UVM built-in tests can be
+// selected in the body task.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class register_test_sequence extends block_3_bench_sequence_base;
+
+ `uvm_object_utils( register_test_sequence );
+
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ function new(string name = "" );
+ super.new(name);
+ endfunction
+
+ // ****************************************************************************
+ virtual task body();
+
+ // Reset the DUT
+ fork
+ // pragma uvmf custom register_test_reset begin
+ // UVMF_CHANGE_ME
+ // Select the desired wait_for_reset or provide custom mechanism.
+ // fork-join for this code block may be unnecessary based on your situation.
+ wb_master_config.wait_for_reset();
+ axi_slave_config.wait_for_reset();
+ // pragma uvmf custom register_test_reset end
+ join
+
+ // pragma uvmf custom register_test_setup begin
+ // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence.
+ // pragma uvmf custom register_test_setup end
+
+ // pragma uvmf custom register_test_operation begin
+ // UVMF_CHANGE_ME Perform your custom register test
+ // pragma uvmf custom register_test_operation end
+
+ endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hdl_top.compile
new file mode 100644
index 00000000..e5040eb0
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hdl_top.compile
@@ -0,0 +1,10 @@
+incdir:
+ - ${uvm_path}/src
+ - .
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+ - ../parameters/block_3_parameters_pkg.compile
+ - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile
+ - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile
+src:
+ - hdl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hdl_top.sv
new file mode 100644
index 00000000..1f2599cb
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hdl_top.sv
@@ -0,0 +1,101 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// Description: This top level module instantiates all synthesizable
+// static content. This and tb_top.sv are the two top level modules
+// of the simulation.
+//
+// This module instantiates the following:
+// DUT: The Design Under Test
+// Interfaces: Signal bundles that contain signals connected to DUT
+// Driver BFM's: BFM's that actively drive interface signals
+// Monitor BFM's: BFM's that passively monitor interface signals
+//
+//----------------------------------------------------------------------
+
+//----------------------------------------------------------------------
+//
+
+module hdl_top;
+
+import block_3_parameters_pkg::*;
+import uvmf_base_pkg_hdl::*;
+
+ // pragma attribute hdl_top partition_module_xrtl
+// pragma uvmf custom clock_generator begin
+ bit clk;
+ // Instantiate a clk driver
+ // tbx clkgen
+ initial begin
+ clk = 0;
+ #9ns;
+ forever begin
+ clk = ~clk;
+ #5ns;
+ end
+ end
+// pragma uvmf custom clock_generator end
+
+// pragma uvmf custom reset_generator begin
+ bit rst;
+ // Instantiate a rst driver
+ // tbx clkgen
+ initial begin
+ rst = 1;
+ #200ns;
+ rst = 0;
+ end
+// pragma uvmf custom reset_generator end
+
+ // pragma uvmf custom module_item_additional begin
+ // pragma uvmf custom module_item_additional end
+
+ // Instantiate the signal bundle, monitor bfm and driver bfm for each interface.
+ // The signal bundle, _if, contains signals to be connected to the DUT.
+ // The monitor, monitor_bfm, observes the bus, _if, and captures transactions.
+ // The driver, driver_bfm, drives transactions onto the bus, _if.
+ wb_m_if wb_master_bus(
+ // pragma uvmf custom wb_master_bus_connections begin
+ .clock(clk), .reset(rst)
+ // pragma uvmf custom wb_master_bus_connections end
+ );
+ axi_s_if axi_slave_bus(
+ // pragma uvmf custom axi_slave_bus_connections begin
+ .axi_clk(clk), .rst(rst)
+ // pragma uvmf custom axi_slave_bus_connections end
+ );
+ wb_m_monitor_bfm wb_master_mon_bfm(wb_master_bus.monitor_port);
+ axi_s_monitor_bfm axi_slave_mon_bfm(axi_slave_bus.monitor_port);
+ wb_m_driver_bfm wb_master_drv_bfm(wb_master_bus.initiator_port);
+ axi_s_driver_bfm axi_slave_drv_bfm(axi_slave_bus.responder_port);
+
+ // pragma uvmf custom dut_instantiation begin
+ // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above
+ // Instantiate your DUT here
+ // These DUT's instantiated to show verilog and vhdl instantiation
+ verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal));
+ vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal));
+ // pragma uvmf custom dut_instantiation end
+
+ initial begin // tbx vif_binding_block
+ import uvm_pkg::uvm_config_db;
+ // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db.
+ // They are placed into the uvm_config_db using the string names defined in the parameters package.
+ // The string names are passed to the agent configurations by test_top through the top level configuration.
+ // They are retrieved by the agents configuration class for use by the agent.
+ uvm_config_db #( virtual wb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_master_BFM , wb_master_mon_bfm );
+ uvm_config_db #( virtual axi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_slave_BFM , axi_slave_mon_bfm );
+ uvm_config_db #( virtual wb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_master_BFM , wb_master_drv_bfm );
+ uvm_config_db #( virtual axi_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_slave_BFM , axi_slave_drv_bfm );
+ end
+
+endmodule
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hdl_top.vinfo
new file mode 100644
index 00000000..881203b6
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hdl_top.vinfo
@@ -0,0 +1,6 @@
+@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/block_3_parameters_pkg.vinfo
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_bfm.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_bfm.vinfo
+hdl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hvl_top.compile
new file mode 100644
index 00000000..d9bfbc86
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hvl_top.compile
@@ -0,0 +1,7 @@
+incdir:
+ - ${uvm_path}/src
+ - .
+needs:
+ - ../tests/block_3_tests_pkg.compile
+src:
+ - hvl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hvl_top.sv
new file mode 100644
index 00000000..785b6f37
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hvl_top.sv
@@ -0,0 +1,33 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This module loads the test package and starts the UVM phases.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+module hvl_top;
+
+import uvm_pkg::*;
+import block_3_tests_pkg::*;
+
+ // pragma uvmf custom module_item_additional begin
+ // pragma uvmf custom module_item_additional end
+
+ initial begin
+ $timeformat(-9,3,"ns",5);
+ run_test();
+ end
+
+endmodule
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hvl_top.vinfo
new file mode 100644
index 00000000..fe43bc9c
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/hvl_top.vinfo
@@ -0,0 +1,2 @@
+@use $UVMF_PROJECT_DIR/tb/tests/block_3_tests_pkg.vinfo
+hvl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/top_filelist_hdl.f
new file mode 100644
index 00000000..1e9dab65
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/top_filelist_hdl.f
@@ -0,0 +1,3 @@
+$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/top_filelist_hvl.f
new file mode 100644
index 00000000..42383ab2
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/testbench/top_filelist_hvl.f
@@ -0,0 +1,3 @@
+$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/block_3_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/block_3_tests_pkg.compile
new file mode 100644
index 00000000..344eca11
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/block_3_tests_pkg.compile
@@ -0,0 +1,9 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile
+ - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m.compile
+ - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s.compile
+ - ../../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile
+ - ../parameters/block_3_parameters_pkg.compile
+ - ../sequences/block_3_sequences_pkg.compile
+src:
+ - block_3_tests_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/block_3_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/block_3_tests_pkg.sv
new file mode 100644
index 00000000..69d11784
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/block_3_tests_pkg.sv
@@ -0,0 +1,54 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package contains all tests currently written for
+// the simulation project. Once compiled, any test can be selected
+// from the vsim command line using +UVM_TESTNAME=yourTestNameHere
+//
+// CONTAINS:
+// -
+// -
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+package block_3_tests_pkg;
+
+ import uvm_pkg::*;
+ import uvmf_base_pkg::*;
+ import block_3_parameters_pkg::*;
+ import block_3_env_pkg::*;
+ import block_3_sequences_pkg::*;
+ import wb_m_pkg::*;
+ import wb_m_pkg_hdl::*;
+ import axi_s_pkg::*;
+ import axi_s_pkg_hdl::*;
+
+
+ `include "uvm_macros.svh"
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+ `include "src/test_top.svh"
+ `include "src/register_test.svh"
+ `include "src/example_derived_test.svh"
+
+ // pragma uvmf custom package_item_additional begin
+ // UVMF_CHANGE_ME : When adding new tests to the src directory
+ // be sure to add the test file here so that it will be
+ // compiled as part of the test package. Be sure to place
+ // the new test after any base tests of the new test.
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/block_3_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/block_3_tests_pkg.vinfo
new file mode 100644
index 00000000..2fb6da4d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/block_3_tests_pkg.vinfo
@@ -0,0 +1,8 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/block_3_parameters_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/sequences/block_3_sequences_pkg.vinfo
++incdir+@vinfodir
+block_3_tests_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/src/example_derived_test.svh
new file mode 100644
index 00000000..4638fe47
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/src/example_derived_test.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+// changes to test_top using the UVM factory type_override:
+//
+// Test scenario:
+// This is a template test that can be used to create future tests.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class example_derived_test extends test_top;
+
+ `uvm_component_utils( example_derived_test );
+
+ function new( string name = "", uvm_component parent = null );
+ super.new( name, parent );
+ endfunction
+
+ virtual function void build_phase(uvm_phase phase);
+ // The factory override below is an example of how to replace the block_3_bench_sequence_base
+ // sequence with the example_derived_test_sequence.
+ block_3_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type());
+ // Execute the build_phase of test_top AFTER all factory overrides have been created.
+ super.build_phase(phase);
+ // pragma uvmf custom configuration_settings_post_randomize begin
+ // UVMF_CHANGE_ME Test specific configuration values can be set here.
+ // The configuration structure has already been randomized.
+ // pragma uvmf custom configuration_settings_post_randomize end
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/src/register_test.svh
new file mode 100644
index 00000000..984802f0
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/src/register_test.svh
@@ -0,0 +1,40 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+// changes to test_top using the UVM factory type_override:
+//
+// Test scenario:
+// This is a template test that can be used to create future tests.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class register_test extends test_top;
+
+ `uvm_component_utils( register_test );
+
+ function new( string name = "", uvm_component parent = null );
+ super.new( name, parent );
+ endfunction
+
+ virtual function void build_phase(uvm_phase phase);
+ // The factory override below replaces the block_3_bench_sequence_base
+ // sequence with the register_test_sequence.
+ block_3_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type());
+ // Execute the build_phase of test_top AFTER all factory overrides have been created.
+ super.build_phase(phase);
+ endfunction
+
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/src/test_top.svh
new file mode 100644
index 00000000..c62a6fe0
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/tb/tests/src/test_top.svh
@@ -0,0 +1,78 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+// Description: This top level UVM test is the base class for all
+// future tests created for this project.
+//
+// This test class contains:
+// Configuration: The top level configuration for the project.
+// Environment: The top level environment for the project.
+// Top_level_sequence: The top level sequence for the project.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+typedef block_3_env_configuration block_3_env_configuration_t;
+typedef block_3_environment block_3_environment_t;
+
+class test_top extends uvmf_test_base #(.CONFIG_T(block_3_env_configuration_t),
+ .ENV_T(block_3_environment_t),
+ .TOP_LEVEL_SEQ_T(block_3_bench_sequence_base));
+
+ `uvm_component_utils( test_top );
+
+
+
+ string interface_names[] = {
+ wb_master_BFM /* wb_master [0] */ ,
+ axi_slave_BFM /* axi_slave [1] */
+};
+
+uvmf_active_passive_t interface_activities[] = {
+ ACTIVE /* wb_master [0] */ ,
+ ACTIVE /* axi_slave [1] */ };
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ // ****************************************************************************
+ // FUNCTION: new()
+ // This is the standard systemVerilog constructor. All components are
+ // constructed in the build_phase to allow factory overriding.
+ //
+ function new( string name = "", uvm_component parent = null );
+ super.new( name ,parent );
+ endfunction
+
+
+
+ // ****************************************************************************
+ // FUNCTION: build_phase()
+ // The construction of the configuration and environment classes is done in
+ // the build_phase of uvmf_test_base. Once the configuraton and environment
+ // classes are built then the initialize call is made to perform the
+ // following:
+ // Monitor and driver BFM virtual interface handle passing into agents
+ // Set the active/passive state for each agent
+ // Once this build_phase completes, the build_phase of the environment is
+ // executed which builds the agents.
+ //
+ virtual function void build_phase(uvm_phase phase);
+// pragma uvmf custom build_phase_pre_super begin
+// pragma uvmf custom build_phase_pre_super end
+ super.build_phase(phase);
+ // pragma uvmf custom configuration_settings_post_randomize begin
+ // pragma uvmf custom configuration_settings_post_randomize end
+ configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities);
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/yaml/block_3_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/yaml/block_3_bench.yaml
new file mode 100644
index 00000000..385d405c
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/block_3/yaml/block_3_bench.yaml
@@ -0,0 +1,17 @@
+uvmf:
+ benches:
+ block_3:
+ active_passive:
+ - bfm_name: wb_master
+ value: ACTIVE
+ - bfm_name: axi_slave
+ value: ACTIVE
+ active_passive_default: ACTIVE
+ clock_half_period: 5ns
+ clock_phase_offset: 9ns
+ existing_library_component: 'True'
+ interface_params: []
+ reset_assertion_level: 'True'
+ reset_duration: 200ns
+ top_env: block_3
+ use_dpi_link: 'False'
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/.project b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/.project
new file mode 100644
index 00000000..99203eb8
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/.project
@@ -0,0 +1,37 @@
+
+
+ subsys
+
+
+
+
+
+ org.python.pydev.PyDevBuilder
+
+
+
+
+ net.sf.sveditor.core.SVProjectBuilder
+
+
+
+
+
+ net.sf.sveditor.core.SVNature
+ org.python.pydev.pythonNature
+
+
+
+ verification_ip
+ 2
+ UVMF_VIP_LIBRARY_HOME
+
+
+
+
+ UVMF_VIP_LIBRARY_HOME
+ $%7BPARENT-2-PROJECT_LOC%7D/verification_ip
+
+
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/.svproject
new file mode 100644
index 00000000..62740391
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/.svproject
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/docs/interfaces.csv
new file mode 100644
index 00000000..8415ca38
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/docs/interfaces.csv
@@ -0,0 +1,18 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+,
+Interface Description, Interface Type, Interface Transaction, Interface Name,
+b1_apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_b1_apb_master_BFM,
+b1_axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_b1_axi_master1_BFM,
+b1_axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_b1_axi_master2_BFM,
+b1_spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_b1_spi_slave_BFM,
+b2_spi_master, spi_m_driver_bfm spi_m_monitor_bfm, spi_m_transaction, spi_m_pkg_b2_spi_master_BFM,
+b2_wb_slave, wb_s_driver_bfm wb_s_monitor_bfm, wb_s_transaction, wb_s_pkg_b2_wb_slave_BFM,
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/dut.compile
new file mode 100644
index 00000000..9b0008fc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/dut.compile
@@ -0,0 +1,6 @@
+
+# pragma uvmf custom dut_compile_info begin
+src:
+ - ./vhdl/vhdl_dut.vhd
+ - ./verilog/verilog_dut.v
+# pragma uvmf custom dut_compile_info end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/verilog/verilog_dut.v
new file mode 100644
index 00000000..96198441
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/verilog/verilog_dut.v
@@ -0,0 +1,21 @@
+module verilog_dut(clk, rst, in_signal, out_signal);
+
+input clk;
+input rst;
+input in_signal;
+output out_signal;
+
+reg out_signal_o;
+
+always @(posedge clk) begin
+ if (rst) begin
+ out_signal_o <= 0;
+ end
+ else begin
+ out_signal_o <= ~in_signal;
+ end
+ end
+
+assign out_signal = out_signal_o;
+
+endmodule
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/verilog/verilog_dut.vinfo
new file mode 100644
index 00000000..87e95f36
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/verilog/verilog_dut.vinfo
@@ -0,0 +1 @@
+verilog_dut.v
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/vhdl/vhdl_dut.vhd
new file mode 100644
index 00000000..904aa37d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/rtl/vhdl/vhdl_dut.vhd
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity vhdl_dut is
+ port ( clk : in std_logic ;
+ rst : in std_logic ;
+ in_signal : in std_logic ;
+ out_signal :out std_logic
+ );
+end vhdl_dut;
+
+architecture rtl of vhdl_dut is
+ begin
+ P1: process
+ variable out_signal_o : std_logic;
+ begin
+ wait until clk'event and clk = '1';
+ out_signal_o := in_signal;
+ out_signal <= out_signal_o;
+ end process;
+ end rtl;
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/Makefile
new file mode 100644
index 00000000..554483b2
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/Makefile
@@ -0,0 +1,202 @@
+
+#
+#----------------------------------------------------------------------
+#
+# DESCRIPTION: This makefile includes the shared makefile and contains
+# bench level make targets.
+#
+#----------------------------------------------------------------------
+
+
+# pragma uvmf custom additional begin
+# pragma uvmf custom additional end
+
+# *********************************************************************************************
+# UVMF library directory:
+# This variable points to the UVMF release where uvmf_base_pkg directory resides.
+# This variable points to release code that is not user modified.
+# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories.
+# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples.
+UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___
+
+# pragma uvmf custom exports begin
+#
+# Project(s) specific verification IP library:
+# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside.
+# This variable allows for your verification IP to reside independent of project bench and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip
+export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip
+#
+# Project specific bench:
+# Directory where bench specific code is located.
+# This variable allows for project_benches to reside independent of verification IP and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/
+export UVMF_PROJECT_DIR ?= $(PWD)/..
+#
+#
+# pragma uvmf custom exports end
+# *********************************************************************************************
+
+## Check PATH for required vinfo scripts
+PVAL := $(shell command -v make_filelist.py 2> /dev/null)
+ifndef PVAL
+ MFLIST = $(UVMF_HOME)/scripts/make_filelist.py
+else
+ MFLIST = make_filelist.py
+endif
+
+
+# Set test case specific Variables
+TEST_NAME ?= test_top
+
+TEST_SEED ?= random
+UVM_CLI_ARGS =
+
+# Usage of Veloce, etc. to be input by the user (subject to defaults)
+USE_VELOCE ?= 0
+
+# Usage of vinfo flow for generating file list
+USE_VINFO ?= 0
+
+# Usage of Veloce and Questa profilers
+USE_VELOCE_PROFILER ?= 0
+USE_QUESTA_PROFILER ?= 0
+
+
+# Set project Variables
+TEST_PLAN_NAME = subsys_TestPlan
+REPORTING_DO_FILE = subsys_reports_script
+
+
+# Include makefile that includes targets for UVM_VIP_Library packages
+include $(UVMF_HOME)/scripts/Makefile
+
+
+
+
+# Include all requisite interface package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/Makefile
+
+# Include all requisite environment package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/Makefile
+
+
+
+# Add to default compile/load/run arguments
+VCOM_ARGS +=
+
+# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS
+
+VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD)
+
+VELANALYZE_ARGS +=
+VELANALYZE_HVL_ARGS +=
+
+BATCH_VOPT_ARGS +=
+DEBUG_VOPT_ARGS +=
+EXTRA_VOPT_TOPS +=
+COMMON_VSIM_ARGS +=
+COMMON_VSIM_ARGS +=
+
+
+BATCH_VSIM_ARGS += #-uvmcontrol=none
+DEBUG_VSIM_ARGS +=
+EXTRA_VSIM_TOPS +=
+
+# pragma uvmf custom additional_args begin
+# pragma uvmf custom additional_args end
+
+
+# Project bench package source
+subsys_PARAMETERS_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/parameters/subsys_parameters_pkg.sv
+
+
+subsys_SEQUENCES_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/sequences/subsys_sequences_pkg.sv
+
+
+subsys_TEST_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/tests/subsys_tests_pkg.sv
+
+# pragma uvmf custom dut_files begin
+# UVMF_CHANGE_ME : Reference Verilog DUT source.
+subsys_VERILOG_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v
+
+# UVMF_CHANGE_ME : Reference VHDL DUT source.
+subsys_VHDL_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd
+# pragma uvmf custom dut_files end
+
+
+# Project bench package targets
+COMP_subsys_PARAMETERS_PKG_TGT_0 = q_comp_subsys_parameters_pkg
+COMP_subsys_PARAMETERS_PKG_TGT_1 = v_comp_subsys_parameters_pkg
+COMP_subsys_PARAMETERS_PKG_TGT = $(COMP_subsys_PARAMETERS_PKG_TGT_$(USE_VELOCE))
+
+comp_subsys_parameters_pkg: $(COMP_subsys_PARAMETERS_PKG_TGT)
+
+q_comp_subsys_parameters_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(subsys_PARAMETERS_PKG)
+
+v_comp_subsys_parameters_pkg: q_comp_subsys_parameters_pkg
+ $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(subsys_PARAMETERS_PKG)
+
+
+comp_subsys_sequence_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(subsys_SEQUENCES_PKG)
+
+comp_subsys_tests_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(subsys_TEST_PKG)
+
+# pragma uvmf custom dut_compile_make_target begin
+# UVMF_CHANGE_ME : Add make target to compile your verilog dut here
+comp_subsys_verilog_dut:
+ echo "Compile your verilog DUT here"
+ $(HDL_COMP_CMD) $(subsys_VERILOG_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here
+comp_subsys_vhdl_dut:
+ echo "Compile your vhdl DUT here"
+ $(HDL_COMP_CMD_VHDL) $(subsys_VHDL_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your dut here
+comp_subsys_dut: comp_subsys_vhdl_dut comp_subsys_verilog_dut
+# pragma uvmf custom dut_compile_make_target end
+
+
+BUILD_TGT_0 = make_build
+BUILD_TGT_1 = vinfo_build
+BUILD_TGT = $(BUILD_TGT_$(USE_VINFO))
+
+
+comp_hvl : comp_hvl_core
+
+
+comp_hvl_core : \
+ comp_apb_m_pkg comp_axi_m_pkg comp_spi_s_pkg comp_spi_m_pkg comp_wb_s_pkg \
+ comp_subsys_env_pkg \
+ comp_subsys_parameters_pkg comp_subsys_sequence_pkg comp_subsys_tests_pkg
+
+comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg
+
+make_build: comp_subsys_dut comp_uvmf_core comp_hvl comp_test_bench
+
+hvl_build: q_comp_apb_m_pkg q_comp_axi_m_pkg q_comp_spi_s_pkg q_comp_spi_m_pkg q_comp_wb_s_pkg comp_subsys_env_pkg comp_subsys_sequence_pkg comp_subsys_tests_pkg hvl_comp_testbench link optimize
+
+
+vinfo_build: comp_subsys_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT)
+
+ $(HDL_COMP_CMD) -F hdl.vf
+ $(VEL_COMP)
+
+build: $(BUILD_TGT)
+
+# pragma uvmf custom additional_targets begin
+# pragma uvmf custom additional_targets end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/bcr_testlist
new file mode 100644
index 00000000..a4aae156
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/bcr_testlist
@@ -0,0 +1,19 @@
+
+
+
+# Test list for use by RMDB file
+# File syntax is
+# TB_INFO { } { }
+# TB ## All subsequent tests will run on this bench until a different "TB" line is seen
+# TEST <1st_seed> ...
+# If not enough seeds are provided then random seeds are used to pad
+# If no repeat count is given, default is 1
+# pragma uvmf custom tb_info begin
+TB_INFO subsys { } { }
+# pragma uvmf custom tb_info end
+TB subsys
+# pragma uvmf custom regression_suite begin
+TEST test_top 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/bcr_testlist.yaml
new file mode 100644
index 00000000..27abcd04
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/bcr_testlist.yaml
@@ -0,0 +1,44 @@
+
+
+
+# YAML test list for use by RMDB file
+# File syntax is
+# uvmf_testlist:
+# testbenches:
+# - name:
+# extra_build_options:
+# extra_run_options:
+# - name:
+# ...
+# - name:
+# tests:
+# - name:
+# uvm_testname: (defaults to test_name)
+# testbench: (defaults to last tb name seen)
+# repeat: (defaults to 1)
+# seeds: [,,...,] (defaults to all random)
+# extra_test_options:
+# - name:
+# ...
+# - name:
+# include:
+# - (relative path reference is to the including YAML file)
+# -
+# ...
+# -
+
+uvmf_testlist:
+ testbenches:
+# pragma uvmf custom tb_info begin
+ - name: subsys
+ extra_build_options: ""
+ extra_run_options: ""
+# pragma uvmf custom tb_info end
+ tests:
+ - testbench: subsys
+# pragma uvmf custom regression_suite begin
+ - name: test_top
+ repeat: 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/compile.do
new file mode 100644
index 00000000..489d3e86
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/compile.do
@@ -0,0 +1,74 @@
+
+
+##################################################################
+## ENVIRONMENT VARIABLES
+##################################################################
+quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip
+quietly set ::env(UVMF_PROJECT_DIR) ..
+
+## Using VRM means that the build is occuring several more directories deeper underneath
+## the sim directory, need to prepend some more '..'
+if {[info exists ::env(VRM_BUILD)]} {
+ quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)"
+ quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)"
+}
+quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)]
+quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)]
+quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)"
+quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)"
+
+
+###################################################################
+## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED
+###################################################################
+file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA
+file delete -force design.bin qwave.db dpiheader.h visualizer*.ses
+file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini
+file delete -force sv_connect.*
+
+###################################################################
+## COMPILE DUT SOURCE CODE
+###################################################################
+vlib work
+# pragma uvmf custom dut_compile_dofile_target begin
+# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples
+vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v
+vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd
+# pragma uvmf custom dut_compile_dofile_target end
+
+###################################################################
+## COMPILE UVMF BASE/COMMON SOURCE CODE
+###################################################################
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f
+
+
+###################################################################
+## UVMF INTERFACE COMPILATION
+###################################################################
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/compile.do
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/compile.do
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/compile.do
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/compile.do
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/compile.do
+
+###################################################################
+## UVMF ENVIRONMENT COMPILATION
+###################################################################
+do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/compile.do
+
+###################################################################
+## UVMF BENCHES COMPILATION
+###################################################################
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/subsys_parameters_pkg.sv
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/subsys_sequences_pkg.sv
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/subsys_tests_pkg.sv
+
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f
+vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f
+
+###################################################################
+## OPTIMIZATION
+###################################################################
+vopt hvl_top hdl_top -o optimized_batch_top_tb
+vopt +acc hvl_top hdl_top -o optimized_debug_top_tb
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hdl.compile
new file mode 100644
index 00000000..8e7bd41a
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hdl.compile
@@ -0,0 +1,5 @@
+needs:
+# pragma uvmf custom dut_compile_info begin
+ - ../rtl/dut.compile
+# pragma uvmf custom dut_compile_info end
+ - ../tb/testbench/hdl_top.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hdl.vinfo
new file mode 100644
index 00000000..da27ec77
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hdl.vinfo
@@ -0,0 +1 @@
+@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hvl.compile
new file mode 100644
index 00000000..ce952549
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hvl.compile
@@ -0,0 +1,2 @@
+needs:
+ - ../tb/testbench/hvl_top.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hvl.vinfo
new file mode 100644
index 00000000..d22eff33
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/hvl.vinfo
@@ -0,0 +1 @@
+@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/run.do
new file mode 100644
index 00000000..101ddc48
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/run.do
@@ -0,0 +1,21 @@
+
+
+quietly set svLibs ""
+quietly set extra_vsim_args ""
+
+###################################################################
+## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS
+###################################################################
+if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} {
+ echo "Adding more args to vsim command"
+ quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS)
+}
+
+##################################################################
+## Launch Questa : generate vsim command line and execute
+##################################################################
+# pragma uvmf custom dut_run_dofile_target begin
+# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test
+quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args]
+# pragma uvmf custom dut_run_dofile_target end
+eval $cmd
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/tbx.config
new file mode 100644
index 00000000..eec58168
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/tbx.config
@@ -0,0 +1,10 @@
+
+
+
+
+
+comp -questa
+velsyn -D1S
+rtlc -allow_4ST
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/testlist
new file mode 100644
index 00000000..81ee4a56
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/testlist
@@ -0,0 +1,20 @@
+
+
+
+
+# Test list for use by RMDB file
+# File syntax is
+# TB_INFO { } { }
+# TB ## All subsequent tests will run on this bench until a different "TB" line is seen
+# TEST <1st_seed> ...
+# If not enough seeds are provided then random seeds are used to pad
+# If no repeat count is given, default is 1
+# pragma uvmf custom tb_info begin
+TB_INFO subsys { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../subsys } { }
+# pragma uvmf custom tb_info end
+TB subsys
+# pragma uvmf custom regression_suite begin
+TEST test_top 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/testlist.yaml
new file mode 100644
index 00000000..b8b6f60b
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/testlist.yaml
@@ -0,0 +1,44 @@
+
+
+
+# YAML test list for use by RMDB file
+# File syntax is
+# uvmf_testlist:
+# testbenches:
+# - name:
+# extra_build_options:
+# extra_run_options:
+# - name:
+# ...
+# - name:
+# tests:
+# - name:
+# uvm_testname: (defaults to test_name)
+# testbench: (defaults to last tb name seen)
+# repeat: (defaults to 1)
+# seeds: [,,...,] (defaults to all random)
+# extra_test_options:
+# - name:
+# ...
+# - name:
+# include:
+# - (relative path reference is to the including YAML file)
+# -
+# ...
+# -
+
+uvmf_testlist:
+ testbenches:
+# pragma uvmf custom tb_info begin
+ - name: subsys
+ extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../subsys"
+ extra_run_options: ""
+# pragma uvmf custom tb_info end
+ tests:
+ - testbench: subsys
+# pragma uvmf custom regression_suite begin
+ - name: test_top
+ repeat: 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/top.compile
new file mode 100644
index 00000000..efd51c07
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/top.compile
@@ -0,0 +1,3 @@
+needs:
+ - hvl.compile
+ - hdl.compile
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/veloce.config
new file mode 100644
index 00000000..d0975155
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/veloce.config
@@ -0,0 +1,26 @@
+
+
+
+
+
+# pragma uvmf custom additional begin
+comp -num_boards 1
+comp -hvl questa
+# Please choose the correct emulator type code for
+# comp -platform command or else velcomp will fail
+# Available types are:
+# - Veloce2 Quattro: D2
+# - Veloce2 Maximus: D2M
+# - Veloce Strato TiL, Ti, and Mi: Strato
+# - Veloce Strato M and Strato T: StratoM
+# - comp -platform
+comp -platform Strato
+
+rtlc -enable_tbx_pragma_checks
+rtlc -allow_4ST
+rtlc -allow_MDR
+rtlc -compile_display
+rtlc -xwave_siglist xwaves.sigs
+# pragma uvmf custom additional end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/viswave.do
new file mode 100644
index 00000000..18bcb537
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/viswave.do
@@ -0,0 +1,46 @@
+
+
+onerror resume
+wave tags F0
+wave update off
+
+wave spacer -backgroundcolor Salmon { b1_apb_master }
+wave add uvm_test_top.environment.b1.apb_master.apb_master_monitor.txn_stream -radix string -tag F0
+wave group b1_apb_master_bus
+wave add -group b1_apb_master_bus hdl_top.b1_apb_master_bus.* -radix hexadecimal -tag F0
+wave group b1_apb_master_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { b1_axi_master1 }
+wave add uvm_test_top.environment.b1.axi_master1.axi_master1_monitor.txn_stream -radix string -tag F0
+wave group b1_axi_master1_bus
+wave add -group b1_axi_master1_bus hdl_top.b1_axi_master1_bus.* -radix hexadecimal -tag F0
+wave group b1_axi_master1_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { b1_axi_master2 }
+wave add uvm_test_top.environment.b1.axi_master2.axi_master2_monitor.txn_stream -radix string -tag F0
+wave group b1_axi_master2_bus
+wave add -group b1_axi_master2_bus hdl_top.b1_axi_master2_bus.* -radix hexadecimal -tag F0
+wave group b1_axi_master2_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { b1_spi_slave }
+wave add uvm_test_top.environment.b1.spi_slave.spi_slave_monitor.txn_stream -radix string -tag F0
+wave group b1_spi_slave_bus
+wave add -group b1_spi_slave_bus hdl_top.b1_spi_slave_bus.* -radix hexadecimal -tag F0
+wave group b1_spi_slave_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { b2_spi_master }
+wave add uvm_test_top.environment.b2.spi_master.spi_master_monitor.txn_stream -radix string -tag F0
+wave group b2_spi_master_bus
+wave add -group b2_spi_master_bus hdl_top.b2_spi_master_bus.* -radix hexadecimal -tag F0
+wave group b2_spi_master_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { b2_wb_slave }
+wave add uvm_test_top.environment.b2.wb_slave.wb_slave_monitor.txn_stream -radix string -tag F0
+wave group b2_wb_slave_bus
+wave add -group b2_wb_slave_bus hdl_top.b2_wb_slave_bus.* -radix hexadecimal -tag F0
+wave group b2_wb_slave_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
+
+wave update on
+WaveSetStreamView
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/wave.do
new file mode 100644
index 00000000..f76bf238
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/wave.do
@@ -0,0 +1,42 @@
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+add wave -noupdate -divider b1_apb_master
+add wave -noupdate /uvm_root/uvm_test_top/environment.b1/apb_master/apb_master_monitor/txn_stream
+add wave -noupdate -group b1_apb_master_bus /hdl_top/b1_apb_master_bus/*
+add wave -noupdate -divider b1_axi_master1
+add wave -noupdate /uvm_root/uvm_test_top/environment.b1/axi_master1/axi_master1_monitor/txn_stream
+add wave -noupdate -group b1_axi_master1_bus /hdl_top/b1_axi_master1_bus/*
+add wave -noupdate -divider b1_axi_master2
+add wave -noupdate /uvm_root/uvm_test_top/environment.b1/axi_master2/axi_master2_monitor/txn_stream
+add wave -noupdate -group b1_axi_master2_bus /hdl_top/b1_axi_master2_bus/*
+add wave -noupdate -divider b1_spi_slave
+add wave -noupdate /uvm_root/uvm_test_top/environment.b1/spi_slave/spi_slave_monitor/txn_stream
+add wave -noupdate -group b1_spi_slave_bus /hdl_top/b1_spi_slave_bus/*
+add wave -noupdate -divider b2_spi_master
+add wave -noupdate /uvm_root/uvm_test_top/environment.b2/spi_master/spi_master_monitor/txn_stream
+add wave -noupdate -group b2_spi_master_bus /hdl_top/b2_spi_master_bus/*
+add wave -noupdate -divider b2_wb_slave
+add wave -noupdate /uvm_root/uvm_test_top/environment.b2/wb_slave/wb_slave_monitor/txn_stream
+add wave -noupdate -group b2_wb_slave_bus /hdl_top/b2_wb_slave_bus/*
+
+TreeUpdate [SetDefaultTree]
+quietly wave cursor active 0
+configure wave -namecolwidth 472
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {27 ns} {168 ns}
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/xwaves.sigs
new file mode 100644
index 00000000..d75f0a57
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/sim/xwaves.sigs
@@ -0,0 +1,17 @@
+
+
+
+
+
+# pragma uvmf custom additional begin
+
+Group All
+
+#Top level signals
+hdl_top.*
+#Add additional levels or individual signals as needed
+hdl_top.*.*
+
+# pragma uvmf custom additional end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/subsys_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/subsys_sve.F
new file mode 100644
index 00000000..69b29dbd
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/subsys_sve.F
@@ -0,0 +1,31 @@
+
+// UVM
++incdir+${UVM_HOME}/src
+${UVM_HOME}/src/uvm_pkg.sv
+
+// Common UVMF files
+-f ${UVMF_HOME}/common/common_sve.f
+
+// BFM Files
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_pkg_sve.F
+
+// Environment Files
+-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F
+
+// Bench Files
++incdir+./tb/tests
+./tb/tests/subsys_tests_pkg.sv
+
++incdir+./tb/sequences
+./tb/sequences/subsys_sequences_pkg.sv
+
++incdir+./tb/parameters
+./tb/parameters/subsys_parameters_pkg.sv
+
+./tb/testbench/hdl_top.sv
+./tb/testbench/hvl_top.sv
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/parameters/subsys_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/parameters/subsys_parameters_pkg.compile
new file mode 100644
index 00000000..29e4d5fd
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/parameters/subsys_parameters_pkg.compile
@@ -0,0 +1,4 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+src:
+ - subsys_parameters_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/parameters/subsys_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/parameters/subsys_parameters_pkg.sv
new file mode 100644
index 00000000..447327c9
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/parameters/subsys_parameters_pkg.sv
@@ -0,0 +1,42 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package contains test level parameters
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+
+package subsys_parameters_pkg;
+
+ import uvmf_base_pkg_hdl::*;
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+
+ // These parameters are used to uniquely identify each interface. The monitor_bfm and
+ // driver_bfm are placed into and retrieved from the uvm_config_db using these string
+ // names as the field_name. The parameter is also used to enable transaction viewing
+ // from the command line for selected interfaces using the UVM command line processing.
+ parameter string b1_apb_master_BFM = "b1_apb_master_BFM"; /* [0] */
+ parameter string b1_axi_master1_BFM = "b1_axi_master1_BFM"; /* [1] */
+ parameter string b1_axi_master2_BFM = "b1_axi_master2_BFM"; /* [2] */
+ parameter string b1_spi_slave_BFM = "b1_spi_slave_BFM"; /* [3] */
+ parameter string b2_spi_master_BFM = "b2_spi_master_BFM"; /* [4] */
+ parameter string b2_wb_slave_BFM = "b2_wb_slave_BFM"; /* [5] */
+
+ // pragma uvmf custom package_item_additional begin
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/parameters/subsys_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/parameters/subsys_parameters_pkg.vinfo
new file mode 100644
index 00000000..63c1753f
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/parameters/subsys_parameters_pkg.vinfo
@@ -0,0 +1,2 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+subsys_parameters_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/src/example_derived_test_sequence.svh
new file mode 100644
index 00000000..c690a827
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/src/example_derived_test_sequence.svh
@@ -0,0 +1,30 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This file contains the top level sequence used in example_derived_test.
+// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base
+// and can override %(benchName)_bench_sequence_base.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class example_derived_test_sequence extends subsys_bench_sequence_base;
+
+ `uvm_object_utils( example_derived_test_sequence );
+
+ function new(string name = "" );
+ super.new(name);
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/src/register_test_sequence.svh
new file mode 100644
index 00000000..270c155d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/src/register_test_sequence.svh
@@ -0,0 +1,61 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This file contains the top level sequence used in register_test.
+// It uses the UVM built in register test. Specific UVM built-in tests can be
+// selected in the body task.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class register_test_sequence extends subsys_bench_sequence_base;
+
+ `uvm_object_utils( register_test_sequence );
+
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ function new(string name = "" );
+ super.new(name);
+ endfunction
+
+ // ****************************************************************************
+ virtual task body();
+
+ // Reset the DUT
+ fork
+ // pragma uvmf custom register_test_reset begin
+ // UVMF_CHANGE_ME
+ // Select the desired wait_for_reset or provide custom mechanism.
+ // fork-join for this code block may be unnecessary based on your situation.
+ b1_apb_master_config.wait_for_reset();
+ b1_axi_master1_config.wait_for_reset();
+ b1_axi_master2_config.wait_for_reset();
+ b1_spi_slave_config.wait_for_reset();
+ b2_spi_master_config.wait_for_reset();
+ b2_wb_slave_config.wait_for_reset();
+ // pragma uvmf custom register_test_reset end
+ join
+
+ // pragma uvmf custom register_test_setup begin
+ // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence.
+ // pragma uvmf custom register_test_setup end
+
+ // pragma uvmf custom register_test_operation begin
+ // UVMF_CHANGE_ME Perform your custom register test
+ // pragma uvmf custom register_test_operation end
+
+ endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/src/subsys_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/src/subsys_bench_sequence_base.svh
new file mode 100644
index 00000000..91ff6612
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/src/subsys_bench_sequence_base.svh
@@ -0,0 +1,162 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// Description: This file contains the top level and utility sequences
+// used by test_top. It can be extended to create derivative top
+// level sequences.
+//
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+
+
+typedef subsys_env_configuration subsys_env_configuration_t;
+
+class subsys_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item);
+
+ `uvm_object_utils( subsys_bench_sequence_base );
+
+ // pragma uvmf custom sequences begin
+
+typedef subsys_env_sequence_base #(
+ .CONFIG_T(subsys_env_configuration_t)
+ )
+ subsys_env_sequence_base_t;
+rand subsys_env_sequence_base_t subsys_env_seq;
+
+
+
+ // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios.
+ // Instantiate sequences here
+ typedef apb_m_random_sequence b1_apb_master_random_seq_t;
+ b1_apb_master_random_seq_t b1_apb_master_random_seq;
+ typedef axi_m_random_sequence b1_axi_master1_random_seq_t;
+ b1_axi_master1_random_seq_t b1_axi_master1_random_seq;
+ typedef axi_m_random_sequence b1_axi_master2_random_seq_t;
+ b1_axi_master2_random_seq_t b1_axi_master2_random_seq;
+ typedef wb_s_responder_sequence b2_wb_slave_responder_seq_t;
+ b2_wb_slave_responder_seq_t b2_wb_slave_responder_seq;
+ // pragma uvmf custom sequences end
+
+ // Sequencer handles for each active interface in the environment
+ typedef apb_m_transaction b1_apb_master_transaction_t;
+ uvm_sequencer #(b1_apb_master_transaction_t) b1_apb_master_sequencer;
+ typedef axi_m_transaction b1_axi_master1_transaction_t;
+ uvm_sequencer #(b1_axi_master1_transaction_t) b1_axi_master1_sequencer;
+ typedef axi_m_transaction b1_axi_master2_transaction_t;
+ uvm_sequencer #(b1_axi_master2_transaction_t) b1_axi_master2_sequencer;
+ typedef wb_s_transaction b2_wb_slave_transaction_t;
+ uvm_sequencer #(b2_wb_slave_transaction_t) b2_wb_slave_sequencer;
+
+
+ // Top level environment configuration handle
+ subsys_env_configuration_t top_configuration;
+
+ // Configuration handles to access interface BFM's
+ apb_m_configuration b1_apb_master_config;
+ axi_m_configuration b1_axi_master1_config;
+ axi_m_configuration b1_axi_master2_config;
+ spi_s_configuration b1_spi_slave_config;
+ spi_m_configuration b2_spi_master_config;
+ wb_s_configuration b2_wb_slave_config;
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ // ****************************************************************************
+ function new( string name = "" );
+ super.new( name );
+ // Retrieve the configuration handles from the uvm_config_db
+
+ // Retrieve top level configuration handle
+ if ( !uvm_config_db#(subsys_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin
+ `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE);
+ `uvm_fatal("CFG", "uvm_config_db#(subsys_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG");
+ end
+
+ // Retrieve config handles for all agents
+ if( !uvm_config_db #( apb_m_configuration )::get( null , UVMF_CONFIGURATIONS , b1_apb_master_BFM , b1_apb_master_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( apb_m_configuration )::get cannot find resource b1_apb_master_BFM" )
+ if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , b1_axi_master1_BFM , b1_axi_master1_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource b1_axi_master1_BFM" )
+ if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , b1_axi_master2_BFM , b1_axi_master2_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource b1_axi_master2_BFM" )
+ if( !uvm_config_db #( spi_s_configuration )::get( null , UVMF_CONFIGURATIONS , b1_spi_slave_BFM , b1_spi_slave_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( spi_s_configuration )::get cannot find resource b1_spi_slave_BFM" )
+ if( !uvm_config_db #( spi_m_configuration )::get( null , UVMF_CONFIGURATIONS , b2_spi_master_BFM , b2_spi_master_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( spi_m_configuration )::get cannot find resource b2_spi_master_BFM" )
+ if( !uvm_config_db #( wb_s_configuration )::get( null , UVMF_CONFIGURATIONS , b2_wb_slave_BFM , b2_wb_slave_config ) )
+ `uvm_fatal("CFG" , "uvm_config_db #( wb_s_configuration )::get cannot find resource b2_wb_slave_BFM" )
+
+ // Assign the sequencer handles from the handles within agent configurations
+ b1_apb_master_sequencer = b1_apb_master_config.get_sequencer();
+ b1_axi_master1_sequencer = b1_axi_master1_config.get_sequencer();
+ b1_axi_master2_sequencer = b1_axi_master2_config.get_sequencer();
+ b2_wb_slave_sequencer = b2_wb_slave_config.get_sequencer();
+
+
+
+ // pragma uvmf custom new begin
+ // pragma uvmf custom new end
+
+ endfunction
+
+ // ****************************************************************************
+ virtual task body();
+ // pragma uvmf custom body begin
+
+ // Construct sequences here
+
+ subsys_env_seq = subsys_env_sequence_base_t::type_id::create("subsys_env_seq");
+
+ b1_apb_master_random_seq = b1_apb_master_random_seq_t::type_id::create("b1_apb_master_random_seq");
+ b1_axi_master1_random_seq = b1_axi_master1_random_seq_t::type_id::create("b1_axi_master1_random_seq");
+ b1_axi_master2_random_seq = b1_axi_master2_random_seq_t::type_id::create("b1_axi_master2_random_seq");
+ b2_wb_slave_responder_seq = b2_wb_slave_responder_seq_t::type_id::create("b2_wb_slave_responder_seq");
+ fork
+ b1_apb_master_config.wait_for_reset();
+ b1_axi_master1_config.wait_for_reset();
+ b1_axi_master2_config.wait_for_reset();
+ b1_spi_slave_config.wait_for_reset();
+ b2_spi_master_config.wait_for_reset();
+ b2_wb_slave_config.wait_for_reset();
+ join
+ // Start RESPONDER sequences here
+ fork
+ b2_wb_slave_responder_seq.start(b2_wb_slave_sequencer);
+ join_none
+ // Start INITIATOR sequences here
+ fork
+ repeat (25) b1_apb_master_random_seq.start(b1_apb_master_sequencer);
+ repeat (25) b1_axi_master1_random_seq.start(b1_axi_master1_sequencer);
+ repeat (25) b1_axi_master2_random_seq.start(b1_axi_master2_sequencer);
+ join
+
+subsys_env_seq.start(top_configuration.vsqr);
+
+ // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after
+ // the last sequence to allow for the last sequence item to flow
+ // through the design.
+ fork
+ b1_apb_master_config.wait_for_num_clocks(400);
+ b1_axi_master1_config.wait_for_num_clocks(400);
+ b1_axi_master2_config.wait_for_num_clocks(400);
+ b1_spi_slave_config.wait_for_num_clocks(400);
+ b2_spi_master_config.wait_for_num_clocks(400);
+ b2_wb_slave_config.wait_for_num_clocks(400);
+ join
+
+ // pragma uvmf custom body end
+ endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/subsys_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/subsys_sequences_pkg.compile
new file mode 100644
index 00000000..9e332e90
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/subsys_sequences_pkg.compile
@@ -0,0 +1,11 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile
+ - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile
+ - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile
+ - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile
+ - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile
+ - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile
+ - ../../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile
+ - ../parameters/subsys_parameters_pkg.compile
+src:
+ - subsys_sequences_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/subsys_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/subsys_sequences_pkg.sv
new file mode 100644
index 00000000..2bb1e636
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/subsys_sequences_pkg.sv
@@ -0,0 +1,57 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package includes all high level sequence classes used
+// in the environment. These include utility sequences and top
+// level sequences.
+//
+// CONTAINS:
+// -
+// -
+//
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+
+package subsys_sequences_pkg;
+ import uvm_pkg::*;
+ import uvmf_base_pkg::*;
+ import apb_m_pkg::*;
+ import apb_m_pkg_hdl::*;
+ import axi_m_pkg::*;
+ import axi_m_pkg_hdl::*;
+ import spi_s_pkg::*;
+ import spi_s_pkg_hdl::*;
+ import spi_m_pkg::*;
+ import spi_m_pkg_hdl::*;
+ import wb_s_pkg::*;
+ import wb_s_pkg_hdl::*;
+ import subsys_parameters_pkg::*;
+ import subsys_env_pkg::*;
+ `include "uvm_macros.svh"
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+ `include "src/subsys_bench_sequence_base.svh"
+ `include "src/register_test_sequence.svh"
+ `include "src/example_derived_test_sequence.svh"
+
+ // pragma uvmf custom package_item_additional begin
+ // UVMF_CHANGE_ME : When adding new sequences to the src directory
+ // be sure to add the sequence file here so that it will be
+ // compiled as part of the sequence package. Be sure to place
+ // the new sequence after any base sequences of the new sequence.
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/subsys_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/subsys_sequences_pkg.vinfo
new file mode 100644
index 00000000..019ac065
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/sequences/subsys_sequences_pkg.vinfo
@@ -0,0 +1,10 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/subsys_parameters_pkg.vinfo
++incdir+@vinfodir
+subsys_sequences_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hdl_top.compile
new file mode 100644
index 00000000..15ba4874
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hdl_top.compile
@@ -0,0 +1,13 @@
+incdir:
+ - ${uvm_path}/src
+ - .
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+ - ../parameters/subsys_parameters_pkg.compile
+ - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile
+ - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile
+ - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile
+ - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile
+ - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile
+src:
+ - hdl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hdl_top.sv
new file mode 100644
index 00000000..d00f22ab
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hdl_top.sv
@@ -0,0 +1,133 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// Description: This top level module instantiates all synthesizable
+// static content. This and tb_top.sv are the two top level modules
+// of the simulation.
+//
+// This module instantiates the following:
+// DUT: The Design Under Test
+// Interfaces: Signal bundles that contain signals connected to DUT
+// Driver BFM's: BFM's that actively drive interface signals
+// Monitor BFM's: BFM's that passively monitor interface signals
+//
+//----------------------------------------------------------------------
+
+//----------------------------------------------------------------------
+//
+
+module hdl_top;
+
+import subsys_parameters_pkg::*;
+import uvmf_base_pkg_hdl::*;
+
+ // pragma attribute hdl_top partition_module_xrtl
+// pragma uvmf custom clock_generator begin
+ bit clk;
+ // Instantiate a clk driver
+ // tbx clkgen
+ initial begin
+ clk = 0;
+ #9ns;
+ forever begin
+ clk = ~clk;
+ #5ns;
+ end
+ end
+// pragma uvmf custom clock_generator end
+
+// pragma uvmf custom reset_generator begin
+ bit rst;
+ // Instantiate a rst driver
+ // tbx clkgen
+ initial begin
+ rst = 1;
+ #200ns;
+ rst = 0;
+ end
+// pragma uvmf custom reset_generator end
+
+ // pragma uvmf custom module_item_additional begin
+ // pragma uvmf custom module_item_additional end
+
+ // Instantiate the signal bundle, monitor bfm and driver bfm for each interface.
+ // The signal bundle, _if, contains signals to be connected to the DUT.
+ // The monitor, monitor_bfm, observes the bus, _if, and captures transactions.
+ // The driver, driver_bfm, drives transactions onto the bus, _if.
+ apb_m_if b1_apb_master_bus(
+ // pragma uvmf custom b1_apb_master_bus_connections begin
+ .pclk(clk), .presetn(rst)
+ // pragma uvmf custom b1_apb_master_bus_connections end
+ );
+ axi_m_if b1_axi_master1_bus(
+ // pragma uvmf custom b1_axi_master1_bus_connections begin
+ .axi_clk(clk), .rst(rst)
+ // pragma uvmf custom b1_axi_master1_bus_connections end
+ );
+ axi_m_if b1_axi_master2_bus(
+ // pragma uvmf custom b1_axi_master2_bus_connections begin
+ .axi_clk(clk), .rst(rst)
+ // pragma uvmf custom b1_axi_master2_bus_connections end
+ );
+ spi_s_if b1_spi_slave_bus(
+ // pragma uvmf custom b1_spi_slave_bus_connections begin
+ .sck(clk), .rst(rst)
+ // pragma uvmf custom b1_spi_slave_bus_connections end
+ );
+ spi_m_if b2_spi_master_bus(
+ // pragma uvmf custom b2_spi_master_bus_connections begin
+ .sck(clk), .rst(rst)
+ // pragma uvmf custom b2_spi_master_bus_connections end
+ );
+ wb_s_if b2_wb_slave_bus(
+ // pragma uvmf custom b2_wb_slave_bus_connections begin
+ .clock(clk), .reset(rst)
+ // pragma uvmf custom b2_wb_slave_bus_connections end
+ );
+ apb_m_monitor_bfm b1_apb_master_mon_bfm(b1_apb_master_bus.monitor_port);
+ axi_m_monitor_bfm b1_axi_master1_mon_bfm(b1_axi_master1_bus.monitor_port);
+ axi_m_monitor_bfm b1_axi_master2_mon_bfm(b1_axi_master2_bus.monitor_port);
+ spi_s_monitor_bfm b1_spi_slave_mon_bfm(b1_spi_slave_bus.monitor_port);
+ spi_m_monitor_bfm b2_spi_master_mon_bfm(b2_spi_master_bus.monitor_port);
+ wb_s_monitor_bfm b2_wb_slave_mon_bfm(b2_wb_slave_bus.monitor_port);
+ apb_m_driver_bfm b1_apb_master_drv_bfm(b1_apb_master_bus.initiator_port);
+ axi_m_driver_bfm b1_axi_master1_drv_bfm(b1_axi_master1_bus.initiator_port);
+ axi_m_driver_bfm b1_axi_master2_drv_bfm(b1_axi_master2_bus.initiator_port);
+ wb_s_driver_bfm b2_wb_slave_drv_bfm(b2_wb_slave_bus.responder_port);
+
+ // pragma uvmf custom dut_instantiation begin
+ // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above
+ // Instantiate your DUT here
+ // These DUT's instantiated to show verilog and vhdl instantiation
+ verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal));
+ vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal));
+ // pragma uvmf custom dut_instantiation end
+
+ initial begin // tbx vif_binding_block
+ import uvm_pkg::uvm_config_db;
+ // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db.
+ // They are placed into the uvm_config_db using the string names defined in the parameters package.
+ // The string names are passed to the agent configurations by test_top through the top level configuration.
+ // They are retrieved by the agents configuration class for use by the agent.
+ uvm_config_db #( virtual apb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_apb_master_BFM , b1_apb_master_mon_bfm );
+ uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master1_BFM , b1_axi_master1_mon_bfm );
+ uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master2_BFM , b1_axi_master2_mon_bfm );
+ uvm_config_db #( virtual spi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_spi_slave_BFM , b1_spi_slave_mon_bfm );
+ uvm_config_db #( virtual spi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_spi_master_BFM , b2_spi_master_mon_bfm );
+ uvm_config_db #( virtual wb_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_wb_slave_BFM , b2_wb_slave_mon_bfm );
+ uvm_config_db #( virtual apb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_apb_master_BFM , b1_apb_master_drv_bfm );
+ uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master1_BFM , b1_axi_master1_drv_bfm );
+ uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master2_BFM , b1_axi_master2_drv_bfm );
+ uvm_config_db #( virtual wb_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_wb_slave_BFM , b2_wb_slave_drv_bfm );
+ end
+
+endmodule
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hdl_top.vinfo
new file mode 100644
index 00000000..a1a47b9c
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hdl_top.vinfo
@@ -0,0 +1,9 @@
+@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/subsys_parameters_pkg.vinfo
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_bfm.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_bfm.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_bfm.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_bfm.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_bfm.vinfo
+hdl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hvl_top.compile
new file mode 100644
index 00000000..83c8142f
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hvl_top.compile
@@ -0,0 +1,7 @@
+incdir:
+ - ${uvm_path}/src
+ - .
+needs:
+ - ../tests/subsys_tests_pkg.compile
+src:
+ - hvl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hvl_top.sv
new file mode 100644
index 00000000..ea97abbc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hvl_top.sv
@@ -0,0 +1,33 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This module loads the test package and starts the UVM phases.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+module hvl_top;
+
+import uvm_pkg::*;
+import subsys_tests_pkg::*;
+
+ // pragma uvmf custom module_item_additional begin
+ // pragma uvmf custom module_item_additional end
+
+ initial begin
+ $timeformat(-9,3,"ns",5);
+ run_test();
+ end
+
+endmodule
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hvl_top.vinfo
new file mode 100644
index 00000000..2c837f2c
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/hvl_top.vinfo
@@ -0,0 +1,2 @@
+@use $UVMF_PROJECT_DIR/tb/tests/subsys_tests_pkg.vinfo
+hvl_top.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/top_filelist_hdl.f
new file mode 100644
index 00000000..1e9dab65
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/top_filelist_hdl.f
@@ -0,0 +1,3 @@
+$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/top_filelist_hvl.f
new file mode 100644
index 00000000..42383ab2
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/testbench/top_filelist_hvl.f
@@ -0,0 +1,3 @@
+$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/src/example_derived_test.svh
new file mode 100644
index 00000000..88999ddc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/src/example_derived_test.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+// changes to test_top using the UVM factory type_override:
+//
+// Test scenario:
+// This is a template test that can be used to create future tests.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class example_derived_test extends test_top;
+
+ `uvm_component_utils( example_derived_test );
+
+ function new( string name = "", uvm_component parent = null );
+ super.new( name, parent );
+ endfunction
+
+ virtual function void build_phase(uvm_phase phase);
+ // The factory override below is an example of how to replace the subsys_bench_sequence_base
+ // sequence with the example_derived_test_sequence.
+ subsys_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type());
+ // Execute the build_phase of test_top AFTER all factory overrides have been created.
+ super.build_phase(phase);
+ // pragma uvmf custom configuration_settings_post_randomize begin
+ // UVMF_CHANGE_ME Test specific configuration values can be set here.
+ // The configuration structure has already been randomized.
+ // pragma uvmf custom configuration_settings_post_randomize end
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/src/register_test.svh
new file mode 100644
index 00000000..f5f98e48
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/src/register_test.svh
@@ -0,0 +1,40 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+// changes to test_top using the UVM factory type_override:
+//
+// Test scenario:
+// This is a template test that can be used to create future tests.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class register_test extends test_top;
+
+ `uvm_component_utils( register_test );
+
+ function new( string name = "", uvm_component parent = null );
+ super.new( name, parent );
+ endfunction
+
+ virtual function void build_phase(uvm_phase phase);
+ // The factory override below replaces the subsys_bench_sequence_base
+ // sequence with the register_test_sequence.
+ subsys_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type());
+ // Execute the build_phase of test_top AFTER all factory overrides have been created.
+ super.build_phase(phase);
+ endfunction
+
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/src/test_top.svh
new file mode 100644
index 00000000..5db5c139
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/src/test_top.svh
@@ -0,0 +1,86 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+// Description: This top level UVM test is the base class for all
+// future tests created for this project.
+//
+// This test class contains:
+// Configuration: The top level configuration for the project.
+// Environment: The top level environment for the project.
+// Top_level_sequence: The top level sequence for the project.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+typedef subsys_env_configuration subsys_env_configuration_t;
+typedef subsys_environment subsys_environment_t;
+
+class test_top extends uvmf_test_base #(.CONFIG_T(subsys_env_configuration_t),
+ .ENV_T(subsys_environment_t),
+ .TOP_LEVEL_SEQ_T(subsys_bench_sequence_base));
+
+ `uvm_component_utils( test_top );
+
+
+
+ string interface_names[] = {
+ b1_apb_master_BFM /* b1_apb_master [0] */ ,
+ b1_axi_master1_BFM /* b1_axi_master1 [1] */ ,
+ b1_axi_master2_BFM /* b1_axi_master2 [2] */ ,
+ b1_spi_slave_BFM /* b1_spi_slave [3] */ ,
+ b2_spi_master_BFM /* b2_spi_master [4] */ ,
+ b2_wb_slave_BFM /* b2_wb_slave [5] */
+};
+
+uvmf_active_passive_t interface_activities[] = {
+ ACTIVE /* b1_apb_master [0] */ ,
+ ACTIVE /* b1_axi_master1 [1] */ ,
+ ACTIVE /* b1_axi_master2 [2] */ ,
+ PASSIVE /* b1_spi_slave [3] */ ,
+ PASSIVE /* b2_spi_master [4] */ ,
+ ACTIVE /* b2_wb_slave [5] */ };
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ // ****************************************************************************
+ // FUNCTION: new()
+ // This is the standard systemVerilog constructor. All components are
+ // constructed in the build_phase to allow factory overriding.
+ //
+ function new( string name = "", uvm_component parent = null );
+ super.new( name ,parent );
+ endfunction
+
+
+
+ // ****************************************************************************
+ // FUNCTION: build_phase()
+ // The construction of the configuration and environment classes is done in
+ // the build_phase of uvmf_test_base. Once the configuraton and environment
+ // classes are built then the initialize call is made to perform the
+ // following:
+ // Monitor and driver BFM virtual interface handle passing into agents
+ // Set the active/passive state for each agent
+ // Once this build_phase completes, the build_phase of the environment is
+ // executed which builds the agents.
+ //
+ virtual function void build_phase(uvm_phase phase);
+// pragma uvmf custom build_phase_pre_super begin
+// pragma uvmf custom build_phase_pre_super end
+ super.build_phase(phase);
+ // pragma uvmf custom configuration_settings_post_randomize begin
+ // pragma uvmf custom configuration_settings_post_randomize end
+ configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities);
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/subsys_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/subsys_tests_pkg.compile
new file mode 100644
index 00000000..106be50e
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/subsys_tests_pkg.compile
@@ -0,0 +1,12 @@
+needs:
+ - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile
+ - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile
+ - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile
+ - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile
+ - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile
+ - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile
+ - ../../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile
+ - ../parameters/subsys_parameters_pkg.compile
+ - ../sequences/subsys_sequences_pkg.compile
+src:
+ - subsys_tests_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/subsys_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/subsys_tests_pkg.sv
new file mode 100644
index 00000000..8daddb39
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/subsys_tests_pkg.sv
@@ -0,0 +1,60 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This package contains all tests currently written for
+// the simulation project. Once compiled, any test can be selected
+// from the vsim command line using +UVM_TESTNAME=yourTestNameHere
+//
+// CONTAINS:
+// -
+// -
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+package subsys_tests_pkg;
+
+ import uvm_pkg::*;
+ import uvmf_base_pkg::*;
+ import subsys_parameters_pkg::*;
+ import subsys_env_pkg::*;
+ import subsys_sequences_pkg::*;
+ import apb_m_pkg::*;
+ import apb_m_pkg_hdl::*;
+ import axi_m_pkg::*;
+ import axi_m_pkg_hdl::*;
+ import spi_s_pkg::*;
+ import spi_s_pkg_hdl::*;
+ import spi_m_pkg::*;
+ import spi_m_pkg_hdl::*;
+ import wb_s_pkg::*;
+ import wb_s_pkg_hdl::*;
+
+
+ `include "uvm_macros.svh"
+
+ // pragma uvmf custom package_imports_additional begin
+ // pragma uvmf custom package_imports_additional end
+
+ `include "src/test_top.svh"
+ `include "src/register_test.svh"
+ `include "src/example_derived_test.svh"
+
+ // pragma uvmf custom package_item_additional begin
+ // UVMF_CHANGE_ME : When adding new tests to the src directory
+ // be sure to add the test file here so that it will be
+ // compiled as part of the test package. Be sure to place
+ // the new test after any base tests of the new test.
+ // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/subsys_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/subsys_tests_pkg.vinfo
new file mode 100644
index 00000000..b50c9a39
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/tb/tests/subsys_tests_pkg.vinfo
@@ -0,0 +1,11 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/parameters/subsys_parameters_pkg.vinfo
+@use $UVMF_PROJECT_DIR/tb/sequences/subsys_sequences_pkg.vinfo
++incdir+@vinfodir
+subsys_tests_pkg.sv
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/yaml/subsys_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/yaml/subsys_bench.yaml
new file mode 100644
index 00000000..bea949dd
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/subsys/yaml/subsys_bench.yaml
@@ -0,0 +1,25 @@
+uvmf:
+ benches:
+ subsys:
+ active_passive:
+ - bfm_name: b1_apb_master
+ value: ACTIVE
+ - bfm_name: b1_axi_master1
+ value: ACTIVE
+ - bfm_name: b1_axi_master2
+ value: ACTIVE
+ - bfm_name: b1_spi_slave
+ value: PASSIVE
+ - bfm_name: b2_spi_master
+ value: PASSIVE
+ - bfm_name: b2_wb_slave
+ value: ACTIVE
+ active_passive_default: ACTIVE
+ clock_half_period: 5ns
+ clock_phase_offset: 9ns
+ existing_library_component: 'True'
+ interface_params: []
+ reset_assertion_level: 'True'
+ reset_duration: 200ns
+ top_env: subsys
+ use_dpi_link: 'False'
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/.project b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/.project
new file mode 100644
index 00000000..d9a56710
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/.project
@@ -0,0 +1,37 @@
+
+
+ system
+
+
+
+
+
+ org.python.pydev.PyDevBuilder
+
+
+
+
+ net.sf.sveditor.core.SVProjectBuilder
+
+
+
+
+
+ net.sf.sveditor.core.SVNature
+ org.python.pydev.pythonNature
+
+
+
+ verification_ip
+ 2
+ UVMF_VIP_LIBRARY_HOME
+
+
+
+
+ UVMF_VIP_LIBRARY_HOME
+ $%7BPARENT-2-PROJECT_LOC%7D/verification_ip
+
+
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/.svproject
new file mode 100644
index 00000000..2604503d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/.svproject
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/docs/interfaces.csv
new file mode 100644
index 00000000..6676d63d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/docs/interfaces.csv
@@ -0,0 +1,20 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+,
+Interface Description, Interface Type, Interface Transaction, Interface Name,
+s1_b1_apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_s1_b1_apb_master_BFM,
+s1_b1_axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_s1_b1_axi_master1_BFM,
+s1_b1_axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_s1_b1_axi_master2_BFM,
+s1_b1_spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_s1_b1_spi_slave_BFM,
+s1_b2_spi_master, spi_m_driver_bfm spi_m_monitor_bfm, spi_m_transaction, spi_m_pkg_s1_b2_spi_master_BFM,
+s1_b2_wb_slave, wb_s_driver_bfm wb_s_monitor_bfm, wb_s_transaction, wb_s_pkg_s1_b2_wb_slave_BFM,
+b3_wb_master, wb_m_driver_bfm wb_m_monitor_bfm, wb_m_transaction, wb_m_pkg_b3_wb_master_BFM,
+b3_axi_slave, axi_s_driver_bfm axi_s_monitor_bfm, axi_s_transaction, axi_s_pkg_b3_axi_slave_BFM,
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/dut.compile
new file mode 100644
index 00000000..9b0008fc
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/dut.compile
@@ -0,0 +1,6 @@
+
+# pragma uvmf custom dut_compile_info begin
+src:
+ - ./vhdl/vhdl_dut.vhd
+ - ./verilog/verilog_dut.v
+# pragma uvmf custom dut_compile_info end
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/verilog/verilog_dut.v
new file mode 100644
index 00000000..96198441
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/verilog/verilog_dut.v
@@ -0,0 +1,21 @@
+module verilog_dut(clk, rst, in_signal, out_signal);
+
+input clk;
+input rst;
+input in_signal;
+output out_signal;
+
+reg out_signal_o;
+
+always @(posedge clk) begin
+ if (rst) begin
+ out_signal_o <= 0;
+ end
+ else begin
+ out_signal_o <= ~in_signal;
+ end
+ end
+
+assign out_signal = out_signal_o;
+
+endmodule
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/verilog/verilog_dut.vinfo
new file mode 100644
index 00000000..87e95f36
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/verilog/verilog_dut.vinfo
@@ -0,0 +1 @@
+verilog_dut.v
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/vhdl/vhdl_dut.vhd
new file mode 100644
index 00000000..904aa37d
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/rtl/vhdl/vhdl_dut.vhd
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity vhdl_dut is
+ port ( clk : in std_logic ;
+ rst : in std_logic ;
+ in_signal : in std_logic ;
+ out_signal :out std_logic
+ );
+end vhdl_dut;
+
+architecture rtl of vhdl_dut is
+ begin
+ P1: process
+ variable out_signal_o : std_logic;
+ begin
+ wait until clk'event and clk = '1';
+ out_signal_o := in_signal;
+ out_signal <= out_signal_o;
+ end process;
+ end rtl;
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/sim/Makefile
new file mode 100644
index 00000000..5700c289
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/sim/Makefile
@@ -0,0 +1,204 @@
+
+#
+#----------------------------------------------------------------------
+#
+# DESCRIPTION: This makefile includes the shared makefile and contains
+# bench level make targets.
+#
+#----------------------------------------------------------------------
+
+
+# pragma uvmf custom additional begin
+# pragma uvmf custom additional end
+
+# *********************************************************************************************
+# UVMF library directory:
+# This variable points to the UVMF release where uvmf_base_pkg directory resides.
+# This variable points to release code that is not user modified.
+# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories.
+# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples.
+UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___
+
+# pragma uvmf custom exports begin
+#
+# Project(s) specific verification IP library:
+# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside.
+# This variable allows for your verification IP to reside independent of project bench and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip
+export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip
+#
+# Project specific bench:
+# Directory where bench specific code is located.
+# This variable allows for project_benches to reside independent of verification IP and UVMF release directories.
+# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/
+export UVMF_PROJECT_DIR ?= $(PWD)/..
+#
+#
+# pragma uvmf custom exports end
+# *********************************************************************************************
+
+## Check PATH for required vinfo scripts
+PVAL := $(shell command -v make_filelist.py 2> /dev/null)
+ifndef PVAL
+ MFLIST = $(UVMF_HOME)/scripts/make_filelist.py
+else
+ MFLIST = make_filelist.py
+endif
+
+
+# Set test case specific Variables
+TEST_NAME ?= test_top
+
+TEST_SEED ?= random
+UVM_CLI_ARGS =
+
+# Usage of Veloce, etc. to be input by the user (subject to defaults)
+USE_VELOCE ?= 0
+
+# Usage of vinfo flow for generating file list
+USE_VINFO ?= 0
+
+# Usage of Veloce and Questa profilers
+USE_VELOCE_PROFILER ?= 0
+USE_QUESTA_PROFILER ?= 0
+
+
+# Set project Variables
+TEST_PLAN_NAME = system_TestPlan
+REPORTING_DO_FILE = system_reports_script
+
+
+# Include makefile that includes targets for UVM_VIP_Library packages
+include $(UVMF_HOME)/scripts/Makefile
+
+
+
+
+# Include all requisite interface package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/Makefile
+
+# Include all requisite environment package targets for this bench
+include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/system_env_pkg/Makefile
+
+
+
+# Add to default compile/load/run arguments
+VCOM_ARGS +=
+
+# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS
+
+VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD)
+
+VELANALYZE_ARGS +=
+VELANALYZE_HVL_ARGS +=
+
+BATCH_VOPT_ARGS +=
+DEBUG_VOPT_ARGS +=
+EXTRA_VOPT_TOPS +=
+COMMON_VSIM_ARGS +=
+COMMON_VSIM_ARGS +=
+
+
+BATCH_VSIM_ARGS += #-uvmcontrol=none
+DEBUG_VSIM_ARGS +=
+EXTRA_VSIM_TOPS +=
+
+# pragma uvmf custom additional_args begin
+# pragma uvmf custom additional_args end
+
+
+# Project bench package source
+system_PARAMETERS_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/parameters/system_parameters_pkg.sv
+
+
+system_SEQUENCES_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/sequences/system_sequences_pkg.sv
+
+
+system_TEST_PKG ?=\
+$(UVMF_PROJECT_DIR)/tb/tests/system_tests_pkg.sv
+
+# pragma uvmf custom dut_files begin
+# UVMF_CHANGE_ME : Reference Verilog DUT source.
+system_VERILOG_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v
+
+# UVMF_CHANGE_ME : Reference VHDL DUT source.
+system_VHDL_DUT ?=\
+$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd
+# pragma uvmf custom dut_files end
+
+
+# Project bench package targets
+COMP_system_PARAMETERS_PKG_TGT_0 = q_comp_system_parameters_pkg
+COMP_system_PARAMETERS_PKG_TGT_1 = v_comp_system_parameters_pkg
+COMP_system_PARAMETERS_PKG_TGT = $(COMP_system_PARAMETERS_PKG_TGT_$(USE_VELOCE))
+
+comp_system_parameters_pkg: $(COMP_system_PARAMETERS_PKG_TGT)
+
+q_comp_system_parameters_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(system_PARAMETERS_PKG)
+
+v_comp_system_parameters_pkg: q_comp_system_parameters_pkg
+ $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(system_PARAMETERS_PKG)
+
+
+comp_system_sequence_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(system_SEQUENCES_PKG)
+
+comp_system_tests_pkg:
+ $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(system_TEST_PKG)
+
+# pragma uvmf custom dut_compile_make_target begin
+# UVMF_CHANGE_ME : Add make target to compile your verilog dut here
+comp_system_verilog_dut:
+ echo "Compile your verilog DUT here"
+ $(HDL_COMP_CMD) $(system_VERILOG_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here
+comp_system_vhdl_dut:
+ echo "Compile your vhdl DUT here"
+ $(HDL_COMP_CMD_VHDL) $(system_VHDL_DUT)
+
+# UVMF_CHANGE_ME : Add make target to compile your dut here
+comp_system_dut: comp_system_vhdl_dut comp_system_verilog_dut
+# pragma uvmf custom dut_compile_make_target end
+
+
+BUILD_TGT_0 = make_build
+BUILD_TGT_1 = vinfo_build
+BUILD_TGT = $(BUILD_TGT_$(USE_VINFO))
+
+
+comp_hvl : comp_hvl_core
+
+
+comp_hvl_core : \
+ comp_apb_m_pkg comp_axi_m_pkg comp_spi_s_pkg comp_spi_m_pkg comp_wb_s_pkg comp_wb_m_pkg comp_axi_s_pkg \
+ comp_system_env_pkg \
+ comp_system_parameters_pkg comp_system_sequence_pkg comp_system_tests_pkg
+
+comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg
+
+make_build: comp_system_dut comp_uvmf_core comp_hvl comp_test_bench
+
+hvl_build: q_comp_apb_m_pkg q_comp_axi_m_pkg q_comp_spi_s_pkg q_comp_spi_m_pkg q_comp_wb_s_pkg q_comp_wb_m_pkg q_comp_axi_s_pkg comp_system_env_pkg comp_system_sequence_pkg comp_system_tests_pkg hvl_comp_testbench link optimize
+
+
+vinfo_build: comp_system_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT)
+
+ $(HDL_COMP_CMD) -F hdl.vf
+ $(VEL_COMP)
+
+build: $(BUILD_TGT)
+
+# pragma uvmf custom additional_targets begin
+# pragma uvmf custom additional_targets end
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/sim/bcr_testlist
new file mode 100644
index 00000000..2bb25c0e
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/sim/bcr_testlist
@@ -0,0 +1,19 @@
+
+
+
+# Test list for use by RMDB file
+# File syntax is
+# TB_INFO { } { }
+# TB ## All subsequent tests will run on this bench until a different "TB" line is seen
+# TEST <1st_seed> ...
+# If not enough seeds are provided then random seeds are used to pad
+# If no repeat count is given, default is 1
+# pragma uvmf custom tb_info begin
+TB_INFO system { } { }
+# pragma uvmf custom tb_info end
+TB system
+# pragma uvmf custom regression_suite begin
+TEST test_top 3
+# pragma uvmf custom regression_suite end
+
+
diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/sim/bcr_testlist.yaml
new file mode 100644
index 00000000..4f661bb2
--- /dev/null
+++ b/UVM_Framework/UVMF_2022.3/challenge_3/output_files/project_benches/system/sim/bcr_testlist.yaml
@@ -0,0 +1,44 @@
+
+
+
+# YAML test list for use by RMDB file
+# File syntax is
+# uvmf_testlist:
+# testbenches:
+# - name:
+# extra_build_options:
+# extra_run_options:
+# - name:
+# ...
+# - name:
+# tests:
+# - name:
+# uvm_testname: (defaults to test_name)
+# testbench: (defaults to last tb name seen)
+# repeat: (defaults to 1)
+# seeds: [,,...,